github.com/mattn/go@v0.0.0-20171011075504-07f7db3ea99f/src/cmd/compile/internal/ssa/gen/S390X.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (Add64 x y) -> (ADD x y) 7 (AddPtr x y) -> (ADD x y) 8 (Add32 x y) -> (ADDW x y) 9 (Add16 x y) -> (ADDW x y) 10 (Add8 x y) -> (ADDW x y) 11 (Add32F x y) -> (FADDS x y) 12 (Add64F x y) -> (FADD x y) 13 14 (Sub64 x y) -> (SUB x y) 15 (SubPtr x y) -> (SUB x y) 16 (Sub32 x y) -> (SUBW x y) 17 (Sub16 x y) -> (SUBW x y) 18 (Sub8 x y) -> (SUBW x y) 19 (Sub32F x y) -> (FSUBS x y) 20 (Sub64F x y) -> (FSUB x y) 21 22 (Mul64 x y) -> (MULLD x y) 23 (Mul32 x y) -> (MULLW x y) 24 (Mul16 x y) -> (MULLW x y) 25 (Mul8 x y) -> (MULLW x y) 26 (Mul32F x y) -> (FMULS x y) 27 (Mul64F x y) -> (FMUL x y) 28 29 (Div32F x y) -> (FDIVS x y) 30 (Div64F x y) -> (FDIV x y) 31 32 (Div64 x y) -> (DIVD x y) 33 (Div64u x y) -> (DIVDU x y) 34 // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, 35 // so a sign/zero extension of the dividend is required. 36 (Div32 x y) -> (DIVW (MOVWreg x) y) 37 (Div32u x y) -> (DIVWU (MOVWZreg x) y) 38 (Div16 x y) -> (DIVW (MOVHreg x) (MOVHreg y)) 39 (Div16u x y) -> (DIVWU (MOVHZreg x) (MOVHZreg y)) 40 (Div8 x y) -> (DIVW (MOVBreg x) (MOVBreg y)) 41 (Div8u x y) -> (DIVWU (MOVBZreg x) (MOVBZreg y)) 42 43 (Hmul64 x y) -> (MULHD x y) 44 (Hmul64u x y) -> (MULHDU x y) 45 (Hmul32 x y) -> (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) 46 (Hmul32u x y) -> (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) 47 48 (Mod64 x y) -> (MODD x y) 49 (Mod64u x y) -> (MODDU x y) 50 // MODW/MODWU has a 64-bit dividend and a 32-bit divisor, 51 // so a sign/zero extension of the dividend is required. 52 (Mod32 x y) -> (MODW (MOVWreg x) y) 53 (Mod32u x y) -> (MODWU (MOVWZreg x) y) 54 (Mod16 x y) -> (MODW (MOVHreg x) (MOVHreg y)) 55 (Mod16u x y) -> (MODWU (MOVHZreg x) (MOVHZreg y)) 56 (Mod8 x y) -> (MODW (MOVBreg x) (MOVBreg y)) 57 (Mod8u x y) -> (MODWU (MOVBZreg x) (MOVBZreg y)) 58 59 // (x + y) / 2 with x>=y -> (x - y) / 2 + y 60 (Avg64u <t> x y) -> (ADD (SRDconst <t> (SUB <t> x y) [1]) y) 61 62 (And64 x y) -> (AND x y) 63 (And32 x y) -> (ANDW x y) 64 (And16 x y) -> (ANDW x y) 65 (And8 x y) -> (ANDW x y) 66 67 (Or64 x y) -> (OR x y) 68 (Or32 x y) -> (ORW x y) 69 (Or16 x y) -> (ORW x y) 70 (Or8 x y) -> (ORW x y) 71 72 (Xor64 x y) -> (XOR x y) 73 (Xor32 x y) -> (XORW x y) 74 (Xor16 x y) -> (XORW x y) 75 (Xor8 x y) -> (XORW x y) 76 77 (Neg64 x) -> (NEG x) 78 (Neg32 x) -> (NEGW x) 79 (Neg16 x) -> (NEGW (MOVHreg x)) 80 (Neg8 x) -> (NEGW (MOVBreg x)) 81 (Neg32F x) -> (FNEGS x) 82 (Neg64F x) -> (FNEG x) 83 84 (Com64 x) -> (NOT x) 85 (Com32 x) -> (NOTW x) 86 (Com16 x) -> (NOTW x) 87 (Com8 x) -> (NOTW x) 88 (NOT x) && true -> (XOR (MOVDconst [-1]) x) 89 (NOTW x) && true -> (XORWconst [-1] x) 90 91 // Lowering boolean ops 92 (AndB x y) -> (ANDW x y) 93 (OrB x y) -> (ORW x y) 94 (Not x) -> (XORWconst [1] x) 95 96 // Lowering pointer arithmetic 97 (OffPtr [off] ptr:(SP)) -> (MOVDaddr [off] ptr) 98 (OffPtr [off] ptr) && is32Bit(off) -> (ADDconst [off] ptr) 99 (OffPtr [off] ptr) -> (ADD (MOVDconst [off]) ptr) 100 101 // Ctz(x) = 64 - findLeftmostOne((x-1)&^x) 102 (Ctz64 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (AND <t> (SUBconst <t> [1] x) (NOT <t> x)))) 103 (Ctz32 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (MOVWZreg (ANDW <t> (SUBWconst <t> [1] x) (NOTW <t> x))))) 104 105 (BitLen64 x) -> (SUB (MOVDconst [64]) (FLOGR x)) 106 107 (Bswap64 x) -> (MOVDBR x) 108 (Bswap32 x) -> (MOVWBR x) 109 110 // math package intrinsics 111 (Sqrt x) -> (FSQRT x) 112 (Floor x) -> (FIDBR [7] x) 113 (Ceil x) -> (FIDBR [6] x) 114 (Trunc x) -> (FIDBR [5] x) 115 (Round x) -> (FIDBR [1] x) 116 117 // Atomic loads. 118 (AtomicLoad32 ptr mem) -> (MOVWZatomicload ptr mem) 119 (AtomicLoad64 ptr mem) -> (MOVDatomicload ptr mem) 120 (AtomicLoadPtr ptr mem) -> (MOVDatomicload ptr mem) 121 122 // Atomic stores. 123 (AtomicStore32 ptr val mem) -> (MOVWatomicstore ptr val mem) 124 (AtomicStore64 ptr val mem) -> (MOVDatomicstore ptr val mem) 125 (AtomicStorePtrNoWB ptr val mem) -> (MOVDatomicstore ptr val mem) 126 127 // Atomic adds. 128 (AtomicAdd32 ptr val mem) -> (AddTupleFirst32 val (LAA ptr val mem)) 129 (AtomicAdd64 ptr val mem) -> (AddTupleFirst64 val (LAAG ptr val mem)) 130 (Select0 <t> (AddTupleFirst32 val tuple)) -> (ADDW val (Select0 <t> tuple)) 131 (Select1 (AddTupleFirst32 _ tuple)) -> (Select1 tuple) 132 (Select0 <t> (AddTupleFirst64 val tuple)) -> (ADD val (Select0 <t> tuple)) 133 (Select1 (AddTupleFirst64 _ tuple)) -> (Select1 tuple) 134 135 // Atomic exchanges. 136 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 137 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 138 139 // Atomic compare and swap. 140 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 141 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 142 143 // Lowering extension 144 // Note: we always extend to 64 bits even though some ops don't need that many result bits. 145 (SignExt8to16 x) -> (MOVBreg x) 146 (SignExt8to32 x) -> (MOVBreg x) 147 (SignExt8to64 x) -> (MOVBreg x) 148 (SignExt16to32 x) -> (MOVHreg x) 149 (SignExt16to64 x) -> (MOVHreg x) 150 (SignExt32to64 x) -> (MOVWreg x) 151 152 (ZeroExt8to16 x) -> (MOVBZreg x) 153 (ZeroExt8to32 x) -> (MOVBZreg x) 154 (ZeroExt8to64 x) -> (MOVBZreg x) 155 (ZeroExt16to32 x) -> (MOVHZreg x) 156 (ZeroExt16to64 x) -> (MOVHZreg x) 157 (ZeroExt32to64 x) -> (MOVWZreg x) 158 159 (Slicemask <t> x) -> (SRADconst (NEG <t> x) [63]) 160 161 // Lowering truncation 162 // Because we ignore high parts of registers, truncates are just copies. 163 (Trunc16to8 x) -> x 164 (Trunc32to8 x) -> x 165 (Trunc32to16 x) -> x 166 (Trunc64to8 x) -> x 167 (Trunc64to16 x) -> x 168 (Trunc64to32 x) -> x 169 170 // Lowering float <-> int 171 (Cvt32to32F x) -> (CEFBRA x) 172 (Cvt32to64F x) -> (CDFBRA x) 173 (Cvt64to32F x) -> (CEGBRA x) 174 (Cvt64to64F x) -> (CDGBRA x) 175 176 (Cvt32Fto32 x) -> (CFEBRA x) 177 (Cvt32Fto64 x) -> (CGEBRA x) 178 (Cvt64Fto32 x) -> (CFDBRA x) 179 (Cvt64Fto64 x) -> (CGDBRA x) 180 181 (Cvt32Fto64F x) -> (LDEBR x) 182 (Cvt64Fto32F x) -> (LEDBR x) 183 184 (Round32F x) -> (LoweredRound32F x) 185 (Round64F x) -> (LoweredRound64F x) 186 187 // Lowering shifts 188 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 189 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 190 (Lsh64x64 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 191 (Lsh64x32 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 192 (Lsh64x16 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 193 (Lsh64x8 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 194 195 (Lsh32x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 196 (Lsh32x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 197 (Lsh32x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 198 (Lsh32x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 199 200 (Lsh16x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 201 (Lsh16x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 202 (Lsh16x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 203 (Lsh16x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 204 205 (Lsh8x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 206 (Lsh8x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 207 (Lsh8x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 208 (Lsh8x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 209 210 (Rsh64Ux64 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 211 (Rsh64Ux32 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 212 (Rsh64Ux16 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 213 (Rsh64Ux8 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 214 215 (Rsh32Ux64 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 216 (Rsh32Ux32 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 217 (Rsh32Ux16 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 218 (Rsh32Ux8 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 219 220 (Rsh16Ux64 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [15]))) 221 (Rsh16Ux32 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [15]))) 222 (Rsh16Ux16 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [15]))) 223 (Rsh16Ux8 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [15]))) 224 225 (Rsh8Ux64 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [7]))) 226 (Rsh8Ux32 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [7]))) 227 (Rsh8Ux16 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [7]))) 228 (Rsh8Ux8 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [7]))) 229 230 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 231 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 232 (Rsh64x64 <t> x y) -> (SRAD <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [63]))))) 233 (Rsh64x32 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [63]))))) 234 (Rsh64x16 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [63]))))) 235 (Rsh64x8 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [63]))))) 236 237 (Rsh32x64 <t> x y) -> (SRAW <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [31]))))) 238 (Rsh32x32 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [31]))))) 239 (Rsh32x16 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [31]))))) 240 (Rsh32x8 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [31]))))) 241 242 (Rsh16x64 <t> x y) -> (SRAW <t> (MOVHreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [15]))))) 243 (Rsh16x32 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [15]))))) 244 (Rsh16x16 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [15]))))) 245 (Rsh16x8 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [15]))))) 246 247 (Rsh8x64 <t> x y) -> (SRAW <t> (MOVBreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [7]))))) 248 (Rsh8x32 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [7]))))) 249 (Rsh8x16 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [7]))))) 250 (Rsh8x8 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [7]))))) 251 252 // Lowering comparisons 253 (Less64 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 254 (Less32 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 255 (Less16 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 256 (Less8 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 257 (Less64U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 258 (Less32U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 259 (Less16U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 260 (Less8U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 261 // Use SETG with reversed operands to dodge NaN case. 262 (Less64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 263 (Less32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 264 265 (Leq64 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 266 (Leq32 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 267 (Leq16 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 268 (Leq8 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 269 (Leq64U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 270 (Leq32U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 271 (Leq16U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 272 (Leq8U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 273 // Use SETGE with reversed operands to dodge NaN case. 274 (Leq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 275 (Leq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 276 277 (Greater64 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 278 (Greater32 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 279 (Greater16 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 280 (Greater8 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 281 (Greater64U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 282 (Greater32U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 283 (Greater16U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 284 (Greater8U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 285 (Greater64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 286 (Greater32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 287 288 (Geq64 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 289 (Geq32 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 290 (Geq16 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 291 (Geq8 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 292 (Geq64U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 293 (Geq32U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 294 (Geq16U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 295 (Geq8U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 296 (Geq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 297 (Geq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 298 299 (Eq64 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 300 (Eq32 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 301 (Eq16 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 302 (Eq8 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 303 (EqB x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 304 (EqPtr x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 305 (Eq64F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 306 (Eq32F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 307 308 (Neq64 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 309 (Neq32 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 310 (Neq16 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 311 (Neq8 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 312 (NeqB x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 313 (NeqPtr x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 314 (Neq64F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 315 (Neq32F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 316 317 // Lowering loads 318 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVDload ptr mem) 319 (Load <t> ptr mem) && is32BitInt(t) && isSigned(t) -> (MOVWload ptr mem) 320 (Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) -> (MOVWZload ptr mem) 321 (Load <t> ptr mem) && is16BitInt(t) && isSigned(t) -> (MOVHload ptr mem) 322 (Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem) 323 (Load <t> ptr mem) && is8BitInt(t) && isSigned(t) -> (MOVBload ptr mem) 324 (Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) -> (MOVBZload ptr mem) 325 (Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem) 326 (Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem) 327 328 // Lowering stores 329 // These more-specific FP versions of Store pattern should come first. 330 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem) 331 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem) 332 333 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 -> (MOVDstore ptr val mem) 334 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 -> (MOVWstore ptr val mem) 335 (Store {t} ptr val mem) && t.(*types.Type).Size() == 2 -> (MOVHstore ptr val mem) 336 (Store {t} ptr val mem) && t.(*types.Type).Size() == 1 -> (MOVBstore ptr val mem) 337 338 // Lowering moves 339 340 // Load and store for small copies. 341 (Move [0] _ _ mem) -> mem 342 (Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem) 343 (Move [2] dst src mem) -> (MOVHstore dst (MOVHZload src mem) mem) 344 (Move [4] dst src mem) -> (MOVWstore dst (MOVWZload src mem) mem) 345 (Move [8] dst src mem) -> (MOVDstore dst (MOVDload src mem) mem) 346 (Move [16] dst src mem) -> 347 (MOVDstore [8] dst (MOVDload [8] src mem) 348 (MOVDstore dst (MOVDload src mem) mem)) 349 (Move [24] dst src mem) -> 350 (MOVDstore [16] dst (MOVDload [16] src mem) 351 (MOVDstore [8] dst (MOVDload [8] src mem) 352 (MOVDstore dst (MOVDload src mem) mem))) 353 (Move [3] dst src mem) -> 354 (MOVBstore [2] dst (MOVBZload [2] src mem) 355 (MOVHstore dst (MOVHZload src mem) mem)) 356 (Move [5] dst src mem) -> 357 (MOVBstore [4] dst (MOVBZload [4] src mem) 358 (MOVWstore dst (MOVWZload src mem) mem)) 359 (Move [6] dst src mem) -> 360 (MOVHstore [4] dst (MOVHZload [4] src mem) 361 (MOVWstore dst (MOVWZload src mem) mem)) 362 (Move [7] dst src mem) -> 363 (MOVBstore [6] dst (MOVBZload [6] src mem) 364 (MOVHstore [4] dst (MOVHZload [4] src mem) 365 (MOVWstore dst (MOVWZload src mem) mem))) 366 367 // MVC for other moves. Use up to 4 instructions (sizes up to 1024 bytes). 368 (Move [s] dst src mem) && s > 0 && s <= 256 -> 369 (MVC [makeValAndOff(s, 0)] dst src mem) 370 (Move [s] dst src mem) && s > 256 && s <= 512 -> 371 (MVC [makeValAndOff(s-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)) 372 (Move [s] dst src mem) && s > 512 && s <= 768 -> 373 (MVC [makeValAndOff(s-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))) 374 (Move [s] dst src mem) && s > 768 && s <= 1024 -> 375 (MVC [makeValAndOff(s-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))) 376 377 // Move more than 1024 bytes using a loop. 378 (Move [s] dst src mem) && s > 1024 -> 379 (LoweredMove [s%256] dst src (ADDconst <src.Type> src [(s/256)*256]) mem) 380 381 // Lowering Zero instructions 382 (Zero [0] _ mem) -> mem 383 (Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem) 384 (Zero [2] destptr mem) -> (MOVHstoreconst [0] destptr mem) 385 (Zero [4] destptr mem) -> (MOVWstoreconst [0] destptr mem) 386 (Zero [8] destptr mem) -> (MOVDstoreconst [0] destptr mem) 387 (Zero [3] destptr mem) -> 388 (MOVBstoreconst [makeValAndOff(0,2)] destptr 389 (MOVHstoreconst [0] destptr mem)) 390 (Zero [5] destptr mem) -> 391 (MOVBstoreconst [makeValAndOff(0,4)] destptr 392 (MOVWstoreconst [0] destptr mem)) 393 (Zero [6] destptr mem) -> 394 (MOVHstoreconst [makeValAndOff(0,4)] destptr 395 (MOVWstoreconst [0] destptr mem)) 396 (Zero [7] destptr mem) -> 397 (MOVWstoreconst [makeValAndOff(0,3)] destptr 398 (MOVWstoreconst [0] destptr mem)) 399 400 (Zero [s] destptr mem) && s > 0 && s <= 1024 -> 401 (CLEAR [makeValAndOff(s, 0)] destptr mem) 402 403 // Move more than 1024 bytes using a loop. 404 (Zero [s] destptr mem) && s > 1024 -> 405 (LoweredZero [s%256] destptr (ADDconst <destptr.Type> destptr [(s/256)*256]) mem) 406 407 // Lowering constants 408 (Const8 [val]) -> (MOVDconst [val]) 409 (Const16 [val]) -> (MOVDconst [val]) 410 (Const32 [val]) -> (MOVDconst [val]) 411 (Const64 [val]) -> (MOVDconst [val]) 412 (Const32F [val]) -> (FMOVSconst [val]) 413 (Const64F [val]) -> (FMOVDconst [val]) 414 (ConstNil) -> (MOVDconst [0]) 415 (ConstBool [b]) -> (MOVDconst [b]) 416 417 // Lowering calls 418 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 419 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 420 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 421 422 // Miscellaneous 423 (Convert <t> x mem) -> (MOVDconvert <t> x mem) 424 (IsNonNil p) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0])) 425 (IsInBounds idx len) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 426 (IsSliceInBounds idx len) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 427 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 428 (GetG mem) -> (LoweredGetG mem) 429 (GetClosurePtr) -> (LoweredGetClosurePtr) 430 (GetCallerSP) -> (LoweredGetCallerSP) 431 (Addr {sym} base) -> (MOVDaddr {sym} base) 432 (ITab (Load ptr mem)) -> (MOVDload ptr mem) 433 434 // block rewrites 435 (If (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LT cmp yes no) 436 (If (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LE cmp yes no) 437 (If (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GT cmp yes no) 438 (If (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GE cmp yes no) 439 (If (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (EQ cmp yes no) 440 (If (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (NE cmp yes no) 441 442 // Special case for floating point - LF/LEF not generated. 443 (If (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GTF cmp yes no) 444 (If (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GEF cmp yes no) 445 446 (If cond yes no) -> (NE (CMPWconst [0] (MOVBZreg <typ.Bool> cond)) yes no) 447 448 // *************************** 449 // Above: lowering rules 450 // Below: optimizations 451 // *************************** 452 // TODO: Should the optimizations be a separate pass? 453 454 // Fold unnecessary type conversions. 455 (MOVDreg <t> x) && t.Compare(x.Type) == types.CMPeq -> x 456 (MOVDnop <t> x) && t.Compare(x.Type) == types.CMPeq -> x 457 458 // Propagate constants through type conversions. 459 (MOVDreg (MOVDconst [c])) -> (MOVDconst [c]) 460 (MOVDnop (MOVDconst [c])) -> (MOVDconst [c]) 461 462 // If a register move has only 1 use, just use the same register without emitting instruction. 463 // MOVDnop doesn't emit instruction, only for ensuring the type. 464 (MOVDreg x) && x.Uses == 1 -> (MOVDnop x) 465 466 // Fold type changes into loads. 467 (MOVDreg <t> x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <t> [off] {sym} ptr mem) 468 (MOVDreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem) 469 (MOVDreg <t> x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <t> [off] {sym} ptr mem) 470 (MOVDreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem) 471 (MOVDreg <t> x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <t> [off] {sym} ptr mem) 472 (MOVDreg <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <t> [off] {sym} ptr mem) 473 (MOVDreg <t> x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDload <t> [off] {sym} ptr mem) 474 475 (MOVDnop <t> x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <t> [off] {sym} ptr mem) 476 (MOVDnop <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <t> [off] {sym} ptr mem) 477 (MOVDnop <t> x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <t> [off] {sym} ptr mem) 478 (MOVDnop <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <t> [off] {sym} ptr mem) 479 (MOVDnop <t> x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <t> [off] {sym} ptr mem) 480 (MOVDnop <t> x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <t> [off] {sym} ptr mem) 481 (MOVDnop <t> x:(MOVDload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDload <t> [off] {sym} ptr mem) 482 483 // TODO(mundaym): uncomment rules once signed indexed loads are added. 484 (MOVDreg <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem) 485 //(MOVDreg <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem) 486 (MOVDreg <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem) 487 //(MOVDreg <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem) 488 (MOVDreg <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem) 489 //(MOVDreg <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem) 490 (MOVDreg <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem) 491 492 (MOVDnop <t> x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <t> [off] {sym} ptr idx mem) 493 //(MOVDnop <t> x:(MOVBloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBloadidx <t> [off] {sym} ptr idx mem) 494 (MOVDnop <t> x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <t> [off] {sym} ptr idx mem) 495 //(MOVDnop <t> x:(MOVHloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHloadidx <t> [off] {sym} ptr idx mem) 496 (MOVDnop <t> x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <t> [off] {sym} ptr idx mem) 497 //(MOVDnop <t> x:(MOVWloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWloadidx <t> [off] {sym} ptr idx mem) 498 (MOVDnop <t> x:(MOVDloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVDloadidx <t> [off] {sym} ptr idx mem) 499 500 // Fold sign extensions into conditional moves of constants. 501 // Designed to remove the MOVBZreg inserted by the If lowering. 502 (MOVBZreg x:(MOVDLT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 503 (MOVBZreg x:(MOVDLE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 504 (MOVBZreg x:(MOVDGT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 505 (MOVBZreg x:(MOVDGE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 506 (MOVBZreg x:(MOVDEQ (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 507 (MOVBZreg x:(MOVDNE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 508 (MOVBZreg x:(MOVDGTnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 509 (MOVBZreg x:(MOVDGEnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> (MOVDreg x) 510 511 // Fold boolean tests into blocks. 512 (NE (CMPWconst [0] (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LT cmp yes no) 513 (NE (CMPWconst [0] (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LE cmp yes no) 514 (NE (CMPWconst [0] (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GT cmp yes no) 515 (NE (CMPWconst [0] (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GE cmp yes no) 516 (NE (CMPWconst [0] (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (EQ cmp yes no) 517 (NE (CMPWconst [0] (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (NE cmp yes no) 518 (NE (CMPWconst [0] (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GTF cmp yes no) 519 (NE (CMPWconst [0] (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GEF cmp yes no) 520 521 // Fold constants into instructions. 522 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x) 523 (ADDW x (MOVDconst [c])) -> (ADDWconst [c] x) 524 525 (SUB x (MOVDconst [c])) && is32Bit(c) -> (SUBconst x [c]) 526 (SUB (MOVDconst [c]) x) && is32Bit(c) -> (NEG (SUBconst <v.Type> x [c])) 527 (SUBW x (MOVDconst [c])) -> (SUBWconst x [c]) 528 (SUBW (MOVDconst [c]) x) -> (NEGW (SUBWconst <v.Type> x [c])) 529 530 (MULLD x (MOVDconst [c])) && is32Bit(c) -> (MULLDconst [c] x) 531 (MULLW x (MOVDconst [c])) -> (MULLWconst [c] x) 532 533 // NILF instructions leave the high 32 bits unchanged which is 534 // equivalent to the leftmost 32 bits being set. 535 // TODO(mundaym): modify the assembler to accept 64-bit values 536 // and use isU32Bit(^c). 537 (AND x (MOVDconst [c])) && is32Bit(c) && c < 0 -> (ANDconst [c] x) 538 (ANDW x (MOVDconst [c])) -> (ANDWconst [c] x) 539 540 (ANDWconst [c] (ANDWconst [d] x)) -> (ANDWconst [c & d] x) 541 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c & d] x) 542 543 (OR x (MOVDconst [c])) && isU32Bit(c) -> (ORconst [c] x) 544 (ORW x (MOVDconst [c])) -> (ORWconst [c] x) 545 546 (XOR x (MOVDconst [c])) && isU32Bit(c) -> (XORconst [c] x) 547 (XORW x (MOVDconst [c])) -> (XORWconst [c] x) 548 549 (SLD x (MOVDconst [c])) -> (SLDconst [c&63] x) 550 (SLW x (MOVDconst [c])) -> (SLWconst [c&63] x) 551 (SRD x (MOVDconst [c])) -> (SRDconst [c&63] x) 552 (SRW x (MOVDconst [c])) -> (SRWconst [c&63] x) 553 (SRAD x (MOVDconst [c])) -> (SRADconst [c&63] x) 554 (SRAW x (MOVDconst [c])) -> (SRAWconst [c&63] x) 555 556 (SRAW x (ANDWconst [63] y)) -> (SRAW x y) 557 (SRAD x (ANDconst [63] y)) -> (SRAD x y) 558 (SLW x (ANDWconst [63] y)) -> (SLW x y) 559 (SLD x (ANDconst [63] y)) -> (SLD x y) 560 (SRW x (ANDWconst [63] y)) -> (SRW x y) 561 (SRD x (ANDconst [63] y)) -> (SRD x y) 562 563 // Rotate generation 564 (ADD (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 565 ( OR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 566 (XOR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (RLLGconst [c] x) 567 568 (ADDW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 569 ( ORW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 570 (XORW (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (RLLconst [c] x) 571 572 (CMP x (MOVDconst [c])) && is32Bit(c) -> (CMPconst x [c]) 573 (CMP (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPconst x [c])) 574 (CMPW x (MOVDconst [c])) -> (CMPWconst x [c]) 575 (CMPW (MOVDconst [c]) x) -> (InvertFlags (CMPWconst x [c])) 576 (CMPU x (MOVDconst [c])) && isU32Bit(c) -> (CMPUconst x [int64(uint32(c))]) 577 (CMPU (MOVDconst [c]) x) && isU32Bit(c) -> (InvertFlags (CMPUconst x [int64(uint32(c))])) 578 (CMPWU x (MOVDconst [c])) -> (CMPWUconst x [int64(uint32(c))]) 579 (CMPWU (MOVDconst [c]) x) -> (InvertFlags (CMPWUconst x [int64(uint32(c))])) 580 581 // Using MOV{W,H,B}Zreg instead of AND is cheaper. 582 (AND x (MOVDconst [0xFF])) -> (MOVBZreg x) 583 (AND x (MOVDconst [0xFFFF])) -> (MOVHZreg x) 584 (AND x (MOVDconst [0xFFFFFFFF])) -> (MOVWZreg x) 585 (ANDWconst [0xFF] x) -> (MOVBZreg x) 586 (ANDWconst [0xFFFF] x) -> (MOVHZreg x) 587 588 // strength reduction 589 (MULLDconst [-1] x) -> (NEG x) 590 (MULLDconst [0] _) -> (MOVDconst [0]) 591 (MULLDconst [1] x) -> x 592 (MULLDconst [c] x) && isPowerOfTwo(c) -> (SLDconst [log2(c)] x) 593 (MULLDconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUB (SLDconst <v.Type> [log2(c+1)] x) x) 594 (MULLDconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADD (SLDconst <v.Type> [log2(c-1)] x) x) 595 596 (MULLWconst [-1] x) -> (NEGW x) 597 (MULLWconst [0] _) -> (MOVDconst [0]) 598 (MULLWconst [1] x) -> x 599 (MULLWconst [c] x) && isPowerOfTwo(c) -> (SLWconst [log2(c)] x) 600 (MULLWconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUBW (SLWconst <v.Type> [log2(c+1)] x) x) 601 (MULLWconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADDW (SLWconst <v.Type> [log2(c-1)] x) x) 602 603 // Fold ADD into MOVDaddr. Odd offsets from SB shouldn't be folded (LARL can't handle them). 604 (ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 605 (ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is20Bit(c+d) -> (MOVDaddr [c+d] {s} x) 606 (ADD idx (MOVDaddr [c] {s} ptr)) && ptr.Op != OpSB && idx.Op != OpSB -> (MOVDaddridx [c] {s} ptr idx) 607 608 // fold ADDconst into MOVDaddrx 609 (ADDconst [c] (MOVDaddridx [d] {s} x y)) && is20Bit(c+d) -> (MOVDaddridx [c+d] {s} x y) 610 (MOVDaddridx [c] {s} (ADDconst [d] x) y) && is20Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 611 (MOVDaddridx [c] {s} x (ADDconst [d] y)) && is20Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 612 613 // reverse ordering of compare instruction 614 (MOVDLT x y (InvertFlags cmp)) -> (MOVDGT x y cmp) 615 (MOVDGT x y (InvertFlags cmp)) -> (MOVDLT x y cmp) 616 (MOVDLE x y (InvertFlags cmp)) -> (MOVDGE x y cmp) 617 (MOVDGE x y (InvertFlags cmp)) -> (MOVDLE x y cmp) 618 (MOVDEQ x y (InvertFlags cmp)) -> (MOVDEQ x y cmp) 619 (MOVDNE x y (InvertFlags cmp)) -> (MOVDNE x y cmp) 620 621 // don't extend after proper load 622 (MOVBreg x:(MOVBload _ _)) -> (MOVDreg x) 623 (MOVBZreg x:(MOVBZload _ _)) -> (MOVDreg x) 624 (MOVHreg x:(MOVBload _ _)) -> (MOVDreg x) 625 (MOVHreg x:(MOVBZload _ _)) -> (MOVDreg x) 626 (MOVHreg x:(MOVHload _ _)) -> (MOVDreg x) 627 (MOVHZreg x:(MOVBZload _ _)) -> (MOVDreg x) 628 (MOVHZreg x:(MOVHZload _ _)) -> (MOVDreg x) 629 (MOVWreg x:(MOVBload _ _)) -> (MOVDreg x) 630 (MOVWreg x:(MOVBZload _ _)) -> (MOVDreg x) 631 (MOVWreg x:(MOVHload _ _)) -> (MOVDreg x) 632 (MOVWreg x:(MOVHZload _ _)) -> (MOVDreg x) 633 (MOVWreg x:(MOVWload _ _)) -> (MOVDreg x) 634 (MOVWZreg x:(MOVBZload _ _)) -> (MOVDreg x) 635 (MOVWZreg x:(MOVHZload _ _)) -> (MOVDreg x) 636 (MOVWZreg x:(MOVWZload _ _)) -> (MOVDreg x) 637 638 // don't extend if argument is already extended 639 (MOVBreg x:(Arg <t>)) && is8BitInt(t) && isSigned(t) -> (MOVDreg x) 640 (MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !isSigned(t) -> (MOVDreg x) 641 (MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && isSigned(t) -> (MOVDreg x) 642 (MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) -> (MOVDreg x) 643 (MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) -> (MOVDreg x) 644 (MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) -> (MOVDreg x) 645 646 // fold double extensions 647 (MOVBreg x:(MOVBreg _)) -> (MOVDreg x) 648 (MOVBZreg x:(MOVBZreg _)) -> (MOVDreg x) 649 (MOVHreg x:(MOVBreg _)) -> (MOVDreg x) 650 (MOVHreg x:(MOVBZreg _)) -> (MOVDreg x) 651 (MOVHreg x:(MOVHreg _)) -> (MOVDreg x) 652 (MOVHZreg x:(MOVBZreg _)) -> (MOVDreg x) 653 (MOVHZreg x:(MOVHZreg _)) -> (MOVDreg x) 654 (MOVWreg x:(MOVBreg _)) -> (MOVDreg x) 655 (MOVWreg x:(MOVBZreg _)) -> (MOVDreg x) 656 (MOVWreg x:(MOVHreg _)) -> (MOVDreg x) 657 (MOVWreg x:(MOVHreg _)) -> (MOVDreg x) 658 (MOVWreg x:(MOVWreg _)) -> (MOVDreg x) 659 (MOVWZreg x:(MOVBZreg _)) -> (MOVDreg x) 660 (MOVWZreg x:(MOVHZreg _)) -> (MOVDreg x) 661 (MOVWZreg x:(MOVWZreg _)) -> (MOVDreg x) 662 663 // fold extensions into constants 664 (MOVBreg (MOVDconst [c])) -> (MOVDconst [int64(int8(c))]) 665 (MOVBZreg (MOVDconst [c])) -> (MOVDconst [int64(uint8(c))]) 666 (MOVHreg (MOVDconst [c])) -> (MOVDconst [int64(int16(c))]) 667 (MOVHZreg (MOVDconst [c])) -> (MOVDconst [int64(uint16(c))]) 668 (MOVWreg (MOVDconst [c])) -> (MOVDconst [int64(int32(c))]) 669 (MOVWZreg (MOVDconst [c])) -> (MOVDconst [int64(uint32(c))]) 670 671 // sign extended loads 672 // Note: The combined instruction must end up in the same block 673 // as the original load. If not, we end up making a value with 674 // memory type live in two different blocks, which can lead to 675 // multiple memory values alive simultaneously. 676 // Make sure we don't combine these ops if the load has another use. 677 // This prevents a single load from being split into multiple loads 678 // which then might return different values. See test/atomicload.go. 679 (MOVBreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 680 (MOVBZreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem) 681 (MOVHreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem) 682 (MOVHZreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem) 683 (MOVWreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 684 (MOVWZreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem) 685 686 (MOVBZreg x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem) 687 (MOVHZreg x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem) 688 (MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem) 689 690 // replace load from same location as preceding store with copy 691 (MOVBZload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBZreg x) 692 (MOVHZload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHZreg x) 693 (MOVWZload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWZreg x) 694 (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDreg x) 695 696 // Don't extend before storing 697 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 698 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 699 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 700 (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 701 (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 702 (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 703 704 // Fold constants into memory operations. 705 // Note that this is not always a good idea because if not all the uses of 706 // the ADDconst get eliminated, we still have to compute the ADDconst and we now 707 // have potentially two live values (ptr and (ADDconst [off] ptr)) instead of one. 708 // Nevertheless, let's do it! 709 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 710 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 711 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem) 712 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 713 (MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem) 714 (MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem) 715 (MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem) 716 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem) 717 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem) 718 719 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 720 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 721 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 722 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 723 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem) 724 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem) 725 726 // Fold constants into stores. 727 (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && is16Bit(c) && isU12Bit(off) && ptr.Op != OpSB -> 728 (MOVDstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 729 (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) && is16Bit(c) && isU12Bit(off) && ptr.Op != OpSB -> 730 (MOVWstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) 731 (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) && isU12Bit(off) && ptr.Op != OpSB -> 732 (MOVHstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) 733 (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) && is20Bit(off) && ptr.Op != OpSB -> 734 (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) 735 736 // Fold address offsets into constant stores. 737 (MOVDstoreconst [sc] {s} (ADDconst [off] ptr) mem) && isU12Bit(ValAndOff(sc).Off()+off) -> 738 (MOVDstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 739 (MOVWstoreconst [sc] {s} (ADDconst [off] ptr) mem) && isU12Bit(ValAndOff(sc).Off()+off) -> 740 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 741 (MOVHstoreconst [sc] {s} (ADDconst [off] ptr) mem) && isU12Bit(ValAndOff(sc).Off()+off) -> 742 (MOVHstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 743 (MOVBstoreconst [sc] {s} (ADDconst [off] ptr) mem) && is20Bit(ValAndOff(sc).Off()+off) -> 744 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 745 746 // Merge address calculations into loads and stores. 747 // Offsets from SB must not be merged into unaligned memory accesses because 748 // loads/stores using PC-relative addressing directly must be aligned to the 749 // size of the target. 750 (MOVDload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0)) -> 751 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 752 (MOVWZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) -> 753 (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 754 (MOVHZload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) -> 755 (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 756 (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 757 (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 758 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 759 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} base mem) 760 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 761 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 762 763 (MOVWload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) -> 764 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 765 (MOVHload [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) -> 766 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) 767 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 768 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 769 770 (MOVDstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%8 == 0 && (off1+off2)%8 == 0)) -> 771 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 772 (MOVWstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%4 == 0 && (off1+off2)%4 == 0)) -> 773 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 774 (MOVHstore [off1] {sym1} (MOVDaddr <t> [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || (t.IsPtr() && t.ElemType().Alignment()%2 == 0 && (off1+off2)%2 == 0)) -> 775 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 776 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 777 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 778 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 779 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 780 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 781 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 782 783 // Cannot store constant to SB directly (no 'move relative long immediate' instructions). 784 (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 785 (MOVDstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 786 (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 787 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 788 (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 789 (MOVHstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 790 (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && ptr.Op != OpSB && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 791 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 792 793 // generating indexed loads and stores 794 (MOVBZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 795 (MOVBZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 796 (MOVHZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 797 (MOVHZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 798 (MOVWZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 799 (MOVWZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 800 (MOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 801 (MOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 802 (FMOVSload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 803 (FMOVSloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 804 (FMOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 805 (FMOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 806 807 (MOVBstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 808 (MOVBstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 809 (MOVHstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 810 (MOVHstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 811 (MOVWstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 812 (MOVWstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 813 (MOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 814 (MOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 815 (FMOVSstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 816 (FMOVSstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 817 (FMOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 818 (FMOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 819 820 (MOVBZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVBZloadidx [off] {sym} ptr idx mem) 821 (MOVHZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVHZloadidx [off] {sym} ptr idx mem) 822 (MOVWZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVWZloadidx [off] {sym} ptr idx mem) 823 (MOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVDloadidx [off] {sym} ptr idx mem) 824 (FMOVSload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVSloadidx [off] {sym} ptr idx mem) 825 (FMOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVDloadidx [off] {sym} ptr idx mem) 826 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx [off] {sym} ptr idx val mem) 827 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVHstoreidx [off] {sym} ptr idx val mem) 828 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx [off] {sym} ptr idx val mem) 829 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVDstoreidx [off] {sym} ptr idx val mem) 830 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVSstoreidx [off] {sym} ptr idx val mem) 831 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVDstoreidx [off] {sym} ptr idx val mem) 832 833 // combine ADD into indexed loads and stores 834 (MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 835 (MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 836 (MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 837 (MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 838 (FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 839 (FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 840 841 (MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 842 (MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 843 (MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 844 (MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 845 (FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 846 (FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 847 848 (MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 849 (MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 850 (MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 851 (MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 852 (FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 853 (FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 854 855 (MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 856 (MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 857 (MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 858 (MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 859 (FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 860 (FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 861 862 // MOVDaddr into MOVDaddridx 863 (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 864 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 865 (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB -> 866 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 867 868 // Absorb InvertFlags into branches. 869 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 870 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 871 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 872 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 873 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 874 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 875 876 // Constant comparisons. 877 (CMPconst (MOVDconst [x]) [y]) && x==y -> (FlagEQ) 878 (CMPconst (MOVDconst [x]) [y]) && x<y -> (FlagLT) 879 (CMPconst (MOVDconst [x]) [y]) && x>y -> (FlagGT) 880 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)==uint64(y) -> (FlagEQ) 881 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) -> (FlagLT) 882 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) -> (FlagGT) 883 884 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 885 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) -> (FlagLT) 886 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) -> (FlagGT) 887 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)==uint32(y) -> (FlagEQ) 888 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) -> (FlagLT) 889 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) -> (FlagGT) 890 891 // Other known comparisons. 892 (CMPconst (MOVBZreg _) [c]) && 0xFF < c -> (FlagLT) 893 (CMPconst (MOVHZreg _) [c]) && 0xFFFF < c -> (FlagLT) 894 (CMPconst (MOVWZreg _) [c]) && 0xFFFFFFFF < c -> (FlagLT) 895 (CMPWconst (SRWconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT) 896 (CMPconst (SRDconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) -> (FlagLT) 897 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT) 898 (CMPWconst (ANDWconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT) 899 900 // Absorb flag constants into SBB ops. 901 (SUBEcarrymask (FlagEQ)) -> (MOVDconst [-1]) 902 (SUBEcarrymask (FlagLT)) -> (MOVDconst [-1]) 903 (SUBEcarrymask (FlagGT)) -> (MOVDconst [0]) 904 (SUBEWcarrymask (FlagEQ)) -> (MOVDconst [-1]) 905 (SUBEWcarrymask (FlagLT)) -> (MOVDconst [-1]) 906 (SUBEWcarrymask (FlagGT)) -> (MOVDconst [0]) 907 908 // Absorb flag constants into branches. 909 (EQ (FlagEQ) yes no) -> (First nil yes no) 910 (EQ (FlagLT) yes no) -> (First nil no yes) 911 (EQ (FlagGT) yes no) -> (First nil no yes) 912 913 (NE (FlagEQ) yes no) -> (First nil no yes) 914 (NE (FlagLT) yes no) -> (First nil yes no) 915 (NE (FlagGT) yes no) -> (First nil yes no) 916 917 (LT (FlagEQ) yes no) -> (First nil no yes) 918 (LT (FlagLT) yes no) -> (First nil yes no) 919 (LT (FlagGT) yes no) -> (First nil no yes) 920 921 (LE (FlagEQ) yes no) -> (First nil yes no) 922 (LE (FlagLT) yes no) -> (First nil yes no) 923 (LE (FlagGT) yes no) -> (First nil no yes) 924 925 (GT (FlagEQ) yes no) -> (First nil no yes) 926 (GT (FlagLT) yes no) -> (First nil no yes) 927 (GT (FlagGT) yes no) -> (First nil yes no) 928 929 (GE (FlagEQ) yes no) -> (First nil yes no) 930 (GE (FlagLT) yes no) -> (First nil no yes) 931 (GE (FlagGT) yes no) -> (First nil yes no) 932 933 // Absorb flag constants into SETxx ops. 934 (MOVDEQ _ x (FlagEQ)) -> x 935 (MOVDEQ y _ (FlagLT)) -> y 936 (MOVDEQ y _ (FlagGT)) -> y 937 938 (MOVDNE y _ (FlagEQ)) -> y 939 (MOVDNE _ x (FlagLT)) -> x 940 (MOVDNE _ x (FlagGT)) -> x 941 942 (MOVDLT y _ (FlagEQ)) -> y 943 (MOVDLT _ x (FlagLT)) -> x 944 (MOVDLT y _ (FlagGT)) -> y 945 946 (MOVDLE _ x (FlagEQ)) -> x 947 (MOVDLE _ x (FlagLT)) -> x 948 (MOVDLE y _ (FlagGT)) -> y 949 950 (MOVDGT y _ (FlagEQ)) -> y 951 (MOVDGT y _ (FlagLT)) -> y 952 (MOVDGT _ x (FlagGT)) -> x 953 954 (MOVDGE _ x (FlagEQ)) -> x 955 (MOVDGE y _ (FlagLT)) -> y 956 (MOVDGE _ x (FlagGT)) -> x 957 958 // Remove redundant *const ops 959 (ADDconst [0] x) -> x 960 (ADDWconst [c] x) && int32(c)==0 -> x 961 (SUBconst [0] x) -> x 962 (SUBWconst [c] x) && int32(c) == 0 -> x 963 (ANDconst [0] _) -> (MOVDconst [0]) 964 (ANDWconst [c] _) && int32(c)==0 -> (MOVDconst [0]) 965 (ANDconst [-1] x) -> x 966 (ANDWconst [c] x) && int32(c)==-1 -> x 967 (ORconst [0] x) -> x 968 (ORWconst [c] x) && int32(c)==0 -> x 969 (ORconst [-1] _) -> (MOVDconst [-1]) 970 (ORWconst [c] _) && int32(c)==-1 -> (MOVDconst [-1]) 971 (XORconst [0] x) -> x 972 (XORWconst [c] x) && int32(c)==0 -> x 973 974 // Convert constant subtracts to constant adds. 975 (SUBconst [c] x) && c != -(1<<31) -> (ADDconst [-c] x) 976 (SUBWconst [c] x) -> (ADDWconst [int64(int32(-c))] x) 977 978 // generic constant folding 979 // TODO: more of this 980 (ADDconst [c] (MOVDconst [d])) -> (MOVDconst [c+d]) 981 (ADDWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c+d))]) 982 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) -> (ADDconst [c+d] x) 983 (ADDWconst [c] (ADDWconst [d] x)) -> (ADDWconst [int64(int32(c+d))] x) 984 (SUBconst (MOVDconst [d]) [c]) -> (MOVDconst [d-c]) 985 (SUBconst (SUBconst x [d]) [c]) && is32Bit(-c-d) -> (ADDconst [-c-d] x) 986 (SRADconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 987 (SRAWconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 988 (NEG (MOVDconst [c])) -> (MOVDconst [-c]) 989 (NEGW (MOVDconst [c])) -> (MOVDconst [int64(int32(-c))]) 990 (MULLDconst [c] (MOVDconst [d])) -> (MOVDconst [c*d]) 991 (MULLWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c*d))]) 992 (AND (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c&d]) 993 (ANDconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 994 (ANDWconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 995 (OR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c|d]) 996 (ORconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 997 (ORWconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 998 (XOR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c^d]) 999 (XORconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 1000 (XORWconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 1001 (LoweredRound32F x:(FMOVSconst)) -> x 1002 (LoweredRound64F x:(FMOVDconst)) -> x 1003 1004 // generic simplifications 1005 // TODO: more of this 1006 (ADD x (NEG y)) -> (SUB x y) 1007 (ADDW x (NEGW y)) -> (SUBW x y) 1008 (SUB x x) -> (MOVDconst [0]) 1009 (SUBW x x) -> (MOVDconst [0]) 1010 (AND x x) -> x 1011 (ANDW x x) -> x 1012 (OR x x) -> x 1013 (ORW x x) -> x 1014 (XOR x x) -> (MOVDconst [0]) 1015 (XORW x x) -> (MOVDconst [0]) 1016 (NEG (ADDconst [c] (NEG x))) && c != -(1<<31) -> (ADDconst [-c] x) 1017 1018 // fused multiply-add 1019 (FADD (FMUL y z) x) -> (FMADD x y z) 1020 (FADDS (FMULS y z) x) -> (FMADDS x y z) 1021 (FSUB (FMUL y z) x) -> (FMSUB x y z) 1022 (FSUBS (FMULS y z) x) -> (FMSUBS x y z) 1023 1024 // Fold memory operations into operations. 1025 // Exclude global data (SB) because these instructions cannot handle relative addresses. 1026 // TODO(mundaym): use LARL in the assembler to handle SB? 1027 // TODO(mundaym): indexed versions of these? 1028 (ADD <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1029 -> (ADDload <t> [off] {sym} x ptr mem) 1030 (ADD <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1031 -> (ADDload <t> [off] {sym} x ptr mem) 1032 (ADDW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1033 -> (ADDWload <t> [off] {sym} x ptr mem) 1034 (ADDW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1035 -> (ADDWload <t> [off] {sym} x ptr mem) 1036 (ADDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1037 -> (ADDWload <t> [off] {sym} x ptr mem) 1038 (ADDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1039 -> (ADDWload <t> [off] {sym} x ptr mem) 1040 (MULLD <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1041 -> (MULLDload <t> [off] {sym} x ptr mem) 1042 (MULLD <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1043 -> (MULLDload <t> [off] {sym} x ptr mem) 1044 (MULLW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1045 -> (MULLWload <t> [off] {sym} x ptr mem) 1046 (MULLW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1047 -> (MULLWload <t> [off] {sym} x ptr mem) 1048 (MULLW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1049 -> (MULLWload <t> [off] {sym} x ptr mem) 1050 (MULLW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1051 -> (MULLWload <t> [off] {sym} x ptr mem) 1052 (SUB <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1053 -> (SUBload <t> [off] {sym} x ptr mem) 1054 (SUBW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1055 -> (SUBWload <t> [off] {sym} x ptr mem) 1056 (SUBW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1057 -> (SUBWload <t> [off] {sym} x ptr mem) 1058 (AND <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1059 -> (ANDload <t> [off] {sym} x ptr mem) 1060 (AND <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1061 -> (ANDload <t> [off] {sym} x ptr mem) 1062 (ANDW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1063 -> (ANDWload <t> [off] {sym} x ptr mem) 1064 (ANDW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1065 -> (ANDWload <t> [off] {sym} x ptr mem) 1066 (ANDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1067 -> (ANDWload <t> [off] {sym} x ptr mem) 1068 (ANDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1069 -> (ANDWload <t> [off] {sym} x ptr mem) 1070 (OR <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1071 -> (ORload <t> [off] {sym} x ptr mem) 1072 (OR <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1073 -> (ORload <t> [off] {sym} x ptr mem) 1074 (ORW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1075 -> (ORWload <t> [off] {sym} x ptr mem) 1076 (ORW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1077 -> (ORWload <t> [off] {sym} x ptr mem) 1078 (ORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1079 -> (ORWload <t> [off] {sym} x ptr mem) 1080 (ORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1081 -> (ORWload <t> [off] {sym} x ptr mem) 1082 (XOR <t> x g:(MOVDload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1083 -> (XORload <t> [off] {sym} x ptr mem) 1084 (XOR <t> g:(MOVDload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1085 -> (XORload <t> [off] {sym} x ptr mem) 1086 (XORW <t> x g:(MOVWload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1087 -> (XORWload <t> [off] {sym} x ptr mem) 1088 (XORW <t> g:(MOVWload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1089 -> (XORWload <t> [off] {sym} x ptr mem) 1090 (XORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1091 -> (XORWload <t> [off] {sym} x ptr mem) 1092 (XORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g, x) && clobber(g) 1093 -> (XORWload <t> [off] {sym} x ptr mem) 1094 1095 // Combine constant stores into larger (unaligned) stores. 1096 // Avoid SB because constant stores to relative offsets are 1097 // emulated by the assembler and also can't handle unaligned offsets. 1098 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) 1099 && p.Op != OpSB 1100 && x.Uses == 1 1101 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1102 && clobber(x) 1103 -> (MOVHstoreconst [makeValAndOff(ValAndOff(c).Val()&0xff | ValAndOff(a).Val()<<8, ValAndOff(a).Off())] {s} p mem) 1104 (MOVHstoreconst [c] {s} p x:(MOVHstoreconst [a] {s} p mem)) 1105 && p.Op != OpSB 1106 && x.Uses == 1 1107 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1108 && clobber(x) 1109 -> (MOVWstore [ValAndOff(a).Off()] {s} p (MOVDconst [int64(int32(ValAndOff(c).Val()&0xffff | ValAndOff(a).Val()<<16))]) mem) 1110 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) 1111 && p.Op != OpSB 1112 && x.Uses == 1 1113 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1114 && clobber(x) 1115 -> (MOVDstore [ValAndOff(a).Off()] {s} p (MOVDconst [ValAndOff(c).Val()&0xffffffff | ValAndOff(a).Val()<<32]) mem) 1116 1117 // Combine stores into larger (unaligned) stores. 1118 // It doesn't work on global data (based on SB) because stores with relative addressing 1119 // require that the memory operand be aligned. 1120 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRDconst [8] w) mem)) 1121 && p.Op != OpSB 1122 && x.Uses == 1 1123 && clobber(x) 1124 -> (MOVHstore [i-1] {s} p w mem) 1125 (MOVBstore [i] {s} p w0:(SRDconst [j] w) x:(MOVBstore [i-1] {s} p (SRDconst [j+8] w) mem)) 1126 && p.Op != OpSB 1127 && x.Uses == 1 1128 && clobber(x) 1129 -> (MOVHstore [i-1] {s} p w0 mem) 1130 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRWconst [8] w) mem)) 1131 && p.Op != OpSB 1132 && x.Uses == 1 1133 && clobber(x) 1134 -> (MOVHstore [i-1] {s} p w mem) 1135 (MOVBstore [i] {s} p w0:(SRWconst [j] w) x:(MOVBstore [i-1] {s} p (SRWconst [j+8] w) mem)) 1136 && p.Op != OpSB 1137 && x.Uses == 1 1138 && clobber(x) 1139 -> (MOVHstore [i-1] {s} p w0 mem) 1140 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRDconst [16] w) mem)) 1141 && p.Op != OpSB 1142 && x.Uses == 1 1143 && clobber(x) 1144 -> (MOVWstore [i-2] {s} p w mem) 1145 (MOVHstore [i] {s} p w0:(SRDconst [j] w) x:(MOVHstore [i-2] {s} p (SRDconst [j+16] w) mem)) 1146 && p.Op != OpSB 1147 && x.Uses == 1 1148 && clobber(x) 1149 -> (MOVWstore [i-2] {s} p w0 mem) 1150 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRWconst [16] w) mem)) 1151 && p.Op != OpSB 1152 && x.Uses == 1 1153 && clobber(x) 1154 -> (MOVWstore [i-2] {s} p w mem) 1155 (MOVHstore [i] {s} p w0:(SRWconst [j] w) x:(MOVHstore [i-2] {s} p (SRWconst [j+16] w) mem)) 1156 && p.Op != OpSB 1157 && x.Uses == 1 1158 && clobber(x) 1159 -> (MOVWstore [i-2] {s} p w0 mem) 1160 (MOVWstore [i] {s} p (SRDconst [32] w) x:(MOVWstore [i-4] {s} p w mem)) 1161 && p.Op != OpSB 1162 && x.Uses == 1 1163 && clobber(x) 1164 -> (MOVDstore [i-4] {s} p w mem) 1165 (MOVWstore [i] {s} p w0:(SRDconst [j] w) x:(MOVWstore [i-4] {s} p (SRDconst [j+32] w) mem)) 1166 && p.Op != OpSB 1167 && x.Uses == 1 1168 && clobber(x) 1169 -> (MOVDstore [i-4] {s} p w0 mem) 1170 1171 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [8] w) mem)) 1172 && x.Uses == 1 1173 && clobber(x) 1174 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1175 (MOVBstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [j+8] w) mem)) 1176 && x.Uses == 1 1177 && clobber(x) 1178 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1179 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [8] w) mem)) 1180 && x.Uses == 1 1181 && clobber(x) 1182 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1183 (MOVBstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [j+8] w) mem)) 1184 && x.Uses == 1 1185 && clobber(x) 1186 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1187 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [16] w) mem)) 1188 && x.Uses == 1 1189 && clobber(x) 1190 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1191 (MOVHstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [j+16] w) mem)) 1192 && x.Uses == 1 1193 && clobber(x) 1194 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1195 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [16] w) mem)) 1196 && x.Uses == 1 1197 && clobber(x) 1198 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1199 (MOVHstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [j+16] w) mem)) 1200 && x.Uses == 1 1201 && clobber(x) 1202 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1203 (MOVWstoreidx [i] {s} p idx w x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [32] w) mem)) 1204 && x.Uses == 1 1205 && clobber(x) 1206 -> (MOVDstoreidx [i-4] {s} p idx w mem) 1207 (MOVWstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [j+32] w) mem)) 1208 && x.Uses == 1 1209 && clobber(x) 1210 -> (MOVDstoreidx [i-4] {s} p idx w0 mem) 1211 1212 // Combine stores into larger (unaligned) stores with the bytes reversed (little endian). 1213 // Store-with-bytes-reversed instructions do not support relative memory addresses, 1214 // so these stores can't operate on global data (SB). 1215 (MOVBstore [i] {s} p (SRDconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1216 && p.Op != OpSB 1217 && x.Uses == 1 1218 && clobber(x) 1219 -> (MOVHBRstore [i-1] {s} p w mem) 1220 (MOVBstore [i] {s} p (SRDconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRDconst [j-8] w) mem)) 1221 && p.Op != OpSB 1222 && x.Uses == 1 1223 && clobber(x) 1224 -> (MOVHBRstore [i-1] {s} p w0 mem) 1225 (MOVBstore [i] {s} p (SRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1226 && p.Op != OpSB 1227 && x.Uses == 1 1228 && clobber(x) 1229 -> (MOVHBRstore [i-1] {s} p w mem) 1230 (MOVBstore [i] {s} p (SRWconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRWconst [j-8] w) mem)) 1231 && p.Op != OpSB 1232 && x.Uses == 1 1233 && clobber(x) 1234 -> (MOVHBRstore [i-1] {s} p w0 mem) 1235 (MOVHBRstore [i] {s} p (SRDconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1236 && x.Uses == 1 1237 && clobber(x) 1238 -> (MOVWBRstore [i-2] {s} p w mem) 1239 (MOVHBRstore [i] {s} p (SRDconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRDconst [j-16] w) mem)) 1240 && x.Uses == 1 1241 && clobber(x) 1242 -> (MOVWBRstore [i-2] {s} p w0 mem) 1243 (MOVHBRstore [i] {s} p (SRWconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1244 && x.Uses == 1 1245 && clobber(x) 1246 -> (MOVWBRstore [i-2] {s} p w mem) 1247 (MOVHBRstore [i] {s} p (SRWconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRWconst [j-16] w) mem)) 1248 && x.Uses == 1 1249 && clobber(x) 1250 -> (MOVWBRstore [i-2] {s} p w0 mem) 1251 (MOVWBRstore [i] {s} p (SRDconst [32] w) x:(MOVWBRstore [i-4] {s} p w mem)) 1252 && x.Uses == 1 1253 && clobber(x) 1254 -> (MOVDBRstore [i-4] {s} p w mem) 1255 (MOVWBRstore [i] {s} p (SRDconst [j] w) x:(MOVWBRstore [i-4] {s} p w0:(SRDconst [j-32] w) mem)) 1256 && x.Uses == 1 1257 && clobber(x) 1258 -> (MOVDBRstore [i-4] {s} p w0 mem) 1259 1260 (MOVBstoreidx [i] {s} p idx (SRDconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1261 && x.Uses == 1 1262 && clobber(x) 1263 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1264 (MOVBstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRDconst [j-8] w) mem)) 1265 && x.Uses == 1 1266 && clobber(x) 1267 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1268 (MOVBstoreidx [i] {s} p idx (SRWconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1269 && x.Uses == 1 1270 && clobber(x) 1271 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1272 (MOVBstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRWconst [j-8] w) mem)) 1273 && x.Uses == 1 1274 && clobber(x) 1275 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1276 (MOVHBRstoreidx [i] {s} p idx (SRDconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1277 && x.Uses == 1 1278 && clobber(x) 1279 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1280 (MOVHBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRDconst [j-16] w) mem)) 1281 && x.Uses == 1 1282 && clobber(x) 1283 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1284 (MOVHBRstoreidx [i] {s} p idx (SRWconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1285 && x.Uses == 1 1286 && clobber(x) 1287 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1288 (MOVHBRstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRWconst [j-16] w) mem)) 1289 && x.Uses == 1 1290 && clobber(x) 1291 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1292 (MOVWBRstoreidx [i] {s} p idx (SRDconst [32] w) x:(MOVWBRstoreidx [i-4] {s} p idx w mem)) 1293 && x.Uses == 1 1294 && clobber(x) 1295 -> (MOVDBRstoreidx [i-4] {s} p idx w mem) 1296 (MOVWBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVWBRstoreidx [i-4] {s} p idx w0:(SRDconst [j-32] w) mem)) 1297 && x.Uses == 1 1298 && clobber(x) 1299 -> (MOVDBRstoreidx [i-4] {s} p idx w0 mem) 1300 1301 // Combining byte loads into larger (unaligned) loads. 1302 1303 // Big-endian loads 1304 1305 (ORW x1:(MOVBZload [i1] {s} p mem) 1306 sh:(SLWconst [8] x0:(MOVBZload [i0] {s} p mem))) 1307 && i1 == i0+1 1308 && p.Op != OpSB 1309 && x0.Uses == 1 1310 && x1.Uses == 1 1311 && sh.Uses == 1 1312 && mergePoint(b,x0,x1) != nil 1313 && clobber(x0) 1314 && clobber(x1) 1315 && clobber(sh) 1316 -> @mergePoint(b,x0,x1) (MOVHZload [i0] {s} p mem) 1317 1318 (OR x1:(MOVBZload [i1] {s} p mem) 1319 sh:(SLDconst [8] x0:(MOVBZload [i0] {s} p mem))) 1320 && i1 == i0+1 1321 && p.Op != OpSB 1322 && x0.Uses == 1 1323 && x1.Uses == 1 1324 && sh.Uses == 1 1325 && mergePoint(b,x0,x1) != nil 1326 && clobber(x0) 1327 && clobber(x1) 1328 && clobber(sh) 1329 -> @mergePoint(b,x0,x1) (MOVHZload [i0] {s} p mem) 1330 1331 (ORW x1:(MOVHZload [i1] {s} p mem) 1332 sh:(SLWconst [16] x0:(MOVHZload [i0] {s} p mem))) 1333 && i1 == i0+2 1334 && p.Op != OpSB 1335 && x0.Uses == 1 1336 && x1.Uses == 1 1337 && sh.Uses == 1 1338 && mergePoint(b,x0,x1) != nil 1339 && clobber(x0) 1340 && clobber(x1) 1341 && clobber(sh) 1342 -> @mergePoint(b,x0,x1) (MOVWZload [i0] {s} p mem) 1343 1344 (OR x1:(MOVHZload [i1] {s} p mem) 1345 sh:(SLDconst [16] x0:(MOVHZload [i0] {s} p mem))) 1346 && i1 == i0+2 1347 && p.Op != OpSB 1348 && x0.Uses == 1 1349 && x1.Uses == 1 1350 && sh.Uses == 1 1351 && mergePoint(b,x0,x1) != nil 1352 && clobber(x0) 1353 && clobber(x1) 1354 && clobber(sh) 1355 -> @mergePoint(b,x0,x1) (MOVWZload [i0] {s} p mem) 1356 1357 (OR x1:(MOVWZload [i1] {s} p mem) 1358 sh:(SLDconst [32] x0:(MOVWZload [i0] {s} p mem))) 1359 && i1 == i0+4 1360 && p.Op != OpSB 1361 && x0.Uses == 1 1362 && x1.Uses == 1 1363 && sh.Uses == 1 1364 && mergePoint(b,x0,x1) != nil 1365 && clobber(x0) 1366 && clobber(x1) 1367 && clobber(sh) 1368 -> @mergePoint(b,x0,x1) (MOVDload [i0] {s} p mem) 1369 1370 (ORW 1371 s0:(SLWconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1372 or:(ORW 1373 s1:(SLWconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1374 y)) 1375 && i1 == i0+1 1376 && j1 == j0-8 1377 && j1 % 16 == 0 1378 && x0.Uses == 1 1379 && x1.Uses == 1 1380 && s0.Uses == 1 1381 && s1.Uses == 1 1382 && or.Uses == 1 1383 && mergePoint(b,x0,x1) != nil 1384 && clobber(x0) 1385 && clobber(x1) 1386 && clobber(s0) 1387 && clobber(s1) 1388 && clobber(or) 1389 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j1] (MOVHZload [i0] {s} p mem)) y) 1390 1391 (OR 1392 s0:(SLDconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1393 or:(OR 1394 s1:(SLDconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1395 y)) 1396 && i1 == i0+1 1397 && j1 == j0-8 1398 && j1 % 16 == 0 1399 && x0.Uses == 1 1400 && x1.Uses == 1 1401 && s0.Uses == 1 1402 && s1.Uses == 1 1403 && or.Uses == 1 1404 && mergePoint(b,x0,x1) != nil 1405 && clobber(x0) 1406 && clobber(x1) 1407 && clobber(s0) 1408 && clobber(s1) 1409 && clobber(or) 1410 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVHZload [i0] {s} p mem)) y) 1411 1412 (OR 1413 s0:(SLDconst [j0] x0:(MOVHZload [i0] {s} p mem)) 1414 or:(OR 1415 s1:(SLDconst [j1] x1:(MOVHZload [i1] {s} p mem)) 1416 y)) 1417 && i1 == i0+2 1418 && j1 == j0-16 1419 && j1 % 32 == 0 1420 && x0.Uses == 1 1421 && x1.Uses == 1 1422 && s0.Uses == 1 1423 && s1.Uses == 1 1424 && or.Uses == 1 1425 && mergePoint(b,x0,x1) != nil 1426 && clobber(x0) 1427 && clobber(x1) 1428 && clobber(s0) 1429 && clobber(s1) 1430 && clobber(or) 1431 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVWZload [i0] {s} p mem)) y) 1432 1433 // Big-endian indexed loads 1434 1435 (ORW x1:(MOVBZloadidx [i1] {s} p idx mem) 1436 sh:(SLWconst [8] x0:(MOVBZloadidx [i0] {s} p idx mem))) 1437 && i1 == i0+1 1438 && p.Op != OpSB 1439 && x0.Uses == 1 1440 && x1.Uses == 1 1441 && sh.Uses == 1 1442 && mergePoint(b,x0,x1) != nil 1443 && clobber(x0) 1444 && clobber(x1) 1445 && clobber(sh) 1446 -> @mergePoint(b,x0,x1) (MOVHZloadidx [i0] {s} p idx mem) 1447 1448 (OR x1:(MOVBZloadidx [i1] {s} p idx mem) 1449 sh:(SLDconst [8] x0:(MOVBZloadidx [i0] {s} p idx mem))) 1450 && i1 == i0+1 1451 && p.Op != OpSB 1452 && x0.Uses == 1 1453 && x1.Uses == 1 1454 && sh.Uses == 1 1455 && mergePoint(b,x0,x1) != nil 1456 && clobber(x0) 1457 && clobber(x1) 1458 && clobber(sh) 1459 -> @mergePoint(b,x0,x1) (MOVHZloadidx [i0] {s} p idx mem) 1460 1461 (ORW x1:(MOVHZloadidx [i1] {s} p idx mem) 1462 sh:(SLWconst [16] x0:(MOVHZloadidx [i0] {s} p idx mem))) 1463 && i1 == i0+2 1464 && p.Op != OpSB 1465 && x0.Uses == 1 1466 && x1.Uses == 1 1467 && sh.Uses == 1 1468 && mergePoint(b,x0,x1) != nil 1469 && clobber(x0) 1470 && clobber(x1) 1471 && clobber(sh) 1472 -> @mergePoint(b,x0,x1) (MOVWZloadidx [i0] {s} p idx mem) 1473 1474 (OR x1:(MOVHZloadidx [i1] {s} p idx mem) 1475 sh:(SLDconst [16] x0:(MOVHZloadidx [i0] {s} p idx mem))) 1476 && i1 == i0+2 1477 && p.Op != OpSB 1478 && x0.Uses == 1 1479 && x1.Uses == 1 1480 && sh.Uses == 1 1481 && mergePoint(b,x0,x1) != nil 1482 && clobber(x0) 1483 && clobber(x1) 1484 && clobber(sh) 1485 -> @mergePoint(b,x0,x1) (MOVWZloadidx [i0] {s} p idx mem) 1486 1487 (OR x1:(MOVWZloadidx [i1] {s} p idx mem) 1488 sh:(SLDconst [32] x0:(MOVWZloadidx [i0] {s} p idx mem))) 1489 && i1 == i0+4 1490 && p.Op != OpSB 1491 && x0.Uses == 1 1492 && x1.Uses == 1 1493 && sh.Uses == 1 1494 && mergePoint(b,x0,x1) != nil 1495 && clobber(x0) 1496 && clobber(x1) 1497 && clobber(sh) 1498 -> @mergePoint(b,x0,x1) (MOVDloadidx [i0] {s} p idx mem) 1499 1500 (ORW 1501 s0:(SLWconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1502 or:(ORW 1503 s1:(SLWconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1504 y)) 1505 && i1 == i0+1 1506 && j1 == j0-8 1507 && j1 % 16 == 0 1508 && x0.Uses == 1 1509 && x1.Uses == 1 1510 && s0.Uses == 1 1511 && s1.Uses == 1 1512 && or.Uses == 1 1513 && mergePoint(b,x0,x1) != nil 1514 && clobber(x0) 1515 && clobber(x1) 1516 && clobber(s0) 1517 && clobber(s1) 1518 && clobber(or) 1519 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j1] (MOVHZloadidx [i0] {s} p idx mem)) y) 1520 1521 (OR 1522 s0:(SLDconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1523 or:(OR 1524 s1:(SLDconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1525 y)) 1526 && i1 == i0+1 1527 && j1 == j0-8 1528 && j1 % 16 == 0 1529 && x0.Uses == 1 1530 && x1.Uses == 1 1531 && s0.Uses == 1 1532 && s1.Uses == 1 1533 && or.Uses == 1 1534 && mergePoint(b,x0,x1) != nil 1535 && clobber(x0) 1536 && clobber(x1) 1537 && clobber(s0) 1538 && clobber(s1) 1539 && clobber(or) 1540 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVHZloadidx [i0] {s} p idx mem)) y) 1541 1542 (OR 1543 s0:(SLDconst [j0] x0:(MOVHZloadidx [i0] {s} p idx mem)) 1544 or:(OR 1545 s1:(SLDconst [j1] x1:(MOVHZloadidx [i1] {s} p idx mem)) 1546 y)) 1547 && i1 == i0+2 1548 && j1 == j0-16 1549 && j1 % 32 == 0 1550 && x0.Uses == 1 1551 && x1.Uses == 1 1552 && s0.Uses == 1 1553 && s1.Uses == 1 1554 && or.Uses == 1 1555 && mergePoint(b,x0,x1) != nil 1556 && clobber(x0) 1557 && clobber(x1) 1558 && clobber(s0) 1559 && clobber(s1) 1560 && clobber(or) 1561 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j1] (MOVWZloadidx [i0] {s} p idx mem)) y) 1562 1563 // Little-endian loads 1564 1565 (ORW x0:(MOVBZload [i0] {s} p mem) 1566 sh:(SLWconst [8] x1:(MOVBZload [i1] {s} p mem))) 1567 && p.Op != OpSB 1568 && i1 == i0+1 1569 && x0.Uses == 1 1570 && x1.Uses == 1 1571 && sh.Uses == 1 1572 && mergePoint(b,x0,x1) != nil 1573 && clobber(x0) 1574 && clobber(x1) 1575 && clobber(sh) 1576 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRload [i0] {s} p mem)) 1577 1578 (OR x0:(MOVBZload [i0] {s} p mem) 1579 sh:(SLDconst [8] x1:(MOVBZload [i1] {s} p mem))) 1580 && p.Op != OpSB 1581 && i1 == i0+1 1582 && x0.Uses == 1 1583 && x1.Uses == 1 1584 && sh.Uses == 1 1585 && mergePoint(b,x0,x1) != nil 1586 && clobber(x0) 1587 && clobber(x1) 1588 && clobber(sh) 1589 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRload [i0] {s} p mem)) 1590 1591 (ORW r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem)) 1592 sh:(SLWconst [16] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem)))) 1593 && i1 == i0+2 1594 && x0.Uses == 1 1595 && x1.Uses == 1 1596 && r0.Uses == 1 1597 && r1.Uses == 1 1598 && sh.Uses == 1 1599 && mergePoint(b,x0,x1) != nil 1600 && clobber(x0) 1601 && clobber(x1) 1602 && clobber(r0) 1603 && clobber(r1) 1604 && clobber(sh) 1605 -> @mergePoint(b,x0,x1) (MOVWBRload [i0] {s} p mem) 1606 1607 (OR r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem)) 1608 sh:(SLDconst [16] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem)))) 1609 && i1 == i0+2 1610 && x0.Uses == 1 1611 && x1.Uses == 1 1612 && r0.Uses == 1 1613 && r1.Uses == 1 1614 && sh.Uses == 1 1615 && mergePoint(b,x0,x1) != nil 1616 && clobber(x0) 1617 && clobber(x1) 1618 && clobber(r0) 1619 && clobber(r1) 1620 && clobber(sh) 1621 -> @mergePoint(b,x0,x1) (MOVWZreg (MOVWBRload [i0] {s} p mem)) 1622 1623 (OR r0:(MOVWZreg x0:(MOVWBRload [i0] {s} p mem)) 1624 sh:(SLDconst [32] r1:(MOVWZreg x1:(MOVWBRload [i1] {s} p mem)))) 1625 && i1 == i0+4 1626 && x0.Uses == 1 1627 && x1.Uses == 1 1628 && r0.Uses == 1 1629 && r1.Uses == 1 1630 && sh.Uses == 1 1631 && mergePoint(b,x0,x1) != nil 1632 && clobber(x0) 1633 && clobber(x1) 1634 && clobber(r0) 1635 && clobber(r1) 1636 && clobber(sh) 1637 -> @mergePoint(b,x0,x1) (MOVDBRload [i0] {s} p mem) 1638 1639 (ORW 1640 s1:(SLWconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1641 or:(ORW 1642 s0:(SLWconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1643 y)) 1644 && p.Op != OpSB 1645 && i1 == i0+1 1646 && j1 == j0+8 1647 && j0 % 16 == 0 1648 && x0.Uses == 1 1649 && x1.Uses == 1 1650 && s0.Uses == 1 1651 && s1.Uses == 1 1652 && or.Uses == 1 1653 && mergePoint(b,x0,x1) != nil 1654 && clobber(x0) 1655 && clobber(x1) 1656 && clobber(s0) 1657 && clobber(s1) 1658 && clobber(or) 1659 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j0] (MOVHZreg (MOVHBRload [i0] {s} p mem))) y) 1660 1661 (OR 1662 s1:(SLDconst [j1] x1:(MOVBZload [i1] {s} p mem)) 1663 or:(OR 1664 s0:(SLDconst [j0] x0:(MOVBZload [i0] {s} p mem)) 1665 y)) 1666 && p.Op != OpSB 1667 && i1 == i0+1 1668 && j1 == j0+8 1669 && j0 % 16 == 0 1670 && x0.Uses == 1 1671 && x1.Uses == 1 1672 && s0.Uses == 1 1673 && s1.Uses == 1 1674 && or.Uses == 1 1675 && mergePoint(b,x0,x1) != nil 1676 && clobber(x0) 1677 && clobber(x1) 1678 && clobber(s0) 1679 && clobber(s1) 1680 && clobber(or) 1681 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVHZreg (MOVHBRload [i0] {s} p mem))) y) 1682 1683 (OR 1684 s1:(SLDconst [j1] r1:(MOVHZreg x1:(MOVHBRload [i1] {s} p mem))) 1685 or:(OR 1686 s0:(SLDconst [j0] r0:(MOVHZreg x0:(MOVHBRload [i0] {s} p mem))) 1687 y)) 1688 && i1 == i0+2 1689 && j1 == j0+16 1690 && j0 % 32 == 0 1691 && x0.Uses == 1 1692 && x1.Uses == 1 1693 && r0.Uses == 1 1694 && r1.Uses == 1 1695 && s0.Uses == 1 1696 && s1.Uses == 1 1697 && or.Uses == 1 1698 && mergePoint(b,x0,x1) != nil 1699 && clobber(x0) 1700 && clobber(x1) 1701 && clobber(r0) 1702 && clobber(r1) 1703 && clobber(s0) 1704 && clobber(s1) 1705 && clobber(or) 1706 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVWZreg (MOVWBRload [i0] {s} p mem))) y) 1707 1708 // Little-endian indexed loads 1709 1710 (ORW x0:(MOVBZloadidx [i0] {s} p idx mem) 1711 sh:(SLWconst [8] x1:(MOVBZloadidx [i1] {s} p idx mem))) 1712 && p.Op != OpSB 1713 && i1 == i0+1 1714 && x0.Uses == 1 1715 && x1.Uses == 1 1716 && sh.Uses == 1 1717 && mergePoint(b,x0,x1) != nil 1718 && clobber(x0) 1719 && clobber(x1) 1720 && clobber(sh) 1721 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem)) 1722 1723 (OR x0:(MOVBZloadidx [i0] {s} p idx mem) 1724 sh:(SLDconst [8] x1:(MOVBZloadidx [i1] {s} p idx mem))) 1725 && p.Op != OpSB 1726 && i1 == i0+1 1727 && x0.Uses == 1 1728 && x1.Uses == 1 1729 && sh.Uses == 1 1730 && mergePoint(b,x0,x1) != nil 1731 && clobber(x0) 1732 && clobber(x1) 1733 && clobber(sh) 1734 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem)) 1735 1736 (ORW r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem)) 1737 sh:(SLWconst [16] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem)))) 1738 && i1 == i0+2 1739 && x0.Uses == 1 1740 && x1.Uses == 1 1741 && r0.Uses == 1 1742 && r1.Uses == 1 1743 && sh.Uses == 1 1744 && mergePoint(b,x0,x1) != nil 1745 && clobber(x0) 1746 && clobber(x1) 1747 && clobber(r0) 1748 && clobber(r1) 1749 && clobber(sh) 1750 -> @mergePoint(b,x0,x1) (MOVWBRloadidx [i0] {s} p idx mem) 1751 1752 (OR r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem)) 1753 sh:(SLDconst [16] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem)))) 1754 && i1 == i0+2 1755 && x0.Uses == 1 1756 && x1.Uses == 1 1757 && r0.Uses == 1 1758 && r1.Uses == 1 1759 && sh.Uses == 1 1760 && mergePoint(b,x0,x1) != nil 1761 && clobber(x0) 1762 && clobber(x1) 1763 && clobber(r0) 1764 && clobber(r1) 1765 && clobber(sh) 1766 -> @mergePoint(b,x0,x1) (MOVWZreg (MOVWBRloadidx [i0] {s} p idx mem)) 1767 1768 (OR r0:(MOVWZreg x0:(MOVWBRloadidx [i0] {s} p idx mem)) 1769 sh:(SLDconst [32] r1:(MOVWZreg x1:(MOVWBRloadidx [i1] {s} p idx mem)))) 1770 && i1 == i0+4 1771 && x0.Uses == 1 1772 && x1.Uses == 1 1773 && r0.Uses == 1 1774 && r1.Uses == 1 1775 && sh.Uses == 1 1776 && mergePoint(b,x0,x1) != nil 1777 && clobber(x0) 1778 && clobber(x1) 1779 && clobber(r0) 1780 && clobber(r1) 1781 && clobber(sh) 1782 -> @mergePoint(b,x0,x1) (MOVDBRloadidx [i0] {s} p idx mem) 1783 1784 (ORW 1785 s1:(SLWconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1786 or:(ORW 1787 s0:(SLWconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1788 y)) 1789 && p.Op != OpSB 1790 && i1 == i0+1 1791 && j1 == j0+8 1792 && j0 % 16 == 0 1793 && x0.Uses == 1 1794 && x1.Uses == 1 1795 && s0.Uses == 1 1796 && s1.Uses == 1 1797 && or.Uses == 1 1798 && mergePoint(b,x0,x1) != nil 1799 && clobber(x0) 1800 && clobber(x1) 1801 && clobber(s0) 1802 && clobber(s1) 1803 && clobber(or) 1804 -> @mergePoint(b,x0,x1) (ORW <v.Type> (SLWconst <v.Type> [j0] (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem))) y) 1805 1806 (OR 1807 s1:(SLDconst [j1] x1:(MOVBZloadidx [i1] {s} p idx mem)) 1808 or:(OR 1809 s0:(SLDconst [j0] x0:(MOVBZloadidx [i0] {s} p idx mem)) 1810 y)) 1811 && p.Op != OpSB 1812 && i1 == i0+1 1813 && j1 == j0+8 1814 && j0 % 16 == 0 1815 && x0.Uses == 1 1816 && x1.Uses == 1 1817 && s0.Uses == 1 1818 && s1.Uses == 1 1819 && or.Uses == 1 1820 && mergePoint(b,x0,x1) != nil 1821 && clobber(x0) 1822 && clobber(x1) 1823 && clobber(s0) 1824 && clobber(s1) 1825 && clobber(or) 1826 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVHZreg (MOVHBRloadidx [i0] {s} p idx mem))) y) 1827 1828 (OR 1829 s1:(SLDconst [j1] r1:(MOVHZreg x1:(MOVHBRloadidx [i1] {s} p idx mem))) 1830 or:(OR 1831 s0:(SLDconst [j0] r0:(MOVHZreg x0:(MOVHBRloadidx [i0] {s} p idx mem))) 1832 y)) 1833 && i1 == i0+2 1834 && j1 == j0+16 1835 && j0 % 32 == 0 1836 && x0.Uses == 1 1837 && x1.Uses == 1 1838 && r0.Uses == 1 1839 && r1.Uses == 1 1840 && s0.Uses == 1 1841 && s1.Uses == 1 1842 && or.Uses == 1 1843 && mergePoint(b,x0,x1) != nil 1844 && clobber(x0) 1845 && clobber(x1) 1846 && clobber(r0) 1847 && clobber(r1) 1848 && clobber(s0) 1849 && clobber(s1) 1850 && clobber(or) 1851 -> @mergePoint(b,x0,x1) (OR <v.Type> (SLDconst <v.Type> [j0] (MOVWZreg (MOVWBRloadidx [i0] {s} p idx mem))) y) 1852 1853 // Combine stores into store multiples. 1854 // 32-bit 1855 (MOVWstore [i] {s} p w1 x:(MOVWstore [i-4] {s} p w0 mem)) 1856 && p.Op != OpSB 1857 && x.Uses == 1 1858 && is20Bit(i-4) 1859 && clobber(x) 1860 -> (STM2 [i-4] {s} p w0 w1 mem) 1861 (MOVWstore [i] {s} p w2 x:(STM2 [i-8] {s} p w0 w1 mem)) 1862 && x.Uses == 1 1863 && is20Bit(i-8) 1864 && clobber(x) 1865 -> (STM3 [i-8] {s} p w0 w1 w2 mem) 1866 (MOVWstore [i] {s} p w3 x:(STM3 [i-12] {s} p w0 w1 w2 mem)) 1867 && x.Uses == 1 1868 && is20Bit(i-12) 1869 && clobber(x) 1870 -> (STM4 [i-12] {s} p w0 w1 w2 w3 mem) 1871 (STM2 [i] {s} p w2 w3 x:(STM2 [i-8] {s} p w0 w1 mem)) 1872 && x.Uses == 1 1873 && is20Bit(i-8) 1874 && clobber(x) 1875 -> (STM4 [i-8] {s} p w0 w1 w2 w3 mem) 1876 // 64-bit 1877 (MOVDstore [i] {s} p w1 x:(MOVDstore [i-8] {s} p w0 mem)) 1878 && p.Op != OpSB 1879 && x.Uses == 1 1880 && is20Bit(i-8) 1881 && clobber(x) 1882 -> (STMG2 [i-8] {s} p w0 w1 mem) 1883 (MOVDstore [i] {s} p w2 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1884 && x.Uses == 1 1885 && is20Bit(i-16) 1886 && clobber(x) 1887 -> (STMG3 [i-16] {s} p w0 w1 w2 mem) 1888 (MOVDstore [i] {s} p w3 x:(STMG3 [i-24] {s} p w0 w1 w2 mem)) 1889 && x.Uses == 1 1890 && is20Bit(i-24) 1891 && clobber(x) 1892 -> (STMG4 [i-24] {s} p w0 w1 w2 w3 mem) 1893 (STMG2 [i] {s} p w2 w3 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1894 && x.Uses == 1 1895 && is20Bit(i-16) 1896 && clobber(x) 1897 -> (STMG4 [i-16] {s} p w0 w1 w2 w3 mem) 1898 1899 // Convert 32-bit store multiples into 64-bit stores. 1900 (STM2 [i] {s} p (SRDconst [32] x) x mem) -> (MOVDstore [i] {s} p x mem)