github.com/mattn/go@v0.0.0-20171011075504-07f7db3ea99f/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 16 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form */ 366 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 367 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 368 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */ 369 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */ 370 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */ 371 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */ 372 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */ 373 374 /* Vector instructions */ 375 376 /* Vector load */ 377 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 378 379 /* Vector store */ 380 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 381 382 /* Vector logical */ 383 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 384 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 385 386 /* Vector add */ 387 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 388 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 389 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 390 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 391 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 392 393 /* Vector subtract */ 394 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 395 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 396 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 397 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 398 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 399 400 /* Vector multiply */ 401 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 402 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */ 403 404 /* Vector rotate */ 405 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 406 407 /* Vector shift */ 408 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 409 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 410 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 411 412 /* Vector count */ 413 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 414 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 415 416 /* Vector compare */ 417 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 418 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 419 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */ 420 421 /* Vector permute */ 422 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 423 424 /* Vector select */ 425 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 426 427 /* Vector splat */ 428 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 429 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 430 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 431 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 432 433 /* Vector AES */ 434 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 435 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 436 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 437 438 /* Vector SHA */ 439 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 440 441 /* VSX vector load */ 442 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 443 444 /* VSX vector store */ 445 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 446 447 /* VSX scalar load */ 448 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 449 450 /* VSX scalar store */ 451 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 452 453 /* VSX scalar as integer load */ 454 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 455 456 /* VSX scalar store as integer */ 457 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 458 459 /* VSX move from VSR */ 460 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 461 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 462 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 463 464 /* VSX move to VSR */ 465 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 466 {AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0}, 467 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 468 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 469 470 /* VSX logical */ 471 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 472 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 473 474 /* VSX select */ 475 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 476 477 /* VSX merge */ 478 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 479 480 /* VSX splat */ 481 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 482 483 /* VSX permute */ 484 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 485 486 /* VSX shift */ 487 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 488 489 /* VSX scalar FP-FP conversion */ 490 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 491 492 /* VSX vector FP-FP conversion */ 493 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 494 495 /* VSX scalar FP-integer conversion */ 496 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 497 498 /* VSX scalar integer-FP conversion */ 499 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 500 501 /* VSX vector FP-integer conversion */ 502 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 503 504 /* VSX vector integer-FP conversion */ 505 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 506 507 /* 64-bit special registers */ 508 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 509 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 510 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 511 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 512 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 513 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 514 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 515 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 516 517 /* 32-bit special registers (gloss over sign-extension or not?) */ 518 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 519 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 520 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 521 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 522 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 523 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 524 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 525 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 526 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 527 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 528 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 529 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 530 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 531 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 532 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 533 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 534 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 535 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 536 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 537 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 538 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 539 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 540 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 541 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 542 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 543 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 544 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 545 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 546 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 547 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 548 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 549 {ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 550 {ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0}, 551 {ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0}, 552 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 553 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 554 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 555 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 556 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 557 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 558 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 559 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 560 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 561 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 562 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 563 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 564 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 565 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 566 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 567 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 568 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 569 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 570 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 571 572 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 573 } 574 575 var oprange [ALAST & obj.AMask][]Optab 576 577 var xcmp [C_NCLASS][C_NCLASS]bool 578 579 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 580 p := cursym.Func.Text 581 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 582 return 583 } 584 585 if oprange[AANDN&obj.AMask] == nil { 586 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 587 } 588 589 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 590 591 pc := int64(0) 592 p.Pc = pc 593 594 var m int 595 var o *Optab 596 for p = p.Link; p != nil; p = p.Link { 597 p.Pc = pc 598 o = c.oplook(p) 599 m = int(o.size) 600 if m == 0 { 601 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 602 c.ctxt.Diag("zero-width instruction\n%v", p) 603 } 604 continue 605 } 606 607 pc += int64(m) 608 } 609 610 c.cursym.Size = pc 611 612 /* 613 * if any procedure is large enough to 614 * generate a large SBRA branch, then 615 * generate extra passes putting branches 616 * around jmps to fix. this is rare. 617 */ 618 bflag := 1 619 620 var otxt int64 621 var q *obj.Prog 622 for bflag != 0 { 623 bflag = 0 624 pc = 0 625 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 626 p.Pc = pc 627 o = c.oplook(p) 628 629 // very large conditional branches 630 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 631 otxt = p.Pcond.Pc - pc 632 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 633 q = c.newprog() 634 q.Link = p.Link 635 p.Link = q 636 q.As = ABR 637 q.To.Type = obj.TYPE_BRANCH 638 q.Pcond = p.Pcond 639 p.Pcond = q 640 q = c.newprog() 641 q.Link = p.Link 642 p.Link = q 643 q.As = ABR 644 q.To.Type = obj.TYPE_BRANCH 645 q.Pcond = q.Link.Link 646 647 //addnop(p->link); 648 //addnop(p); 649 bflag = 1 650 } 651 } 652 653 m = int(o.size) 654 if m == 0 { 655 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 656 c.ctxt.Diag("zero-width instruction\n%v", p) 657 } 658 continue 659 } 660 661 pc += int64(m) 662 } 663 664 c.cursym.Size = pc 665 } 666 667 pc += -pc & (funcAlign - 1) 668 c.cursym.Size = pc 669 670 /* 671 * lay out the code, emitting code and data relocations. 672 */ 673 674 c.cursym.Grow(c.cursym.Size) 675 676 bp := c.cursym.P 677 var i int32 678 var out [6]uint32 679 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 680 c.pc = p.Pc 681 o = c.oplook(p) 682 if int(o.size) > 4*len(out) { 683 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 684 } 685 c.asmout(p, o, out[:]) 686 for i = 0; i < int32(o.size/4); i++ { 687 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 688 bp = bp[4:] 689 } 690 } 691 } 692 693 func isint32(v int64) bool { 694 return int64(int32(v)) == v 695 } 696 697 func isuint32(v uint64) bool { 698 return uint64(uint32(v)) == v 699 } 700 701 func (c *ctxt9) aclass(a *obj.Addr) int { 702 switch a.Type { 703 case obj.TYPE_NONE: 704 return C_NONE 705 706 case obj.TYPE_REG: 707 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 708 return C_REG 709 } 710 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 711 return C_FREG 712 } 713 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 714 return C_VREG 715 } 716 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 717 return C_VSREG 718 } 719 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 720 return C_CREG 721 } 722 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 723 switch a.Reg { 724 case REG_LR: 725 return C_LR 726 727 case REG_XER: 728 return C_XER 729 730 case REG_CTR: 731 return C_CTR 732 } 733 734 return C_SPR 735 } 736 737 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 738 return C_SPR 739 } 740 if a.Reg == REG_FPSCR { 741 return C_FPSCR 742 } 743 if a.Reg == REG_MSR { 744 return C_MSR 745 } 746 return C_GOK 747 748 case obj.TYPE_MEM: 749 switch a.Name { 750 case obj.NAME_EXTERN, 751 obj.NAME_STATIC: 752 if a.Sym == nil { 753 break 754 } 755 c.instoffset = a.Offset 756 if a.Sym != nil { // use relocation 757 if a.Sym.Type == objabi.STLSBSS { 758 if c.ctxt.Flag_shared { 759 return C_TLS_IE 760 } else { 761 return C_TLS_LE 762 } 763 } 764 return C_ADDR 765 } 766 return C_LEXT 767 768 case obj.NAME_GOTREF: 769 return C_GOTADDR 770 771 case obj.NAME_AUTO: 772 c.instoffset = int64(c.autosize) + a.Offset 773 if c.instoffset >= -BIG && c.instoffset < BIG { 774 return C_SAUTO 775 } 776 return C_LAUTO 777 778 case obj.NAME_PARAM: 779 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 780 if c.instoffset >= -BIG && c.instoffset < BIG { 781 return C_SAUTO 782 } 783 return C_LAUTO 784 785 case obj.NAME_NONE: 786 c.instoffset = a.Offset 787 if c.instoffset == 0 { 788 return C_ZOREG 789 } 790 if c.instoffset >= -BIG && c.instoffset < BIG { 791 return C_SOREG 792 } 793 return C_LOREG 794 } 795 796 return C_GOK 797 798 case obj.TYPE_TEXTSIZE: 799 return C_TEXTSIZE 800 801 case obj.TYPE_CONST, 802 obj.TYPE_ADDR: 803 switch a.Name { 804 case obj.NAME_NONE: 805 c.instoffset = a.Offset 806 if a.Reg != 0 { 807 if -BIG <= c.instoffset && c.instoffset <= BIG { 808 return C_SACON 809 } 810 if isint32(c.instoffset) { 811 return C_LACON 812 } 813 return C_DACON 814 } 815 816 goto consize 817 818 case obj.NAME_EXTERN, 819 obj.NAME_STATIC: 820 s := a.Sym 821 if s == nil { 822 break 823 } 824 825 c.instoffset = a.Offset 826 827 /* not sure why this barfs */ 828 return C_LCON 829 830 case obj.NAME_AUTO: 831 c.instoffset = int64(c.autosize) + a.Offset 832 if c.instoffset >= -BIG && c.instoffset < BIG { 833 return C_SACON 834 } 835 return C_LACON 836 837 case obj.NAME_PARAM: 838 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 839 if c.instoffset >= -BIG && c.instoffset < BIG { 840 return C_SACON 841 } 842 return C_LACON 843 } 844 845 return C_GOK 846 847 consize: 848 if c.instoffset >= 0 { 849 if c.instoffset == 0 { 850 return C_ZCON 851 } 852 if c.instoffset <= 0x7fff { 853 return C_SCON 854 } 855 if c.instoffset <= 0xffff { 856 return C_ANDCON 857 } 858 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 859 return C_UCON 860 } 861 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 862 return C_LCON 863 } 864 return C_DCON 865 } 866 867 if c.instoffset >= -0x8000 { 868 return C_ADDCON 869 } 870 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 871 return C_UCON 872 } 873 if isint32(c.instoffset) { 874 return C_LCON 875 } 876 return C_DCON 877 878 case obj.TYPE_BRANCH: 879 if a.Sym != nil && c.ctxt.Flag_dynlink { 880 return C_LBRAPIC 881 } 882 return C_SBRA 883 } 884 885 return C_GOK 886 } 887 888 func prasm(p *obj.Prog) { 889 fmt.Printf("%v\n", p) 890 } 891 892 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 893 a1 := int(p.Optab) 894 if a1 != 0 { 895 return &optab[a1-1] 896 } 897 a1 = int(p.From.Class) 898 if a1 == 0 { 899 a1 = c.aclass(&p.From) + 1 900 p.From.Class = int8(a1) 901 } 902 903 a1-- 904 a3 := C_NONE + 1 905 if p.GetFrom3() != nil { 906 a3 = int(p.GetFrom3().Class) 907 if a3 == 0 { 908 a3 = c.aclass(p.GetFrom3()) + 1 909 p.GetFrom3().Class = int8(a3) 910 } 911 } 912 913 a3-- 914 a4 := int(p.To.Class) 915 if a4 == 0 { 916 a4 = c.aclass(&p.To) + 1 917 p.To.Class = int8(a4) 918 } 919 920 a4-- 921 a2 := C_NONE 922 if p.Reg != 0 { 923 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 924 a2 = C_REG 925 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 926 a2 = C_VREG 927 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 928 a2 = C_VSREG 929 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 930 a2 = C_FREG 931 } 932 } 933 934 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 935 ops := oprange[p.As&obj.AMask] 936 c1 := &xcmp[a1] 937 c3 := &xcmp[a3] 938 c4 := &xcmp[a4] 939 for i := range ops { 940 op := &ops[i] 941 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 942 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 943 return op 944 } 945 } 946 947 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 948 prasm(p) 949 if ops == nil { 950 ops = optab 951 } 952 return &ops[0] 953 } 954 955 func cmp(a int, b int) bool { 956 if a == b { 957 return true 958 } 959 switch a { 960 case C_LCON: 961 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 962 return true 963 } 964 965 case C_ADDCON: 966 if b == C_ZCON || b == C_SCON { 967 return true 968 } 969 970 case C_ANDCON: 971 if b == C_ZCON || b == C_SCON { 972 return true 973 } 974 975 case C_SPR: 976 if b == C_LR || b == C_XER || b == C_CTR { 977 return true 978 } 979 980 case C_UCON: 981 if b == C_ZCON { 982 return true 983 } 984 985 case C_SCON: 986 if b == C_ZCON { 987 return true 988 } 989 990 case C_LACON: 991 if b == C_SACON { 992 return true 993 } 994 995 case C_LBRA: 996 if b == C_SBRA { 997 return true 998 } 999 1000 case C_LEXT: 1001 if b == C_SEXT { 1002 return true 1003 } 1004 1005 case C_LAUTO: 1006 if b == C_SAUTO { 1007 return true 1008 } 1009 1010 case C_REG: 1011 if b == C_ZCON { 1012 return r0iszero != 0 /*TypeKind(100016)*/ 1013 } 1014 1015 case C_LOREG: 1016 if b == C_ZOREG || b == C_SOREG { 1017 return true 1018 } 1019 1020 case C_SOREG: 1021 if b == C_ZOREG { 1022 return true 1023 } 1024 1025 case C_ANY: 1026 return true 1027 } 1028 1029 return false 1030 } 1031 1032 type ocmp []Optab 1033 1034 func (x ocmp) Len() int { 1035 return len(x) 1036 } 1037 1038 func (x ocmp) Swap(i, j int) { 1039 x[i], x[j] = x[j], x[i] 1040 } 1041 1042 func (x ocmp) Less(i, j int) bool { 1043 p1 := &x[i] 1044 p2 := &x[j] 1045 n := int(p1.as) - int(p2.as) 1046 if n != 0 { 1047 return n < 0 1048 } 1049 n = int(p1.a1) - int(p2.a1) 1050 if n != 0 { 1051 return n < 0 1052 } 1053 n = int(p1.a2) - int(p2.a2) 1054 if n != 0 { 1055 return n < 0 1056 } 1057 n = int(p1.a3) - int(p2.a3) 1058 if n != 0 { 1059 return n < 0 1060 } 1061 n = int(p1.a4) - int(p2.a4) 1062 if n != 0 { 1063 return n < 0 1064 } 1065 return false 1066 } 1067 func opset(a, b0 obj.As) { 1068 oprange[a&obj.AMask] = oprange[b0] 1069 } 1070 1071 func buildop(ctxt *obj.Link) { 1072 if oprange[AANDN&obj.AMask] != nil { 1073 // Already initialized; stop now. 1074 // This happens in the cmd/asm tests, 1075 // each of which re-initializes the arch. 1076 return 1077 } 1078 1079 var n int 1080 1081 for i := 0; i < C_NCLASS; i++ { 1082 for n = 0; n < C_NCLASS; n++ { 1083 if cmp(n, i) { 1084 xcmp[i][n] = true 1085 } 1086 } 1087 } 1088 for n = 0; optab[n].as != obj.AXXX; n++ { 1089 } 1090 sort.Sort(ocmp(optab[:n])) 1091 for i := 0; i < n; i++ { 1092 r := optab[i].as 1093 r0 := r & obj.AMask 1094 start := i 1095 for optab[i].as == r { 1096 i++ 1097 } 1098 oprange[r0] = optab[start:i] 1099 i-- 1100 1101 switch r { 1102 default: 1103 ctxt.Diag("unknown op in build: %v", r) 1104 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1105 1106 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1107 opset(ADCBI, r0) 1108 1109 opset(ADCBST, r0) 1110 opset(ADCBT, r0) 1111 opset(ADCBTST, r0) 1112 opset(ADCBZ, r0) 1113 opset(AICBI, r0) 1114 1115 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1116 opset(ASTWCCC, r0) 1117 opset(ASTBCCC, r0) 1118 1119 opset(ASTDCCC, r0) 1120 1121 case AREM: /* macro */ 1122 opset(AREMCC, r0) 1123 1124 opset(AREMV, r0) 1125 opset(AREMVCC, r0) 1126 1127 case AREMU: 1128 opset(AREMU, r0) 1129 opset(AREMUCC, r0) 1130 opset(AREMUV, r0) 1131 opset(AREMUVCC, r0) 1132 1133 case AREMD: 1134 opset(AREMDCC, r0) 1135 opset(AREMDV, r0) 1136 opset(AREMDVCC, r0) 1137 1138 case AREMDU: 1139 opset(AREMDU, r0) 1140 opset(AREMDUCC, r0) 1141 opset(AREMDUV, r0) 1142 opset(AREMDUVCC, r0) 1143 1144 case ADIVW: /* op Rb[,Ra],Rd */ 1145 opset(AMULHW, r0) 1146 1147 opset(AMULHWCC, r0) 1148 opset(AMULHWU, r0) 1149 opset(AMULHWUCC, r0) 1150 opset(AMULLWCC, r0) 1151 opset(AMULLWVCC, r0) 1152 opset(AMULLWV, r0) 1153 opset(ADIVWCC, r0) 1154 opset(ADIVWV, r0) 1155 opset(ADIVWVCC, r0) 1156 opset(ADIVWU, r0) 1157 opset(ADIVWUCC, r0) 1158 opset(ADIVWUV, r0) 1159 opset(ADIVWUVCC, r0) 1160 opset(AADDCC, r0) 1161 opset(AADDCV, r0) 1162 opset(AADDCVCC, r0) 1163 opset(AADDV, r0) 1164 opset(AADDVCC, r0) 1165 opset(AADDE, r0) 1166 opset(AADDECC, r0) 1167 opset(AADDEV, r0) 1168 opset(AADDEVCC, r0) 1169 opset(ACRAND, r0) 1170 opset(ACRANDN, r0) 1171 opset(ACREQV, r0) 1172 opset(ACRNAND, r0) 1173 opset(ACRNOR, r0) 1174 opset(ACROR, r0) 1175 opset(ACRORN, r0) 1176 opset(ACRXOR, r0) 1177 opset(AMULHD, r0) 1178 opset(AMULHDCC, r0) 1179 opset(AMULHDU, r0) 1180 opset(AMULHDUCC, r0) 1181 opset(AMULLD, r0) 1182 opset(AMULLDCC, r0) 1183 opset(AMULLDVCC, r0) 1184 opset(AMULLDV, r0) 1185 opset(ADIVD, r0) 1186 opset(ADIVDCC, r0) 1187 opset(ADIVDE, r0) 1188 opset(ADIVDEU, r0) 1189 opset(ADIVDECC, r0) 1190 opset(ADIVDEUCC, r0) 1191 opset(ADIVDVCC, r0) 1192 opset(ADIVDV, r0) 1193 opset(ADIVDU, r0) 1194 opset(ADIVDUCC, r0) 1195 opset(ADIVDUVCC, r0) 1196 opset(ADIVDUCC, r0) 1197 1198 case APOPCNTD: 1199 opset(APOPCNTW, r0) 1200 opset(APOPCNTB, r0) 1201 1202 case ACOPY: /* copy, paste. */ 1203 opset(APASTECC, r0) 1204 1205 case AMADDHD: /* maddhd, maddhdu, maddld */ 1206 opset(AMADDHDU, r0) 1207 opset(AMADDLD, r0) 1208 1209 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1210 opset(AMOVH, r0) 1211 opset(AMOVHZ, r0) 1212 1213 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1214 opset(AMOVHU, r0) 1215 1216 opset(AMOVHZU, r0) 1217 opset(AMOVWU, r0) 1218 opset(AMOVWZU, r0) 1219 opset(AMOVDU, r0) 1220 opset(AMOVMW, r0) 1221 1222 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1223 opset(ALVEBX, r0) 1224 opset(ALVEHX, r0) 1225 opset(ALVEWX, r0) 1226 opset(ALVX, r0) 1227 opset(ALVXL, r0) 1228 opset(ALVSL, r0) 1229 opset(ALVSR, r0) 1230 1231 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1232 opset(ASTVEBX, r0) 1233 opset(ASTVEHX, r0) 1234 opset(ASTVEWX, r0) 1235 opset(ASTVX, r0) 1236 opset(ASTVXL, r0) 1237 1238 case AVAND: /* vand, vandc, vnand */ 1239 opset(AVAND, r0) 1240 opset(AVANDC, r0) 1241 opset(AVNAND, r0) 1242 1243 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1244 opset(AVOR, r0) 1245 opset(AVORC, r0) 1246 opset(AVXOR, r0) 1247 opset(AVNOR, r0) 1248 opset(AVEQV, r0) 1249 1250 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1251 opset(AVADDUBM, r0) 1252 opset(AVADDUHM, r0) 1253 opset(AVADDUWM, r0) 1254 opset(AVADDUDM, r0) 1255 opset(AVADDUQM, r0) 1256 1257 case AVADDCU: /* vaddcuq, vaddcuw */ 1258 opset(AVADDCUQ, r0) 1259 opset(AVADDCUW, r0) 1260 1261 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1262 opset(AVADDUBS, r0) 1263 opset(AVADDUHS, r0) 1264 opset(AVADDUWS, r0) 1265 1266 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1267 opset(AVADDSBS, r0) 1268 opset(AVADDSHS, r0) 1269 opset(AVADDSWS, r0) 1270 1271 case AVADDE: /* vaddeuqm, vaddecuq */ 1272 opset(AVADDEUQM, r0) 1273 opset(AVADDECUQ, r0) 1274 1275 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1276 opset(AVSUBUBM, r0) 1277 opset(AVSUBUHM, r0) 1278 opset(AVSUBUWM, r0) 1279 opset(AVSUBUDM, r0) 1280 opset(AVSUBUQM, r0) 1281 1282 case AVSUBCU: /* vsubcuq, vsubcuw */ 1283 opset(AVSUBCUQ, r0) 1284 opset(AVSUBCUW, r0) 1285 1286 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1287 opset(AVSUBUBS, r0) 1288 opset(AVSUBUHS, r0) 1289 opset(AVSUBUWS, r0) 1290 1291 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1292 opset(AVSUBSBS, r0) 1293 opset(AVSUBSHS, r0) 1294 opset(AVSUBSWS, r0) 1295 1296 case AVSUBE: /* vsubeuqm, vsubecuq */ 1297 opset(AVSUBEUQM, r0) 1298 opset(AVSUBECUQ, r0) 1299 1300 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1301 opset(AVPMSUMB, r0) 1302 opset(AVPMSUMH, r0) 1303 opset(AVPMSUMW, r0) 1304 opset(AVPMSUMD, r0) 1305 1306 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1307 opset(AVRLB, r0) 1308 opset(AVRLH, r0) 1309 opset(AVRLW, r0) 1310 opset(AVRLD, r0) 1311 1312 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1313 opset(AVSLB, r0) 1314 opset(AVSLH, r0) 1315 opset(AVSLW, r0) 1316 opset(AVSL, r0) 1317 opset(AVSLO, r0) 1318 opset(AVSRB, r0) 1319 opset(AVSRH, r0) 1320 opset(AVSRW, r0) 1321 opset(AVSR, r0) 1322 opset(AVSRO, r0) 1323 opset(AVSLD, r0) 1324 opset(AVSRD, r0) 1325 1326 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1327 opset(AVSRAB, r0) 1328 opset(AVSRAH, r0) 1329 opset(AVSRAW, r0) 1330 opset(AVSRAD, r0) 1331 1332 case AVSOI: /* vsldoi */ 1333 opset(AVSLDOI, r0) 1334 1335 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1336 opset(AVCLZB, r0) 1337 opset(AVCLZH, r0) 1338 opset(AVCLZW, r0) 1339 opset(AVCLZD, r0) 1340 1341 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1342 opset(AVPOPCNTB, r0) 1343 opset(AVPOPCNTH, r0) 1344 opset(AVPOPCNTW, r0) 1345 opset(AVPOPCNTD, r0) 1346 1347 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1348 opset(AVCMPEQUB, r0) 1349 opset(AVCMPEQUBCC, r0) 1350 opset(AVCMPEQUH, r0) 1351 opset(AVCMPEQUHCC, r0) 1352 opset(AVCMPEQUW, r0) 1353 opset(AVCMPEQUWCC, r0) 1354 opset(AVCMPEQUD, r0) 1355 opset(AVCMPEQUDCC, r0) 1356 1357 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1358 opset(AVCMPGTUB, r0) 1359 opset(AVCMPGTUBCC, r0) 1360 opset(AVCMPGTUH, r0) 1361 opset(AVCMPGTUHCC, r0) 1362 opset(AVCMPGTUW, r0) 1363 opset(AVCMPGTUWCC, r0) 1364 opset(AVCMPGTUD, r0) 1365 opset(AVCMPGTUDCC, r0) 1366 opset(AVCMPGTSB, r0) 1367 opset(AVCMPGTSBCC, r0) 1368 opset(AVCMPGTSH, r0) 1369 opset(AVCMPGTSHCC, r0) 1370 opset(AVCMPGTSW, r0) 1371 opset(AVCMPGTSWCC, r0) 1372 opset(AVCMPGTSD, r0) 1373 opset(AVCMPGTSDCC, r0) 1374 1375 case AVCMPNEZB: /* vcmpnezb[.] */ 1376 opset(AVCMPNEZBCC, r0) 1377 1378 case AVPERM: /* vperm */ 1379 opset(AVPERM, r0) 1380 1381 case AVSEL: /* vsel */ 1382 opset(AVSEL, r0) 1383 1384 case AVSPLT: /* vspltb, vsplth, vspltw */ 1385 opset(AVSPLTB, r0) 1386 opset(AVSPLTH, r0) 1387 opset(AVSPLTW, r0) 1388 1389 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1390 opset(AVSPLTISB, r0) 1391 opset(AVSPLTISH, r0) 1392 opset(AVSPLTISW, r0) 1393 1394 case AVCIPH: /* vcipher, vcipherlast */ 1395 opset(AVCIPHER, r0) 1396 opset(AVCIPHERLAST, r0) 1397 1398 case AVNCIPH: /* vncipher, vncipherlast */ 1399 opset(AVNCIPHER, r0) 1400 opset(AVNCIPHERLAST, r0) 1401 1402 case AVSBOX: /* vsbox */ 1403 opset(AVSBOX, r0) 1404 1405 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1406 opset(AVSHASIGMAW, r0) 1407 opset(AVSHASIGMAD, r0) 1408 1409 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1410 opset(ALXVD2X, r0) 1411 opset(ALXVDSX, r0) 1412 opset(ALXVW4X, r0) 1413 1414 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1415 opset(ASTXVD2X, r0) 1416 opset(ASTXVW4X, r0) 1417 1418 case ALXS: /* lxsdx */ 1419 opset(ALXSDX, r0) 1420 1421 case ASTXS: /* stxsdx */ 1422 opset(ASTXSDX, r0) 1423 1424 case ALXSI: /* lxsiwax, lxsiwzx */ 1425 opset(ALXSIWAX, r0) 1426 opset(ALXSIWZX, r0) 1427 1428 case ASTXSI: /* stxsiwx */ 1429 opset(ASTXSIWX, r0) 1430 1431 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */ 1432 opset(AMFVSRD, r0) 1433 opset(AMFFPRD, r0) 1434 opset(AMFVRD, r0) 1435 opset(AMFVSRWZ, r0) 1436 opset(AMFVSRLD, r0) 1437 1438 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */ 1439 opset(AMTVSRD, r0) 1440 opset(AMTFPRD, r0) 1441 opset(AMTVRD, r0) 1442 opset(AMTVSRWA, r0) 1443 opset(AMTVSRWZ, r0) 1444 opset(AMTVSRDD, r0) 1445 opset(AMTVSRWS, r0) 1446 1447 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1448 opset(AXXLANDQ, r0) 1449 opset(AXXLANDC, r0) 1450 opset(AXXLEQV, r0) 1451 opset(AXXLNAND, r0) 1452 1453 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1454 opset(AXXLORC, r0) 1455 opset(AXXLNOR, r0) 1456 opset(AXXLORQ, r0) 1457 opset(AXXLXOR, r0) 1458 1459 case AXXSEL: /* xxsel */ 1460 opset(AXXSEL, r0) 1461 1462 case AXXMRG: /* xxmrghw, xxmrglw */ 1463 opset(AXXMRGHW, r0) 1464 opset(AXXMRGLW, r0) 1465 1466 case AXXSPLT: /* xxspltw */ 1467 opset(AXXSPLTW, r0) 1468 1469 case AXXPERM: /* xxpermdi */ 1470 opset(AXXPERMDI, r0) 1471 1472 case AXXSI: /* xxsldwi */ 1473 opset(AXXSLDWI, r0) 1474 1475 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1476 opset(AXSCVDPSP, r0) 1477 opset(AXSCVSPDP, r0) 1478 opset(AXSCVDPSPN, r0) 1479 opset(AXSCVSPDPN, r0) 1480 1481 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1482 opset(AXVCVDPSP, r0) 1483 opset(AXVCVSPDP, r0) 1484 1485 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1486 opset(AXSCVDPSXDS, r0) 1487 opset(AXSCVDPSXWS, r0) 1488 opset(AXSCVDPUXDS, r0) 1489 opset(AXSCVDPUXWS, r0) 1490 1491 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1492 opset(AXSCVSXDDP, r0) 1493 opset(AXSCVUXDDP, r0) 1494 opset(AXSCVSXDSP, r0) 1495 opset(AXSCVUXDSP, r0) 1496 1497 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1498 opset(AXVCVDPSXDS, r0) 1499 opset(AXVCVDPSXWS, r0) 1500 opset(AXVCVDPUXDS, r0) 1501 opset(AXVCVDPUXWS, r0) 1502 opset(AXVCVSPSXDS, r0) 1503 opset(AXVCVSPSXWS, r0) 1504 opset(AXVCVSPUXDS, r0) 1505 opset(AXVCVSPUXWS, r0) 1506 1507 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1508 opset(AXVCVSXDDP, r0) 1509 opset(AXVCVSXWDP, r0) 1510 opset(AXVCVUXDDP, r0) 1511 opset(AXVCVUXWDP, r0) 1512 opset(AXVCVSXDSP, r0) 1513 opset(AXVCVSXWSP, r0) 1514 opset(AXVCVUXDSP, r0) 1515 opset(AXVCVUXWSP, r0) 1516 1517 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1518 opset(AANDN, r0) 1519 1520 opset(AANDNCC, r0) 1521 opset(AEQV, r0) 1522 opset(AEQVCC, r0) 1523 opset(ANAND, r0) 1524 opset(ANANDCC, r0) 1525 opset(ANOR, r0) 1526 opset(ANORCC, r0) 1527 opset(AORCC, r0) 1528 opset(AORN, r0) 1529 opset(AORNCC, r0) 1530 opset(AXORCC, r0) 1531 1532 case AADDME: /* op Ra, Rd */ 1533 opset(AADDMECC, r0) 1534 1535 opset(AADDMEV, r0) 1536 opset(AADDMEVCC, r0) 1537 opset(AADDZE, r0) 1538 opset(AADDZECC, r0) 1539 opset(AADDZEV, r0) 1540 opset(AADDZEVCC, r0) 1541 opset(ASUBME, r0) 1542 opset(ASUBMECC, r0) 1543 opset(ASUBMEV, r0) 1544 opset(ASUBMEVCC, r0) 1545 opset(ASUBZE, r0) 1546 opset(ASUBZECC, r0) 1547 opset(ASUBZEV, r0) 1548 opset(ASUBZEVCC, r0) 1549 1550 case AADDC: 1551 opset(AADDCCC, r0) 1552 1553 case ABEQ: 1554 opset(ABGE, r0) 1555 opset(ABGT, r0) 1556 opset(ABLE, r0) 1557 opset(ABLT, r0) 1558 opset(ABNE, r0) 1559 opset(ABVC, r0) 1560 opset(ABVS, r0) 1561 1562 case ABR: 1563 opset(ABL, r0) 1564 1565 case ABC: 1566 opset(ABCL, r0) 1567 1568 case AEXTSB: /* op Rs, Ra */ 1569 opset(AEXTSBCC, r0) 1570 1571 opset(AEXTSH, r0) 1572 opset(AEXTSHCC, r0) 1573 opset(ACNTLZW, r0) 1574 opset(ACNTLZWCC, r0) 1575 opset(ACNTLZD, r0) 1576 opset(AEXTSW, r0) 1577 opset(AEXTSWCC, r0) 1578 opset(ACNTLZDCC, r0) 1579 1580 case AFABS: /* fop [s,]d */ 1581 opset(AFABSCC, r0) 1582 1583 opset(AFNABS, r0) 1584 opset(AFNABSCC, r0) 1585 opset(AFNEG, r0) 1586 opset(AFNEGCC, r0) 1587 opset(AFRSP, r0) 1588 opset(AFRSPCC, r0) 1589 opset(AFCTIW, r0) 1590 opset(AFCTIWCC, r0) 1591 opset(AFCTIWZ, r0) 1592 opset(AFCTIWZCC, r0) 1593 opset(AFCTID, r0) 1594 opset(AFCTIDCC, r0) 1595 opset(AFCTIDZ, r0) 1596 opset(AFCTIDZCC, r0) 1597 opset(AFCFID, r0) 1598 opset(AFCFIDCC, r0) 1599 opset(AFCFIDU, r0) 1600 opset(AFCFIDUCC, r0) 1601 opset(AFCFIDS, r0) 1602 opset(AFCFIDSCC, r0) 1603 opset(AFRES, r0) 1604 opset(AFRESCC, r0) 1605 opset(AFRIM, r0) 1606 opset(AFRIMCC, r0) 1607 opset(AFRIP, r0) 1608 opset(AFRIPCC, r0) 1609 opset(AFRIZ, r0) 1610 opset(AFRIZCC, r0) 1611 opset(AFRSQRTE, r0) 1612 opset(AFRSQRTECC, r0) 1613 opset(AFSQRT, r0) 1614 opset(AFSQRTCC, r0) 1615 opset(AFSQRTS, r0) 1616 opset(AFSQRTSCC, r0) 1617 1618 case AFADD: 1619 opset(AFADDS, r0) 1620 opset(AFADDCC, r0) 1621 opset(AFADDSCC, r0) 1622 opset(AFDIV, r0) 1623 opset(AFDIVS, r0) 1624 opset(AFDIVCC, r0) 1625 opset(AFDIVSCC, r0) 1626 opset(AFSUB, r0) 1627 opset(AFSUBS, r0) 1628 opset(AFSUBCC, r0) 1629 opset(AFSUBSCC, r0) 1630 1631 case AFMADD: 1632 opset(AFMADDCC, r0) 1633 opset(AFMADDS, r0) 1634 opset(AFMADDSCC, r0) 1635 opset(AFMSUB, r0) 1636 opset(AFMSUBCC, r0) 1637 opset(AFMSUBS, r0) 1638 opset(AFMSUBSCC, r0) 1639 opset(AFNMADD, r0) 1640 opset(AFNMADDCC, r0) 1641 opset(AFNMADDS, r0) 1642 opset(AFNMADDSCC, r0) 1643 opset(AFNMSUB, r0) 1644 opset(AFNMSUBCC, r0) 1645 opset(AFNMSUBS, r0) 1646 opset(AFNMSUBSCC, r0) 1647 opset(AFSEL, r0) 1648 opset(AFSELCC, r0) 1649 1650 case AFMUL: 1651 opset(AFMULS, r0) 1652 opset(AFMULCC, r0) 1653 opset(AFMULSCC, r0) 1654 1655 case AFCMPO: 1656 opset(AFCMPU, r0) 1657 1658 case AISEL: 1659 opset(AISEL, r0) 1660 1661 case AMTFSB0: 1662 opset(AMTFSB0CC, r0) 1663 opset(AMTFSB1, r0) 1664 opset(AMTFSB1CC, r0) 1665 1666 case ANEG: /* op [Ra,] Rd */ 1667 opset(ANEGCC, r0) 1668 1669 opset(ANEGV, r0) 1670 opset(ANEGVCC, r0) 1671 1672 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1673 opset(AXOR, r0) 1674 1675 case ASLW: 1676 opset(ASLWCC, r0) 1677 opset(ASRW, r0) 1678 opset(ASRWCC, r0) 1679 opset(AROTLW, r0) 1680 1681 case ASLD: 1682 opset(ASLDCC, r0) 1683 opset(ASRD, r0) 1684 opset(ASRDCC, r0) 1685 opset(AROTL, r0) 1686 1687 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1688 opset(ASRAWCC, r0) 1689 1690 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1691 opset(ASRADCC, r0) 1692 1693 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1694 opset(ASUB, r0) 1695 1696 opset(ASUBCC, r0) 1697 opset(ASUBV, r0) 1698 opset(ASUBVCC, r0) 1699 opset(ASUBCCC, r0) 1700 opset(ASUBCV, r0) 1701 opset(ASUBCVCC, r0) 1702 opset(ASUBE, r0) 1703 opset(ASUBECC, r0) 1704 opset(ASUBEV, r0) 1705 opset(ASUBEVCC, r0) 1706 1707 case ASYNC: 1708 opset(AISYNC, r0) 1709 opset(ALWSYNC, r0) 1710 opset(APTESYNC, r0) 1711 opset(ATLBSYNC, r0) 1712 1713 case ARLWMI: 1714 opset(ARLWMICC, r0) 1715 opset(ARLWNM, r0) 1716 opset(ARLWNMCC, r0) 1717 1718 case ARLDMI: 1719 opset(ARLDMICC, r0) 1720 opset(ARLDIMI, r0) 1721 opset(ARLDIMICC, r0) 1722 1723 case ARLDC: 1724 opset(ARLDCCC, r0) 1725 1726 case ARLDCL: 1727 opset(ARLDCR, r0) 1728 opset(ARLDCLCC, r0) 1729 opset(ARLDCRCC, r0) 1730 1731 case ARLDICL: 1732 opset(ARLDICLCC, r0) 1733 opset(ARLDICR, r0) 1734 opset(ARLDICRCC, r0) 1735 1736 case AFMOVD: 1737 opset(AFMOVDCC, r0) 1738 opset(AFMOVDU, r0) 1739 opset(AFMOVS, r0) 1740 opset(AFMOVSU, r0) 1741 1742 case AECIWX: 1743 opset(ALBAR, r0) 1744 opset(ALWAR, r0) 1745 opset(ALDAR, r0) 1746 1747 case ASYSCALL: /* just the op; flow of control */ 1748 opset(ARFI, r0) 1749 1750 opset(ARFCI, r0) 1751 opset(ARFID, r0) 1752 opset(AHRFID, r0) 1753 1754 case AMOVHBR: 1755 opset(AMOVWBR, r0) 1756 opset(AMOVDBR, r0) 1757 1758 case ASLBMFEE: 1759 opset(ASLBMFEV, r0) 1760 1761 case ATW: 1762 opset(ATD, r0) 1763 1764 case ATLBIE: 1765 opset(ASLBIE, r0) 1766 opset(ATLBIEL, r0) 1767 1768 case AEIEIO: 1769 opset(ASLBIA, r0) 1770 1771 case ACMP: 1772 opset(ACMPW, r0) 1773 1774 case ACMPU: 1775 opset(ACMPWU, r0) 1776 1777 case ACMPB: 1778 opset(ACMPB, r0) 1779 1780 case AFTDIV: 1781 opset(AFTDIV, r0) 1782 1783 case AFTSQRT: 1784 opset(AFTSQRT, r0) 1785 1786 case AADD, 1787 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1788 AFMOVSX, 1789 AFMOVSZ, 1790 ALSW, 1791 AMOVW, 1792 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1793 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1794 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1795 AMOVB, /* macro: move byte with sign extension */ 1796 AMOVBU, /* macro: move byte with sign extension & update */ 1797 AMOVFL, 1798 AMULLW, 1799 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1800 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1801 ASTSW, 1802 ASLBMTE, 1803 AWORD, 1804 ADWORD, 1805 ADARN, 1806 ALDMX, 1807 AVMSUMUDM, 1808 AADDEX, 1809 ACMPEQB, 1810 obj.ANOP, 1811 obj.ATEXT, 1812 obj.AUNDEF, 1813 obj.AFUNCDATA, 1814 obj.APCDATA, 1815 obj.ADUFFZERO, 1816 obj.ADUFFCOPY: 1817 break 1818 } 1819 } 1820 } 1821 1822 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1823 return o<<26 | xo<<1 | oe<<11 1824 } 1825 1826 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1827 return o<<26 | xo<<2 | oe<<11 1828 } 1829 1830 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1831 return o<<26 | xo<<3 | oe<<11 1832 } 1833 1834 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1835 return o<<26 | xo<<4 | oe<<11 1836 } 1837 1838 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1839 return o<<26 | xo | oe<<11 | rc&1 1840 } 1841 1842 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1843 return o<<26 | xo | oe<<11 | (rc&1)<<10 1844 } 1845 1846 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1847 return o<<26 | xo<<1 | oe<<10 | rc&1 1848 } 1849 1850 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1851 return OPVCC(o, xo, 0, rc) 1852 } 1853 1854 func OP(o uint32, xo uint32) uint32 { 1855 return OPVCC(o, xo, 0, 0) 1856 } 1857 1858 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1859 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1860 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1861 } 1862 1863 /* VX-form 2-register operands, r/none/r */ 1864 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1865 return op | (d&31)<<21 | (a&31)<<11 1866 } 1867 1868 /* VA-form 4-register operands */ 1869 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1870 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1871 } 1872 1873 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1874 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1875 } 1876 1877 /* VX-form 2-register + UIM operands */ 1878 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1879 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1880 } 1881 1882 /* VX-form 2-register + ST + SIX operands */ 1883 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1884 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1885 } 1886 1887 /* VA-form 3-register + SHB operands */ 1888 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1889 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1890 } 1891 1892 /* VX-form 1-register + SIM operands */ 1893 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1894 return op | (d&31)<<21 | (simm&31)<<16 1895 } 1896 1897 /* XX1-form 3-register operands, 1 VSR operand */ 1898 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1899 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1900 /* between 0-63, so we can properly set the rightmost bits. */ 1901 r := d - REG_VS0 1902 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1903 } 1904 1905 /* XX2-form 3-register operands, 2 VSR operands */ 1906 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1907 xt := d - REG_VS0 1908 xb := b - REG_VS0 1909 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1910 } 1911 1912 /* XX3-form 3 VSR operands */ 1913 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1914 xt := d - REG_VS0 1915 xa := a - REG_VS0 1916 xb := b - REG_VS0 1917 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1918 } 1919 1920 /* XX3-form 3 VSR operands + immediate */ 1921 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1922 xt := d - REG_VS0 1923 xa := a - REG_VS0 1924 xb := b - REG_VS0 1925 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1926 } 1927 1928 /* XX4-form, 4 VSR operands */ 1929 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1930 xt := d - REG_VS0 1931 xa := a - REG_VS0 1932 xb := b - REG_VS0 1933 xc := c - REG_VS0 1934 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1935 } 1936 1937 /* Z23-form, 3-register operands + CY field */ 1938 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1939 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7 1940 } 1941 1942 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1943 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1944 } 1945 1946 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1947 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1948 } 1949 1950 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1951 return op | li&0x03FFFFFC | aa<<1 1952 } 1953 1954 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1955 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1956 } 1957 1958 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1959 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1960 } 1961 1962 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1963 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1964 } 1965 1966 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1967 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1968 } 1969 1970 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1971 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1972 } 1973 1974 const ( 1975 /* each rhs is OPVCC(_, _, _, _) */ 1976 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1977 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1978 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1979 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1980 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1981 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1982 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1983 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1984 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1985 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1986 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1987 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1988 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1989 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1990 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1991 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1992 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1993 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1994 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1995 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1996 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1997 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1998 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1999 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 2000 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 2001 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 2002 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 2003 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 2004 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 2005 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 2006 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 2007 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 2008 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 2009 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 2010 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 2011 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 2012 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 2013 ) 2014 2015 func oclass(a *obj.Addr) int { 2016 return int(a.Class) - 1 2017 } 2018 2019 const ( 2020 D_FORM = iota 2021 DS_FORM 2022 ) 2023 2024 // This function determines when a non-indexed load or store is D or 2025 // DS form for use in finding the size of the offset field in the instruction. 2026 // The size is needed when setting the offset value in the instruction 2027 // and when generating relocation for that field. 2028 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 2029 // loads and stores with an offset field are D form. This function should 2030 // only be called with the same opcodes as are handled by opstore and opload. 2031 func (c *ctxt9) opform(insn uint32) int { 2032 switch insn { 2033 default: 2034 c.ctxt.Diag("bad insn in loadform: %x", insn) 2035 case OPVCC(58, 0, 0, 0), // ld 2036 OPVCC(58, 0, 0, 1), // ldu 2037 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2038 OPVCC(62, 0, 0, 0), // std 2039 OPVCC(62, 0, 0, 1): //stdu 2040 return DS_FORM 2041 case OP_ADDI, // add 2042 OPVCC(32, 0, 0, 0), // lwz 2043 OPVCC(33, 0, 0, 0), // lwzu 2044 OPVCC(34, 0, 0, 0), // lbz 2045 OPVCC(35, 0, 0, 0), // lbzu 2046 OPVCC(40, 0, 0, 0), // lhz 2047 OPVCC(41, 0, 0, 0), // lhzu 2048 OPVCC(42, 0, 0, 0), // lha 2049 OPVCC(43, 0, 0, 0), // lhau 2050 OPVCC(46, 0, 0, 0), // lmw 2051 OPVCC(48, 0, 0, 0), // lfs 2052 OPVCC(49, 0, 0, 0), // lfsu 2053 OPVCC(50, 0, 0, 0), // lfd 2054 OPVCC(51, 0, 0, 0), // lfdu 2055 OPVCC(36, 0, 0, 0), // stw 2056 OPVCC(37, 0, 0, 0), // stwu 2057 OPVCC(38, 0, 0, 0), // stb 2058 OPVCC(39, 0, 0, 0), // stbu 2059 OPVCC(44, 0, 0, 0), // sth 2060 OPVCC(45, 0, 0, 0), // sthu 2061 OPVCC(47, 0, 0, 0), // stmw 2062 OPVCC(52, 0, 0, 0), // stfs 2063 OPVCC(53, 0, 0, 0), // stfsu 2064 OPVCC(54, 0, 0, 0), // stfd 2065 OPVCC(55, 0, 0, 0): // stfdu 2066 return D_FORM 2067 } 2068 return 0 2069 } 2070 2071 // Encode instructions and create relocation for accessing s+d according to the 2072 // instruction op with source or destination (as appropriate) register reg. 2073 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2074 var base uint32 2075 form := c.opform(op) 2076 if c.ctxt.Flag_shared { 2077 base = REG_R2 2078 } else { 2079 base = REG_R0 2080 } 2081 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2082 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2083 rel := obj.Addrel(c.cursym) 2084 rel.Off = int32(c.pc) 2085 rel.Siz = 8 2086 rel.Sym = s 2087 rel.Add = d 2088 if c.ctxt.Flag_shared { 2089 switch form { 2090 case D_FORM: 2091 rel.Type = objabi.R_ADDRPOWER_TOCREL 2092 case DS_FORM: 2093 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2094 } 2095 2096 } else { 2097 switch form { 2098 case D_FORM: 2099 rel.Type = objabi.R_ADDRPOWER 2100 case DS_FORM: 2101 rel.Type = objabi.R_ADDRPOWER_DS 2102 } 2103 } 2104 return 2105 } 2106 2107 /* 2108 * 32-bit masks 2109 */ 2110 func getmask(m []byte, v uint32) bool { 2111 m[1] = 0 2112 m[0] = m[1] 2113 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2114 if getmask(m, ^v) { 2115 i := int(m[0]) 2116 m[0] = m[1] + 1 2117 m[1] = byte(i - 1) 2118 return true 2119 } 2120 2121 return false 2122 } 2123 2124 for i := 0; i < 32; i++ { 2125 if v&(1<<uint(31-i)) != 0 { 2126 m[0] = byte(i) 2127 for { 2128 m[1] = byte(i) 2129 i++ 2130 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2131 break 2132 } 2133 } 2134 2135 for ; i < 32; i++ { 2136 if v&(1<<uint(31-i)) != 0 { 2137 return false 2138 } 2139 } 2140 return true 2141 } 2142 } 2143 2144 return false 2145 } 2146 2147 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2148 if !getmask(m, v) { 2149 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2150 } 2151 } 2152 2153 /* 2154 * 64-bit masks (rldic etc) 2155 */ 2156 func getmask64(m []byte, v uint64) bool { 2157 m[1] = 0 2158 m[0] = m[1] 2159 for i := 0; i < 64; i++ { 2160 if v&(uint64(1)<<uint(63-i)) != 0 { 2161 m[0] = byte(i) 2162 for { 2163 m[1] = byte(i) 2164 i++ 2165 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2166 break 2167 } 2168 } 2169 2170 for ; i < 64; i++ { 2171 if v&(uint64(1)<<uint(63-i)) != 0 { 2172 return false 2173 } 2174 } 2175 return true 2176 } 2177 } 2178 2179 return false 2180 } 2181 2182 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2183 if !getmask64(m, v) { 2184 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2185 } 2186 } 2187 2188 func loadu32(r int, d int64) uint32 { 2189 v := int32(d >> 16) 2190 if isuint32(uint64(d)) { 2191 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2192 } 2193 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2194 } 2195 2196 func high16adjusted(d int32) uint16 { 2197 if d&0x8000 != 0 { 2198 return uint16((d >> 16) + 1) 2199 } 2200 return uint16(d >> 16) 2201 } 2202 2203 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2204 o1 := uint32(0) 2205 o2 := uint32(0) 2206 o3 := uint32(0) 2207 o4 := uint32(0) 2208 o5 := uint32(0) 2209 2210 //print("%v => case %d\n", p, o->type); 2211 switch o.type_ { 2212 default: 2213 c.ctxt.Diag("unknown type %d", o.type_) 2214 prasm(p) 2215 2216 case 0: /* pseudo ops */ 2217 break 2218 2219 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2220 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2221 v := c.regoff(&p.From) 2222 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2223 //nerrors--; 2224 c.ctxt.Diag("literal operation on R0\n%v", p) 2225 } 2226 2227 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2228 break 2229 } 2230 2231 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2232 2233 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2234 r := int(p.Reg) 2235 2236 if r == 0 { 2237 r = int(p.To.Reg) 2238 } 2239 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2240 2241 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2242 d := c.vregoff(&p.From) 2243 2244 v := int32(d) 2245 r := int(p.From.Reg) 2246 if r == 0 { 2247 r = int(o.param) 2248 } 2249 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2250 c.ctxt.Diag("literal operation on R0\n%v", p) 2251 } 2252 a := OP_ADDI 2253 if o.a1 == C_UCON { 2254 if d&0xffff != 0 { 2255 log.Fatalf("invalid handling of %v", p) 2256 } 2257 v >>= 16 2258 if r == REGZERO && isuint32(uint64(d)) { 2259 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2260 break 2261 } 2262 2263 a = OP_ADDIS 2264 } else { 2265 if int64(int16(d)) != d { 2266 log.Fatalf("invalid handling of %v", p) 2267 } 2268 } 2269 2270 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2271 2272 case 4: /* add/mul $scon,[r1],r2 */ 2273 v := c.regoff(&p.From) 2274 2275 r := int(p.Reg) 2276 if r == 0 { 2277 r = int(p.To.Reg) 2278 } 2279 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2280 c.ctxt.Diag("literal operation on R0\n%v", p) 2281 } 2282 if int32(int16(v)) != v { 2283 log.Fatalf("mishandled instruction %v", p) 2284 } 2285 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2286 2287 case 5: /* syscall */ 2288 o1 = c.oprrr(p.As) 2289 2290 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2291 r := int(p.Reg) 2292 2293 if r == 0 { 2294 r = int(p.To.Reg) 2295 } 2296 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2297 switch p.As { 2298 case AROTL: 2299 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2300 case AROTLW: 2301 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2302 default: 2303 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2304 } 2305 2306 case 7: /* mov r, soreg ==> stw o(r) */ 2307 r := int(p.To.Reg) 2308 2309 if r == 0 { 2310 r = int(o.param) 2311 } 2312 v := c.regoff(&p.To) 2313 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2314 if v != 0 { 2315 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2316 } 2317 if c.ctxt.Flag_shared && r == REG_R13 { 2318 rel := obj.Addrel(c.cursym) 2319 rel.Off = int32(c.pc) 2320 rel.Siz = 4 2321 // This (and the matching part in the load case 2322 // below) are the only places in the ppc64 toolchain 2323 // that knows the name of the tls variable. Possibly 2324 // we could add some assembly syntax so that the name 2325 // of the variable does not have to be assumed. 2326 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2327 rel.Type = objabi.R_POWER_TLS 2328 } 2329 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2330 } else { 2331 if int32(int16(v)) != v { 2332 log.Fatalf("mishandled instruction %v", p) 2333 } 2334 // Offsets in DS form stores must be a multiple of 4 2335 inst := c.opstore(p.As) 2336 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2337 log.Fatalf("invalid offset for DS form load/store %v", p) 2338 } 2339 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2340 } 2341 2342 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2343 r := int(p.From.Reg) 2344 2345 if r == 0 { 2346 r = int(o.param) 2347 } 2348 v := c.regoff(&p.From) 2349 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2350 if v != 0 { 2351 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2352 } 2353 if c.ctxt.Flag_shared && r == REG_R13 { 2354 rel := obj.Addrel(c.cursym) 2355 rel.Off = int32(c.pc) 2356 rel.Siz = 4 2357 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2358 rel.Type = objabi.R_POWER_TLS 2359 } 2360 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2361 } else { 2362 if int32(int16(v)) != v { 2363 log.Fatalf("mishandled instruction %v", p) 2364 } 2365 // Offsets in DS form loads must be a multiple of 4 2366 inst := c.opload(p.As) 2367 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2368 log.Fatalf("invalid offset for DS form load/store %v", p) 2369 } 2370 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2371 } 2372 2373 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2374 r := int(p.From.Reg) 2375 2376 if r == 0 { 2377 r = int(o.param) 2378 } 2379 v := c.regoff(&p.From) 2380 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2381 if v != 0 { 2382 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2383 } 2384 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2385 } else { 2386 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2387 } 2388 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2389 2390 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2391 r := int(p.Reg) 2392 2393 if r == 0 { 2394 r = int(p.To.Reg) 2395 } 2396 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2397 2398 case 11: /* br/bl lbra */ 2399 v := int32(0) 2400 2401 if p.Pcond != nil { 2402 v = int32(p.Pcond.Pc - p.Pc) 2403 if v&03 != 0 { 2404 c.ctxt.Diag("odd branch target address\n%v", p) 2405 v &^= 03 2406 } 2407 2408 if v < -(1<<25) || v >= 1<<24 { 2409 c.ctxt.Diag("branch too far\n%v", p) 2410 } 2411 } 2412 2413 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2414 if p.To.Sym != nil { 2415 rel := obj.Addrel(c.cursym) 2416 rel.Off = int32(c.pc) 2417 rel.Siz = 4 2418 rel.Sym = p.To.Sym 2419 v += int32(p.To.Offset) 2420 if v&03 != 0 { 2421 c.ctxt.Diag("odd branch target address\n%v", p) 2422 v &^= 03 2423 } 2424 2425 rel.Add = int64(v) 2426 rel.Type = objabi.R_CALLPOWER 2427 } 2428 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2429 2430 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2431 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2432 v := c.regoff(&p.From) 2433 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2434 c.ctxt.Diag("literal operation on R0\n%v", p) 2435 } 2436 2437 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2438 break 2439 } 2440 2441 if p.As == AMOVW { 2442 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2443 } else { 2444 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2445 } 2446 2447 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2448 if p.As == AMOVBZ { 2449 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2450 } else if p.As == AMOVH { 2451 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2452 } else if p.As == AMOVHZ { 2453 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2454 } else if p.As == AMOVWZ { 2455 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2456 } else { 2457 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2458 } 2459 2460 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2461 r := int(p.Reg) 2462 2463 if r == 0 { 2464 r = int(p.To.Reg) 2465 } 2466 d := c.vregoff(p.GetFrom3()) 2467 var a int 2468 switch p.As { 2469 2470 // These opcodes expect a mask operand that has to be converted into the 2471 // appropriate operand. The way these were defined, not all valid masks are possible. 2472 // Left here for compatibility in case they were used or generated. 2473 case ARLDCL, ARLDCLCC: 2474 var mask [2]uint8 2475 c.maskgen64(p, mask[:], uint64(d)) 2476 2477 a = int(mask[0]) /* MB */ 2478 if mask[1] != 63 { 2479 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2480 } 2481 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2482 o1 |= (uint32(a) & 31) << 6 2483 if a&0x20 != 0 { 2484 o1 |= 1 << 5 /* mb[5] is top bit */ 2485 } 2486 2487 case ARLDCR, ARLDCRCC: 2488 var mask [2]uint8 2489 c.maskgen64(p, mask[:], uint64(d)) 2490 2491 a = int(mask[1]) /* ME */ 2492 if mask[0] != 0 { 2493 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2494 } 2495 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2496 o1 |= (uint32(a) & 31) << 6 2497 if a&0x20 != 0 { 2498 o1 |= 1 << 5 /* mb[5] is top bit */ 2499 } 2500 2501 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2502 case ARLDICR, ARLDICRCC: 2503 me := int(d) 2504 sh := c.regoff(&p.From) 2505 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2506 2507 case ARLDICL, ARLDICLCC: 2508 mb := int(d) 2509 sh := c.regoff(&p.From) 2510 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2511 2512 default: 2513 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2514 a = 0 2515 } 2516 2517 case 17, /* bc bo,bi,lbra (same for now) */ 2518 16: /* bc bo,bi,sbra */ 2519 a := 0 2520 2521 r := int(p.Reg) 2522 2523 if p.From.Type == obj.TYPE_CONST { 2524 a = int(c.regoff(&p.From)) 2525 } else if p.From.Type == obj.TYPE_REG { 2526 if r != 0 { 2527 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2528 } 2529 // BI values for the CR 2530 switch p.From.Reg { 2531 case REG_CR0: 2532 r = BI_CR0 2533 case REG_CR1: 2534 r = BI_CR1 2535 case REG_CR2: 2536 r = BI_CR2 2537 case REG_CR3: 2538 r = BI_CR3 2539 case REG_CR4: 2540 r = BI_CR4 2541 case REG_CR5: 2542 r = BI_CR5 2543 case REG_CR6: 2544 r = BI_CR6 2545 case REG_CR7: 2546 r = BI_CR7 2547 default: 2548 c.ctxt.Diag("unrecognized register: expecting CR\n") 2549 } 2550 } 2551 v := int32(0) 2552 if p.Pcond != nil { 2553 v = int32(p.Pcond.Pc - p.Pc) 2554 } 2555 if v&03 != 0 { 2556 c.ctxt.Diag("odd branch target address\n%v", p) 2557 v &^= 03 2558 } 2559 2560 if v < -(1<<16) || v >= 1<<15 { 2561 c.ctxt.Diag("branch too far\n%v", p) 2562 } 2563 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2564 2565 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2566 var v int32 2567 if p.As == ABC || p.As == ABCL { 2568 v = c.regoff(&p.To) & 31 2569 } else { 2570 v = 20 /* unconditional */ 2571 } 2572 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2573 o2 = OPVCC(19, 16, 0, 0) 2574 if p.As == ABL || p.As == ABCL { 2575 o2 |= 1 2576 } 2577 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2578 2579 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2580 var v int32 2581 if p.As == ABC || p.As == ABCL { 2582 v = c.regoff(&p.From) & 31 2583 } else { 2584 v = 20 /* unconditional */ 2585 } 2586 r := int(p.Reg) 2587 if r == 0 { 2588 r = 0 2589 } 2590 switch oclass(&p.To) { 2591 case C_CTR: 2592 o1 = OPVCC(19, 528, 0, 0) 2593 2594 case C_LR: 2595 o1 = OPVCC(19, 16, 0, 0) 2596 2597 default: 2598 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2599 v = 0 2600 } 2601 2602 if p.As == ABL || p.As == ABCL { 2603 o1 |= 1 2604 } 2605 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2606 2607 case 19: /* mov $lcon,r ==> cau+or */ 2608 d := c.vregoff(&p.From) 2609 2610 if p.From.Sym == nil { 2611 o1 = loadu32(int(p.To.Reg), d) 2612 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2613 } else { 2614 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2615 } 2616 2617 //if(dlm) reloc(&p->from, p->pc, 0); 2618 2619 case 20: /* add $ucon,,r */ 2620 v := c.regoff(&p.From) 2621 2622 r := int(p.Reg) 2623 if r == 0 { 2624 r = int(p.To.Reg) 2625 } 2626 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2627 c.ctxt.Diag("literal operation on R0\n%v", p) 2628 } 2629 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2630 2631 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2632 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2633 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2634 } 2635 d := c.vregoff(&p.From) 2636 o1 = loadu32(REGTMP, d) 2637 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2638 r := int(p.Reg) 2639 if r == 0 { 2640 r = int(p.To.Reg) 2641 } 2642 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2643 if p.From.Sym != nil { 2644 c.ctxt.Diag("%v is not supported", p) 2645 } 2646 2647 //if(dlm) reloc(&p->from, p->pc, 0); 2648 2649 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2650 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2651 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2652 } 2653 d := c.vregoff(&p.From) 2654 o1 = loadu32(REGTMP, d) 2655 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2656 r := int(p.Reg) 2657 if r == 0 { 2658 r = int(p.To.Reg) 2659 } 2660 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2661 if p.From.Sym != nil { 2662 c.ctxt.Diag("%v is not supported", p) 2663 } 2664 2665 //if(dlm) reloc(&p->from, p->pc, 0); 2666 2667 /*24*/ 2668 case 25: 2669 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2670 v := c.regoff(&p.From) 2671 2672 if v < 0 { 2673 v = 0 2674 } else if v > 63 { 2675 v = 63 2676 } 2677 r := int(p.Reg) 2678 if r == 0 { 2679 r = int(p.To.Reg) 2680 } 2681 var a int 2682 op := uint32(0) 2683 switch p.As { 2684 case ASLD, ASLDCC: 2685 a = int(63 - v) 2686 op = OP_RLDICR 2687 2688 case ASRD, ASRDCC: 2689 a = int(v) 2690 v = 64 - v 2691 op = OP_RLDICL 2692 case AROTL: 2693 a = int(0) 2694 op = OP_RLDICL 2695 default: 2696 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2697 a = 0 2698 o1 = 0 2699 } 2700 2701 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2702 if p.As == ASLDCC || p.As == ASRDCC { 2703 o1 |= 1 // Set the condition code bit 2704 } 2705 2706 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2707 if p.To.Reg == REGTMP { 2708 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2709 } 2710 v := c.regoff(&p.From) 2711 r := int(p.From.Reg) 2712 if r == 0 { 2713 r = int(o.param) 2714 } 2715 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2716 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2717 2718 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2719 v := c.regoff(p.GetFrom3()) 2720 2721 r := int(p.From.Reg) 2722 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2723 2724 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2725 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2726 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2727 } 2728 v := c.regoff(p.GetFrom3()) 2729 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2730 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2731 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2732 if p.From.Sym != nil { 2733 c.ctxt.Diag("%v is not supported", p) 2734 } 2735 2736 //if(dlm) reloc(&p->from3, p->pc, 0); 2737 2738 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2739 v := c.regoff(&p.From) 2740 2741 d := c.vregoff(p.GetFrom3()) 2742 var mask [2]uint8 2743 c.maskgen64(p, mask[:], uint64(d)) 2744 var a int 2745 switch p.As { 2746 case ARLDC, ARLDCCC: 2747 a = int(mask[0]) /* MB */ 2748 if int32(mask[1]) != (63 - v) { 2749 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2750 } 2751 2752 case ARLDCL, ARLDCLCC: 2753 a = int(mask[0]) /* MB */ 2754 if mask[1] != 63 { 2755 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2756 } 2757 2758 case ARLDCR, ARLDCRCC: 2759 a = int(mask[1]) /* ME */ 2760 if mask[0] != 0 { 2761 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2762 } 2763 2764 default: 2765 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2766 a = 0 2767 } 2768 2769 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2770 o1 |= (uint32(a) & 31) << 6 2771 if v&0x20 != 0 { 2772 o1 |= 1 << 1 2773 } 2774 if a&0x20 != 0 { 2775 o1 |= 1 << 5 /* mb[5] is top bit */ 2776 } 2777 2778 case 30: /* rldimi $sh,s,$mask,a */ 2779 v := c.regoff(&p.From) 2780 2781 d := c.vregoff(p.GetFrom3()) 2782 2783 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2784 // the ppc64 asm. 2785 switch p.As { 2786 case ARLDMI, ARLDMICC: 2787 var mask [2]uint8 2788 c.maskgen64(p, mask[:], uint64(d)) 2789 if int32(mask[1]) != (63 - v) { 2790 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2791 } 2792 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2793 o1 |= (uint32(mask[0]) & 31) << 6 2794 if v&0x20 != 0 { 2795 o1 |= 1 << 1 2796 } 2797 if mask[0]&0x20 != 0 { 2798 o1 |= 1 << 5 /* mb[5] is top bit */ 2799 } 2800 2801 // Opcodes with shift count operands. 2802 case ARLDIMI, ARLDIMICC: 2803 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2804 o1 |= (uint32(d) & 31) << 6 2805 if d&0x20 != 0 { 2806 o1 |= 1 << 5 2807 } 2808 if v&0x20 != 0 { 2809 o1 |= 1 << 1 2810 } 2811 } 2812 2813 case 31: /* dword */ 2814 d := c.vregoff(&p.From) 2815 2816 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2817 o1 = uint32(d >> 32) 2818 o2 = uint32(d) 2819 } else { 2820 o1 = uint32(d) 2821 o2 = uint32(d >> 32) 2822 } 2823 2824 if p.From.Sym != nil { 2825 rel := obj.Addrel(c.cursym) 2826 rel.Off = int32(c.pc) 2827 rel.Siz = 8 2828 rel.Sym = p.From.Sym 2829 rel.Add = p.From.Offset 2830 rel.Type = objabi.R_ADDR 2831 o2 = 0 2832 o1 = o2 2833 } 2834 2835 case 32: /* fmul frc,fra,frd */ 2836 r := int(p.Reg) 2837 2838 if r == 0 { 2839 r = int(p.To.Reg) 2840 } 2841 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2842 2843 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2844 r := int(p.From.Reg) 2845 2846 if oclass(&p.From) == C_NONE { 2847 r = int(p.To.Reg) 2848 } 2849 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2850 2851 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2852 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6 2853 2854 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2855 v := c.regoff(&p.To) 2856 2857 r := int(p.To.Reg) 2858 if r == 0 { 2859 r = int(o.param) 2860 } 2861 // Offsets in DS form stores must be a multiple of 4 2862 inst := c.opstore(p.As) 2863 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2864 log.Fatalf("invalid offset for DS form load/store %v", p) 2865 } 2866 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2867 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2868 2869 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2870 v := c.regoff(&p.From) 2871 2872 r := int(p.From.Reg) 2873 if r == 0 { 2874 r = int(o.param) 2875 } 2876 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2877 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2878 2879 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2880 v := c.regoff(&p.From) 2881 2882 r := int(p.From.Reg) 2883 if r == 0 { 2884 r = int(o.param) 2885 } 2886 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2887 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2888 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2889 2890 case 40: /* word */ 2891 o1 = uint32(c.regoff(&p.From)) 2892 2893 case 41: /* stswi */ 2894 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2895 2896 case 42: /* lswi */ 2897 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2898 2899 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */ 2900 /* TH field for dcbt/dcbtst: */ 2901 /* 0 = Block access - program will soon access EA. */ 2902 /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */ 2903 /* 16 = Block access - program will soon make a transient access to EA. */ 2904 /* 17 = Block access - program will not access EA for a long time. */ 2905 2906 /* L field for dcbf: */ 2907 /* 0 = invalidates the block containing EA in all processors. */ 2908 /* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */ 2909 /* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */ 2910 if p.To.Type == obj.TYPE_NONE { 2911 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2912 } else { 2913 th := c.regoff(&p.To) 2914 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg)) 2915 } 2916 2917 case 44: /* indexed store */ 2918 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2919 2920 case 45: /* indexed load */ 2921 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2922 2923 case 46: /* plain op */ 2924 o1 = c.oprrr(p.As) 2925 2926 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2927 r := int(p.From.Reg) 2928 2929 if r == 0 { 2930 r = int(p.To.Reg) 2931 } 2932 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2933 2934 case 48: /* op Rs, Ra */ 2935 r := int(p.From.Reg) 2936 2937 if r == 0 { 2938 r = int(p.To.Reg) 2939 } 2940 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2941 2942 case 49: /* op Rb; op $n, Rb */ 2943 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2944 v := c.regoff(&p.From) & 1 2945 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2946 } else { 2947 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2948 } 2949 2950 case 50: /* rem[u] r1[,r2],r3 */ 2951 r := int(p.Reg) 2952 2953 if r == 0 { 2954 r = int(p.To.Reg) 2955 } 2956 v := c.oprrr(p.As) 2957 t := v & (1<<10 | 1) /* OE|Rc */ 2958 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2959 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2960 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2961 if p.As == AREMU { 2962 o4 = o3 2963 2964 /* Clear top 32 bits */ 2965 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2966 } 2967 2968 case 51: /* remd[u] r1[,r2],r3 */ 2969 r := int(p.Reg) 2970 2971 if r == 0 { 2972 r = int(p.To.Reg) 2973 } 2974 v := c.oprrr(p.As) 2975 t := v & (1<<10 | 1) /* OE|Rc */ 2976 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2977 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2978 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2979 2980 case 52: /* mtfsbNx cr(n) */ 2981 v := c.regoff(&p.From) & 31 2982 2983 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2984 2985 case 53: /* mffsX ,fr1 */ 2986 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2987 2988 case 54: /* mov msr,r1; mov r1, msr*/ 2989 if oclass(&p.From) == C_REG { 2990 if p.As == AMOVD { 2991 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2992 } else { 2993 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2994 } 2995 } else { 2996 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2997 } 2998 2999 case 55: /* op Rb, Rd */ 3000 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 3001 3002 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 3003 v := c.regoff(&p.From) 3004 3005 r := int(p.Reg) 3006 if r == 0 { 3007 r = int(p.To.Reg) 3008 } 3009 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 3010 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 3011 o1 |= 1 << 1 /* mb[5] */ 3012 } 3013 3014 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 3015 v := c.regoff(&p.From) 3016 3017 r := int(p.Reg) 3018 if r == 0 { 3019 r = int(p.To.Reg) 3020 } 3021 3022 /* 3023 * Let user (gs) shoot himself in the foot. 3024 * qc has already complained. 3025 * 3026 if(v < 0 || v > 31) 3027 ctxt->diag("illegal shift %ld\n%v", v, p); 3028 */ 3029 if v < 0 { 3030 v = 0 3031 } else if v > 32 { 3032 v = 32 3033 } 3034 var mask [2]uint8 3035 switch p.As { 3036 case AROTLW: 3037 mask[0], mask[1] = 0, 31 3038 case ASRW, ASRWCC: 3039 mask[0], mask[1] = uint8(v), 31 3040 v = 32 - v 3041 default: 3042 mask[0], mask[1] = 0, uint8(31-v) 3043 } 3044 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3045 if p.As == ASLWCC || p.As == ASRWCC { 3046 o1 |= 1 // set the condition code 3047 } 3048 3049 case 58: /* logical $andcon,[s],a */ 3050 v := c.regoff(&p.From) 3051 3052 r := int(p.Reg) 3053 if r == 0 { 3054 r = int(p.To.Reg) 3055 } 3056 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3057 3058 case 59: /* or/and $ucon,,r */ 3059 v := c.regoff(&p.From) 3060 3061 r := int(p.Reg) 3062 if r == 0 { 3063 r = int(p.To.Reg) 3064 } 3065 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3066 3067 case 60: /* tw to,a,b */ 3068 r := int(c.regoff(&p.From) & 31) 3069 3070 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3071 3072 case 61: /* tw to,a,$simm */ 3073 r := int(c.regoff(&p.From) & 31) 3074 3075 v := c.regoff(&p.To) 3076 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3077 3078 case 62: /* rlwmi $sh,s,$mask,a */ 3079 v := c.regoff(&p.From) 3080 3081 var mask [2]uint8 3082 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3083 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3084 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3085 3086 case 63: /* rlwmi b,s,$mask,a */ 3087 var mask [2]uint8 3088 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3089 3090 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3091 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3092 3093 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3094 var v int32 3095 if p.From3Type() != obj.TYPE_NONE { 3096 v = c.regoff(p.GetFrom3()) & 255 3097 } else { 3098 v = 255 3099 } 3100 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3101 3102 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3103 if p.To.Reg == 0 { 3104 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3105 } 3106 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3107 3108 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3109 var r int 3110 var v int32 3111 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3112 r = int(p.From.Reg) 3113 v = int32(p.To.Reg) 3114 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3115 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3116 } else { 3117 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3118 } 3119 } else { 3120 r = int(p.To.Reg) 3121 v = int32(p.From.Reg) 3122 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3123 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3124 } else { 3125 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3126 } 3127 } 3128 3129 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3130 3131 case 67: /* mcrf crfD,crfS */ 3132 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3133 c.ctxt.Diag("illegal CR field number\n%v", p) 3134 } 3135 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3136 3137 case 68: /* mfcr rD; mfocrf CRM,rD */ 3138 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3139 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3140 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3141 } else { 3142 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3143 } 3144 3145 case 69: /* mtcrf CRM,rS */ 3146 var v int32 3147 if p.From3Type() != obj.TYPE_NONE { 3148 if p.To.Reg != 0 { 3149 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3150 } 3151 v = c.regoff(p.GetFrom3()) & 0xff 3152 } else { 3153 if p.To.Reg == 0 { 3154 v = 0xff /* CR */ 3155 } else { 3156 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3157 } 3158 } 3159 3160 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3161 3162 case 70: /* [f]cmp r,r,cr*/ 3163 var r int 3164 if p.Reg == 0 { 3165 r = 0 3166 } else { 3167 r = (int(p.Reg) & 7) << 2 3168 } 3169 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3170 3171 case 71: /* cmp[l] r,i,cr*/ 3172 var r int 3173 if p.Reg == 0 { 3174 r = 0 3175 } else { 3176 r = (int(p.Reg) & 7) << 2 3177 } 3178 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3179 3180 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3181 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3182 3183 case 73: /* mcrfs crfD,crfS */ 3184 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3185 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3186 } 3187 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3188 3189 case 77: /* syscall $scon, syscall Rx */ 3190 if p.From.Type == obj.TYPE_CONST { 3191 if p.From.Offset > BIG || p.From.Offset < -BIG { 3192 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3193 } 3194 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3195 } else if p.From.Type == obj.TYPE_REG { 3196 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3197 } else { 3198 c.ctxt.Diag("illegal syscall: %v", p) 3199 o1 = 0x7fe00008 // trap always 3200 } 3201 3202 o2 = c.oprrr(p.As) 3203 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3204 3205 case 78: /* undef */ 3206 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3207 always to be an illegal instruction." */ 3208 3209 /* relocation operations */ 3210 case 74: 3211 v := c.vregoff(&p.To) 3212 // Offsets in DS form stores must be a multiple of 4 3213 inst := c.opstore(p.As) 3214 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3215 log.Fatalf("invalid offset for DS form load/store %v", p) 3216 } 3217 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3218 3219 //if(dlm) reloc(&p->to, p->pc, 1); 3220 3221 case 75: 3222 v := c.vregoff(&p.From) 3223 // Offsets in DS form loads must be a multiple of 4 3224 inst := c.opload(p.As) 3225 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3226 log.Fatalf("invalid offset for DS form load/store %v", p) 3227 } 3228 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3229 3230 //if(dlm) reloc(&p->from, p->pc, 1); 3231 3232 case 76: 3233 v := c.vregoff(&p.From) 3234 // Offsets in DS form loads must be a multiple of 4 3235 inst := c.opload(p.As) 3236 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3237 log.Fatalf("invalid offset for DS form load/store %v", p) 3238 } 3239 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3240 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3241 3242 //if(dlm) reloc(&p->from, p->pc, 1); 3243 3244 case 79: 3245 if p.From.Offset != 0 { 3246 c.ctxt.Diag("invalid offset against tls var %v", p) 3247 } 3248 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3249 rel := obj.Addrel(c.cursym) 3250 rel.Off = int32(c.pc) 3251 rel.Siz = 4 3252 rel.Sym = p.From.Sym 3253 rel.Type = objabi.R_POWER_TLS_LE 3254 3255 case 80: 3256 if p.From.Offset != 0 { 3257 c.ctxt.Diag("invalid offset against tls var %v", p) 3258 } 3259 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3260 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3261 rel := obj.Addrel(c.cursym) 3262 rel.Off = int32(c.pc) 3263 rel.Siz = 8 3264 rel.Sym = p.From.Sym 3265 rel.Type = objabi.R_POWER_TLS_IE 3266 3267 case 81: 3268 v := c.vregoff(&p.To) 3269 if v != 0 { 3270 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3271 } 3272 3273 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3274 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3275 rel := obj.Addrel(c.cursym) 3276 rel.Off = int32(c.pc) 3277 rel.Siz = 8 3278 rel.Sym = p.From.Sym 3279 rel.Type = objabi.R_ADDRPOWER_GOT 3280 case 82: /* vector instructions, VX-form and VC-form */ 3281 if p.From.Type == obj.TYPE_REG { 3282 /* reg reg none OR reg reg reg */ 3283 /* 3-register operand order: VRA, VRB, VRT */ 3284 /* 2-register operand order: VRA, VRT */ 3285 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3286 } else if p.From3Type() == obj.TYPE_CONST { 3287 /* imm imm reg reg */ 3288 /* operand order: SIX, VRA, ST, VRT */ 3289 six := int(c.regoff(&p.From)) 3290 st := int(c.regoff(p.GetFrom3())) 3291 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3292 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3293 /* imm reg reg */ 3294 /* operand order: UIM, VRB, VRT */ 3295 uim := int(c.regoff(&p.From)) 3296 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3297 } else { 3298 /* imm reg */ 3299 /* operand order: SIM, VRT */ 3300 sim := int(c.regoff(&p.From)) 3301 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3302 } 3303 3304 case 83: /* vector instructions, VA-form */ 3305 if p.From.Type == obj.TYPE_REG { 3306 /* reg reg reg reg */ 3307 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3308 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3309 } else if p.From.Type == obj.TYPE_CONST { 3310 /* imm reg reg reg */ 3311 /* operand order: SHB, VRA, VRB, VRT */ 3312 shb := int(c.regoff(&p.From)) 3313 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb)) 3314 } 3315 3316 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3317 bc := c.vregoff(&p.From) 3318 3319 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3320 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc)) 3321 3322 case 85: /* vector instructions, VX-form */ 3323 /* reg none reg */ 3324 /* 2-register operand order: VRB, VRT */ 3325 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3326 3327 case 86: /* VSX indexed store, XX1-form */ 3328 /* reg reg reg */ 3329 /* 3-register operand order: XT, (RB)(RA*1) */ 3330 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3331 3332 case 87: /* VSX indexed load, XX1-form */ 3333 /* reg reg reg */ 3334 /* 3-register operand order: (RB)(RA*1), XT */ 3335 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3336 3337 case 88: /* VSX instructions, XX1-form */ 3338 /* reg reg none OR reg reg reg */ 3339 /* 3-register operand order: RA, RB, XT */ 3340 /* 2-register operand order: XS, RA or RA, XT */ 3341 xt := int32(p.To.Reg) 3342 xs := int32(p.From.Reg) 3343 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3344 if REG_V0 <= xt && xt <= REG_V31 { 3345 /* Convert V0-V31 to VS32-VS63 */ 3346 xt = xt + 64 3347 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3348 } else if REG_F0 <= xt && xt <= REG_F31 { 3349 /* Convert F0-F31 to VS0-VS31 */ 3350 xt = xt + 64 3351 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3352 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3353 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3354 } else if REG_V0 <= xs && xs <= REG_V31 { 3355 /* Likewise for XS */ 3356 xs = xs + 64 3357 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3358 } else if REG_F0 <= xs && xs <= REG_F31 { 3359 xs = xs + 64 3360 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3361 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3362 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3363 } 3364 3365 case 89: /* VSX instructions, XX2-form */ 3366 /* reg none reg OR reg imm reg */ 3367 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3368 uim := int(c.regoff(p.GetFrom3())) 3369 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3370 3371 case 90: /* VSX instructions, XX3-form */ 3372 if p.From3Type() == obj.TYPE_NONE { 3373 /* reg reg reg */ 3374 /* 3-register operand order: XA, XB, XT */ 3375 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3376 } else if p.From3Type() == obj.TYPE_CONST { 3377 /* reg reg reg imm */ 3378 /* operand order: XA, XB, DM, XT */ 3379 dm := int(c.regoff(p.GetFrom3())) 3380 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3381 } 3382 3383 case 91: /* VSX instructions, XX4-form */ 3384 /* reg reg reg reg */ 3385 /* 3-register operand order: XA, XB, XC, XT */ 3386 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3387 3388 case 92: /* X-form instructions, 3-operands */ 3389 if p.To.Type == obj.TYPE_CONST { 3390 /* imm reg reg */ 3391 xf := int32(p.From.Reg) 3392 if REG_F0 <= xf && xf <= REG_F31 { 3393 /* operand order: FRA, FRB, BF */ 3394 bf := int(c.regoff(&p.To)) << 2 3395 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3396 } else { 3397 /* operand order: RA, RB, L */ 3398 l := int(c.regoff(&p.To)) 3399 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg)) 3400 } 3401 } else if p.From3Type() == obj.TYPE_CONST { 3402 /* reg reg imm */ 3403 /* operand order: RB, L, RA */ 3404 l := int(c.regoff(p.GetFrom3())) 3405 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg)) 3406 } else if p.To.Type == obj.TYPE_REG { 3407 cr := int32(p.To.Reg) 3408 if REG_CR0 <= cr && cr <= REG_CR7 { 3409 /* cr reg reg */ 3410 /* operand order: RA, RB, BF */ 3411 bf := (int(p.To.Reg) & 7) << 2 3412 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3413 } else if p.From.Type == obj.TYPE_CONST { 3414 /* reg imm */ 3415 /* operand order: L, RT */ 3416 l := int(c.regoff(&p.From)) 3417 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg)) 3418 } else { 3419 switch p.As { 3420 case ACOPY, APASTECC: 3421 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg)) 3422 default: 3423 /* reg reg reg */ 3424 /* operand order: RS, RB, RA */ 3425 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3426 } 3427 } 3428 } 3429 3430 case 93: /* X-form instructions, 2-operands */ 3431 if p.To.Type == obj.TYPE_CONST { 3432 /* imm reg */ 3433 /* operand order: FRB, BF */ 3434 bf := int(c.regoff(&p.To)) << 2 3435 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3436 } else if p.Reg == 0 { 3437 /* popcnt* r,r, X-form */ 3438 /* operand order: RS, RA */ 3439 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3440 } 3441 3442 case 94: /* Z23-form instructions, 4-operands */ 3443 /* reg reg reg imm */ 3444 /* operand order: RA, RB, CY, RT */ 3445 cy := int(c.regoff(p.GetFrom3())) 3446 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy)) 3447 } 3448 3449 out[0] = o1 3450 out[1] = o2 3451 out[2] = o3 3452 out[3] = o4 3453 out[4] = o5 3454 return 3455 } 3456 3457 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3458 c.instoffset = 0 3459 if a != nil { 3460 c.aclass(a) 3461 } 3462 return c.instoffset 3463 } 3464 3465 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3466 return int32(c.vregoff(a)) 3467 } 3468 3469 func (c *ctxt9) oprrr(a obj.As) uint32 { 3470 switch a { 3471 case AADD: 3472 return OPVCC(31, 266, 0, 0) 3473 case AADDCC: 3474 return OPVCC(31, 266, 0, 1) 3475 case AADDV: 3476 return OPVCC(31, 266, 1, 0) 3477 case AADDVCC: 3478 return OPVCC(31, 266, 1, 1) 3479 case AADDC: 3480 return OPVCC(31, 10, 0, 0) 3481 case AADDCCC: 3482 return OPVCC(31, 10, 0, 1) 3483 case AADDCV: 3484 return OPVCC(31, 10, 1, 0) 3485 case AADDCVCC: 3486 return OPVCC(31, 10, 1, 1) 3487 case AADDE: 3488 return OPVCC(31, 138, 0, 0) 3489 case AADDECC: 3490 return OPVCC(31, 138, 0, 1) 3491 case AADDEV: 3492 return OPVCC(31, 138, 1, 0) 3493 case AADDEVCC: 3494 return OPVCC(31, 138, 1, 1) 3495 case AADDME: 3496 return OPVCC(31, 234, 0, 0) 3497 case AADDMECC: 3498 return OPVCC(31, 234, 0, 1) 3499 case AADDMEV: 3500 return OPVCC(31, 234, 1, 0) 3501 case AADDMEVCC: 3502 return OPVCC(31, 234, 1, 1) 3503 case AADDZE: 3504 return OPVCC(31, 202, 0, 0) 3505 case AADDZECC: 3506 return OPVCC(31, 202, 0, 1) 3507 case AADDZEV: 3508 return OPVCC(31, 202, 1, 0) 3509 case AADDZEVCC: 3510 return OPVCC(31, 202, 1, 1) 3511 case AADDEX: 3512 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */ 3513 3514 case AAND: 3515 return OPVCC(31, 28, 0, 0) 3516 case AANDCC: 3517 return OPVCC(31, 28, 0, 1) 3518 case AANDN: 3519 return OPVCC(31, 60, 0, 0) 3520 case AANDNCC: 3521 return OPVCC(31, 60, 0, 1) 3522 3523 case ACMP: 3524 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3525 case ACMPU: 3526 return OPVCC(31, 32, 0, 0) | 1<<21 3527 case ACMPW: 3528 return OPVCC(31, 0, 0, 0) /* L=0 */ 3529 case ACMPWU: 3530 return OPVCC(31, 32, 0, 0) 3531 case ACMPB: 3532 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3533 3534 case ACNTLZW: 3535 return OPVCC(31, 26, 0, 0) 3536 case ACNTLZWCC: 3537 return OPVCC(31, 26, 0, 1) 3538 case ACNTLZD: 3539 return OPVCC(31, 58, 0, 0) 3540 case ACNTLZDCC: 3541 return OPVCC(31, 58, 0, 1) 3542 3543 case ACRAND: 3544 return OPVCC(19, 257, 0, 0) 3545 case ACRANDN: 3546 return OPVCC(19, 129, 0, 0) 3547 case ACREQV: 3548 return OPVCC(19, 289, 0, 0) 3549 case ACRNAND: 3550 return OPVCC(19, 225, 0, 0) 3551 case ACRNOR: 3552 return OPVCC(19, 33, 0, 0) 3553 case ACROR: 3554 return OPVCC(19, 449, 0, 0) 3555 case ACRORN: 3556 return OPVCC(19, 417, 0, 0) 3557 case ACRXOR: 3558 return OPVCC(19, 193, 0, 0) 3559 3560 case ADCBF: 3561 return OPVCC(31, 86, 0, 0) 3562 case ADCBI: 3563 return OPVCC(31, 470, 0, 0) 3564 case ADCBST: 3565 return OPVCC(31, 54, 0, 0) 3566 case ADCBT: 3567 return OPVCC(31, 278, 0, 0) 3568 case ADCBTST: 3569 return OPVCC(31, 246, 0, 0) 3570 case ADCBZ: 3571 return OPVCC(31, 1014, 0, 0) 3572 3573 case AREM, ADIVW: 3574 return OPVCC(31, 491, 0, 0) 3575 3576 case AREMCC, ADIVWCC: 3577 return OPVCC(31, 491, 0, 1) 3578 3579 case AREMV, ADIVWV: 3580 return OPVCC(31, 491, 1, 0) 3581 3582 case AREMVCC, ADIVWVCC: 3583 return OPVCC(31, 491, 1, 1) 3584 3585 case AREMU, ADIVWU: 3586 return OPVCC(31, 459, 0, 0) 3587 3588 case AREMUCC, ADIVWUCC: 3589 return OPVCC(31, 459, 0, 1) 3590 3591 case AREMUV, ADIVWUV: 3592 return OPVCC(31, 459, 1, 0) 3593 3594 case AREMUVCC, ADIVWUVCC: 3595 return OPVCC(31, 459, 1, 1) 3596 3597 case AREMD, ADIVD: 3598 return OPVCC(31, 489, 0, 0) 3599 3600 case AREMDCC, ADIVDCC: 3601 return OPVCC(31, 489, 0, 1) 3602 3603 case ADIVDE: 3604 return OPVCC(31, 425, 0, 0) 3605 3606 case ADIVDECC: 3607 return OPVCC(31, 425, 0, 1) 3608 3609 case ADIVDEU: 3610 return OPVCC(31, 393, 0, 0) 3611 3612 case ADIVDEUCC: 3613 return OPVCC(31, 393, 0, 1) 3614 3615 case AREMDV, ADIVDV: 3616 return OPVCC(31, 489, 1, 0) 3617 3618 case AREMDVCC, ADIVDVCC: 3619 return OPVCC(31, 489, 1, 1) 3620 3621 case AREMDU, ADIVDU: 3622 return OPVCC(31, 457, 0, 0) 3623 3624 case AREMDUCC, ADIVDUCC: 3625 return OPVCC(31, 457, 0, 1) 3626 3627 case AREMDUV, ADIVDUV: 3628 return OPVCC(31, 457, 1, 0) 3629 3630 case AREMDUVCC, ADIVDUVCC: 3631 return OPVCC(31, 457, 1, 1) 3632 3633 case AEIEIO: 3634 return OPVCC(31, 854, 0, 0) 3635 3636 case AEQV: 3637 return OPVCC(31, 284, 0, 0) 3638 case AEQVCC: 3639 return OPVCC(31, 284, 0, 1) 3640 3641 case AEXTSB: 3642 return OPVCC(31, 954, 0, 0) 3643 case AEXTSBCC: 3644 return OPVCC(31, 954, 0, 1) 3645 case AEXTSH: 3646 return OPVCC(31, 922, 0, 0) 3647 case AEXTSHCC: 3648 return OPVCC(31, 922, 0, 1) 3649 case AEXTSW: 3650 return OPVCC(31, 986, 0, 0) 3651 case AEXTSWCC: 3652 return OPVCC(31, 986, 0, 1) 3653 3654 case AFABS: 3655 return OPVCC(63, 264, 0, 0) 3656 case AFABSCC: 3657 return OPVCC(63, 264, 0, 1) 3658 case AFADD: 3659 return OPVCC(63, 21, 0, 0) 3660 case AFADDCC: 3661 return OPVCC(63, 21, 0, 1) 3662 case AFADDS: 3663 return OPVCC(59, 21, 0, 0) 3664 case AFADDSCC: 3665 return OPVCC(59, 21, 0, 1) 3666 case AFCMPO: 3667 return OPVCC(63, 32, 0, 0) 3668 case AFCMPU: 3669 return OPVCC(63, 0, 0, 0) 3670 case AFCFID: 3671 return OPVCC(63, 846, 0, 0) 3672 case AFCFIDCC: 3673 return OPVCC(63, 846, 0, 1) 3674 case AFCFIDU: 3675 return OPVCC(63, 974, 0, 0) 3676 case AFCFIDUCC: 3677 return OPVCC(63, 974, 0, 1) 3678 case AFCFIDS: 3679 return OPVCC(59, 846, 0, 0) 3680 case AFCFIDSCC: 3681 return OPVCC(59, 846, 0, 1) 3682 case AFCTIW: 3683 return OPVCC(63, 14, 0, 0) 3684 case AFCTIWCC: 3685 return OPVCC(63, 14, 0, 1) 3686 case AFCTIWZ: 3687 return OPVCC(63, 15, 0, 0) 3688 case AFCTIWZCC: 3689 return OPVCC(63, 15, 0, 1) 3690 case AFCTID: 3691 return OPVCC(63, 814, 0, 0) 3692 case AFCTIDCC: 3693 return OPVCC(63, 814, 0, 1) 3694 case AFCTIDZ: 3695 return OPVCC(63, 815, 0, 0) 3696 case AFCTIDZCC: 3697 return OPVCC(63, 815, 0, 1) 3698 case AFDIV: 3699 return OPVCC(63, 18, 0, 0) 3700 case AFDIVCC: 3701 return OPVCC(63, 18, 0, 1) 3702 case AFDIVS: 3703 return OPVCC(59, 18, 0, 0) 3704 case AFDIVSCC: 3705 return OPVCC(59, 18, 0, 1) 3706 case AFMADD: 3707 return OPVCC(63, 29, 0, 0) 3708 case AFMADDCC: 3709 return OPVCC(63, 29, 0, 1) 3710 case AFMADDS: 3711 return OPVCC(59, 29, 0, 0) 3712 case AFMADDSCC: 3713 return OPVCC(59, 29, 0, 1) 3714 3715 case AFMOVS, AFMOVD: 3716 return OPVCC(63, 72, 0, 0) /* load */ 3717 case AFMOVDCC: 3718 return OPVCC(63, 72, 0, 1) 3719 case AFMSUB: 3720 return OPVCC(63, 28, 0, 0) 3721 case AFMSUBCC: 3722 return OPVCC(63, 28, 0, 1) 3723 case AFMSUBS: 3724 return OPVCC(59, 28, 0, 0) 3725 case AFMSUBSCC: 3726 return OPVCC(59, 28, 0, 1) 3727 case AFMUL: 3728 return OPVCC(63, 25, 0, 0) 3729 case AFMULCC: 3730 return OPVCC(63, 25, 0, 1) 3731 case AFMULS: 3732 return OPVCC(59, 25, 0, 0) 3733 case AFMULSCC: 3734 return OPVCC(59, 25, 0, 1) 3735 case AFNABS: 3736 return OPVCC(63, 136, 0, 0) 3737 case AFNABSCC: 3738 return OPVCC(63, 136, 0, 1) 3739 case AFNEG: 3740 return OPVCC(63, 40, 0, 0) 3741 case AFNEGCC: 3742 return OPVCC(63, 40, 0, 1) 3743 case AFNMADD: 3744 return OPVCC(63, 31, 0, 0) 3745 case AFNMADDCC: 3746 return OPVCC(63, 31, 0, 1) 3747 case AFNMADDS: 3748 return OPVCC(59, 31, 0, 0) 3749 case AFNMADDSCC: 3750 return OPVCC(59, 31, 0, 1) 3751 case AFNMSUB: 3752 return OPVCC(63, 30, 0, 0) 3753 case AFNMSUBCC: 3754 return OPVCC(63, 30, 0, 1) 3755 case AFNMSUBS: 3756 return OPVCC(59, 30, 0, 0) 3757 case AFNMSUBSCC: 3758 return OPVCC(59, 30, 0, 1) 3759 case AFRES: 3760 return OPVCC(59, 24, 0, 0) 3761 case AFRESCC: 3762 return OPVCC(59, 24, 0, 1) 3763 case AFRIM: 3764 return OPVCC(63, 488, 0, 0) 3765 case AFRIMCC: 3766 return OPVCC(63, 488, 0, 1) 3767 case AFRIP: 3768 return OPVCC(63, 456, 0, 0) 3769 case AFRIPCC: 3770 return OPVCC(63, 456, 0, 1) 3771 case AFRIZ: 3772 return OPVCC(63, 424, 0, 0) 3773 case AFRIZCC: 3774 return OPVCC(63, 424, 0, 1) 3775 case AFRSP: 3776 return OPVCC(63, 12, 0, 0) 3777 case AFRSPCC: 3778 return OPVCC(63, 12, 0, 1) 3779 case AFRSQRTE: 3780 return OPVCC(63, 26, 0, 0) 3781 case AFRSQRTECC: 3782 return OPVCC(63, 26, 0, 1) 3783 case AFSEL: 3784 return OPVCC(63, 23, 0, 0) 3785 case AFSELCC: 3786 return OPVCC(63, 23, 0, 1) 3787 case AFSQRT: 3788 return OPVCC(63, 22, 0, 0) 3789 case AFSQRTCC: 3790 return OPVCC(63, 22, 0, 1) 3791 case AFSQRTS: 3792 return OPVCC(59, 22, 0, 0) 3793 case AFSQRTSCC: 3794 return OPVCC(59, 22, 0, 1) 3795 case AFSUB: 3796 return OPVCC(63, 20, 0, 0) 3797 case AFSUBCC: 3798 return OPVCC(63, 20, 0, 1) 3799 case AFSUBS: 3800 return OPVCC(59, 20, 0, 0) 3801 case AFSUBSCC: 3802 return OPVCC(59, 20, 0, 1) 3803 3804 case AICBI: 3805 return OPVCC(31, 982, 0, 0) 3806 case AISYNC: 3807 return OPVCC(19, 150, 0, 0) 3808 3809 case AMTFSB0: 3810 return OPVCC(63, 70, 0, 0) 3811 case AMTFSB0CC: 3812 return OPVCC(63, 70, 0, 1) 3813 case AMTFSB1: 3814 return OPVCC(63, 38, 0, 0) 3815 case AMTFSB1CC: 3816 return OPVCC(63, 38, 0, 1) 3817 3818 case AMULHW: 3819 return OPVCC(31, 75, 0, 0) 3820 case AMULHWCC: 3821 return OPVCC(31, 75, 0, 1) 3822 case AMULHWU: 3823 return OPVCC(31, 11, 0, 0) 3824 case AMULHWUCC: 3825 return OPVCC(31, 11, 0, 1) 3826 case AMULLW: 3827 return OPVCC(31, 235, 0, 0) 3828 case AMULLWCC: 3829 return OPVCC(31, 235, 0, 1) 3830 case AMULLWV: 3831 return OPVCC(31, 235, 1, 0) 3832 case AMULLWVCC: 3833 return OPVCC(31, 235, 1, 1) 3834 3835 case AMULHD: 3836 return OPVCC(31, 73, 0, 0) 3837 case AMULHDCC: 3838 return OPVCC(31, 73, 0, 1) 3839 case AMULHDU: 3840 return OPVCC(31, 9, 0, 0) 3841 case AMULHDUCC: 3842 return OPVCC(31, 9, 0, 1) 3843 case AMULLD: 3844 return OPVCC(31, 233, 0, 0) 3845 case AMULLDCC: 3846 return OPVCC(31, 233, 0, 1) 3847 case AMULLDV: 3848 return OPVCC(31, 233, 1, 0) 3849 case AMULLDVCC: 3850 return OPVCC(31, 233, 1, 1) 3851 3852 case ANAND: 3853 return OPVCC(31, 476, 0, 0) 3854 case ANANDCC: 3855 return OPVCC(31, 476, 0, 1) 3856 case ANEG: 3857 return OPVCC(31, 104, 0, 0) 3858 case ANEGCC: 3859 return OPVCC(31, 104, 0, 1) 3860 case ANEGV: 3861 return OPVCC(31, 104, 1, 0) 3862 case ANEGVCC: 3863 return OPVCC(31, 104, 1, 1) 3864 case ANOR: 3865 return OPVCC(31, 124, 0, 0) 3866 case ANORCC: 3867 return OPVCC(31, 124, 0, 1) 3868 case AOR: 3869 return OPVCC(31, 444, 0, 0) 3870 case AORCC: 3871 return OPVCC(31, 444, 0, 1) 3872 case AORN: 3873 return OPVCC(31, 412, 0, 0) 3874 case AORNCC: 3875 return OPVCC(31, 412, 0, 1) 3876 3877 case APOPCNTD: 3878 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3879 case APOPCNTW: 3880 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3881 case APOPCNTB: 3882 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3883 3884 case ARFI: 3885 return OPVCC(19, 50, 0, 0) 3886 case ARFCI: 3887 return OPVCC(19, 51, 0, 0) 3888 case ARFID: 3889 return OPVCC(19, 18, 0, 0) 3890 case AHRFID: 3891 return OPVCC(19, 274, 0, 0) 3892 3893 case ARLWMI: 3894 return OPVCC(20, 0, 0, 0) 3895 case ARLWMICC: 3896 return OPVCC(20, 0, 0, 1) 3897 case ARLWNM: 3898 return OPVCC(23, 0, 0, 0) 3899 case ARLWNMCC: 3900 return OPVCC(23, 0, 0, 1) 3901 3902 case ARLDCL: 3903 return OPVCC(30, 8, 0, 0) 3904 case ARLDCR: 3905 return OPVCC(30, 9, 0, 0) 3906 3907 case ARLDICL: 3908 return OPVCC(30, 0, 0, 0) 3909 case ARLDICLCC: 3910 return OPVCC(30, 0, 0, 1) 3911 case ARLDICR: 3912 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3913 case ARLDICRCC: 3914 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3915 3916 case ASYSCALL: 3917 return OPVCC(17, 1, 0, 0) 3918 3919 case ASLW: 3920 return OPVCC(31, 24, 0, 0) 3921 case ASLWCC: 3922 return OPVCC(31, 24, 0, 1) 3923 case ASLD: 3924 return OPVCC(31, 27, 0, 0) 3925 case ASLDCC: 3926 return OPVCC(31, 27, 0, 1) 3927 3928 case ASRAW: 3929 return OPVCC(31, 792, 0, 0) 3930 case ASRAWCC: 3931 return OPVCC(31, 792, 0, 1) 3932 case ASRAD: 3933 return OPVCC(31, 794, 0, 0) 3934 case ASRADCC: 3935 return OPVCC(31, 794, 0, 1) 3936 3937 case ASRW: 3938 return OPVCC(31, 536, 0, 0) 3939 case ASRWCC: 3940 return OPVCC(31, 536, 0, 1) 3941 case ASRD: 3942 return OPVCC(31, 539, 0, 0) 3943 case ASRDCC: 3944 return OPVCC(31, 539, 0, 1) 3945 3946 case ASUB: 3947 return OPVCC(31, 40, 0, 0) 3948 case ASUBCC: 3949 return OPVCC(31, 40, 0, 1) 3950 case ASUBV: 3951 return OPVCC(31, 40, 1, 0) 3952 case ASUBVCC: 3953 return OPVCC(31, 40, 1, 1) 3954 case ASUBC: 3955 return OPVCC(31, 8, 0, 0) 3956 case ASUBCCC: 3957 return OPVCC(31, 8, 0, 1) 3958 case ASUBCV: 3959 return OPVCC(31, 8, 1, 0) 3960 case ASUBCVCC: 3961 return OPVCC(31, 8, 1, 1) 3962 case ASUBE: 3963 return OPVCC(31, 136, 0, 0) 3964 case ASUBECC: 3965 return OPVCC(31, 136, 0, 1) 3966 case ASUBEV: 3967 return OPVCC(31, 136, 1, 0) 3968 case ASUBEVCC: 3969 return OPVCC(31, 136, 1, 1) 3970 case ASUBME: 3971 return OPVCC(31, 232, 0, 0) 3972 case ASUBMECC: 3973 return OPVCC(31, 232, 0, 1) 3974 case ASUBMEV: 3975 return OPVCC(31, 232, 1, 0) 3976 case ASUBMEVCC: 3977 return OPVCC(31, 232, 1, 1) 3978 case ASUBZE: 3979 return OPVCC(31, 200, 0, 0) 3980 case ASUBZECC: 3981 return OPVCC(31, 200, 0, 1) 3982 case ASUBZEV: 3983 return OPVCC(31, 200, 1, 0) 3984 case ASUBZEVCC: 3985 return OPVCC(31, 200, 1, 1) 3986 3987 case ASYNC: 3988 return OPVCC(31, 598, 0, 0) 3989 case ALWSYNC: 3990 return OPVCC(31, 598, 0, 0) | 1<<21 3991 3992 case APTESYNC: 3993 return OPVCC(31, 598, 0, 0) | 2<<21 3994 3995 case ATLBIE: 3996 return OPVCC(31, 306, 0, 0) 3997 case ATLBIEL: 3998 return OPVCC(31, 274, 0, 0) 3999 case ATLBSYNC: 4000 return OPVCC(31, 566, 0, 0) 4001 case ASLBIA: 4002 return OPVCC(31, 498, 0, 0) 4003 case ASLBIE: 4004 return OPVCC(31, 434, 0, 0) 4005 case ASLBMFEE: 4006 return OPVCC(31, 915, 0, 0) 4007 case ASLBMFEV: 4008 return OPVCC(31, 851, 0, 0) 4009 case ASLBMTE: 4010 return OPVCC(31, 402, 0, 0) 4011 4012 case ATW: 4013 return OPVCC(31, 4, 0, 0) 4014 case ATD: 4015 return OPVCC(31, 68, 0, 0) 4016 4017 /* Vector (VMX/Altivec) instructions */ 4018 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4019 /* are enabled starting at POWER6 (ISA 2.05). */ 4020 case AVAND: 4021 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 4022 case AVANDC: 4023 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 4024 case AVNAND: 4025 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 4026 4027 case AVOR: 4028 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 4029 case AVORC: 4030 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 4031 case AVNOR: 4032 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 4033 case AVXOR: 4034 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 4035 case AVEQV: 4036 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 4037 4038 case AVADDUBM: 4039 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 4040 case AVADDUHM: 4041 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 4042 case AVADDUWM: 4043 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 4044 case AVADDUDM: 4045 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 4046 case AVADDUQM: 4047 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 4048 4049 case AVADDCUQ: 4050 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 4051 case AVADDCUW: 4052 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 4053 4054 case AVADDUBS: 4055 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 4056 case AVADDUHS: 4057 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 4058 case AVADDUWS: 4059 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 4060 4061 case AVADDSBS: 4062 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 4063 case AVADDSHS: 4064 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 4065 case AVADDSWS: 4066 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 4067 4068 case AVADDEUQM: 4069 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 4070 case AVADDECUQ: 4071 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4072 4073 case AVPMSUMB: 4074 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4075 case AVPMSUMH: 4076 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4077 case AVPMSUMW: 4078 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4079 case AVPMSUMD: 4080 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4081 4082 case AVMSUMUDM: 4083 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */ 4084 4085 case AVSUBUBM: 4086 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4087 case AVSUBUHM: 4088 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4089 case AVSUBUWM: 4090 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4091 case AVSUBUDM: 4092 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4093 case AVSUBUQM: 4094 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4095 4096 case AVSUBCUQ: 4097 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4098 case AVSUBCUW: 4099 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4100 4101 case AVSUBUBS: 4102 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4103 case AVSUBUHS: 4104 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4105 case AVSUBUWS: 4106 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4107 4108 case AVSUBSBS: 4109 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4110 case AVSUBSHS: 4111 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4112 case AVSUBSWS: 4113 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4114 4115 case AVSUBEUQM: 4116 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4117 case AVSUBECUQ: 4118 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4119 4120 case AVRLB: 4121 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4122 case AVRLH: 4123 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4124 case AVRLW: 4125 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4126 case AVRLD: 4127 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4128 4129 case AVSLB: 4130 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4131 case AVSLH: 4132 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4133 case AVSLW: 4134 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4135 case AVSL: 4136 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4137 case AVSLO: 4138 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4139 case AVSRB: 4140 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4141 case AVSRH: 4142 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4143 case AVSRW: 4144 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4145 case AVSR: 4146 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4147 case AVSRO: 4148 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4149 case AVSLD: 4150 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4151 case AVSRD: 4152 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4153 4154 case AVSRAB: 4155 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4156 case AVSRAH: 4157 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4158 case AVSRAW: 4159 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4160 case AVSRAD: 4161 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4162 4163 case AVCLZB: 4164 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4165 case AVCLZH: 4166 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4167 case AVCLZW: 4168 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4169 case AVCLZD: 4170 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4171 4172 case AVPOPCNTB: 4173 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4174 case AVPOPCNTH: 4175 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4176 case AVPOPCNTW: 4177 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4178 case AVPOPCNTD: 4179 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4180 4181 case AVCMPEQUB: 4182 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4183 case AVCMPEQUBCC: 4184 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4185 case AVCMPEQUH: 4186 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4187 case AVCMPEQUHCC: 4188 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4189 case AVCMPEQUW: 4190 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4191 case AVCMPEQUWCC: 4192 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4193 case AVCMPEQUD: 4194 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4195 case AVCMPEQUDCC: 4196 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4197 4198 case AVCMPGTUB: 4199 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4200 case AVCMPGTUBCC: 4201 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4202 case AVCMPGTUH: 4203 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4204 case AVCMPGTUHCC: 4205 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4206 case AVCMPGTUW: 4207 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4208 case AVCMPGTUWCC: 4209 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4210 case AVCMPGTUD: 4211 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4212 case AVCMPGTUDCC: 4213 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4214 case AVCMPGTSB: 4215 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4216 case AVCMPGTSBCC: 4217 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4218 case AVCMPGTSH: 4219 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4220 case AVCMPGTSHCC: 4221 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4222 case AVCMPGTSW: 4223 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4224 case AVCMPGTSWCC: 4225 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4226 case AVCMPGTSD: 4227 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4228 case AVCMPGTSDCC: 4229 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4230 4231 case AVCMPNEZB: 4232 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */ 4233 case AVCMPNEZBCC: 4234 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */ 4235 4236 case AVPERM: 4237 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4238 4239 case AVSEL: 4240 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4241 4242 case AVCIPHER: 4243 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4244 case AVCIPHERLAST: 4245 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4246 case AVNCIPHER: 4247 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4248 case AVNCIPHERLAST: 4249 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4250 case AVSBOX: 4251 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4252 /* End of vector instructions */ 4253 4254 /* Vector scalar (VSX) instructions */ 4255 /* ISA 2.06 enables these for POWER7. */ 4256 case AMFVSRD, AMFVRD, AMFFPRD: 4257 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4258 case AMFVSRWZ: 4259 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4260 case AMFVSRLD: 4261 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */ 4262 4263 case AMTVSRD, AMTFPRD, AMTVRD: 4264 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4265 case AMTVSRWA: 4266 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4267 case AMTVSRWZ: 4268 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4269 case AMTVSRDD: 4270 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */ 4271 case AMTVSRWS: 4272 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */ 4273 4274 case AXXLANDQ: 4275 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4276 case AXXLANDC: 4277 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4278 case AXXLEQV: 4279 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4280 case AXXLNAND: 4281 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4282 4283 case AXXLORC: 4284 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4285 case AXXLNOR: 4286 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4287 case AXXLORQ: 4288 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4289 case AXXLXOR: 4290 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4291 4292 case AXXSEL: 4293 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4294 4295 case AXXMRGHW: 4296 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4297 case AXXMRGLW: 4298 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4299 4300 case AXXSPLTW: 4301 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4302 4303 case AXXPERMDI: 4304 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4305 4306 case AXXSLDWI: 4307 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4308 4309 case AXSCVDPSP: 4310 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4311 case AXSCVSPDP: 4312 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4313 case AXSCVDPSPN: 4314 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4315 case AXSCVSPDPN: 4316 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4317 4318 case AXVCVDPSP: 4319 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4320 case AXVCVSPDP: 4321 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4322 4323 case AXSCVDPSXDS: 4324 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4325 case AXSCVDPSXWS: 4326 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4327 case AXSCVDPUXDS: 4328 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4329 case AXSCVDPUXWS: 4330 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4331 4332 case AXSCVSXDDP: 4333 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4334 case AXSCVUXDDP: 4335 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4336 case AXSCVSXDSP: 4337 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4338 case AXSCVUXDSP: 4339 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4340 4341 case AXVCVDPSXDS: 4342 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4343 case AXVCVDPSXWS: 4344 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4345 case AXVCVDPUXDS: 4346 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4347 case AXVCVDPUXWS: 4348 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4349 case AXVCVSPSXDS: 4350 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4351 case AXVCVSPSXWS: 4352 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4353 case AXVCVSPUXDS: 4354 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4355 case AXVCVSPUXWS: 4356 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4357 4358 case AXVCVSXDDP: 4359 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4360 case AXVCVSXWDP: 4361 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4362 case AXVCVUXDDP: 4363 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4364 case AXVCVUXWDP: 4365 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4366 case AXVCVSXDSP: 4367 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4368 case AXVCVSXWSP: 4369 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4370 case AXVCVUXDSP: 4371 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4372 case AXVCVUXWSP: 4373 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4374 /* End of VSX instructions */ 4375 4376 case AMADDHD: 4377 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */ 4378 case AMADDHDU: 4379 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */ 4380 case AMADDLD: 4381 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */ 4382 4383 case AXOR: 4384 return OPVCC(31, 316, 0, 0) 4385 case AXORCC: 4386 return OPVCC(31, 316, 0, 1) 4387 } 4388 4389 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4390 return 0 4391 } 4392 4393 func (c *ctxt9) opirrr(a obj.As) uint32 { 4394 switch a { 4395 /* Vector (VMX/Altivec) instructions */ 4396 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4397 /* are enabled starting at POWER6 (ISA 2.05). */ 4398 case AVSLDOI: 4399 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4400 } 4401 4402 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4403 return 0 4404 } 4405 4406 func (c *ctxt9) opiirr(a obj.As) uint32 { 4407 switch a { 4408 /* Vector (VMX/Altivec) instructions */ 4409 /* ISA 2.07 enables these for POWER8 and beyond. */ 4410 case AVSHASIGMAW: 4411 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4412 case AVSHASIGMAD: 4413 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4414 } 4415 4416 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4417 return 0 4418 } 4419 4420 func (c *ctxt9) opirr(a obj.As) uint32 { 4421 switch a { 4422 case AADD: 4423 return OPVCC(14, 0, 0, 0) 4424 case AADDC: 4425 return OPVCC(12, 0, 0, 0) 4426 case AADDCCC: 4427 return OPVCC(13, 0, 0, 0) 4428 case -AADD: 4429 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4430 4431 case AANDCC: 4432 return OPVCC(28, 0, 0, 0) 4433 case -AANDCC: 4434 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4435 4436 case ABR: 4437 return OPVCC(18, 0, 0, 0) 4438 case ABL: 4439 return OPVCC(18, 0, 0, 0) | 1 4440 case obj.ADUFFZERO: 4441 return OPVCC(18, 0, 0, 0) | 1 4442 case obj.ADUFFCOPY: 4443 return OPVCC(18, 0, 0, 0) | 1 4444 case ABC: 4445 return OPVCC(16, 0, 0, 0) 4446 case ABCL: 4447 return OPVCC(16, 0, 0, 0) | 1 4448 4449 case ABEQ: 4450 return AOP_RRR(16<<26, 12, 2, 0) 4451 case ABGE: 4452 return AOP_RRR(16<<26, 4, 0, 0) 4453 case ABGT: 4454 return AOP_RRR(16<<26, 12, 1, 0) 4455 case ABLE: 4456 return AOP_RRR(16<<26, 4, 1, 0) 4457 case ABLT: 4458 return AOP_RRR(16<<26, 12, 0, 0) 4459 case ABNE: 4460 return AOP_RRR(16<<26, 4, 2, 0) 4461 case ABVC: 4462 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4463 case ABVS: 4464 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4465 4466 case ACMP: 4467 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4468 case ACMPU: 4469 return OPVCC(10, 0, 0, 0) | 1<<21 4470 case ACMPW: 4471 return OPVCC(11, 0, 0, 0) /* L=0 */ 4472 case ACMPWU: 4473 return OPVCC(10, 0, 0, 0) 4474 case ACMPEQB: 4475 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 4476 4477 case ALSW: 4478 return OPVCC(31, 597, 0, 0) 4479 4480 case ACOPY: 4481 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */ 4482 case APASTECC: 4483 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */ 4484 case ADARN: 4485 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */ 4486 4487 case AMULLW: 4488 return OPVCC(7, 0, 0, 0) 4489 4490 case AOR: 4491 return OPVCC(24, 0, 0, 0) 4492 case -AOR: 4493 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4494 4495 case ARLWMI: 4496 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4497 case ARLWMICC: 4498 return OPVCC(20, 0, 0, 1) 4499 case ARLDMI: 4500 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4501 case ARLDMICC: 4502 return OPVCC(30, 0, 0, 1) | 3<<2 4503 case ARLDIMI: 4504 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4505 case ARLDIMICC: 4506 return OPVCC(30, 0, 0, 1) | 3<<2 4507 case ARLWNM: 4508 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4509 case ARLWNMCC: 4510 return OPVCC(21, 0, 0, 1) 4511 4512 case ARLDCL: 4513 return OPVCC(30, 0, 0, 0) /* rldicl */ 4514 case ARLDCLCC: 4515 return OPVCC(30, 0, 0, 1) 4516 case ARLDCR: 4517 return OPVCC(30, 1, 0, 0) /* rldicr */ 4518 case ARLDCRCC: 4519 return OPVCC(30, 1, 0, 1) 4520 case ARLDC: 4521 return OPVCC(30, 0, 0, 0) | 2<<2 4522 case ARLDCCC: 4523 return OPVCC(30, 0, 0, 1) | 2<<2 4524 4525 case ASRAW: 4526 return OPVCC(31, 824, 0, 0) 4527 case ASRAWCC: 4528 return OPVCC(31, 824, 0, 1) 4529 case ASRAD: 4530 return OPVCC(31, (413 << 1), 0, 0) 4531 case ASRADCC: 4532 return OPVCC(31, (413 << 1), 0, 1) 4533 4534 case ASTSW: 4535 return OPVCC(31, 725, 0, 0) 4536 4537 case ASUBC: 4538 return OPVCC(8, 0, 0, 0) 4539 4540 case ATW: 4541 return OPVCC(3, 0, 0, 0) 4542 case ATD: 4543 return OPVCC(2, 0, 0, 0) 4544 4545 /* Vector (VMX/Altivec) instructions */ 4546 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4547 /* are enabled starting at POWER6 (ISA 2.05). */ 4548 case AVSPLTB: 4549 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4550 case AVSPLTH: 4551 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4552 case AVSPLTW: 4553 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4554 4555 case AVSPLTISB: 4556 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4557 case AVSPLTISH: 4558 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4559 case AVSPLTISW: 4560 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4561 /* End of vector instructions */ 4562 4563 case AFTDIV: 4564 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4565 case AFTSQRT: 4566 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4567 4568 case AXOR: 4569 return OPVCC(26, 0, 0, 0) /* XORIL */ 4570 case -AXOR: 4571 return OPVCC(27, 0, 0, 0) /* XORIU */ 4572 } 4573 4574 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4575 return 0 4576 } 4577 4578 /* 4579 * load o(a),d 4580 */ 4581 func (c *ctxt9) opload(a obj.As) uint32 { 4582 switch a { 4583 case AMOVD: 4584 return OPVCC(58, 0, 0, 0) /* ld */ 4585 case AMOVDU: 4586 return OPVCC(58, 0, 0, 1) /* ldu */ 4587 case AMOVWZ: 4588 return OPVCC(32, 0, 0, 0) /* lwz */ 4589 case AMOVWZU: 4590 return OPVCC(33, 0, 0, 0) /* lwzu */ 4591 case AMOVW: 4592 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4593 4594 /* no AMOVWU */ 4595 case AMOVB, AMOVBZ: 4596 return OPVCC(34, 0, 0, 0) 4597 /* load */ 4598 4599 case AMOVBU, AMOVBZU: 4600 return OPVCC(35, 0, 0, 0) 4601 case AFMOVD: 4602 return OPVCC(50, 0, 0, 0) 4603 case AFMOVDU: 4604 return OPVCC(51, 0, 0, 0) 4605 case AFMOVS: 4606 return OPVCC(48, 0, 0, 0) 4607 case AFMOVSU: 4608 return OPVCC(49, 0, 0, 0) 4609 case AMOVH: 4610 return OPVCC(42, 0, 0, 0) 4611 case AMOVHU: 4612 return OPVCC(43, 0, 0, 0) 4613 case AMOVHZ: 4614 return OPVCC(40, 0, 0, 0) 4615 case AMOVHZU: 4616 return OPVCC(41, 0, 0, 0) 4617 case AMOVMW: 4618 return OPVCC(46, 0, 0, 0) /* lmw */ 4619 } 4620 4621 c.ctxt.Diag("bad load opcode %v", a) 4622 return 0 4623 } 4624 4625 /* 4626 * indexed load a(b),d 4627 */ 4628 func (c *ctxt9) oploadx(a obj.As) uint32 { 4629 switch a { 4630 case AMOVWZ: 4631 return OPVCC(31, 23, 0, 0) /* lwzx */ 4632 case AMOVWZU: 4633 return OPVCC(31, 55, 0, 0) /* lwzux */ 4634 case AMOVW: 4635 return OPVCC(31, 341, 0, 0) /* lwax */ 4636 case AMOVWU: 4637 return OPVCC(31, 373, 0, 0) /* lwaux */ 4638 4639 case AMOVB, AMOVBZ: 4640 return OPVCC(31, 87, 0, 0) /* lbzx */ 4641 4642 case AMOVBU, AMOVBZU: 4643 return OPVCC(31, 119, 0, 0) /* lbzux */ 4644 case AFMOVD: 4645 return OPVCC(31, 599, 0, 0) /* lfdx */ 4646 case AFMOVDU: 4647 return OPVCC(31, 631, 0, 0) /* lfdux */ 4648 case AFMOVS: 4649 return OPVCC(31, 535, 0, 0) /* lfsx */ 4650 case AFMOVSU: 4651 return OPVCC(31, 567, 0, 0) /* lfsux */ 4652 case AFMOVSX: 4653 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4654 case AFMOVSZ: 4655 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4656 case AMOVH: 4657 return OPVCC(31, 343, 0, 0) /* lhax */ 4658 case AMOVHU: 4659 return OPVCC(31, 375, 0, 0) /* lhaux */ 4660 case AMOVHBR: 4661 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4662 case AMOVWBR: 4663 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4664 case AMOVDBR: 4665 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4666 case AMOVHZ: 4667 return OPVCC(31, 279, 0, 0) /* lhzx */ 4668 case AMOVHZU: 4669 return OPVCC(31, 311, 0, 0) /* lhzux */ 4670 case AECIWX: 4671 return OPVCC(31, 310, 0, 0) /* eciwx */ 4672 case ALBAR: 4673 return OPVCC(31, 52, 0, 0) /* lbarx */ 4674 case ALWAR: 4675 return OPVCC(31, 20, 0, 0) /* lwarx */ 4676 case ALDAR: 4677 return OPVCC(31, 84, 0, 0) 4678 case ALSW: 4679 return OPVCC(31, 533, 0, 0) /* lswx */ 4680 case AMOVD: 4681 return OPVCC(31, 21, 0, 0) /* ldx */ 4682 case AMOVDU: 4683 return OPVCC(31, 53, 0, 0) /* ldux */ 4684 case ALDMX: 4685 return OPVCC(31, 309, 0, 0) /* ldmx */ 4686 4687 /* Vector (VMX/Altivec) instructions */ 4688 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4689 /* are enabled starting at POWER6 (ISA 2.05). */ 4690 case ALVEBX: 4691 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4692 case ALVEHX: 4693 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4694 case ALVEWX: 4695 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4696 case ALVX: 4697 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4698 case ALVXL: 4699 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4700 case ALVSL: 4701 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4702 case ALVSR: 4703 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4704 /* End of vector instructions */ 4705 4706 /* Vector scalar (VSX) instructions */ 4707 /* ISA 2.06 enables these for POWER7. */ 4708 case ALXVD2X: 4709 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4710 case ALXVDSX: 4711 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4712 case ALXVW4X: 4713 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4714 4715 case ALXSDX: 4716 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4717 4718 case ALXSIWAX: 4719 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4720 case ALXSIWZX: 4721 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4722 /* End of vector scalar instructions */ 4723 4724 } 4725 4726 c.ctxt.Diag("bad loadx opcode %v", a) 4727 return 0 4728 } 4729 4730 /* 4731 * store s,o(d) 4732 */ 4733 func (c *ctxt9) opstore(a obj.As) uint32 { 4734 switch a { 4735 case AMOVB, AMOVBZ: 4736 return OPVCC(38, 0, 0, 0) /* stb */ 4737 4738 case AMOVBU, AMOVBZU: 4739 return OPVCC(39, 0, 0, 0) /* stbu */ 4740 case AFMOVD: 4741 return OPVCC(54, 0, 0, 0) /* stfd */ 4742 case AFMOVDU: 4743 return OPVCC(55, 0, 0, 0) /* stfdu */ 4744 case AFMOVS: 4745 return OPVCC(52, 0, 0, 0) /* stfs */ 4746 case AFMOVSU: 4747 return OPVCC(53, 0, 0, 0) /* stfsu */ 4748 4749 case AMOVHZ, AMOVH: 4750 return OPVCC(44, 0, 0, 0) /* sth */ 4751 4752 case AMOVHZU, AMOVHU: 4753 return OPVCC(45, 0, 0, 0) /* sthu */ 4754 case AMOVMW: 4755 return OPVCC(47, 0, 0, 0) /* stmw */ 4756 case ASTSW: 4757 return OPVCC(31, 725, 0, 0) /* stswi */ 4758 4759 case AMOVWZ, AMOVW: 4760 return OPVCC(36, 0, 0, 0) /* stw */ 4761 4762 case AMOVWZU, AMOVWU: 4763 return OPVCC(37, 0, 0, 0) /* stwu */ 4764 case AMOVD: 4765 return OPVCC(62, 0, 0, 0) /* std */ 4766 case AMOVDU: 4767 return OPVCC(62, 0, 0, 1) /* stdu */ 4768 } 4769 4770 c.ctxt.Diag("unknown store opcode %v", a) 4771 return 0 4772 } 4773 4774 /* 4775 * indexed store s,a(b) 4776 */ 4777 func (c *ctxt9) opstorex(a obj.As) uint32 { 4778 switch a { 4779 case AMOVB, AMOVBZ: 4780 return OPVCC(31, 215, 0, 0) /* stbx */ 4781 4782 case AMOVBU, AMOVBZU: 4783 return OPVCC(31, 247, 0, 0) /* stbux */ 4784 case AFMOVD: 4785 return OPVCC(31, 727, 0, 0) /* stfdx */ 4786 case AFMOVDU: 4787 return OPVCC(31, 759, 0, 0) /* stfdux */ 4788 case AFMOVS: 4789 return OPVCC(31, 663, 0, 0) /* stfsx */ 4790 case AFMOVSU: 4791 return OPVCC(31, 695, 0, 0) /* stfsux */ 4792 case AFMOVSX: 4793 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4794 4795 case AMOVHZ, AMOVH: 4796 return OPVCC(31, 407, 0, 0) /* sthx */ 4797 case AMOVHBR: 4798 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4799 4800 case AMOVHZU, AMOVHU: 4801 return OPVCC(31, 439, 0, 0) /* sthux */ 4802 4803 case AMOVWZ, AMOVW: 4804 return OPVCC(31, 151, 0, 0) /* stwx */ 4805 4806 case AMOVWZU, AMOVWU: 4807 return OPVCC(31, 183, 0, 0) /* stwux */ 4808 case ASTSW: 4809 return OPVCC(31, 661, 0, 0) /* stswx */ 4810 case AMOVWBR: 4811 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4812 case ASTBCCC: 4813 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4814 case ASTWCCC: 4815 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4816 case ASTDCCC: 4817 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4818 case AECOWX: 4819 return OPVCC(31, 438, 0, 0) /* ecowx */ 4820 case AMOVD: 4821 return OPVCC(31, 149, 0, 0) /* stdx */ 4822 case AMOVDU: 4823 return OPVCC(31, 181, 0, 0) /* stdux */ 4824 4825 /* Vector (VMX/Altivec) instructions */ 4826 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4827 /* are enabled starting at POWER6 (ISA 2.05). */ 4828 case ASTVEBX: 4829 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4830 case ASTVEHX: 4831 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4832 case ASTVEWX: 4833 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4834 case ASTVX: 4835 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4836 case ASTVXL: 4837 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4838 /* End of vector instructions */ 4839 4840 /* Vector scalar (VSX) instructions */ 4841 /* ISA 2.06 enables these for POWER7. */ 4842 case ASTXVD2X: 4843 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4844 case ASTXVW4X: 4845 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4846 4847 case ASTXSDX: 4848 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4849 4850 case ASTXSIWX: 4851 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4852 /* End of vector scalar instructions */ 4853 4854 } 4855 4856 c.ctxt.Diag("unknown storex opcode %v", a) 4857 return 0 4858 }