code.gitea.io/gitea@v1.21.7/options/gitignore/SynopsysVCS (about)

     1  # Waveform formats
     2  *.vcd
     3  *.vpd
     4  *.evcd
     5  *.fsdb
     6  
     7  # Default name of the simulation executable.  A different name can be
     8  # specified with this switch (the associated daidir database name is
     9  # also taken from here):  -o <path>/<filename>
    10  simv
    11  
    12  # Generated for Verilog and VHDL top configs
    13  simv.daidir/
    14  simv.db.dir/
    15  
    16  # Infrastructure necessary to co-simulate SystemC models with
    17  # Verilog/VHDL models.  An alternate directory may be specified with this
    18  # switch:  -Mdir=<directory_path>
    19  csrc/
    20  
    21  # Log file - the following switch allows to specify the file that will be
    22  # used to write all messages from simulation:  -l <filename>
    23  *.log
    24  
    25  # Coverage results (generated with urg) and database location.  The
    26  # following switch can also be used:  urg -dir <coverage_directory>.vdb
    27  simv.vdb/
    28  urgReport/
    29  
    30  # DVE and UCLI related files.
    31  DVEfiles/
    32  ucli.key
    33  
    34  # When the design is elaborated for DirectC, the following file is created
    35  # with declarations for C/C++ functions.
    36  vc_hdrs.h