gitee.com/mysnapcore/mysnapd@v0.1.0/interfaces/builtin/fpga.go (about)

     1  // -*- Mode: Go; indent-tabs-mode: t -*-
     2  
     3  /*
     4   * Copyright (C) 2020 Canonical Ltd
     5   *
     6   * This program is free software: you can redistribute it and/or modify
     7   * it under the terms of the GNU General Public License version 3 as
     8   * published by the Free Software Foundation.
     9   *
    10   * This program is distributed in the hope that it will be useful,
    11   * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13   * GNU General Public License for more details.
    14   *
    15   * You should have received a copy of the GNU General Public License
    16   * along with this program.  If not, see <http://www.gnu.org/licenses/>.
    17   *
    18   */
    19  
    20  package builtin
    21  
    22  const fpgaSummary = `allows access to the FPGA subsystem`
    23  
    24  const fpgaBaseDeclarationSlots = `
    25    fpga:
    26      allow-installation:
    27        slot-snap-type:
    28          - core
    29      deny-auto-connection: true
    30  `
    31  
    32  const fpgaConnectedPlugAppArmor = `
    33  # Description: Can access fpga subsystem.
    34  
    35  # Devices
    36  /dev/fpga[0-9]* rw,
    37  
    38  # /sys/class/fpga_* specified by:
    39  # https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-manager
    40  # https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-region
    41  # https://github.com/torvalds/linux/blob/master/Documentation/ABI/testing/sysfs-class-fpga-bridge
    42  /sys/class/fpga_manager/fpga[0-9]*/{name,state,status} r,
    43  /sys/class/fpga_region/region[0-9]*/compat_id r,
    44  /sys/class/fpga_bridge/bridge[0-9]*/{name,state} r,
    45  
    46  # Xilinx zynqmp FPGA, created by zynqmp_fpga_manager driver
    47  # https://github.com/torvalds/linux/blob/master/drivers/fpga/zynqmp-fpga.c
    48  /sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/{name,state,status} r,
    49  /sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/firmware w,
    50  /sys/devices/platform/firmware:zynqmp-firmware/firmware:zynqmp-firmware:pcap/fpga_manager/fpga[0-9]*/{flags,key} rw,
    51  /sys/devices/platform/fpga-full/fpga_region/region[0-9]*/compat_id r,
    52  
    53  # Xilinx zynqmp module parameters (not upstreamed yet)
    54  # https://github.com/Xilinx/linux-xlnx/blob/master/drivers/fpga/zynqmp-fpga.c#L36
    55  /sys/module/zynqmp_fpga/parameters/readback_type rw,
    56  `
    57  
    58  var fpgaConnectedPlugUDev = []string{
    59  	`SUBSYSTEM=="misc", KERNEL=="fpga[0-9]*"`,
    60  }
    61  
    62  func init() {
    63  	registerIface(&commonInterface{
    64  		name:                  "fpga",
    65  		summary:               fpgaSummary,
    66  		implicitOnCore:        true,
    67  		implicitOnClassic:     true,
    68  		baseDeclarationSlots:  fpgaBaseDeclarationSlots,
    69  		connectedPlugAppArmor: fpgaConnectedPlugAppArmor,
    70  		connectedPlugUDev:     fpgaConnectedPlugUDev,
    71  	})
    72  }