github.com/4ad/go@v0.0.0-20161219182952-69a12818b605/src/cmd/internal/obj/sparc64/a.out.go (about) 1 // Copyright 2015 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package sparc64 6 7 import "cmd/internal/obj" 8 9 // General purpose registers, kept in the low bits of Prog.Reg. 10 const ( 11 // integer 12 REG_G0 = obj.RBaseSPARC64 + iota 13 REG_G1 14 REG_G2 15 REG_G3 16 REG_G4 17 REG_G5 18 REG_G6 19 REG_G7 20 REG_O0 21 REG_O1 22 REG_O2 23 REG_O3 24 REG_O4 25 REG_O5 26 REG_O6 27 REG_O7 28 REG_L0 29 REG_L1 30 REG_L2 31 REG_L3 32 REG_L4 33 REG_L5 34 REG_L6 35 REG_L7 36 REG_I0 37 REG_I1 38 REG_I2 39 REG_I3 40 REG_I4 41 REG_I5 42 REG_I6 43 REG_I7 44 45 // single-precision floating point 46 REG_F0 47 REG_F1 48 REG_F2 49 REG_F3 50 REG_F4 51 REG_F5 52 REG_F6 53 REG_F7 54 REG_F8 55 REG_F9 56 REG_F10 57 REG_F11 58 REG_F12 59 REG_F13 60 REG_F14 61 REG_F15 62 REG_F16 63 REG_F17 64 REG_F18 65 REG_F19 66 REG_F20 67 REG_F21 68 REG_F22 69 REG_F23 70 REG_F24 71 REG_F25 72 REG_F26 73 REG_F27 74 REG_F28 75 REG_F29 76 REG_F30 77 REG_F31 78 79 // double-precision floating point; the first half is aliased to 80 // single-precision registers, that is: Dn is aliased to Fn, Fn+1, 81 // where n ≤ 30. 82 REG_D0 83 REG_D32 84 REG_D2 85 REG_D34 86 REG_D4 87 REG_D36 88 REG_D6 89 REG_D38 90 REG_D8 91 REG_D40 92 REG_D10 93 REG_D42 94 REG_D12 95 REG_D44 96 REG_D14 97 REG_D46 98 REG_D16 99 REG_D48 100 REG_D18 101 REG_D50 102 REG_D20 103 REG_D52 104 REG_D22 105 REG_D54 106 REG_D24 107 REG_D56 108 REG_D26 109 REG_D58 110 REG_D28 111 REG_D60 112 REG_D30 113 REG_D62 114 115 // common single/double-precision virtualized registers. 116 // Yn is aliased to F2n, F2n+1, D2n. 117 REG_Y0 118 REG_Y1 119 REG_Y2 120 REG_Y3 121 REG_Y4 122 REG_Y5 123 REG_Y6 124 REG_Y7 125 REG_Y8 126 REG_Y9 127 REG_Y10 128 REG_Y11 129 REG_Y12 130 REG_Y13 131 REG_Y14 132 REG_Y15 133 ) 134 135 const ( 136 // floating-point condition-code registers 137 REG_FCC0 = REG_G0 + 256 + iota 138 REG_FCC1 139 REG_FCC2 140 REG_FCC3 141 ) 142 143 const ( 144 // integer condition-code flags 145 REG_ICC = REG_G0 + 384 146 REG_XCC = REG_G0 + 384 + 2 147 ) 148 149 const ( 150 REG_SPECIAL = REG_G0 + 512 151 152 REG_CCR = REG_SPECIAL + 2 153 REG_TICK = REG_SPECIAL + 4 154 REG_RPC = REG_SPECIAL + 5 155 156 REG_BSP = REG_RSP + 256 157 REG_BFP = REG_RFP + 256 158 159 REG_LAST = REG_G0 + 1024 160 ) 161 162 // Register assignments: 163 const ( 164 REG_ZR = REG_G0 165 REG_RT1 = REG_G1 166 REG_CTXT = REG_G2 167 REG_G = REG_G3 168 REG_RT2 = REG_G4 169 REG_TMP = REG_G5 170 REG_TLS = REG_G7 171 REG_RSP = REG_O6 172 REG_OLR = REG_O7 173 REG_TMP2 = REG_L0 174 REG_RFP = REG_I6 175 REG_ILR = REG_I7 176 REG_FTMP = REG_F30 177 REG_DTMP = REG_D30 178 REG_YTMP = REG_Y15 179 REG_YTWO = REG_Y14 180 ) 181 182 const ( 183 REG_MIN = REG_G0 184 REG_MAX = REG_I5 185 ) 186 187 const ( 188 StackBias = 0x7ff // craziness 189 WindowSaveAreaSize = 16 * 8 // only slots for RFP and PLR used 190 ArgumentsSaveAreaSize = 6 * 8 // unused 191 MinStackFrameSize = WindowSaveAreaSize + ArgumentsSaveAreaSize 192 ) 193 194 const ( 195 BIG = 1<<12 - 1 // magnitude of smallest negative immediate 196 ) 197 198 // Prog.mark 199 const ( 200 FOLL = 1 << iota 201 LABEL 202 LEAF 203 ) 204 205 const ( 206 ClassUnknown = iota 207 208 ClassReg // R1..R31 209 ClassFReg // F0..F31 210 ClassDReg // D0..D62 211 ClassCond // ICC, XCC 212 ClassFCond // FCC0..FCC3 213 ClassSpcReg // TICK, CCR, etc 214 215 ClassZero // $0 or ZR 216 ClassConst5 // unsigned 5-bit constant 217 ClassConst6 // unsigned 6-bit constant 218 ClassConst10 // signed 10-bit constant 219 ClassConst11 // signed 11-bit constant 220 ClassConst13 // signed 13-bit constant 221 ClassConst31_ // signed 32-bit constant, negative 222 ClassConst31 // signed 32-bit constant, positive or zero 223 ClassConst32 // 32-bit constant 224 ClassConst // 64-bit constant 225 ClassFConst // floating-point constant 226 227 ClassRegReg // $(Rn+Rm) or $(Rn)(Rm*1) 228 ClassRegConst13 // $n(R), n is 13-bit signed 229 ClassRegConst // $n(R), n large 230 231 ClassIndirRegReg // (Rn+Rm) or (Rn)(Rm*1) 232 ClassIndir0 // (R) 233 ClassIndir13 // n(R), n is 13-bit signed 234 ClassIndir // n(R), n large 235 236 ClassBranch // n(PC) branch target, n is 21-bit signed, mod 4 237 ClassLargeBranch // n(PC) branch target, n is 32-bit signed, mod 4 238 239 ClassAddr // $sym(SB) 240 ClassMem // sym(SB) 241 ClassTLSAddr // $tlssym(SB) 242 ClassTLSMem // tlssym(SB) 243 244 ClassTextSize 245 ClassNone 246 247 ClassBias = 64 // BFP or BSP present in Addr, bitwise OR with classes above 248 ) 249 250 var cnames = []string{ 251 ClassUnknown: "ClassUnknown", 252 ClassReg: "ClassReg", 253 ClassFReg: "ClassFReg", 254 ClassDReg: "ClassDReg", 255 ClassCond: "ClassCond", 256 ClassFCond: "ClassFCond", 257 ClassSpcReg: "ClassSpcReg", 258 ClassZero: "ClassZero", 259 ClassConst5: "ClassConst5", 260 ClassConst6: "ClassConst6", 261 ClassConst10: "ClassConst10", 262 ClassConst11: "ClassConst11", 263 ClassConst13: "ClassConst13", 264 ClassConst31_: "ClassConst31-", 265 ClassConst31: "ClassConst31+", 266 ClassConst32: "ClassConst32", 267 ClassConst: "ClassConst", 268 ClassFConst: "ClassFConst", 269 ClassRegReg: "ClassRegReg", 270 ClassRegConst13: "ClassRegConst13", 271 ClassRegConst: "ClassRegConst", 272 ClassIndirRegReg: "ClassIndirRegReg", 273 ClassIndir0: "ClassIndir0", 274 ClassIndir13: "ClassIndir13", 275 ClassIndir: "ClassIndir", 276 ClassBranch: "ClassBranch", 277 ClassLargeBranch: "ClassLargeBranch", 278 ClassAddr: "ClassAddr", 279 ClassMem: "ClassMem", 280 ClassTLSAddr: "ClassTLSAddr", 281 ClassTLSMem: "ClassTLSMem", 282 ClassTextSize: "ClassTextSize", 283 ClassNone: "ClassNone", 284 ClassBias: "ClassBias", 285 } 286 287 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p sparc64 288 289 const ( 290 AADD = obj.ABaseSPARC64 + obj.A_ARCHSPECIFIC + iota 291 AADDCC 292 AADDC 293 AADDCCC 294 AAND 295 AANDCC 296 AANDN 297 AANDNCC 298 299 // These are the two-operand SPARCv9 32-, and 64-bit, branch 300 // on integer condition codes with prediction (BPcc), not the 301 // single-operand SPARCv8 32-bit branch on integer condition 302 // codes (Bicc). 303 ABN 304 ABNE 305 ABE 306 ABG 307 ABLE 308 ABGE 309 ABL 310 ABGU 311 ABLEU 312 ABCC 313 ABCS 314 ABPOS 315 ABNEG 316 ABVC 317 ABVS 318 319 ABRZ 320 ABRLEZ 321 ABRLZ 322 ABRNZ 323 ABRGZ 324 ABRGEZ 325 ACASW 326 ACASD 327 AFABSS 328 AFABSD 329 AFADDS 330 AFADDD 331 AFBA 332 AFBN 333 AFBU 334 AFBG 335 AFBUG 336 AFBL 337 AFBUL 338 AFBLG 339 AFBNE 340 AFBE 341 AFBUE 342 AFBGE 343 AFBUGE 344 AFBLE 345 AFBULE 346 AFBO 347 AFCMPS 348 AFCMPD 349 AFDIVS 350 AFDIVD 351 AFITOS 352 AFITOD 353 AFLUSH 354 AFLUSHW 355 AFMOVS // the SPARC64 instruction, and alias for loads and stores 356 AFMOVD // the SPARC64 instruction, and alias for loads and stores 357 AFMULS 358 AFMULD 359 AFSMULD 360 AFNEGS 361 AFNEGD 362 AFSQRTS 363 AFSQRTD 364 AFSTOX 365 AFDTOX 366 AFSTOI 367 AFDTOI 368 AFSTOD 369 AFDTOS 370 AFSUBS 371 AFSUBD 372 AFXTOS 373 AFXTOD 374 AJMPL 375 ALDSB 376 ALDSH 377 ALDSW 378 ALDUB 379 ALDD 380 ALDDF 381 ALDSF 382 ALDUH 383 ALDUW 384 AMEMBAR 385 AMOVA 386 AMOVCC 387 AMOVCS 388 AMOVE 389 AMOVG 390 AMOVGE 391 AMOVGU 392 AMOVL 393 AMOVLE 394 AMOVLEU 395 AMOVN 396 AMOVNE 397 AMOVNEG 398 AMOVPOS 399 AMOVRGEZ 400 AMOVRGZ 401 AMOVRLEZ 402 AMOVRLZ 403 AMOVRNZ 404 AMOVRZ 405 AMOVVC 406 AMOVVS 407 AMULD 408 AOR 409 AORCC 410 AORN 411 AORNCC 412 ARD 413 ARESTORE // not used under normal circumstances 414 ASAVE // not used under normal circumstances 415 ASDIVD 416 ASETHI 417 AUDIVD 418 ASLLW 419 ASRLW 420 ASRAW 421 ASLLD 422 ASRLD 423 ASRAD 424 ASTB 425 ASTH 426 ASTW 427 ASTD 428 ASTSF 429 ASTDF 430 ASUB 431 ASUBCC 432 ASUBC 433 ASUBCCC 434 ATA 435 AXOR 436 AXORCC 437 AXNOR 438 AXNORCC 439 440 // Pseudo-instructions, aliases to SPARC64 instructions and 441 // synthetic instructions. 442 ACMP // SUBCC R1, R2, ZR 443 ANEG 444 AMOVUB 445 AMOVB 446 AMOVUH 447 AMOVH 448 AMOVUW 449 AMOVW 450 AMOVD // also the SPARC64 synthetic instruction 451 ARNOP // SETHI $0, ZR 452 453 // These are aliases to two-operand SPARCv9 32-, and 64-bit, 454 // branch on integer condition codes with prediction (BPcc), 455 // with ICC implied. 456 ABNW 457 ABNEW 458 ABEW 459 ABGW 460 ABLEW 461 ABGEW 462 ABLW 463 ABGUW 464 ABLEUW 465 ABCCW 466 ABCSW 467 ABPOSW 468 ABNEGW 469 ABVCW 470 ABVSW 471 472 // These are aliases to two-operand SPARCv9 32-, and 64-bit, 473 // branch on integer condition codes with prediction (BPcc), 474 // with XCC implied. 475 ABND 476 ABNED 477 ABED 478 ABGD 479 ABLED 480 ABGED 481 ABLD 482 ABGUD 483 ABLEUD 484 ABCCD 485 ABCSD 486 ABPOSD 487 ABNEGD 488 ABVCD 489 ABVSD 490 491 AWORD 492 ADWORD 493 494 // JMPL $8(ILR), ZR 495 // RESTORE $0, ZR, ZR 496 ARETRESTORE 497 498 ALAST 499 )