github.com/ActiveState/go@v0.0.0-20170614201249-0b81c023a722/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 16 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 366 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 367 368 /* Vector instructions */ 369 370 /* Vector load */ 371 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 372 373 /* Vector store */ 374 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 375 376 /* Vector logical */ 377 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 378 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 379 380 /* Vector add */ 381 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 382 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 383 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 384 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 385 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 386 387 /* Vector subtract */ 388 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 389 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 390 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 391 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 392 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 393 394 /* Vector multiply */ 395 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 396 397 /* Vector rotate */ 398 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 399 400 /* Vector shift */ 401 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 402 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 403 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 404 405 /* Vector count */ 406 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 407 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 408 409 /* Vector compare */ 410 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 411 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 412 413 /* Vector permute */ 414 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 415 416 /* Vector select */ 417 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 418 419 /* Vector splat */ 420 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 421 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 422 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 423 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 424 425 /* Vector AES */ 426 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 427 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 428 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 429 430 /* Vector SHA */ 431 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 432 433 /* VSX vector load */ 434 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 435 436 /* VSX vector store */ 437 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 438 439 /* VSX scalar load */ 440 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 441 442 /* VSX scalar store */ 443 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 444 445 /* VSX scalar as integer load */ 446 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 447 448 /* VSX scalar store as integer */ 449 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 450 451 /* VSX move from VSR */ 452 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 453 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 454 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 455 456 /* VSX move to VSR */ 457 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 458 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 459 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 460 461 /* VSX logical */ 462 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 463 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 464 465 /* VSX select */ 466 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 467 468 /* VSX merge */ 469 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 470 471 /* VSX splat */ 472 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 473 474 /* VSX permute */ 475 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 476 477 /* VSX shift */ 478 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 479 480 /* VSX scalar FP-FP conversion */ 481 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 482 483 /* VSX vector FP-FP conversion */ 484 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 485 486 /* VSX scalar FP-integer conversion */ 487 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 488 489 /* VSX scalar integer-FP conversion */ 490 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 491 492 /* VSX vector FP-integer conversion */ 493 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 494 495 /* VSX vector integer-FP conversion */ 496 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 497 498 /* 64-bit special registers */ 499 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 500 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 501 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 502 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 503 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 504 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 505 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 506 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 507 508 /* 32-bit special registers (gloss over sign-extension or not?) */ 509 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 510 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 511 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 512 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 513 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 514 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 515 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 516 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 517 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 518 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 519 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 520 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 521 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 522 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 523 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 524 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 525 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 526 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 527 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 528 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 529 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 530 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 531 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 532 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 533 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 534 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 535 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 536 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 537 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 538 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 539 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 540 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 541 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 542 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 543 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 544 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 545 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 546 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 547 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 548 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 549 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 550 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 551 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 552 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 553 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 554 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 555 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 556 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 557 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 558 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 559 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 560 561 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 562 } 563 564 var oprange [ALAST & obj.AMask][]Optab 565 566 var xcmp [C_NCLASS][C_NCLASS]bool 567 568 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 569 p := cursym.Func.Text 570 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 571 return 572 } 573 574 if oprange[AANDN&obj.AMask] == nil { 575 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 576 } 577 578 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 579 580 pc := int64(0) 581 p.Pc = pc 582 583 var m int 584 var o *Optab 585 for p = p.Link; p != nil; p = p.Link { 586 p.Pc = pc 587 o = c.oplook(p) 588 m = int(o.size) 589 if m == 0 { 590 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 591 c.ctxt.Diag("zero-width instruction\n%v", p) 592 } 593 continue 594 } 595 596 pc += int64(m) 597 } 598 599 c.cursym.Size = pc 600 601 /* 602 * if any procedure is large enough to 603 * generate a large SBRA branch, then 604 * generate extra passes putting branches 605 * around jmps to fix. this is rare. 606 */ 607 bflag := 1 608 609 var otxt int64 610 var q *obj.Prog 611 for bflag != 0 { 612 bflag = 0 613 pc = 0 614 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 615 p.Pc = pc 616 o = c.oplook(p) 617 618 // very large conditional branches 619 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 620 otxt = p.Pcond.Pc - pc 621 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 622 q = c.newprog() 623 q.Link = p.Link 624 p.Link = q 625 q.As = ABR 626 q.To.Type = obj.TYPE_BRANCH 627 q.Pcond = p.Pcond 628 p.Pcond = q 629 q = c.newprog() 630 q.Link = p.Link 631 p.Link = q 632 q.As = ABR 633 q.To.Type = obj.TYPE_BRANCH 634 q.Pcond = q.Link.Link 635 636 //addnop(p->link); 637 //addnop(p); 638 bflag = 1 639 } 640 } 641 642 m = int(o.size) 643 if m == 0 { 644 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 645 c.ctxt.Diag("zero-width instruction\n%v", p) 646 } 647 continue 648 } 649 650 pc += int64(m) 651 } 652 653 c.cursym.Size = pc 654 } 655 656 pc += -pc & (funcAlign - 1) 657 c.cursym.Size = pc 658 659 /* 660 * lay out the code, emitting code and data relocations. 661 */ 662 663 c.cursym.Grow(c.cursym.Size) 664 665 bp := c.cursym.P 666 var i int32 667 var out [6]uint32 668 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 669 c.pc = p.Pc 670 o = c.oplook(p) 671 if int(o.size) > 4*len(out) { 672 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 673 } 674 c.asmout(p, o, out[:]) 675 for i = 0; i < int32(o.size/4); i++ { 676 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 677 bp = bp[4:] 678 } 679 } 680 } 681 682 func isint32(v int64) bool { 683 return int64(int32(v)) == v 684 } 685 686 func isuint32(v uint64) bool { 687 return uint64(uint32(v)) == v 688 } 689 690 func (c *ctxt9) aclass(a *obj.Addr) int { 691 switch a.Type { 692 case obj.TYPE_NONE: 693 return C_NONE 694 695 case obj.TYPE_REG: 696 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 697 return C_REG 698 } 699 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 700 return C_FREG 701 } 702 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 703 return C_VREG 704 } 705 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 706 return C_VSREG 707 } 708 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 709 return C_CREG 710 } 711 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 712 switch a.Reg { 713 case REG_LR: 714 return C_LR 715 716 case REG_XER: 717 return C_XER 718 719 case REG_CTR: 720 return C_CTR 721 } 722 723 return C_SPR 724 } 725 726 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 727 return C_SPR 728 } 729 if a.Reg == REG_FPSCR { 730 return C_FPSCR 731 } 732 if a.Reg == REG_MSR { 733 return C_MSR 734 } 735 return C_GOK 736 737 case obj.TYPE_MEM: 738 switch a.Name { 739 case obj.NAME_EXTERN, 740 obj.NAME_STATIC: 741 if a.Sym == nil { 742 break 743 } 744 c.instoffset = a.Offset 745 if a.Sym != nil { // use relocation 746 if a.Sym.Type == objabi.STLSBSS { 747 if c.ctxt.Flag_shared { 748 return C_TLS_IE 749 } else { 750 return C_TLS_LE 751 } 752 } 753 return C_ADDR 754 } 755 return C_LEXT 756 757 case obj.NAME_GOTREF: 758 return C_GOTADDR 759 760 case obj.NAME_AUTO: 761 c.instoffset = int64(c.autosize) + a.Offset 762 if c.instoffset >= -BIG && c.instoffset < BIG { 763 return C_SAUTO 764 } 765 return C_LAUTO 766 767 case obj.NAME_PARAM: 768 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 769 if c.instoffset >= -BIG && c.instoffset < BIG { 770 return C_SAUTO 771 } 772 return C_LAUTO 773 774 case obj.NAME_NONE: 775 c.instoffset = a.Offset 776 if c.instoffset == 0 { 777 return C_ZOREG 778 } 779 if c.instoffset >= -BIG && c.instoffset < BIG { 780 return C_SOREG 781 } 782 return C_LOREG 783 } 784 785 return C_GOK 786 787 case obj.TYPE_TEXTSIZE: 788 return C_TEXTSIZE 789 790 case obj.TYPE_CONST, 791 obj.TYPE_ADDR: 792 switch a.Name { 793 case obj.NAME_NONE: 794 c.instoffset = a.Offset 795 if a.Reg != 0 { 796 if -BIG <= c.instoffset && c.instoffset <= BIG { 797 return C_SACON 798 } 799 if isint32(c.instoffset) { 800 return C_LACON 801 } 802 return C_DACON 803 } 804 805 goto consize 806 807 case obj.NAME_EXTERN, 808 obj.NAME_STATIC: 809 s := a.Sym 810 if s == nil { 811 break 812 } 813 814 c.instoffset = a.Offset 815 816 /* not sure why this barfs */ 817 return C_LCON 818 819 case obj.NAME_AUTO: 820 c.instoffset = int64(c.autosize) + a.Offset 821 if c.instoffset >= -BIG && c.instoffset < BIG { 822 return C_SACON 823 } 824 return C_LACON 825 826 case obj.NAME_PARAM: 827 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 828 if c.instoffset >= -BIG && c.instoffset < BIG { 829 return C_SACON 830 } 831 return C_LACON 832 } 833 834 return C_GOK 835 836 consize: 837 if c.instoffset >= 0 { 838 if c.instoffset == 0 { 839 return C_ZCON 840 } 841 if c.instoffset <= 0x7fff { 842 return C_SCON 843 } 844 if c.instoffset <= 0xffff { 845 return C_ANDCON 846 } 847 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 848 return C_UCON 849 } 850 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 851 return C_LCON 852 } 853 return C_DCON 854 } 855 856 if c.instoffset >= -0x8000 { 857 return C_ADDCON 858 } 859 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 860 return C_UCON 861 } 862 if isint32(c.instoffset) { 863 return C_LCON 864 } 865 return C_DCON 866 867 case obj.TYPE_BRANCH: 868 if a.Sym != nil && c.ctxt.Flag_dynlink { 869 return C_LBRAPIC 870 } 871 return C_SBRA 872 } 873 874 return C_GOK 875 } 876 877 func prasm(p *obj.Prog) { 878 fmt.Printf("%v\n", p) 879 } 880 881 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 882 a1 := int(p.Optab) 883 if a1 != 0 { 884 return &optab[a1-1] 885 } 886 a1 = int(p.From.Class) 887 if a1 == 0 { 888 a1 = c.aclass(&p.From) + 1 889 p.From.Class = int8(a1) 890 } 891 892 a1-- 893 a3 := C_NONE + 1 894 if p.From3 != nil { 895 a3 = int(p.From3.Class) 896 if a3 == 0 { 897 a3 = c.aclass(p.From3) + 1 898 p.From3.Class = int8(a3) 899 } 900 } 901 902 a3-- 903 a4 := int(p.To.Class) 904 if a4 == 0 { 905 a4 = c.aclass(&p.To) + 1 906 p.To.Class = int8(a4) 907 } 908 909 a4-- 910 a2 := C_NONE 911 if p.Reg != 0 { 912 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 913 a2 = C_REG 914 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 915 a2 = C_VREG 916 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 917 a2 = C_VSREG 918 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 919 a2 = C_FREG 920 } 921 } 922 923 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 924 ops := oprange[p.As&obj.AMask] 925 c1 := &xcmp[a1] 926 c3 := &xcmp[a3] 927 c4 := &xcmp[a4] 928 for i := range ops { 929 op := &ops[i] 930 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 931 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 932 return op 933 } 934 } 935 936 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 937 prasm(p) 938 if ops == nil { 939 ops = optab 940 } 941 return &ops[0] 942 } 943 944 func cmp(a int, b int) bool { 945 if a == b { 946 return true 947 } 948 switch a { 949 case C_LCON: 950 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 951 return true 952 } 953 954 case C_ADDCON: 955 if b == C_ZCON || b == C_SCON { 956 return true 957 } 958 959 case C_ANDCON: 960 if b == C_ZCON || b == C_SCON { 961 return true 962 } 963 964 case C_SPR: 965 if b == C_LR || b == C_XER || b == C_CTR { 966 return true 967 } 968 969 case C_UCON: 970 if b == C_ZCON { 971 return true 972 } 973 974 case C_SCON: 975 if b == C_ZCON { 976 return true 977 } 978 979 case C_LACON: 980 if b == C_SACON { 981 return true 982 } 983 984 case C_LBRA: 985 if b == C_SBRA { 986 return true 987 } 988 989 case C_LEXT: 990 if b == C_SEXT { 991 return true 992 } 993 994 case C_LAUTO: 995 if b == C_SAUTO { 996 return true 997 } 998 999 case C_REG: 1000 if b == C_ZCON { 1001 return r0iszero != 0 /*TypeKind(100016)*/ 1002 } 1003 1004 case C_LOREG: 1005 if b == C_ZOREG || b == C_SOREG { 1006 return true 1007 } 1008 1009 case C_SOREG: 1010 if b == C_ZOREG { 1011 return true 1012 } 1013 1014 case C_ANY: 1015 return true 1016 } 1017 1018 return false 1019 } 1020 1021 type ocmp []Optab 1022 1023 func (x ocmp) Len() int { 1024 return len(x) 1025 } 1026 1027 func (x ocmp) Swap(i, j int) { 1028 x[i], x[j] = x[j], x[i] 1029 } 1030 1031 func (x ocmp) Less(i, j int) bool { 1032 p1 := &x[i] 1033 p2 := &x[j] 1034 n := int(p1.as) - int(p2.as) 1035 if n != 0 { 1036 return n < 0 1037 } 1038 n = int(p1.a1) - int(p2.a1) 1039 if n != 0 { 1040 return n < 0 1041 } 1042 n = int(p1.a2) - int(p2.a2) 1043 if n != 0 { 1044 return n < 0 1045 } 1046 n = int(p1.a3) - int(p2.a3) 1047 if n != 0 { 1048 return n < 0 1049 } 1050 n = int(p1.a4) - int(p2.a4) 1051 if n != 0 { 1052 return n < 0 1053 } 1054 return false 1055 } 1056 func opset(a, b0 obj.As) { 1057 oprange[a&obj.AMask] = oprange[b0] 1058 } 1059 1060 func buildop(ctxt *obj.Link) { 1061 if oprange[AANDN&obj.AMask] != nil { 1062 // Already initialized; stop now. 1063 // This happens in the cmd/asm tests, 1064 // each of which re-initializes the arch. 1065 return 1066 } 1067 1068 var n int 1069 1070 for i := 0; i < C_NCLASS; i++ { 1071 for n = 0; n < C_NCLASS; n++ { 1072 if cmp(n, i) { 1073 xcmp[i][n] = true 1074 } 1075 } 1076 } 1077 for n = 0; optab[n].as != obj.AXXX; n++ { 1078 } 1079 sort.Sort(ocmp(optab[:n])) 1080 for i := 0; i < n; i++ { 1081 r := optab[i].as 1082 r0 := r & obj.AMask 1083 start := i 1084 for optab[i].as == r { 1085 i++ 1086 } 1087 oprange[r0] = optab[start:i] 1088 i-- 1089 1090 switch r { 1091 default: 1092 ctxt.Diag("unknown op in build: %v", r) 1093 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1094 1095 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1096 opset(ADCBI, r0) 1097 1098 opset(ADCBST, r0) 1099 opset(ADCBT, r0) 1100 opset(ADCBTST, r0) 1101 opset(ADCBZ, r0) 1102 opset(AICBI, r0) 1103 1104 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1105 opset(ASTWCCC, r0) 1106 opset(ASTBCCC, r0) 1107 1108 opset(ASTDCCC, r0) 1109 1110 case AREM: /* macro */ 1111 opset(AREMCC, r0) 1112 1113 opset(AREMV, r0) 1114 opset(AREMVCC, r0) 1115 1116 case AREMU: 1117 opset(AREMU, r0) 1118 opset(AREMUCC, r0) 1119 opset(AREMUV, r0) 1120 opset(AREMUVCC, r0) 1121 1122 case AREMD: 1123 opset(AREMDCC, r0) 1124 opset(AREMDV, r0) 1125 opset(AREMDVCC, r0) 1126 1127 case AREMDU: 1128 opset(AREMDU, r0) 1129 opset(AREMDUCC, r0) 1130 opset(AREMDUV, r0) 1131 opset(AREMDUVCC, r0) 1132 1133 case ADIVW: /* op Rb[,Ra],Rd */ 1134 opset(AMULHW, r0) 1135 1136 opset(AMULHWCC, r0) 1137 opset(AMULHWU, r0) 1138 opset(AMULHWUCC, r0) 1139 opset(AMULLWCC, r0) 1140 opset(AMULLWVCC, r0) 1141 opset(AMULLWV, r0) 1142 opset(ADIVWCC, r0) 1143 opset(ADIVWV, r0) 1144 opset(ADIVWVCC, r0) 1145 opset(ADIVWU, r0) 1146 opset(ADIVWUCC, r0) 1147 opset(ADIVWUV, r0) 1148 opset(ADIVWUVCC, r0) 1149 opset(AADDCC, r0) 1150 opset(AADDCV, r0) 1151 opset(AADDCVCC, r0) 1152 opset(AADDV, r0) 1153 opset(AADDVCC, r0) 1154 opset(AADDE, r0) 1155 opset(AADDECC, r0) 1156 opset(AADDEV, r0) 1157 opset(AADDEVCC, r0) 1158 opset(ACRAND, r0) 1159 opset(ACRANDN, r0) 1160 opset(ACREQV, r0) 1161 opset(ACRNAND, r0) 1162 opset(ACRNOR, r0) 1163 opset(ACROR, r0) 1164 opset(ACRORN, r0) 1165 opset(ACRXOR, r0) 1166 opset(AMULHD, r0) 1167 opset(AMULHDCC, r0) 1168 opset(AMULHDU, r0) 1169 opset(AMULHDUCC, r0) 1170 opset(AMULLD, r0) 1171 opset(AMULLDCC, r0) 1172 opset(AMULLDVCC, r0) 1173 opset(AMULLDV, r0) 1174 opset(ADIVD, r0) 1175 opset(ADIVDCC, r0) 1176 opset(ADIVDE, r0) 1177 opset(ADIVDEU, r0) 1178 opset(ADIVDECC, r0) 1179 opset(ADIVDEUCC, r0) 1180 opset(ADIVDVCC, r0) 1181 opset(ADIVDV, r0) 1182 opset(ADIVDU, r0) 1183 opset(ADIVDUCC, r0) 1184 opset(ADIVDUVCC, r0) 1185 opset(ADIVDUCC, r0) 1186 1187 case APOPCNTD: 1188 opset(APOPCNTW, r0) 1189 opset(APOPCNTB, r0) 1190 1191 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1192 opset(AMOVH, r0) 1193 1194 opset(AMOVHZ, r0) 1195 1196 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1197 opset(AMOVHU, r0) 1198 1199 opset(AMOVHZU, r0) 1200 opset(AMOVWU, r0) 1201 opset(AMOVWZU, r0) 1202 opset(AMOVDU, r0) 1203 opset(AMOVMW, r0) 1204 1205 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1206 opset(ALVEBX, r0) 1207 opset(ALVEHX, r0) 1208 opset(ALVEWX, r0) 1209 opset(ALVX, r0) 1210 opset(ALVXL, r0) 1211 opset(ALVSL, r0) 1212 opset(ALVSR, r0) 1213 1214 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1215 opset(ASTVEBX, r0) 1216 opset(ASTVEHX, r0) 1217 opset(ASTVEWX, r0) 1218 opset(ASTVX, r0) 1219 opset(ASTVXL, r0) 1220 1221 case AVAND: /* vand, vandc, vnand */ 1222 opset(AVAND, r0) 1223 opset(AVANDC, r0) 1224 opset(AVNAND, r0) 1225 1226 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1227 opset(AVOR, r0) 1228 opset(AVORC, r0) 1229 opset(AVXOR, r0) 1230 opset(AVNOR, r0) 1231 opset(AVEQV, r0) 1232 1233 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1234 opset(AVADDUBM, r0) 1235 opset(AVADDUHM, r0) 1236 opset(AVADDUWM, r0) 1237 opset(AVADDUDM, r0) 1238 opset(AVADDUQM, r0) 1239 1240 case AVADDCU: /* vaddcuq, vaddcuw */ 1241 opset(AVADDCUQ, r0) 1242 opset(AVADDCUW, r0) 1243 1244 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1245 opset(AVADDUBS, r0) 1246 opset(AVADDUHS, r0) 1247 opset(AVADDUWS, r0) 1248 1249 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1250 opset(AVADDSBS, r0) 1251 opset(AVADDSHS, r0) 1252 opset(AVADDSWS, r0) 1253 1254 case AVADDE: /* vaddeuqm, vaddecuq */ 1255 opset(AVADDEUQM, r0) 1256 opset(AVADDECUQ, r0) 1257 1258 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1259 opset(AVSUBUBM, r0) 1260 opset(AVSUBUHM, r0) 1261 opset(AVSUBUWM, r0) 1262 opset(AVSUBUDM, r0) 1263 opset(AVSUBUQM, r0) 1264 1265 case AVSUBCU: /* vsubcuq, vsubcuw */ 1266 opset(AVSUBCUQ, r0) 1267 opset(AVSUBCUW, r0) 1268 1269 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1270 opset(AVSUBUBS, r0) 1271 opset(AVSUBUHS, r0) 1272 opset(AVSUBUWS, r0) 1273 1274 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1275 opset(AVSUBSBS, r0) 1276 opset(AVSUBSHS, r0) 1277 opset(AVSUBSWS, r0) 1278 1279 case AVSUBE: /* vsubeuqm, vsubecuq */ 1280 opset(AVSUBEUQM, r0) 1281 opset(AVSUBECUQ, r0) 1282 1283 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1284 opset(AVPMSUMB, r0) 1285 opset(AVPMSUMH, r0) 1286 opset(AVPMSUMW, r0) 1287 opset(AVPMSUMD, r0) 1288 1289 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1290 opset(AVRLB, r0) 1291 opset(AVRLH, r0) 1292 opset(AVRLW, r0) 1293 opset(AVRLD, r0) 1294 1295 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1296 opset(AVSLB, r0) 1297 opset(AVSLH, r0) 1298 opset(AVSLW, r0) 1299 opset(AVSL, r0) 1300 opset(AVSLO, r0) 1301 opset(AVSRB, r0) 1302 opset(AVSRH, r0) 1303 opset(AVSRW, r0) 1304 opset(AVSR, r0) 1305 opset(AVSRO, r0) 1306 opset(AVSLD, r0) 1307 opset(AVSRD, r0) 1308 1309 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1310 opset(AVSRAB, r0) 1311 opset(AVSRAH, r0) 1312 opset(AVSRAW, r0) 1313 opset(AVSRAD, r0) 1314 1315 case AVSOI: /* vsldoi */ 1316 opset(AVSLDOI, r0) 1317 1318 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1319 opset(AVCLZB, r0) 1320 opset(AVCLZH, r0) 1321 opset(AVCLZW, r0) 1322 opset(AVCLZD, r0) 1323 1324 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1325 opset(AVPOPCNTB, r0) 1326 opset(AVPOPCNTH, r0) 1327 opset(AVPOPCNTW, r0) 1328 opset(AVPOPCNTD, r0) 1329 1330 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1331 opset(AVCMPEQUB, r0) 1332 opset(AVCMPEQUBCC, r0) 1333 opset(AVCMPEQUH, r0) 1334 opset(AVCMPEQUHCC, r0) 1335 opset(AVCMPEQUW, r0) 1336 opset(AVCMPEQUWCC, r0) 1337 opset(AVCMPEQUD, r0) 1338 opset(AVCMPEQUDCC, r0) 1339 1340 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1341 opset(AVCMPGTUB, r0) 1342 opset(AVCMPGTUBCC, r0) 1343 opset(AVCMPGTUH, r0) 1344 opset(AVCMPGTUHCC, r0) 1345 opset(AVCMPGTUW, r0) 1346 opset(AVCMPGTUWCC, r0) 1347 opset(AVCMPGTUD, r0) 1348 opset(AVCMPGTUDCC, r0) 1349 opset(AVCMPGTSB, r0) 1350 opset(AVCMPGTSBCC, r0) 1351 opset(AVCMPGTSH, r0) 1352 opset(AVCMPGTSHCC, r0) 1353 opset(AVCMPGTSW, r0) 1354 opset(AVCMPGTSWCC, r0) 1355 opset(AVCMPGTSD, r0) 1356 opset(AVCMPGTSDCC, r0) 1357 1358 case AVPERM: /* vperm */ 1359 opset(AVPERM, r0) 1360 1361 case AVSEL: /* vsel */ 1362 opset(AVSEL, r0) 1363 1364 case AVSPLT: /* vspltb, vsplth, vspltw */ 1365 opset(AVSPLTB, r0) 1366 opset(AVSPLTH, r0) 1367 opset(AVSPLTW, r0) 1368 1369 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1370 opset(AVSPLTISB, r0) 1371 opset(AVSPLTISH, r0) 1372 opset(AVSPLTISW, r0) 1373 1374 case AVCIPH: /* vcipher, vcipherlast */ 1375 opset(AVCIPHER, r0) 1376 opset(AVCIPHERLAST, r0) 1377 1378 case AVNCIPH: /* vncipher, vncipherlast */ 1379 opset(AVNCIPHER, r0) 1380 opset(AVNCIPHERLAST, r0) 1381 1382 case AVSBOX: /* vsbox */ 1383 opset(AVSBOX, r0) 1384 1385 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1386 opset(AVSHASIGMAW, r0) 1387 opset(AVSHASIGMAD, r0) 1388 1389 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1390 opset(ALXVD2X, r0) 1391 opset(ALXVDSX, r0) 1392 opset(ALXVW4X, r0) 1393 1394 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1395 opset(ASTXVD2X, r0) 1396 opset(ASTXVW4X, r0) 1397 1398 case ALXS: /* lxsdx */ 1399 opset(ALXSDX, r0) 1400 1401 case ASTXS: /* stxsdx */ 1402 opset(ASTXSDX, r0) 1403 1404 case ALXSI: /* lxsiwax, lxsiwzx */ 1405 opset(ALXSIWAX, r0) 1406 opset(ALXSIWZX, r0) 1407 1408 case ASTXSI: /* stxsiwx */ 1409 opset(ASTXSIWX, r0) 1410 1411 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics) */ 1412 opset(AMFVSRD, r0) 1413 opset(AMFFPRD, r0) 1414 opset(AMFVRD, r0) 1415 opset(AMFVSRWZ, r0) 1416 1417 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics) */ 1418 opset(AMTVSRD, r0) 1419 opset(AMTFPRD, r0) 1420 opset(AMTVRD, r0) 1421 opset(AMTVSRWA, r0) 1422 opset(AMTVSRWZ, r0) 1423 1424 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1425 opset(AXXLANDQ, r0) 1426 opset(AXXLANDC, r0) 1427 opset(AXXLEQV, r0) 1428 opset(AXXLNAND, r0) 1429 1430 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1431 opset(AXXLORC, r0) 1432 opset(AXXLNOR, r0) 1433 opset(AXXLORQ, r0) 1434 opset(AXXLXOR, r0) 1435 1436 case AXXSEL: /* xxsel */ 1437 opset(AXXSEL, r0) 1438 1439 case AXXMRG: /* xxmrghw, xxmrglw */ 1440 opset(AXXMRGHW, r0) 1441 opset(AXXMRGLW, r0) 1442 1443 case AXXSPLT: /* xxspltw */ 1444 opset(AXXSPLTW, r0) 1445 1446 case AXXPERM: /* xxpermdi */ 1447 opset(AXXPERMDI, r0) 1448 1449 case AXXSI: /* xxsldwi */ 1450 opset(AXXSLDWI, r0) 1451 1452 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1453 opset(AXSCVDPSP, r0) 1454 opset(AXSCVSPDP, r0) 1455 opset(AXSCVDPSPN, r0) 1456 opset(AXSCVSPDPN, r0) 1457 1458 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1459 opset(AXVCVDPSP, r0) 1460 opset(AXVCVSPDP, r0) 1461 1462 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1463 opset(AXSCVDPSXDS, r0) 1464 opset(AXSCVDPSXWS, r0) 1465 opset(AXSCVDPUXDS, r0) 1466 opset(AXSCVDPUXWS, r0) 1467 1468 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1469 opset(AXSCVSXDDP, r0) 1470 opset(AXSCVUXDDP, r0) 1471 opset(AXSCVSXDSP, r0) 1472 opset(AXSCVUXDSP, r0) 1473 1474 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1475 opset(AXVCVDPSXDS, r0) 1476 opset(AXVCVDPSXWS, r0) 1477 opset(AXVCVDPUXDS, r0) 1478 opset(AXVCVDPUXWS, r0) 1479 opset(AXVCVSPSXDS, r0) 1480 opset(AXVCVSPSXWS, r0) 1481 opset(AXVCVSPUXDS, r0) 1482 opset(AXVCVSPUXWS, r0) 1483 1484 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1485 opset(AXVCVSXDDP, r0) 1486 opset(AXVCVSXWDP, r0) 1487 opset(AXVCVUXDDP, r0) 1488 opset(AXVCVUXWDP, r0) 1489 opset(AXVCVSXDSP, r0) 1490 opset(AXVCVSXWSP, r0) 1491 opset(AXVCVUXDSP, r0) 1492 opset(AXVCVUXWSP, r0) 1493 1494 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1495 opset(AANDN, r0) 1496 1497 opset(AANDNCC, r0) 1498 opset(AEQV, r0) 1499 opset(AEQVCC, r0) 1500 opset(ANAND, r0) 1501 opset(ANANDCC, r0) 1502 opset(ANOR, r0) 1503 opset(ANORCC, r0) 1504 opset(AORCC, r0) 1505 opset(AORN, r0) 1506 opset(AORNCC, r0) 1507 opset(AXORCC, r0) 1508 1509 case AADDME: /* op Ra, Rd */ 1510 opset(AADDMECC, r0) 1511 1512 opset(AADDMEV, r0) 1513 opset(AADDMEVCC, r0) 1514 opset(AADDZE, r0) 1515 opset(AADDZECC, r0) 1516 opset(AADDZEV, r0) 1517 opset(AADDZEVCC, r0) 1518 opset(ASUBME, r0) 1519 opset(ASUBMECC, r0) 1520 opset(ASUBMEV, r0) 1521 opset(ASUBMEVCC, r0) 1522 opset(ASUBZE, r0) 1523 opset(ASUBZECC, r0) 1524 opset(ASUBZEV, r0) 1525 opset(ASUBZEVCC, r0) 1526 1527 case AADDC: 1528 opset(AADDCCC, r0) 1529 1530 case ABEQ: 1531 opset(ABGE, r0) 1532 opset(ABGT, r0) 1533 opset(ABLE, r0) 1534 opset(ABLT, r0) 1535 opset(ABNE, r0) 1536 opset(ABVC, r0) 1537 opset(ABVS, r0) 1538 1539 case ABR: 1540 opset(ABL, r0) 1541 1542 case ABC: 1543 opset(ABCL, r0) 1544 1545 case AEXTSB: /* op Rs, Ra */ 1546 opset(AEXTSBCC, r0) 1547 1548 opset(AEXTSH, r0) 1549 opset(AEXTSHCC, r0) 1550 opset(ACNTLZW, r0) 1551 opset(ACNTLZWCC, r0) 1552 opset(ACNTLZD, r0) 1553 opset(AEXTSW, r0) 1554 opset(AEXTSWCC, r0) 1555 opset(ACNTLZDCC, r0) 1556 1557 case AFABS: /* fop [s,]d */ 1558 opset(AFABSCC, r0) 1559 1560 opset(AFNABS, r0) 1561 opset(AFNABSCC, r0) 1562 opset(AFNEG, r0) 1563 opset(AFNEGCC, r0) 1564 opset(AFRSP, r0) 1565 opset(AFRSPCC, r0) 1566 opset(AFCTIW, r0) 1567 opset(AFCTIWCC, r0) 1568 opset(AFCTIWZ, r0) 1569 opset(AFCTIWZCC, r0) 1570 opset(AFCTID, r0) 1571 opset(AFCTIDCC, r0) 1572 opset(AFCTIDZ, r0) 1573 opset(AFCTIDZCC, r0) 1574 opset(AFCFID, r0) 1575 opset(AFCFIDCC, r0) 1576 opset(AFCFIDU, r0) 1577 opset(AFCFIDUCC, r0) 1578 opset(AFRES, r0) 1579 opset(AFRESCC, r0) 1580 opset(AFRIM, r0) 1581 opset(AFRIMCC, r0) 1582 opset(AFRIP, r0) 1583 opset(AFRIPCC, r0) 1584 opset(AFRIZ, r0) 1585 opset(AFRIZCC, r0) 1586 opset(AFRSQRTE, r0) 1587 opset(AFRSQRTECC, r0) 1588 opset(AFSQRT, r0) 1589 opset(AFSQRTCC, r0) 1590 opset(AFSQRTS, r0) 1591 opset(AFSQRTSCC, r0) 1592 1593 case AFADD: 1594 opset(AFADDS, r0) 1595 opset(AFADDCC, r0) 1596 opset(AFADDSCC, r0) 1597 opset(AFDIV, r0) 1598 opset(AFDIVS, r0) 1599 opset(AFDIVCC, r0) 1600 opset(AFDIVSCC, r0) 1601 opset(AFSUB, r0) 1602 opset(AFSUBS, r0) 1603 opset(AFSUBCC, r0) 1604 opset(AFSUBSCC, r0) 1605 1606 case AFMADD: 1607 opset(AFMADDCC, r0) 1608 opset(AFMADDS, r0) 1609 opset(AFMADDSCC, r0) 1610 opset(AFMSUB, r0) 1611 opset(AFMSUBCC, r0) 1612 opset(AFMSUBS, r0) 1613 opset(AFMSUBSCC, r0) 1614 opset(AFNMADD, r0) 1615 opset(AFNMADDCC, r0) 1616 opset(AFNMADDS, r0) 1617 opset(AFNMADDSCC, r0) 1618 opset(AFNMSUB, r0) 1619 opset(AFNMSUBCC, r0) 1620 opset(AFNMSUBS, r0) 1621 opset(AFNMSUBSCC, r0) 1622 opset(AFSEL, r0) 1623 opset(AFSELCC, r0) 1624 1625 case AFMUL: 1626 opset(AFMULS, r0) 1627 opset(AFMULCC, r0) 1628 opset(AFMULSCC, r0) 1629 1630 case AFCMPO: 1631 opset(AFCMPU, r0) 1632 1633 case AISEL: 1634 opset(AISEL, r0) 1635 1636 case AMTFSB0: 1637 opset(AMTFSB0CC, r0) 1638 opset(AMTFSB1, r0) 1639 opset(AMTFSB1CC, r0) 1640 1641 case ANEG: /* op [Ra,] Rd */ 1642 opset(ANEGCC, r0) 1643 1644 opset(ANEGV, r0) 1645 opset(ANEGVCC, r0) 1646 1647 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1648 opset(AXOR, r0) 1649 1650 case ASLW: 1651 opset(ASLWCC, r0) 1652 opset(ASRW, r0) 1653 opset(ASRWCC, r0) 1654 opset(AROTLW, r0) 1655 1656 case ASLD: 1657 opset(ASLDCC, r0) 1658 opset(ASRD, r0) 1659 opset(ASRDCC, r0) 1660 opset(AROTL, r0) 1661 1662 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1663 opset(ASRAWCC, r0) 1664 1665 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1666 opset(ASRADCC, r0) 1667 1668 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1669 opset(ASUB, r0) 1670 1671 opset(ASUBCC, r0) 1672 opset(ASUBV, r0) 1673 opset(ASUBVCC, r0) 1674 opset(ASUBCCC, r0) 1675 opset(ASUBCV, r0) 1676 opset(ASUBCVCC, r0) 1677 opset(ASUBE, r0) 1678 opset(ASUBECC, r0) 1679 opset(ASUBEV, r0) 1680 opset(ASUBEVCC, r0) 1681 1682 case ASYNC: 1683 opset(AISYNC, r0) 1684 opset(ALWSYNC, r0) 1685 opset(APTESYNC, r0) 1686 opset(ATLBSYNC, r0) 1687 1688 case ARLWMI: 1689 opset(ARLWMICC, r0) 1690 opset(ARLWNM, r0) 1691 opset(ARLWNMCC, r0) 1692 1693 case ARLDMI: 1694 opset(ARLDMICC, r0) 1695 opset(ARLDIMI, r0) 1696 opset(ARLDIMICC, r0) 1697 1698 case ARLDC: 1699 opset(ARLDCCC, r0) 1700 1701 case ARLDCL: 1702 opset(ARLDCR, r0) 1703 opset(ARLDCLCC, r0) 1704 opset(ARLDCRCC, r0) 1705 1706 case ARLDICL: 1707 opset(ARLDICLCC, r0) 1708 opset(ARLDICR, r0) 1709 opset(ARLDICRCC, r0) 1710 1711 case AFMOVD: 1712 opset(AFMOVDCC, r0) 1713 opset(AFMOVDU, r0) 1714 opset(AFMOVS, r0) 1715 opset(AFMOVSU, r0) 1716 1717 case AECIWX: 1718 opset(ALBAR, r0) 1719 opset(ALWAR, r0) 1720 opset(ALDAR, r0) 1721 1722 case ASYSCALL: /* just the op; flow of control */ 1723 opset(ARFI, r0) 1724 1725 opset(ARFCI, r0) 1726 opset(ARFID, r0) 1727 opset(AHRFID, r0) 1728 1729 case AMOVHBR: 1730 opset(AMOVWBR, r0) 1731 opset(AMOVDBR, r0) 1732 1733 case ASLBMFEE: 1734 opset(ASLBMFEV, r0) 1735 1736 case ATW: 1737 opset(ATD, r0) 1738 1739 case ATLBIE: 1740 opset(ASLBIE, r0) 1741 opset(ATLBIEL, r0) 1742 1743 case AEIEIO: 1744 opset(ASLBIA, r0) 1745 1746 case ACMP: 1747 opset(ACMPW, r0) 1748 1749 case ACMPU: 1750 opset(ACMPWU, r0) 1751 1752 case ACMPB: 1753 opset(ACMPB, r0) 1754 1755 case AFTDIV: 1756 opset(AFTDIV, r0) 1757 1758 case AFTSQRT: 1759 opset(AFTSQRT, r0) 1760 1761 case AADD, 1762 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1763 AFMOVSX, 1764 AFMOVSZ, 1765 ALSW, 1766 AMOVW, 1767 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1768 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1769 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1770 AMOVB, /* macro: move byte with sign extension */ 1771 AMOVBU, /* macro: move byte with sign extension & update */ 1772 AMOVFL, 1773 AMULLW, 1774 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1775 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1776 ASTSW, 1777 ASLBMTE, 1778 AWORD, 1779 ADWORD, 1780 obj.ANOP, 1781 obj.ATEXT, 1782 obj.AUNDEF, 1783 obj.AFUNCDATA, 1784 obj.APCDATA, 1785 obj.ADUFFZERO, 1786 obj.ADUFFCOPY: 1787 break 1788 } 1789 } 1790 } 1791 1792 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1793 return o<<26 | xo<<1 | oe<<11 1794 } 1795 1796 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1797 return o<<26 | xo<<2 | oe<<11 1798 } 1799 1800 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1801 return o<<26 | xo<<3 | oe<<11 1802 } 1803 1804 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1805 return o<<26 | xo<<4 | oe<<11 1806 } 1807 1808 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1809 return o<<26 | xo | oe<<11 | rc&1 1810 } 1811 1812 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1813 return o<<26 | xo | oe<<11 | (rc&1)<<10 1814 } 1815 1816 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1817 return o<<26 | xo<<1 | oe<<10 | rc&1 1818 } 1819 1820 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1821 return OPVCC(o, xo, 0, rc) 1822 } 1823 1824 func OP(o uint32, xo uint32) uint32 { 1825 return OPVCC(o, xo, 0, 0) 1826 } 1827 1828 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1829 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1830 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1831 } 1832 1833 /* VX-form 2-register operands, r/none/r */ 1834 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1835 return op | (d&31)<<21 | (a&31)<<11 1836 } 1837 1838 /* VA-form 4-register operands */ 1839 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1840 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1841 } 1842 1843 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1844 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1845 } 1846 1847 /* VX-form 2-register + UIM operands */ 1848 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1849 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1850 } 1851 1852 /* VX-form 2-register + ST + SIX operands */ 1853 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1854 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1855 } 1856 1857 /* VA-form 3-register + SHB operands */ 1858 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1859 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1860 } 1861 1862 /* VX-form 1-register + SIM operands */ 1863 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1864 return op | (d&31)<<21 | (simm&31)<<16 1865 } 1866 1867 /* XX1-form 3-register operands, 1 VSR operand */ 1868 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1869 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1870 /* between 0-63, so we can properly set the rightmost bits. */ 1871 r := d - REG_VS0 1872 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1873 } 1874 1875 /* XX2-form 3-register operands, 2 VSR operands */ 1876 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1877 xt := d - REG_VS0 1878 xb := b - REG_VS0 1879 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1880 } 1881 1882 /* XX3-form 3 VSR operands */ 1883 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1884 xt := d - REG_VS0 1885 xa := a - REG_VS0 1886 xb := b - REG_VS0 1887 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1888 } 1889 1890 /* XX3-form 3 VSR operands + immediate */ 1891 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1892 xt := d - REG_VS0 1893 xa := a - REG_VS0 1894 xb := b - REG_VS0 1895 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1896 } 1897 1898 /* XX4-form, 4 VSR operands */ 1899 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1900 xt := d - REG_VS0 1901 xa := a - REG_VS0 1902 xb := b - REG_VS0 1903 xc := c - REG_VS0 1904 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1905 } 1906 1907 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1908 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1909 } 1910 1911 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1912 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1913 } 1914 1915 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1916 return op | li&0x03FFFFFC | aa<<1 1917 } 1918 1919 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1920 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1921 } 1922 1923 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1924 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1925 } 1926 1927 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1928 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1929 } 1930 1931 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1932 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1933 } 1934 1935 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1936 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1937 } 1938 1939 const ( 1940 /* each rhs is OPVCC(_, _, _, _) */ 1941 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1942 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1943 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1944 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1945 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1946 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1947 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1948 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1949 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1950 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1951 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1952 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1953 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1954 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1955 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1956 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1957 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1958 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1959 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1960 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1961 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1962 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1963 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1964 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1965 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1966 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1967 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1968 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 1969 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 1970 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 1971 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 1972 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 1973 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 1974 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 1975 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 1976 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 1977 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 1978 ) 1979 1980 func oclass(a *obj.Addr) int { 1981 return int(a.Class) - 1 1982 } 1983 1984 const ( 1985 D_FORM = iota 1986 DS_FORM 1987 ) 1988 1989 // This function determines when a non-indexed load or store is D or 1990 // DS form for use in finding the size of the offset field in the instruction. 1991 // The size is needed when setting the offset value in the instruction 1992 // and when generating relocation for that field. 1993 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 1994 // loads and stores with an offset field are D form. This function should 1995 // only be called with the same opcodes as are handled by opstore and opload. 1996 func (c *ctxt9) opform(insn uint32) int { 1997 switch insn { 1998 default: 1999 c.ctxt.Diag("bad insn in loadform: %x", insn) 2000 case OPVCC(58, 0, 0, 0), // ld 2001 OPVCC(58, 0, 0, 1), // ldu 2002 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2003 OPVCC(62, 0, 0, 0), // std 2004 OPVCC(62, 0, 0, 1): //stdu 2005 return DS_FORM 2006 case OP_ADDI, // add 2007 OPVCC(32, 0, 0, 0), // lwz 2008 OPVCC(33, 0, 0, 0), // lwzu 2009 OPVCC(34, 0, 0, 0), // lbz 2010 OPVCC(35, 0, 0, 0), // lbzu 2011 OPVCC(40, 0, 0, 0), // lhz 2012 OPVCC(41, 0, 0, 0), // lhzu 2013 OPVCC(42, 0, 0, 0), // lha 2014 OPVCC(43, 0, 0, 0), // lhau 2015 OPVCC(46, 0, 0, 0), // lmw 2016 OPVCC(48, 0, 0, 0), // lfs 2017 OPVCC(49, 0, 0, 0), // lfsu 2018 OPVCC(50, 0, 0, 0), // lfd 2019 OPVCC(51, 0, 0, 0), // lfdu 2020 OPVCC(36, 0, 0, 0), // stw 2021 OPVCC(37, 0, 0, 0), // stwu 2022 OPVCC(38, 0, 0, 0), // stb 2023 OPVCC(39, 0, 0, 0), // stbu 2024 OPVCC(44, 0, 0, 0), // sth 2025 OPVCC(45, 0, 0, 0), // sthu 2026 OPVCC(47, 0, 0, 0), // stmw 2027 OPVCC(52, 0, 0, 0), // stfs 2028 OPVCC(53, 0, 0, 0), // stfsu 2029 OPVCC(54, 0, 0, 0), // stfd 2030 OPVCC(55, 0, 0, 0): // stfdu 2031 return D_FORM 2032 } 2033 return 0 2034 } 2035 2036 // Encode instructions and create relocation for accessing s+d according to the 2037 // instruction op with source or destination (as appropriate) register reg. 2038 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2039 var base uint32 2040 form := c.opform(op) 2041 if c.ctxt.Flag_shared { 2042 base = REG_R2 2043 } else { 2044 base = REG_R0 2045 } 2046 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2047 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2048 rel := obj.Addrel(c.cursym) 2049 rel.Off = int32(c.pc) 2050 rel.Siz = 8 2051 rel.Sym = s 2052 rel.Add = d 2053 if c.ctxt.Flag_shared { 2054 switch form { 2055 case D_FORM: 2056 rel.Type = objabi.R_ADDRPOWER_TOCREL 2057 case DS_FORM: 2058 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2059 } 2060 2061 } else { 2062 switch form { 2063 case D_FORM: 2064 rel.Type = objabi.R_ADDRPOWER 2065 case DS_FORM: 2066 rel.Type = objabi.R_ADDRPOWER_DS 2067 } 2068 } 2069 return 2070 } 2071 2072 /* 2073 * 32-bit masks 2074 */ 2075 func getmask(m []byte, v uint32) bool { 2076 m[1] = 0 2077 m[0] = m[1] 2078 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2079 if getmask(m, ^v) { 2080 i := int(m[0]) 2081 m[0] = m[1] + 1 2082 m[1] = byte(i - 1) 2083 return true 2084 } 2085 2086 return false 2087 } 2088 2089 for i := 0; i < 32; i++ { 2090 if v&(1<<uint(31-i)) != 0 { 2091 m[0] = byte(i) 2092 for { 2093 m[1] = byte(i) 2094 i++ 2095 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2096 break 2097 } 2098 } 2099 2100 for ; i < 32; i++ { 2101 if v&(1<<uint(31-i)) != 0 { 2102 return false 2103 } 2104 } 2105 return true 2106 } 2107 } 2108 2109 return false 2110 } 2111 2112 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2113 if !getmask(m, v) { 2114 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2115 } 2116 } 2117 2118 /* 2119 * 64-bit masks (rldic etc) 2120 */ 2121 func getmask64(m []byte, v uint64) bool { 2122 m[1] = 0 2123 m[0] = m[1] 2124 for i := 0; i < 64; i++ { 2125 if v&(uint64(1)<<uint(63-i)) != 0 { 2126 m[0] = byte(i) 2127 for { 2128 m[1] = byte(i) 2129 i++ 2130 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2131 break 2132 } 2133 } 2134 2135 for ; i < 64; i++ { 2136 if v&(uint64(1)<<uint(63-i)) != 0 { 2137 return false 2138 } 2139 } 2140 return true 2141 } 2142 } 2143 2144 return false 2145 } 2146 2147 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2148 if !getmask64(m, v) { 2149 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2150 } 2151 } 2152 2153 func loadu32(r int, d int64) uint32 { 2154 v := int32(d >> 16) 2155 if isuint32(uint64(d)) { 2156 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2157 } 2158 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2159 } 2160 2161 func high16adjusted(d int32) uint16 { 2162 if d&0x8000 != 0 { 2163 return uint16((d >> 16) + 1) 2164 } 2165 return uint16(d >> 16) 2166 } 2167 2168 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2169 o1 := uint32(0) 2170 o2 := uint32(0) 2171 o3 := uint32(0) 2172 o4 := uint32(0) 2173 o5 := uint32(0) 2174 2175 //print("%v => case %d\n", p, o->type); 2176 switch o.type_ { 2177 default: 2178 c.ctxt.Diag("unknown type %d", o.type_) 2179 prasm(p) 2180 2181 case 0: /* pseudo ops */ 2182 break 2183 2184 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2185 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2186 v := c.regoff(&p.From) 2187 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2188 //nerrors--; 2189 c.ctxt.Diag("literal operation on R0\n%v", p) 2190 } 2191 2192 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2193 break 2194 } 2195 2196 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2197 2198 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2199 r := int(p.Reg) 2200 2201 if r == 0 { 2202 r = int(p.To.Reg) 2203 } 2204 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2205 2206 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2207 d := c.vregoff(&p.From) 2208 2209 v := int32(d) 2210 r := int(p.From.Reg) 2211 if r == 0 { 2212 r = int(o.param) 2213 } 2214 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2215 c.ctxt.Diag("literal operation on R0\n%v", p) 2216 } 2217 a := OP_ADDI 2218 if o.a1 == C_UCON { 2219 if d&0xffff != 0 { 2220 log.Fatalf("invalid handling of %v", p) 2221 } 2222 v >>= 16 2223 if r == REGZERO && isuint32(uint64(d)) { 2224 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2225 break 2226 } 2227 2228 a = OP_ADDIS 2229 } else { 2230 if int64(int16(d)) != d { 2231 log.Fatalf("invalid handling of %v", p) 2232 } 2233 } 2234 2235 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2236 2237 case 4: /* add/mul $scon,[r1],r2 */ 2238 v := c.regoff(&p.From) 2239 2240 r := int(p.Reg) 2241 if r == 0 { 2242 r = int(p.To.Reg) 2243 } 2244 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2245 c.ctxt.Diag("literal operation on R0\n%v", p) 2246 } 2247 if int32(int16(v)) != v { 2248 log.Fatalf("mishandled instruction %v", p) 2249 } 2250 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2251 2252 case 5: /* syscall */ 2253 o1 = c.oprrr(p.As) 2254 2255 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2256 r := int(p.Reg) 2257 2258 if r == 0 { 2259 r = int(p.To.Reg) 2260 } 2261 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2262 switch p.As { 2263 case AROTL: 2264 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2265 case AROTLW: 2266 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2267 default: 2268 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2269 } 2270 2271 case 7: /* mov r, soreg ==> stw o(r) */ 2272 r := int(p.To.Reg) 2273 2274 if r == 0 { 2275 r = int(o.param) 2276 } 2277 v := c.regoff(&p.To) 2278 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2279 if v != 0 { 2280 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2281 } 2282 if c.ctxt.Flag_shared && r == REG_R13 { 2283 rel := obj.Addrel(c.cursym) 2284 rel.Off = int32(c.pc) 2285 rel.Siz = 4 2286 // This (and the matching part in the load case 2287 // below) are the only places in the ppc64 toolchain 2288 // that knows the name of the tls variable. Possibly 2289 // we could add some assembly syntax so that the name 2290 // of the variable does not have to be assumed. 2291 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2292 rel.Type = objabi.R_POWER_TLS 2293 } 2294 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2295 } else { 2296 if int32(int16(v)) != v { 2297 log.Fatalf("mishandled instruction %v", p) 2298 } 2299 // Offsets in DS form stores must be a multiple of 4 2300 inst := c.opstore(p.As) 2301 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2302 log.Fatalf("invalid offset for DS form load/store %v", p) 2303 } 2304 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2305 } 2306 2307 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2308 r := int(p.From.Reg) 2309 2310 if r == 0 { 2311 r = int(o.param) 2312 } 2313 v := c.regoff(&p.From) 2314 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2315 if v != 0 { 2316 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2317 } 2318 if c.ctxt.Flag_shared && r == REG_R13 { 2319 rel := obj.Addrel(c.cursym) 2320 rel.Off = int32(c.pc) 2321 rel.Siz = 4 2322 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2323 rel.Type = objabi.R_POWER_TLS 2324 } 2325 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2326 } else { 2327 if int32(int16(v)) != v { 2328 log.Fatalf("mishandled instruction %v", p) 2329 } 2330 // Offsets in DS form loads must be a multiple of 4 2331 inst := c.opload(p.As) 2332 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2333 log.Fatalf("invalid offset for DS form load/store %v", p) 2334 } 2335 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2336 } 2337 2338 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2339 r := int(p.From.Reg) 2340 2341 if r == 0 { 2342 r = int(o.param) 2343 } 2344 v := c.regoff(&p.From) 2345 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2346 if v != 0 { 2347 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2348 } 2349 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2350 } else { 2351 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2352 } 2353 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2354 2355 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2356 r := int(p.Reg) 2357 2358 if r == 0 { 2359 r = int(p.To.Reg) 2360 } 2361 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2362 2363 case 11: /* br/bl lbra */ 2364 v := int32(0) 2365 2366 if p.Pcond != nil { 2367 v = int32(p.Pcond.Pc - p.Pc) 2368 if v&03 != 0 { 2369 c.ctxt.Diag("odd branch target address\n%v", p) 2370 v &^= 03 2371 } 2372 2373 if v < -(1<<25) || v >= 1<<24 { 2374 c.ctxt.Diag("branch too far\n%v", p) 2375 } 2376 } 2377 2378 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2379 if p.To.Sym != nil { 2380 rel := obj.Addrel(c.cursym) 2381 rel.Off = int32(c.pc) 2382 rel.Siz = 4 2383 rel.Sym = p.To.Sym 2384 v += int32(p.To.Offset) 2385 if v&03 != 0 { 2386 c.ctxt.Diag("odd branch target address\n%v", p) 2387 v &^= 03 2388 } 2389 2390 rel.Add = int64(v) 2391 rel.Type = objabi.R_CALLPOWER 2392 } 2393 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2394 2395 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2396 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2397 v := c.regoff(&p.From) 2398 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2399 c.ctxt.Diag("literal operation on R0\n%v", p) 2400 } 2401 2402 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2403 break 2404 } 2405 2406 if p.As == AMOVW { 2407 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2408 } else { 2409 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2410 } 2411 2412 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2413 if p.As == AMOVBZ { 2414 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2415 } else if p.As == AMOVH { 2416 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2417 } else if p.As == AMOVHZ { 2418 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2419 } else if p.As == AMOVWZ { 2420 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2421 } else { 2422 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2423 } 2424 2425 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2426 r := int(p.Reg) 2427 2428 if r == 0 { 2429 r = int(p.To.Reg) 2430 } 2431 d := c.vregoff(p.From3) 2432 var a int 2433 switch p.As { 2434 2435 // These opcodes expect a mask operand that has to be converted into the 2436 // appropriate operand. The way these were defined, not all valid masks are possible. 2437 // Left here for compatibility in case they were used or generated. 2438 case ARLDCL, ARLDCLCC: 2439 var mask [2]uint8 2440 c.maskgen64(p, mask[:], uint64(d)) 2441 2442 a = int(mask[0]) /* MB */ 2443 if mask[1] != 63 { 2444 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2445 } 2446 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2447 o1 |= (uint32(a) & 31) << 6 2448 if a&0x20 != 0 { 2449 o1 |= 1 << 5 /* mb[5] is top bit */ 2450 } 2451 2452 case ARLDCR, ARLDCRCC: 2453 var mask [2]uint8 2454 c.maskgen64(p, mask[:], uint64(d)) 2455 2456 a = int(mask[1]) /* ME */ 2457 if mask[0] != 0 { 2458 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2459 } 2460 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2461 o1 |= (uint32(a) & 31) << 6 2462 if a&0x20 != 0 { 2463 o1 |= 1 << 5 /* mb[5] is top bit */ 2464 } 2465 2466 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2467 case ARLDICR, ARLDICRCC: 2468 me := int(d) 2469 sh := c.regoff(&p.From) 2470 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2471 2472 case ARLDICL, ARLDICLCC: 2473 mb := int(d) 2474 sh := c.regoff(&p.From) 2475 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2476 2477 default: 2478 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2479 a = 0 2480 } 2481 2482 case 17, /* bc bo,bi,lbra (same for now) */ 2483 16: /* bc bo,bi,sbra */ 2484 a := 0 2485 2486 r := int(p.Reg) 2487 2488 if p.From.Type == obj.TYPE_CONST { 2489 a = int(c.regoff(&p.From)) 2490 } else if p.From.Type == obj.TYPE_REG { 2491 if r != 0 { 2492 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2493 } 2494 // BI values for the CR 2495 switch p.From.Reg { 2496 case REG_CR0: 2497 r = BI_CR0 2498 case REG_CR1: 2499 r = BI_CR1 2500 case REG_CR2: 2501 r = BI_CR2 2502 case REG_CR3: 2503 r = BI_CR3 2504 case REG_CR4: 2505 r = BI_CR4 2506 case REG_CR5: 2507 r = BI_CR5 2508 case REG_CR6: 2509 r = BI_CR6 2510 case REG_CR7: 2511 r = BI_CR7 2512 default: 2513 c.ctxt.Diag("unrecognized register: expecting CR\n") 2514 } 2515 } 2516 v := int32(0) 2517 if p.Pcond != nil { 2518 v = int32(p.Pcond.Pc - p.Pc) 2519 } 2520 if v&03 != 0 { 2521 c.ctxt.Diag("odd branch target address\n%v", p) 2522 v &^= 03 2523 } 2524 2525 if v < -(1<<16) || v >= 1<<15 { 2526 c.ctxt.Diag("branch too far\n%v", p) 2527 } 2528 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2529 2530 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2531 var v int32 2532 if p.As == ABC || p.As == ABCL { 2533 v = c.regoff(&p.To) & 31 2534 } else { 2535 v = 20 /* unconditional */ 2536 } 2537 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2538 o2 = OPVCC(19, 16, 0, 0) 2539 if p.As == ABL || p.As == ABCL { 2540 o2 |= 1 2541 } 2542 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2543 2544 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2545 var v int32 2546 if p.As == ABC || p.As == ABCL { 2547 v = c.regoff(&p.From) & 31 2548 } else { 2549 v = 20 /* unconditional */ 2550 } 2551 r := int(p.Reg) 2552 if r == 0 { 2553 r = 0 2554 } 2555 switch oclass(&p.To) { 2556 case C_CTR: 2557 o1 = OPVCC(19, 528, 0, 0) 2558 2559 case C_LR: 2560 o1 = OPVCC(19, 16, 0, 0) 2561 2562 default: 2563 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2564 v = 0 2565 } 2566 2567 if p.As == ABL || p.As == ABCL { 2568 o1 |= 1 2569 } 2570 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2571 2572 case 19: /* mov $lcon,r ==> cau+or */ 2573 d := c.vregoff(&p.From) 2574 2575 if p.From.Sym == nil { 2576 o1 = loadu32(int(p.To.Reg), d) 2577 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2578 } else { 2579 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2580 } 2581 2582 //if(dlm) reloc(&p->from, p->pc, 0); 2583 2584 case 20: /* add $ucon,,r */ 2585 v := c.regoff(&p.From) 2586 2587 r := int(p.Reg) 2588 if r == 0 { 2589 r = int(p.To.Reg) 2590 } 2591 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2592 c.ctxt.Diag("literal operation on R0\n%v", p) 2593 } 2594 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2595 2596 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2597 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2598 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2599 } 2600 d := c.vregoff(&p.From) 2601 o1 = loadu32(REGTMP, d) 2602 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2603 r := int(p.Reg) 2604 if r == 0 { 2605 r = int(p.To.Reg) 2606 } 2607 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2608 if p.From.Sym != nil { 2609 c.ctxt.Diag("%v is not supported", p) 2610 } 2611 2612 //if(dlm) reloc(&p->from, p->pc, 0); 2613 2614 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2615 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2616 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2617 } 2618 d := c.vregoff(&p.From) 2619 o1 = loadu32(REGTMP, d) 2620 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2621 r := int(p.Reg) 2622 if r == 0 { 2623 r = int(p.To.Reg) 2624 } 2625 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2626 if p.From.Sym != nil { 2627 c.ctxt.Diag("%v is not supported", p) 2628 } 2629 2630 //if(dlm) reloc(&p->from, p->pc, 0); 2631 2632 /*24*/ 2633 case 25: 2634 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2635 v := c.regoff(&p.From) 2636 2637 if v < 0 { 2638 v = 0 2639 } else if v > 63 { 2640 v = 63 2641 } 2642 r := int(p.Reg) 2643 if r == 0 { 2644 r = int(p.To.Reg) 2645 } 2646 var a int 2647 op := uint32(0) 2648 switch p.As { 2649 case ASLD, ASLDCC: 2650 a = int(63 - v) 2651 op = OP_RLDICR 2652 2653 case ASRD, ASRDCC: 2654 a = int(v) 2655 v = 64 - v 2656 op = OP_RLDICL 2657 case AROTL: 2658 a = int(0) 2659 op = OP_RLDICL 2660 default: 2661 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2662 a = 0 2663 o1 = 0 2664 } 2665 2666 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2667 if p.As == ASLDCC || p.As == ASRDCC { 2668 o1 |= 1 // Set the condition code bit 2669 } 2670 2671 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2672 if p.To.Reg == REGTMP { 2673 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2674 } 2675 v := c.regoff(&p.From) 2676 r := int(p.From.Reg) 2677 if r == 0 { 2678 r = int(o.param) 2679 } 2680 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2681 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2682 2683 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2684 v := c.regoff(p.From3) 2685 2686 r := int(p.From.Reg) 2687 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2688 2689 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2690 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2691 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2692 } 2693 v := c.regoff(p.From3) 2694 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2695 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2696 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2697 if p.From.Sym != nil { 2698 c.ctxt.Diag("%v is not supported", p) 2699 } 2700 2701 //if(dlm) reloc(&p->from3, p->pc, 0); 2702 2703 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2704 v := c.regoff(&p.From) 2705 2706 d := c.vregoff(p.From3) 2707 var mask [2]uint8 2708 c.maskgen64(p, mask[:], uint64(d)) 2709 var a int 2710 switch p.As { 2711 case ARLDC, ARLDCCC: 2712 a = int(mask[0]) /* MB */ 2713 if int32(mask[1]) != (63 - v) { 2714 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2715 } 2716 2717 case ARLDCL, ARLDCLCC: 2718 a = int(mask[0]) /* MB */ 2719 if mask[1] != 63 { 2720 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2721 } 2722 2723 case ARLDCR, ARLDCRCC: 2724 a = int(mask[1]) /* ME */ 2725 if mask[0] != 0 { 2726 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2727 } 2728 2729 default: 2730 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2731 a = 0 2732 } 2733 2734 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2735 o1 |= (uint32(a) & 31) << 6 2736 if v&0x20 != 0 { 2737 o1 |= 1 << 1 2738 } 2739 if a&0x20 != 0 { 2740 o1 |= 1 << 5 /* mb[5] is top bit */ 2741 } 2742 2743 case 30: /* rldimi $sh,s,$mask,a */ 2744 v := c.regoff(&p.From) 2745 2746 d := c.vregoff(p.From3) 2747 2748 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2749 // the ppc64 asm. 2750 switch p.As { 2751 case ARLDMI, ARLDMICC: 2752 var mask [2]uint8 2753 c.maskgen64(p, mask[:], uint64(d)) 2754 if int32(mask[1]) != (63 - v) { 2755 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2756 } 2757 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2758 o1 |= (uint32(mask[0]) & 31) << 6 2759 if v&0x20 != 0 { 2760 o1 |= 1 << 1 2761 } 2762 if mask[0]&0x20 != 0 { 2763 o1 |= 1 << 5 /* mb[5] is top bit */ 2764 } 2765 2766 // Opcodes with shift count operands. 2767 case ARLDIMI, ARLDIMICC: 2768 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2769 o1 |= (uint32(d) & 31) << 6 2770 if d&0x20 != 0 { 2771 o1 |= 1 << 5 2772 } 2773 if v&0x20 != 0 { 2774 o1 |= 1 << 1 2775 } 2776 } 2777 2778 case 31: /* dword */ 2779 d := c.vregoff(&p.From) 2780 2781 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2782 o1 = uint32(d >> 32) 2783 o2 = uint32(d) 2784 } else { 2785 o1 = uint32(d) 2786 o2 = uint32(d >> 32) 2787 } 2788 2789 if p.From.Sym != nil { 2790 rel := obj.Addrel(c.cursym) 2791 rel.Off = int32(c.pc) 2792 rel.Siz = 8 2793 rel.Sym = p.From.Sym 2794 rel.Add = p.From.Offset 2795 rel.Type = objabi.R_ADDR 2796 o2 = 0 2797 o1 = o2 2798 } 2799 2800 case 32: /* fmul frc,fra,frd */ 2801 r := int(p.Reg) 2802 2803 if r == 0 { 2804 r = int(p.To.Reg) 2805 } 2806 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2807 2808 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2809 r := int(p.From.Reg) 2810 2811 if oclass(&p.From) == C_NONE { 2812 r = int(p.To.Reg) 2813 } 2814 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2815 2816 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2817 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2818 2819 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2820 v := c.regoff(&p.To) 2821 2822 r := int(p.To.Reg) 2823 if r == 0 { 2824 r = int(o.param) 2825 } 2826 // Offsets in DS form stores must be a multiple of 4 2827 inst := c.opstore(p.As) 2828 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2829 log.Fatalf("invalid offset for DS form load/store %v", p) 2830 } 2831 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2832 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2833 2834 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2835 v := c.regoff(&p.From) 2836 2837 r := int(p.From.Reg) 2838 if r == 0 { 2839 r = int(o.param) 2840 } 2841 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2842 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2843 2844 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2845 v := c.regoff(&p.From) 2846 2847 r := int(p.From.Reg) 2848 if r == 0 { 2849 r = int(o.param) 2850 } 2851 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2852 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2853 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2854 2855 case 40: /* word */ 2856 o1 = uint32(c.regoff(&p.From)) 2857 2858 case 41: /* stswi */ 2859 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2860 2861 case 42: /* lswi */ 2862 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2863 2864 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2865 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2866 2867 case 44: /* indexed store */ 2868 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2869 2870 case 45: /* indexed load */ 2871 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2872 2873 case 46: /* plain op */ 2874 o1 = c.oprrr(p.As) 2875 2876 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2877 r := int(p.From.Reg) 2878 2879 if r == 0 { 2880 r = int(p.To.Reg) 2881 } 2882 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2883 2884 case 48: /* op Rs, Ra */ 2885 r := int(p.From.Reg) 2886 2887 if r == 0 { 2888 r = int(p.To.Reg) 2889 } 2890 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2891 2892 case 49: /* op Rb; op $n, Rb */ 2893 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2894 v := c.regoff(&p.From) & 1 2895 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2896 } else { 2897 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2898 } 2899 2900 case 50: /* rem[u] r1[,r2],r3 */ 2901 r := int(p.Reg) 2902 2903 if r == 0 { 2904 r = int(p.To.Reg) 2905 } 2906 v := c.oprrr(p.As) 2907 t := v & (1<<10 | 1) /* OE|Rc */ 2908 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2909 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2910 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2911 if p.As == AREMU { 2912 o4 = o3 2913 2914 /* Clear top 32 bits */ 2915 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2916 } 2917 2918 case 51: /* remd[u] r1[,r2],r3 */ 2919 r := int(p.Reg) 2920 2921 if r == 0 { 2922 r = int(p.To.Reg) 2923 } 2924 v := c.oprrr(p.As) 2925 t := v & (1<<10 | 1) /* OE|Rc */ 2926 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2927 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2928 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2929 2930 case 52: /* mtfsbNx cr(n) */ 2931 v := c.regoff(&p.From) & 31 2932 2933 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2934 2935 case 53: /* mffsX ,fr1 */ 2936 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2937 2938 case 54: /* mov msr,r1; mov r1, msr*/ 2939 if oclass(&p.From) == C_REG { 2940 if p.As == AMOVD { 2941 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2942 } else { 2943 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2944 } 2945 } else { 2946 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2947 } 2948 2949 case 55: /* op Rb, Rd */ 2950 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2951 2952 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2953 v := c.regoff(&p.From) 2954 2955 r := int(p.Reg) 2956 if r == 0 { 2957 r = int(p.To.Reg) 2958 } 2959 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2960 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2961 o1 |= 1 << 1 /* mb[5] */ 2962 } 2963 2964 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2965 v := c.regoff(&p.From) 2966 2967 r := int(p.Reg) 2968 if r == 0 { 2969 r = int(p.To.Reg) 2970 } 2971 2972 /* 2973 * Let user (gs) shoot himself in the foot. 2974 * qc has already complained. 2975 * 2976 if(v < 0 || v > 31) 2977 ctxt->diag("illegal shift %ld\n%v", v, p); 2978 */ 2979 if v < 0 { 2980 v = 0 2981 } else if v > 32 { 2982 v = 32 2983 } 2984 var mask [2]uint8 2985 switch p.As { 2986 case AROTLW: 2987 mask[0], mask[1] = 0, 31 2988 case ASRW, ASRWCC: 2989 mask[0], mask[1] = uint8(v), 31 2990 v = 32 - v 2991 default: 2992 mask[0], mask[1] = 0, uint8(31-v) 2993 } 2994 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 2995 if p.As == ASLWCC || p.As == ASRWCC { 2996 o1 |= 1 // set the condition code 2997 } 2998 2999 case 58: /* logical $andcon,[s],a */ 3000 v := c.regoff(&p.From) 3001 3002 r := int(p.Reg) 3003 if r == 0 { 3004 r = int(p.To.Reg) 3005 } 3006 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3007 3008 case 59: /* or/and $ucon,,r */ 3009 v := c.regoff(&p.From) 3010 3011 r := int(p.Reg) 3012 if r == 0 { 3013 r = int(p.To.Reg) 3014 } 3015 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3016 3017 case 60: /* tw to,a,b */ 3018 r := int(c.regoff(&p.From) & 31) 3019 3020 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3021 3022 case 61: /* tw to,a,$simm */ 3023 r := int(c.regoff(&p.From) & 31) 3024 3025 v := c.regoff(&p.To) 3026 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3027 3028 case 62: /* rlwmi $sh,s,$mask,a */ 3029 v := c.regoff(&p.From) 3030 3031 var mask [2]uint8 3032 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3033 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3034 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3035 3036 case 63: /* rlwmi b,s,$mask,a */ 3037 var mask [2]uint8 3038 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3039 3040 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3041 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3042 3043 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3044 var v int32 3045 if p.From3Type() != obj.TYPE_NONE { 3046 v = c.regoff(p.From3) & 255 3047 } else { 3048 v = 255 3049 } 3050 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3051 3052 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3053 if p.To.Reg == 0 { 3054 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3055 } 3056 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3057 3058 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3059 var r int 3060 var v int32 3061 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3062 r = int(p.From.Reg) 3063 v = int32(p.To.Reg) 3064 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3065 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3066 } else { 3067 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3068 } 3069 } else { 3070 r = int(p.To.Reg) 3071 v = int32(p.From.Reg) 3072 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3073 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3074 } else { 3075 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3076 } 3077 } 3078 3079 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3080 3081 case 67: /* mcrf crfD,crfS */ 3082 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3083 c.ctxt.Diag("illegal CR field number\n%v", p) 3084 } 3085 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3086 3087 case 68: /* mfcr rD; mfocrf CRM,rD */ 3088 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3089 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3090 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3091 } else { 3092 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3093 } 3094 3095 case 69: /* mtcrf CRM,rS */ 3096 var v int32 3097 if p.From3Type() != obj.TYPE_NONE { 3098 if p.To.Reg != 0 { 3099 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3100 } 3101 v = c.regoff(p.From3) & 0xff 3102 } else { 3103 if p.To.Reg == 0 { 3104 v = 0xff /* CR */ 3105 } else { 3106 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3107 } 3108 } 3109 3110 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3111 3112 case 70: /* [f]cmp r,r,cr*/ 3113 var r int 3114 if p.Reg == 0 { 3115 r = 0 3116 } else { 3117 r = (int(p.Reg) & 7) << 2 3118 } 3119 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3120 3121 case 71: /* cmp[l] r,i,cr*/ 3122 var r int 3123 if p.Reg == 0 { 3124 r = 0 3125 } else { 3126 r = (int(p.Reg) & 7) << 2 3127 } 3128 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3129 3130 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3131 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3132 3133 case 73: /* mcrfs crfD,crfS */ 3134 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3135 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3136 } 3137 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3138 3139 case 77: /* syscall $scon, syscall Rx */ 3140 if p.From.Type == obj.TYPE_CONST { 3141 if p.From.Offset > BIG || p.From.Offset < -BIG { 3142 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3143 } 3144 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3145 } else if p.From.Type == obj.TYPE_REG { 3146 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3147 } else { 3148 c.ctxt.Diag("illegal syscall: %v", p) 3149 o1 = 0x7fe00008 // trap always 3150 } 3151 3152 o2 = c.oprrr(p.As) 3153 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3154 3155 case 78: /* undef */ 3156 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3157 always to be an illegal instruction." */ 3158 3159 /* relocation operations */ 3160 case 74: 3161 v := c.vregoff(&p.To) 3162 // Offsets in DS form stores must be a multiple of 4 3163 inst := c.opstore(p.As) 3164 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3165 log.Fatalf("invalid offset for DS form load/store %v", p) 3166 } 3167 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3168 3169 //if(dlm) reloc(&p->to, p->pc, 1); 3170 3171 case 75: 3172 v := c.vregoff(&p.From) 3173 // Offsets in DS form loads must be a multiple of 4 3174 inst := c.opload(p.As) 3175 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3176 log.Fatalf("invalid offset for DS form load/store %v", p) 3177 } 3178 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3179 3180 //if(dlm) reloc(&p->from, p->pc, 1); 3181 3182 case 76: 3183 v := c.vregoff(&p.From) 3184 // Offsets in DS form loads must be a multiple of 4 3185 inst := c.opload(p.As) 3186 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3187 log.Fatalf("invalid offset for DS form load/store %v", p) 3188 } 3189 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3190 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3191 3192 //if(dlm) reloc(&p->from, p->pc, 1); 3193 3194 case 79: 3195 if p.From.Offset != 0 { 3196 c.ctxt.Diag("invalid offset against tls var %v", p) 3197 } 3198 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3199 rel := obj.Addrel(c.cursym) 3200 rel.Off = int32(c.pc) 3201 rel.Siz = 4 3202 rel.Sym = p.From.Sym 3203 rel.Type = objabi.R_POWER_TLS_LE 3204 3205 case 80: 3206 if p.From.Offset != 0 { 3207 c.ctxt.Diag("invalid offset against tls var %v", p) 3208 } 3209 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3210 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3211 rel := obj.Addrel(c.cursym) 3212 rel.Off = int32(c.pc) 3213 rel.Siz = 8 3214 rel.Sym = p.From.Sym 3215 rel.Type = objabi.R_POWER_TLS_IE 3216 3217 case 81: 3218 v := c.vregoff(&p.To) 3219 if v != 0 { 3220 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3221 } 3222 3223 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3224 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3225 rel := obj.Addrel(c.cursym) 3226 rel.Off = int32(c.pc) 3227 rel.Siz = 8 3228 rel.Sym = p.From.Sym 3229 rel.Type = objabi.R_ADDRPOWER_GOT 3230 case 82: /* vector instructions, VX-form and VC-form */ 3231 if p.From.Type == obj.TYPE_REG { 3232 /* reg reg none OR reg reg reg */ 3233 /* 3-register operand order: VRA, VRB, VRT */ 3234 /* 2-register operand order: VRA, VRT */ 3235 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3236 } else if p.From3Type() == obj.TYPE_CONST { 3237 /* imm imm reg reg */ 3238 /* operand order: SIX, VRA, ST, VRT */ 3239 six := int(c.regoff(&p.From)) 3240 st := int(c.regoff(p.From3)) 3241 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3242 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3243 /* imm reg reg */ 3244 /* operand order: UIM, VRB, VRT */ 3245 uim := int(c.regoff(&p.From)) 3246 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3247 } else { 3248 /* imm reg */ 3249 /* operand order: SIM, VRT */ 3250 sim := int(c.regoff(&p.From)) 3251 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3252 } 3253 3254 case 83: /* vector instructions, VA-form */ 3255 if p.From.Type == obj.TYPE_REG { 3256 /* reg reg reg reg */ 3257 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3258 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3259 } else if p.From.Type == obj.TYPE_CONST { 3260 /* imm reg reg reg */ 3261 /* operand order: SHB, VRA, VRB, VRT */ 3262 shb := int(c.regoff(&p.From)) 3263 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3264 } 3265 3266 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3267 bc := c.vregoff(&p.From) 3268 3269 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3270 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3271 3272 case 85: /* vector instructions, VX-form */ 3273 /* reg none reg */ 3274 /* 2-register operand order: VRB, VRT */ 3275 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3276 3277 case 86: /* VSX indexed store, XX1-form */ 3278 /* reg reg reg */ 3279 /* 3-register operand order: XT, (RB)(RA*1) */ 3280 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3281 3282 case 87: /* VSX indexed load, XX1-form */ 3283 /* reg reg reg */ 3284 /* 3-register operand order: (RB)(RA*1), XT */ 3285 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3286 3287 case 88: /* VSX instructions, XX1-form */ 3288 /* reg reg none OR reg reg reg */ 3289 /* 3-register operand order: RA, RB, XT */ 3290 /* 2-register operand order: XS, RA or RA, XT */ 3291 xt := int32(p.To.Reg) 3292 xs := int32(p.From.Reg) 3293 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3294 if REG_V0 <= xt && xt <= REG_V31 { 3295 /* Convert V0-V31 to VS32-VS63 */ 3296 xt = xt + 64 3297 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3298 } else if REG_F0 <= xt && xt <= REG_F31 { 3299 /* Convert F0-F31 to VS0-VS31 */ 3300 xt = xt + 64 3301 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3302 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3303 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3304 } else if REG_V0 <= xs && xs <= REG_V31 { 3305 /* Likewise for XS */ 3306 xs = xs + 64 3307 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3308 } else if REG_F0 <= xs && xs <= REG_F31 { 3309 xs = xs + 64 3310 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3311 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3312 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3313 } 3314 3315 case 89: /* VSX instructions, XX2-form */ 3316 /* reg none reg OR reg imm reg */ 3317 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3318 uim := int(c.regoff(p.From3)) 3319 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3320 3321 case 90: /* VSX instructions, XX3-form */ 3322 if p.From3Type() == obj.TYPE_NONE { 3323 /* reg reg reg */ 3324 /* 3-register operand order: XA, XB, XT */ 3325 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3326 } else if p.From3Type() == obj.TYPE_CONST { 3327 /* reg reg reg imm */ 3328 /* operand order: XA, XB, DM, XT */ 3329 dm := int(c.regoff(p.From3)) 3330 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3331 } 3332 3333 case 91: /* VSX instructions, XX4-form */ 3334 /* reg reg reg reg */ 3335 /* 3-register operand order: XA, XB, XC, XT */ 3336 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3337 3338 case 92: /* X-form instructions, 3-operands */ 3339 if p.To.Type == obj.TYPE_CONST { 3340 /* imm reg reg */ 3341 /* operand order: FRA, FRB, BF */ 3342 bf := int(c.regoff(&p.To)) << 2 3343 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3344 } else if p.To.Type == obj.TYPE_REG { 3345 /* reg reg reg */ 3346 /* operand order: RS, RB, RA */ 3347 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3348 } 3349 3350 case 93: /* X-form instructions, 2-operands */ 3351 if p.To.Type == obj.TYPE_CONST { 3352 /* imm reg */ 3353 /* operand order: FRB, BF */ 3354 bf := int(c.regoff(&p.To)) << 2 3355 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3356 } else if p.Reg == 0 { 3357 /* popcnt* r,r, X-form */ 3358 /* operand order: RS, RA */ 3359 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3360 } 3361 3362 } 3363 3364 out[0] = o1 3365 out[1] = o2 3366 out[2] = o3 3367 out[3] = o4 3368 out[4] = o5 3369 return 3370 } 3371 3372 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3373 c.instoffset = 0 3374 if a != nil { 3375 c.aclass(a) 3376 } 3377 return c.instoffset 3378 } 3379 3380 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3381 return int32(c.vregoff(a)) 3382 } 3383 3384 func (c *ctxt9) oprrr(a obj.As) uint32 { 3385 switch a { 3386 case AADD: 3387 return OPVCC(31, 266, 0, 0) 3388 case AADDCC: 3389 return OPVCC(31, 266, 0, 1) 3390 case AADDV: 3391 return OPVCC(31, 266, 1, 0) 3392 case AADDVCC: 3393 return OPVCC(31, 266, 1, 1) 3394 case AADDC: 3395 return OPVCC(31, 10, 0, 0) 3396 case AADDCCC: 3397 return OPVCC(31, 10, 0, 1) 3398 case AADDCV: 3399 return OPVCC(31, 10, 1, 0) 3400 case AADDCVCC: 3401 return OPVCC(31, 10, 1, 1) 3402 case AADDE: 3403 return OPVCC(31, 138, 0, 0) 3404 case AADDECC: 3405 return OPVCC(31, 138, 0, 1) 3406 case AADDEV: 3407 return OPVCC(31, 138, 1, 0) 3408 case AADDEVCC: 3409 return OPVCC(31, 138, 1, 1) 3410 case AADDME: 3411 return OPVCC(31, 234, 0, 0) 3412 case AADDMECC: 3413 return OPVCC(31, 234, 0, 1) 3414 case AADDMEV: 3415 return OPVCC(31, 234, 1, 0) 3416 case AADDMEVCC: 3417 return OPVCC(31, 234, 1, 1) 3418 case AADDZE: 3419 return OPVCC(31, 202, 0, 0) 3420 case AADDZECC: 3421 return OPVCC(31, 202, 0, 1) 3422 case AADDZEV: 3423 return OPVCC(31, 202, 1, 0) 3424 case AADDZEVCC: 3425 return OPVCC(31, 202, 1, 1) 3426 3427 case AAND: 3428 return OPVCC(31, 28, 0, 0) 3429 case AANDCC: 3430 return OPVCC(31, 28, 0, 1) 3431 case AANDN: 3432 return OPVCC(31, 60, 0, 0) 3433 case AANDNCC: 3434 return OPVCC(31, 60, 0, 1) 3435 3436 case ACMP: 3437 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3438 case ACMPU: 3439 return OPVCC(31, 32, 0, 0) | 1<<21 3440 case ACMPW: 3441 return OPVCC(31, 0, 0, 0) /* L=0 */ 3442 case ACMPWU: 3443 return OPVCC(31, 32, 0, 0) 3444 case ACMPB: 3445 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3446 3447 case ACNTLZW: 3448 return OPVCC(31, 26, 0, 0) 3449 case ACNTLZWCC: 3450 return OPVCC(31, 26, 0, 1) 3451 case ACNTLZD: 3452 return OPVCC(31, 58, 0, 0) 3453 case ACNTLZDCC: 3454 return OPVCC(31, 58, 0, 1) 3455 3456 case ACRAND: 3457 return OPVCC(19, 257, 0, 0) 3458 case ACRANDN: 3459 return OPVCC(19, 129, 0, 0) 3460 case ACREQV: 3461 return OPVCC(19, 289, 0, 0) 3462 case ACRNAND: 3463 return OPVCC(19, 225, 0, 0) 3464 case ACRNOR: 3465 return OPVCC(19, 33, 0, 0) 3466 case ACROR: 3467 return OPVCC(19, 449, 0, 0) 3468 case ACRORN: 3469 return OPVCC(19, 417, 0, 0) 3470 case ACRXOR: 3471 return OPVCC(19, 193, 0, 0) 3472 3473 case ADCBF: 3474 return OPVCC(31, 86, 0, 0) 3475 case ADCBI: 3476 return OPVCC(31, 470, 0, 0) 3477 case ADCBST: 3478 return OPVCC(31, 54, 0, 0) 3479 case ADCBT: 3480 return OPVCC(31, 278, 0, 0) 3481 case ADCBTST: 3482 return OPVCC(31, 246, 0, 0) 3483 case ADCBZ: 3484 return OPVCC(31, 1014, 0, 0) 3485 3486 case AREM, ADIVW: 3487 return OPVCC(31, 491, 0, 0) 3488 3489 case AREMCC, ADIVWCC: 3490 return OPVCC(31, 491, 0, 1) 3491 3492 case AREMV, ADIVWV: 3493 return OPVCC(31, 491, 1, 0) 3494 3495 case AREMVCC, ADIVWVCC: 3496 return OPVCC(31, 491, 1, 1) 3497 3498 case AREMU, ADIVWU: 3499 return OPVCC(31, 459, 0, 0) 3500 3501 case AREMUCC, ADIVWUCC: 3502 return OPVCC(31, 459, 0, 1) 3503 3504 case AREMUV, ADIVWUV: 3505 return OPVCC(31, 459, 1, 0) 3506 3507 case AREMUVCC, ADIVWUVCC: 3508 return OPVCC(31, 459, 1, 1) 3509 3510 case AREMD, ADIVD: 3511 return OPVCC(31, 489, 0, 0) 3512 3513 case AREMDCC, ADIVDCC: 3514 return OPVCC(31, 489, 0, 1) 3515 3516 case ADIVDE: 3517 return OPVCC(31, 425, 0, 0) 3518 3519 case ADIVDECC: 3520 return OPVCC(31, 425, 0, 1) 3521 3522 case ADIVDEU: 3523 return OPVCC(31, 393, 0, 0) 3524 3525 case ADIVDEUCC: 3526 return OPVCC(31, 393, 0, 1) 3527 3528 case AREMDV, ADIVDV: 3529 return OPVCC(31, 489, 1, 0) 3530 3531 case AREMDVCC, ADIVDVCC: 3532 return OPVCC(31, 489, 1, 1) 3533 3534 case AREMDU, ADIVDU: 3535 return OPVCC(31, 457, 0, 0) 3536 3537 case AREMDUCC, ADIVDUCC: 3538 return OPVCC(31, 457, 0, 1) 3539 3540 case AREMDUV, ADIVDUV: 3541 return OPVCC(31, 457, 1, 0) 3542 3543 case AREMDUVCC, ADIVDUVCC: 3544 return OPVCC(31, 457, 1, 1) 3545 3546 case AEIEIO: 3547 return OPVCC(31, 854, 0, 0) 3548 3549 case AEQV: 3550 return OPVCC(31, 284, 0, 0) 3551 case AEQVCC: 3552 return OPVCC(31, 284, 0, 1) 3553 3554 case AEXTSB: 3555 return OPVCC(31, 954, 0, 0) 3556 case AEXTSBCC: 3557 return OPVCC(31, 954, 0, 1) 3558 case AEXTSH: 3559 return OPVCC(31, 922, 0, 0) 3560 case AEXTSHCC: 3561 return OPVCC(31, 922, 0, 1) 3562 case AEXTSW: 3563 return OPVCC(31, 986, 0, 0) 3564 case AEXTSWCC: 3565 return OPVCC(31, 986, 0, 1) 3566 3567 case AFABS: 3568 return OPVCC(63, 264, 0, 0) 3569 case AFABSCC: 3570 return OPVCC(63, 264, 0, 1) 3571 case AFADD: 3572 return OPVCC(63, 21, 0, 0) 3573 case AFADDCC: 3574 return OPVCC(63, 21, 0, 1) 3575 case AFADDS: 3576 return OPVCC(59, 21, 0, 0) 3577 case AFADDSCC: 3578 return OPVCC(59, 21, 0, 1) 3579 case AFCMPO: 3580 return OPVCC(63, 32, 0, 0) 3581 case AFCMPU: 3582 return OPVCC(63, 0, 0, 0) 3583 case AFCFID: 3584 return OPVCC(63, 846, 0, 0) 3585 case AFCFIDCC: 3586 return OPVCC(63, 846, 0, 1) 3587 case AFCFIDU: 3588 return OPVCC(63, 974, 0, 0) 3589 case AFCFIDUCC: 3590 return OPVCC(63, 974, 0, 1) 3591 case AFCTIW: 3592 return OPVCC(63, 14, 0, 0) 3593 case AFCTIWCC: 3594 return OPVCC(63, 14, 0, 1) 3595 case AFCTIWZ: 3596 return OPVCC(63, 15, 0, 0) 3597 case AFCTIWZCC: 3598 return OPVCC(63, 15, 0, 1) 3599 case AFCTID: 3600 return OPVCC(63, 814, 0, 0) 3601 case AFCTIDCC: 3602 return OPVCC(63, 814, 0, 1) 3603 case AFCTIDZ: 3604 return OPVCC(63, 815, 0, 0) 3605 case AFCTIDZCC: 3606 return OPVCC(63, 815, 0, 1) 3607 case AFDIV: 3608 return OPVCC(63, 18, 0, 0) 3609 case AFDIVCC: 3610 return OPVCC(63, 18, 0, 1) 3611 case AFDIVS: 3612 return OPVCC(59, 18, 0, 0) 3613 case AFDIVSCC: 3614 return OPVCC(59, 18, 0, 1) 3615 case AFMADD: 3616 return OPVCC(63, 29, 0, 0) 3617 case AFMADDCC: 3618 return OPVCC(63, 29, 0, 1) 3619 case AFMADDS: 3620 return OPVCC(59, 29, 0, 0) 3621 case AFMADDSCC: 3622 return OPVCC(59, 29, 0, 1) 3623 3624 case AFMOVS, AFMOVD: 3625 return OPVCC(63, 72, 0, 0) /* load */ 3626 case AFMOVDCC: 3627 return OPVCC(63, 72, 0, 1) 3628 case AFMSUB: 3629 return OPVCC(63, 28, 0, 0) 3630 case AFMSUBCC: 3631 return OPVCC(63, 28, 0, 1) 3632 case AFMSUBS: 3633 return OPVCC(59, 28, 0, 0) 3634 case AFMSUBSCC: 3635 return OPVCC(59, 28, 0, 1) 3636 case AFMUL: 3637 return OPVCC(63, 25, 0, 0) 3638 case AFMULCC: 3639 return OPVCC(63, 25, 0, 1) 3640 case AFMULS: 3641 return OPVCC(59, 25, 0, 0) 3642 case AFMULSCC: 3643 return OPVCC(59, 25, 0, 1) 3644 case AFNABS: 3645 return OPVCC(63, 136, 0, 0) 3646 case AFNABSCC: 3647 return OPVCC(63, 136, 0, 1) 3648 case AFNEG: 3649 return OPVCC(63, 40, 0, 0) 3650 case AFNEGCC: 3651 return OPVCC(63, 40, 0, 1) 3652 case AFNMADD: 3653 return OPVCC(63, 31, 0, 0) 3654 case AFNMADDCC: 3655 return OPVCC(63, 31, 0, 1) 3656 case AFNMADDS: 3657 return OPVCC(59, 31, 0, 0) 3658 case AFNMADDSCC: 3659 return OPVCC(59, 31, 0, 1) 3660 case AFNMSUB: 3661 return OPVCC(63, 30, 0, 0) 3662 case AFNMSUBCC: 3663 return OPVCC(63, 30, 0, 1) 3664 case AFNMSUBS: 3665 return OPVCC(59, 30, 0, 0) 3666 case AFNMSUBSCC: 3667 return OPVCC(59, 30, 0, 1) 3668 case AFRES: 3669 return OPVCC(59, 24, 0, 0) 3670 case AFRESCC: 3671 return OPVCC(59, 24, 0, 1) 3672 case AFRIM: 3673 return OPVCC(63, 488, 0, 0) 3674 case AFRIMCC: 3675 return OPVCC(63, 488, 0, 1) 3676 case AFRIP: 3677 return OPVCC(63, 456, 0, 0) 3678 case AFRIPCC: 3679 return OPVCC(63, 456, 0, 1) 3680 case AFRIZ: 3681 return OPVCC(63, 424, 0, 0) 3682 case AFRIZCC: 3683 return OPVCC(63, 424, 0, 1) 3684 case AFRSP: 3685 return OPVCC(63, 12, 0, 0) 3686 case AFRSPCC: 3687 return OPVCC(63, 12, 0, 1) 3688 case AFRSQRTE: 3689 return OPVCC(63, 26, 0, 0) 3690 case AFRSQRTECC: 3691 return OPVCC(63, 26, 0, 1) 3692 case AFSEL: 3693 return OPVCC(63, 23, 0, 0) 3694 case AFSELCC: 3695 return OPVCC(63, 23, 0, 1) 3696 case AFSQRT: 3697 return OPVCC(63, 22, 0, 0) 3698 case AFSQRTCC: 3699 return OPVCC(63, 22, 0, 1) 3700 case AFSQRTS: 3701 return OPVCC(59, 22, 0, 0) 3702 case AFSQRTSCC: 3703 return OPVCC(59, 22, 0, 1) 3704 case AFSUB: 3705 return OPVCC(63, 20, 0, 0) 3706 case AFSUBCC: 3707 return OPVCC(63, 20, 0, 1) 3708 case AFSUBS: 3709 return OPVCC(59, 20, 0, 0) 3710 case AFSUBSCC: 3711 return OPVCC(59, 20, 0, 1) 3712 3713 case AICBI: 3714 return OPVCC(31, 982, 0, 0) 3715 case AISYNC: 3716 return OPVCC(19, 150, 0, 0) 3717 3718 case AMTFSB0: 3719 return OPVCC(63, 70, 0, 0) 3720 case AMTFSB0CC: 3721 return OPVCC(63, 70, 0, 1) 3722 case AMTFSB1: 3723 return OPVCC(63, 38, 0, 0) 3724 case AMTFSB1CC: 3725 return OPVCC(63, 38, 0, 1) 3726 3727 case AMULHW: 3728 return OPVCC(31, 75, 0, 0) 3729 case AMULHWCC: 3730 return OPVCC(31, 75, 0, 1) 3731 case AMULHWU: 3732 return OPVCC(31, 11, 0, 0) 3733 case AMULHWUCC: 3734 return OPVCC(31, 11, 0, 1) 3735 case AMULLW: 3736 return OPVCC(31, 235, 0, 0) 3737 case AMULLWCC: 3738 return OPVCC(31, 235, 0, 1) 3739 case AMULLWV: 3740 return OPVCC(31, 235, 1, 0) 3741 case AMULLWVCC: 3742 return OPVCC(31, 235, 1, 1) 3743 3744 case AMULHD: 3745 return OPVCC(31, 73, 0, 0) 3746 case AMULHDCC: 3747 return OPVCC(31, 73, 0, 1) 3748 case AMULHDU: 3749 return OPVCC(31, 9, 0, 0) 3750 case AMULHDUCC: 3751 return OPVCC(31, 9, 0, 1) 3752 case AMULLD: 3753 return OPVCC(31, 233, 0, 0) 3754 case AMULLDCC: 3755 return OPVCC(31, 233, 0, 1) 3756 case AMULLDV: 3757 return OPVCC(31, 233, 1, 0) 3758 case AMULLDVCC: 3759 return OPVCC(31, 233, 1, 1) 3760 3761 case ANAND: 3762 return OPVCC(31, 476, 0, 0) 3763 case ANANDCC: 3764 return OPVCC(31, 476, 0, 1) 3765 case ANEG: 3766 return OPVCC(31, 104, 0, 0) 3767 case ANEGCC: 3768 return OPVCC(31, 104, 0, 1) 3769 case ANEGV: 3770 return OPVCC(31, 104, 1, 0) 3771 case ANEGVCC: 3772 return OPVCC(31, 104, 1, 1) 3773 case ANOR: 3774 return OPVCC(31, 124, 0, 0) 3775 case ANORCC: 3776 return OPVCC(31, 124, 0, 1) 3777 case AOR: 3778 return OPVCC(31, 444, 0, 0) 3779 case AORCC: 3780 return OPVCC(31, 444, 0, 1) 3781 case AORN: 3782 return OPVCC(31, 412, 0, 0) 3783 case AORNCC: 3784 return OPVCC(31, 412, 0, 1) 3785 3786 case APOPCNTD: 3787 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3788 case APOPCNTW: 3789 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3790 case APOPCNTB: 3791 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3792 3793 case ARFI: 3794 return OPVCC(19, 50, 0, 0) 3795 case ARFCI: 3796 return OPVCC(19, 51, 0, 0) 3797 case ARFID: 3798 return OPVCC(19, 18, 0, 0) 3799 case AHRFID: 3800 return OPVCC(19, 274, 0, 0) 3801 3802 case ARLWMI: 3803 return OPVCC(20, 0, 0, 0) 3804 case ARLWMICC: 3805 return OPVCC(20, 0, 0, 1) 3806 case ARLWNM: 3807 return OPVCC(23, 0, 0, 0) 3808 case ARLWNMCC: 3809 return OPVCC(23, 0, 0, 1) 3810 3811 case ARLDCL: 3812 return OPVCC(30, 8, 0, 0) 3813 case ARLDCR: 3814 return OPVCC(30, 9, 0, 0) 3815 3816 case ARLDICL: 3817 return OPVCC(30, 0, 0, 0) 3818 case ARLDICLCC: 3819 return OPVCC(30, 0, 0, 1) 3820 case ARLDICR: 3821 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3822 case ARLDICRCC: 3823 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3824 3825 case ASYSCALL: 3826 return OPVCC(17, 1, 0, 0) 3827 3828 case ASLW: 3829 return OPVCC(31, 24, 0, 0) 3830 case ASLWCC: 3831 return OPVCC(31, 24, 0, 1) 3832 case ASLD: 3833 return OPVCC(31, 27, 0, 0) 3834 case ASLDCC: 3835 return OPVCC(31, 27, 0, 1) 3836 3837 case ASRAW: 3838 return OPVCC(31, 792, 0, 0) 3839 case ASRAWCC: 3840 return OPVCC(31, 792, 0, 1) 3841 case ASRAD: 3842 return OPVCC(31, 794, 0, 0) 3843 case ASRADCC: 3844 return OPVCC(31, 794, 0, 1) 3845 3846 case ASRW: 3847 return OPVCC(31, 536, 0, 0) 3848 case ASRWCC: 3849 return OPVCC(31, 536, 0, 1) 3850 case ASRD: 3851 return OPVCC(31, 539, 0, 0) 3852 case ASRDCC: 3853 return OPVCC(31, 539, 0, 1) 3854 3855 case ASUB: 3856 return OPVCC(31, 40, 0, 0) 3857 case ASUBCC: 3858 return OPVCC(31, 40, 0, 1) 3859 case ASUBV: 3860 return OPVCC(31, 40, 1, 0) 3861 case ASUBVCC: 3862 return OPVCC(31, 40, 1, 1) 3863 case ASUBC: 3864 return OPVCC(31, 8, 0, 0) 3865 case ASUBCCC: 3866 return OPVCC(31, 8, 0, 1) 3867 case ASUBCV: 3868 return OPVCC(31, 8, 1, 0) 3869 case ASUBCVCC: 3870 return OPVCC(31, 8, 1, 1) 3871 case ASUBE: 3872 return OPVCC(31, 136, 0, 0) 3873 case ASUBECC: 3874 return OPVCC(31, 136, 0, 1) 3875 case ASUBEV: 3876 return OPVCC(31, 136, 1, 0) 3877 case ASUBEVCC: 3878 return OPVCC(31, 136, 1, 1) 3879 case ASUBME: 3880 return OPVCC(31, 232, 0, 0) 3881 case ASUBMECC: 3882 return OPVCC(31, 232, 0, 1) 3883 case ASUBMEV: 3884 return OPVCC(31, 232, 1, 0) 3885 case ASUBMEVCC: 3886 return OPVCC(31, 232, 1, 1) 3887 case ASUBZE: 3888 return OPVCC(31, 200, 0, 0) 3889 case ASUBZECC: 3890 return OPVCC(31, 200, 0, 1) 3891 case ASUBZEV: 3892 return OPVCC(31, 200, 1, 0) 3893 case ASUBZEVCC: 3894 return OPVCC(31, 200, 1, 1) 3895 3896 case ASYNC: 3897 return OPVCC(31, 598, 0, 0) 3898 case ALWSYNC: 3899 return OPVCC(31, 598, 0, 0) | 1<<21 3900 3901 case APTESYNC: 3902 return OPVCC(31, 598, 0, 0) | 2<<21 3903 3904 case ATLBIE: 3905 return OPVCC(31, 306, 0, 0) 3906 case ATLBIEL: 3907 return OPVCC(31, 274, 0, 0) 3908 case ATLBSYNC: 3909 return OPVCC(31, 566, 0, 0) 3910 case ASLBIA: 3911 return OPVCC(31, 498, 0, 0) 3912 case ASLBIE: 3913 return OPVCC(31, 434, 0, 0) 3914 case ASLBMFEE: 3915 return OPVCC(31, 915, 0, 0) 3916 case ASLBMFEV: 3917 return OPVCC(31, 851, 0, 0) 3918 case ASLBMTE: 3919 return OPVCC(31, 402, 0, 0) 3920 3921 case ATW: 3922 return OPVCC(31, 4, 0, 0) 3923 case ATD: 3924 return OPVCC(31, 68, 0, 0) 3925 3926 /* Vector (VMX/Altivec) instructions */ 3927 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3928 /* are enabled starting at POWER6 (ISA 2.05). */ 3929 case AVAND: 3930 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3931 case AVANDC: 3932 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 3933 case AVNAND: 3934 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 3935 3936 case AVOR: 3937 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 3938 case AVORC: 3939 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 3940 case AVNOR: 3941 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 3942 case AVXOR: 3943 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 3944 case AVEQV: 3945 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 3946 3947 case AVADDUBM: 3948 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 3949 case AVADDUHM: 3950 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 3951 case AVADDUWM: 3952 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 3953 case AVADDUDM: 3954 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 3955 case AVADDUQM: 3956 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 3957 3958 case AVADDCUQ: 3959 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 3960 case AVADDCUW: 3961 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 3962 3963 case AVADDUBS: 3964 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 3965 case AVADDUHS: 3966 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 3967 case AVADDUWS: 3968 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 3969 3970 case AVADDSBS: 3971 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 3972 case AVADDSHS: 3973 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 3974 case AVADDSWS: 3975 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 3976 3977 case AVADDEUQM: 3978 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 3979 case AVADDECUQ: 3980 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 3981 3982 case AVPMSUMB: 3983 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 3984 case AVPMSUMH: 3985 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 3986 case AVPMSUMW: 3987 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 3988 case AVPMSUMD: 3989 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 3990 3991 case AVSUBUBM: 3992 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 3993 case AVSUBUHM: 3994 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 3995 case AVSUBUWM: 3996 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 3997 case AVSUBUDM: 3998 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 3999 case AVSUBUQM: 4000 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4001 4002 case AVSUBCUQ: 4003 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4004 case AVSUBCUW: 4005 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4006 4007 case AVSUBUBS: 4008 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4009 case AVSUBUHS: 4010 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4011 case AVSUBUWS: 4012 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4013 4014 case AVSUBSBS: 4015 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4016 case AVSUBSHS: 4017 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4018 case AVSUBSWS: 4019 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4020 4021 case AVSUBEUQM: 4022 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4023 case AVSUBECUQ: 4024 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4025 4026 case AVRLB: 4027 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4028 case AVRLH: 4029 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4030 case AVRLW: 4031 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4032 case AVRLD: 4033 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4034 4035 case AVSLB: 4036 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4037 case AVSLH: 4038 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4039 case AVSLW: 4040 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4041 case AVSL: 4042 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4043 case AVSLO: 4044 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4045 case AVSRB: 4046 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4047 case AVSRH: 4048 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4049 case AVSRW: 4050 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4051 case AVSR: 4052 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4053 case AVSRO: 4054 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4055 case AVSLD: 4056 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4057 case AVSRD: 4058 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4059 4060 case AVSRAB: 4061 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4062 case AVSRAH: 4063 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4064 case AVSRAW: 4065 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4066 case AVSRAD: 4067 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4068 4069 case AVCLZB: 4070 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4071 case AVCLZH: 4072 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4073 case AVCLZW: 4074 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4075 case AVCLZD: 4076 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4077 4078 case AVPOPCNTB: 4079 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4080 case AVPOPCNTH: 4081 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4082 case AVPOPCNTW: 4083 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4084 case AVPOPCNTD: 4085 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4086 4087 case AVCMPEQUB: 4088 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4089 case AVCMPEQUBCC: 4090 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4091 case AVCMPEQUH: 4092 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4093 case AVCMPEQUHCC: 4094 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4095 case AVCMPEQUW: 4096 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4097 case AVCMPEQUWCC: 4098 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4099 case AVCMPEQUD: 4100 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4101 case AVCMPEQUDCC: 4102 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4103 4104 case AVCMPGTUB: 4105 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4106 case AVCMPGTUBCC: 4107 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4108 case AVCMPGTUH: 4109 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4110 case AVCMPGTUHCC: 4111 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4112 case AVCMPGTUW: 4113 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4114 case AVCMPGTUWCC: 4115 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4116 case AVCMPGTUD: 4117 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4118 case AVCMPGTUDCC: 4119 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4120 case AVCMPGTSB: 4121 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4122 case AVCMPGTSBCC: 4123 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4124 case AVCMPGTSH: 4125 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4126 case AVCMPGTSHCC: 4127 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4128 case AVCMPGTSW: 4129 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4130 case AVCMPGTSWCC: 4131 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4132 case AVCMPGTSD: 4133 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4134 case AVCMPGTSDCC: 4135 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4136 4137 case AVPERM: 4138 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4139 4140 case AVSEL: 4141 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4142 4143 case AVCIPHER: 4144 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4145 case AVCIPHERLAST: 4146 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4147 case AVNCIPHER: 4148 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4149 case AVNCIPHERLAST: 4150 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4151 case AVSBOX: 4152 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4153 /* End of vector instructions */ 4154 4155 /* Vector scalar (VSX) instructions */ 4156 /* ISA 2.06 enables these for POWER7. */ 4157 case AMFVSRD, AMFVRD, AMFFPRD: 4158 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4159 case AMFVSRWZ: 4160 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4161 4162 case AMTVSRD, AMTFPRD, AMTVRD: 4163 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4164 case AMTVSRWA: 4165 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4166 case AMTVSRWZ: 4167 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4168 4169 case AXXLANDQ: 4170 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4171 case AXXLANDC: 4172 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4173 case AXXLEQV: 4174 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4175 case AXXLNAND: 4176 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4177 4178 case AXXLORC: 4179 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4180 case AXXLNOR: 4181 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4182 case AXXLORQ: 4183 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4184 case AXXLXOR: 4185 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4186 4187 case AXXSEL: 4188 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4189 4190 case AXXMRGHW: 4191 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4192 case AXXMRGLW: 4193 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4194 4195 case AXXSPLTW: 4196 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4197 4198 case AXXPERMDI: 4199 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4200 4201 case AXXSLDWI: 4202 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4203 4204 case AXSCVDPSP: 4205 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4206 case AXSCVSPDP: 4207 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4208 case AXSCVDPSPN: 4209 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4210 case AXSCVSPDPN: 4211 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4212 4213 case AXVCVDPSP: 4214 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4215 case AXVCVSPDP: 4216 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4217 4218 case AXSCVDPSXDS: 4219 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4220 case AXSCVDPSXWS: 4221 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4222 case AXSCVDPUXDS: 4223 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4224 case AXSCVDPUXWS: 4225 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4226 4227 case AXSCVSXDDP: 4228 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4229 case AXSCVUXDDP: 4230 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4231 case AXSCVSXDSP: 4232 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4233 case AXSCVUXDSP: 4234 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4235 4236 case AXVCVDPSXDS: 4237 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4238 case AXVCVDPSXWS: 4239 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4240 case AXVCVDPUXDS: 4241 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4242 case AXVCVDPUXWS: 4243 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4244 case AXVCVSPSXDS: 4245 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4246 case AXVCVSPSXWS: 4247 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4248 case AXVCVSPUXDS: 4249 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4250 case AXVCVSPUXWS: 4251 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4252 4253 case AXVCVSXDDP: 4254 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4255 case AXVCVSXWDP: 4256 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4257 case AXVCVUXDDP: 4258 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4259 case AXVCVUXWDP: 4260 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4261 case AXVCVSXDSP: 4262 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4263 case AXVCVSXWSP: 4264 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4265 case AXVCVUXDSP: 4266 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4267 case AXVCVUXWSP: 4268 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4269 /* End of VSX instructions */ 4270 4271 case AXOR: 4272 return OPVCC(31, 316, 0, 0) 4273 case AXORCC: 4274 return OPVCC(31, 316, 0, 1) 4275 } 4276 4277 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4278 return 0 4279 } 4280 4281 func (c *ctxt9) opirrr(a obj.As) uint32 { 4282 switch a { 4283 /* Vector (VMX/Altivec) instructions */ 4284 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4285 /* are enabled starting at POWER6 (ISA 2.05). */ 4286 case AVSLDOI: 4287 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4288 } 4289 4290 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4291 return 0 4292 } 4293 4294 func (c *ctxt9) opiirr(a obj.As) uint32 { 4295 switch a { 4296 /* Vector (VMX/Altivec) instructions */ 4297 /* ISA 2.07 enables these for POWER8 and beyond. */ 4298 case AVSHASIGMAW: 4299 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4300 case AVSHASIGMAD: 4301 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4302 } 4303 4304 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4305 return 0 4306 } 4307 4308 func (c *ctxt9) opirr(a obj.As) uint32 { 4309 switch a { 4310 case AADD: 4311 return OPVCC(14, 0, 0, 0) 4312 case AADDC: 4313 return OPVCC(12, 0, 0, 0) 4314 case AADDCCC: 4315 return OPVCC(13, 0, 0, 0) 4316 case -AADD: 4317 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4318 4319 case AANDCC: 4320 return OPVCC(28, 0, 0, 0) 4321 case -AANDCC: 4322 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4323 4324 case ABR: 4325 return OPVCC(18, 0, 0, 0) 4326 case ABL: 4327 return OPVCC(18, 0, 0, 0) | 1 4328 case obj.ADUFFZERO: 4329 return OPVCC(18, 0, 0, 0) | 1 4330 case obj.ADUFFCOPY: 4331 return OPVCC(18, 0, 0, 0) | 1 4332 case ABC: 4333 return OPVCC(16, 0, 0, 0) 4334 case ABCL: 4335 return OPVCC(16, 0, 0, 0) | 1 4336 4337 case ABEQ: 4338 return AOP_RRR(16<<26, 12, 2, 0) 4339 case ABGE: 4340 return AOP_RRR(16<<26, 4, 0, 0) 4341 case ABGT: 4342 return AOP_RRR(16<<26, 12, 1, 0) 4343 case ABLE: 4344 return AOP_RRR(16<<26, 4, 1, 0) 4345 case ABLT: 4346 return AOP_RRR(16<<26, 12, 0, 0) 4347 case ABNE: 4348 return AOP_RRR(16<<26, 4, 2, 0) 4349 case ABVC: 4350 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4351 case ABVS: 4352 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4353 4354 case ACMP: 4355 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4356 case ACMPU: 4357 return OPVCC(10, 0, 0, 0) | 1<<21 4358 case ACMPW: 4359 return OPVCC(11, 0, 0, 0) /* L=0 */ 4360 case ACMPWU: 4361 return OPVCC(10, 0, 0, 0) 4362 case ALSW: 4363 return OPVCC(31, 597, 0, 0) 4364 4365 case AMULLW: 4366 return OPVCC(7, 0, 0, 0) 4367 4368 case AOR: 4369 return OPVCC(24, 0, 0, 0) 4370 case -AOR: 4371 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4372 4373 case ARLWMI: 4374 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4375 case ARLWMICC: 4376 return OPVCC(20, 0, 0, 1) 4377 case ARLDMI: 4378 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4379 case ARLDMICC: 4380 return OPVCC(30, 0, 0, 1) | 3<<2 4381 case ARLDIMI: 4382 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4383 case ARLDIMICC: 4384 return OPVCC(30, 0, 0, 1) | 3<<2 4385 case ARLWNM: 4386 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4387 case ARLWNMCC: 4388 return OPVCC(21, 0, 0, 1) 4389 4390 case ARLDCL: 4391 return OPVCC(30, 0, 0, 0) /* rldicl */ 4392 case ARLDCLCC: 4393 return OPVCC(30, 0, 0, 1) 4394 case ARLDCR: 4395 return OPVCC(30, 1, 0, 0) /* rldicr */ 4396 case ARLDCRCC: 4397 return OPVCC(30, 1, 0, 1) 4398 case ARLDC: 4399 return OPVCC(30, 0, 0, 0) | 2<<2 4400 case ARLDCCC: 4401 return OPVCC(30, 0, 0, 1) | 2<<2 4402 4403 case ASRAW: 4404 return OPVCC(31, 824, 0, 0) 4405 case ASRAWCC: 4406 return OPVCC(31, 824, 0, 1) 4407 case ASRAD: 4408 return OPVCC(31, (413 << 1), 0, 0) 4409 case ASRADCC: 4410 return OPVCC(31, (413 << 1), 0, 1) 4411 4412 case ASTSW: 4413 return OPVCC(31, 725, 0, 0) 4414 4415 case ASUBC: 4416 return OPVCC(8, 0, 0, 0) 4417 4418 case ATW: 4419 return OPVCC(3, 0, 0, 0) 4420 case ATD: 4421 return OPVCC(2, 0, 0, 0) 4422 4423 /* Vector (VMX/Altivec) instructions */ 4424 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4425 /* are enabled starting at POWER6 (ISA 2.05). */ 4426 case AVSPLTB: 4427 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4428 case AVSPLTH: 4429 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4430 case AVSPLTW: 4431 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4432 4433 case AVSPLTISB: 4434 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4435 case AVSPLTISH: 4436 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4437 case AVSPLTISW: 4438 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4439 /* End of vector instructions */ 4440 4441 case AFTDIV: 4442 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4443 case AFTSQRT: 4444 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4445 4446 case AXOR: 4447 return OPVCC(26, 0, 0, 0) /* XORIL */ 4448 case -AXOR: 4449 return OPVCC(27, 0, 0, 0) /* XORIU */ 4450 } 4451 4452 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4453 return 0 4454 } 4455 4456 /* 4457 * load o(a),d 4458 */ 4459 func (c *ctxt9) opload(a obj.As) uint32 { 4460 switch a { 4461 case AMOVD: 4462 return OPVCC(58, 0, 0, 0) /* ld */ 4463 case AMOVDU: 4464 return OPVCC(58, 0, 0, 1) /* ldu */ 4465 case AMOVWZ: 4466 return OPVCC(32, 0, 0, 0) /* lwz */ 4467 case AMOVWZU: 4468 return OPVCC(33, 0, 0, 0) /* lwzu */ 4469 case AMOVW: 4470 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4471 4472 /* no AMOVWU */ 4473 case AMOVB, AMOVBZ: 4474 return OPVCC(34, 0, 0, 0) 4475 /* load */ 4476 4477 case AMOVBU, AMOVBZU: 4478 return OPVCC(35, 0, 0, 0) 4479 case AFMOVD: 4480 return OPVCC(50, 0, 0, 0) 4481 case AFMOVDU: 4482 return OPVCC(51, 0, 0, 0) 4483 case AFMOVS: 4484 return OPVCC(48, 0, 0, 0) 4485 case AFMOVSU: 4486 return OPVCC(49, 0, 0, 0) 4487 case AMOVH: 4488 return OPVCC(42, 0, 0, 0) 4489 case AMOVHU: 4490 return OPVCC(43, 0, 0, 0) 4491 case AMOVHZ: 4492 return OPVCC(40, 0, 0, 0) 4493 case AMOVHZU: 4494 return OPVCC(41, 0, 0, 0) 4495 case AMOVMW: 4496 return OPVCC(46, 0, 0, 0) /* lmw */ 4497 } 4498 4499 c.ctxt.Diag("bad load opcode %v", a) 4500 return 0 4501 } 4502 4503 /* 4504 * indexed load a(b),d 4505 */ 4506 func (c *ctxt9) oploadx(a obj.As) uint32 { 4507 switch a { 4508 case AMOVWZ: 4509 return OPVCC(31, 23, 0, 0) /* lwzx */ 4510 case AMOVWZU: 4511 return OPVCC(31, 55, 0, 0) /* lwzux */ 4512 case AMOVW: 4513 return OPVCC(31, 341, 0, 0) /* lwax */ 4514 case AMOVWU: 4515 return OPVCC(31, 373, 0, 0) /* lwaux */ 4516 4517 case AMOVB, AMOVBZ: 4518 return OPVCC(31, 87, 0, 0) /* lbzx */ 4519 4520 case AMOVBU, AMOVBZU: 4521 return OPVCC(31, 119, 0, 0) /* lbzux */ 4522 case AFMOVD: 4523 return OPVCC(31, 599, 0, 0) /* lfdx */ 4524 case AFMOVDU: 4525 return OPVCC(31, 631, 0, 0) /* lfdux */ 4526 case AFMOVS: 4527 return OPVCC(31, 535, 0, 0) /* lfsx */ 4528 case AFMOVSU: 4529 return OPVCC(31, 567, 0, 0) /* lfsux */ 4530 case AFMOVSX: 4531 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4532 case AFMOVSZ: 4533 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4534 case AMOVH: 4535 return OPVCC(31, 343, 0, 0) /* lhax */ 4536 case AMOVHU: 4537 return OPVCC(31, 375, 0, 0) /* lhaux */ 4538 case AMOVHBR: 4539 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4540 case AMOVWBR: 4541 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4542 case AMOVDBR: 4543 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4544 case AMOVHZ: 4545 return OPVCC(31, 279, 0, 0) /* lhzx */ 4546 case AMOVHZU: 4547 return OPVCC(31, 311, 0, 0) /* lhzux */ 4548 case AECIWX: 4549 return OPVCC(31, 310, 0, 0) /* eciwx */ 4550 case ALBAR: 4551 return OPVCC(31, 52, 0, 0) /* lbarx */ 4552 case ALWAR: 4553 return OPVCC(31, 20, 0, 0) /* lwarx */ 4554 case ALDAR: 4555 return OPVCC(31, 84, 0, 0) 4556 case ALSW: 4557 return OPVCC(31, 533, 0, 0) /* lswx */ 4558 case AMOVD: 4559 return OPVCC(31, 21, 0, 0) /* ldx */ 4560 case AMOVDU: 4561 return OPVCC(31, 53, 0, 0) /* ldux */ 4562 4563 /* Vector (VMX/Altivec) instructions */ 4564 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4565 /* are enabled starting at POWER6 (ISA 2.05). */ 4566 case ALVEBX: 4567 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4568 case ALVEHX: 4569 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4570 case ALVEWX: 4571 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4572 case ALVX: 4573 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4574 case ALVXL: 4575 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4576 case ALVSL: 4577 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4578 case ALVSR: 4579 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4580 /* End of vector instructions */ 4581 4582 /* Vector scalar (VSX) instructions */ 4583 /* ISA 2.06 enables these for POWER7. */ 4584 case ALXVD2X: 4585 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4586 case ALXVDSX: 4587 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4588 case ALXVW4X: 4589 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4590 4591 case ALXSDX: 4592 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4593 4594 case ALXSIWAX: 4595 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4596 case ALXSIWZX: 4597 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4598 /* End of vector scalar instructions */ 4599 4600 } 4601 4602 c.ctxt.Diag("bad loadx opcode %v", a) 4603 return 0 4604 } 4605 4606 /* 4607 * store s,o(d) 4608 */ 4609 func (c *ctxt9) opstore(a obj.As) uint32 { 4610 switch a { 4611 case AMOVB, AMOVBZ: 4612 return OPVCC(38, 0, 0, 0) /* stb */ 4613 4614 case AMOVBU, AMOVBZU: 4615 return OPVCC(39, 0, 0, 0) /* stbu */ 4616 case AFMOVD: 4617 return OPVCC(54, 0, 0, 0) /* stfd */ 4618 case AFMOVDU: 4619 return OPVCC(55, 0, 0, 0) /* stfdu */ 4620 case AFMOVS: 4621 return OPVCC(52, 0, 0, 0) /* stfs */ 4622 case AFMOVSU: 4623 return OPVCC(53, 0, 0, 0) /* stfsu */ 4624 4625 case AMOVHZ, AMOVH: 4626 return OPVCC(44, 0, 0, 0) /* sth */ 4627 4628 case AMOVHZU, AMOVHU: 4629 return OPVCC(45, 0, 0, 0) /* sthu */ 4630 case AMOVMW: 4631 return OPVCC(47, 0, 0, 0) /* stmw */ 4632 case ASTSW: 4633 return OPVCC(31, 725, 0, 0) /* stswi */ 4634 4635 case AMOVWZ, AMOVW: 4636 return OPVCC(36, 0, 0, 0) /* stw */ 4637 4638 case AMOVWZU, AMOVWU: 4639 return OPVCC(37, 0, 0, 0) /* stwu */ 4640 case AMOVD: 4641 return OPVCC(62, 0, 0, 0) /* std */ 4642 case AMOVDU: 4643 return OPVCC(62, 0, 0, 1) /* stdu */ 4644 } 4645 4646 c.ctxt.Diag("unknown store opcode %v", a) 4647 return 0 4648 } 4649 4650 /* 4651 * indexed store s,a(b) 4652 */ 4653 func (c *ctxt9) opstorex(a obj.As) uint32 { 4654 switch a { 4655 case AMOVB, AMOVBZ: 4656 return OPVCC(31, 215, 0, 0) /* stbx */ 4657 4658 case AMOVBU, AMOVBZU: 4659 return OPVCC(31, 247, 0, 0) /* stbux */ 4660 case AFMOVD: 4661 return OPVCC(31, 727, 0, 0) /* stfdx */ 4662 case AFMOVDU: 4663 return OPVCC(31, 759, 0, 0) /* stfdux */ 4664 case AFMOVS: 4665 return OPVCC(31, 663, 0, 0) /* stfsx */ 4666 case AFMOVSU: 4667 return OPVCC(31, 695, 0, 0) /* stfsux */ 4668 case AFMOVSX: 4669 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4670 4671 case AMOVHZ, AMOVH: 4672 return OPVCC(31, 407, 0, 0) /* sthx */ 4673 case AMOVHBR: 4674 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4675 4676 case AMOVHZU, AMOVHU: 4677 return OPVCC(31, 439, 0, 0) /* sthux */ 4678 4679 case AMOVWZ, AMOVW: 4680 return OPVCC(31, 151, 0, 0) /* stwx */ 4681 4682 case AMOVWZU, AMOVWU: 4683 return OPVCC(31, 183, 0, 0) /* stwux */ 4684 case ASTSW: 4685 return OPVCC(31, 661, 0, 0) /* stswx */ 4686 case AMOVWBR: 4687 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4688 case ASTBCCC: 4689 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4690 case ASTWCCC: 4691 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4692 case ASTDCCC: 4693 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4694 case AECOWX: 4695 return OPVCC(31, 438, 0, 0) /* ecowx */ 4696 case AMOVD: 4697 return OPVCC(31, 149, 0, 0) /* stdx */ 4698 case AMOVDU: 4699 return OPVCC(31, 181, 0, 0) /* stdux */ 4700 4701 /* Vector (VMX/Altivec) instructions */ 4702 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4703 /* are enabled starting at POWER6 (ISA 2.05). */ 4704 case ASTVEBX: 4705 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4706 case ASTVEHX: 4707 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4708 case ASTVEWX: 4709 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4710 case ASTVX: 4711 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4712 case ASTVXL: 4713 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4714 /* End of vector instructions */ 4715 4716 /* Vector scalar (VSX) instructions */ 4717 /* ISA 2.06 enables these for POWER7. */ 4718 case ASTXVD2X: 4719 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4720 case ASTXVW4X: 4721 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4722 4723 case ASTXSDX: 4724 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4725 4726 case ASTXSIWX: 4727 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4728 /* End of vector scalar instructions */ 4729 4730 } 4731 4732 c.ctxt.Diag("unknown storex opcode %v", a) 4733 return 0 4734 }