github.com/FenixAra/go@v0.0.0-20170127160404-96ea0918e670/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/s390x" 13 "cmd/internal/obj/x86" 14 ) 15 16 const ( 17 BlockInvalid BlockKind = iota 18 19 Block386EQ 20 Block386NE 21 Block386LT 22 Block386LE 23 Block386GT 24 Block386GE 25 Block386ULT 26 Block386ULE 27 Block386UGT 28 Block386UGE 29 Block386EQF 30 Block386NEF 31 Block386ORD 32 Block386NAN 33 34 BlockAMD64EQ 35 BlockAMD64NE 36 BlockAMD64LT 37 BlockAMD64LE 38 BlockAMD64GT 39 BlockAMD64GE 40 BlockAMD64ULT 41 BlockAMD64ULE 42 BlockAMD64UGT 43 BlockAMD64UGE 44 BlockAMD64EQF 45 BlockAMD64NEF 46 BlockAMD64ORD 47 BlockAMD64NAN 48 49 BlockARMEQ 50 BlockARMNE 51 BlockARMLT 52 BlockARMLE 53 BlockARMGT 54 BlockARMGE 55 BlockARMULT 56 BlockARMULE 57 BlockARMUGT 58 BlockARMUGE 59 60 BlockARM64EQ 61 BlockARM64NE 62 BlockARM64LT 63 BlockARM64LE 64 BlockARM64GT 65 BlockARM64GE 66 BlockARM64ULT 67 BlockARM64ULE 68 BlockARM64UGT 69 BlockARM64UGE 70 BlockARM64Z 71 BlockARM64NZ 72 BlockARM64ZW 73 BlockARM64NZW 74 75 BlockMIPSEQ 76 BlockMIPSNE 77 BlockMIPSLTZ 78 BlockMIPSLEZ 79 BlockMIPSGTZ 80 BlockMIPSGEZ 81 BlockMIPSFPT 82 BlockMIPSFPF 83 84 BlockMIPS64EQ 85 BlockMIPS64NE 86 BlockMIPS64LTZ 87 BlockMIPS64LEZ 88 BlockMIPS64GTZ 89 BlockMIPS64GEZ 90 BlockMIPS64FPT 91 BlockMIPS64FPF 92 93 BlockPPC64EQ 94 BlockPPC64NE 95 BlockPPC64LT 96 BlockPPC64LE 97 BlockPPC64GT 98 BlockPPC64GE 99 BlockPPC64FLT 100 BlockPPC64FLE 101 BlockPPC64FGT 102 BlockPPC64FGE 103 104 BlockS390XEQ 105 BlockS390XNE 106 BlockS390XLT 107 BlockS390XLE 108 BlockS390XGT 109 BlockS390XGE 110 BlockS390XGTF 111 BlockS390XGEF 112 113 BlockPlain 114 BlockIf 115 BlockDefer 116 BlockRet 117 BlockRetJmp 118 BlockExit 119 BlockFirst 120 ) 121 122 var blockString = [...]string{ 123 BlockInvalid: "BlockInvalid", 124 125 Block386EQ: "EQ", 126 Block386NE: "NE", 127 Block386LT: "LT", 128 Block386LE: "LE", 129 Block386GT: "GT", 130 Block386GE: "GE", 131 Block386ULT: "ULT", 132 Block386ULE: "ULE", 133 Block386UGT: "UGT", 134 Block386UGE: "UGE", 135 Block386EQF: "EQF", 136 Block386NEF: "NEF", 137 Block386ORD: "ORD", 138 Block386NAN: "NAN", 139 140 BlockAMD64EQ: "EQ", 141 BlockAMD64NE: "NE", 142 BlockAMD64LT: "LT", 143 BlockAMD64LE: "LE", 144 BlockAMD64GT: "GT", 145 BlockAMD64GE: "GE", 146 BlockAMD64ULT: "ULT", 147 BlockAMD64ULE: "ULE", 148 BlockAMD64UGT: "UGT", 149 BlockAMD64UGE: "UGE", 150 BlockAMD64EQF: "EQF", 151 BlockAMD64NEF: "NEF", 152 BlockAMD64ORD: "ORD", 153 BlockAMD64NAN: "NAN", 154 155 BlockARMEQ: "EQ", 156 BlockARMNE: "NE", 157 BlockARMLT: "LT", 158 BlockARMLE: "LE", 159 BlockARMGT: "GT", 160 BlockARMGE: "GE", 161 BlockARMULT: "ULT", 162 BlockARMULE: "ULE", 163 BlockARMUGT: "UGT", 164 BlockARMUGE: "UGE", 165 166 BlockARM64EQ: "EQ", 167 BlockARM64NE: "NE", 168 BlockARM64LT: "LT", 169 BlockARM64LE: "LE", 170 BlockARM64GT: "GT", 171 BlockARM64GE: "GE", 172 BlockARM64ULT: "ULT", 173 BlockARM64ULE: "ULE", 174 BlockARM64UGT: "UGT", 175 BlockARM64UGE: "UGE", 176 BlockARM64Z: "Z", 177 BlockARM64NZ: "NZ", 178 BlockARM64ZW: "ZW", 179 BlockARM64NZW: "NZW", 180 181 BlockMIPSEQ: "EQ", 182 BlockMIPSNE: "NE", 183 BlockMIPSLTZ: "LTZ", 184 BlockMIPSLEZ: "LEZ", 185 BlockMIPSGTZ: "GTZ", 186 BlockMIPSGEZ: "GEZ", 187 BlockMIPSFPT: "FPT", 188 BlockMIPSFPF: "FPF", 189 190 BlockMIPS64EQ: "EQ", 191 BlockMIPS64NE: "NE", 192 BlockMIPS64LTZ: "LTZ", 193 BlockMIPS64LEZ: "LEZ", 194 BlockMIPS64GTZ: "GTZ", 195 BlockMIPS64GEZ: "GEZ", 196 BlockMIPS64FPT: "FPT", 197 BlockMIPS64FPF: "FPF", 198 199 BlockPPC64EQ: "EQ", 200 BlockPPC64NE: "NE", 201 BlockPPC64LT: "LT", 202 BlockPPC64LE: "LE", 203 BlockPPC64GT: "GT", 204 BlockPPC64GE: "GE", 205 BlockPPC64FLT: "FLT", 206 BlockPPC64FLE: "FLE", 207 BlockPPC64FGT: "FGT", 208 BlockPPC64FGE: "FGE", 209 210 BlockS390XEQ: "EQ", 211 BlockS390XNE: "NE", 212 BlockS390XLT: "LT", 213 BlockS390XLE: "LE", 214 BlockS390XGT: "GT", 215 BlockS390XGE: "GE", 216 BlockS390XGTF: "GTF", 217 BlockS390XGEF: "GEF", 218 219 BlockPlain: "Plain", 220 BlockIf: "If", 221 BlockDefer: "Defer", 222 BlockRet: "Ret", 223 BlockRetJmp: "RetJmp", 224 BlockExit: "Exit", 225 BlockFirst: "First", 226 } 227 228 func (k BlockKind) String() string { return blockString[k] } 229 230 const ( 231 OpInvalid Op = iota 232 233 Op386ADDSS 234 Op386ADDSD 235 Op386SUBSS 236 Op386SUBSD 237 Op386MULSS 238 Op386MULSD 239 Op386DIVSS 240 Op386DIVSD 241 Op386MOVSSload 242 Op386MOVSDload 243 Op386MOVSSconst 244 Op386MOVSDconst 245 Op386MOVSSloadidx1 246 Op386MOVSSloadidx4 247 Op386MOVSDloadidx1 248 Op386MOVSDloadidx8 249 Op386MOVSSstore 250 Op386MOVSDstore 251 Op386MOVSSstoreidx1 252 Op386MOVSSstoreidx4 253 Op386MOVSDstoreidx1 254 Op386MOVSDstoreidx8 255 Op386ADDL 256 Op386ADDLconst 257 Op386ADDLcarry 258 Op386ADDLconstcarry 259 Op386ADCL 260 Op386ADCLconst 261 Op386SUBL 262 Op386SUBLconst 263 Op386SUBLcarry 264 Op386SUBLconstcarry 265 Op386SBBL 266 Op386SBBLconst 267 Op386MULL 268 Op386MULLconst 269 Op386HMULL 270 Op386HMULLU 271 Op386HMULW 272 Op386HMULB 273 Op386HMULWU 274 Op386HMULBU 275 Op386MULLQU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLdefer 394 Op386CALLgo 395 Op386CALLinter 396 Op386DUFFCOPY 397 Op386REPMOVSL 398 Op386InvertFlags 399 Op386LoweredGetG 400 Op386LoweredGetClosurePtr 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDQ 437 OpAMD64ADDL 438 OpAMD64ADDQconst 439 OpAMD64ADDLconst 440 OpAMD64SUBQ 441 OpAMD64SUBL 442 OpAMD64SUBQconst 443 OpAMD64SUBLconst 444 OpAMD64MULQ 445 OpAMD64MULL 446 OpAMD64MULQconst 447 OpAMD64MULLconst 448 OpAMD64HMULQ 449 OpAMD64HMULL 450 OpAMD64HMULW 451 OpAMD64HMULB 452 OpAMD64HMULQU 453 OpAMD64HMULLU 454 OpAMD64HMULWU 455 OpAMD64HMULBU 456 OpAMD64AVGQU 457 OpAMD64DIVQ 458 OpAMD64DIVL 459 OpAMD64DIVW 460 OpAMD64DIVQU 461 OpAMD64DIVLU 462 OpAMD64DIVWU 463 OpAMD64MULQU2 464 OpAMD64DIVQU2 465 OpAMD64ANDQ 466 OpAMD64ANDL 467 OpAMD64ANDQconst 468 OpAMD64ANDLconst 469 OpAMD64ORQ 470 OpAMD64ORL 471 OpAMD64ORQconst 472 OpAMD64ORLconst 473 OpAMD64XORQ 474 OpAMD64XORL 475 OpAMD64XORQconst 476 OpAMD64XORLconst 477 OpAMD64CMPQ 478 OpAMD64CMPL 479 OpAMD64CMPW 480 OpAMD64CMPB 481 OpAMD64CMPQconst 482 OpAMD64CMPLconst 483 OpAMD64CMPWconst 484 OpAMD64CMPBconst 485 OpAMD64UCOMISS 486 OpAMD64UCOMISD 487 OpAMD64TESTQ 488 OpAMD64TESTL 489 OpAMD64TESTW 490 OpAMD64TESTB 491 OpAMD64TESTQconst 492 OpAMD64TESTLconst 493 OpAMD64TESTWconst 494 OpAMD64TESTBconst 495 OpAMD64SHLQ 496 OpAMD64SHLL 497 OpAMD64SHLQconst 498 OpAMD64SHLLconst 499 OpAMD64SHRQ 500 OpAMD64SHRL 501 OpAMD64SHRW 502 OpAMD64SHRB 503 OpAMD64SHRQconst 504 OpAMD64SHRLconst 505 OpAMD64SHRWconst 506 OpAMD64SHRBconst 507 OpAMD64SARQ 508 OpAMD64SARL 509 OpAMD64SARW 510 OpAMD64SARB 511 OpAMD64SARQconst 512 OpAMD64SARLconst 513 OpAMD64SARWconst 514 OpAMD64SARBconst 515 OpAMD64ROLQconst 516 OpAMD64ROLLconst 517 OpAMD64ROLWconst 518 OpAMD64ROLBconst 519 OpAMD64NEGQ 520 OpAMD64NEGL 521 OpAMD64NOTQ 522 OpAMD64NOTL 523 OpAMD64BSFQ 524 OpAMD64BSFL 525 OpAMD64CMOVQEQ 526 OpAMD64CMOVLEQ 527 OpAMD64BSWAPQ 528 OpAMD64BSWAPL 529 OpAMD64SQRTSD 530 OpAMD64SBBQcarrymask 531 OpAMD64SBBLcarrymask 532 OpAMD64SETEQ 533 OpAMD64SETNE 534 OpAMD64SETL 535 OpAMD64SETLE 536 OpAMD64SETG 537 OpAMD64SETGE 538 OpAMD64SETB 539 OpAMD64SETBE 540 OpAMD64SETA 541 OpAMD64SETAE 542 OpAMD64SETEQF 543 OpAMD64SETNEF 544 OpAMD64SETORD 545 OpAMD64SETNAN 546 OpAMD64SETGF 547 OpAMD64SETGEF 548 OpAMD64MOVBQSX 549 OpAMD64MOVBQZX 550 OpAMD64MOVWQSX 551 OpAMD64MOVWQZX 552 OpAMD64MOVLQSX 553 OpAMD64MOVLQZX 554 OpAMD64MOVLconst 555 OpAMD64MOVQconst 556 OpAMD64CVTTSD2SL 557 OpAMD64CVTTSD2SQ 558 OpAMD64CVTTSS2SL 559 OpAMD64CVTTSS2SQ 560 OpAMD64CVTSL2SS 561 OpAMD64CVTSL2SD 562 OpAMD64CVTSQ2SS 563 OpAMD64CVTSQ2SD 564 OpAMD64CVTSD2SS 565 OpAMD64CVTSS2SD 566 OpAMD64PXOR 567 OpAMD64LEAQ 568 OpAMD64LEAQ1 569 OpAMD64LEAQ2 570 OpAMD64LEAQ4 571 OpAMD64LEAQ8 572 OpAMD64LEAL 573 OpAMD64MOVBload 574 OpAMD64MOVBQSXload 575 OpAMD64MOVWload 576 OpAMD64MOVWQSXload 577 OpAMD64MOVLload 578 OpAMD64MOVLQSXload 579 OpAMD64MOVQload 580 OpAMD64MOVBstore 581 OpAMD64MOVWstore 582 OpAMD64MOVLstore 583 OpAMD64MOVQstore 584 OpAMD64MOVOload 585 OpAMD64MOVOstore 586 OpAMD64MOVBloadidx1 587 OpAMD64MOVWloadidx1 588 OpAMD64MOVWloadidx2 589 OpAMD64MOVLloadidx1 590 OpAMD64MOVLloadidx4 591 OpAMD64MOVQloadidx1 592 OpAMD64MOVQloadidx8 593 OpAMD64MOVBstoreidx1 594 OpAMD64MOVWstoreidx1 595 OpAMD64MOVWstoreidx2 596 OpAMD64MOVLstoreidx1 597 OpAMD64MOVLstoreidx4 598 OpAMD64MOVQstoreidx1 599 OpAMD64MOVQstoreidx8 600 OpAMD64MOVBstoreconst 601 OpAMD64MOVWstoreconst 602 OpAMD64MOVLstoreconst 603 OpAMD64MOVQstoreconst 604 OpAMD64MOVBstoreconstidx1 605 OpAMD64MOVWstoreconstidx1 606 OpAMD64MOVWstoreconstidx2 607 OpAMD64MOVLstoreconstidx1 608 OpAMD64MOVLstoreconstidx4 609 OpAMD64MOVQstoreconstidx1 610 OpAMD64MOVQstoreconstidx8 611 OpAMD64DUFFZERO 612 OpAMD64MOVOconst 613 OpAMD64REPSTOSQ 614 OpAMD64CALLstatic 615 OpAMD64CALLclosure 616 OpAMD64CALLdefer 617 OpAMD64CALLgo 618 OpAMD64CALLinter 619 OpAMD64DUFFCOPY 620 OpAMD64REPMOVSQ 621 OpAMD64InvertFlags 622 OpAMD64LoweredGetG 623 OpAMD64LoweredGetClosurePtr 624 OpAMD64LoweredNilCheck 625 OpAMD64MOVQconvert 626 OpAMD64MOVLconvert 627 OpAMD64FlagEQ 628 OpAMD64FlagLT_ULT 629 OpAMD64FlagLT_UGT 630 OpAMD64FlagGT_UGT 631 OpAMD64FlagGT_ULT 632 OpAMD64MOVLatomicload 633 OpAMD64MOVQatomicload 634 OpAMD64XCHGL 635 OpAMD64XCHGQ 636 OpAMD64XADDLlock 637 OpAMD64XADDQlock 638 OpAMD64AddTupleFirst32 639 OpAMD64AddTupleFirst64 640 OpAMD64CMPXCHGLlock 641 OpAMD64CMPXCHGQlock 642 OpAMD64ANDBlock 643 OpAMD64ORBlock 644 645 OpARMADD 646 OpARMADDconst 647 OpARMSUB 648 OpARMSUBconst 649 OpARMRSB 650 OpARMRSBconst 651 OpARMMUL 652 OpARMHMUL 653 OpARMHMULU 654 OpARMUDIVrtcall 655 OpARMADDS 656 OpARMADDSconst 657 OpARMADC 658 OpARMADCconst 659 OpARMSUBS 660 OpARMSUBSconst 661 OpARMRSBSconst 662 OpARMSBC 663 OpARMSBCconst 664 OpARMRSCconst 665 OpARMMULLU 666 OpARMMULA 667 OpARMADDF 668 OpARMADDD 669 OpARMSUBF 670 OpARMSUBD 671 OpARMMULF 672 OpARMMULD 673 OpARMDIVF 674 OpARMDIVD 675 OpARMAND 676 OpARMANDconst 677 OpARMOR 678 OpARMORconst 679 OpARMXOR 680 OpARMXORconst 681 OpARMBIC 682 OpARMBICconst 683 OpARMMVN 684 OpARMNEGF 685 OpARMNEGD 686 OpARMSQRTD 687 OpARMCLZ 688 OpARMSLL 689 OpARMSLLconst 690 OpARMSRL 691 OpARMSRLconst 692 OpARMSRA 693 OpARMSRAconst 694 OpARMSRRconst 695 OpARMADDshiftLL 696 OpARMADDshiftRL 697 OpARMADDshiftRA 698 OpARMSUBshiftLL 699 OpARMSUBshiftRL 700 OpARMSUBshiftRA 701 OpARMRSBshiftLL 702 OpARMRSBshiftRL 703 OpARMRSBshiftRA 704 OpARMANDshiftLL 705 OpARMANDshiftRL 706 OpARMANDshiftRA 707 OpARMORshiftLL 708 OpARMORshiftRL 709 OpARMORshiftRA 710 OpARMXORshiftLL 711 OpARMXORshiftRL 712 OpARMXORshiftRA 713 OpARMXORshiftRR 714 OpARMBICshiftLL 715 OpARMBICshiftRL 716 OpARMBICshiftRA 717 OpARMMVNshiftLL 718 OpARMMVNshiftRL 719 OpARMMVNshiftRA 720 OpARMADCshiftLL 721 OpARMADCshiftRL 722 OpARMADCshiftRA 723 OpARMSBCshiftLL 724 OpARMSBCshiftRL 725 OpARMSBCshiftRA 726 OpARMRSCshiftLL 727 OpARMRSCshiftRL 728 OpARMRSCshiftRA 729 OpARMADDSshiftLL 730 OpARMADDSshiftRL 731 OpARMADDSshiftRA 732 OpARMSUBSshiftLL 733 OpARMSUBSshiftRL 734 OpARMSUBSshiftRA 735 OpARMRSBSshiftLL 736 OpARMRSBSshiftRL 737 OpARMRSBSshiftRA 738 OpARMADDshiftLLreg 739 OpARMADDshiftRLreg 740 OpARMADDshiftRAreg 741 OpARMSUBshiftLLreg 742 OpARMSUBshiftRLreg 743 OpARMSUBshiftRAreg 744 OpARMRSBshiftLLreg 745 OpARMRSBshiftRLreg 746 OpARMRSBshiftRAreg 747 OpARMANDshiftLLreg 748 OpARMANDshiftRLreg 749 OpARMANDshiftRAreg 750 OpARMORshiftLLreg 751 OpARMORshiftRLreg 752 OpARMORshiftRAreg 753 OpARMXORshiftLLreg 754 OpARMXORshiftRLreg 755 OpARMXORshiftRAreg 756 OpARMBICshiftLLreg 757 OpARMBICshiftRLreg 758 OpARMBICshiftRAreg 759 OpARMMVNshiftLLreg 760 OpARMMVNshiftRLreg 761 OpARMMVNshiftRAreg 762 OpARMADCshiftLLreg 763 OpARMADCshiftRLreg 764 OpARMADCshiftRAreg 765 OpARMSBCshiftLLreg 766 OpARMSBCshiftRLreg 767 OpARMSBCshiftRAreg 768 OpARMRSCshiftLLreg 769 OpARMRSCshiftRLreg 770 OpARMRSCshiftRAreg 771 OpARMADDSshiftLLreg 772 OpARMADDSshiftRLreg 773 OpARMADDSshiftRAreg 774 OpARMSUBSshiftLLreg 775 OpARMSUBSshiftRLreg 776 OpARMSUBSshiftRAreg 777 OpARMRSBSshiftLLreg 778 OpARMRSBSshiftRLreg 779 OpARMRSBSshiftRAreg 780 OpARMCMP 781 OpARMCMPconst 782 OpARMCMN 783 OpARMCMNconst 784 OpARMTST 785 OpARMTSTconst 786 OpARMTEQ 787 OpARMTEQconst 788 OpARMCMPF 789 OpARMCMPD 790 OpARMCMPshiftLL 791 OpARMCMPshiftRL 792 OpARMCMPshiftRA 793 OpARMCMPshiftLLreg 794 OpARMCMPshiftRLreg 795 OpARMCMPshiftRAreg 796 OpARMCMPF0 797 OpARMCMPD0 798 OpARMMOVWconst 799 OpARMMOVFconst 800 OpARMMOVDconst 801 OpARMMOVWaddr 802 OpARMMOVBload 803 OpARMMOVBUload 804 OpARMMOVHload 805 OpARMMOVHUload 806 OpARMMOVWload 807 OpARMMOVFload 808 OpARMMOVDload 809 OpARMMOVBstore 810 OpARMMOVHstore 811 OpARMMOVWstore 812 OpARMMOVFstore 813 OpARMMOVDstore 814 OpARMMOVWloadidx 815 OpARMMOVWloadshiftLL 816 OpARMMOVWloadshiftRL 817 OpARMMOVWloadshiftRA 818 OpARMMOVWstoreidx 819 OpARMMOVWstoreshiftLL 820 OpARMMOVWstoreshiftRL 821 OpARMMOVWstoreshiftRA 822 OpARMMOVBreg 823 OpARMMOVBUreg 824 OpARMMOVHreg 825 OpARMMOVHUreg 826 OpARMMOVWreg 827 OpARMMOVWnop 828 OpARMMOVWF 829 OpARMMOVWD 830 OpARMMOVWUF 831 OpARMMOVWUD 832 OpARMMOVFW 833 OpARMMOVDW 834 OpARMMOVFWU 835 OpARMMOVDWU 836 OpARMMOVFD 837 OpARMMOVDF 838 OpARMCMOVWHSconst 839 OpARMCMOVWLSconst 840 OpARMSRAcond 841 OpARMCALLstatic 842 OpARMCALLclosure 843 OpARMCALLdefer 844 OpARMCALLgo 845 OpARMCALLinter 846 OpARMLoweredNilCheck 847 OpARMEqual 848 OpARMNotEqual 849 OpARMLessThan 850 OpARMLessEqual 851 OpARMGreaterThan 852 OpARMGreaterEqual 853 OpARMLessThanU 854 OpARMLessEqualU 855 OpARMGreaterThanU 856 OpARMGreaterEqualU 857 OpARMDUFFZERO 858 OpARMDUFFCOPY 859 OpARMLoweredZero 860 OpARMLoweredMove 861 OpARMLoweredGetClosurePtr 862 OpARMMOVWconvert 863 OpARMFlagEQ 864 OpARMFlagLT_ULT 865 OpARMFlagLT_UGT 866 OpARMFlagGT_UGT 867 OpARMFlagGT_ULT 868 OpARMInvertFlags 869 870 OpARM64ADD 871 OpARM64ADDconst 872 OpARM64SUB 873 OpARM64SUBconst 874 OpARM64MUL 875 OpARM64MULW 876 OpARM64MULH 877 OpARM64UMULH 878 OpARM64MULL 879 OpARM64UMULL 880 OpARM64DIV 881 OpARM64UDIV 882 OpARM64DIVW 883 OpARM64UDIVW 884 OpARM64MOD 885 OpARM64UMOD 886 OpARM64MODW 887 OpARM64UMODW 888 OpARM64FADDS 889 OpARM64FADDD 890 OpARM64FSUBS 891 OpARM64FSUBD 892 OpARM64FMULS 893 OpARM64FMULD 894 OpARM64FDIVS 895 OpARM64FDIVD 896 OpARM64AND 897 OpARM64ANDconst 898 OpARM64OR 899 OpARM64ORconst 900 OpARM64XOR 901 OpARM64XORconst 902 OpARM64BIC 903 OpARM64BICconst 904 OpARM64MVN 905 OpARM64NEG 906 OpARM64FNEGS 907 OpARM64FNEGD 908 OpARM64FSQRTD 909 OpARM64REV 910 OpARM64REVW 911 OpARM64REV16W 912 OpARM64RBIT 913 OpARM64RBITW 914 OpARM64CLZ 915 OpARM64CLZW 916 OpARM64SLL 917 OpARM64SLLconst 918 OpARM64SRL 919 OpARM64SRLconst 920 OpARM64SRA 921 OpARM64SRAconst 922 OpARM64RORconst 923 OpARM64RORWconst 924 OpARM64CMP 925 OpARM64CMPconst 926 OpARM64CMPW 927 OpARM64CMPWconst 928 OpARM64CMN 929 OpARM64CMNconst 930 OpARM64CMNW 931 OpARM64CMNWconst 932 OpARM64FCMPS 933 OpARM64FCMPD 934 OpARM64ADDshiftLL 935 OpARM64ADDshiftRL 936 OpARM64ADDshiftRA 937 OpARM64SUBshiftLL 938 OpARM64SUBshiftRL 939 OpARM64SUBshiftRA 940 OpARM64ANDshiftLL 941 OpARM64ANDshiftRL 942 OpARM64ANDshiftRA 943 OpARM64ORshiftLL 944 OpARM64ORshiftRL 945 OpARM64ORshiftRA 946 OpARM64XORshiftLL 947 OpARM64XORshiftRL 948 OpARM64XORshiftRA 949 OpARM64BICshiftLL 950 OpARM64BICshiftRL 951 OpARM64BICshiftRA 952 OpARM64CMPshiftLL 953 OpARM64CMPshiftRL 954 OpARM64CMPshiftRA 955 OpARM64MOVDconst 956 OpARM64FMOVSconst 957 OpARM64FMOVDconst 958 OpARM64MOVDaddr 959 OpARM64MOVBload 960 OpARM64MOVBUload 961 OpARM64MOVHload 962 OpARM64MOVHUload 963 OpARM64MOVWload 964 OpARM64MOVWUload 965 OpARM64MOVDload 966 OpARM64FMOVSload 967 OpARM64FMOVDload 968 OpARM64MOVBstore 969 OpARM64MOVHstore 970 OpARM64MOVWstore 971 OpARM64MOVDstore 972 OpARM64FMOVSstore 973 OpARM64FMOVDstore 974 OpARM64MOVBstorezero 975 OpARM64MOVHstorezero 976 OpARM64MOVWstorezero 977 OpARM64MOVDstorezero 978 OpARM64MOVBreg 979 OpARM64MOVBUreg 980 OpARM64MOVHreg 981 OpARM64MOVHUreg 982 OpARM64MOVWreg 983 OpARM64MOVWUreg 984 OpARM64MOVDreg 985 OpARM64MOVDnop 986 OpARM64SCVTFWS 987 OpARM64SCVTFWD 988 OpARM64UCVTFWS 989 OpARM64UCVTFWD 990 OpARM64SCVTFS 991 OpARM64SCVTFD 992 OpARM64UCVTFS 993 OpARM64UCVTFD 994 OpARM64FCVTZSSW 995 OpARM64FCVTZSDW 996 OpARM64FCVTZUSW 997 OpARM64FCVTZUDW 998 OpARM64FCVTZSS 999 OpARM64FCVTZSD 1000 OpARM64FCVTZUS 1001 OpARM64FCVTZUD 1002 OpARM64FCVTSD 1003 OpARM64FCVTDS 1004 OpARM64CSELULT 1005 OpARM64CSELULT0 1006 OpARM64CALLstatic 1007 OpARM64CALLclosure 1008 OpARM64CALLdefer 1009 OpARM64CALLgo 1010 OpARM64CALLinter 1011 OpARM64LoweredNilCheck 1012 OpARM64Equal 1013 OpARM64NotEqual 1014 OpARM64LessThan 1015 OpARM64LessEqual 1016 OpARM64GreaterThan 1017 OpARM64GreaterEqual 1018 OpARM64LessThanU 1019 OpARM64LessEqualU 1020 OpARM64GreaterThanU 1021 OpARM64GreaterEqualU 1022 OpARM64DUFFZERO 1023 OpARM64LoweredZero 1024 OpARM64DUFFCOPY 1025 OpARM64LoweredMove 1026 OpARM64LoweredGetClosurePtr 1027 OpARM64MOVDconvert 1028 OpARM64FlagEQ 1029 OpARM64FlagLT_ULT 1030 OpARM64FlagLT_UGT 1031 OpARM64FlagGT_UGT 1032 OpARM64FlagGT_ULT 1033 OpARM64InvertFlags 1034 OpARM64LDAR 1035 OpARM64LDARW 1036 OpARM64STLR 1037 OpARM64STLRW 1038 OpARM64LoweredAtomicExchange64 1039 OpARM64LoweredAtomicExchange32 1040 OpARM64LoweredAtomicAdd64 1041 OpARM64LoweredAtomicAdd32 1042 OpARM64LoweredAtomicCas64 1043 OpARM64LoweredAtomicCas32 1044 OpARM64LoweredAtomicAnd8 1045 OpARM64LoweredAtomicOr8 1046 1047 OpMIPSADD 1048 OpMIPSADDconst 1049 OpMIPSSUB 1050 OpMIPSSUBconst 1051 OpMIPSMUL 1052 OpMIPSMULT 1053 OpMIPSMULTU 1054 OpMIPSDIV 1055 OpMIPSDIVU 1056 OpMIPSADDF 1057 OpMIPSADDD 1058 OpMIPSSUBF 1059 OpMIPSSUBD 1060 OpMIPSMULF 1061 OpMIPSMULD 1062 OpMIPSDIVF 1063 OpMIPSDIVD 1064 OpMIPSAND 1065 OpMIPSANDconst 1066 OpMIPSOR 1067 OpMIPSORconst 1068 OpMIPSXOR 1069 OpMIPSXORconst 1070 OpMIPSNOR 1071 OpMIPSNORconst 1072 OpMIPSNEG 1073 OpMIPSNEGF 1074 OpMIPSNEGD 1075 OpMIPSSQRTD 1076 OpMIPSSLL 1077 OpMIPSSLLconst 1078 OpMIPSSRL 1079 OpMIPSSRLconst 1080 OpMIPSSRA 1081 OpMIPSSRAconst 1082 OpMIPSCLZ 1083 OpMIPSSGT 1084 OpMIPSSGTconst 1085 OpMIPSSGTzero 1086 OpMIPSSGTU 1087 OpMIPSSGTUconst 1088 OpMIPSSGTUzero 1089 OpMIPSCMPEQF 1090 OpMIPSCMPEQD 1091 OpMIPSCMPGEF 1092 OpMIPSCMPGED 1093 OpMIPSCMPGTF 1094 OpMIPSCMPGTD 1095 OpMIPSMOVWconst 1096 OpMIPSMOVFconst 1097 OpMIPSMOVDconst 1098 OpMIPSMOVWaddr 1099 OpMIPSMOVBload 1100 OpMIPSMOVBUload 1101 OpMIPSMOVHload 1102 OpMIPSMOVHUload 1103 OpMIPSMOVWload 1104 OpMIPSMOVFload 1105 OpMIPSMOVDload 1106 OpMIPSMOVBstore 1107 OpMIPSMOVHstore 1108 OpMIPSMOVWstore 1109 OpMIPSMOVFstore 1110 OpMIPSMOVDstore 1111 OpMIPSMOVBstorezero 1112 OpMIPSMOVHstorezero 1113 OpMIPSMOVWstorezero 1114 OpMIPSMOVBreg 1115 OpMIPSMOVBUreg 1116 OpMIPSMOVHreg 1117 OpMIPSMOVHUreg 1118 OpMIPSMOVWreg 1119 OpMIPSMOVWnop 1120 OpMIPSCMOVZ 1121 OpMIPSCMOVZzero 1122 OpMIPSMOVWF 1123 OpMIPSMOVWD 1124 OpMIPSTRUNCFW 1125 OpMIPSTRUNCDW 1126 OpMIPSMOVFD 1127 OpMIPSMOVDF 1128 OpMIPSCALLstatic 1129 OpMIPSCALLclosure 1130 OpMIPSCALLdefer 1131 OpMIPSCALLgo 1132 OpMIPSCALLinter 1133 OpMIPSLoweredAtomicLoad 1134 OpMIPSLoweredAtomicStore 1135 OpMIPSLoweredAtomicStorezero 1136 OpMIPSLoweredAtomicExchange 1137 OpMIPSLoweredAtomicAdd 1138 OpMIPSLoweredAtomicAddconst 1139 OpMIPSLoweredAtomicCas 1140 OpMIPSLoweredAtomicAnd 1141 OpMIPSLoweredAtomicOr 1142 OpMIPSLoweredZero 1143 OpMIPSLoweredMove 1144 OpMIPSLoweredNilCheck 1145 OpMIPSFPFlagTrue 1146 OpMIPSFPFlagFalse 1147 OpMIPSLoweredGetClosurePtr 1148 OpMIPSMOVWconvert 1149 1150 OpMIPS64ADDV 1151 OpMIPS64ADDVconst 1152 OpMIPS64SUBV 1153 OpMIPS64SUBVconst 1154 OpMIPS64MULV 1155 OpMIPS64MULVU 1156 OpMIPS64DIVV 1157 OpMIPS64DIVVU 1158 OpMIPS64ADDF 1159 OpMIPS64ADDD 1160 OpMIPS64SUBF 1161 OpMIPS64SUBD 1162 OpMIPS64MULF 1163 OpMIPS64MULD 1164 OpMIPS64DIVF 1165 OpMIPS64DIVD 1166 OpMIPS64AND 1167 OpMIPS64ANDconst 1168 OpMIPS64OR 1169 OpMIPS64ORconst 1170 OpMIPS64XOR 1171 OpMIPS64XORconst 1172 OpMIPS64NOR 1173 OpMIPS64NORconst 1174 OpMIPS64NEGV 1175 OpMIPS64NEGF 1176 OpMIPS64NEGD 1177 OpMIPS64SLLV 1178 OpMIPS64SLLVconst 1179 OpMIPS64SRLV 1180 OpMIPS64SRLVconst 1181 OpMIPS64SRAV 1182 OpMIPS64SRAVconst 1183 OpMIPS64SGT 1184 OpMIPS64SGTconst 1185 OpMIPS64SGTU 1186 OpMIPS64SGTUconst 1187 OpMIPS64CMPEQF 1188 OpMIPS64CMPEQD 1189 OpMIPS64CMPGEF 1190 OpMIPS64CMPGED 1191 OpMIPS64CMPGTF 1192 OpMIPS64CMPGTD 1193 OpMIPS64MOVVconst 1194 OpMIPS64MOVFconst 1195 OpMIPS64MOVDconst 1196 OpMIPS64MOVVaddr 1197 OpMIPS64MOVBload 1198 OpMIPS64MOVBUload 1199 OpMIPS64MOVHload 1200 OpMIPS64MOVHUload 1201 OpMIPS64MOVWload 1202 OpMIPS64MOVWUload 1203 OpMIPS64MOVVload 1204 OpMIPS64MOVFload 1205 OpMIPS64MOVDload 1206 OpMIPS64MOVBstore 1207 OpMIPS64MOVHstore 1208 OpMIPS64MOVWstore 1209 OpMIPS64MOVVstore 1210 OpMIPS64MOVFstore 1211 OpMIPS64MOVDstore 1212 OpMIPS64MOVBstorezero 1213 OpMIPS64MOVHstorezero 1214 OpMIPS64MOVWstorezero 1215 OpMIPS64MOVVstorezero 1216 OpMIPS64MOVBreg 1217 OpMIPS64MOVBUreg 1218 OpMIPS64MOVHreg 1219 OpMIPS64MOVHUreg 1220 OpMIPS64MOVWreg 1221 OpMIPS64MOVWUreg 1222 OpMIPS64MOVVreg 1223 OpMIPS64MOVVnop 1224 OpMIPS64MOVWF 1225 OpMIPS64MOVWD 1226 OpMIPS64MOVVF 1227 OpMIPS64MOVVD 1228 OpMIPS64TRUNCFW 1229 OpMIPS64TRUNCDW 1230 OpMIPS64TRUNCFV 1231 OpMIPS64TRUNCDV 1232 OpMIPS64MOVFD 1233 OpMIPS64MOVDF 1234 OpMIPS64CALLstatic 1235 OpMIPS64CALLclosure 1236 OpMIPS64CALLdefer 1237 OpMIPS64CALLgo 1238 OpMIPS64CALLinter 1239 OpMIPS64DUFFZERO 1240 OpMIPS64LoweredZero 1241 OpMIPS64LoweredMove 1242 OpMIPS64LoweredNilCheck 1243 OpMIPS64FPFlagTrue 1244 OpMIPS64FPFlagFalse 1245 OpMIPS64LoweredGetClosurePtr 1246 OpMIPS64MOVVconvert 1247 1248 OpPPC64ADD 1249 OpPPC64ADDconst 1250 OpPPC64FADD 1251 OpPPC64FADDS 1252 OpPPC64SUB 1253 OpPPC64FSUB 1254 OpPPC64FSUBS 1255 OpPPC64MULLD 1256 OpPPC64MULLW 1257 OpPPC64MULHD 1258 OpPPC64MULHW 1259 OpPPC64MULHDU 1260 OpPPC64MULHWU 1261 OpPPC64FMUL 1262 OpPPC64FMULS 1263 OpPPC64SRAD 1264 OpPPC64SRAW 1265 OpPPC64SRD 1266 OpPPC64SRW 1267 OpPPC64SLD 1268 OpPPC64SLW 1269 OpPPC64ADDconstForCarry 1270 OpPPC64MaskIfNotCarry 1271 OpPPC64SRADconst 1272 OpPPC64SRAWconst 1273 OpPPC64SRDconst 1274 OpPPC64SRWconst 1275 OpPPC64SLDconst 1276 OpPPC64SLWconst 1277 OpPPC64FDIV 1278 OpPPC64FDIVS 1279 OpPPC64DIVD 1280 OpPPC64DIVW 1281 OpPPC64DIVDU 1282 OpPPC64DIVWU 1283 OpPPC64FCTIDZ 1284 OpPPC64FCTIWZ 1285 OpPPC64FCFID 1286 OpPPC64FRSP 1287 OpPPC64Xf2i64 1288 OpPPC64Xi2f64 1289 OpPPC64AND 1290 OpPPC64ANDN 1291 OpPPC64OR 1292 OpPPC64ORN 1293 OpPPC64XOR 1294 OpPPC64EQV 1295 OpPPC64NEG 1296 OpPPC64FNEG 1297 OpPPC64FSQRT 1298 OpPPC64FSQRTS 1299 OpPPC64ORconst 1300 OpPPC64XORconst 1301 OpPPC64ANDconst 1302 OpPPC64ANDCCconst 1303 OpPPC64MOVBreg 1304 OpPPC64MOVBZreg 1305 OpPPC64MOVHreg 1306 OpPPC64MOVHZreg 1307 OpPPC64MOVWreg 1308 OpPPC64MOVWZreg 1309 OpPPC64MOVBZload 1310 OpPPC64MOVHload 1311 OpPPC64MOVHZload 1312 OpPPC64MOVWload 1313 OpPPC64MOVWZload 1314 OpPPC64MOVDload 1315 OpPPC64FMOVDload 1316 OpPPC64FMOVSload 1317 OpPPC64MOVBstore 1318 OpPPC64MOVHstore 1319 OpPPC64MOVWstore 1320 OpPPC64MOVDstore 1321 OpPPC64FMOVDstore 1322 OpPPC64FMOVSstore 1323 OpPPC64MOVBstorezero 1324 OpPPC64MOVHstorezero 1325 OpPPC64MOVWstorezero 1326 OpPPC64MOVDstorezero 1327 OpPPC64MOVDaddr 1328 OpPPC64MOVDconst 1329 OpPPC64FMOVDconst 1330 OpPPC64FMOVSconst 1331 OpPPC64FCMPU 1332 OpPPC64CMP 1333 OpPPC64CMPU 1334 OpPPC64CMPW 1335 OpPPC64CMPWU 1336 OpPPC64CMPconst 1337 OpPPC64CMPUconst 1338 OpPPC64CMPWconst 1339 OpPPC64CMPWUconst 1340 OpPPC64Equal 1341 OpPPC64NotEqual 1342 OpPPC64LessThan 1343 OpPPC64FLessThan 1344 OpPPC64LessEqual 1345 OpPPC64FLessEqual 1346 OpPPC64GreaterThan 1347 OpPPC64FGreaterThan 1348 OpPPC64GreaterEqual 1349 OpPPC64FGreaterEqual 1350 OpPPC64LoweredGetClosurePtr 1351 OpPPC64LoweredNilCheck 1352 OpPPC64MOVDconvert 1353 OpPPC64CALLstatic 1354 OpPPC64CALLclosure 1355 OpPPC64CALLdefer 1356 OpPPC64CALLgo 1357 OpPPC64CALLinter 1358 OpPPC64LoweredZero 1359 OpPPC64LoweredMove 1360 OpPPC64InvertFlags 1361 OpPPC64FlagEQ 1362 OpPPC64FlagLT 1363 OpPPC64FlagGT 1364 1365 OpS390XFADDS 1366 OpS390XFADD 1367 OpS390XFSUBS 1368 OpS390XFSUB 1369 OpS390XFMULS 1370 OpS390XFMUL 1371 OpS390XFDIVS 1372 OpS390XFDIV 1373 OpS390XFNEGS 1374 OpS390XFNEG 1375 OpS390XFMOVSload 1376 OpS390XFMOVDload 1377 OpS390XFMOVSconst 1378 OpS390XFMOVDconst 1379 OpS390XFMOVSloadidx 1380 OpS390XFMOVDloadidx 1381 OpS390XFMOVSstore 1382 OpS390XFMOVDstore 1383 OpS390XFMOVSstoreidx 1384 OpS390XFMOVDstoreidx 1385 OpS390XADD 1386 OpS390XADDW 1387 OpS390XADDconst 1388 OpS390XADDWconst 1389 OpS390XADDload 1390 OpS390XADDWload 1391 OpS390XSUB 1392 OpS390XSUBW 1393 OpS390XSUBconst 1394 OpS390XSUBWconst 1395 OpS390XSUBload 1396 OpS390XSUBWload 1397 OpS390XMULLD 1398 OpS390XMULLW 1399 OpS390XMULLDconst 1400 OpS390XMULLWconst 1401 OpS390XMULLDload 1402 OpS390XMULLWload 1403 OpS390XMULHD 1404 OpS390XMULHDU 1405 OpS390XDIVD 1406 OpS390XDIVW 1407 OpS390XDIVDU 1408 OpS390XDIVWU 1409 OpS390XMODD 1410 OpS390XMODW 1411 OpS390XMODDU 1412 OpS390XMODWU 1413 OpS390XAND 1414 OpS390XANDW 1415 OpS390XANDconst 1416 OpS390XANDWconst 1417 OpS390XANDload 1418 OpS390XANDWload 1419 OpS390XOR 1420 OpS390XORW 1421 OpS390XORconst 1422 OpS390XORWconst 1423 OpS390XORload 1424 OpS390XORWload 1425 OpS390XXOR 1426 OpS390XXORW 1427 OpS390XXORconst 1428 OpS390XXORWconst 1429 OpS390XXORload 1430 OpS390XXORWload 1431 OpS390XCMP 1432 OpS390XCMPW 1433 OpS390XCMPU 1434 OpS390XCMPWU 1435 OpS390XCMPconst 1436 OpS390XCMPWconst 1437 OpS390XCMPUconst 1438 OpS390XCMPWUconst 1439 OpS390XFCMPS 1440 OpS390XFCMP 1441 OpS390XSLD 1442 OpS390XSLW 1443 OpS390XSLDconst 1444 OpS390XSLWconst 1445 OpS390XSRD 1446 OpS390XSRW 1447 OpS390XSRDconst 1448 OpS390XSRWconst 1449 OpS390XSRAD 1450 OpS390XSRAW 1451 OpS390XSRADconst 1452 OpS390XSRAWconst 1453 OpS390XRLLGconst 1454 OpS390XRLLconst 1455 OpS390XNEG 1456 OpS390XNEGW 1457 OpS390XNOT 1458 OpS390XNOTW 1459 OpS390XFSQRT 1460 OpS390XSUBEcarrymask 1461 OpS390XSUBEWcarrymask 1462 OpS390XMOVDEQ 1463 OpS390XMOVDNE 1464 OpS390XMOVDLT 1465 OpS390XMOVDLE 1466 OpS390XMOVDGT 1467 OpS390XMOVDGE 1468 OpS390XMOVDGTnoinv 1469 OpS390XMOVDGEnoinv 1470 OpS390XMOVBreg 1471 OpS390XMOVBZreg 1472 OpS390XMOVHreg 1473 OpS390XMOVHZreg 1474 OpS390XMOVWreg 1475 OpS390XMOVWZreg 1476 OpS390XMOVDconst 1477 OpS390XCFDBRA 1478 OpS390XCGDBRA 1479 OpS390XCFEBRA 1480 OpS390XCGEBRA 1481 OpS390XCEFBRA 1482 OpS390XCDFBRA 1483 OpS390XCEGBRA 1484 OpS390XCDGBRA 1485 OpS390XLEDBR 1486 OpS390XLDEBR 1487 OpS390XMOVDaddr 1488 OpS390XMOVDaddridx 1489 OpS390XMOVBZload 1490 OpS390XMOVBload 1491 OpS390XMOVHZload 1492 OpS390XMOVHload 1493 OpS390XMOVWZload 1494 OpS390XMOVWload 1495 OpS390XMOVDload 1496 OpS390XMOVWBR 1497 OpS390XMOVDBR 1498 OpS390XMOVHBRload 1499 OpS390XMOVWBRload 1500 OpS390XMOVDBRload 1501 OpS390XMOVBstore 1502 OpS390XMOVHstore 1503 OpS390XMOVWstore 1504 OpS390XMOVDstore 1505 OpS390XMOVHBRstore 1506 OpS390XMOVWBRstore 1507 OpS390XMOVDBRstore 1508 OpS390XMVC 1509 OpS390XMOVBZloadidx 1510 OpS390XMOVHZloadidx 1511 OpS390XMOVWZloadidx 1512 OpS390XMOVDloadidx 1513 OpS390XMOVHBRloadidx 1514 OpS390XMOVWBRloadidx 1515 OpS390XMOVDBRloadidx 1516 OpS390XMOVBstoreidx 1517 OpS390XMOVHstoreidx 1518 OpS390XMOVWstoreidx 1519 OpS390XMOVDstoreidx 1520 OpS390XMOVHBRstoreidx 1521 OpS390XMOVWBRstoreidx 1522 OpS390XMOVDBRstoreidx 1523 OpS390XMOVBstoreconst 1524 OpS390XMOVHstoreconst 1525 OpS390XMOVWstoreconst 1526 OpS390XMOVDstoreconst 1527 OpS390XCLEAR 1528 OpS390XCALLstatic 1529 OpS390XCALLclosure 1530 OpS390XCALLdefer 1531 OpS390XCALLgo 1532 OpS390XCALLinter 1533 OpS390XInvertFlags 1534 OpS390XLoweredGetG 1535 OpS390XLoweredGetClosurePtr 1536 OpS390XLoweredNilCheck 1537 OpS390XMOVDconvert 1538 OpS390XFlagEQ 1539 OpS390XFlagLT 1540 OpS390XFlagGT 1541 OpS390XMOVWZatomicload 1542 OpS390XMOVDatomicload 1543 OpS390XMOVWatomicstore 1544 OpS390XMOVDatomicstore 1545 OpS390XLAA 1546 OpS390XLAAG 1547 OpS390XAddTupleFirst32 1548 OpS390XAddTupleFirst64 1549 OpS390XLoweredAtomicCas32 1550 OpS390XLoweredAtomicCas64 1551 OpS390XLoweredAtomicExchange32 1552 OpS390XLoweredAtomicExchange64 1553 OpS390XFLOGR 1554 OpS390XSTMG2 1555 OpS390XSTMG3 1556 OpS390XSTMG4 1557 OpS390XSTM2 1558 OpS390XSTM3 1559 OpS390XSTM4 1560 OpS390XLoweredMove 1561 OpS390XLoweredZero 1562 1563 OpAdd8 1564 OpAdd16 1565 OpAdd32 1566 OpAdd64 1567 OpAddPtr 1568 OpAdd32F 1569 OpAdd64F 1570 OpSub8 1571 OpSub16 1572 OpSub32 1573 OpSub64 1574 OpSubPtr 1575 OpSub32F 1576 OpSub64F 1577 OpMul8 1578 OpMul16 1579 OpMul32 1580 OpMul64 1581 OpMul32F 1582 OpMul64F 1583 OpDiv32F 1584 OpDiv64F 1585 OpHmul8 1586 OpHmul8u 1587 OpHmul16 1588 OpHmul16u 1589 OpHmul32 1590 OpHmul32u 1591 OpHmul64 1592 OpHmul64u 1593 OpMul32uhilo 1594 OpMul64uhilo 1595 OpAvg64u 1596 OpDiv8 1597 OpDiv8u 1598 OpDiv16 1599 OpDiv16u 1600 OpDiv32 1601 OpDiv32u 1602 OpDiv64 1603 OpDiv64u 1604 OpDiv128u 1605 OpMod8 1606 OpMod8u 1607 OpMod16 1608 OpMod16u 1609 OpMod32 1610 OpMod32u 1611 OpMod64 1612 OpMod64u 1613 OpAnd8 1614 OpAnd16 1615 OpAnd32 1616 OpAnd64 1617 OpOr8 1618 OpOr16 1619 OpOr32 1620 OpOr64 1621 OpXor8 1622 OpXor16 1623 OpXor32 1624 OpXor64 1625 OpLsh8x8 1626 OpLsh8x16 1627 OpLsh8x32 1628 OpLsh8x64 1629 OpLsh16x8 1630 OpLsh16x16 1631 OpLsh16x32 1632 OpLsh16x64 1633 OpLsh32x8 1634 OpLsh32x16 1635 OpLsh32x32 1636 OpLsh32x64 1637 OpLsh64x8 1638 OpLsh64x16 1639 OpLsh64x32 1640 OpLsh64x64 1641 OpRsh8x8 1642 OpRsh8x16 1643 OpRsh8x32 1644 OpRsh8x64 1645 OpRsh16x8 1646 OpRsh16x16 1647 OpRsh16x32 1648 OpRsh16x64 1649 OpRsh32x8 1650 OpRsh32x16 1651 OpRsh32x32 1652 OpRsh32x64 1653 OpRsh64x8 1654 OpRsh64x16 1655 OpRsh64x32 1656 OpRsh64x64 1657 OpRsh8Ux8 1658 OpRsh8Ux16 1659 OpRsh8Ux32 1660 OpRsh8Ux64 1661 OpRsh16Ux8 1662 OpRsh16Ux16 1663 OpRsh16Ux32 1664 OpRsh16Ux64 1665 OpRsh32Ux8 1666 OpRsh32Ux16 1667 OpRsh32Ux32 1668 OpRsh32Ux64 1669 OpRsh64Ux8 1670 OpRsh64Ux16 1671 OpRsh64Ux32 1672 OpRsh64Ux64 1673 OpLrot8 1674 OpLrot16 1675 OpLrot32 1676 OpLrot64 1677 OpEq8 1678 OpEq16 1679 OpEq32 1680 OpEq64 1681 OpEqPtr 1682 OpEqInter 1683 OpEqSlice 1684 OpEq32F 1685 OpEq64F 1686 OpNeq8 1687 OpNeq16 1688 OpNeq32 1689 OpNeq64 1690 OpNeqPtr 1691 OpNeqInter 1692 OpNeqSlice 1693 OpNeq32F 1694 OpNeq64F 1695 OpLess8 1696 OpLess8U 1697 OpLess16 1698 OpLess16U 1699 OpLess32 1700 OpLess32U 1701 OpLess64 1702 OpLess64U 1703 OpLess32F 1704 OpLess64F 1705 OpLeq8 1706 OpLeq8U 1707 OpLeq16 1708 OpLeq16U 1709 OpLeq32 1710 OpLeq32U 1711 OpLeq64 1712 OpLeq64U 1713 OpLeq32F 1714 OpLeq64F 1715 OpGreater8 1716 OpGreater8U 1717 OpGreater16 1718 OpGreater16U 1719 OpGreater32 1720 OpGreater32U 1721 OpGreater64 1722 OpGreater64U 1723 OpGreater32F 1724 OpGreater64F 1725 OpGeq8 1726 OpGeq8U 1727 OpGeq16 1728 OpGeq16U 1729 OpGeq32 1730 OpGeq32U 1731 OpGeq64 1732 OpGeq64U 1733 OpGeq32F 1734 OpGeq64F 1735 OpAndB 1736 OpOrB 1737 OpEqB 1738 OpNeqB 1739 OpNot 1740 OpNeg8 1741 OpNeg16 1742 OpNeg32 1743 OpNeg64 1744 OpNeg32F 1745 OpNeg64F 1746 OpCom8 1747 OpCom16 1748 OpCom32 1749 OpCom64 1750 OpCtz32 1751 OpCtz64 1752 OpBswap32 1753 OpBswap64 1754 OpSqrt 1755 OpPhi 1756 OpCopy 1757 OpConvert 1758 OpConstBool 1759 OpConstString 1760 OpConstNil 1761 OpConst8 1762 OpConst16 1763 OpConst32 1764 OpConst64 1765 OpConst32F 1766 OpConst64F 1767 OpConstInterface 1768 OpConstSlice 1769 OpInitMem 1770 OpArg 1771 OpAddr 1772 OpSP 1773 OpSB 1774 OpFunc 1775 OpLoad 1776 OpStore 1777 OpMove 1778 OpZero 1779 OpStoreWB 1780 OpMoveWB 1781 OpMoveWBVolatile 1782 OpZeroWB 1783 OpClosureCall 1784 OpStaticCall 1785 OpDeferCall 1786 OpGoCall 1787 OpInterCall 1788 OpSignExt8to16 1789 OpSignExt8to32 1790 OpSignExt8to64 1791 OpSignExt16to32 1792 OpSignExt16to64 1793 OpSignExt32to64 1794 OpZeroExt8to16 1795 OpZeroExt8to32 1796 OpZeroExt8to64 1797 OpZeroExt16to32 1798 OpZeroExt16to64 1799 OpZeroExt32to64 1800 OpTrunc16to8 1801 OpTrunc32to8 1802 OpTrunc32to16 1803 OpTrunc64to8 1804 OpTrunc64to16 1805 OpTrunc64to32 1806 OpCvt32to32F 1807 OpCvt32to64F 1808 OpCvt64to32F 1809 OpCvt64to64F 1810 OpCvt32Fto32 1811 OpCvt32Fto64 1812 OpCvt64Fto32 1813 OpCvt64Fto64 1814 OpCvt32Fto64F 1815 OpCvt64Fto32F 1816 OpIsNonNil 1817 OpIsInBounds 1818 OpIsSliceInBounds 1819 OpNilCheck 1820 OpGetG 1821 OpGetClosurePtr 1822 OpPtrIndex 1823 OpOffPtr 1824 OpSliceMake 1825 OpSlicePtr 1826 OpSliceLen 1827 OpSliceCap 1828 OpComplexMake 1829 OpComplexReal 1830 OpComplexImag 1831 OpStringMake 1832 OpStringPtr 1833 OpStringLen 1834 OpIMake 1835 OpITab 1836 OpIData 1837 OpStructMake0 1838 OpStructMake1 1839 OpStructMake2 1840 OpStructMake3 1841 OpStructMake4 1842 OpStructSelect 1843 OpArrayMake0 1844 OpArrayMake1 1845 OpArraySelect 1846 OpStoreReg 1847 OpLoadReg 1848 OpFwdRef 1849 OpUnknown 1850 OpVarDef 1851 OpVarKill 1852 OpVarLive 1853 OpKeepAlive 1854 OpInt64Make 1855 OpInt64Hi 1856 OpInt64Lo 1857 OpAdd32carry 1858 OpAdd32withcarry 1859 OpSub32carry 1860 OpSub32withcarry 1861 OpSignmask 1862 OpZeromask 1863 OpSlicemask 1864 OpCvt32Uto32F 1865 OpCvt32Uto64F 1866 OpCvt32Fto32U 1867 OpCvt64Fto32U 1868 OpCvt64Uto32F 1869 OpCvt64Uto64F 1870 OpCvt32Fto64U 1871 OpCvt64Fto64U 1872 OpSelect0 1873 OpSelect1 1874 OpAtomicLoad32 1875 OpAtomicLoad64 1876 OpAtomicLoadPtr 1877 OpAtomicStore32 1878 OpAtomicStore64 1879 OpAtomicStorePtrNoWB 1880 OpAtomicExchange32 1881 OpAtomicExchange64 1882 OpAtomicAdd32 1883 OpAtomicAdd64 1884 OpAtomicCompareAndSwap32 1885 OpAtomicCompareAndSwap64 1886 OpAtomicAnd8 1887 OpAtomicOr8 1888 ) 1889 1890 var opcodeTable = [...]opInfo{ 1891 {name: "OpInvalid"}, 1892 1893 { 1894 name: "ADDSS", 1895 argLen: 2, 1896 commutative: true, 1897 resultInArg0: true, 1898 usesScratch: true, 1899 asm: x86.AADDSS, 1900 reg: regInfo{ 1901 inputs: []inputInfo{ 1902 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1903 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1904 }, 1905 outputs: []outputInfo{ 1906 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1907 }, 1908 }, 1909 }, 1910 { 1911 name: "ADDSD", 1912 argLen: 2, 1913 commutative: true, 1914 resultInArg0: true, 1915 asm: x86.AADDSD, 1916 reg: regInfo{ 1917 inputs: []inputInfo{ 1918 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1919 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1920 }, 1921 outputs: []outputInfo{ 1922 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1923 }, 1924 }, 1925 }, 1926 { 1927 name: "SUBSS", 1928 argLen: 2, 1929 resultInArg0: true, 1930 usesScratch: true, 1931 asm: x86.ASUBSS, 1932 reg: regInfo{ 1933 inputs: []inputInfo{ 1934 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1935 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1936 }, 1937 outputs: []outputInfo{ 1938 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1939 }, 1940 }, 1941 }, 1942 { 1943 name: "SUBSD", 1944 argLen: 2, 1945 resultInArg0: true, 1946 asm: x86.ASUBSD, 1947 reg: regInfo{ 1948 inputs: []inputInfo{ 1949 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1950 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1951 }, 1952 outputs: []outputInfo{ 1953 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1954 }, 1955 }, 1956 }, 1957 { 1958 name: "MULSS", 1959 argLen: 2, 1960 commutative: true, 1961 resultInArg0: true, 1962 usesScratch: true, 1963 asm: x86.AMULSS, 1964 reg: regInfo{ 1965 inputs: []inputInfo{ 1966 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1967 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1968 }, 1969 outputs: []outputInfo{ 1970 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1971 }, 1972 }, 1973 }, 1974 { 1975 name: "MULSD", 1976 argLen: 2, 1977 commutative: true, 1978 resultInArg0: true, 1979 asm: x86.AMULSD, 1980 reg: regInfo{ 1981 inputs: []inputInfo{ 1982 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1983 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1984 }, 1985 outputs: []outputInfo{ 1986 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1987 }, 1988 }, 1989 }, 1990 { 1991 name: "DIVSS", 1992 argLen: 2, 1993 resultInArg0: true, 1994 usesScratch: true, 1995 asm: x86.ADIVSS, 1996 reg: regInfo{ 1997 inputs: []inputInfo{ 1998 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1999 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2000 }, 2001 outputs: []outputInfo{ 2002 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2003 }, 2004 }, 2005 }, 2006 { 2007 name: "DIVSD", 2008 argLen: 2, 2009 resultInArg0: true, 2010 asm: x86.ADIVSD, 2011 reg: regInfo{ 2012 inputs: []inputInfo{ 2013 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2014 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2015 }, 2016 outputs: []outputInfo{ 2017 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2018 }, 2019 }, 2020 }, 2021 { 2022 name: "MOVSSload", 2023 auxType: auxSymOff, 2024 argLen: 2, 2025 faultOnNilArg0: true, 2026 asm: x86.AMOVSS, 2027 reg: regInfo{ 2028 inputs: []inputInfo{ 2029 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2030 }, 2031 outputs: []outputInfo{ 2032 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2033 }, 2034 }, 2035 }, 2036 { 2037 name: "MOVSDload", 2038 auxType: auxSymOff, 2039 argLen: 2, 2040 faultOnNilArg0: true, 2041 asm: x86.AMOVSD, 2042 reg: regInfo{ 2043 inputs: []inputInfo{ 2044 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2045 }, 2046 outputs: []outputInfo{ 2047 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2048 }, 2049 }, 2050 }, 2051 { 2052 name: "MOVSSconst", 2053 auxType: auxFloat32, 2054 argLen: 0, 2055 rematerializeable: true, 2056 asm: x86.AMOVSS, 2057 reg: regInfo{ 2058 outputs: []outputInfo{ 2059 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2060 }, 2061 }, 2062 }, 2063 { 2064 name: "MOVSDconst", 2065 auxType: auxFloat64, 2066 argLen: 0, 2067 rematerializeable: true, 2068 asm: x86.AMOVSD, 2069 reg: regInfo{ 2070 outputs: []outputInfo{ 2071 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2072 }, 2073 }, 2074 }, 2075 { 2076 name: "MOVSSloadidx1", 2077 auxType: auxSymOff, 2078 argLen: 3, 2079 asm: x86.AMOVSS, 2080 reg: regInfo{ 2081 inputs: []inputInfo{ 2082 {1, 255}, // AX CX DX BX SP BP SI DI 2083 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2084 }, 2085 outputs: []outputInfo{ 2086 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2087 }, 2088 }, 2089 }, 2090 { 2091 name: "MOVSSloadidx4", 2092 auxType: auxSymOff, 2093 argLen: 3, 2094 asm: x86.AMOVSS, 2095 reg: regInfo{ 2096 inputs: []inputInfo{ 2097 {1, 255}, // AX CX DX BX SP BP SI DI 2098 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2099 }, 2100 outputs: []outputInfo{ 2101 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2102 }, 2103 }, 2104 }, 2105 { 2106 name: "MOVSDloadidx1", 2107 auxType: auxSymOff, 2108 argLen: 3, 2109 asm: x86.AMOVSD, 2110 reg: regInfo{ 2111 inputs: []inputInfo{ 2112 {1, 255}, // AX CX DX BX SP BP SI DI 2113 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2114 }, 2115 outputs: []outputInfo{ 2116 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2117 }, 2118 }, 2119 }, 2120 { 2121 name: "MOVSDloadidx8", 2122 auxType: auxSymOff, 2123 argLen: 3, 2124 asm: x86.AMOVSD, 2125 reg: regInfo{ 2126 inputs: []inputInfo{ 2127 {1, 255}, // AX CX DX BX SP BP SI DI 2128 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2129 }, 2130 outputs: []outputInfo{ 2131 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2132 }, 2133 }, 2134 }, 2135 { 2136 name: "MOVSSstore", 2137 auxType: auxSymOff, 2138 argLen: 3, 2139 faultOnNilArg0: true, 2140 asm: x86.AMOVSS, 2141 reg: regInfo{ 2142 inputs: []inputInfo{ 2143 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2144 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2145 }, 2146 }, 2147 }, 2148 { 2149 name: "MOVSDstore", 2150 auxType: auxSymOff, 2151 argLen: 3, 2152 faultOnNilArg0: true, 2153 asm: x86.AMOVSD, 2154 reg: regInfo{ 2155 inputs: []inputInfo{ 2156 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2157 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2158 }, 2159 }, 2160 }, 2161 { 2162 name: "MOVSSstoreidx1", 2163 auxType: auxSymOff, 2164 argLen: 4, 2165 asm: x86.AMOVSS, 2166 reg: regInfo{ 2167 inputs: []inputInfo{ 2168 {1, 255}, // AX CX DX BX SP BP SI DI 2169 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2170 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2171 }, 2172 }, 2173 }, 2174 { 2175 name: "MOVSSstoreidx4", 2176 auxType: auxSymOff, 2177 argLen: 4, 2178 asm: x86.AMOVSS, 2179 reg: regInfo{ 2180 inputs: []inputInfo{ 2181 {1, 255}, // AX CX DX BX SP BP SI DI 2182 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2183 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2184 }, 2185 }, 2186 }, 2187 { 2188 name: "MOVSDstoreidx1", 2189 auxType: auxSymOff, 2190 argLen: 4, 2191 asm: x86.AMOVSD, 2192 reg: regInfo{ 2193 inputs: []inputInfo{ 2194 {1, 255}, // AX CX DX BX SP BP SI DI 2195 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2196 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2197 }, 2198 }, 2199 }, 2200 { 2201 name: "MOVSDstoreidx8", 2202 auxType: auxSymOff, 2203 argLen: 4, 2204 asm: x86.AMOVSD, 2205 reg: regInfo{ 2206 inputs: []inputInfo{ 2207 {1, 255}, // AX CX DX BX SP BP SI DI 2208 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2209 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2210 }, 2211 }, 2212 }, 2213 { 2214 name: "ADDL", 2215 argLen: 2, 2216 commutative: true, 2217 clobberFlags: true, 2218 asm: x86.AADDL, 2219 reg: regInfo{ 2220 inputs: []inputInfo{ 2221 {1, 239}, // AX CX DX BX BP SI DI 2222 {0, 255}, // AX CX DX BX SP BP SI DI 2223 }, 2224 outputs: []outputInfo{ 2225 {0, 239}, // AX CX DX BX BP SI DI 2226 }, 2227 }, 2228 }, 2229 { 2230 name: "ADDLconst", 2231 auxType: auxInt32, 2232 argLen: 1, 2233 clobberFlags: true, 2234 asm: x86.AADDL, 2235 reg: regInfo{ 2236 inputs: []inputInfo{ 2237 {0, 255}, // AX CX DX BX SP BP SI DI 2238 }, 2239 outputs: []outputInfo{ 2240 {0, 239}, // AX CX DX BX BP SI DI 2241 }, 2242 }, 2243 }, 2244 { 2245 name: "ADDLcarry", 2246 argLen: 2, 2247 commutative: true, 2248 resultInArg0: true, 2249 asm: x86.AADDL, 2250 reg: regInfo{ 2251 inputs: []inputInfo{ 2252 {0, 239}, // AX CX DX BX BP SI DI 2253 {1, 239}, // AX CX DX BX BP SI DI 2254 }, 2255 outputs: []outputInfo{ 2256 {1, 0}, 2257 {0, 239}, // AX CX DX BX BP SI DI 2258 }, 2259 }, 2260 }, 2261 { 2262 name: "ADDLconstcarry", 2263 auxType: auxInt32, 2264 argLen: 1, 2265 resultInArg0: true, 2266 asm: x86.AADDL, 2267 reg: regInfo{ 2268 inputs: []inputInfo{ 2269 {0, 239}, // AX CX DX BX BP SI DI 2270 }, 2271 outputs: []outputInfo{ 2272 {1, 0}, 2273 {0, 239}, // AX CX DX BX BP SI DI 2274 }, 2275 }, 2276 }, 2277 { 2278 name: "ADCL", 2279 argLen: 3, 2280 commutative: true, 2281 resultInArg0: true, 2282 clobberFlags: true, 2283 asm: x86.AADCL, 2284 reg: regInfo{ 2285 inputs: []inputInfo{ 2286 {0, 239}, // AX CX DX BX BP SI DI 2287 {1, 239}, // AX CX DX BX BP SI DI 2288 }, 2289 outputs: []outputInfo{ 2290 {0, 239}, // AX CX DX BX BP SI DI 2291 }, 2292 }, 2293 }, 2294 { 2295 name: "ADCLconst", 2296 auxType: auxInt32, 2297 argLen: 2, 2298 resultInArg0: true, 2299 clobberFlags: true, 2300 asm: x86.AADCL, 2301 reg: regInfo{ 2302 inputs: []inputInfo{ 2303 {0, 239}, // AX CX DX BX BP SI DI 2304 }, 2305 outputs: []outputInfo{ 2306 {0, 239}, // AX CX DX BX BP SI DI 2307 }, 2308 }, 2309 }, 2310 { 2311 name: "SUBL", 2312 argLen: 2, 2313 resultInArg0: true, 2314 clobberFlags: true, 2315 asm: x86.ASUBL, 2316 reg: regInfo{ 2317 inputs: []inputInfo{ 2318 {0, 239}, // AX CX DX BX BP SI DI 2319 {1, 239}, // AX CX DX BX BP SI DI 2320 }, 2321 outputs: []outputInfo{ 2322 {0, 239}, // AX CX DX BX BP SI DI 2323 }, 2324 }, 2325 }, 2326 { 2327 name: "SUBLconst", 2328 auxType: auxInt32, 2329 argLen: 1, 2330 resultInArg0: true, 2331 clobberFlags: true, 2332 asm: x86.ASUBL, 2333 reg: regInfo{ 2334 inputs: []inputInfo{ 2335 {0, 239}, // AX CX DX BX BP SI DI 2336 }, 2337 outputs: []outputInfo{ 2338 {0, 239}, // AX CX DX BX BP SI DI 2339 }, 2340 }, 2341 }, 2342 { 2343 name: "SUBLcarry", 2344 argLen: 2, 2345 resultInArg0: true, 2346 asm: x86.ASUBL, 2347 reg: regInfo{ 2348 inputs: []inputInfo{ 2349 {0, 239}, // AX CX DX BX BP SI DI 2350 {1, 239}, // AX CX DX BX BP SI DI 2351 }, 2352 outputs: []outputInfo{ 2353 {1, 0}, 2354 {0, 239}, // AX CX DX BX BP SI DI 2355 }, 2356 }, 2357 }, 2358 { 2359 name: "SUBLconstcarry", 2360 auxType: auxInt32, 2361 argLen: 1, 2362 resultInArg0: true, 2363 asm: x86.ASUBL, 2364 reg: regInfo{ 2365 inputs: []inputInfo{ 2366 {0, 239}, // AX CX DX BX BP SI DI 2367 }, 2368 outputs: []outputInfo{ 2369 {1, 0}, 2370 {0, 239}, // AX CX DX BX BP SI DI 2371 }, 2372 }, 2373 }, 2374 { 2375 name: "SBBL", 2376 argLen: 3, 2377 resultInArg0: true, 2378 clobberFlags: true, 2379 asm: x86.ASBBL, 2380 reg: regInfo{ 2381 inputs: []inputInfo{ 2382 {0, 239}, // AX CX DX BX BP SI DI 2383 {1, 239}, // AX CX DX BX BP SI DI 2384 }, 2385 outputs: []outputInfo{ 2386 {0, 239}, // AX CX DX BX BP SI DI 2387 }, 2388 }, 2389 }, 2390 { 2391 name: "SBBLconst", 2392 auxType: auxInt32, 2393 argLen: 2, 2394 resultInArg0: true, 2395 clobberFlags: true, 2396 asm: x86.ASBBL, 2397 reg: regInfo{ 2398 inputs: []inputInfo{ 2399 {0, 239}, // AX CX DX BX BP SI DI 2400 }, 2401 outputs: []outputInfo{ 2402 {0, 239}, // AX CX DX BX BP SI DI 2403 }, 2404 }, 2405 }, 2406 { 2407 name: "MULL", 2408 argLen: 2, 2409 commutative: true, 2410 resultInArg0: true, 2411 clobberFlags: true, 2412 asm: x86.AIMULL, 2413 reg: regInfo{ 2414 inputs: []inputInfo{ 2415 {0, 239}, // AX CX DX BX BP SI DI 2416 {1, 239}, // AX CX DX BX BP SI DI 2417 }, 2418 outputs: []outputInfo{ 2419 {0, 239}, // AX CX DX BX BP SI DI 2420 }, 2421 }, 2422 }, 2423 { 2424 name: "MULLconst", 2425 auxType: auxInt32, 2426 argLen: 1, 2427 resultInArg0: true, 2428 clobberFlags: true, 2429 asm: x86.AIMULL, 2430 reg: regInfo{ 2431 inputs: []inputInfo{ 2432 {0, 239}, // AX CX DX BX BP SI DI 2433 }, 2434 outputs: []outputInfo{ 2435 {0, 239}, // AX CX DX BX BP SI DI 2436 }, 2437 }, 2438 }, 2439 { 2440 name: "HMULL", 2441 argLen: 2, 2442 clobberFlags: true, 2443 asm: x86.AIMULL, 2444 reg: regInfo{ 2445 inputs: []inputInfo{ 2446 {0, 1}, // AX 2447 {1, 255}, // AX CX DX BX SP BP SI DI 2448 }, 2449 clobbers: 1, // AX 2450 outputs: []outputInfo{ 2451 {0, 4}, // DX 2452 }, 2453 }, 2454 }, 2455 { 2456 name: "HMULLU", 2457 argLen: 2, 2458 clobberFlags: true, 2459 asm: x86.AMULL, 2460 reg: regInfo{ 2461 inputs: []inputInfo{ 2462 {0, 1}, // AX 2463 {1, 255}, // AX CX DX BX SP BP SI DI 2464 }, 2465 clobbers: 1, // AX 2466 outputs: []outputInfo{ 2467 {0, 4}, // DX 2468 }, 2469 }, 2470 }, 2471 { 2472 name: "HMULW", 2473 argLen: 2, 2474 clobberFlags: true, 2475 asm: x86.AIMULW, 2476 reg: regInfo{ 2477 inputs: []inputInfo{ 2478 {0, 1}, // AX 2479 {1, 255}, // AX CX DX BX SP BP SI DI 2480 }, 2481 clobbers: 1, // AX 2482 outputs: []outputInfo{ 2483 {0, 4}, // DX 2484 }, 2485 }, 2486 }, 2487 { 2488 name: "HMULB", 2489 argLen: 2, 2490 clobberFlags: true, 2491 asm: x86.AIMULB, 2492 reg: regInfo{ 2493 inputs: []inputInfo{ 2494 {0, 1}, // AX 2495 {1, 255}, // AX CX DX BX SP BP SI DI 2496 }, 2497 clobbers: 1, // AX 2498 outputs: []outputInfo{ 2499 {0, 4}, // DX 2500 }, 2501 }, 2502 }, 2503 { 2504 name: "HMULWU", 2505 argLen: 2, 2506 clobberFlags: true, 2507 asm: x86.AMULW, 2508 reg: regInfo{ 2509 inputs: []inputInfo{ 2510 {0, 1}, // AX 2511 {1, 255}, // AX CX DX BX SP BP SI DI 2512 }, 2513 clobbers: 1, // AX 2514 outputs: []outputInfo{ 2515 {0, 4}, // DX 2516 }, 2517 }, 2518 }, 2519 { 2520 name: "HMULBU", 2521 argLen: 2, 2522 clobberFlags: true, 2523 asm: x86.AMULB, 2524 reg: regInfo{ 2525 inputs: []inputInfo{ 2526 {0, 1}, // AX 2527 {1, 255}, // AX CX DX BX SP BP SI DI 2528 }, 2529 clobbers: 1, // AX 2530 outputs: []outputInfo{ 2531 {0, 4}, // DX 2532 }, 2533 }, 2534 }, 2535 { 2536 name: "MULLQU", 2537 argLen: 2, 2538 clobberFlags: true, 2539 asm: x86.AMULL, 2540 reg: regInfo{ 2541 inputs: []inputInfo{ 2542 {0, 1}, // AX 2543 {1, 255}, // AX CX DX BX SP BP SI DI 2544 }, 2545 outputs: []outputInfo{ 2546 {0, 4}, // DX 2547 {1, 1}, // AX 2548 }, 2549 }, 2550 }, 2551 { 2552 name: "DIVL", 2553 argLen: 2, 2554 clobberFlags: true, 2555 asm: x86.AIDIVL, 2556 reg: regInfo{ 2557 inputs: []inputInfo{ 2558 {0, 1}, // AX 2559 {1, 251}, // AX CX BX SP BP SI DI 2560 }, 2561 clobbers: 4, // DX 2562 outputs: []outputInfo{ 2563 {0, 1}, // AX 2564 }, 2565 }, 2566 }, 2567 { 2568 name: "DIVW", 2569 argLen: 2, 2570 clobberFlags: true, 2571 asm: x86.AIDIVW, 2572 reg: regInfo{ 2573 inputs: []inputInfo{ 2574 {0, 1}, // AX 2575 {1, 251}, // AX CX BX SP BP SI DI 2576 }, 2577 clobbers: 4, // DX 2578 outputs: []outputInfo{ 2579 {0, 1}, // AX 2580 }, 2581 }, 2582 }, 2583 { 2584 name: "DIVLU", 2585 argLen: 2, 2586 clobberFlags: true, 2587 asm: x86.ADIVL, 2588 reg: regInfo{ 2589 inputs: []inputInfo{ 2590 {0, 1}, // AX 2591 {1, 251}, // AX CX BX SP BP SI DI 2592 }, 2593 clobbers: 4, // DX 2594 outputs: []outputInfo{ 2595 {0, 1}, // AX 2596 }, 2597 }, 2598 }, 2599 { 2600 name: "DIVWU", 2601 argLen: 2, 2602 clobberFlags: true, 2603 asm: x86.ADIVW, 2604 reg: regInfo{ 2605 inputs: []inputInfo{ 2606 {0, 1}, // AX 2607 {1, 251}, // AX CX BX SP BP SI DI 2608 }, 2609 clobbers: 4, // DX 2610 outputs: []outputInfo{ 2611 {0, 1}, // AX 2612 }, 2613 }, 2614 }, 2615 { 2616 name: "MODL", 2617 argLen: 2, 2618 clobberFlags: true, 2619 asm: x86.AIDIVL, 2620 reg: regInfo{ 2621 inputs: []inputInfo{ 2622 {0, 1}, // AX 2623 {1, 251}, // AX CX BX SP BP SI DI 2624 }, 2625 clobbers: 1, // AX 2626 outputs: []outputInfo{ 2627 {0, 4}, // DX 2628 }, 2629 }, 2630 }, 2631 { 2632 name: "MODW", 2633 argLen: 2, 2634 clobberFlags: true, 2635 asm: x86.AIDIVW, 2636 reg: regInfo{ 2637 inputs: []inputInfo{ 2638 {0, 1}, // AX 2639 {1, 251}, // AX CX BX SP BP SI DI 2640 }, 2641 clobbers: 1, // AX 2642 outputs: []outputInfo{ 2643 {0, 4}, // DX 2644 }, 2645 }, 2646 }, 2647 { 2648 name: "MODLU", 2649 argLen: 2, 2650 clobberFlags: true, 2651 asm: x86.ADIVL, 2652 reg: regInfo{ 2653 inputs: []inputInfo{ 2654 {0, 1}, // AX 2655 {1, 251}, // AX CX BX SP BP SI DI 2656 }, 2657 clobbers: 1, // AX 2658 outputs: []outputInfo{ 2659 {0, 4}, // DX 2660 }, 2661 }, 2662 }, 2663 { 2664 name: "MODWU", 2665 argLen: 2, 2666 clobberFlags: true, 2667 asm: x86.ADIVW, 2668 reg: regInfo{ 2669 inputs: []inputInfo{ 2670 {0, 1}, // AX 2671 {1, 251}, // AX CX BX SP BP SI DI 2672 }, 2673 clobbers: 1, // AX 2674 outputs: []outputInfo{ 2675 {0, 4}, // DX 2676 }, 2677 }, 2678 }, 2679 { 2680 name: "ANDL", 2681 argLen: 2, 2682 commutative: true, 2683 resultInArg0: true, 2684 clobberFlags: true, 2685 asm: x86.AANDL, 2686 reg: regInfo{ 2687 inputs: []inputInfo{ 2688 {0, 239}, // AX CX DX BX BP SI DI 2689 {1, 239}, // AX CX DX BX BP SI DI 2690 }, 2691 outputs: []outputInfo{ 2692 {0, 239}, // AX CX DX BX BP SI DI 2693 }, 2694 }, 2695 }, 2696 { 2697 name: "ANDLconst", 2698 auxType: auxInt32, 2699 argLen: 1, 2700 resultInArg0: true, 2701 clobberFlags: true, 2702 asm: x86.AANDL, 2703 reg: regInfo{ 2704 inputs: []inputInfo{ 2705 {0, 239}, // AX CX DX BX BP SI DI 2706 }, 2707 outputs: []outputInfo{ 2708 {0, 239}, // AX CX DX BX BP SI DI 2709 }, 2710 }, 2711 }, 2712 { 2713 name: "ORL", 2714 argLen: 2, 2715 commutative: true, 2716 resultInArg0: true, 2717 clobberFlags: true, 2718 asm: x86.AORL, 2719 reg: regInfo{ 2720 inputs: []inputInfo{ 2721 {0, 239}, // AX CX DX BX BP SI DI 2722 {1, 239}, // AX CX DX BX BP SI DI 2723 }, 2724 outputs: []outputInfo{ 2725 {0, 239}, // AX CX DX BX BP SI DI 2726 }, 2727 }, 2728 }, 2729 { 2730 name: "ORLconst", 2731 auxType: auxInt32, 2732 argLen: 1, 2733 resultInArg0: true, 2734 clobberFlags: true, 2735 asm: x86.AORL, 2736 reg: regInfo{ 2737 inputs: []inputInfo{ 2738 {0, 239}, // AX CX DX BX BP SI DI 2739 }, 2740 outputs: []outputInfo{ 2741 {0, 239}, // AX CX DX BX BP SI DI 2742 }, 2743 }, 2744 }, 2745 { 2746 name: "XORL", 2747 argLen: 2, 2748 commutative: true, 2749 resultInArg0: true, 2750 clobberFlags: true, 2751 asm: x86.AXORL, 2752 reg: regInfo{ 2753 inputs: []inputInfo{ 2754 {0, 239}, // AX CX DX BX BP SI DI 2755 {1, 239}, // AX CX DX BX BP SI DI 2756 }, 2757 outputs: []outputInfo{ 2758 {0, 239}, // AX CX DX BX BP SI DI 2759 }, 2760 }, 2761 }, 2762 { 2763 name: "XORLconst", 2764 auxType: auxInt32, 2765 argLen: 1, 2766 resultInArg0: true, 2767 clobberFlags: true, 2768 asm: x86.AXORL, 2769 reg: regInfo{ 2770 inputs: []inputInfo{ 2771 {0, 239}, // AX CX DX BX BP SI DI 2772 }, 2773 outputs: []outputInfo{ 2774 {0, 239}, // AX CX DX BX BP SI DI 2775 }, 2776 }, 2777 }, 2778 { 2779 name: "CMPL", 2780 argLen: 2, 2781 asm: x86.ACMPL, 2782 reg: regInfo{ 2783 inputs: []inputInfo{ 2784 {0, 255}, // AX CX DX BX SP BP SI DI 2785 {1, 255}, // AX CX DX BX SP BP SI DI 2786 }, 2787 }, 2788 }, 2789 { 2790 name: "CMPW", 2791 argLen: 2, 2792 asm: x86.ACMPW, 2793 reg: regInfo{ 2794 inputs: []inputInfo{ 2795 {0, 255}, // AX CX DX BX SP BP SI DI 2796 {1, 255}, // AX CX DX BX SP BP SI DI 2797 }, 2798 }, 2799 }, 2800 { 2801 name: "CMPB", 2802 argLen: 2, 2803 asm: x86.ACMPB, 2804 reg: regInfo{ 2805 inputs: []inputInfo{ 2806 {0, 255}, // AX CX DX BX SP BP SI DI 2807 {1, 255}, // AX CX DX BX SP BP SI DI 2808 }, 2809 }, 2810 }, 2811 { 2812 name: "CMPLconst", 2813 auxType: auxInt32, 2814 argLen: 1, 2815 asm: x86.ACMPL, 2816 reg: regInfo{ 2817 inputs: []inputInfo{ 2818 {0, 255}, // AX CX DX BX SP BP SI DI 2819 }, 2820 }, 2821 }, 2822 { 2823 name: "CMPWconst", 2824 auxType: auxInt16, 2825 argLen: 1, 2826 asm: x86.ACMPW, 2827 reg: regInfo{ 2828 inputs: []inputInfo{ 2829 {0, 255}, // AX CX DX BX SP BP SI DI 2830 }, 2831 }, 2832 }, 2833 { 2834 name: "CMPBconst", 2835 auxType: auxInt8, 2836 argLen: 1, 2837 asm: x86.ACMPB, 2838 reg: regInfo{ 2839 inputs: []inputInfo{ 2840 {0, 255}, // AX CX DX BX SP BP SI DI 2841 }, 2842 }, 2843 }, 2844 { 2845 name: "UCOMISS", 2846 argLen: 2, 2847 usesScratch: true, 2848 asm: x86.AUCOMISS, 2849 reg: regInfo{ 2850 inputs: []inputInfo{ 2851 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2852 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2853 }, 2854 }, 2855 }, 2856 { 2857 name: "UCOMISD", 2858 argLen: 2, 2859 usesScratch: true, 2860 asm: x86.AUCOMISD, 2861 reg: regInfo{ 2862 inputs: []inputInfo{ 2863 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2864 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2865 }, 2866 }, 2867 }, 2868 { 2869 name: "TESTL", 2870 argLen: 2, 2871 asm: x86.ATESTL, 2872 reg: regInfo{ 2873 inputs: []inputInfo{ 2874 {0, 255}, // AX CX DX BX SP BP SI DI 2875 {1, 255}, // AX CX DX BX SP BP SI DI 2876 }, 2877 }, 2878 }, 2879 { 2880 name: "TESTW", 2881 argLen: 2, 2882 asm: x86.ATESTW, 2883 reg: regInfo{ 2884 inputs: []inputInfo{ 2885 {0, 255}, // AX CX DX BX SP BP SI DI 2886 {1, 255}, // AX CX DX BX SP BP SI DI 2887 }, 2888 }, 2889 }, 2890 { 2891 name: "TESTB", 2892 argLen: 2, 2893 asm: x86.ATESTB, 2894 reg: regInfo{ 2895 inputs: []inputInfo{ 2896 {0, 255}, // AX CX DX BX SP BP SI DI 2897 {1, 255}, // AX CX DX BX SP BP SI DI 2898 }, 2899 }, 2900 }, 2901 { 2902 name: "TESTLconst", 2903 auxType: auxInt32, 2904 argLen: 1, 2905 asm: x86.ATESTL, 2906 reg: regInfo{ 2907 inputs: []inputInfo{ 2908 {0, 255}, // AX CX DX BX SP BP SI DI 2909 }, 2910 }, 2911 }, 2912 { 2913 name: "TESTWconst", 2914 auxType: auxInt16, 2915 argLen: 1, 2916 asm: x86.ATESTW, 2917 reg: regInfo{ 2918 inputs: []inputInfo{ 2919 {0, 255}, // AX CX DX BX SP BP SI DI 2920 }, 2921 }, 2922 }, 2923 { 2924 name: "TESTBconst", 2925 auxType: auxInt8, 2926 argLen: 1, 2927 asm: x86.ATESTB, 2928 reg: regInfo{ 2929 inputs: []inputInfo{ 2930 {0, 255}, // AX CX DX BX SP BP SI DI 2931 }, 2932 }, 2933 }, 2934 { 2935 name: "SHLL", 2936 argLen: 2, 2937 resultInArg0: true, 2938 clobberFlags: true, 2939 asm: x86.ASHLL, 2940 reg: regInfo{ 2941 inputs: []inputInfo{ 2942 {1, 2}, // CX 2943 {0, 239}, // AX CX DX BX BP SI DI 2944 }, 2945 outputs: []outputInfo{ 2946 {0, 239}, // AX CX DX BX BP SI DI 2947 }, 2948 }, 2949 }, 2950 { 2951 name: "SHLLconst", 2952 auxType: auxInt32, 2953 argLen: 1, 2954 resultInArg0: true, 2955 clobberFlags: true, 2956 asm: x86.ASHLL, 2957 reg: regInfo{ 2958 inputs: []inputInfo{ 2959 {0, 239}, // AX CX DX BX BP SI DI 2960 }, 2961 outputs: []outputInfo{ 2962 {0, 239}, // AX CX DX BX BP SI DI 2963 }, 2964 }, 2965 }, 2966 { 2967 name: "SHRL", 2968 argLen: 2, 2969 resultInArg0: true, 2970 clobberFlags: true, 2971 asm: x86.ASHRL, 2972 reg: regInfo{ 2973 inputs: []inputInfo{ 2974 {1, 2}, // CX 2975 {0, 239}, // AX CX DX BX BP SI DI 2976 }, 2977 outputs: []outputInfo{ 2978 {0, 239}, // AX CX DX BX BP SI DI 2979 }, 2980 }, 2981 }, 2982 { 2983 name: "SHRW", 2984 argLen: 2, 2985 resultInArg0: true, 2986 clobberFlags: true, 2987 asm: x86.ASHRW, 2988 reg: regInfo{ 2989 inputs: []inputInfo{ 2990 {1, 2}, // CX 2991 {0, 239}, // AX CX DX BX BP SI DI 2992 }, 2993 outputs: []outputInfo{ 2994 {0, 239}, // AX CX DX BX BP SI DI 2995 }, 2996 }, 2997 }, 2998 { 2999 name: "SHRB", 3000 argLen: 2, 3001 resultInArg0: true, 3002 clobberFlags: true, 3003 asm: x86.ASHRB, 3004 reg: regInfo{ 3005 inputs: []inputInfo{ 3006 {1, 2}, // CX 3007 {0, 239}, // AX CX DX BX BP SI DI 3008 }, 3009 outputs: []outputInfo{ 3010 {0, 239}, // AX CX DX BX BP SI DI 3011 }, 3012 }, 3013 }, 3014 { 3015 name: "SHRLconst", 3016 auxType: auxInt32, 3017 argLen: 1, 3018 resultInArg0: true, 3019 clobberFlags: true, 3020 asm: x86.ASHRL, 3021 reg: regInfo{ 3022 inputs: []inputInfo{ 3023 {0, 239}, // AX CX DX BX BP SI DI 3024 }, 3025 outputs: []outputInfo{ 3026 {0, 239}, // AX CX DX BX BP SI DI 3027 }, 3028 }, 3029 }, 3030 { 3031 name: "SHRWconst", 3032 auxType: auxInt16, 3033 argLen: 1, 3034 resultInArg0: true, 3035 clobberFlags: true, 3036 asm: x86.ASHRW, 3037 reg: regInfo{ 3038 inputs: []inputInfo{ 3039 {0, 239}, // AX CX DX BX BP SI DI 3040 }, 3041 outputs: []outputInfo{ 3042 {0, 239}, // AX CX DX BX BP SI DI 3043 }, 3044 }, 3045 }, 3046 { 3047 name: "SHRBconst", 3048 auxType: auxInt8, 3049 argLen: 1, 3050 resultInArg0: true, 3051 clobberFlags: true, 3052 asm: x86.ASHRB, 3053 reg: regInfo{ 3054 inputs: []inputInfo{ 3055 {0, 239}, // AX CX DX BX BP SI DI 3056 }, 3057 outputs: []outputInfo{ 3058 {0, 239}, // AX CX DX BX BP SI DI 3059 }, 3060 }, 3061 }, 3062 { 3063 name: "SARL", 3064 argLen: 2, 3065 resultInArg0: true, 3066 clobberFlags: true, 3067 asm: x86.ASARL, 3068 reg: regInfo{ 3069 inputs: []inputInfo{ 3070 {1, 2}, // CX 3071 {0, 239}, // AX CX DX BX BP SI DI 3072 }, 3073 outputs: []outputInfo{ 3074 {0, 239}, // AX CX DX BX BP SI DI 3075 }, 3076 }, 3077 }, 3078 { 3079 name: "SARW", 3080 argLen: 2, 3081 resultInArg0: true, 3082 clobberFlags: true, 3083 asm: x86.ASARW, 3084 reg: regInfo{ 3085 inputs: []inputInfo{ 3086 {1, 2}, // CX 3087 {0, 239}, // AX CX DX BX BP SI DI 3088 }, 3089 outputs: []outputInfo{ 3090 {0, 239}, // AX CX DX BX BP SI DI 3091 }, 3092 }, 3093 }, 3094 { 3095 name: "SARB", 3096 argLen: 2, 3097 resultInArg0: true, 3098 clobberFlags: true, 3099 asm: x86.ASARB, 3100 reg: regInfo{ 3101 inputs: []inputInfo{ 3102 {1, 2}, // CX 3103 {0, 239}, // AX CX DX BX BP SI DI 3104 }, 3105 outputs: []outputInfo{ 3106 {0, 239}, // AX CX DX BX BP SI DI 3107 }, 3108 }, 3109 }, 3110 { 3111 name: "SARLconst", 3112 auxType: auxInt32, 3113 argLen: 1, 3114 resultInArg0: true, 3115 clobberFlags: true, 3116 asm: x86.ASARL, 3117 reg: regInfo{ 3118 inputs: []inputInfo{ 3119 {0, 239}, // AX CX DX BX BP SI DI 3120 }, 3121 outputs: []outputInfo{ 3122 {0, 239}, // AX CX DX BX BP SI DI 3123 }, 3124 }, 3125 }, 3126 { 3127 name: "SARWconst", 3128 auxType: auxInt16, 3129 argLen: 1, 3130 resultInArg0: true, 3131 clobberFlags: true, 3132 asm: x86.ASARW, 3133 reg: regInfo{ 3134 inputs: []inputInfo{ 3135 {0, 239}, // AX CX DX BX BP SI DI 3136 }, 3137 outputs: []outputInfo{ 3138 {0, 239}, // AX CX DX BX BP SI DI 3139 }, 3140 }, 3141 }, 3142 { 3143 name: "SARBconst", 3144 auxType: auxInt8, 3145 argLen: 1, 3146 resultInArg0: true, 3147 clobberFlags: true, 3148 asm: x86.ASARB, 3149 reg: regInfo{ 3150 inputs: []inputInfo{ 3151 {0, 239}, // AX CX DX BX BP SI DI 3152 }, 3153 outputs: []outputInfo{ 3154 {0, 239}, // AX CX DX BX BP SI DI 3155 }, 3156 }, 3157 }, 3158 { 3159 name: "ROLLconst", 3160 auxType: auxInt32, 3161 argLen: 1, 3162 resultInArg0: true, 3163 clobberFlags: true, 3164 asm: x86.AROLL, 3165 reg: regInfo{ 3166 inputs: []inputInfo{ 3167 {0, 239}, // AX CX DX BX BP SI DI 3168 }, 3169 outputs: []outputInfo{ 3170 {0, 239}, // AX CX DX BX BP SI DI 3171 }, 3172 }, 3173 }, 3174 { 3175 name: "ROLWconst", 3176 auxType: auxInt16, 3177 argLen: 1, 3178 resultInArg0: true, 3179 clobberFlags: true, 3180 asm: x86.AROLW, 3181 reg: regInfo{ 3182 inputs: []inputInfo{ 3183 {0, 239}, // AX CX DX BX BP SI DI 3184 }, 3185 outputs: []outputInfo{ 3186 {0, 239}, // AX CX DX BX BP SI DI 3187 }, 3188 }, 3189 }, 3190 { 3191 name: "ROLBconst", 3192 auxType: auxInt8, 3193 argLen: 1, 3194 resultInArg0: true, 3195 clobberFlags: true, 3196 asm: x86.AROLB, 3197 reg: regInfo{ 3198 inputs: []inputInfo{ 3199 {0, 239}, // AX CX DX BX BP SI DI 3200 }, 3201 outputs: []outputInfo{ 3202 {0, 239}, // AX CX DX BX BP SI DI 3203 }, 3204 }, 3205 }, 3206 { 3207 name: "NEGL", 3208 argLen: 1, 3209 resultInArg0: true, 3210 clobberFlags: true, 3211 asm: x86.ANEGL, 3212 reg: regInfo{ 3213 inputs: []inputInfo{ 3214 {0, 239}, // AX CX DX BX BP SI DI 3215 }, 3216 outputs: []outputInfo{ 3217 {0, 239}, // AX CX DX BX BP SI DI 3218 }, 3219 }, 3220 }, 3221 { 3222 name: "NOTL", 3223 argLen: 1, 3224 resultInArg0: true, 3225 clobberFlags: true, 3226 asm: x86.ANOTL, 3227 reg: regInfo{ 3228 inputs: []inputInfo{ 3229 {0, 239}, // AX CX DX BX BP SI DI 3230 }, 3231 outputs: []outputInfo{ 3232 {0, 239}, // AX CX DX BX BP SI DI 3233 }, 3234 }, 3235 }, 3236 { 3237 name: "BSFL", 3238 argLen: 1, 3239 clobberFlags: true, 3240 asm: x86.ABSFL, 3241 reg: regInfo{ 3242 inputs: []inputInfo{ 3243 {0, 239}, // AX CX DX BX BP SI DI 3244 }, 3245 outputs: []outputInfo{ 3246 {0, 239}, // AX CX DX BX BP SI DI 3247 }, 3248 }, 3249 }, 3250 { 3251 name: "BSFW", 3252 argLen: 1, 3253 clobberFlags: true, 3254 asm: x86.ABSFW, 3255 reg: regInfo{ 3256 inputs: []inputInfo{ 3257 {0, 239}, // AX CX DX BX BP SI DI 3258 }, 3259 outputs: []outputInfo{ 3260 {0, 239}, // AX CX DX BX BP SI DI 3261 }, 3262 }, 3263 }, 3264 { 3265 name: "BSRL", 3266 argLen: 1, 3267 clobberFlags: true, 3268 asm: x86.ABSRL, 3269 reg: regInfo{ 3270 inputs: []inputInfo{ 3271 {0, 239}, // AX CX DX BX BP SI DI 3272 }, 3273 outputs: []outputInfo{ 3274 {0, 239}, // AX CX DX BX BP SI DI 3275 }, 3276 }, 3277 }, 3278 { 3279 name: "BSRW", 3280 argLen: 1, 3281 clobberFlags: true, 3282 asm: x86.ABSRW, 3283 reg: regInfo{ 3284 inputs: []inputInfo{ 3285 {0, 239}, // AX CX DX BX BP SI DI 3286 }, 3287 outputs: []outputInfo{ 3288 {0, 239}, // AX CX DX BX BP SI DI 3289 }, 3290 }, 3291 }, 3292 { 3293 name: "BSWAPL", 3294 argLen: 1, 3295 resultInArg0: true, 3296 clobberFlags: true, 3297 asm: x86.ABSWAPL, 3298 reg: regInfo{ 3299 inputs: []inputInfo{ 3300 {0, 239}, // AX CX DX BX BP SI DI 3301 }, 3302 outputs: []outputInfo{ 3303 {0, 239}, // AX CX DX BX BP SI DI 3304 }, 3305 }, 3306 }, 3307 { 3308 name: "SQRTSD", 3309 argLen: 1, 3310 asm: x86.ASQRTSD, 3311 reg: regInfo{ 3312 inputs: []inputInfo{ 3313 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3314 }, 3315 outputs: []outputInfo{ 3316 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3317 }, 3318 }, 3319 }, 3320 { 3321 name: "SBBLcarrymask", 3322 argLen: 1, 3323 asm: x86.ASBBL, 3324 reg: regInfo{ 3325 outputs: []outputInfo{ 3326 {0, 239}, // AX CX DX BX BP SI DI 3327 }, 3328 }, 3329 }, 3330 { 3331 name: "SETEQ", 3332 argLen: 1, 3333 asm: x86.ASETEQ, 3334 reg: regInfo{ 3335 outputs: []outputInfo{ 3336 {0, 239}, // AX CX DX BX BP SI DI 3337 }, 3338 }, 3339 }, 3340 { 3341 name: "SETNE", 3342 argLen: 1, 3343 asm: x86.ASETNE, 3344 reg: regInfo{ 3345 outputs: []outputInfo{ 3346 {0, 239}, // AX CX DX BX BP SI DI 3347 }, 3348 }, 3349 }, 3350 { 3351 name: "SETL", 3352 argLen: 1, 3353 asm: x86.ASETLT, 3354 reg: regInfo{ 3355 outputs: []outputInfo{ 3356 {0, 239}, // AX CX DX BX BP SI DI 3357 }, 3358 }, 3359 }, 3360 { 3361 name: "SETLE", 3362 argLen: 1, 3363 asm: x86.ASETLE, 3364 reg: regInfo{ 3365 outputs: []outputInfo{ 3366 {0, 239}, // AX CX DX BX BP SI DI 3367 }, 3368 }, 3369 }, 3370 { 3371 name: "SETG", 3372 argLen: 1, 3373 asm: x86.ASETGT, 3374 reg: regInfo{ 3375 outputs: []outputInfo{ 3376 {0, 239}, // AX CX DX BX BP SI DI 3377 }, 3378 }, 3379 }, 3380 { 3381 name: "SETGE", 3382 argLen: 1, 3383 asm: x86.ASETGE, 3384 reg: regInfo{ 3385 outputs: []outputInfo{ 3386 {0, 239}, // AX CX DX BX BP SI DI 3387 }, 3388 }, 3389 }, 3390 { 3391 name: "SETB", 3392 argLen: 1, 3393 asm: x86.ASETCS, 3394 reg: regInfo{ 3395 outputs: []outputInfo{ 3396 {0, 239}, // AX CX DX BX BP SI DI 3397 }, 3398 }, 3399 }, 3400 { 3401 name: "SETBE", 3402 argLen: 1, 3403 asm: x86.ASETLS, 3404 reg: regInfo{ 3405 outputs: []outputInfo{ 3406 {0, 239}, // AX CX DX BX BP SI DI 3407 }, 3408 }, 3409 }, 3410 { 3411 name: "SETA", 3412 argLen: 1, 3413 asm: x86.ASETHI, 3414 reg: regInfo{ 3415 outputs: []outputInfo{ 3416 {0, 239}, // AX CX DX BX BP SI DI 3417 }, 3418 }, 3419 }, 3420 { 3421 name: "SETAE", 3422 argLen: 1, 3423 asm: x86.ASETCC, 3424 reg: regInfo{ 3425 outputs: []outputInfo{ 3426 {0, 239}, // AX CX DX BX BP SI DI 3427 }, 3428 }, 3429 }, 3430 { 3431 name: "SETEQF", 3432 argLen: 1, 3433 clobberFlags: true, 3434 asm: x86.ASETEQ, 3435 reg: regInfo{ 3436 clobbers: 1, // AX 3437 outputs: []outputInfo{ 3438 {0, 238}, // CX DX BX BP SI DI 3439 }, 3440 }, 3441 }, 3442 { 3443 name: "SETNEF", 3444 argLen: 1, 3445 clobberFlags: true, 3446 asm: x86.ASETNE, 3447 reg: regInfo{ 3448 clobbers: 1, // AX 3449 outputs: []outputInfo{ 3450 {0, 238}, // CX DX BX BP SI DI 3451 }, 3452 }, 3453 }, 3454 { 3455 name: "SETORD", 3456 argLen: 1, 3457 asm: x86.ASETPC, 3458 reg: regInfo{ 3459 outputs: []outputInfo{ 3460 {0, 239}, // AX CX DX BX BP SI DI 3461 }, 3462 }, 3463 }, 3464 { 3465 name: "SETNAN", 3466 argLen: 1, 3467 asm: x86.ASETPS, 3468 reg: regInfo{ 3469 outputs: []outputInfo{ 3470 {0, 239}, // AX CX DX BX BP SI DI 3471 }, 3472 }, 3473 }, 3474 { 3475 name: "SETGF", 3476 argLen: 1, 3477 asm: x86.ASETHI, 3478 reg: regInfo{ 3479 outputs: []outputInfo{ 3480 {0, 239}, // AX CX DX BX BP SI DI 3481 }, 3482 }, 3483 }, 3484 { 3485 name: "SETGEF", 3486 argLen: 1, 3487 asm: x86.ASETCC, 3488 reg: regInfo{ 3489 outputs: []outputInfo{ 3490 {0, 239}, // AX CX DX BX BP SI DI 3491 }, 3492 }, 3493 }, 3494 { 3495 name: "MOVBLSX", 3496 argLen: 1, 3497 asm: x86.AMOVBLSX, 3498 reg: regInfo{ 3499 inputs: []inputInfo{ 3500 {0, 239}, // AX CX DX BX BP SI DI 3501 }, 3502 outputs: []outputInfo{ 3503 {0, 239}, // AX CX DX BX BP SI DI 3504 }, 3505 }, 3506 }, 3507 { 3508 name: "MOVBLZX", 3509 argLen: 1, 3510 asm: x86.AMOVBLZX, 3511 reg: regInfo{ 3512 inputs: []inputInfo{ 3513 {0, 239}, // AX CX DX BX BP SI DI 3514 }, 3515 outputs: []outputInfo{ 3516 {0, 239}, // AX CX DX BX BP SI DI 3517 }, 3518 }, 3519 }, 3520 { 3521 name: "MOVWLSX", 3522 argLen: 1, 3523 asm: x86.AMOVWLSX, 3524 reg: regInfo{ 3525 inputs: []inputInfo{ 3526 {0, 239}, // AX CX DX BX BP SI DI 3527 }, 3528 outputs: []outputInfo{ 3529 {0, 239}, // AX CX DX BX BP SI DI 3530 }, 3531 }, 3532 }, 3533 { 3534 name: "MOVWLZX", 3535 argLen: 1, 3536 asm: x86.AMOVWLZX, 3537 reg: regInfo{ 3538 inputs: []inputInfo{ 3539 {0, 239}, // AX CX DX BX BP SI DI 3540 }, 3541 outputs: []outputInfo{ 3542 {0, 239}, // AX CX DX BX BP SI DI 3543 }, 3544 }, 3545 }, 3546 { 3547 name: "MOVLconst", 3548 auxType: auxInt32, 3549 argLen: 0, 3550 rematerializeable: true, 3551 asm: x86.AMOVL, 3552 reg: regInfo{ 3553 outputs: []outputInfo{ 3554 {0, 239}, // AX CX DX BX BP SI DI 3555 }, 3556 }, 3557 }, 3558 { 3559 name: "CVTTSD2SL", 3560 argLen: 1, 3561 usesScratch: true, 3562 asm: x86.ACVTTSD2SL, 3563 reg: regInfo{ 3564 inputs: []inputInfo{ 3565 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3566 }, 3567 outputs: []outputInfo{ 3568 {0, 239}, // AX CX DX BX BP SI DI 3569 }, 3570 }, 3571 }, 3572 { 3573 name: "CVTTSS2SL", 3574 argLen: 1, 3575 usesScratch: true, 3576 asm: x86.ACVTTSS2SL, 3577 reg: regInfo{ 3578 inputs: []inputInfo{ 3579 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3580 }, 3581 outputs: []outputInfo{ 3582 {0, 239}, // AX CX DX BX BP SI DI 3583 }, 3584 }, 3585 }, 3586 { 3587 name: "CVTSL2SS", 3588 argLen: 1, 3589 usesScratch: true, 3590 asm: x86.ACVTSL2SS, 3591 reg: regInfo{ 3592 inputs: []inputInfo{ 3593 {0, 239}, // AX CX DX BX BP SI DI 3594 }, 3595 outputs: []outputInfo{ 3596 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3597 }, 3598 }, 3599 }, 3600 { 3601 name: "CVTSL2SD", 3602 argLen: 1, 3603 usesScratch: true, 3604 asm: x86.ACVTSL2SD, 3605 reg: regInfo{ 3606 inputs: []inputInfo{ 3607 {0, 239}, // AX CX DX BX BP SI DI 3608 }, 3609 outputs: []outputInfo{ 3610 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3611 }, 3612 }, 3613 }, 3614 { 3615 name: "CVTSD2SS", 3616 argLen: 1, 3617 usesScratch: true, 3618 asm: x86.ACVTSD2SS, 3619 reg: regInfo{ 3620 inputs: []inputInfo{ 3621 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3622 }, 3623 outputs: []outputInfo{ 3624 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3625 }, 3626 }, 3627 }, 3628 { 3629 name: "CVTSS2SD", 3630 argLen: 1, 3631 asm: x86.ACVTSS2SD, 3632 reg: regInfo{ 3633 inputs: []inputInfo{ 3634 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3635 }, 3636 outputs: []outputInfo{ 3637 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3638 }, 3639 }, 3640 }, 3641 { 3642 name: "PXOR", 3643 argLen: 2, 3644 commutative: true, 3645 resultInArg0: true, 3646 asm: x86.APXOR, 3647 reg: regInfo{ 3648 inputs: []inputInfo{ 3649 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3650 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3651 }, 3652 outputs: []outputInfo{ 3653 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3654 }, 3655 }, 3656 }, 3657 { 3658 name: "LEAL", 3659 auxType: auxSymOff, 3660 argLen: 1, 3661 rematerializeable: true, 3662 reg: regInfo{ 3663 inputs: []inputInfo{ 3664 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3665 }, 3666 outputs: []outputInfo{ 3667 {0, 239}, // AX CX DX BX BP SI DI 3668 }, 3669 }, 3670 }, 3671 { 3672 name: "LEAL1", 3673 auxType: auxSymOff, 3674 argLen: 2, 3675 reg: regInfo{ 3676 inputs: []inputInfo{ 3677 {1, 255}, // AX CX DX BX SP BP SI DI 3678 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3679 }, 3680 outputs: []outputInfo{ 3681 {0, 239}, // AX CX DX BX BP SI DI 3682 }, 3683 }, 3684 }, 3685 { 3686 name: "LEAL2", 3687 auxType: auxSymOff, 3688 argLen: 2, 3689 reg: regInfo{ 3690 inputs: []inputInfo{ 3691 {1, 255}, // AX CX DX BX SP BP SI DI 3692 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3693 }, 3694 outputs: []outputInfo{ 3695 {0, 239}, // AX CX DX BX BP SI DI 3696 }, 3697 }, 3698 }, 3699 { 3700 name: "LEAL4", 3701 auxType: auxSymOff, 3702 argLen: 2, 3703 reg: regInfo{ 3704 inputs: []inputInfo{ 3705 {1, 255}, // AX CX DX BX SP BP SI DI 3706 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3707 }, 3708 outputs: []outputInfo{ 3709 {0, 239}, // AX CX DX BX BP SI DI 3710 }, 3711 }, 3712 }, 3713 { 3714 name: "LEAL8", 3715 auxType: auxSymOff, 3716 argLen: 2, 3717 reg: regInfo{ 3718 inputs: []inputInfo{ 3719 {1, 255}, // AX CX DX BX SP BP SI DI 3720 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3721 }, 3722 outputs: []outputInfo{ 3723 {0, 239}, // AX CX DX BX BP SI DI 3724 }, 3725 }, 3726 }, 3727 { 3728 name: "MOVBload", 3729 auxType: auxSymOff, 3730 argLen: 2, 3731 faultOnNilArg0: true, 3732 asm: x86.AMOVBLZX, 3733 reg: regInfo{ 3734 inputs: []inputInfo{ 3735 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3736 }, 3737 outputs: []outputInfo{ 3738 {0, 239}, // AX CX DX BX BP SI DI 3739 }, 3740 }, 3741 }, 3742 { 3743 name: "MOVBLSXload", 3744 auxType: auxSymOff, 3745 argLen: 2, 3746 faultOnNilArg0: true, 3747 asm: x86.AMOVBLSX, 3748 reg: regInfo{ 3749 inputs: []inputInfo{ 3750 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3751 }, 3752 outputs: []outputInfo{ 3753 {0, 239}, // AX CX DX BX BP SI DI 3754 }, 3755 }, 3756 }, 3757 { 3758 name: "MOVWload", 3759 auxType: auxSymOff, 3760 argLen: 2, 3761 faultOnNilArg0: true, 3762 asm: x86.AMOVWLZX, 3763 reg: regInfo{ 3764 inputs: []inputInfo{ 3765 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3766 }, 3767 outputs: []outputInfo{ 3768 {0, 239}, // AX CX DX BX BP SI DI 3769 }, 3770 }, 3771 }, 3772 { 3773 name: "MOVWLSXload", 3774 auxType: auxSymOff, 3775 argLen: 2, 3776 faultOnNilArg0: true, 3777 asm: x86.AMOVWLSX, 3778 reg: regInfo{ 3779 inputs: []inputInfo{ 3780 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3781 }, 3782 outputs: []outputInfo{ 3783 {0, 239}, // AX CX DX BX BP SI DI 3784 }, 3785 }, 3786 }, 3787 { 3788 name: "MOVLload", 3789 auxType: auxSymOff, 3790 argLen: 2, 3791 faultOnNilArg0: true, 3792 asm: x86.AMOVL, 3793 reg: regInfo{ 3794 inputs: []inputInfo{ 3795 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3796 }, 3797 outputs: []outputInfo{ 3798 {0, 239}, // AX CX DX BX BP SI DI 3799 }, 3800 }, 3801 }, 3802 { 3803 name: "MOVBstore", 3804 auxType: auxSymOff, 3805 argLen: 3, 3806 faultOnNilArg0: true, 3807 asm: x86.AMOVB, 3808 reg: regInfo{ 3809 inputs: []inputInfo{ 3810 {1, 255}, // AX CX DX BX SP BP SI DI 3811 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3812 }, 3813 }, 3814 }, 3815 { 3816 name: "MOVWstore", 3817 auxType: auxSymOff, 3818 argLen: 3, 3819 faultOnNilArg0: true, 3820 asm: x86.AMOVW, 3821 reg: regInfo{ 3822 inputs: []inputInfo{ 3823 {1, 255}, // AX CX DX BX SP BP SI DI 3824 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3825 }, 3826 }, 3827 }, 3828 { 3829 name: "MOVLstore", 3830 auxType: auxSymOff, 3831 argLen: 3, 3832 faultOnNilArg0: true, 3833 asm: x86.AMOVL, 3834 reg: regInfo{ 3835 inputs: []inputInfo{ 3836 {1, 255}, // AX CX DX BX SP BP SI DI 3837 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3838 }, 3839 }, 3840 }, 3841 { 3842 name: "MOVBloadidx1", 3843 auxType: auxSymOff, 3844 argLen: 3, 3845 asm: x86.AMOVBLZX, 3846 reg: regInfo{ 3847 inputs: []inputInfo{ 3848 {1, 255}, // AX CX DX BX SP BP SI DI 3849 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3850 }, 3851 outputs: []outputInfo{ 3852 {0, 239}, // AX CX DX BX BP SI DI 3853 }, 3854 }, 3855 }, 3856 { 3857 name: "MOVWloadidx1", 3858 auxType: auxSymOff, 3859 argLen: 3, 3860 asm: x86.AMOVWLZX, 3861 reg: regInfo{ 3862 inputs: []inputInfo{ 3863 {1, 255}, // AX CX DX BX SP BP SI DI 3864 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3865 }, 3866 outputs: []outputInfo{ 3867 {0, 239}, // AX CX DX BX BP SI DI 3868 }, 3869 }, 3870 }, 3871 { 3872 name: "MOVWloadidx2", 3873 auxType: auxSymOff, 3874 argLen: 3, 3875 asm: x86.AMOVWLZX, 3876 reg: regInfo{ 3877 inputs: []inputInfo{ 3878 {1, 255}, // AX CX DX BX SP BP SI DI 3879 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3880 }, 3881 outputs: []outputInfo{ 3882 {0, 239}, // AX CX DX BX BP SI DI 3883 }, 3884 }, 3885 }, 3886 { 3887 name: "MOVLloadidx1", 3888 auxType: auxSymOff, 3889 argLen: 3, 3890 asm: x86.AMOVL, 3891 reg: regInfo{ 3892 inputs: []inputInfo{ 3893 {1, 255}, // AX CX DX BX SP BP SI DI 3894 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3895 }, 3896 outputs: []outputInfo{ 3897 {0, 239}, // AX CX DX BX BP SI DI 3898 }, 3899 }, 3900 }, 3901 { 3902 name: "MOVLloadidx4", 3903 auxType: auxSymOff, 3904 argLen: 3, 3905 asm: x86.AMOVL, 3906 reg: regInfo{ 3907 inputs: []inputInfo{ 3908 {1, 255}, // AX CX DX BX SP BP SI DI 3909 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3910 }, 3911 outputs: []outputInfo{ 3912 {0, 239}, // AX CX DX BX BP SI DI 3913 }, 3914 }, 3915 }, 3916 { 3917 name: "MOVBstoreidx1", 3918 auxType: auxSymOff, 3919 argLen: 4, 3920 asm: x86.AMOVB, 3921 reg: regInfo{ 3922 inputs: []inputInfo{ 3923 {1, 255}, // AX CX DX BX SP BP SI DI 3924 {2, 255}, // AX CX DX BX SP BP SI DI 3925 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3926 }, 3927 }, 3928 }, 3929 { 3930 name: "MOVWstoreidx1", 3931 auxType: auxSymOff, 3932 argLen: 4, 3933 asm: x86.AMOVW, 3934 reg: regInfo{ 3935 inputs: []inputInfo{ 3936 {1, 255}, // AX CX DX BX SP BP SI DI 3937 {2, 255}, // AX CX DX BX SP BP SI DI 3938 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3939 }, 3940 }, 3941 }, 3942 { 3943 name: "MOVWstoreidx2", 3944 auxType: auxSymOff, 3945 argLen: 4, 3946 asm: x86.AMOVW, 3947 reg: regInfo{ 3948 inputs: []inputInfo{ 3949 {1, 255}, // AX CX DX BX SP BP SI DI 3950 {2, 255}, // AX CX DX BX SP BP SI DI 3951 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3952 }, 3953 }, 3954 }, 3955 { 3956 name: "MOVLstoreidx1", 3957 auxType: auxSymOff, 3958 argLen: 4, 3959 asm: x86.AMOVL, 3960 reg: regInfo{ 3961 inputs: []inputInfo{ 3962 {1, 255}, // AX CX DX BX SP BP SI DI 3963 {2, 255}, // AX CX DX BX SP BP SI DI 3964 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3965 }, 3966 }, 3967 }, 3968 { 3969 name: "MOVLstoreidx4", 3970 auxType: auxSymOff, 3971 argLen: 4, 3972 asm: x86.AMOVL, 3973 reg: regInfo{ 3974 inputs: []inputInfo{ 3975 {1, 255}, // AX CX DX BX SP BP SI DI 3976 {2, 255}, // AX CX DX BX SP BP SI DI 3977 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3978 }, 3979 }, 3980 }, 3981 { 3982 name: "MOVBstoreconst", 3983 auxType: auxSymValAndOff, 3984 argLen: 2, 3985 faultOnNilArg0: true, 3986 asm: x86.AMOVB, 3987 reg: regInfo{ 3988 inputs: []inputInfo{ 3989 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3990 }, 3991 }, 3992 }, 3993 { 3994 name: "MOVWstoreconst", 3995 auxType: auxSymValAndOff, 3996 argLen: 2, 3997 faultOnNilArg0: true, 3998 asm: x86.AMOVW, 3999 reg: regInfo{ 4000 inputs: []inputInfo{ 4001 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4002 }, 4003 }, 4004 }, 4005 { 4006 name: "MOVLstoreconst", 4007 auxType: auxSymValAndOff, 4008 argLen: 2, 4009 faultOnNilArg0: true, 4010 asm: x86.AMOVL, 4011 reg: regInfo{ 4012 inputs: []inputInfo{ 4013 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4014 }, 4015 }, 4016 }, 4017 { 4018 name: "MOVBstoreconstidx1", 4019 auxType: auxSymValAndOff, 4020 argLen: 3, 4021 asm: x86.AMOVB, 4022 reg: regInfo{ 4023 inputs: []inputInfo{ 4024 {1, 255}, // AX CX DX BX SP BP SI DI 4025 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4026 }, 4027 }, 4028 }, 4029 { 4030 name: "MOVWstoreconstidx1", 4031 auxType: auxSymValAndOff, 4032 argLen: 3, 4033 asm: x86.AMOVW, 4034 reg: regInfo{ 4035 inputs: []inputInfo{ 4036 {1, 255}, // AX CX DX BX SP BP SI DI 4037 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4038 }, 4039 }, 4040 }, 4041 { 4042 name: "MOVWstoreconstidx2", 4043 auxType: auxSymValAndOff, 4044 argLen: 3, 4045 asm: x86.AMOVW, 4046 reg: regInfo{ 4047 inputs: []inputInfo{ 4048 {1, 255}, // AX CX DX BX SP BP SI DI 4049 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4050 }, 4051 }, 4052 }, 4053 { 4054 name: "MOVLstoreconstidx1", 4055 auxType: auxSymValAndOff, 4056 argLen: 3, 4057 asm: x86.AMOVL, 4058 reg: regInfo{ 4059 inputs: []inputInfo{ 4060 {1, 255}, // AX CX DX BX SP BP SI DI 4061 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4062 }, 4063 }, 4064 }, 4065 { 4066 name: "MOVLstoreconstidx4", 4067 auxType: auxSymValAndOff, 4068 argLen: 3, 4069 asm: x86.AMOVL, 4070 reg: regInfo{ 4071 inputs: []inputInfo{ 4072 {1, 255}, // AX CX DX BX SP BP SI DI 4073 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4074 }, 4075 }, 4076 }, 4077 { 4078 name: "DUFFZERO", 4079 auxType: auxInt64, 4080 argLen: 3, 4081 reg: regInfo{ 4082 inputs: []inputInfo{ 4083 {0, 128}, // DI 4084 {1, 1}, // AX 4085 }, 4086 clobbers: 130, // CX DI 4087 }, 4088 }, 4089 { 4090 name: "REPSTOSL", 4091 argLen: 4, 4092 reg: regInfo{ 4093 inputs: []inputInfo{ 4094 {0, 128}, // DI 4095 {1, 2}, // CX 4096 {2, 1}, // AX 4097 }, 4098 clobbers: 130, // CX DI 4099 }, 4100 }, 4101 { 4102 name: "CALLstatic", 4103 auxType: auxSymOff, 4104 argLen: 1, 4105 clobberFlags: true, 4106 call: true, 4107 reg: regInfo{ 4108 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4109 }, 4110 }, 4111 { 4112 name: "CALLclosure", 4113 auxType: auxInt64, 4114 argLen: 3, 4115 clobberFlags: true, 4116 call: true, 4117 reg: regInfo{ 4118 inputs: []inputInfo{ 4119 {1, 4}, // DX 4120 {0, 255}, // AX CX DX BX SP BP SI DI 4121 }, 4122 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4123 }, 4124 }, 4125 { 4126 name: "CALLdefer", 4127 auxType: auxInt64, 4128 argLen: 1, 4129 clobberFlags: true, 4130 call: true, 4131 reg: regInfo{ 4132 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4133 }, 4134 }, 4135 { 4136 name: "CALLgo", 4137 auxType: auxInt64, 4138 argLen: 1, 4139 clobberFlags: true, 4140 call: true, 4141 reg: regInfo{ 4142 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4143 }, 4144 }, 4145 { 4146 name: "CALLinter", 4147 auxType: auxInt64, 4148 argLen: 2, 4149 clobberFlags: true, 4150 call: true, 4151 reg: regInfo{ 4152 inputs: []inputInfo{ 4153 {0, 239}, // AX CX DX BX BP SI DI 4154 }, 4155 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4156 }, 4157 }, 4158 { 4159 name: "DUFFCOPY", 4160 auxType: auxInt64, 4161 argLen: 3, 4162 clobberFlags: true, 4163 reg: regInfo{ 4164 inputs: []inputInfo{ 4165 {0, 128}, // DI 4166 {1, 64}, // SI 4167 }, 4168 clobbers: 194, // CX SI DI 4169 }, 4170 }, 4171 { 4172 name: "REPMOVSL", 4173 argLen: 4, 4174 reg: regInfo{ 4175 inputs: []inputInfo{ 4176 {0, 128}, // DI 4177 {1, 64}, // SI 4178 {2, 2}, // CX 4179 }, 4180 clobbers: 194, // CX SI DI 4181 }, 4182 }, 4183 { 4184 name: "InvertFlags", 4185 argLen: 1, 4186 reg: regInfo{}, 4187 }, 4188 { 4189 name: "LoweredGetG", 4190 argLen: 1, 4191 reg: regInfo{ 4192 outputs: []outputInfo{ 4193 {0, 239}, // AX CX DX BX BP SI DI 4194 }, 4195 }, 4196 }, 4197 { 4198 name: "LoweredGetClosurePtr", 4199 argLen: 0, 4200 reg: regInfo{ 4201 outputs: []outputInfo{ 4202 {0, 4}, // DX 4203 }, 4204 }, 4205 }, 4206 { 4207 name: "LoweredNilCheck", 4208 argLen: 2, 4209 clobberFlags: true, 4210 nilCheck: true, 4211 faultOnNilArg0: true, 4212 reg: regInfo{ 4213 inputs: []inputInfo{ 4214 {0, 255}, // AX CX DX BX SP BP SI DI 4215 }, 4216 }, 4217 }, 4218 { 4219 name: "MOVLconvert", 4220 argLen: 2, 4221 asm: x86.AMOVL, 4222 reg: regInfo{ 4223 inputs: []inputInfo{ 4224 {0, 239}, // AX CX DX BX BP SI DI 4225 }, 4226 outputs: []outputInfo{ 4227 {0, 239}, // AX CX DX BX BP SI DI 4228 }, 4229 }, 4230 }, 4231 { 4232 name: "FlagEQ", 4233 argLen: 0, 4234 reg: regInfo{}, 4235 }, 4236 { 4237 name: "FlagLT_ULT", 4238 argLen: 0, 4239 reg: regInfo{}, 4240 }, 4241 { 4242 name: "FlagLT_UGT", 4243 argLen: 0, 4244 reg: regInfo{}, 4245 }, 4246 { 4247 name: "FlagGT_UGT", 4248 argLen: 0, 4249 reg: regInfo{}, 4250 }, 4251 { 4252 name: "FlagGT_ULT", 4253 argLen: 0, 4254 reg: regInfo{}, 4255 }, 4256 { 4257 name: "FCHS", 4258 argLen: 1, 4259 reg: regInfo{ 4260 inputs: []inputInfo{ 4261 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4262 }, 4263 outputs: []outputInfo{ 4264 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4265 }, 4266 }, 4267 }, 4268 { 4269 name: "MOVSSconst1", 4270 auxType: auxFloat32, 4271 argLen: 0, 4272 reg: regInfo{ 4273 outputs: []outputInfo{ 4274 {0, 239}, // AX CX DX BX BP SI DI 4275 }, 4276 }, 4277 }, 4278 { 4279 name: "MOVSDconst1", 4280 auxType: auxFloat64, 4281 argLen: 0, 4282 reg: regInfo{ 4283 outputs: []outputInfo{ 4284 {0, 239}, // AX CX DX BX BP SI DI 4285 }, 4286 }, 4287 }, 4288 { 4289 name: "MOVSSconst2", 4290 argLen: 1, 4291 asm: x86.AMOVSS, 4292 reg: regInfo{ 4293 inputs: []inputInfo{ 4294 {0, 239}, // AX CX DX BX BP SI DI 4295 }, 4296 outputs: []outputInfo{ 4297 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4298 }, 4299 }, 4300 }, 4301 { 4302 name: "MOVSDconst2", 4303 argLen: 1, 4304 asm: x86.AMOVSD, 4305 reg: regInfo{ 4306 inputs: []inputInfo{ 4307 {0, 239}, // AX CX DX BX BP SI DI 4308 }, 4309 outputs: []outputInfo{ 4310 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4311 }, 4312 }, 4313 }, 4314 4315 { 4316 name: "ADDSS", 4317 argLen: 2, 4318 commutative: true, 4319 resultInArg0: true, 4320 asm: x86.AADDSS, 4321 reg: regInfo{ 4322 inputs: []inputInfo{ 4323 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4324 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4325 }, 4326 outputs: []outputInfo{ 4327 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4328 }, 4329 }, 4330 }, 4331 { 4332 name: "ADDSD", 4333 argLen: 2, 4334 commutative: true, 4335 resultInArg0: true, 4336 asm: x86.AADDSD, 4337 reg: regInfo{ 4338 inputs: []inputInfo{ 4339 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4340 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4341 }, 4342 outputs: []outputInfo{ 4343 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4344 }, 4345 }, 4346 }, 4347 { 4348 name: "SUBSS", 4349 argLen: 2, 4350 resultInArg0: true, 4351 asm: x86.ASUBSS, 4352 reg: regInfo{ 4353 inputs: []inputInfo{ 4354 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4355 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4356 }, 4357 outputs: []outputInfo{ 4358 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4359 }, 4360 }, 4361 }, 4362 { 4363 name: "SUBSD", 4364 argLen: 2, 4365 resultInArg0: true, 4366 asm: x86.ASUBSD, 4367 reg: regInfo{ 4368 inputs: []inputInfo{ 4369 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4370 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4371 }, 4372 outputs: []outputInfo{ 4373 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4374 }, 4375 }, 4376 }, 4377 { 4378 name: "MULSS", 4379 argLen: 2, 4380 commutative: true, 4381 resultInArg0: true, 4382 asm: x86.AMULSS, 4383 reg: regInfo{ 4384 inputs: []inputInfo{ 4385 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4386 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4387 }, 4388 outputs: []outputInfo{ 4389 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4390 }, 4391 }, 4392 }, 4393 { 4394 name: "MULSD", 4395 argLen: 2, 4396 commutative: true, 4397 resultInArg0: true, 4398 asm: x86.AMULSD, 4399 reg: regInfo{ 4400 inputs: []inputInfo{ 4401 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4402 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4403 }, 4404 outputs: []outputInfo{ 4405 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4406 }, 4407 }, 4408 }, 4409 { 4410 name: "DIVSS", 4411 argLen: 2, 4412 resultInArg0: true, 4413 asm: x86.ADIVSS, 4414 reg: regInfo{ 4415 inputs: []inputInfo{ 4416 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4417 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4418 }, 4419 outputs: []outputInfo{ 4420 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4421 }, 4422 }, 4423 }, 4424 { 4425 name: "DIVSD", 4426 argLen: 2, 4427 resultInArg0: true, 4428 asm: x86.ADIVSD, 4429 reg: regInfo{ 4430 inputs: []inputInfo{ 4431 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4432 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4433 }, 4434 outputs: []outputInfo{ 4435 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4436 }, 4437 }, 4438 }, 4439 { 4440 name: "MOVSSload", 4441 auxType: auxSymOff, 4442 argLen: 2, 4443 faultOnNilArg0: true, 4444 asm: x86.AMOVSS, 4445 reg: regInfo{ 4446 inputs: []inputInfo{ 4447 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4448 }, 4449 outputs: []outputInfo{ 4450 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4451 }, 4452 }, 4453 }, 4454 { 4455 name: "MOVSDload", 4456 auxType: auxSymOff, 4457 argLen: 2, 4458 faultOnNilArg0: true, 4459 asm: x86.AMOVSD, 4460 reg: regInfo{ 4461 inputs: []inputInfo{ 4462 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4463 }, 4464 outputs: []outputInfo{ 4465 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4466 }, 4467 }, 4468 }, 4469 { 4470 name: "MOVSSconst", 4471 auxType: auxFloat32, 4472 argLen: 0, 4473 rematerializeable: true, 4474 asm: x86.AMOVSS, 4475 reg: regInfo{ 4476 outputs: []outputInfo{ 4477 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4478 }, 4479 }, 4480 }, 4481 { 4482 name: "MOVSDconst", 4483 auxType: auxFloat64, 4484 argLen: 0, 4485 rematerializeable: true, 4486 asm: x86.AMOVSD, 4487 reg: regInfo{ 4488 outputs: []outputInfo{ 4489 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4490 }, 4491 }, 4492 }, 4493 { 4494 name: "MOVSSloadidx1", 4495 auxType: auxSymOff, 4496 argLen: 3, 4497 asm: x86.AMOVSS, 4498 reg: regInfo{ 4499 inputs: []inputInfo{ 4500 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4501 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4502 }, 4503 outputs: []outputInfo{ 4504 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4505 }, 4506 }, 4507 }, 4508 { 4509 name: "MOVSSloadidx4", 4510 auxType: auxSymOff, 4511 argLen: 3, 4512 asm: x86.AMOVSS, 4513 reg: regInfo{ 4514 inputs: []inputInfo{ 4515 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4516 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4517 }, 4518 outputs: []outputInfo{ 4519 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4520 }, 4521 }, 4522 }, 4523 { 4524 name: "MOVSDloadidx1", 4525 auxType: auxSymOff, 4526 argLen: 3, 4527 asm: x86.AMOVSD, 4528 reg: regInfo{ 4529 inputs: []inputInfo{ 4530 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4531 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4532 }, 4533 outputs: []outputInfo{ 4534 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4535 }, 4536 }, 4537 }, 4538 { 4539 name: "MOVSDloadidx8", 4540 auxType: auxSymOff, 4541 argLen: 3, 4542 asm: x86.AMOVSD, 4543 reg: regInfo{ 4544 inputs: []inputInfo{ 4545 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4546 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4547 }, 4548 outputs: []outputInfo{ 4549 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4550 }, 4551 }, 4552 }, 4553 { 4554 name: "MOVSSstore", 4555 auxType: auxSymOff, 4556 argLen: 3, 4557 faultOnNilArg0: true, 4558 asm: x86.AMOVSS, 4559 reg: regInfo{ 4560 inputs: []inputInfo{ 4561 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4563 }, 4564 }, 4565 }, 4566 { 4567 name: "MOVSDstore", 4568 auxType: auxSymOff, 4569 argLen: 3, 4570 faultOnNilArg0: true, 4571 asm: x86.AMOVSD, 4572 reg: regInfo{ 4573 inputs: []inputInfo{ 4574 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4575 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4576 }, 4577 }, 4578 }, 4579 { 4580 name: "MOVSSstoreidx1", 4581 auxType: auxSymOff, 4582 argLen: 4, 4583 asm: x86.AMOVSS, 4584 reg: regInfo{ 4585 inputs: []inputInfo{ 4586 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4587 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4588 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4589 }, 4590 }, 4591 }, 4592 { 4593 name: "MOVSSstoreidx4", 4594 auxType: auxSymOff, 4595 argLen: 4, 4596 asm: x86.AMOVSS, 4597 reg: regInfo{ 4598 inputs: []inputInfo{ 4599 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4600 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4601 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4602 }, 4603 }, 4604 }, 4605 { 4606 name: "MOVSDstoreidx1", 4607 auxType: auxSymOff, 4608 argLen: 4, 4609 asm: x86.AMOVSD, 4610 reg: regInfo{ 4611 inputs: []inputInfo{ 4612 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4613 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4614 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4615 }, 4616 }, 4617 }, 4618 { 4619 name: "MOVSDstoreidx8", 4620 auxType: auxSymOff, 4621 argLen: 4, 4622 asm: x86.AMOVSD, 4623 reg: regInfo{ 4624 inputs: []inputInfo{ 4625 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4626 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4627 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4628 }, 4629 }, 4630 }, 4631 { 4632 name: "ADDQ", 4633 argLen: 2, 4634 commutative: true, 4635 clobberFlags: true, 4636 asm: x86.AADDQ, 4637 reg: regInfo{ 4638 inputs: []inputInfo{ 4639 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4640 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4641 }, 4642 outputs: []outputInfo{ 4643 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4644 }, 4645 }, 4646 }, 4647 { 4648 name: "ADDL", 4649 argLen: 2, 4650 commutative: true, 4651 clobberFlags: true, 4652 asm: x86.AADDL, 4653 reg: regInfo{ 4654 inputs: []inputInfo{ 4655 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4656 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4657 }, 4658 outputs: []outputInfo{ 4659 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4660 }, 4661 }, 4662 }, 4663 { 4664 name: "ADDQconst", 4665 auxType: auxInt64, 4666 argLen: 1, 4667 clobberFlags: true, 4668 asm: x86.AADDQ, 4669 reg: regInfo{ 4670 inputs: []inputInfo{ 4671 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4672 }, 4673 outputs: []outputInfo{ 4674 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4675 }, 4676 }, 4677 }, 4678 { 4679 name: "ADDLconst", 4680 auxType: auxInt32, 4681 argLen: 1, 4682 clobberFlags: true, 4683 asm: x86.AADDL, 4684 reg: regInfo{ 4685 inputs: []inputInfo{ 4686 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4687 }, 4688 outputs: []outputInfo{ 4689 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4690 }, 4691 }, 4692 }, 4693 { 4694 name: "SUBQ", 4695 argLen: 2, 4696 resultInArg0: true, 4697 clobberFlags: true, 4698 asm: x86.ASUBQ, 4699 reg: regInfo{ 4700 inputs: []inputInfo{ 4701 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4702 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4703 }, 4704 outputs: []outputInfo{ 4705 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4706 }, 4707 }, 4708 }, 4709 { 4710 name: "SUBL", 4711 argLen: 2, 4712 resultInArg0: true, 4713 clobberFlags: true, 4714 asm: x86.ASUBL, 4715 reg: regInfo{ 4716 inputs: []inputInfo{ 4717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4718 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4719 }, 4720 outputs: []outputInfo{ 4721 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4722 }, 4723 }, 4724 }, 4725 { 4726 name: "SUBQconst", 4727 auxType: auxInt64, 4728 argLen: 1, 4729 resultInArg0: true, 4730 clobberFlags: true, 4731 asm: x86.ASUBQ, 4732 reg: regInfo{ 4733 inputs: []inputInfo{ 4734 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4735 }, 4736 outputs: []outputInfo{ 4737 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4738 }, 4739 }, 4740 }, 4741 { 4742 name: "SUBLconst", 4743 auxType: auxInt32, 4744 argLen: 1, 4745 resultInArg0: true, 4746 clobberFlags: true, 4747 asm: x86.ASUBL, 4748 reg: regInfo{ 4749 inputs: []inputInfo{ 4750 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4751 }, 4752 outputs: []outputInfo{ 4753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4754 }, 4755 }, 4756 }, 4757 { 4758 name: "MULQ", 4759 argLen: 2, 4760 commutative: true, 4761 resultInArg0: true, 4762 clobberFlags: true, 4763 asm: x86.AIMULQ, 4764 reg: regInfo{ 4765 inputs: []inputInfo{ 4766 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4767 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4768 }, 4769 outputs: []outputInfo{ 4770 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4771 }, 4772 }, 4773 }, 4774 { 4775 name: "MULL", 4776 argLen: 2, 4777 commutative: true, 4778 resultInArg0: true, 4779 clobberFlags: true, 4780 asm: x86.AIMULL, 4781 reg: regInfo{ 4782 inputs: []inputInfo{ 4783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4784 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4785 }, 4786 outputs: []outputInfo{ 4787 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4788 }, 4789 }, 4790 }, 4791 { 4792 name: "MULQconst", 4793 auxType: auxInt64, 4794 argLen: 1, 4795 resultInArg0: true, 4796 clobberFlags: true, 4797 asm: x86.AIMULQ, 4798 reg: regInfo{ 4799 inputs: []inputInfo{ 4800 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4801 }, 4802 outputs: []outputInfo{ 4803 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4804 }, 4805 }, 4806 }, 4807 { 4808 name: "MULLconst", 4809 auxType: auxInt32, 4810 argLen: 1, 4811 resultInArg0: true, 4812 clobberFlags: true, 4813 asm: x86.AIMULL, 4814 reg: regInfo{ 4815 inputs: []inputInfo{ 4816 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4817 }, 4818 outputs: []outputInfo{ 4819 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4820 }, 4821 }, 4822 }, 4823 { 4824 name: "HMULQ", 4825 argLen: 2, 4826 clobberFlags: true, 4827 asm: x86.AIMULQ, 4828 reg: regInfo{ 4829 inputs: []inputInfo{ 4830 {0, 1}, // AX 4831 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4832 }, 4833 clobbers: 1, // AX 4834 outputs: []outputInfo{ 4835 {0, 4}, // DX 4836 }, 4837 }, 4838 }, 4839 { 4840 name: "HMULL", 4841 argLen: 2, 4842 clobberFlags: true, 4843 asm: x86.AIMULL, 4844 reg: regInfo{ 4845 inputs: []inputInfo{ 4846 {0, 1}, // AX 4847 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4848 }, 4849 clobbers: 1, // AX 4850 outputs: []outputInfo{ 4851 {0, 4}, // DX 4852 }, 4853 }, 4854 }, 4855 { 4856 name: "HMULW", 4857 argLen: 2, 4858 clobberFlags: true, 4859 asm: x86.AIMULW, 4860 reg: regInfo{ 4861 inputs: []inputInfo{ 4862 {0, 1}, // AX 4863 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4864 }, 4865 clobbers: 1, // AX 4866 outputs: []outputInfo{ 4867 {0, 4}, // DX 4868 }, 4869 }, 4870 }, 4871 { 4872 name: "HMULB", 4873 argLen: 2, 4874 clobberFlags: true, 4875 asm: x86.AIMULB, 4876 reg: regInfo{ 4877 inputs: []inputInfo{ 4878 {0, 1}, // AX 4879 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4880 }, 4881 clobbers: 1, // AX 4882 outputs: []outputInfo{ 4883 {0, 4}, // DX 4884 }, 4885 }, 4886 }, 4887 { 4888 name: "HMULQU", 4889 argLen: 2, 4890 clobberFlags: true, 4891 asm: x86.AMULQ, 4892 reg: regInfo{ 4893 inputs: []inputInfo{ 4894 {0, 1}, // AX 4895 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4896 }, 4897 clobbers: 1, // AX 4898 outputs: []outputInfo{ 4899 {0, 4}, // DX 4900 }, 4901 }, 4902 }, 4903 { 4904 name: "HMULLU", 4905 argLen: 2, 4906 clobberFlags: true, 4907 asm: x86.AMULL, 4908 reg: regInfo{ 4909 inputs: []inputInfo{ 4910 {0, 1}, // AX 4911 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4912 }, 4913 clobbers: 1, // AX 4914 outputs: []outputInfo{ 4915 {0, 4}, // DX 4916 }, 4917 }, 4918 }, 4919 { 4920 name: "HMULWU", 4921 argLen: 2, 4922 clobberFlags: true, 4923 asm: x86.AMULW, 4924 reg: regInfo{ 4925 inputs: []inputInfo{ 4926 {0, 1}, // AX 4927 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4928 }, 4929 clobbers: 1, // AX 4930 outputs: []outputInfo{ 4931 {0, 4}, // DX 4932 }, 4933 }, 4934 }, 4935 { 4936 name: "HMULBU", 4937 argLen: 2, 4938 clobberFlags: true, 4939 asm: x86.AMULB, 4940 reg: regInfo{ 4941 inputs: []inputInfo{ 4942 {0, 1}, // AX 4943 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4944 }, 4945 clobbers: 1, // AX 4946 outputs: []outputInfo{ 4947 {0, 4}, // DX 4948 }, 4949 }, 4950 }, 4951 { 4952 name: "AVGQU", 4953 argLen: 2, 4954 commutative: true, 4955 resultInArg0: true, 4956 clobberFlags: true, 4957 reg: regInfo{ 4958 inputs: []inputInfo{ 4959 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4960 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4961 }, 4962 outputs: []outputInfo{ 4963 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4964 }, 4965 }, 4966 }, 4967 { 4968 name: "DIVQ", 4969 argLen: 2, 4970 clobberFlags: true, 4971 asm: x86.AIDIVQ, 4972 reg: regInfo{ 4973 inputs: []inputInfo{ 4974 {0, 1}, // AX 4975 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4976 }, 4977 outputs: []outputInfo{ 4978 {0, 1}, // AX 4979 {1, 4}, // DX 4980 }, 4981 }, 4982 }, 4983 { 4984 name: "DIVL", 4985 argLen: 2, 4986 clobberFlags: true, 4987 asm: x86.AIDIVL, 4988 reg: regInfo{ 4989 inputs: []inputInfo{ 4990 {0, 1}, // AX 4991 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4992 }, 4993 outputs: []outputInfo{ 4994 {0, 1}, // AX 4995 {1, 4}, // DX 4996 }, 4997 }, 4998 }, 4999 { 5000 name: "DIVW", 5001 argLen: 2, 5002 clobberFlags: true, 5003 asm: x86.AIDIVW, 5004 reg: regInfo{ 5005 inputs: []inputInfo{ 5006 {0, 1}, // AX 5007 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5008 }, 5009 outputs: []outputInfo{ 5010 {0, 1}, // AX 5011 {1, 4}, // DX 5012 }, 5013 }, 5014 }, 5015 { 5016 name: "DIVQU", 5017 argLen: 2, 5018 clobberFlags: true, 5019 asm: x86.ADIVQ, 5020 reg: regInfo{ 5021 inputs: []inputInfo{ 5022 {0, 1}, // AX 5023 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5024 }, 5025 outputs: []outputInfo{ 5026 {0, 1}, // AX 5027 {1, 4}, // DX 5028 }, 5029 }, 5030 }, 5031 { 5032 name: "DIVLU", 5033 argLen: 2, 5034 clobberFlags: true, 5035 asm: x86.ADIVL, 5036 reg: regInfo{ 5037 inputs: []inputInfo{ 5038 {0, 1}, // AX 5039 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5040 }, 5041 outputs: []outputInfo{ 5042 {0, 1}, // AX 5043 {1, 4}, // DX 5044 }, 5045 }, 5046 }, 5047 { 5048 name: "DIVWU", 5049 argLen: 2, 5050 clobberFlags: true, 5051 asm: x86.ADIVW, 5052 reg: regInfo{ 5053 inputs: []inputInfo{ 5054 {0, 1}, // AX 5055 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5056 }, 5057 outputs: []outputInfo{ 5058 {0, 1}, // AX 5059 {1, 4}, // DX 5060 }, 5061 }, 5062 }, 5063 { 5064 name: "MULQU2", 5065 argLen: 2, 5066 clobberFlags: true, 5067 asm: x86.AMULQ, 5068 reg: regInfo{ 5069 inputs: []inputInfo{ 5070 {0, 1}, // AX 5071 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5072 }, 5073 outputs: []outputInfo{ 5074 {0, 4}, // DX 5075 {1, 1}, // AX 5076 }, 5077 }, 5078 }, 5079 { 5080 name: "DIVQU2", 5081 argLen: 3, 5082 clobberFlags: true, 5083 asm: x86.ADIVQ, 5084 reg: regInfo{ 5085 inputs: []inputInfo{ 5086 {0, 4}, // DX 5087 {1, 1}, // AX 5088 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5089 }, 5090 outputs: []outputInfo{ 5091 {0, 1}, // AX 5092 {1, 4}, // DX 5093 }, 5094 }, 5095 }, 5096 { 5097 name: "ANDQ", 5098 argLen: 2, 5099 commutative: true, 5100 resultInArg0: true, 5101 clobberFlags: true, 5102 asm: x86.AANDQ, 5103 reg: regInfo{ 5104 inputs: []inputInfo{ 5105 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5106 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5107 }, 5108 outputs: []outputInfo{ 5109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5110 }, 5111 }, 5112 }, 5113 { 5114 name: "ANDL", 5115 argLen: 2, 5116 commutative: true, 5117 resultInArg0: true, 5118 clobberFlags: true, 5119 asm: x86.AANDL, 5120 reg: regInfo{ 5121 inputs: []inputInfo{ 5122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5123 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5124 }, 5125 outputs: []outputInfo{ 5126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5127 }, 5128 }, 5129 }, 5130 { 5131 name: "ANDQconst", 5132 auxType: auxInt64, 5133 argLen: 1, 5134 resultInArg0: true, 5135 clobberFlags: true, 5136 asm: x86.AANDQ, 5137 reg: regInfo{ 5138 inputs: []inputInfo{ 5139 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5140 }, 5141 outputs: []outputInfo{ 5142 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5143 }, 5144 }, 5145 }, 5146 { 5147 name: "ANDLconst", 5148 auxType: auxInt32, 5149 argLen: 1, 5150 resultInArg0: true, 5151 clobberFlags: true, 5152 asm: x86.AANDL, 5153 reg: regInfo{ 5154 inputs: []inputInfo{ 5155 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5156 }, 5157 outputs: []outputInfo{ 5158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5159 }, 5160 }, 5161 }, 5162 { 5163 name: "ORQ", 5164 argLen: 2, 5165 commutative: true, 5166 resultInArg0: true, 5167 clobberFlags: true, 5168 asm: x86.AORQ, 5169 reg: regInfo{ 5170 inputs: []inputInfo{ 5171 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5172 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5173 }, 5174 outputs: []outputInfo{ 5175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5176 }, 5177 }, 5178 }, 5179 { 5180 name: "ORL", 5181 argLen: 2, 5182 commutative: true, 5183 resultInArg0: true, 5184 clobberFlags: true, 5185 asm: x86.AORL, 5186 reg: regInfo{ 5187 inputs: []inputInfo{ 5188 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5189 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5190 }, 5191 outputs: []outputInfo{ 5192 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5193 }, 5194 }, 5195 }, 5196 { 5197 name: "ORQconst", 5198 auxType: auxInt64, 5199 argLen: 1, 5200 resultInArg0: true, 5201 clobberFlags: true, 5202 asm: x86.AORQ, 5203 reg: regInfo{ 5204 inputs: []inputInfo{ 5205 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5206 }, 5207 outputs: []outputInfo{ 5208 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5209 }, 5210 }, 5211 }, 5212 { 5213 name: "ORLconst", 5214 auxType: auxInt32, 5215 argLen: 1, 5216 resultInArg0: true, 5217 clobberFlags: true, 5218 asm: x86.AORL, 5219 reg: regInfo{ 5220 inputs: []inputInfo{ 5221 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5222 }, 5223 outputs: []outputInfo{ 5224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5225 }, 5226 }, 5227 }, 5228 { 5229 name: "XORQ", 5230 argLen: 2, 5231 commutative: true, 5232 resultInArg0: true, 5233 clobberFlags: true, 5234 asm: x86.AXORQ, 5235 reg: regInfo{ 5236 inputs: []inputInfo{ 5237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5238 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5239 }, 5240 outputs: []outputInfo{ 5241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5242 }, 5243 }, 5244 }, 5245 { 5246 name: "XORL", 5247 argLen: 2, 5248 commutative: true, 5249 resultInArg0: true, 5250 clobberFlags: true, 5251 asm: x86.AXORL, 5252 reg: regInfo{ 5253 inputs: []inputInfo{ 5254 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5255 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5256 }, 5257 outputs: []outputInfo{ 5258 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5259 }, 5260 }, 5261 }, 5262 { 5263 name: "XORQconst", 5264 auxType: auxInt64, 5265 argLen: 1, 5266 resultInArg0: true, 5267 clobberFlags: true, 5268 asm: x86.AXORQ, 5269 reg: regInfo{ 5270 inputs: []inputInfo{ 5271 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5272 }, 5273 outputs: []outputInfo{ 5274 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5275 }, 5276 }, 5277 }, 5278 { 5279 name: "XORLconst", 5280 auxType: auxInt32, 5281 argLen: 1, 5282 resultInArg0: true, 5283 clobberFlags: true, 5284 asm: x86.AXORL, 5285 reg: regInfo{ 5286 inputs: []inputInfo{ 5287 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5288 }, 5289 outputs: []outputInfo{ 5290 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5291 }, 5292 }, 5293 }, 5294 { 5295 name: "CMPQ", 5296 argLen: 2, 5297 asm: x86.ACMPQ, 5298 reg: regInfo{ 5299 inputs: []inputInfo{ 5300 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5301 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5302 }, 5303 }, 5304 }, 5305 { 5306 name: "CMPL", 5307 argLen: 2, 5308 asm: x86.ACMPL, 5309 reg: regInfo{ 5310 inputs: []inputInfo{ 5311 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5313 }, 5314 }, 5315 }, 5316 { 5317 name: "CMPW", 5318 argLen: 2, 5319 asm: x86.ACMPW, 5320 reg: regInfo{ 5321 inputs: []inputInfo{ 5322 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5323 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5324 }, 5325 }, 5326 }, 5327 { 5328 name: "CMPB", 5329 argLen: 2, 5330 asm: x86.ACMPB, 5331 reg: regInfo{ 5332 inputs: []inputInfo{ 5333 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5334 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5335 }, 5336 }, 5337 }, 5338 { 5339 name: "CMPQconst", 5340 auxType: auxInt64, 5341 argLen: 1, 5342 asm: x86.ACMPQ, 5343 reg: regInfo{ 5344 inputs: []inputInfo{ 5345 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5346 }, 5347 }, 5348 }, 5349 { 5350 name: "CMPLconst", 5351 auxType: auxInt32, 5352 argLen: 1, 5353 asm: x86.ACMPL, 5354 reg: regInfo{ 5355 inputs: []inputInfo{ 5356 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5357 }, 5358 }, 5359 }, 5360 { 5361 name: "CMPWconst", 5362 auxType: auxInt16, 5363 argLen: 1, 5364 asm: x86.ACMPW, 5365 reg: regInfo{ 5366 inputs: []inputInfo{ 5367 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5368 }, 5369 }, 5370 }, 5371 { 5372 name: "CMPBconst", 5373 auxType: auxInt8, 5374 argLen: 1, 5375 asm: x86.ACMPB, 5376 reg: regInfo{ 5377 inputs: []inputInfo{ 5378 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5379 }, 5380 }, 5381 }, 5382 { 5383 name: "UCOMISS", 5384 argLen: 2, 5385 asm: x86.AUCOMISS, 5386 reg: regInfo{ 5387 inputs: []inputInfo{ 5388 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5389 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5390 }, 5391 }, 5392 }, 5393 { 5394 name: "UCOMISD", 5395 argLen: 2, 5396 asm: x86.AUCOMISD, 5397 reg: regInfo{ 5398 inputs: []inputInfo{ 5399 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5400 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5401 }, 5402 }, 5403 }, 5404 { 5405 name: "TESTQ", 5406 argLen: 2, 5407 asm: x86.ATESTQ, 5408 reg: regInfo{ 5409 inputs: []inputInfo{ 5410 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5411 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5412 }, 5413 }, 5414 }, 5415 { 5416 name: "TESTL", 5417 argLen: 2, 5418 asm: x86.ATESTL, 5419 reg: regInfo{ 5420 inputs: []inputInfo{ 5421 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5422 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5423 }, 5424 }, 5425 }, 5426 { 5427 name: "TESTW", 5428 argLen: 2, 5429 asm: x86.ATESTW, 5430 reg: regInfo{ 5431 inputs: []inputInfo{ 5432 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5433 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5434 }, 5435 }, 5436 }, 5437 { 5438 name: "TESTB", 5439 argLen: 2, 5440 asm: x86.ATESTB, 5441 reg: regInfo{ 5442 inputs: []inputInfo{ 5443 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5444 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5445 }, 5446 }, 5447 }, 5448 { 5449 name: "TESTQconst", 5450 auxType: auxInt64, 5451 argLen: 1, 5452 asm: x86.ATESTQ, 5453 reg: regInfo{ 5454 inputs: []inputInfo{ 5455 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5456 }, 5457 }, 5458 }, 5459 { 5460 name: "TESTLconst", 5461 auxType: auxInt32, 5462 argLen: 1, 5463 asm: x86.ATESTL, 5464 reg: regInfo{ 5465 inputs: []inputInfo{ 5466 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5467 }, 5468 }, 5469 }, 5470 { 5471 name: "TESTWconst", 5472 auxType: auxInt16, 5473 argLen: 1, 5474 asm: x86.ATESTW, 5475 reg: regInfo{ 5476 inputs: []inputInfo{ 5477 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5478 }, 5479 }, 5480 }, 5481 { 5482 name: "TESTBconst", 5483 auxType: auxInt8, 5484 argLen: 1, 5485 asm: x86.ATESTB, 5486 reg: regInfo{ 5487 inputs: []inputInfo{ 5488 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5489 }, 5490 }, 5491 }, 5492 { 5493 name: "SHLQ", 5494 argLen: 2, 5495 resultInArg0: true, 5496 clobberFlags: true, 5497 asm: x86.ASHLQ, 5498 reg: regInfo{ 5499 inputs: []inputInfo{ 5500 {1, 2}, // CX 5501 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5502 }, 5503 outputs: []outputInfo{ 5504 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5505 }, 5506 }, 5507 }, 5508 { 5509 name: "SHLL", 5510 argLen: 2, 5511 resultInArg0: true, 5512 clobberFlags: true, 5513 asm: x86.ASHLL, 5514 reg: regInfo{ 5515 inputs: []inputInfo{ 5516 {1, 2}, // CX 5517 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5518 }, 5519 outputs: []outputInfo{ 5520 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5521 }, 5522 }, 5523 }, 5524 { 5525 name: "SHLQconst", 5526 auxType: auxInt64, 5527 argLen: 1, 5528 resultInArg0: true, 5529 clobberFlags: true, 5530 asm: x86.ASHLQ, 5531 reg: regInfo{ 5532 inputs: []inputInfo{ 5533 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5534 }, 5535 outputs: []outputInfo{ 5536 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5537 }, 5538 }, 5539 }, 5540 { 5541 name: "SHLLconst", 5542 auxType: auxInt32, 5543 argLen: 1, 5544 resultInArg0: true, 5545 clobberFlags: true, 5546 asm: x86.ASHLL, 5547 reg: regInfo{ 5548 inputs: []inputInfo{ 5549 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5550 }, 5551 outputs: []outputInfo{ 5552 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5553 }, 5554 }, 5555 }, 5556 { 5557 name: "SHRQ", 5558 argLen: 2, 5559 resultInArg0: true, 5560 clobberFlags: true, 5561 asm: x86.ASHRQ, 5562 reg: regInfo{ 5563 inputs: []inputInfo{ 5564 {1, 2}, // CX 5565 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5566 }, 5567 outputs: []outputInfo{ 5568 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5569 }, 5570 }, 5571 }, 5572 { 5573 name: "SHRL", 5574 argLen: 2, 5575 resultInArg0: true, 5576 clobberFlags: true, 5577 asm: x86.ASHRL, 5578 reg: regInfo{ 5579 inputs: []inputInfo{ 5580 {1, 2}, // CX 5581 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5582 }, 5583 outputs: []outputInfo{ 5584 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5585 }, 5586 }, 5587 }, 5588 { 5589 name: "SHRW", 5590 argLen: 2, 5591 resultInArg0: true, 5592 clobberFlags: true, 5593 asm: x86.ASHRW, 5594 reg: regInfo{ 5595 inputs: []inputInfo{ 5596 {1, 2}, // CX 5597 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5598 }, 5599 outputs: []outputInfo{ 5600 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5601 }, 5602 }, 5603 }, 5604 { 5605 name: "SHRB", 5606 argLen: 2, 5607 resultInArg0: true, 5608 clobberFlags: true, 5609 asm: x86.ASHRB, 5610 reg: regInfo{ 5611 inputs: []inputInfo{ 5612 {1, 2}, // CX 5613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5614 }, 5615 outputs: []outputInfo{ 5616 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5617 }, 5618 }, 5619 }, 5620 { 5621 name: "SHRQconst", 5622 auxType: auxInt64, 5623 argLen: 1, 5624 resultInArg0: true, 5625 clobberFlags: true, 5626 asm: x86.ASHRQ, 5627 reg: regInfo{ 5628 inputs: []inputInfo{ 5629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5630 }, 5631 outputs: []outputInfo{ 5632 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5633 }, 5634 }, 5635 }, 5636 { 5637 name: "SHRLconst", 5638 auxType: auxInt32, 5639 argLen: 1, 5640 resultInArg0: true, 5641 clobberFlags: true, 5642 asm: x86.ASHRL, 5643 reg: regInfo{ 5644 inputs: []inputInfo{ 5645 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5646 }, 5647 outputs: []outputInfo{ 5648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5649 }, 5650 }, 5651 }, 5652 { 5653 name: "SHRWconst", 5654 auxType: auxInt16, 5655 argLen: 1, 5656 resultInArg0: true, 5657 clobberFlags: true, 5658 asm: x86.ASHRW, 5659 reg: regInfo{ 5660 inputs: []inputInfo{ 5661 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5662 }, 5663 outputs: []outputInfo{ 5664 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5665 }, 5666 }, 5667 }, 5668 { 5669 name: "SHRBconst", 5670 auxType: auxInt8, 5671 argLen: 1, 5672 resultInArg0: true, 5673 clobberFlags: true, 5674 asm: x86.ASHRB, 5675 reg: regInfo{ 5676 inputs: []inputInfo{ 5677 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5678 }, 5679 outputs: []outputInfo{ 5680 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5681 }, 5682 }, 5683 }, 5684 { 5685 name: "SARQ", 5686 argLen: 2, 5687 resultInArg0: true, 5688 clobberFlags: true, 5689 asm: x86.ASARQ, 5690 reg: regInfo{ 5691 inputs: []inputInfo{ 5692 {1, 2}, // CX 5693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5694 }, 5695 outputs: []outputInfo{ 5696 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5697 }, 5698 }, 5699 }, 5700 { 5701 name: "SARL", 5702 argLen: 2, 5703 resultInArg0: true, 5704 clobberFlags: true, 5705 asm: x86.ASARL, 5706 reg: regInfo{ 5707 inputs: []inputInfo{ 5708 {1, 2}, // CX 5709 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5710 }, 5711 outputs: []outputInfo{ 5712 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5713 }, 5714 }, 5715 }, 5716 { 5717 name: "SARW", 5718 argLen: 2, 5719 resultInArg0: true, 5720 clobberFlags: true, 5721 asm: x86.ASARW, 5722 reg: regInfo{ 5723 inputs: []inputInfo{ 5724 {1, 2}, // CX 5725 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5726 }, 5727 outputs: []outputInfo{ 5728 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5729 }, 5730 }, 5731 }, 5732 { 5733 name: "SARB", 5734 argLen: 2, 5735 resultInArg0: true, 5736 clobberFlags: true, 5737 asm: x86.ASARB, 5738 reg: regInfo{ 5739 inputs: []inputInfo{ 5740 {1, 2}, // CX 5741 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5742 }, 5743 outputs: []outputInfo{ 5744 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5745 }, 5746 }, 5747 }, 5748 { 5749 name: "SARQconst", 5750 auxType: auxInt64, 5751 argLen: 1, 5752 resultInArg0: true, 5753 clobberFlags: true, 5754 asm: x86.ASARQ, 5755 reg: regInfo{ 5756 inputs: []inputInfo{ 5757 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5758 }, 5759 outputs: []outputInfo{ 5760 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5761 }, 5762 }, 5763 }, 5764 { 5765 name: "SARLconst", 5766 auxType: auxInt32, 5767 argLen: 1, 5768 resultInArg0: true, 5769 clobberFlags: true, 5770 asm: x86.ASARL, 5771 reg: regInfo{ 5772 inputs: []inputInfo{ 5773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5774 }, 5775 outputs: []outputInfo{ 5776 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5777 }, 5778 }, 5779 }, 5780 { 5781 name: "SARWconst", 5782 auxType: auxInt16, 5783 argLen: 1, 5784 resultInArg0: true, 5785 clobberFlags: true, 5786 asm: x86.ASARW, 5787 reg: regInfo{ 5788 inputs: []inputInfo{ 5789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5790 }, 5791 outputs: []outputInfo{ 5792 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5793 }, 5794 }, 5795 }, 5796 { 5797 name: "SARBconst", 5798 auxType: auxInt8, 5799 argLen: 1, 5800 resultInArg0: true, 5801 clobberFlags: true, 5802 asm: x86.ASARB, 5803 reg: regInfo{ 5804 inputs: []inputInfo{ 5805 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5806 }, 5807 outputs: []outputInfo{ 5808 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5809 }, 5810 }, 5811 }, 5812 { 5813 name: "ROLQconst", 5814 auxType: auxInt64, 5815 argLen: 1, 5816 resultInArg0: true, 5817 clobberFlags: true, 5818 asm: x86.AROLQ, 5819 reg: regInfo{ 5820 inputs: []inputInfo{ 5821 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5822 }, 5823 outputs: []outputInfo{ 5824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5825 }, 5826 }, 5827 }, 5828 { 5829 name: "ROLLconst", 5830 auxType: auxInt32, 5831 argLen: 1, 5832 resultInArg0: true, 5833 clobberFlags: true, 5834 asm: x86.AROLL, 5835 reg: regInfo{ 5836 inputs: []inputInfo{ 5837 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5838 }, 5839 outputs: []outputInfo{ 5840 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5841 }, 5842 }, 5843 }, 5844 { 5845 name: "ROLWconst", 5846 auxType: auxInt16, 5847 argLen: 1, 5848 resultInArg0: true, 5849 clobberFlags: true, 5850 asm: x86.AROLW, 5851 reg: regInfo{ 5852 inputs: []inputInfo{ 5853 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5854 }, 5855 outputs: []outputInfo{ 5856 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5857 }, 5858 }, 5859 }, 5860 { 5861 name: "ROLBconst", 5862 auxType: auxInt8, 5863 argLen: 1, 5864 resultInArg0: true, 5865 clobberFlags: true, 5866 asm: x86.AROLB, 5867 reg: regInfo{ 5868 inputs: []inputInfo{ 5869 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5870 }, 5871 outputs: []outputInfo{ 5872 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5873 }, 5874 }, 5875 }, 5876 { 5877 name: "NEGQ", 5878 argLen: 1, 5879 resultInArg0: true, 5880 clobberFlags: true, 5881 asm: x86.ANEGQ, 5882 reg: regInfo{ 5883 inputs: []inputInfo{ 5884 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5885 }, 5886 outputs: []outputInfo{ 5887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5888 }, 5889 }, 5890 }, 5891 { 5892 name: "NEGL", 5893 argLen: 1, 5894 resultInArg0: true, 5895 clobberFlags: true, 5896 asm: x86.ANEGL, 5897 reg: regInfo{ 5898 inputs: []inputInfo{ 5899 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5900 }, 5901 outputs: []outputInfo{ 5902 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5903 }, 5904 }, 5905 }, 5906 { 5907 name: "NOTQ", 5908 argLen: 1, 5909 resultInArg0: true, 5910 clobberFlags: true, 5911 asm: x86.ANOTQ, 5912 reg: regInfo{ 5913 inputs: []inputInfo{ 5914 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5915 }, 5916 outputs: []outputInfo{ 5917 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5918 }, 5919 }, 5920 }, 5921 { 5922 name: "NOTL", 5923 argLen: 1, 5924 resultInArg0: true, 5925 clobberFlags: true, 5926 asm: x86.ANOTL, 5927 reg: regInfo{ 5928 inputs: []inputInfo{ 5929 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5930 }, 5931 outputs: []outputInfo{ 5932 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5933 }, 5934 }, 5935 }, 5936 { 5937 name: "BSFQ", 5938 argLen: 1, 5939 asm: x86.ABSFQ, 5940 reg: regInfo{ 5941 inputs: []inputInfo{ 5942 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5943 }, 5944 outputs: []outputInfo{ 5945 {1, 0}, 5946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5947 }, 5948 }, 5949 }, 5950 { 5951 name: "BSFL", 5952 argLen: 1, 5953 asm: x86.ABSFL, 5954 reg: regInfo{ 5955 inputs: []inputInfo{ 5956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 }, 5958 outputs: []outputInfo{ 5959 {1, 0}, 5960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5961 }, 5962 }, 5963 }, 5964 { 5965 name: "CMOVQEQ", 5966 argLen: 3, 5967 resultInArg0: true, 5968 asm: x86.ACMOVQEQ, 5969 reg: regInfo{ 5970 inputs: []inputInfo{ 5971 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5972 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 outputs: []outputInfo{ 5975 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5976 }, 5977 }, 5978 }, 5979 { 5980 name: "CMOVLEQ", 5981 argLen: 3, 5982 resultInArg0: true, 5983 asm: x86.ACMOVLEQ, 5984 reg: regInfo{ 5985 inputs: []inputInfo{ 5986 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5987 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5988 }, 5989 outputs: []outputInfo{ 5990 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5991 }, 5992 }, 5993 }, 5994 { 5995 name: "BSWAPQ", 5996 argLen: 1, 5997 resultInArg0: true, 5998 clobberFlags: true, 5999 asm: x86.ABSWAPQ, 6000 reg: regInfo{ 6001 inputs: []inputInfo{ 6002 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6003 }, 6004 outputs: []outputInfo{ 6005 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6006 }, 6007 }, 6008 }, 6009 { 6010 name: "BSWAPL", 6011 argLen: 1, 6012 resultInArg0: true, 6013 clobberFlags: true, 6014 asm: x86.ABSWAPL, 6015 reg: regInfo{ 6016 inputs: []inputInfo{ 6017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6018 }, 6019 outputs: []outputInfo{ 6020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6021 }, 6022 }, 6023 }, 6024 { 6025 name: "SQRTSD", 6026 argLen: 1, 6027 asm: x86.ASQRTSD, 6028 reg: regInfo{ 6029 inputs: []inputInfo{ 6030 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6031 }, 6032 outputs: []outputInfo{ 6033 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6034 }, 6035 }, 6036 }, 6037 { 6038 name: "SBBQcarrymask", 6039 argLen: 1, 6040 asm: x86.ASBBQ, 6041 reg: regInfo{ 6042 outputs: []outputInfo{ 6043 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6044 }, 6045 }, 6046 }, 6047 { 6048 name: "SBBLcarrymask", 6049 argLen: 1, 6050 asm: x86.ASBBL, 6051 reg: regInfo{ 6052 outputs: []outputInfo{ 6053 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6054 }, 6055 }, 6056 }, 6057 { 6058 name: "SETEQ", 6059 argLen: 1, 6060 asm: x86.ASETEQ, 6061 reg: regInfo{ 6062 outputs: []outputInfo{ 6063 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6064 }, 6065 }, 6066 }, 6067 { 6068 name: "SETNE", 6069 argLen: 1, 6070 asm: x86.ASETNE, 6071 reg: regInfo{ 6072 outputs: []outputInfo{ 6073 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6074 }, 6075 }, 6076 }, 6077 { 6078 name: "SETL", 6079 argLen: 1, 6080 asm: x86.ASETLT, 6081 reg: regInfo{ 6082 outputs: []outputInfo{ 6083 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6084 }, 6085 }, 6086 }, 6087 { 6088 name: "SETLE", 6089 argLen: 1, 6090 asm: x86.ASETLE, 6091 reg: regInfo{ 6092 outputs: []outputInfo{ 6093 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6094 }, 6095 }, 6096 }, 6097 { 6098 name: "SETG", 6099 argLen: 1, 6100 asm: x86.ASETGT, 6101 reg: regInfo{ 6102 outputs: []outputInfo{ 6103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6104 }, 6105 }, 6106 }, 6107 { 6108 name: "SETGE", 6109 argLen: 1, 6110 asm: x86.ASETGE, 6111 reg: regInfo{ 6112 outputs: []outputInfo{ 6113 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6114 }, 6115 }, 6116 }, 6117 { 6118 name: "SETB", 6119 argLen: 1, 6120 asm: x86.ASETCS, 6121 reg: regInfo{ 6122 outputs: []outputInfo{ 6123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6124 }, 6125 }, 6126 }, 6127 { 6128 name: "SETBE", 6129 argLen: 1, 6130 asm: x86.ASETLS, 6131 reg: regInfo{ 6132 outputs: []outputInfo{ 6133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6134 }, 6135 }, 6136 }, 6137 { 6138 name: "SETA", 6139 argLen: 1, 6140 asm: x86.ASETHI, 6141 reg: regInfo{ 6142 outputs: []outputInfo{ 6143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6144 }, 6145 }, 6146 }, 6147 { 6148 name: "SETAE", 6149 argLen: 1, 6150 asm: x86.ASETCC, 6151 reg: regInfo{ 6152 outputs: []outputInfo{ 6153 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6154 }, 6155 }, 6156 }, 6157 { 6158 name: "SETEQF", 6159 argLen: 1, 6160 clobberFlags: true, 6161 asm: x86.ASETEQ, 6162 reg: regInfo{ 6163 clobbers: 1, // AX 6164 outputs: []outputInfo{ 6165 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6166 }, 6167 }, 6168 }, 6169 { 6170 name: "SETNEF", 6171 argLen: 1, 6172 clobberFlags: true, 6173 asm: x86.ASETNE, 6174 reg: regInfo{ 6175 clobbers: 1, // AX 6176 outputs: []outputInfo{ 6177 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6178 }, 6179 }, 6180 }, 6181 { 6182 name: "SETORD", 6183 argLen: 1, 6184 asm: x86.ASETPC, 6185 reg: regInfo{ 6186 outputs: []outputInfo{ 6187 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6188 }, 6189 }, 6190 }, 6191 { 6192 name: "SETNAN", 6193 argLen: 1, 6194 asm: x86.ASETPS, 6195 reg: regInfo{ 6196 outputs: []outputInfo{ 6197 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6198 }, 6199 }, 6200 }, 6201 { 6202 name: "SETGF", 6203 argLen: 1, 6204 asm: x86.ASETHI, 6205 reg: regInfo{ 6206 outputs: []outputInfo{ 6207 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6208 }, 6209 }, 6210 }, 6211 { 6212 name: "SETGEF", 6213 argLen: 1, 6214 asm: x86.ASETCC, 6215 reg: regInfo{ 6216 outputs: []outputInfo{ 6217 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6218 }, 6219 }, 6220 }, 6221 { 6222 name: "MOVBQSX", 6223 argLen: 1, 6224 asm: x86.AMOVBQSX, 6225 reg: regInfo{ 6226 inputs: []inputInfo{ 6227 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6228 }, 6229 outputs: []outputInfo{ 6230 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6231 }, 6232 }, 6233 }, 6234 { 6235 name: "MOVBQZX", 6236 argLen: 1, 6237 asm: x86.AMOVBLZX, 6238 reg: regInfo{ 6239 inputs: []inputInfo{ 6240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6241 }, 6242 outputs: []outputInfo{ 6243 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6244 }, 6245 }, 6246 }, 6247 { 6248 name: "MOVWQSX", 6249 argLen: 1, 6250 asm: x86.AMOVWQSX, 6251 reg: regInfo{ 6252 inputs: []inputInfo{ 6253 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6254 }, 6255 outputs: []outputInfo{ 6256 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6257 }, 6258 }, 6259 }, 6260 { 6261 name: "MOVWQZX", 6262 argLen: 1, 6263 asm: x86.AMOVWLZX, 6264 reg: regInfo{ 6265 inputs: []inputInfo{ 6266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6267 }, 6268 outputs: []outputInfo{ 6269 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6270 }, 6271 }, 6272 }, 6273 { 6274 name: "MOVLQSX", 6275 argLen: 1, 6276 asm: x86.AMOVLQSX, 6277 reg: regInfo{ 6278 inputs: []inputInfo{ 6279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6280 }, 6281 outputs: []outputInfo{ 6282 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6283 }, 6284 }, 6285 }, 6286 { 6287 name: "MOVLQZX", 6288 argLen: 1, 6289 asm: x86.AMOVL, 6290 reg: regInfo{ 6291 inputs: []inputInfo{ 6292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6293 }, 6294 outputs: []outputInfo{ 6295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6296 }, 6297 }, 6298 }, 6299 { 6300 name: "MOVLconst", 6301 auxType: auxInt32, 6302 argLen: 0, 6303 rematerializeable: true, 6304 asm: x86.AMOVL, 6305 reg: regInfo{ 6306 outputs: []outputInfo{ 6307 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6308 }, 6309 }, 6310 }, 6311 { 6312 name: "MOVQconst", 6313 auxType: auxInt64, 6314 argLen: 0, 6315 rematerializeable: true, 6316 asm: x86.AMOVQ, 6317 reg: regInfo{ 6318 outputs: []outputInfo{ 6319 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6320 }, 6321 }, 6322 }, 6323 { 6324 name: "CVTTSD2SL", 6325 argLen: 1, 6326 asm: x86.ACVTTSD2SL, 6327 reg: regInfo{ 6328 inputs: []inputInfo{ 6329 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6330 }, 6331 outputs: []outputInfo{ 6332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6333 }, 6334 }, 6335 }, 6336 { 6337 name: "CVTTSD2SQ", 6338 argLen: 1, 6339 asm: x86.ACVTTSD2SQ, 6340 reg: regInfo{ 6341 inputs: []inputInfo{ 6342 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6343 }, 6344 outputs: []outputInfo{ 6345 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6346 }, 6347 }, 6348 }, 6349 { 6350 name: "CVTTSS2SL", 6351 argLen: 1, 6352 asm: x86.ACVTTSS2SL, 6353 reg: regInfo{ 6354 inputs: []inputInfo{ 6355 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6356 }, 6357 outputs: []outputInfo{ 6358 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6359 }, 6360 }, 6361 }, 6362 { 6363 name: "CVTTSS2SQ", 6364 argLen: 1, 6365 asm: x86.ACVTTSS2SQ, 6366 reg: regInfo{ 6367 inputs: []inputInfo{ 6368 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6369 }, 6370 outputs: []outputInfo{ 6371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6372 }, 6373 }, 6374 }, 6375 { 6376 name: "CVTSL2SS", 6377 argLen: 1, 6378 asm: x86.ACVTSL2SS, 6379 reg: regInfo{ 6380 inputs: []inputInfo{ 6381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6382 }, 6383 outputs: []outputInfo{ 6384 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6385 }, 6386 }, 6387 }, 6388 { 6389 name: "CVTSL2SD", 6390 argLen: 1, 6391 asm: x86.ACVTSL2SD, 6392 reg: regInfo{ 6393 inputs: []inputInfo{ 6394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6395 }, 6396 outputs: []outputInfo{ 6397 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6398 }, 6399 }, 6400 }, 6401 { 6402 name: "CVTSQ2SS", 6403 argLen: 1, 6404 asm: x86.ACVTSQ2SS, 6405 reg: regInfo{ 6406 inputs: []inputInfo{ 6407 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6408 }, 6409 outputs: []outputInfo{ 6410 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6411 }, 6412 }, 6413 }, 6414 { 6415 name: "CVTSQ2SD", 6416 argLen: 1, 6417 asm: x86.ACVTSQ2SD, 6418 reg: regInfo{ 6419 inputs: []inputInfo{ 6420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6421 }, 6422 outputs: []outputInfo{ 6423 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6424 }, 6425 }, 6426 }, 6427 { 6428 name: "CVTSD2SS", 6429 argLen: 1, 6430 asm: x86.ACVTSD2SS, 6431 reg: regInfo{ 6432 inputs: []inputInfo{ 6433 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6434 }, 6435 outputs: []outputInfo{ 6436 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6437 }, 6438 }, 6439 }, 6440 { 6441 name: "CVTSS2SD", 6442 argLen: 1, 6443 asm: x86.ACVTSS2SD, 6444 reg: regInfo{ 6445 inputs: []inputInfo{ 6446 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6447 }, 6448 outputs: []outputInfo{ 6449 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6450 }, 6451 }, 6452 }, 6453 { 6454 name: "PXOR", 6455 argLen: 2, 6456 commutative: true, 6457 resultInArg0: true, 6458 asm: x86.APXOR, 6459 reg: regInfo{ 6460 inputs: []inputInfo{ 6461 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6462 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6463 }, 6464 outputs: []outputInfo{ 6465 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6466 }, 6467 }, 6468 }, 6469 { 6470 name: "LEAQ", 6471 auxType: auxSymOff, 6472 argLen: 1, 6473 rematerializeable: true, 6474 asm: x86.ALEAQ, 6475 reg: regInfo{ 6476 inputs: []inputInfo{ 6477 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6478 }, 6479 outputs: []outputInfo{ 6480 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6481 }, 6482 }, 6483 }, 6484 { 6485 name: "LEAQ1", 6486 auxType: auxSymOff, 6487 argLen: 2, 6488 reg: regInfo{ 6489 inputs: []inputInfo{ 6490 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6491 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6492 }, 6493 outputs: []outputInfo{ 6494 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6495 }, 6496 }, 6497 }, 6498 { 6499 name: "LEAQ2", 6500 auxType: auxSymOff, 6501 argLen: 2, 6502 reg: regInfo{ 6503 inputs: []inputInfo{ 6504 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6505 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6506 }, 6507 outputs: []outputInfo{ 6508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6509 }, 6510 }, 6511 }, 6512 { 6513 name: "LEAQ4", 6514 auxType: auxSymOff, 6515 argLen: 2, 6516 reg: regInfo{ 6517 inputs: []inputInfo{ 6518 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6519 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6520 }, 6521 outputs: []outputInfo{ 6522 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6523 }, 6524 }, 6525 }, 6526 { 6527 name: "LEAQ8", 6528 auxType: auxSymOff, 6529 argLen: 2, 6530 reg: regInfo{ 6531 inputs: []inputInfo{ 6532 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6533 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6534 }, 6535 outputs: []outputInfo{ 6536 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6537 }, 6538 }, 6539 }, 6540 { 6541 name: "LEAL", 6542 auxType: auxSymOff, 6543 argLen: 1, 6544 rematerializeable: true, 6545 asm: x86.ALEAL, 6546 reg: regInfo{ 6547 inputs: []inputInfo{ 6548 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6549 }, 6550 outputs: []outputInfo{ 6551 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6552 }, 6553 }, 6554 }, 6555 { 6556 name: "MOVBload", 6557 auxType: auxSymOff, 6558 argLen: 2, 6559 faultOnNilArg0: true, 6560 asm: x86.AMOVBLZX, 6561 reg: regInfo{ 6562 inputs: []inputInfo{ 6563 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6564 }, 6565 outputs: []outputInfo{ 6566 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6567 }, 6568 }, 6569 }, 6570 { 6571 name: "MOVBQSXload", 6572 auxType: auxSymOff, 6573 argLen: 2, 6574 faultOnNilArg0: true, 6575 asm: x86.AMOVBQSX, 6576 reg: regInfo{ 6577 inputs: []inputInfo{ 6578 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6579 }, 6580 outputs: []outputInfo{ 6581 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6582 }, 6583 }, 6584 }, 6585 { 6586 name: "MOVWload", 6587 auxType: auxSymOff, 6588 argLen: 2, 6589 faultOnNilArg0: true, 6590 asm: x86.AMOVWLZX, 6591 reg: regInfo{ 6592 inputs: []inputInfo{ 6593 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6594 }, 6595 outputs: []outputInfo{ 6596 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6597 }, 6598 }, 6599 }, 6600 { 6601 name: "MOVWQSXload", 6602 auxType: auxSymOff, 6603 argLen: 2, 6604 faultOnNilArg0: true, 6605 asm: x86.AMOVWQSX, 6606 reg: regInfo{ 6607 inputs: []inputInfo{ 6608 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6609 }, 6610 outputs: []outputInfo{ 6611 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6612 }, 6613 }, 6614 }, 6615 { 6616 name: "MOVLload", 6617 auxType: auxSymOff, 6618 argLen: 2, 6619 faultOnNilArg0: true, 6620 asm: x86.AMOVL, 6621 reg: regInfo{ 6622 inputs: []inputInfo{ 6623 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6624 }, 6625 outputs: []outputInfo{ 6626 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6627 }, 6628 }, 6629 }, 6630 { 6631 name: "MOVLQSXload", 6632 auxType: auxSymOff, 6633 argLen: 2, 6634 faultOnNilArg0: true, 6635 asm: x86.AMOVLQSX, 6636 reg: regInfo{ 6637 inputs: []inputInfo{ 6638 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6639 }, 6640 outputs: []outputInfo{ 6641 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6642 }, 6643 }, 6644 }, 6645 { 6646 name: "MOVQload", 6647 auxType: auxSymOff, 6648 argLen: 2, 6649 faultOnNilArg0: true, 6650 asm: x86.AMOVQ, 6651 reg: regInfo{ 6652 inputs: []inputInfo{ 6653 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6654 }, 6655 outputs: []outputInfo{ 6656 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6657 }, 6658 }, 6659 }, 6660 { 6661 name: "MOVBstore", 6662 auxType: auxSymOff, 6663 argLen: 3, 6664 faultOnNilArg0: true, 6665 asm: x86.AMOVB, 6666 reg: regInfo{ 6667 inputs: []inputInfo{ 6668 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6669 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6670 }, 6671 }, 6672 }, 6673 { 6674 name: "MOVWstore", 6675 auxType: auxSymOff, 6676 argLen: 3, 6677 faultOnNilArg0: true, 6678 asm: x86.AMOVW, 6679 reg: regInfo{ 6680 inputs: []inputInfo{ 6681 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6682 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6683 }, 6684 }, 6685 }, 6686 { 6687 name: "MOVLstore", 6688 auxType: auxSymOff, 6689 argLen: 3, 6690 faultOnNilArg0: true, 6691 asm: x86.AMOVL, 6692 reg: regInfo{ 6693 inputs: []inputInfo{ 6694 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6695 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6696 }, 6697 }, 6698 }, 6699 { 6700 name: "MOVQstore", 6701 auxType: auxSymOff, 6702 argLen: 3, 6703 faultOnNilArg0: true, 6704 asm: x86.AMOVQ, 6705 reg: regInfo{ 6706 inputs: []inputInfo{ 6707 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6708 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6709 }, 6710 }, 6711 }, 6712 { 6713 name: "MOVOload", 6714 auxType: auxSymOff, 6715 argLen: 2, 6716 faultOnNilArg0: true, 6717 asm: x86.AMOVUPS, 6718 reg: regInfo{ 6719 inputs: []inputInfo{ 6720 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6721 }, 6722 outputs: []outputInfo{ 6723 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6724 }, 6725 }, 6726 }, 6727 { 6728 name: "MOVOstore", 6729 auxType: auxSymOff, 6730 argLen: 3, 6731 faultOnNilArg0: true, 6732 asm: x86.AMOVUPS, 6733 reg: regInfo{ 6734 inputs: []inputInfo{ 6735 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6736 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6737 }, 6738 }, 6739 }, 6740 { 6741 name: "MOVBloadidx1", 6742 auxType: auxSymOff, 6743 argLen: 3, 6744 asm: x86.AMOVBLZX, 6745 reg: regInfo{ 6746 inputs: []inputInfo{ 6747 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6749 }, 6750 outputs: []outputInfo{ 6751 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6752 }, 6753 }, 6754 }, 6755 { 6756 name: "MOVWloadidx1", 6757 auxType: auxSymOff, 6758 argLen: 3, 6759 asm: x86.AMOVWLZX, 6760 reg: regInfo{ 6761 inputs: []inputInfo{ 6762 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6763 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6764 }, 6765 outputs: []outputInfo{ 6766 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6767 }, 6768 }, 6769 }, 6770 { 6771 name: "MOVWloadidx2", 6772 auxType: auxSymOff, 6773 argLen: 3, 6774 asm: x86.AMOVWLZX, 6775 reg: regInfo{ 6776 inputs: []inputInfo{ 6777 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6778 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6779 }, 6780 outputs: []outputInfo{ 6781 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6782 }, 6783 }, 6784 }, 6785 { 6786 name: "MOVLloadidx1", 6787 auxType: auxSymOff, 6788 argLen: 3, 6789 asm: x86.AMOVL, 6790 reg: regInfo{ 6791 inputs: []inputInfo{ 6792 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6793 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6794 }, 6795 outputs: []outputInfo{ 6796 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6797 }, 6798 }, 6799 }, 6800 { 6801 name: "MOVLloadidx4", 6802 auxType: auxSymOff, 6803 argLen: 3, 6804 asm: x86.AMOVL, 6805 reg: regInfo{ 6806 inputs: []inputInfo{ 6807 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6808 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6809 }, 6810 outputs: []outputInfo{ 6811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6812 }, 6813 }, 6814 }, 6815 { 6816 name: "MOVQloadidx1", 6817 auxType: auxSymOff, 6818 argLen: 3, 6819 asm: x86.AMOVQ, 6820 reg: regInfo{ 6821 inputs: []inputInfo{ 6822 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6823 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6824 }, 6825 outputs: []outputInfo{ 6826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6827 }, 6828 }, 6829 }, 6830 { 6831 name: "MOVQloadidx8", 6832 auxType: auxSymOff, 6833 argLen: 3, 6834 asm: x86.AMOVQ, 6835 reg: regInfo{ 6836 inputs: []inputInfo{ 6837 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6838 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6839 }, 6840 outputs: []outputInfo{ 6841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6842 }, 6843 }, 6844 }, 6845 { 6846 name: "MOVBstoreidx1", 6847 auxType: auxSymOff, 6848 argLen: 4, 6849 asm: x86.AMOVB, 6850 reg: regInfo{ 6851 inputs: []inputInfo{ 6852 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6853 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6854 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6855 }, 6856 }, 6857 }, 6858 { 6859 name: "MOVWstoreidx1", 6860 auxType: auxSymOff, 6861 argLen: 4, 6862 asm: x86.AMOVW, 6863 reg: regInfo{ 6864 inputs: []inputInfo{ 6865 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6866 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6867 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6868 }, 6869 }, 6870 }, 6871 { 6872 name: "MOVWstoreidx2", 6873 auxType: auxSymOff, 6874 argLen: 4, 6875 asm: x86.AMOVW, 6876 reg: regInfo{ 6877 inputs: []inputInfo{ 6878 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6879 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6880 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6881 }, 6882 }, 6883 }, 6884 { 6885 name: "MOVLstoreidx1", 6886 auxType: auxSymOff, 6887 argLen: 4, 6888 asm: x86.AMOVL, 6889 reg: regInfo{ 6890 inputs: []inputInfo{ 6891 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6892 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6893 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6894 }, 6895 }, 6896 }, 6897 { 6898 name: "MOVLstoreidx4", 6899 auxType: auxSymOff, 6900 argLen: 4, 6901 asm: x86.AMOVL, 6902 reg: regInfo{ 6903 inputs: []inputInfo{ 6904 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6905 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6906 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6907 }, 6908 }, 6909 }, 6910 { 6911 name: "MOVQstoreidx1", 6912 auxType: auxSymOff, 6913 argLen: 4, 6914 asm: x86.AMOVQ, 6915 reg: regInfo{ 6916 inputs: []inputInfo{ 6917 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6918 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6919 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6920 }, 6921 }, 6922 }, 6923 { 6924 name: "MOVQstoreidx8", 6925 auxType: auxSymOff, 6926 argLen: 4, 6927 asm: x86.AMOVQ, 6928 reg: regInfo{ 6929 inputs: []inputInfo{ 6930 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6931 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6932 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6933 }, 6934 }, 6935 }, 6936 { 6937 name: "MOVBstoreconst", 6938 auxType: auxSymValAndOff, 6939 argLen: 2, 6940 faultOnNilArg0: true, 6941 asm: x86.AMOVB, 6942 reg: regInfo{ 6943 inputs: []inputInfo{ 6944 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6945 }, 6946 }, 6947 }, 6948 { 6949 name: "MOVWstoreconst", 6950 auxType: auxSymValAndOff, 6951 argLen: 2, 6952 faultOnNilArg0: true, 6953 asm: x86.AMOVW, 6954 reg: regInfo{ 6955 inputs: []inputInfo{ 6956 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6957 }, 6958 }, 6959 }, 6960 { 6961 name: "MOVLstoreconst", 6962 auxType: auxSymValAndOff, 6963 argLen: 2, 6964 faultOnNilArg0: true, 6965 asm: x86.AMOVL, 6966 reg: regInfo{ 6967 inputs: []inputInfo{ 6968 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6969 }, 6970 }, 6971 }, 6972 { 6973 name: "MOVQstoreconst", 6974 auxType: auxSymValAndOff, 6975 argLen: 2, 6976 faultOnNilArg0: true, 6977 asm: x86.AMOVQ, 6978 reg: regInfo{ 6979 inputs: []inputInfo{ 6980 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6981 }, 6982 }, 6983 }, 6984 { 6985 name: "MOVBstoreconstidx1", 6986 auxType: auxSymValAndOff, 6987 argLen: 3, 6988 asm: x86.AMOVB, 6989 reg: regInfo{ 6990 inputs: []inputInfo{ 6991 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6992 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6993 }, 6994 }, 6995 }, 6996 { 6997 name: "MOVWstoreconstidx1", 6998 auxType: auxSymValAndOff, 6999 argLen: 3, 7000 asm: x86.AMOVW, 7001 reg: regInfo{ 7002 inputs: []inputInfo{ 7003 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7004 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7005 }, 7006 }, 7007 }, 7008 { 7009 name: "MOVWstoreconstidx2", 7010 auxType: auxSymValAndOff, 7011 argLen: 3, 7012 asm: x86.AMOVW, 7013 reg: regInfo{ 7014 inputs: []inputInfo{ 7015 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7016 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7017 }, 7018 }, 7019 }, 7020 { 7021 name: "MOVLstoreconstidx1", 7022 auxType: auxSymValAndOff, 7023 argLen: 3, 7024 asm: x86.AMOVL, 7025 reg: regInfo{ 7026 inputs: []inputInfo{ 7027 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7028 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7029 }, 7030 }, 7031 }, 7032 { 7033 name: "MOVLstoreconstidx4", 7034 auxType: auxSymValAndOff, 7035 argLen: 3, 7036 asm: x86.AMOVL, 7037 reg: regInfo{ 7038 inputs: []inputInfo{ 7039 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7040 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7041 }, 7042 }, 7043 }, 7044 { 7045 name: "MOVQstoreconstidx1", 7046 auxType: auxSymValAndOff, 7047 argLen: 3, 7048 asm: x86.AMOVQ, 7049 reg: regInfo{ 7050 inputs: []inputInfo{ 7051 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7052 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7053 }, 7054 }, 7055 }, 7056 { 7057 name: "MOVQstoreconstidx8", 7058 auxType: auxSymValAndOff, 7059 argLen: 3, 7060 asm: x86.AMOVQ, 7061 reg: regInfo{ 7062 inputs: []inputInfo{ 7063 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7064 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7065 }, 7066 }, 7067 }, 7068 { 7069 name: "DUFFZERO", 7070 auxType: auxInt64, 7071 argLen: 3, 7072 clobberFlags: true, 7073 reg: regInfo{ 7074 inputs: []inputInfo{ 7075 {0, 128}, // DI 7076 {1, 65536}, // X0 7077 }, 7078 clobbers: 128, // DI 7079 }, 7080 }, 7081 { 7082 name: "MOVOconst", 7083 auxType: auxInt128, 7084 argLen: 0, 7085 rematerializeable: true, 7086 reg: regInfo{ 7087 outputs: []outputInfo{ 7088 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7089 }, 7090 }, 7091 }, 7092 { 7093 name: "REPSTOSQ", 7094 argLen: 4, 7095 reg: regInfo{ 7096 inputs: []inputInfo{ 7097 {0, 128}, // DI 7098 {1, 2}, // CX 7099 {2, 1}, // AX 7100 }, 7101 clobbers: 130, // CX DI 7102 }, 7103 }, 7104 { 7105 name: "CALLstatic", 7106 auxType: auxSymOff, 7107 argLen: 1, 7108 clobberFlags: true, 7109 call: true, 7110 reg: regInfo{ 7111 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7112 }, 7113 }, 7114 { 7115 name: "CALLclosure", 7116 auxType: auxInt64, 7117 argLen: 3, 7118 clobberFlags: true, 7119 call: true, 7120 reg: regInfo{ 7121 inputs: []inputInfo{ 7122 {1, 4}, // DX 7123 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7124 }, 7125 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7126 }, 7127 }, 7128 { 7129 name: "CALLdefer", 7130 auxType: auxInt64, 7131 argLen: 1, 7132 clobberFlags: true, 7133 call: true, 7134 reg: regInfo{ 7135 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7136 }, 7137 }, 7138 { 7139 name: "CALLgo", 7140 auxType: auxInt64, 7141 argLen: 1, 7142 clobberFlags: true, 7143 call: true, 7144 reg: regInfo{ 7145 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7146 }, 7147 }, 7148 { 7149 name: "CALLinter", 7150 auxType: auxInt64, 7151 argLen: 2, 7152 clobberFlags: true, 7153 call: true, 7154 reg: regInfo{ 7155 inputs: []inputInfo{ 7156 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7157 }, 7158 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7159 }, 7160 }, 7161 { 7162 name: "DUFFCOPY", 7163 auxType: auxInt64, 7164 argLen: 3, 7165 clobberFlags: true, 7166 reg: regInfo{ 7167 inputs: []inputInfo{ 7168 {0, 128}, // DI 7169 {1, 64}, // SI 7170 }, 7171 clobbers: 65728, // SI DI X0 7172 }, 7173 }, 7174 { 7175 name: "REPMOVSQ", 7176 argLen: 4, 7177 reg: regInfo{ 7178 inputs: []inputInfo{ 7179 {0, 128}, // DI 7180 {1, 64}, // SI 7181 {2, 2}, // CX 7182 }, 7183 clobbers: 194, // CX SI DI 7184 }, 7185 }, 7186 { 7187 name: "InvertFlags", 7188 argLen: 1, 7189 reg: regInfo{}, 7190 }, 7191 { 7192 name: "LoweredGetG", 7193 argLen: 1, 7194 reg: regInfo{ 7195 outputs: []outputInfo{ 7196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7197 }, 7198 }, 7199 }, 7200 { 7201 name: "LoweredGetClosurePtr", 7202 argLen: 0, 7203 reg: regInfo{ 7204 outputs: []outputInfo{ 7205 {0, 4}, // DX 7206 }, 7207 }, 7208 }, 7209 { 7210 name: "LoweredNilCheck", 7211 argLen: 2, 7212 clobberFlags: true, 7213 nilCheck: true, 7214 faultOnNilArg0: true, 7215 reg: regInfo{ 7216 inputs: []inputInfo{ 7217 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7218 }, 7219 }, 7220 }, 7221 { 7222 name: "MOVQconvert", 7223 argLen: 2, 7224 asm: x86.AMOVQ, 7225 reg: regInfo{ 7226 inputs: []inputInfo{ 7227 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7228 }, 7229 outputs: []outputInfo{ 7230 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7231 }, 7232 }, 7233 }, 7234 { 7235 name: "MOVLconvert", 7236 argLen: 2, 7237 asm: x86.AMOVL, 7238 reg: regInfo{ 7239 inputs: []inputInfo{ 7240 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7241 }, 7242 outputs: []outputInfo{ 7243 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7244 }, 7245 }, 7246 }, 7247 { 7248 name: "FlagEQ", 7249 argLen: 0, 7250 reg: regInfo{}, 7251 }, 7252 { 7253 name: "FlagLT_ULT", 7254 argLen: 0, 7255 reg: regInfo{}, 7256 }, 7257 { 7258 name: "FlagLT_UGT", 7259 argLen: 0, 7260 reg: regInfo{}, 7261 }, 7262 { 7263 name: "FlagGT_UGT", 7264 argLen: 0, 7265 reg: regInfo{}, 7266 }, 7267 { 7268 name: "FlagGT_ULT", 7269 argLen: 0, 7270 reg: regInfo{}, 7271 }, 7272 { 7273 name: "MOVLatomicload", 7274 auxType: auxSymOff, 7275 argLen: 2, 7276 faultOnNilArg0: true, 7277 asm: x86.AMOVL, 7278 reg: regInfo{ 7279 inputs: []inputInfo{ 7280 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7281 }, 7282 outputs: []outputInfo{ 7283 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7284 }, 7285 }, 7286 }, 7287 { 7288 name: "MOVQatomicload", 7289 auxType: auxSymOff, 7290 argLen: 2, 7291 faultOnNilArg0: true, 7292 asm: x86.AMOVQ, 7293 reg: regInfo{ 7294 inputs: []inputInfo{ 7295 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7296 }, 7297 outputs: []outputInfo{ 7298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7299 }, 7300 }, 7301 }, 7302 { 7303 name: "XCHGL", 7304 auxType: auxSymOff, 7305 argLen: 3, 7306 resultInArg0: true, 7307 faultOnNilArg1: true, 7308 asm: x86.AXCHGL, 7309 reg: regInfo{ 7310 inputs: []inputInfo{ 7311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7312 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7313 }, 7314 outputs: []outputInfo{ 7315 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7316 }, 7317 }, 7318 }, 7319 { 7320 name: "XCHGQ", 7321 auxType: auxSymOff, 7322 argLen: 3, 7323 resultInArg0: true, 7324 faultOnNilArg1: true, 7325 asm: x86.AXCHGQ, 7326 reg: regInfo{ 7327 inputs: []inputInfo{ 7328 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7329 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7330 }, 7331 outputs: []outputInfo{ 7332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7333 }, 7334 }, 7335 }, 7336 { 7337 name: "XADDLlock", 7338 auxType: auxSymOff, 7339 argLen: 3, 7340 resultInArg0: true, 7341 clobberFlags: true, 7342 faultOnNilArg1: true, 7343 asm: x86.AXADDL, 7344 reg: regInfo{ 7345 inputs: []inputInfo{ 7346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7347 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7348 }, 7349 outputs: []outputInfo{ 7350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7351 }, 7352 }, 7353 }, 7354 { 7355 name: "XADDQlock", 7356 auxType: auxSymOff, 7357 argLen: 3, 7358 resultInArg0: true, 7359 clobberFlags: true, 7360 faultOnNilArg1: true, 7361 asm: x86.AXADDQ, 7362 reg: regInfo{ 7363 inputs: []inputInfo{ 7364 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7365 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7366 }, 7367 outputs: []outputInfo{ 7368 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7369 }, 7370 }, 7371 }, 7372 { 7373 name: "AddTupleFirst32", 7374 argLen: 2, 7375 reg: regInfo{}, 7376 }, 7377 { 7378 name: "AddTupleFirst64", 7379 argLen: 2, 7380 reg: regInfo{}, 7381 }, 7382 { 7383 name: "CMPXCHGLlock", 7384 auxType: auxSymOff, 7385 argLen: 4, 7386 clobberFlags: true, 7387 faultOnNilArg0: true, 7388 asm: x86.ACMPXCHGL, 7389 reg: regInfo{ 7390 inputs: []inputInfo{ 7391 {1, 1}, // AX 7392 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7393 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7394 }, 7395 clobbers: 1, // AX 7396 outputs: []outputInfo{ 7397 {1, 0}, 7398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7399 }, 7400 }, 7401 }, 7402 { 7403 name: "CMPXCHGQlock", 7404 auxType: auxSymOff, 7405 argLen: 4, 7406 clobberFlags: true, 7407 faultOnNilArg0: true, 7408 asm: x86.ACMPXCHGQ, 7409 reg: regInfo{ 7410 inputs: []inputInfo{ 7411 {1, 1}, // AX 7412 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7413 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7414 }, 7415 clobbers: 1, // AX 7416 outputs: []outputInfo{ 7417 {1, 0}, 7418 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7419 }, 7420 }, 7421 }, 7422 { 7423 name: "ANDBlock", 7424 auxType: auxSymOff, 7425 argLen: 3, 7426 clobberFlags: true, 7427 faultOnNilArg0: true, 7428 asm: x86.AANDB, 7429 reg: regInfo{ 7430 inputs: []inputInfo{ 7431 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7432 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7433 }, 7434 }, 7435 }, 7436 { 7437 name: "ORBlock", 7438 auxType: auxSymOff, 7439 argLen: 3, 7440 clobberFlags: true, 7441 faultOnNilArg0: true, 7442 asm: x86.AORB, 7443 reg: regInfo{ 7444 inputs: []inputInfo{ 7445 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7446 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7447 }, 7448 }, 7449 }, 7450 7451 { 7452 name: "ADD", 7453 argLen: 2, 7454 commutative: true, 7455 asm: arm.AADD, 7456 reg: regInfo{ 7457 inputs: []inputInfo{ 7458 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7459 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7460 }, 7461 outputs: []outputInfo{ 7462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7463 }, 7464 }, 7465 }, 7466 { 7467 name: "ADDconst", 7468 auxType: auxInt32, 7469 argLen: 1, 7470 asm: arm.AADD, 7471 reg: regInfo{ 7472 inputs: []inputInfo{ 7473 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 7474 }, 7475 outputs: []outputInfo{ 7476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7477 }, 7478 }, 7479 }, 7480 { 7481 name: "SUB", 7482 argLen: 2, 7483 asm: arm.ASUB, 7484 reg: regInfo{ 7485 inputs: []inputInfo{ 7486 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7487 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7488 }, 7489 outputs: []outputInfo{ 7490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7491 }, 7492 }, 7493 }, 7494 { 7495 name: "SUBconst", 7496 auxType: auxInt32, 7497 argLen: 1, 7498 asm: arm.ASUB, 7499 reg: regInfo{ 7500 inputs: []inputInfo{ 7501 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7502 }, 7503 outputs: []outputInfo{ 7504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7505 }, 7506 }, 7507 }, 7508 { 7509 name: "RSB", 7510 argLen: 2, 7511 asm: arm.ARSB, 7512 reg: regInfo{ 7513 inputs: []inputInfo{ 7514 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7515 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7516 }, 7517 outputs: []outputInfo{ 7518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7519 }, 7520 }, 7521 }, 7522 { 7523 name: "RSBconst", 7524 auxType: auxInt32, 7525 argLen: 1, 7526 asm: arm.ARSB, 7527 reg: regInfo{ 7528 inputs: []inputInfo{ 7529 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7530 }, 7531 outputs: []outputInfo{ 7532 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7533 }, 7534 }, 7535 }, 7536 { 7537 name: "MUL", 7538 argLen: 2, 7539 commutative: true, 7540 asm: arm.AMUL, 7541 reg: regInfo{ 7542 inputs: []inputInfo{ 7543 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7544 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7545 }, 7546 outputs: []outputInfo{ 7547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7548 }, 7549 }, 7550 }, 7551 { 7552 name: "HMUL", 7553 argLen: 2, 7554 commutative: true, 7555 asm: arm.AMULL, 7556 reg: regInfo{ 7557 inputs: []inputInfo{ 7558 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7559 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7560 }, 7561 outputs: []outputInfo{ 7562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7563 }, 7564 }, 7565 }, 7566 { 7567 name: "HMULU", 7568 argLen: 2, 7569 commutative: true, 7570 asm: arm.AMULLU, 7571 reg: regInfo{ 7572 inputs: []inputInfo{ 7573 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7574 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7575 }, 7576 outputs: []outputInfo{ 7577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7578 }, 7579 }, 7580 }, 7581 { 7582 name: "UDIVrtcall", 7583 argLen: 2, 7584 clobberFlags: true, 7585 reg: regInfo{ 7586 inputs: []inputInfo{ 7587 {0, 2}, // R1 7588 {1, 1}, // R0 7589 }, 7590 clobbers: 16396, // R2 R3 R14 7591 outputs: []outputInfo{ 7592 {0, 1}, // R0 7593 {1, 2}, // R1 7594 }, 7595 }, 7596 }, 7597 { 7598 name: "ADDS", 7599 argLen: 2, 7600 commutative: true, 7601 asm: arm.AADD, 7602 reg: regInfo{ 7603 inputs: []inputInfo{ 7604 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7605 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7606 }, 7607 outputs: []outputInfo{ 7608 {1, 0}, 7609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7610 }, 7611 }, 7612 }, 7613 { 7614 name: "ADDSconst", 7615 auxType: auxInt32, 7616 argLen: 1, 7617 asm: arm.AADD, 7618 reg: regInfo{ 7619 inputs: []inputInfo{ 7620 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7621 }, 7622 outputs: []outputInfo{ 7623 {1, 0}, 7624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7625 }, 7626 }, 7627 }, 7628 { 7629 name: "ADC", 7630 argLen: 3, 7631 commutative: true, 7632 asm: arm.AADC, 7633 reg: regInfo{ 7634 inputs: []inputInfo{ 7635 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7636 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7637 }, 7638 outputs: []outputInfo{ 7639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7640 }, 7641 }, 7642 }, 7643 { 7644 name: "ADCconst", 7645 auxType: auxInt32, 7646 argLen: 2, 7647 asm: arm.AADC, 7648 reg: regInfo{ 7649 inputs: []inputInfo{ 7650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7651 }, 7652 outputs: []outputInfo{ 7653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7654 }, 7655 }, 7656 }, 7657 { 7658 name: "SUBS", 7659 argLen: 2, 7660 asm: arm.ASUB, 7661 reg: regInfo{ 7662 inputs: []inputInfo{ 7663 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7664 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7665 }, 7666 outputs: []outputInfo{ 7667 {1, 0}, 7668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7669 }, 7670 }, 7671 }, 7672 { 7673 name: "SUBSconst", 7674 auxType: auxInt32, 7675 argLen: 1, 7676 asm: arm.ASUB, 7677 reg: regInfo{ 7678 inputs: []inputInfo{ 7679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7680 }, 7681 outputs: []outputInfo{ 7682 {1, 0}, 7683 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7684 }, 7685 }, 7686 }, 7687 { 7688 name: "RSBSconst", 7689 auxType: auxInt32, 7690 argLen: 1, 7691 asm: arm.ARSB, 7692 reg: regInfo{ 7693 inputs: []inputInfo{ 7694 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7695 }, 7696 outputs: []outputInfo{ 7697 {1, 0}, 7698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7699 }, 7700 }, 7701 }, 7702 { 7703 name: "SBC", 7704 argLen: 3, 7705 asm: arm.ASBC, 7706 reg: regInfo{ 7707 inputs: []inputInfo{ 7708 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7709 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7710 }, 7711 outputs: []outputInfo{ 7712 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7713 }, 7714 }, 7715 }, 7716 { 7717 name: "SBCconst", 7718 auxType: auxInt32, 7719 argLen: 2, 7720 asm: arm.ASBC, 7721 reg: regInfo{ 7722 inputs: []inputInfo{ 7723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7724 }, 7725 outputs: []outputInfo{ 7726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7727 }, 7728 }, 7729 }, 7730 { 7731 name: "RSCconst", 7732 auxType: auxInt32, 7733 argLen: 2, 7734 asm: arm.ARSC, 7735 reg: regInfo{ 7736 inputs: []inputInfo{ 7737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7738 }, 7739 outputs: []outputInfo{ 7740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7741 }, 7742 }, 7743 }, 7744 { 7745 name: "MULLU", 7746 argLen: 2, 7747 commutative: true, 7748 asm: arm.AMULLU, 7749 reg: regInfo{ 7750 inputs: []inputInfo{ 7751 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7752 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7753 }, 7754 outputs: []outputInfo{ 7755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7756 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7757 }, 7758 }, 7759 }, 7760 { 7761 name: "MULA", 7762 argLen: 3, 7763 asm: arm.AMULA, 7764 reg: regInfo{ 7765 inputs: []inputInfo{ 7766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7767 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7768 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7769 }, 7770 outputs: []outputInfo{ 7771 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7772 }, 7773 }, 7774 }, 7775 { 7776 name: "ADDF", 7777 argLen: 2, 7778 commutative: true, 7779 asm: arm.AADDF, 7780 reg: regInfo{ 7781 inputs: []inputInfo{ 7782 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7783 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7784 }, 7785 outputs: []outputInfo{ 7786 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7787 }, 7788 }, 7789 }, 7790 { 7791 name: "ADDD", 7792 argLen: 2, 7793 commutative: true, 7794 asm: arm.AADDD, 7795 reg: regInfo{ 7796 inputs: []inputInfo{ 7797 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7798 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7799 }, 7800 outputs: []outputInfo{ 7801 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7802 }, 7803 }, 7804 }, 7805 { 7806 name: "SUBF", 7807 argLen: 2, 7808 asm: arm.ASUBF, 7809 reg: regInfo{ 7810 inputs: []inputInfo{ 7811 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7812 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7813 }, 7814 outputs: []outputInfo{ 7815 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7816 }, 7817 }, 7818 }, 7819 { 7820 name: "SUBD", 7821 argLen: 2, 7822 asm: arm.ASUBD, 7823 reg: regInfo{ 7824 inputs: []inputInfo{ 7825 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7826 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7827 }, 7828 outputs: []outputInfo{ 7829 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7830 }, 7831 }, 7832 }, 7833 { 7834 name: "MULF", 7835 argLen: 2, 7836 commutative: true, 7837 asm: arm.AMULF, 7838 reg: regInfo{ 7839 inputs: []inputInfo{ 7840 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7841 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7842 }, 7843 outputs: []outputInfo{ 7844 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7845 }, 7846 }, 7847 }, 7848 { 7849 name: "MULD", 7850 argLen: 2, 7851 commutative: true, 7852 asm: arm.AMULD, 7853 reg: regInfo{ 7854 inputs: []inputInfo{ 7855 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7856 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7857 }, 7858 outputs: []outputInfo{ 7859 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7860 }, 7861 }, 7862 }, 7863 { 7864 name: "DIVF", 7865 argLen: 2, 7866 asm: arm.ADIVF, 7867 reg: regInfo{ 7868 inputs: []inputInfo{ 7869 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7870 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7871 }, 7872 outputs: []outputInfo{ 7873 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7874 }, 7875 }, 7876 }, 7877 { 7878 name: "DIVD", 7879 argLen: 2, 7880 asm: arm.ADIVD, 7881 reg: regInfo{ 7882 inputs: []inputInfo{ 7883 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7884 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7885 }, 7886 outputs: []outputInfo{ 7887 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7888 }, 7889 }, 7890 }, 7891 { 7892 name: "AND", 7893 argLen: 2, 7894 commutative: true, 7895 asm: arm.AAND, 7896 reg: regInfo{ 7897 inputs: []inputInfo{ 7898 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7899 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7900 }, 7901 outputs: []outputInfo{ 7902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7903 }, 7904 }, 7905 }, 7906 { 7907 name: "ANDconst", 7908 auxType: auxInt32, 7909 argLen: 1, 7910 asm: arm.AAND, 7911 reg: regInfo{ 7912 inputs: []inputInfo{ 7913 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7914 }, 7915 outputs: []outputInfo{ 7916 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7917 }, 7918 }, 7919 }, 7920 { 7921 name: "OR", 7922 argLen: 2, 7923 commutative: true, 7924 asm: arm.AORR, 7925 reg: regInfo{ 7926 inputs: []inputInfo{ 7927 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7928 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7929 }, 7930 outputs: []outputInfo{ 7931 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7932 }, 7933 }, 7934 }, 7935 { 7936 name: "ORconst", 7937 auxType: auxInt32, 7938 argLen: 1, 7939 asm: arm.AORR, 7940 reg: regInfo{ 7941 inputs: []inputInfo{ 7942 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7943 }, 7944 outputs: []outputInfo{ 7945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7946 }, 7947 }, 7948 }, 7949 { 7950 name: "XOR", 7951 argLen: 2, 7952 commutative: true, 7953 asm: arm.AEOR, 7954 reg: regInfo{ 7955 inputs: []inputInfo{ 7956 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7957 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7958 }, 7959 outputs: []outputInfo{ 7960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7961 }, 7962 }, 7963 }, 7964 { 7965 name: "XORconst", 7966 auxType: auxInt32, 7967 argLen: 1, 7968 asm: arm.AEOR, 7969 reg: regInfo{ 7970 inputs: []inputInfo{ 7971 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7972 }, 7973 outputs: []outputInfo{ 7974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7975 }, 7976 }, 7977 }, 7978 { 7979 name: "BIC", 7980 argLen: 2, 7981 asm: arm.ABIC, 7982 reg: regInfo{ 7983 inputs: []inputInfo{ 7984 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7985 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 7986 }, 7987 outputs: []outputInfo{ 7988 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 7989 }, 7990 }, 7991 }, 7992 { 7993 name: "BICconst", 7994 auxType: auxInt32, 7995 argLen: 1, 7996 asm: arm.ABIC, 7997 reg: regInfo{ 7998 inputs: []inputInfo{ 7999 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8000 }, 8001 outputs: []outputInfo{ 8002 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8003 }, 8004 }, 8005 }, 8006 { 8007 name: "MVN", 8008 argLen: 1, 8009 asm: arm.AMVN, 8010 reg: regInfo{ 8011 inputs: []inputInfo{ 8012 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8013 }, 8014 outputs: []outputInfo{ 8015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8016 }, 8017 }, 8018 }, 8019 { 8020 name: "NEGF", 8021 argLen: 1, 8022 asm: arm.ANEGF, 8023 reg: regInfo{ 8024 inputs: []inputInfo{ 8025 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8026 }, 8027 outputs: []outputInfo{ 8028 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8029 }, 8030 }, 8031 }, 8032 { 8033 name: "NEGD", 8034 argLen: 1, 8035 asm: arm.ANEGD, 8036 reg: regInfo{ 8037 inputs: []inputInfo{ 8038 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8039 }, 8040 outputs: []outputInfo{ 8041 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8042 }, 8043 }, 8044 }, 8045 { 8046 name: "SQRTD", 8047 argLen: 1, 8048 asm: arm.ASQRTD, 8049 reg: regInfo{ 8050 inputs: []inputInfo{ 8051 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8052 }, 8053 outputs: []outputInfo{ 8054 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8055 }, 8056 }, 8057 }, 8058 { 8059 name: "CLZ", 8060 argLen: 1, 8061 asm: arm.ACLZ, 8062 reg: regInfo{ 8063 inputs: []inputInfo{ 8064 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8065 }, 8066 outputs: []outputInfo{ 8067 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8068 }, 8069 }, 8070 }, 8071 { 8072 name: "SLL", 8073 argLen: 2, 8074 asm: arm.ASLL, 8075 reg: regInfo{ 8076 inputs: []inputInfo{ 8077 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8078 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8079 }, 8080 outputs: []outputInfo{ 8081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8082 }, 8083 }, 8084 }, 8085 { 8086 name: "SLLconst", 8087 auxType: auxInt32, 8088 argLen: 1, 8089 asm: arm.ASLL, 8090 reg: regInfo{ 8091 inputs: []inputInfo{ 8092 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8093 }, 8094 outputs: []outputInfo{ 8095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8096 }, 8097 }, 8098 }, 8099 { 8100 name: "SRL", 8101 argLen: 2, 8102 asm: arm.ASRL, 8103 reg: regInfo{ 8104 inputs: []inputInfo{ 8105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8106 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8107 }, 8108 outputs: []outputInfo{ 8109 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8110 }, 8111 }, 8112 }, 8113 { 8114 name: "SRLconst", 8115 auxType: auxInt32, 8116 argLen: 1, 8117 asm: arm.ASRL, 8118 reg: regInfo{ 8119 inputs: []inputInfo{ 8120 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8121 }, 8122 outputs: []outputInfo{ 8123 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8124 }, 8125 }, 8126 }, 8127 { 8128 name: "SRA", 8129 argLen: 2, 8130 asm: arm.ASRA, 8131 reg: regInfo{ 8132 inputs: []inputInfo{ 8133 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8134 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8135 }, 8136 outputs: []outputInfo{ 8137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8138 }, 8139 }, 8140 }, 8141 { 8142 name: "SRAconst", 8143 auxType: auxInt32, 8144 argLen: 1, 8145 asm: arm.ASRA, 8146 reg: regInfo{ 8147 inputs: []inputInfo{ 8148 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8149 }, 8150 outputs: []outputInfo{ 8151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8152 }, 8153 }, 8154 }, 8155 { 8156 name: "SRRconst", 8157 auxType: auxInt32, 8158 argLen: 1, 8159 reg: regInfo{ 8160 inputs: []inputInfo{ 8161 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8162 }, 8163 outputs: []outputInfo{ 8164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8165 }, 8166 }, 8167 }, 8168 { 8169 name: "ADDshiftLL", 8170 auxType: auxInt32, 8171 argLen: 2, 8172 asm: arm.AADD, 8173 reg: regInfo{ 8174 inputs: []inputInfo{ 8175 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8176 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8177 }, 8178 outputs: []outputInfo{ 8179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8180 }, 8181 }, 8182 }, 8183 { 8184 name: "ADDshiftRL", 8185 auxType: auxInt32, 8186 argLen: 2, 8187 asm: arm.AADD, 8188 reg: regInfo{ 8189 inputs: []inputInfo{ 8190 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8191 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8192 }, 8193 outputs: []outputInfo{ 8194 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8195 }, 8196 }, 8197 }, 8198 { 8199 name: "ADDshiftRA", 8200 auxType: auxInt32, 8201 argLen: 2, 8202 asm: arm.AADD, 8203 reg: regInfo{ 8204 inputs: []inputInfo{ 8205 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8206 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8207 }, 8208 outputs: []outputInfo{ 8209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8210 }, 8211 }, 8212 }, 8213 { 8214 name: "SUBshiftLL", 8215 auxType: auxInt32, 8216 argLen: 2, 8217 asm: arm.ASUB, 8218 reg: regInfo{ 8219 inputs: []inputInfo{ 8220 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8221 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8222 }, 8223 outputs: []outputInfo{ 8224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8225 }, 8226 }, 8227 }, 8228 { 8229 name: "SUBshiftRL", 8230 auxType: auxInt32, 8231 argLen: 2, 8232 asm: arm.ASUB, 8233 reg: regInfo{ 8234 inputs: []inputInfo{ 8235 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8236 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8237 }, 8238 outputs: []outputInfo{ 8239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8240 }, 8241 }, 8242 }, 8243 { 8244 name: "SUBshiftRA", 8245 auxType: auxInt32, 8246 argLen: 2, 8247 asm: arm.ASUB, 8248 reg: regInfo{ 8249 inputs: []inputInfo{ 8250 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8251 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8252 }, 8253 outputs: []outputInfo{ 8254 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8255 }, 8256 }, 8257 }, 8258 { 8259 name: "RSBshiftLL", 8260 auxType: auxInt32, 8261 argLen: 2, 8262 asm: arm.ARSB, 8263 reg: regInfo{ 8264 inputs: []inputInfo{ 8265 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8266 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8267 }, 8268 outputs: []outputInfo{ 8269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8270 }, 8271 }, 8272 }, 8273 { 8274 name: "RSBshiftRL", 8275 auxType: auxInt32, 8276 argLen: 2, 8277 asm: arm.ARSB, 8278 reg: regInfo{ 8279 inputs: []inputInfo{ 8280 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8281 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8282 }, 8283 outputs: []outputInfo{ 8284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8285 }, 8286 }, 8287 }, 8288 { 8289 name: "RSBshiftRA", 8290 auxType: auxInt32, 8291 argLen: 2, 8292 asm: arm.ARSB, 8293 reg: regInfo{ 8294 inputs: []inputInfo{ 8295 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8296 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8297 }, 8298 outputs: []outputInfo{ 8299 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8300 }, 8301 }, 8302 }, 8303 { 8304 name: "ANDshiftLL", 8305 auxType: auxInt32, 8306 argLen: 2, 8307 asm: arm.AAND, 8308 reg: regInfo{ 8309 inputs: []inputInfo{ 8310 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8311 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8312 }, 8313 outputs: []outputInfo{ 8314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8315 }, 8316 }, 8317 }, 8318 { 8319 name: "ANDshiftRL", 8320 auxType: auxInt32, 8321 argLen: 2, 8322 asm: arm.AAND, 8323 reg: regInfo{ 8324 inputs: []inputInfo{ 8325 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8326 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8327 }, 8328 outputs: []outputInfo{ 8329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8330 }, 8331 }, 8332 }, 8333 { 8334 name: "ANDshiftRA", 8335 auxType: auxInt32, 8336 argLen: 2, 8337 asm: arm.AAND, 8338 reg: regInfo{ 8339 inputs: []inputInfo{ 8340 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8341 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8342 }, 8343 outputs: []outputInfo{ 8344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8345 }, 8346 }, 8347 }, 8348 { 8349 name: "ORshiftLL", 8350 auxType: auxInt32, 8351 argLen: 2, 8352 asm: arm.AORR, 8353 reg: regInfo{ 8354 inputs: []inputInfo{ 8355 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8356 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8357 }, 8358 outputs: []outputInfo{ 8359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8360 }, 8361 }, 8362 }, 8363 { 8364 name: "ORshiftRL", 8365 auxType: auxInt32, 8366 argLen: 2, 8367 asm: arm.AORR, 8368 reg: regInfo{ 8369 inputs: []inputInfo{ 8370 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8371 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8372 }, 8373 outputs: []outputInfo{ 8374 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8375 }, 8376 }, 8377 }, 8378 { 8379 name: "ORshiftRA", 8380 auxType: auxInt32, 8381 argLen: 2, 8382 asm: arm.AORR, 8383 reg: regInfo{ 8384 inputs: []inputInfo{ 8385 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8386 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8387 }, 8388 outputs: []outputInfo{ 8389 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8390 }, 8391 }, 8392 }, 8393 { 8394 name: "XORshiftLL", 8395 auxType: auxInt32, 8396 argLen: 2, 8397 asm: arm.AEOR, 8398 reg: regInfo{ 8399 inputs: []inputInfo{ 8400 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8401 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8402 }, 8403 outputs: []outputInfo{ 8404 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8405 }, 8406 }, 8407 }, 8408 { 8409 name: "XORshiftRL", 8410 auxType: auxInt32, 8411 argLen: 2, 8412 asm: arm.AEOR, 8413 reg: regInfo{ 8414 inputs: []inputInfo{ 8415 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8416 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8417 }, 8418 outputs: []outputInfo{ 8419 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8420 }, 8421 }, 8422 }, 8423 { 8424 name: "XORshiftRA", 8425 auxType: auxInt32, 8426 argLen: 2, 8427 asm: arm.AEOR, 8428 reg: regInfo{ 8429 inputs: []inputInfo{ 8430 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8431 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8432 }, 8433 outputs: []outputInfo{ 8434 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8435 }, 8436 }, 8437 }, 8438 { 8439 name: "XORshiftRR", 8440 auxType: auxInt32, 8441 argLen: 2, 8442 asm: arm.AEOR, 8443 reg: regInfo{ 8444 inputs: []inputInfo{ 8445 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8446 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8447 }, 8448 outputs: []outputInfo{ 8449 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8450 }, 8451 }, 8452 }, 8453 { 8454 name: "BICshiftLL", 8455 auxType: auxInt32, 8456 argLen: 2, 8457 asm: arm.ABIC, 8458 reg: regInfo{ 8459 inputs: []inputInfo{ 8460 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8461 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8462 }, 8463 outputs: []outputInfo{ 8464 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8465 }, 8466 }, 8467 }, 8468 { 8469 name: "BICshiftRL", 8470 auxType: auxInt32, 8471 argLen: 2, 8472 asm: arm.ABIC, 8473 reg: regInfo{ 8474 inputs: []inputInfo{ 8475 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8476 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8477 }, 8478 outputs: []outputInfo{ 8479 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8480 }, 8481 }, 8482 }, 8483 { 8484 name: "BICshiftRA", 8485 auxType: auxInt32, 8486 argLen: 2, 8487 asm: arm.ABIC, 8488 reg: regInfo{ 8489 inputs: []inputInfo{ 8490 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8491 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8492 }, 8493 outputs: []outputInfo{ 8494 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8495 }, 8496 }, 8497 }, 8498 { 8499 name: "MVNshiftLL", 8500 auxType: auxInt32, 8501 argLen: 1, 8502 asm: arm.AMVN, 8503 reg: regInfo{ 8504 inputs: []inputInfo{ 8505 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8506 }, 8507 outputs: []outputInfo{ 8508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8509 }, 8510 }, 8511 }, 8512 { 8513 name: "MVNshiftRL", 8514 auxType: auxInt32, 8515 argLen: 1, 8516 asm: arm.AMVN, 8517 reg: regInfo{ 8518 inputs: []inputInfo{ 8519 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8520 }, 8521 outputs: []outputInfo{ 8522 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8523 }, 8524 }, 8525 }, 8526 { 8527 name: "MVNshiftRA", 8528 auxType: auxInt32, 8529 argLen: 1, 8530 asm: arm.AMVN, 8531 reg: regInfo{ 8532 inputs: []inputInfo{ 8533 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8534 }, 8535 outputs: []outputInfo{ 8536 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8537 }, 8538 }, 8539 }, 8540 { 8541 name: "ADCshiftLL", 8542 auxType: auxInt32, 8543 argLen: 3, 8544 asm: arm.AADC, 8545 reg: regInfo{ 8546 inputs: []inputInfo{ 8547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8548 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8549 }, 8550 outputs: []outputInfo{ 8551 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8552 }, 8553 }, 8554 }, 8555 { 8556 name: "ADCshiftRL", 8557 auxType: auxInt32, 8558 argLen: 3, 8559 asm: arm.AADC, 8560 reg: regInfo{ 8561 inputs: []inputInfo{ 8562 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8563 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8564 }, 8565 outputs: []outputInfo{ 8566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8567 }, 8568 }, 8569 }, 8570 { 8571 name: "ADCshiftRA", 8572 auxType: auxInt32, 8573 argLen: 3, 8574 asm: arm.AADC, 8575 reg: regInfo{ 8576 inputs: []inputInfo{ 8577 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8578 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8579 }, 8580 outputs: []outputInfo{ 8581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8582 }, 8583 }, 8584 }, 8585 { 8586 name: "SBCshiftLL", 8587 auxType: auxInt32, 8588 argLen: 3, 8589 asm: arm.ASBC, 8590 reg: regInfo{ 8591 inputs: []inputInfo{ 8592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8593 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8594 }, 8595 outputs: []outputInfo{ 8596 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8597 }, 8598 }, 8599 }, 8600 { 8601 name: "SBCshiftRL", 8602 auxType: auxInt32, 8603 argLen: 3, 8604 asm: arm.ASBC, 8605 reg: regInfo{ 8606 inputs: []inputInfo{ 8607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8608 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8609 }, 8610 outputs: []outputInfo{ 8611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8612 }, 8613 }, 8614 }, 8615 { 8616 name: "SBCshiftRA", 8617 auxType: auxInt32, 8618 argLen: 3, 8619 asm: arm.ASBC, 8620 reg: regInfo{ 8621 inputs: []inputInfo{ 8622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8623 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8624 }, 8625 outputs: []outputInfo{ 8626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8627 }, 8628 }, 8629 }, 8630 { 8631 name: "RSCshiftLL", 8632 auxType: auxInt32, 8633 argLen: 3, 8634 asm: arm.ARSC, 8635 reg: regInfo{ 8636 inputs: []inputInfo{ 8637 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8638 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8639 }, 8640 outputs: []outputInfo{ 8641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8642 }, 8643 }, 8644 }, 8645 { 8646 name: "RSCshiftRL", 8647 auxType: auxInt32, 8648 argLen: 3, 8649 asm: arm.ARSC, 8650 reg: regInfo{ 8651 inputs: []inputInfo{ 8652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8653 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8654 }, 8655 outputs: []outputInfo{ 8656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8657 }, 8658 }, 8659 }, 8660 { 8661 name: "RSCshiftRA", 8662 auxType: auxInt32, 8663 argLen: 3, 8664 asm: arm.ARSC, 8665 reg: regInfo{ 8666 inputs: []inputInfo{ 8667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8668 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8669 }, 8670 outputs: []outputInfo{ 8671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8672 }, 8673 }, 8674 }, 8675 { 8676 name: "ADDSshiftLL", 8677 auxType: auxInt32, 8678 argLen: 2, 8679 asm: arm.AADD, 8680 reg: regInfo{ 8681 inputs: []inputInfo{ 8682 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8683 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8684 }, 8685 outputs: []outputInfo{ 8686 {1, 0}, 8687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8688 }, 8689 }, 8690 }, 8691 { 8692 name: "ADDSshiftRL", 8693 auxType: auxInt32, 8694 argLen: 2, 8695 asm: arm.AADD, 8696 reg: regInfo{ 8697 inputs: []inputInfo{ 8698 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8699 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8700 }, 8701 outputs: []outputInfo{ 8702 {1, 0}, 8703 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8704 }, 8705 }, 8706 }, 8707 { 8708 name: "ADDSshiftRA", 8709 auxType: auxInt32, 8710 argLen: 2, 8711 asm: arm.AADD, 8712 reg: regInfo{ 8713 inputs: []inputInfo{ 8714 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8715 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8716 }, 8717 outputs: []outputInfo{ 8718 {1, 0}, 8719 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8720 }, 8721 }, 8722 }, 8723 { 8724 name: "SUBSshiftLL", 8725 auxType: auxInt32, 8726 argLen: 2, 8727 asm: arm.ASUB, 8728 reg: regInfo{ 8729 inputs: []inputInfo{ 8730 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8731 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8732 }, 8733 outputs: []outputInfo{ 8734 {1, 0}, 8735 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8736 }, 8737 }, 8738 }, 8739 { 8740 name: "SUBSshiftRL", 8741 auxType: auxInt32, 8742 argLen: 2, 8743 asm: arm.ASUB, 8744 reg: regInfo{ 8745 inputs: []inputInfo{ 8746 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8747 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8748 }, 8749 outputs: []outputInfo{ 8750 {1, 0}, 8751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8752 }, 8753 }, 8754 }, 8755 { 8756 name: "SUBSshiftRA", 8757 auxType: auxInt32, 8758 argLen: 2, 8759 asm: arm.ASUB, 8760 reg: regInfo{ 8761 inputs: []inputInfo{ 8762 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8763 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8764 }, 8765 outputs: []outputInfo{ 8766 {1, 0}, 8767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8768 }, 8769 }, 8770 }, 8771 { 8772 name: "RSBSshiftLL", 8773 auxType: auxInt32, 8774 argLen: 2, 8775 asm: arm.ARSB, 8776 reg: regInfo{ 8777 inputs: []inputInfo{ 8778 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8779 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8780 }, 8781 outputs: []outputInfo{ 8782 {1, 0}, 8783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8784 }, 8785 }, 8786 }, 8787 { 8788 name: "RSBSshiftRL", 8789 auxType: auxInt32, 8790 argLen: 2, 8791 asm: arm.ARSB, 8792 reg: regInfo{ 8793 inputs: []inputInfo{ 8794 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8795 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8796 }, 8797 outputs: []outputInfo{ 8798 {1, 0}, 8799 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8800 }, 8801 }, 8802 }, 8803 { 8804 name: "RSBSshiftRA", 8805 auxType: auxInt32, 8806 argLen: 2, 8807 asm: arm.ARSB, 8808 reg: regInfo{ 8809 inputs: []inputInfo{ 8810 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8811 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8812 }, 8813 outputs: []outputInfo{ 8814 {1, 0}, 8815 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8816 }, 8817 }, 8818 }, 8819 { 8820 name: "ADDshiftLLreg", 8821 argLen: 3, 8822 asm: arm.AADD, 8823 reg: regInfo{ 8824 inputs: []inputInfo{ 8825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8826 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8827 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8828 }, 8829 outputs: []outputInfo{ 8830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8831 }, 8832 }, 8833 }, 8834 { 8835 name: "ADDshiftRLreg", 8836 argLen: 3, 8837 asm: arm.AADD, 8838 reg: regInfo{ 8839 inputs: []inputInfo{ 8840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8841 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8842 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8843 }, 8844 outputs: []outputInfo{ 8845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8846 }, 8847 }, 8848 }, 8849 { 8850 name: "ADDshiftRAreg", 8851 argLen: 3, 8852 asm: arm.AADD, 8853 reg: regInfo{ 8854 inputs: []inputInfo{ 8855 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8856 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8857 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8858 }, 8859 outputs: []outputInfo{ 8860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8861 }, 8862 }, 8863 }, 8864 { 8865 name: "SUBshiftLLreg", 8866 argLen: 3, 8867 asm: arm.ASUB, 8868 reg: regInfo{ 8869 inputs: []inputInfo{ 8870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8871 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8872 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8873 }, 8874 outputs: []outputInfo{ 8875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8876 }, 8877 }, 8878 }, 8879 { 8880 name: "SUBshiftRLreg", 8881 argLen: 3, 8882 asm: arm.ASUB, 8883 reg: regInfo{ 8884 inputs: []inputInfo{ 8885 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8886 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8887 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8888 }, 8889 outputs: []outputInfo{ 8890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8891 }, 8892 }, 8893 }, 8894 { 8895 name: "SUBshiftRAreg", 8896 argLen: 3, 8897 asm: arm.ASUB, 8898 reg: regInfo{ 8899 inputs: []inputInfo{ 8900 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8901 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8902 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8903 }, 8904 outputs: []outputInfo{ 8905 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8906 }, 8907 }, 8908 }, 8909 { 8910 name: "RSBshiftLLreg", 8911 argLen: 3, 8912 asm: arm.ARSB, 8913 reg: regInfo{ 8914 inputs: []inputInfo{ 8915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8916 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8917 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8918 }, 8919 outputs: []outputInfo{ 8920 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8921 }, 8922 }, 8923 }, 8924 { 8925 name: "RSBshiftRLreg", 8926 argLen: 3, 8927 asm: arm.ARSB, 8928 reg: regInfo{ 8929 inputs: []inputInfo{ 8930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8931 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8932 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8933 }, 8934 outputs: []outputInfo{ 8935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8936 }, 8937 }, 8938 }, 8939 { 8940 name: "RSBshiftRAreg", 8941 argLen: 3, 8942 asm: arm.ARSB, 8943 reg: regInfo{ 8944 inputs: []inputInfo{ 8945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8946 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8947 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8948 }, 8949 outputs: []outputInfo{ 8950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8951 }, 8952 }, 8953 }, 8954 { 8955 name: "ANDshiftLLreg", 8956 argLen: 3, 8957 asm: arm.AAND, 8958 reg: regInfo{ 8959 inputs: []inputInfo{ 8960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8961 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8962 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8963 }, 8964 outputs: []outputInfo{ 8965 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8966 }, 8967 }, 8968 }, 8969 { 8970 name: "ANDshiftRLreg", 8971 argLen: 3, 8972 asm: arm.AAND, 8973 reg: regInfo{ 8974 inputs: []inputInfo{ 8975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8976 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8977 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8978 }, 8979 outputs: []outputInfo{ 8980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8981 }, 8982 }, 8983 }, 8984 { 8985 name: "ANDshiftRAreg", 8986 argLen: 3, 8987 asm: arm.AAND, 8988 reg: regInfo{ 8989 inputs: []inputInfo{ 8990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8991 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8992 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8993 }, 8994 outputs: []outputInfo{ 8995 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8996 }, 8997 }, 8998 }, 8999 { 9000 name: "ORshiftLLreg", 9001 argLen: 3, 9002 asm: arm.AORR, 9003 reg: regInfo{ 9004 inputs: []inputInfo{ 9005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9006 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9007 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9008 }, 9009 outputs: []outputInfo{ 9010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9011 }, 9012 }, 9013 }, 9014 { 9015 name: "ORshiftRLreg", 9016 argLen: 3, 9017 asm: arm.AORR, 9018 reg: regInfo{ 9019 inputs: []inputInfo{ 9020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9021 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9022 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9023 }, 9024 outputs: []outputInfo{ 9025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9026 }, 9027 }, 9028 }, 9029 { 9030 name: "ORshiftRAreg", 9031 argLen: 3, 9032 asm: arm.AORR, 9033 reg: regInfo{ 9034 inputs: []inputInfo{ 9035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9036 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9037 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9038 }, 9039 outputs: []outputInfo{ 9040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9041 }, 9042 }, 9043 }, 9044 { 9045 name: "XORshiftLLreg", 9046 argLen: 3, 9047 asm: arm.AEOR, 9048 reg: regInfo{ 9049 inputs: []inputInfo{ 9050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9051 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9052 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9053 }, 9054 outputs: []outputInfo{ 9055 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9056 }, 9057 }, 9058 }, 9059 { 9060 name: "XORshiftRLreg", 9061 argLen: 3, 9062 asm: arm.AEOR, 9063 reg: regInfo{ 9064 inputs: []inputInfo{ 9065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9066 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9067 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9068 }, 9069 outputs: []outputInfo{ 9070 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9071 }, 9072 }, 9073 }, 9074 { 9075 name: "XORshiftRAreg", 9076 argLen: 3, 9077 asm: arm.AEOR, 9078 reg: regInfo{ 9079 inputs: []inputInfo{ 9080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9081 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9082 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9083 }, 9084 outputs: []outputInfo{ 9085 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9086 }, 9087 }, 9088 }, 9089 { 9090 name: "BICshiftLLreg", 9091 argLen: 3, 9092 asm: arm.ABIC, 9093 reg: regInfo{ 9094 inputs: []inputInfo{ 9095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9096 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9097 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9098 }, 9099 outputs: []outputInfo{ 9100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9101 }, 9102 }, 9103 }, 9104 { 9105 name: "BICshiftRLreg", 9106 argLen: 3, 9107 asm: arm.ABIC, 9108 reg: regInfo{ 9109 inputs: []inputInfo{ 9110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9111 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9112 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9113 }, 9114 outputs: []outputInfo{ 9115 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9116 }, 9117 }, 9118 }, 9119 { 9120 name: "BICshiftRAreg", 9121 argLen: 3, 9122 asm: arm.ABIC, 9123 reg: regInfo{ 9124 inputs: []inputInfo{ 9125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9126 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9127 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9128 }, 9129 outputs: []outputInfo{ 9130 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9131 }, 9132 }, 9133 }, 9134 { 9135 name: "MVNshiftLLreg", 9136 argLen: 2, 9137 asm: arm.AMVN, 9138 reg: regInfo{ 9139 inputs: []inputInfo{ 9140 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9141 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9142 }, 9143 outputs: []outputInfo{ 9144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9145 }, 9146 }, 9147 }, 9148 { 9149 name: "MVNshiftRLreg", 9150 argLen: 2, 9151 asm: arm.AMVN, 9152 reg: regInfo{ 9153 inputs: []inputInfo{ 9154 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9155 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9156 }, 9157 outputs: []outputInfo{ 9158 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9159 }, 9160 }, 9161 }, 9162 { 9163 name: "MVNshiftRAreg", 9164 argLen: 2, 9165 asm: arm.AMVN, 9166 reg: regInfo{ 9167 inputs: []inputInfo{ 9168 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9169 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9170 }, 9171 outputs: []outputInfo{ 9172 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9173 }, 9174 }, 9175 }, 9176 { 9177 name: "ADCshiftLLreg", 9178 argLen: 4, 9179 asm: arm.AADC, 9180 reg: regInfo{ 9181 inputs: []inputInfo{ 9182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9183 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9184 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9185 }, 9186 outputs: []outputInfo{ 9187 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9188 }, 9189 }, 9190 }, 9191 { 9192 name: "ADCshiftRLreg", 9193 argLen: 4, 9194 asm: arm.AADC, 9195 reg: regInfo{ 9196 inputs: []inputInfo{ 9197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9198 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9199 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9200 }, 9201 outputs: []outputInfo{ 9202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9203 }, 9204 }, 9205 }, 9206 { 9207 name: "ADCshiftRAreg", 9208 argLen: 4, 9209 asm: arm.AADC, 9210 reg: regInfo{ 9211 inputs: []inputInfo{ 9212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9213 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9214 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9215 }, 9216 outputs: []outputInfo{ 9217 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9218 }, 9219 }, 9220 }, 9221 { 9222 name: "SBCshiftLLreg", 9223 argLen: 4, 9224 asm: arm.ASBC, 9225 reg: regInfo{ 9226 inputs: []inputInfo{ 9227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9228 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9229 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9230 }, 9231 outputs: []outputInfo{ 9232 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9233 }, 9234 }, 9235 }, 9236 { 9237 name: "SBCshiftRLreg", 9238 argLen: 4, 9239 asm: arm.ASBC, 9240 reg: regInfo{ 9241 inputs: []inputInfo{ 9242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9243 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9244 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9245 }, 9246 outputs: []outputInfo{ 9247 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9248 }, 9249 }, 9250 }, 9251 { 9252 name: "SBCshiftRAreg", 9253 argLen: 4, 9254 asm: arm.ASBC, 9255 reg: regInfo{ 9256 inputs: []inputInfo{ 9257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9258 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9259 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9260 }, 9261 outputs: []outputInfo{ 9262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9263 }, 9264 }, 9265 }, 9266 { 9267 name: "RSCshiftLLreg", 9268 argLen: 4, 9269 asm: arm.ARSC, 9270 reg: regInfo{ 9271 inputs: []inputInfo{ 9272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9273 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9274 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9275 }, 9276 outputs: []outputInfo{ 9277 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9278 }, 9279 }, 9280 }, 9281 { 9282 name: "RSCshiftRLreg", 9283 argLen: 4, 9284 asm: arm.ARSC, 9285 reg: regInfo{ 9286 inputs: []inputInfo{ 9287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9288 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9289 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9290 }, 9291 outputs: []outputInfo{ 9292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9293 }, 9294 }, 9295 }, 9296 { 9297 name: "RSCshiftRAreg", 9298 argLen: 4, 9299 asm: arm.ARSC, 9300 reg: regInfo{ 9301 inputs: []inputInfo{ 9302 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9303 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9304 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9305 }, 9306 outputs: []outputInfo{ 9307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9308 }, 9309 }, 9310 }, 9311 { 9312 name: "ADDSshiftLLreg", 9313 argLen: 3, 9314 asm: arm.AADD, 9315 reg: regInfo{ 9316 inputs: []inputInfo{ 9317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9318 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9319 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9320 }, 9321 outputs: []outputInfo{ 9322 {1, 0}, 9323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9324 }, 9325 }, 9326 }, 9327 { 9328 name: "ADDSshiftRLreg", 9329 argLen: 3, 9330 asm: arm.AADD, 9331 reg: regInfo{ 9332 inputs: []inputInfo{ 9333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9334 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9335 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9336 }, 9337 outputs: []outputInfo{ 9338 {1, 0}, 9339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9340 }, 9341 }, 9342 }, 9343 { 9344 name: "ADDSshiftRAreg", 9345 argLen: 3, 9346 asm: arm.AADD, 9347 reg: regInfo{ 9348 inputs: []inputInfo{ 9349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9350 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9351 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9352 }, 9353 outputs: []outputInfo{ 9354 {1, 0}, 9355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9356 }, 9357 }, 9358 }, 9359 { 9360 name: "SUBSshiftLLreg", 9361 argLen: 3, 9362 asm: arm.ASUB, 9363 reg: regInfo{ 9364 inputs: []inputInfo{ 9365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9366 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9367 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9368 }, 9369 outputs: []outputInfo{ 9370 {1, 0}, 9371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9372 }, 9373 }, 9374 }, 9375 { 9376 name: "SUBSshiftRLreg", 9377 argLen: 3, 9378 asm: arm.ASUB, 9379 reg: regInfo{ 9380 inputs: []inputInfo{ 9381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9382 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9383 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9384 }, 9385 outputs: []outputInfo{ 9386 {1, 0}, 9387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9388 }, 9389 }, 9390 }, 9391 { 9392 name: "SUBSshiftRAreg", 9393 argLen: 3, 9394 asm: arm.ASUB, 9395 reg: regInfo{ 9396 inputs: []inputInfo{ 9397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9398 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9399 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 }, 9401 outputs: []outputInfo{ 9402 {1, 0}, 9403 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9404 }, 9405 }, 9406 }, 9407 { 9408 name: "RSBSshiftLLreg", 9409 argLen: 3, 9410 asm: arm.ARSB, 9411 reg: regInfo{ 9412 inputs: []inputInfo{ 9413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9414 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9416 }, 9417 outputs: []outputInfo{ 9418 {1, 0}, 9419 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9420 }, 9421 }, 9422 }, 9423 { 9424 name: "RSBSshiftRLreg", 9425 argLen: 3, 9426 asm: arm.ARSB, 9427 reg: regInfo{ 9428 inputs: []inputInfo{ 9429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9430 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9431 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9432 }, 9433 outputs: []outputInfo{ 9434 {1, 0}, 9435 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9436 }, 9437 }, 9438 }, 9439 { 9440 name: "RSBSshiftRAreg", 9441 argLen: 3, 9442 asm: arm.ARSB, 9443 reg: regInfo{ 9444 inputs: []inputInfo{ 9445 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9446 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9447 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9448 }, 9449 outputs: []outputInfo{ 9450 {1, 0}, 9451 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9452 }, 9453 }, 9454 }, 9455 { 9456 name: "CMP", 9457 argLen: 2, 9458 asm: arm.ACMP, 9459 reg: regInfo{ 9460 inputs: []inputInfo{ 9461 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9462 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9463 }, 9464 }, 9465 }, 9466 { 9467 name: "CMPconst", 9468 auxType: auxInt32, 9469 argLen: 1, 9470 asm: arm.ACMP, 9471 reg: regInfo{ 9472 inputs: []inputInfo{ 9473 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9474 }, 9475 }, 9476 }, 9477 { 9478 name: "CMN", 9479 argLen: 2, 9480 asm: arm.ACMN, 9481 reg: regInfo{ 9482 inputs: []inputInfo{ 9483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9484 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9485 }, 9486 }, 9487 }, 9488 { 9489 name: "CMNconst", 9490 auxType: auxInt32, 9491 argLen: 1, 9492 asm: arm.ACMN, 9493 reg: regInfo{ 9494 inputs: []inputInfo{ 9495 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9496 }, 9497 }, 9498 }, 9499 { 9500 name: "TST", 9501 argLen: 2, 9502 commutative: true, 9503 asm: arm.ATST, 9504 reg: regInfo{ 9505 inputs: []inputInfo{ 9506 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9507 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9508 }, 9509 }, 9510 }, 9511 { 9512 name: "TSTconst", 9513 auxType: auxInt32, 9514 argLen: 1, 9515 asm: arm.ATST, 9516 reg: regInfo{ 9517 inputs: []inputInfo{ 9518 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9519 }, 9520 }, 9521 }, 9522 { 9523 name: "TEQ", 9524 argLen: 2, 9525 commutative: true, 9526 asm: arm.ATEQ, 9527 reg: regInfo{ 9528 inputs: []inputInfo{ 9529 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9530 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9531 }, 9532 }, 9533 }, 9534 { 9535 name: "TEQconst", 9536 auxType: auxInt32, 9537 argLen: 1, 9538 asm: arm.ATEQ, 9539 reg: regInfo{ 9540 inputs: []inputInfo{ 9541 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9542 }, 9543 }, 9544 }, 9545 { 9546 name: "CMPF", 9547 argLen: 2, 9548 asm: arm.ACMPF, 9549 reg: regInfo{ 9550 inputs: []inputInfo{ 9551 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9552 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9553 }, 9554 }, 9555 }, 9556 { 9557 name: "CMPD", 9558 argLen: 2, 9559 asm: arm.ACMPD, 9560 reg: regInfo{ 9561 inputs: []inputInfo{ 9562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9563 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9564 }, 9565 }, 9566 }, 9567 { 9568 name: "CMPshiftLL", 9569 auxType: auxInt32, 9570 argLen: 2, 9571 asm: arm.ACMP, 9572 reg: regInfo{ 9573 inputs: []inputInfo{ 9574 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9575 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9576 }, 9577 }, 9578 }, 9579 { 9580 name: "CMPshiftRL", 9581 auxType: auxInt32, 9582 argLen: 2, 9583 asm: arm.ACMP, 9584 reg: regInfo{ 9585 inputs: []inputInfo{ 9586 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9587 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9588 }, 9589 }, 9590 }, 9591 { 9592 name: "CMPshiftRA", 9593 auxType: auxInt32, 9594 argLen: 2, 9595 asm: arm.ACMP, 9596 reg: regInfo{ 9597 inputs: []inputInfo{ 9598 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9599 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9600 }, 9601 }, 9602 }, 9603 { 9604 name: "CMPshiftLLreg", 9605 argLen: 3, 9606 asm: arm.ACMP, 9607 reg: regInfo{ 9608 inputs: []inputInfo{ 9609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9610 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9611 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9612 }, 9613 }, 9614 }, 9615 { 9616 name: "CMPshiftRLreg", 9617 argLen: 3, 9618 asm: arm.ACMP, 9619 reg: regInfo{ 9620 inputs: []inputInfo{ 9621 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9622 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9623 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9624 }, 9625 }, 9626 }, 9627 { 9628 name: "CMPshiftRAreg", 9629 argLen: 3, 9630 asm: arm.ACMP, 9631 reg: regInfo{ 9632 inputs: []inputInfo{ 9633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9635 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9636 }, 9637 }, 9638 }, 9639 { 9640 name: "CMPF0", 9641 argLen: 1, 9642 asm: arm.ACMPF, 9643 reg: regInfo{ 9644 inputs: []inputInfo{ 9645 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9646 }, 9647 }, 9648 }, 9649 { 9650 name: "CMPD0", 9651 argLen: 1, 9652 asm: arm.ACMPD, 9653 reg: regInfo{ 9654 inputs: []inputInfo{ 9655 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9656 }, 9657 }, 9658 }, 9659 { 9660 name: "MOVWconst", 9661 auxType: auxInt32, 9662 argLen: 0, 9663 rematerializeable: true, 9664 asm: arm.AMOVW, 9665 reg: regInfo{ 9666 outputs: []outputInfo{ 9667 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9668 }, 9669 }, 9670 }, 9671 { 9672 name: "MOVFconst", 9673 auxType: auxFloat64, 9674 argLen: 0, 9675 rematerializeable: true, 9676 asm: arm.AMOVF, 9677 reg: regInfo{ 9678 outputs: []outputInfo{ 9679 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9680 }, 9681 }, 9682 }, 9683 { 9684 name: "MOVDconst", 9685 auxType: auxFloat64, 9686 argLen: 0, 9687 rematerializeable: true, 9688 asm: arm.AMOVD, 9689 reg: regInfo{ 9690 outputs: []outputInfo{ 9691 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9692 }, 9693 }, 9694 }, 9695 { 9696 name: "MOVWaddr", 9697 auxType: auxSymOff, 9698 argLen: 1, 9699 rematerializeable: true, 9700 asm: arm.AMOVW, 9701 reg: regInfo{ 9702 inputs: []inputInfo{ 9703 {0, 4294975488}, // SP SB 9704 }, 9705 outputs: []outputInfo{ 9706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9707 }, 9708 }, 9709 }, 9710 { 9711 name: "MOVBload", 9712 auxType: auxSymOff, 9713 argLen: 2, 9714 faultOnNilArg0: true, 9715 asm: arm.AMOVB, 9716 reg: regInfo{ 9717 inputs: []inputInfo{ 9718 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9719 }, 9720 outputs: []outputInfo{ 9721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9722 }, 9723 }, 9724 }, 9725 { 9726 name: "MOVBUload", 9727 auxType: auxSymOff, 9728 argLen: 2, 9729 faultOnNilArg0: true, 9730 asm: arm.AMOVBU, 9731 reg: regInfo{ 9732 inputs: []inputInfo{ 9733 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9734 }, 9735 outputs: []outputInfo{ 9736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9737 }, 9738 }, 9739 }, 9740 { 9741 name: "MOVHload", 9742 auxType: auxSymOff, 9743 argLen: 2, 9744 faultOnNilArg0: true, 9745 asm: arm.AMOVH, 9746 reg: regInfo{ 9747 inputs: []inputInfo{ 9748 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9749 }, 9750 outputs: []outputInfo{ 9751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9752 }, 9753 }, 9754 }, 9755 { 9756 name: "MOVHUload", 9757 auxType: auxSymOff, 9758 argLen: 2, 9759 faultOnNilArg0: true, 9760 asm: arm.AMOVHU, 9761 reg: regInfo{ 9762 inputs: []inputInfo{ 9763 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9764 }, 9765 outputs: []outputInfo{ 9766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9767 }, 9768 }, 9769 }, 9770 { 9771 name: "MOVWload", 9772 auxType: auxSymOff, 9773 argLen: 2, 9774 faultOnNilArg0: true, 9775 asm: arm.AMOVW, 9776 reg: regInfo{ 9777 inputs: []inputInfo{ 9778 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9779 }, 9780 outputs: []outputInfo{ 9781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9782 }, 9783 }, 9784 }, 9785 { 9786 name: "MOVFload", 9787 auxType: auxSymOff, 9788 argLen: 2, 9789 faultOnNilArg0: true, 9790 asm: arm.AMOVF, 9791 reg: regInfo{ 9792 inputs: []inputInfo{ 9793 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9794 }, 9795 outputs: []outputInfo{ 9796 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9797 }, 9798 }, 9799 }, 9800 { 9801 name: "MOVDload", 9802 auxType: auxSymOff, 9803 argLen: 2, 9804 faultOnNilArg0: true, 9805 asm: arm.AMOVD, 9806 reg: regInfo{ 9807 inputs: []inputInfo{ 9808 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9809 }, 9810 outputs: []outputInfo{ 9811 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9812 }, 9813 }, 9814 }, 9815 { 9816 name: "MOVBstore", 9817 auxType: auxSymOff, 9818 argLen: 3, 9819 faultOnNilArg0: true, 9820 asm: arm.AMOVB, 9821 reg: regInfo{ 9822 inputs: []inputInfo{ 9823 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9824 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9825 }, 9826 }, 9827 }, 9828 { 9829 name: "MOVHstore", 9830 auxType: auxSymOff, 9831 argLen: 3, 9832 faultOnNilArg0: true, 9833 asm: arm.AMOVH, 9834 reg: regInfo{ 9835 inputs: []inputInfo{ 9836 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9837 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9838 }, 9839 }, 9840 }, 9841 { 9842 name: "MOVWstore", 9843 auxType: auxSymOff, 9844 argLen: 3, 9845 faultOnNilArg0: true, 9846 asm: arm.AMOVW, 9847 reg: regInfo{ 9848 inputs: []inputInfo{ 9849 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9850 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9851 }, 9852 }, 9853 }, 9854 { 9855 name: "MOVFstore", 9856 auxType: auxSymOff, 9857 argLen: 3, 9858 faultOnNilArg0: true, 9859 asm: arm.AMOVF, 9860 reg: regInfo{ 9861 inputs: []inputInfo{ 9862 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9863 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9864 }, 9865 }, 9866 }, 9867 { 9868 name: "MOVDstore", 9869 auxType: auxSymOff, 9870 argLen: 3, 9871 faultOnNilArg0: true, 9872 asm: arm.AMOVD, 9873 reg: regInfo{ 9874 inputs: []inputInfo{ 9875 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9876 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9877 }, 9878 }, 9879 }, 9880 { 9881 name: "MOVWloadidx", 9882 argLen: 3, 9883 asm: arm.AMOVW, 9884 reg: regInfo{ 9885 inputs: []inputInfo{ 9886 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9887 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9888 }, 9889 outputs: []outputInfo{ 9890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9891 }, 9892 }, 9893 }, 9894 { 9895 name: "MOVWloadshiftLL", 9896 auxType: auxInt32, 9897 argLen: 3, 9898 asm: arm.AMOVW, 9899 reg: regInfo{ 9900 inputs: []inputInfo{ 9901 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9902 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9903 }, 9904 outputs: []outputInfo{ 9905 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9906 }, 9907 }, 9908 }, 9909 { 9910 name: "MOVWloadshiftRL", 9911 auxType: auxInt32, 9912 argLen: 3, 9913 asm: arm.AMOVW, 9914 reg: regInfo{ 9915 inputs: []inputInfo{ 9916 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9917 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9918 }, 9919 outputs: []outputInfo{ 9920 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9921 }, 9922 }, 9923 }, 9924 { 9925 name: "MOVWloadshiftRA", 9926 auxType: auxInt32, 9927 argLen: 3, 9928 asm: arm.AMOVW, 9929 reg: regInfo{ 9930 inputs: []inputInfo{ 9931 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9932 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9933 }, 9934 outputs: []outputInfo{ 9935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9936 }, 9937 }, 9938 }, 9939 { 9940 name: "MOVWstoreidx", 9941 argLen: 4, 9942 asm: arm.AMOVW, 9943 reg: regInfo{ 9944 inputs: []inputInfo{ 9945 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9946 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9947 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9948 }, 9949 }, 9950 }, 9951 { 9952 name: "MOVWstoreshiftLL", 9953 auxType: auxInt32, 9954 argLen: 4, 9955 asm: arm.AMOVW, 9956 reg: regInfo{ 9957 inputs: []inputInfo{ 9958 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9959 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9960 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9961 }, 9962 }, 9963 }, 9964 { 9965 name: "MOVWstoreshiftRL", 9966 auxType: auxInt32, 9967 argLen: 4, 9968 asm: arm.AMOVW, 9969 reg: regInfo{ 9970 inputs: []inputInfo{ 9971 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9972 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9973 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9974 }, 9975 }, 9976 }, 9977 { 9978 name: "MOVWstoreshiftRA", 9979 auxType: auxInt32, 9980 argLen: 4, 9981 asm: arm.AMOVW, 9982 reg: regInfo{ 9983 inputs: []inputInfo{ 9984 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9985 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9986 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 9987 }, 9988 }, 9989 }, 9990 { 9991 name: "MOVBreg", 9992 argLen: 1, 9993 asm: arm.AMOVBS, 9994 reg: regInfo{ 9995 inputs: []inputInfo{ 9996 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9997 }, 9998 outputs: []outputInfo{ 9999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10000 }, 10001 }, 10002 }, 10003 { 10004 name: "MOVBUreg", 10005 argLen: 1, 10006 asm: arm.AMOVBU, 10007 reg: regInfo{ 10008 inputs: []inputInfo{ 10009 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10010 }, 10011 outputs: []outputInfo{ 10012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10013 }, 10014 }, 10015 }, 10016 { 10017 name: "MOVHreg", 10018 argLen: 1, 10019 asm: arm.AMOVHS, 10020 reg: regInfo{ 10021 inputs: []inputInfo{ 10022 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10023 }, 10024 outputs: []outputInfo{ 10025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10026 }, 10027 }, 10028 }, 10029 { 10030 name: "MOVHUreg", 10031 argLen: 1, 10032 asm: arm.AMOVHU, 10033 reg: regInfo{ 10034 inputs: []inputInfo{ 10035 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10036 }, 10037 outputs: []outputInfo{ 10038 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10039 }, 10040 }, 10041 }, 10042 { 10043 name: "MOVWreg", 10044 argLen: 1, 10045 asm: arm.AMOVW, 10046 reg: regInfo{ 10047 inputs: []inputInfo{ 10048 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10049 }, 10050 outputs: []outputInfo{ 10051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10052 }, 10053 }, 10054 }, 10055 { 10056 name: "MOVWnop", 10057 argLen: 1, 10058 resultInArg0: true, 10059 reg: regInfo{ 10060 inputs: []inputInfo{ 10061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 }, 10063 outputs: []outputInfo{ 10064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10065 }, 10066 }, 10067 }, 10068 { 10069 name: "MOVWF", 10070 argLen: 1, 10071 asm: arm.AMOVWF, 10072 reg: regInfo{ 10073 inputs: []inputInfo{ 10074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10075 }, 10076 outputs: []outputInfo{ 10077 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10078 }, 10079 }, 10080 }, 10081 { 10082 name: "MOVWD", 10083 argLen: 1, 10084 asm: arm.AMOVWD, 10085 reg: regInfo{ 10086 inputs: []inputInfo{ 10087 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10088 }, 10089 outputs: []outputInfo{ 10090 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10091 }, 10092 }, 10093 }, 10094 { 10095 name: "MOVWUF", 10096 argLen: 1, 10097 asm: arm.AMOVWF, 10098 reg: regInfo{ 10099 inputs: []inputInfo{ 10100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10101 }, 10102 outputs: []outputInfo{ 10103 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10104 }, 10105 }, 10106 }, 10107 { 10108 name: "MOVWUD", 10109 argLen: 1, 10110 asm: arm.AMOVWD, 10111 reg: regInfo{ 10112 inputs: []inputInfo{ 10113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10114 }, 10115 outputs: []outputInfo{ 10116 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10117 }, 10118 }, 10119 }, 10120 { 10121 name: "MOVFW", 10122 argLen: 1, 10123 asm: arm.AMOVFW, 10124 reg: regInfo{ 10125 inputs: []inputInfo{ 10126 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10127 }, 10128 outputs: []outputInfo{ 10129 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10130 }, 10131 }, 10132 }, 10133 { 10134 name: "MOVDW", 10135 argLen: 1, 10136 asm: arm.AMOVDW, 10137 reg: regInfo{ 10138 inputs: []inputInfo{ 10139 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10140 }, 10141 outputs: []outputInfo{ 10142 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10143 }, 10144 }, 10145 }, 10146 { 10147 name: "MOVFWU", 10148 argLen: 1, 10149 asm: arm.AMOVFW, 10150 reg: regInfo{ 10151 inputs: []inputInfo{ 10152 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10153 }, 10154 outputs: []outputInfo{ 10155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10156 }, 10157 }, 10158 }, 10159 { 10160 name: "MOVDWU", 10161 argLen: 1, 10162 asm: arm.AMOVDW, 10163 reg: regInfo{ 10164 inputs: []inputInfo{ 10165 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10166 }, 10167 outputs: []outputInfo{ 10168 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10169 }, 10170 }, 10171 }, 10172 { 10173 name: "MOVFD", 10174 argLen: 1, 10175 asm: arm.AMOVFD, 10176 reg: regInfo{ 10177 inputs: []inputInfo{ 10178 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10179 }, 10180 outputs: []outputInfo{ 10181 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10182 }, 10183 }, 10184 }, 10185 { 10186 name: "MOVDF", 10187 argLen: 1, 10188 asm: arm.AMOVDF, 10189 reg: regInfo{ 10190 inputs: []inputInfo{ 10191 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10192 }, 10193 outputs: []outputInfo{ 10194 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10195 }, 10196 }, 10197 }, 10198 { 10199 name: "CMOVWHSconst", 10200 auxType: auxInt32, 10201 argLen: 2, 10202 resultInArg0: true, 10203 asm: arm.AMOVW, 10204 reg: regInfo{ 10205 inputs: []inputInfo{ 10206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10207 }, 10208 outputs: []outputInfo{ 10209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10210 }, 10211 }, 10212 }, 10213 { 10214 name: "CMOVWLSconst", 10215 auxType: auxInt32, 10216 argLen: 2, 10217 resultInArg0: true, 10218 asm: arm.AMOVW, 10219 reg: regInfo{ 10220 inputs: []inputInfo{ 10221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10222 }, 10223 outputs: []outputInfo{ 10224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10225 }, 10226 }, 10227 }, 10228 { 10229 name: "SRAcond", 10230 argLen: 3, 10231 asm: arm.ASRA, 10232 reg: regInfo{ 10233 inputs: []inputInfo{ 10234 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10235 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10236 }, 10237 outputs: []outputInfo{ 10238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10239 }, 10240 }, 10241 }, 10242 { 10243 name: "CALLstatic", 10244 auxType: auxSymOff, 10245 argLen: 1, 10246 clobberFlags: true, 10247 call: true, 10248 reg: regInfo{ 10249 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10250 }, 10251 }, 10252 { 10253 name: "CALLclosure", 10254 auxType: auxInt64, 10255 argLen: 3, 10256 clobberFlags: true, 10257 call: true, 10258 reg: regInfo{ 10259 inputs: []inputInfo{ 10260 {1, 128}, // R7 10261 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 10262 }, 10263 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10264 }, 10265 }, 10266 { 10267 name: "CALLdefer", 10268 auxType: auxInt64, 10269 argLen: 1, 10270 clobberFlags: true, 10271 call: true, 10272 reg: regInfo{ 10273 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10274 }, 10275 }, 10276 { 10277 name: "CALLgo", 10278 auxType: auxInt64, 10279 argLen: 1, 10280 clobberFlags: true, 10281 call: true, 10282 reg: regInfo{ 10283 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10284 }, 10285 }, 10286 { 10287 name: "CALLinter", 10288 auxType: auxInt64, 10289 argLen: 2, 10290 clobberFlags: true, 10291 call: true, 10292 reg: regInfo{ 10293 inputs: []inputInfo{ 10294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10295 }, 10296 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10297 }, 10298 }, 10299 { 10300 name: "LoweredNilCheck", 10301 argLen: 2, 10302 nilCheck: true, 10303 faultOnNilArg0: true, 10304 reg: regInfo{ 10305 inputs: []inputInfo{ 10306 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10307 }, 10308 }, 10309 }, 10310 { 10311 name: "Equal", 10312 argLen: 1, 10313 reg: regInfo{ 10314 outputs: []outputInfo{ 10315 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10316 }, 10317 }, 10318 }, 10319 { 10320 name: "NotEqual", 10321 argLen: 1, 10322 reg: regInfo{ 10323 outputs: []outputInfo{ 10324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10325 }, 10326 }, 10327 }, 10328 { 10329 name: "LessThan", 10330 argLen: 1, 10331 reg: regInfo{ 10332 outputs: []outputInfo{ 10333 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10334 }, 10335 }, 10336 }, 10337 { 10338 name: "LessEqual", 10339 argLen: 1, 10340 reg: regInfo{ 10341 outputs: []outputInfo{ 10342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10343 }, 10344 }, 10345 }, 10346 { 10347 name: "GreaterThan", 10348 argLen: 1, 10349 reg: regInfo{ 10350 outputs: []outputInfo{ 10351 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10352 }, 10353 }, 10354 }, 10355 { 10356 name: "GreaterEqual", 10357 argLen: 1, 10358 reg: regInfo{ 10359 outputs: []outputInfo{ 10360 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10361 }, 10362 }, 10363 }, 10364 { 10365 name: "LessThanU", 10366 argLen: 1, 10367 reg: regInfo{ 10368 outputs: []outputInfo{ 10369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10370 }, 10371 }, 10372 }, 10373 { 10374 name: "LessEqualU", 10375 argLen: 1, 10376 reg: regInfo{ 10377 outputs: []outputInfo{ 10378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10379 }, 10380 }, 10381 }, 10382 { 10383 name: "GreaterThanU", 10384 argLen: 1, 10385 reg: regInfo{ 10386 outputs: []outputInfo{ 10387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10388 }, 10389 }, 10390 }, 10391 { 10392 name: "GreaterEqualU", 10393 argLen: 1, 10394 reg: regInfo{ 10395 outputs: []outputInfo{ 10396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10397 }, 10398 }, 10399 }, 10400 { 10401 name: "DUFFZERO", 10402 auxType: auxInt64, 10403 argLen: 3, 10404 faultOnNilArg0: true, 10405 reg: regInfo{ 10406 inputs: []inputInfo{ 10407 {0, 2}, // R1 10408 {1, 1}, // R0 10409 }, 10410 clobbers: 16386, // R1 R14 10411 }, 10412 }, 10413 { 10414 name: "DUFFCOPY", 10415 auxType: auxInt64, 10416 argLen: 3, 10417 faultOnNilArg0: true, 10418 faultOnNilArg1: true, 10419 reg: regInfo{ 10420 inputs: []inputInfo{ 10421 {0, 4}, // R2 10422 {1, 2}, // R1 10423 }, 10424 clobbers: 16391, // R0 R1 R2 R14 10425 }, 10426 }, 10427 { 10428 name: "LoweredZero", 10429 auxType: auxInt64, 10430 argLen: 4, 10431 clobberFlags: true, 10432 faultOnNilArg0: true, 10433 reg: regInfo{ 10434 inputs: []inputInfo{ 10435 {0, 2}, // R1 10436 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10437 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10438 }, 10439 clobbers: 2, // R1 10440 }, 10441 }, 10442 { 10443 name: "LoweredMove", 10444 auxType: auxInt64, 10445 argLen: 4, 10446 clobberFlags: true, 10447 faultOnNilArg0: true, 10448 faultOnNilArg1: true, 10449 reg: regInfo{ 10450 inputs: []inputInfo{ 10451 {0, 4}, // R2 10452 {1, 2}, // R1 10453 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10454 }, 10455 clobbers: 6, // R1 R2 10456 }, 10457 }, 10458 { 10459 name: "LoweredGetClosurePtr", 10460 argLen: 0, 10461 reg: regInfo{ 10462 outputs: []outputInfo{ 10463 {0, 128}, // R7 10464 }, 10465 }, 10466 }, 10467 { 10468 name: "MOVWconvert", 10469 argLen: 2, 10470 asm: arm.AMOVW, 10471 reg: regInfo{ 10472 inputs: []inputInfo{ 10473 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10474 }, 10475 outputs: []outputInfo{ 10476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10477 }, 10478 }, 10479 }, 10480 { 10481 name: "FlagEQ", 10482 argLen: 0, 10483 reg: regInfo{}, 10484 }, 10485 { 10486 name: "FlagLT_ULT", 10487 argLen: 0, 10488 reg: regInfo{}, 10489 }, 10490 { 10491 name: "FlagLT_UGT", 10492 argLen: 0, 10493 reg: regInfo{}, 10494 }, 10495 { 10496 name: "FlagGT_UGT", 10497 argLen: 0, 10498 reg: regInfo{}, 10499 }, 10500 { 10501 name: "FlagGT_ULT", 10502 argLen: 0, 10503 reg: regInfo{}, 10504 }, 10505 { 10506 name: "InvertFlags", 10507 argLen: 1, 10508 reg: regInfo{}, 10509 }, 10510 10511 { 10512 name: "ADD", 10513 argLen: 2, 10514 commutative: true, 10515 asm: arm64.AADD, 10516 reg: regInfo{ 10517 inputs: []inputInfo{ 10518 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10519 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10520 }, 10521 outputs: []outputInfo{ 10522 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10523 }, 10524 }, 10525 }, 10526 { 10527 name: "ADDconst", 10528 auxType: auxInt64, 10529 argLen: 1, 10530 asm: arm64.AADD, 10531 reg: regInfo{ 10532 inputs: []inputInfo{ 10533 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 10534 }, 10535 outputs: []outputInfo{ 10536 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10537 }, 10538 }, 10539 }, 10540 { 10541 name: "SUB", 10542 argLen: 2, 10543 asm: arm64.ASUB, 10544 reg: regInfo{ 10545 inputs: []inputInfo{ 10546 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10547 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10548 }, 10549 outputs: []outputInfo{ 10550 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10551 }, 10552 }, 10553 }, 10554 { 10555 name: "SUBconst", 10556 auxType: auxInt64, 10557 argLen: 1, 10558 asm: arm64.ASUB, 10559 reg: regInfo{ 10560 inputs: []inputInfo{ 10561 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10562 }, 10563 outputs: []outputInfo{ 10564 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10565 }, 10566 }, 10567 }, 10568 { 10569 name: "MUL", 10570 argLen: 2, 10571 commutative: true, 10572 asm: arm64.AMUL, 10573 reg: regInfo{ 10574 inputs: []inputInfo{ 10575 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10576 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10577 }, 10578 outputs: []outputInfo{ 10579 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10580 }, 10581 }, 10582 }, 10583 { 10584 name: "MULW", 10585 argLen: 2, 10586 commutative: true, 10587 asm: arm64.AMULW, 10588 reg: regInfo{ 10589 inputs: []inputInfo{ 10590 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10591 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10592 }, 10593 outputs: []outputInfo{ 10594 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10595 }, 10596 }, 10597 }, 10598 { 10599 name: "MULH", 10600 argLen: 2, 10601 commutative: true, 10602 asm: arm64.ASMULH, 10603 reg: regInfo{ 10604 inputs: []inputInfo{ 10605 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10606 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10607 }, 10608 outputs: []outputInfo{ 10609 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10610 }, 10611 }, 10612 }, 10613 { 10614 name: "UMULH", 10615 argLen: 2, 10616 commutative: true, 10617 asm: arm64.AUMULH, 10618 reg: regInfo{ 10619 inputs: []inputInfo{ 10620 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10621 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10622 }, 10623 outputs: []outputInfo{ 10624 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10625 }, 10626 }, 10627 }, 10628 { 10629 name: "MULL", 10630 argLen: 2, 10631 commutative: true, 10632 asm: arm64.ASMULL, 10633 reg: regInfo{ 10634 inputs: []inputInfo{ 10635 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10636 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10637 }, 10638 outputs: []outputInfo{ 10639 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10640 }, 10641 }, 10642 }, 10643 { 10644 name: "UMULL", 10645 argLen: 2, 10646 commutative: true, 10647 asm: arm64.AUMULL, 10648 reg: regInfo{ 10649 inputs: []inputInfo{ 10650 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10651 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10652 }, 10653 outputs: []outputInfo{ 10654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10655 }, 10656 }, 10657 }, 10658 { 10659 name: "DIV", 10660 argLen: 2, 10661 asm: arm64.ASDIV, 10662 reg: regInfo{ 10663 inputs: []inputInfo{ 10664 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10665 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10666 }, 10667 outputs: []outputInfo{ 10668 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10669 }, 10670 }, 10671 }, 10672 { 10673 name: "UDIV", 10674 argLen: 2, 10675 asm: arm64.AUDIV, 10676 reg: regInfo{ 10677 inputs: []inputInfo{ 10678 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10680 }, 10681 outputs: []outputInfo{ 10682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10683 }, 10684 }, 10685 }, 10686 { 10687 name: "DIVW", 10688 argLen: 2, 10689 asm: arm64.ASDIVW, 10690 reg: regInfo{ 10691 inputs: []inputInfo{ 10692 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10693 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10694 }, 10695 outputs: []outputInfo{ 10696 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10697 }, 10698 }, 10699 }, 10700 { 10701 name: "UDIVW", 10702 argLen: 2, 10703 asm: arm64.AUDIVW, 10704 reg: regInfo{ 10705 inputs: []inputInfo{ 10706 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10707 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10708 }, 10709 outputs: []outputInfo{ 10710 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10711 }, 10712 }, 10713 }, 10714 { 10715 name: "MOD", 10716 argLen: 2, 10717 asm: arm64.AREM, 10718 reg: regInfo{ 10719 inputs: []inputInfo{ 10720 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10721 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10722 }, 10723 outputs: []outputInfo{ 10724 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10725 }, 10726 }, 10727 }, 10728 { 10729 name: "UMOD", 10730 argLen: 2, 10731 asm: arm64.AUREM, 10732 reg: regInfo{ 10733 inputs: []inputInfo{ 10734 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10735 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10736 }, 10737 outputs: []outputInfo{ 10738 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10739 }, 10740 }, 10741 }, 10742 { 10743 name: "MODW", 10744 argLen: 2, 10745 asm: arm64.AREMW, 10746 reg: regInfo{ 10747 inputs: []inputInfo{ 10748 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10749 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10750 }, 10751 outputs: []outputInfo{ 10752 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10753 }, 10754 }, 10755 }, 10756 { 10757 name: "UMODW", 10758 argLen: 2, 10759 asm: arm64.AUREMW, 10760 reg: regInfo{ 10761 inputs: []inputInfo{ 10762 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10764 }, 10765 outputs: []outputInfo{ 10766 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10767 }, 10768 }, 10769 }, 10770 { 10771 name: "FADDS", 10772 argLen: 2, 10773 commutative: true, 10774 asm: arm64.AFADDS, 10775 reg: regInfo{ 10776 inputs: []inputInfo{ 10777 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10778 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10779 }, 10780 outputs: []outputInfo{ 10781 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10782 }, 10783 }, 10784 }, 10785 { 10786 name: "FADDD", 10787 argLen: 2, 10788 commutative: true, 10789 asm: arm64.AFADDD, 10790 reg: regInfo{ 10791 inputs: []inputInfo{ 10792 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10793 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10794 }, 10795 outputs: []outputInfo{ 10796 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10797 }, 10798 }, 10799 }, 10800 { 10801 name: "FSUBS", 10802 argLen: 2, 10803 asm: arm64.AFSUBS, 10804 reg: regInfo{ 10805 inputs: []inputInfo{ 10806 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10807 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10808 }, 10809 outputs: []outputInfo{ 10810 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10811 }, 10812 }, 10813 }, 10814 { 10815 name: "FSUBD", 10816 argLen: 2, 10817 asm: arm64.AFSUBD, 10818 reg: regInfo{ 10819 inputs: []inputInfo{ 10820 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10821 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10822 }, 10823 outputs: []outputInfo{ 10824 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10825 }, 10826 }, 10827 }, 10828 { 10829 name: "FMULS", 10830 argLen: 2, 10831 commutative: true, 10832 asm: arm64.AFMULS, 10833 reg: regInfo{ 10834 inputs: []inputInfo{ 10835 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10836 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10837 }, 10838 outputs: []outputInfo{ 10839 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10840 }, 10841 }, 10842 }, 10843 { 10844 name: "FMULD", 10845 argLen: 2, 10846 commutative: true, 10847 asm: arm64.AFMULD, 10848 reg: regInfo{ 10849 inputs: []inputInfo{ 10850 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10851 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10852 }, 10853 outputs: []outputInfo{ 10854 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10855 }, 10856 }, 10857 }, 10858 { 10859 name: "FDIVS", 10860 argLen: 2, 10861 asm: arm64.AFDIVS, 10862 reg: regInfo{ 10863 inputs: []inputInfo{ 10864 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10865 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10866 }, 10867 outputs: []outputInfo{ 10868 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10869 }, 10870 }, 10871 }, 10872 { 10873 name: "FDIVD", 10874 argLen: 2, 10875 asm: arm64.AFDIVD, 10876 reg: regInfo{ 10877 inputs: []inputInfo{ 10878 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10879 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10880 }, 10881 outputs: []outputInfo{ 10882 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 10883 }, 10884 }, 10885 }, 10886 { 10887 name: "AND", 10888 argLen: 2, 10889 commutative: true, 10890 asm: arm64.AAND, 10891 reg: regInfo{ 10892 inputs: []inputInfo{ 10893 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10894 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10895 }, 10896 outputs: []outputInfo{ 10897 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10898 }, 10899 }, 10900 }, 10901 { 10902 name: "ANDconst", 10903 auxType: auxInt64, 10904 argLen: 1, 10905 asm: arm64.AAND, 10906 reg: regInfo{ 10907 inputs: []inputInfo{ 10908 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10909 }, 10910 outputs: []outputInfo{ 10911 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10912 }, 10913 }, 10914 }, 10915 { 10916 name: "OR", 10917 argLen: 2, 10918 commutative: true, 10919 asm: arm64.AORR, 10920 reg: regInfo{ 10921 inputs: []inputInfo{ 10922 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10923 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10924 }, 10925 outputs: []outputInfo{ 10926 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10927 }, 10928 }, 10929 }, 10930 { 10931 name: "ORconst", 10932 auxType: auxInt64, 10933 argLen: 1, 10934 asm: arm64.AORR, 10935 reg: regInfo{ 10936 inputs: []inputInfo{ 10937 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10938 }, 10939 outputs: []outputInfo{ 10940 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10941 }, 10942 }, 10943 }, 10944 { 10945 name: "XOR", 10946 argLen: 2, 10947 commutative: true, 10948 asm: arm64.AEOR, 10949 reg: regInfo{ 10950 inputs: []inputInfo{ 10951 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10952 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10953 }, 10954 outputs: []outputInfo{ 10955 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10956 }, 10957 }, 10958 }, 10959 { 10960 name: "XORconst", 10961 auxType: auxInt64, 10962 argLen: 1, 10963 asm: arm64.AEOR, 10964 reg: regInfo{ 10965 inputs: []inputInfo{ 10966 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10967 }, 10968 outputs: []outputInfo{ 10969 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10970 }, 10971 }, 10972 }, 10973 { 10974 name: "BIC", 10975 argLen: 2, 10976 asm: arm64.ABIC, 10977 reg: regInfo{ 10978 inputs: []inputInfo{ 10979 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10980 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10981 }, 10982 outputs: []outputInfo{ 10983 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10984 }, 10985 }, 10986 }, 10987 { 10988 name: "BICconst", 10989 auxType: auxInt64, 10990 argLen: 1, 10991 asm: arm64.ABIC, 10992 reg: regInfo{ 10993 inputs: []inputInfo{ 10994 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 10995 }, 10996 outputs: []outputInfo{ 10997 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 10998 }, 10999 }, 11000 }, 11001 { 11002 name: "MVN", 11003 argLen: 1, 11004 asm: arm64.AMVN, 11005 reg: regInfo{ 11006 inputs: []inputInfo{ 11007 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11008 }, 11009 outputs: []outputInfo{ 11010 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11011 }, 11012 }, 11013 }, 11014 { 11015 name: "NEG", 11016 argLen: 1, 11017 asm: arm64.ANEG, 11018 reg: regInfo{ 11019 inputs: []inputInfo{ 11020 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11021 }, 11022 outputs: []outputInfo{ 11023 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11024 }, 11025 }, 11026 }, 11027 { 11028 name: "FNEGS", 11029 argLen: 1, 11030 asm: arm64.AFNEGS, 11031 reg: regInfo{ 11032 inputs: []inputInfo{ 11033 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11034 }, 11035 outputs: []outputInfo{ 11036 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11037 }, 11038 }, 11039 }, 11040 { 11041 name: "FNEGD", 11042 argLen: 1, 11043 asm: arm64.AFNEGD, 11044 reg: regInfo{ 11045 inputs: []inputInfo{ 11046 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11047 }, 11048 outputs: []outputInfo{ 11049 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11050 }, 11051 }, 11052 }, 11053 { 11054 name: "FSQRTD", 11055 argLen: 1, 11056 asm: arm64.AFSQRTD, 11057 reg: regInfo{ 11058 inputs: []inputInfo{ 11059 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11060 }, 11061 outputs: []outputInfo{ 11062 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11063 }, 11064 }, 11065 }, 11066 { 11067 name: "REV", 11068 argLen: 1, 11069 asm: arm64.AREV, 11070 reg: regInfo{ 11071 inputs: []inputInfo{ 11072 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11073 }, 11074 outputs: []outputInfo{ 11075 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11076 }, 11077 }, 11078 }, 11079 { 11080 name: "REVW", 11081 argLen: 1, 11082 asm: arm64.AREVW, 11083 reg: regInfo{ 11084 inputs: []inputInfo{ 11085 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11086 }, 11087 outputs: []outputInfo{ 11088 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11089 }, 11090 }, 11091 }, 11092 { 11093 name: "REV16W", 11094 argLen: 1, 11095 asm: arm64.AREV16W, 11096 reg: regInfo{ 11097 inputs: []inputInfo{ 11098 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11099 }, 11100 outputs: []outputInfo{ 11101 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11102 }, 11103 }, 11104 }, 11105 { 11106 name: "RBIT", 11107 argLen: 1, 11108 asm: arm64.ARBIT, 11109 reg: regInfo{ 11110 inputs: []inputInfo{ 11111 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11112 }, 11113 outputs: []outputInfo{ 11114 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11115 }, 11116 }, 11117 }, 11118 { 11119 name: "RBITW", 11120 argLen: 1, 11121 asm: arm64.ARBITW, 11122 reg: regInfo{ 11123 inputs: []inputInfo{ 11124 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11125 }, 11126 outputs: []outputInfo{ 11127 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11128 }, 11129 }, 11130 }, 11131 { 11132 name: "CLZ", 11133 argLen: 1, 11134 asm: arm64.ACLZ, 11135 reg: regInfo{ 11136 inputs: []inputInfo{ 11137 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11138 }, 11139 outputs: []outputInfo{ 11140 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11141 }, 11142 }, 11143 }, 11144 { 11145 name: "CLZW", 11146 argLen: 1, 11147 asm: arm64.ACLZW, 11148 reg: regInfo{ 11149 inputs: []inputInfo{ 11150 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11151 }, 11152 outputs: []outputInfo{ 11153 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11154 }, 11155 }, 11156 }, 11157 { 11158 name: "SLL", 11159 argLen: 2, 11160 asm: arm64.ALSL, 11161 reg: regInfo{ 11162 inputs: []inputInfo{ 11163 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11164 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11165 }, 11166 outputs: []outputInfo{ 11167 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11168 }, 11169 }, 11170 }, 11171 { 11172 name: "SLLconst", 11173 auxType: auxInt64, 11174 argLen: 1, 11175 asm: arm64.ALSL, 11176 reg: regInfo{ 11177 inputs: []inputInfo{ 11178 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11179 }, 11180 outputs: []outputInfo{ 11181 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11182 }, 11183 }, 11184 }, 11185 { 11186 name: "SRL", 11187 argLen: 2, 11188 asm: arm64.ALSR, 11189 reg: regInfo{ 11190 inputs: []inputInfo{ 11191 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11192 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11193 }, 11194 outputs: []outputInfo{ 11195 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11196 }, 11197 }, 11198 }, 11199 { 11200 name: "SRLconst", 11201 auxType: auxInt64, 11202 argLen: 1, 11203 asm: arm64.ALSR, 11204 reg: regInfo{ 11205 inputs: []inputInfo{ 11206 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11207 }, 11208 outputs: []outputInfo{ 11209 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11210 }, 11211 }, 11212 }, 11213 { 11214 name: "SRA", 11215 argLen: 2, 11216 asm: arm64.AASR, 11217 reg: regInfo{ 11218 inputs: []inputInfo{ 11219 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11220 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11221 }, 11222 outputs: []outputInfo{ 11223 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11224 }, 11225 }, 11226 }, 11227 { 11228 name: "SRAconst", 11229 auxType: auxInt64, 11230 argLen: 1, 11231 asm: arm64.AASR, 11232 reg: regInfo{ 11233 inputs: []inputInfo{ 11234 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11235 }, 11236 outputs: []outputInfo{ 11237 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11238 }, 11239 }, 11240 }, 11241 { 11242 name: "RORconst", 11243 auxType: auxInt64, 11244 argLen: 1, 11245 asm: arm64.AROR, 11246 reg: regInfo{ 11247 inputs: []inputInfo{ 11248 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11249 }, 11250 outputs: []outputInfo{ 11251 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11252 }, 11253 }, 11254 }, 11255 { 11256 name: "RORWconst", 11257 auxType: auxInt64, 11258 argLen: 1, 11259 asm: arm64.ARORW, 11260 reg: regInfo{ 11261 inputs: []inputInfo{ 11262 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11263 }, 11264 outputs: []outputInfo{ 11265 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11266 }, 11267 }, 11268 }, 11269 { 11270 name: "CMP", 11271 argLen: 2, 11272 asm: arm64.ACMP, 11273 reg: regInfo{ 11274 inputs: []inputInfo{ 11275 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11276 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11277 }, 11278 }, 11279 }, 11280 { 11281 name: "CMPconst", 11282 auxType: auxInt64, 11283 argLen: 1, 11284 asm: arm64.ACMP, 11285 reg: regInfo{ 11286 inputs: []inputInfo{ 11287 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11288 }, 11289 }, 11290 }, 11291 { 11292 name: "CMPW", 11293 argLen: 2, 11294 asm: arm64.ACMPW, 11295 reg: regInfo{ 11296 inputs: []inputInfo{ 11297 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11298 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11299 }, 11300 }, 11301 }, 11302 { 11303 name: "CMPWconst", 11304 auxType: auxInt32, 11305 argLen: 1, 11306 asm: arm64.ACMPW, 11307 reg: regInfo{ 11308 inputs: []inputInfo{ 11309 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11310 }, 11311 }, 11312 }, 11313 { 11314 name: "CMN", 11315 argLen: 2, 11316 asm: arm64.ACMN, 11317 reg: regInfo{ 11318 inputs: []inputInfo{ 11319 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11320 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11321 }, 11322 }, 11323 }, 11324 { 11325 name: "CMNconst", 11326 auxType: auxInt64, 11327 argLen: 1, 11328 asm: arm64.ACMN, 11329 reg: regInfo{ 11330 inputs: []inputInfo{ 11331 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11332 }, 11333 }, 11334 }, 11335 { 11336 name: "CMNW", 11337 argLen: 2, 11338 asm: arm64.ACMNW, 11339 reg: regInfo{ 11340 inputs: []inputInfo{ 11341 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11342 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11343 }, 11344 }, 11345 }, 11346 { 11347 name: "CMNWconst", 11348 auxType: auxInt32, 11349 argLen: 1, 11350 asm: arm64.ACMNW, 11351 reg: regInfo{ 11352 inputs: []inputInfo{ 11353 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11354 }, 11355 }, 11356 }, 11357 { 11358 name: "FCMPS", 11359 argLen: 2, 11360 asm: arm64.AFCMPS, 11361 reg: regInfo{ 11362 inputs: []inputInfo{ 11363 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11364 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11365 }, 11366 }, 11367 }, 11368 { 11369 name: "FCMPD", 11370 argLen: 2, 11371 asm: arm64.AFCMPD, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11375 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11376 }, 11377 }, 11378 }, 11379 { 11380 name: "ADDshiftLL", 11381 auxType: auxInt64, 11382 argLen: 2, 11383 asm: arm64.AADD, 11384 reg: regInfo{ 11385 inputs: []inputInfo{ 11386 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11387 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11388 }, 11389 outputs: []outputInfo{ 11390 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11391 }, 11392 }, 11393 }, 11394 { 11395 name: "ADDshiftRL", 11396 auxType: auxInt64, 11397 argLen: 2, 11398 asm: arm64.AADD, 11399 reg: regInfo{ 11400 inputs: []inputInfo{ 11401 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11402 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11403 }, 11404 outputs: []outputInfo{ 11405 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11406 }, 11407 }, 11408 }, 11409 { 11410 name: "ADDshiftRA", 11411 auxType: auxInt64, 11412 argLen: 2, 11413 asm: arm64.AADD, 11414 reg: regInfo{ 11415 inputs: []inputInfo{ 11416 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11417 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11418 }, 11419 outputs: []outputInfo{ 11420 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11421 }, 11422 }, 11423 }, 11424 { 11425 name: "SUBshiftLL", 11426 auxType: auxInt64, 11427 argLen: 2, 11428 asm: arm64.ASUB, 11429 reg: regInfo{ 11430 inputs: []inputInfo{ 11431 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11432 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11433 }, 11434 outputs: []outputInfo{ 11435 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11436 }, 11437 }, 11438 }, 11439 { 11440 name: "SUBshiftRL", 11441 auxType: auxInt64, 11442 argLen: 2, 11443 asm: arm64.ASUB, 11444 reg: regInfo{ 11445 inputs: []inputInfo{ 11446 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11447 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11448 }, 11449 outputs: []outputInfo{ 11450 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11451 }, 11452 }, 11453 }, 11454 { 11455 name: "SUBshiftRA", 11456 auxType: auxInt64, 11457 argLen: 2, 11458 asm: arm64.ASUB, 11459 reg: regInfo{ 11460 inputs: []inputInfo{ 11461 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11462 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11463 }, 11464 outputs: []outputInfo{ 11465 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11466 }, 11467 }, 11468 }, 11469 { 11470 name: "ANDshiftLL", 11471 auxType: auxInt64, 11472 argLen: 2, 11473 asm: arm64.AAND, 11474 reg: regInfo{ 11475 inputs: []inputInfo{ 11476 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11477 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11478 }, 11479 outputs: []outputInfo{ 11480 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11481 }, 11482 }, 11483 }, 11484 { 11485 name: "ANDshiftRL", 11486 auxType: auxInt64, 11487 argLen: 2, 11488 asm: arm64.AAND, 11489 reg: regInfo{ 11490 inputs: []inputInfo{ 11491 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11492 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11493 }, 11494 outputs: []outputInfo{ 11495 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11496 }, 11497 }, 11498 }, 11499 { 11500 name: "ANDshiftRA", 11501 auxType: auxInt64, 11502 argLen: 2, 11503 asm: arm64.AAND, 11504 reg: regInfo{ 11505 inputs: []inputInfo{ 11506 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11507 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11508 }, 11509 outputs: []outputInfo{ 11510 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11511 }, 11512 }, 11513 }, 11514 { 11515 name: "ORshiftLL", 11516 auxType: auxInt64, 11517 argLen: 2, 11518 asm: arm64.AORR, 11519 reg: regInfo{ 11520 inputs: []inputInfo{ 11521 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11522 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11523 }, 11524 outputs: []outputInfo{ 11525 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11526 }, 11527 }, 11528 }, 11529 { 11530 name: "ORshiftRL", 11531 auxType: auxInt64, 11532 argLen: 2, 11533 asm: arm64.AORR, 11534 reg: regInfo{ 11535 inputs: []inputInfo{ 11536 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11537 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11538 }, 11539 outputs: []outputInfo{ 11540 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11541 }, 11542 }, 11543 }, 11544 { 11545 name: "ORshiftRA", 11546 auxType: auxInt64, 11547 argLen: 2, 11548 asm: arm64.AORR, 11549 reg: regInfo{ 11550 inputs: []inputInfo{ 11551 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11552 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11553 }, 11554 outputs: []outputInfo{ 11555 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11556 }, 11557 }, 11558 }, 11559 { 11560 name: "XORshiftLL", 11561 auxType: auxInt64, 11562 argLen: 2, 11563 asm: arm64.AEOR, 11564 reg: regInfo{ 11565 inputs: []inputInfo{ 11566 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11567 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11568 }, 11569 outputs: []outputInfo{ 11570 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11571 }, 11572 }, 11573 }, 11574 { 11575 name: "XORshiftRL", 11576 auxType: auxInt64, 11577 argLen: 2, 11578 asm: arm64.AEOR, 11579 reg: regInfo{ 11580 inputs: []inputInfo{ 11581 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11582 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11583 }, 11584 outputs: []outputInfo{ 11585 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11586 }, 11587 }, 11588 }, 11589 { 11590 name: "XORshiftRA", 11591 auxType: auxInt64, 11592 argLen: 2, 11593 asm: arm64.AEOR, 11594 reg: regInfo{ 11595 inputs: []inputInfo{ 11596 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11597 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11598 }, 11599 outputs: []outputInfo{ 11600 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11601 }, 11602 }, 11603 }, 11604 { 11605 name: "BICshiftLL", 11606 auxType: auxInt64, 11607 argLen: 2, 11608 asm: arm64.ABIC, 11609 reg: regInfo{ 11610 inputs: []inputInfo{ 11611 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11612 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11613 }, 11614 outputs: []outputInfo{ 11615 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11616 }, 11617 }, 11618 }, 11619 { 11620 name: "BICshiftRL", 11621 auxType: auxInt64, 11622 argLen: 2, 11623 asm: arm64.ABIC, 11624 reg: regInfo{ 11625 inputs: []inputInfo{ 11626 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11627 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11628 }, 11629 outputs: []outputInfo{ 11630 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11631 }, 11632 }, 11633 }, 11634 { 11635 name: "BICshiftRA", 11636 auxType: auxInt64, 11637 argLen: 2, 11638 asm: arm64.ABIC, 11639 reg: regInfo{ 11640 inputs: []inputInfo{ 11641 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11642 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11643 }, 11644 outputs: []outputInfo{ 11645 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11646 }, 11647 }, 11648 }, 11649 { 11650 name: "CMPshiftLL", 11651 auxType: auxInt64, 11652 argLen: 2, 11653 asm: arm64.ACMP, 11654 reg: regInfo{ 11655 inputs: []inputInfo{ 11656 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11657 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11658 }, 11659 }, 11660 }, 11661 { 11662 name: "CMPshiftRL", 11663 auxType: auxInt64, 11664 argLen: 2, 11665 asm: arm64.ACMP, 11666 reg: regInfo{ 11667 inputs: []inputInfo{ 11668 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11669 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11670 }, 11671 }, 11672 }, 11673 { 11674 name: "CMPshiftRA", 11675 auxType: auxInt64, 11676 argLen: 2, 11677 asm: arm64.ACMP, 11678 reg: regInfo{ 11679 inputs: []inputInfo{ 11680 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11681 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11682 }, 11683 }, 11684 }, 11685 { 11686 name: "MOVDconst", 11687 auxType: auxInt64, 11688 argLen: 0, 11689 rematerializeable: true, 11690 asm: arm64.AMOVD, 11691 reg: regInfo{ 11692 outputs: []outputInfo{ 11693 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11694 }, 11695 }, 11696 }, 11697 { 11698 name: "FMOVSconst", 11699 auxType: auxFloat64, 11700 argLen: 0, 11701 rematerializeable: true, 11702 asm: arm64.AFMOVS, 11703 reg: regInfo{ 11704 outputs: []outputInfo{ 11705 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11706 }, 11707 }, 11708 }, 11709 { 11710 name: "FMOVDconst", 11711 auxType: auxFloat64, 11712 argLen: 0, 11713 rematerializeable: true, 11714 asm: arm64.AFMOVD, 11715 reg: regInfo{ 11716 outputs: []outputInfo{ 11717 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11718 }, 11719 }, 11720 }, 11721 { 11722 name: "MOVDaddr", 11723 auxType: auxSymOff, 11724 argLen: 1, 11725 rematerializeable: true, 11726 asm: arm64.AMOVD, 11727 reg: regInfo{ 11728 inputs: []inputInfo{ 11729 {0, 9223372037928517632}, // SP SB 11730 }, 11731 outputs: []outputInfo{ 11732 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11733 }, 11734 }, 11735 }, 11736 { 11737 name: "MOVBload", 11738 auxType: auxSymOff, 11739 argLen: 2, 11740 faultOnNilArg0: true, 11741 asm: arm64.AMOVB, 11742 reg: regInfo{ 11743 inputs: []inputInfo{ 11744 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11745 }, 11746 outputs: []outputInfo{ 11747 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11748 }, 11749 }, 11750 }, 11751 { 11752 name: "MOVBUload", 11753 auxType: auxSymOff, 11754 argLen: 2, 11755 faultOnNilArg0: true, 11756 asm: arm64.AMOVBU, 11757 reg: regInfo{ 11758 inputs: []inputInfo{ 11759 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11760 }, 11761 outputs: []outputInfo{ 11762 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11763 }, 11764 }, 11765 }, 11766 { 11767 name: "MOVHload", 11768 auxType: auxSymOff, 11769 argLen: 2, 11770 faultOnNilArg0: true, 11771 asm: arm64.AMOVH, 11772 reg: regInfo{ 11773 inputs: []inputInfo{ 11774 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11775 }, 11776 outputs: []outputInfo{ 11777 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11778 }, 11779 }, 11780 }, 11781 { 11782 name: "MOVHUload", 11783 auxType: auxSymOff, 11784 argLen: 2, 11785 faultOnNilArg0: true, 11786 asm: arm64.AMOVHU, 11787 reg: regInfo{ 11788 inputs: []inputInfo{ 11789 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11790 }, 11791 outputs: []outputInfo{ 11792 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11793 }, 11794 }, 11795 }, 11796 { 11797 name: "MOVWload", 11798 auxType: auxSymOff, 11799 argLen: 2, 11800 faultOnNilArg0: true, 11801 asm: arm64.AMOVW, 11802 reg: regInfo{ 11803 inputs: []inputInfo{ 11804 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11805 }, 11806 outputs: []outputInfo{ 11807 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11808 }, 11809 }, 11810 }, 11811 { 11812 name: "MOVWUload", 11813 auxType: auxSymOff, 11814 argLen: 2, 11815 faultOnNilArg0: true, 11816 asm: arm64.AMOVWU, 11817 reg: regInfo{ 11818 inputs: []inputInfo{ 11819 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11820 }, 11821 outputs: []outputInfo{ 11822 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11823 }, 11824 }, 11825 }, 11826 { 11827 name: "MOVDload", 11828 auxType: auxSymOff, 11829 argLen: 2, 11830 faultOnNilArg0: true, 11831 asm: arm64.AMOVD, 11832 reg: regInfo{ 11833 inputs: []inputInfo{ 11834 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11835 }, 11836 outputs: []outputInfo{ 11837 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11838 }, 11839 }, 11840 }, 11841 { 11842 name: "FMOVSload", 11843 auxType: auxSymOff, 11844 argLen: 2, 11845 faultOnNilArg0: true, 11846 asm: arm64.AFMOVS, 11847 reg: regInfo{ 11848 inputs: []inputInfo{ 11849 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11850 }, 11851 outputs: []outputInfo{ 11852 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11853 }, 11854 }, 11855 }, 11856 { 11857 name: "FMOVDload", 11858 auxType: auxSymOff, 11859 argLen: 2, 11860 faultOnNilArg0: true, 11861 asm: arm64.AFMOVD, 11862 reg: regInfo{ 11863 inputs: []inputInfo{ 11864 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11865 }, 11866 outputs: []outputInfo{ 11867 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11868 }, 11869 }, 11870 }, 11871 { 11872 name: "MOVBstore", 11873 auxType: auxSymOff, 11874 argLen: 3, 11875 faultOnNilArg0: true, 11876 asm: arm64.AMOVB, 11877 reg: regInfo{ 11878 inputs: []inputInfo{ 11879 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11880 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11881 }, 11882 }, 11883 }, 11884 { 11885 name: "MOVHstore", 11886 auxType: auxSymOff, 11887 argLen: 3, 11888 faultOnNilArg0: true, 11889 asm: arm64.AMOVH, 11890 reg: regInfo{ 11891 inputs: []inputInfo{ 11892 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11893 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11894 }, 11895 }, 11896 }, 11897 { 11898 name: "MOVWstore", 11899 auxType: auxSymOff, 11900 argLen: 3, 11901 faultOnNilArg0: true, 11902 asm: arm64.AMOVW, 11903 reg: regInfo{ 11904 inputs: []inputInfo{ 11905 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11906 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11907 }, 11908 }, 11909 }, 11910 { 11911 name: "MOVDstore", 11912 auxType: auxSymOff, 11913 argLen: 3, 11914 faultOnNilArg0: true, 11915 asm: arm64.AMOVD, 11916 reg: regInfo{ 11917 inputs: []inputInfo{ 11918 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11919 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11920 }, 11921 }, 11922 }, 11923 { 11924 name: "FMOVSstore", 11925 auxType: auxSymOff, 11926 argLen: 3, 11927 faultOnNilArg0: true, 11928 asm: arm64.AFMOVS, 11929 reg: regInfo{ 11930 inputs: []inputInfo{ 11931 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11932 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11933 }, 11934 }, 11935 }, 11936 { 11937 name: "FMOVDstore", 11938 auxType: auxSymOff, 11939 argLen: 3, 11940 faultOnNilArg0: true, 11941 asm: arm64.AFMOVD, 11942 reg: regInfo{ 11943 inputs: []inputInfo{ 11944 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11945 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 11946 }, 11947 }, 11948 }, 11949 { 11950 name: "MOVBstorezero", 11951 auxType: auxSymOff, 11952 argLen: 2, 11953 faultOnNilArg0: true, 11954 asm: arm64.AMOVB, 11955 reg: regInfo{ 11956 inputs: []inputInfo{ 11957 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11958 }, 11959 }, 11960 }, 11961 { 11962 name: "MOVHstorezero", 11963 auxType: auxSymOff, 11964 argLen: 2, 11965 faultOnNilArg0: true, 11966 asm: arm64.AMOVH, 11967 reg: regInfo{ 11968 inputs: []inputInfo{ 11969 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11970 }, 11971 }, 11972 }, 11973 { 11974 name: "MOVWstorezero", 11975 auxType: auxSymOff, 11976 argLen: 2, 11977 faultOnNilArg0: true, 11978 asm: arm64.AMOVW, 11979 reg: regInfo{ 11980 inputs: []inputInfo{ 11981 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11982 }, 11983 }, 11984 }, 11985 { 11986 name: "MOVDstorezero", 11987 auxType: auxSymOff, 11988 argLen: 2, 11989 faultOnNilArg0: true, 11990 asm: arm64.AMOVD, 11991 reg: regInfo{ 11992 inputs: []inputInfo{ 11993 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 11994 }, 11995 }, 11996 }, 11997 { 11998 name: "MOVBreg", 11999 argLen: 1, 12000 asm: arm64.AMOVB, 12001 reg: regInfo{ 12002 inputs: []inputInfo{ 12003 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12004 }, 12005 outputs: []outputInfo{ 12006 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12007 }, 12008 }, 12009 }, 12010 { 12011 name: "MOVBUreg", 12012 argLen: 1, 12013 asm: arm64.AMOVBU, 12014 reg: regInfo{ 12015 inputs: []inputInfo{ 12016 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12017 }, 12018 outputs: []outputInfo{ 12019 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12020 }, 12021 }, 12022 }, 12023 { 12024 name: "MOVHreg", 12025 argLen: 1, 12026 asm: arm64.AMOVH, 12027 reg: regInfo{ 12028 inputs: []inputInfo{ 12029 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12030 }, 12031 outputs: []outputInfo{ 12032 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12033 }, 12034 }, 12035 }, 12036 { 12037 name: "MOVHUreg", 12038 argLen: 1, 12039 asm: arm64.AMOVHU, 12040 reg: regInfo{ 12041 inputs: []inputInfo{ 12042 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12043 }, 12044 outputs: []outputInfo{ 12045 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12046 }, 12047 }, 12048 }, 12049 { 12050 name: "MOVWreg", 12051 argLen: 1, 12052 asm: arm64.AMOVW, 12053 reg: regInfo{ 12054 inputs: []inputInfo{ 12055 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12056 }, 12057 outputs: []outputInfo{ 12058 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12059 }, 12060 }, 12061 }, 12062 { 12063 name: "MOVWUreg", 12064 argLen: 1, 12065 asm: arm64.AMOVWU, 12066 reg: regInfo{ 12067 inputs: []inputInfo{ 12068 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12069 }, 12070 outputs: []outputInfo{ 12071 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12072 }, 12073 }, 12074 }, 12075 { 12076 name: "MOVDreg", 12077 argLen: 1, 12078 asm: arm64.AMOVD, 12079 reg: regInfo{ 12080 inputs: []inputInfo{ 12081 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12082 }, 12083 outputs: []outputInfo{ 12084 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12085 }, 12086 }, 12087 }, 12088 { 12089 name: "MOVDnop", 12090 argLen: 1, 12091 resultInArg0: true, 12092 reg: regInfo{ 12093 inputs: []inputInfo{ 12094 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12095 }, 12096 outputs: []outputInfo{ 12097 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12098 }, 12099 }, 12100 }, 12101 { 12102 name: "SCVTFWS", 12103 argLen: 1, 12104 asm: arm64.ASCVTFWS, 12105 reg: regInfo{ 12106 inputs: []inputInfo{ 12107 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12108 }, 12109 outputs: []outputInfo{ 12110 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12111 }, 12112 }, 12113 }, 12114 { 12115 name: "SCVTFWD", 12116 argLen: 1, 12117 asm: arm64.ASCVTFWD, 12118 reg: regInfo{ 12119 inputs: []inputInfo{ 12120 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12121 }, 12122 outputs: []outputInfo{ 12123 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12124 }, 12125 }, 12126 }, 12127 { 12128 name: "UCVTFWS", 12129 argLen: 1, 12130 asm: arm64.AUCVTFWS, 12131 reg: regInfo{ 12132 inputs: []inputInfo{ 12133 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12134 }, 12135 outputs: []outputInfo{ 12136 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12137 }, 12138 }, 12139 }, 12140 { 12141 name: "UCVTFWD", 12142 argLen: 1, 12143 asm: arm64.AUCVTFWD, 12144 reg: regInfo{ 12145 inputs: []inputInfo{ 12146 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12147 }, 12148 outputs: []outputInfo{ 12149 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12150 }, 12151 }, 12152 }, 12153 { 12154 name: "SCVTFS", 12155 argLen: 1, 12156 asm: arm64.ASCVTFS, 12157 reg: regInfo{ 12158 inputs: []inputInfo{ 12159 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12160 }, 12161 outputs: []outputInfo{ 12162 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12163 }, 12164 }, 12165 }, 12166 { 12167 name: "SCVTFD", 12168 argLen: 1, 12169 asm: arm64.ASCVTFD, 12170 reg: regInfo{ 12171 inputs: []inputInfo{ 12172 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12173 }, 12174 outputs: []outputInfo{ 12175 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12176 }, 12177 }, 12178 }, 12179 { 12180 name: "UCVTFS", 12181 argLen: 1, 12182 asm: arm64.AUCVTFS, 12183 reg: regInfo{ 12184 inputs: []inputInfo{ 12185 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12186 }, 12187 outputs: []outputInfo{ 12188 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12189 }, 12190 }, 12191 }, 12192 { 12193 name: "UCVTFD", 12194 argLen: 1, 12195 asm: arm64.AUCVTFD, 12196 reg: regInfo{ 12197 inputs: []inputInfo{ 12198 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12199 }, 12200 outputs: []outputInfo{ 12201 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12202 }, 12203 }, 12204 }, 12205 { 12206 name: "FCVTZSSW", 12207 argLen: 1, 12208 asm: arm64.AFCVTZSSW, 12209 reg: regInfo{ 12210 inputs: []inputInfo{ 12211 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12212 }, 12213 outputs: []outputInfo{ 12214 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12215 }, 12216 }, 12217 }, 12218 { 12219 name: "FCVTZSDW", 12220 argLen: 1, 12221 asm: arm64.AFCVTZSDW, 12222 reg: regInfo{ 12223 inputs: []inputInfo{ 12224 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12225 }, 12226 outputs: []outputInfo{ 12227 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12228 }, 12229 }, 12230 }, 12231 { 12232 name: "FCVTZUSW", 12233 argLen: 1, 12234 asm: arm64.AFCVTZUSW, 12235 reg: regInfo{ 12236 inputs: []inputInfo{ 12237 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12238 }, 12239 outputs: []outputInfo{ 12240 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12241 }, 12242 }, 12243 }, 12244 { 12245 name: "FCVTZUDW", 12246 argLen: 1, 12247 asm: arm64.AFCVTZUDW, 12248 reg: regInfo{ 12249 inputs: []inputInfo{ 12250 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12251 }, 12252 outputs: []outputInfo{ 12253 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12254 }, 12255 }, 12256 }, 12257 { 12258 name: "FCVTZSS", 12259 argLen: 1, 12260 asm: arm64.AFCVTZSS, 12261 reg: regInfo{ 12262 inputs: []inputInfo{ 12263 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12264 }, 12265 outputs: []outputInfo{ 12266 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12267 }, 12268 }, 12269 }, 12270 { 12271 name: "FCVTZSD", 12272 argLen: 1, 12273 asm: arm64.AFCVTZSD, 12274 reg: regInfo{ 12275 inputs: []inputInfo{ 12276 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12277 }, 12278 outputs: []outputInfo{ 12279 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12280 }, 12281 }, 12282 }, 12283 { 12284 name: "FCVTZUS", 12285 argLen: 1, 12286 asm: arm64.AFCVTZUS, 12287 reg: regInfo{ 12288 inputs: []inputInfo{ 12289 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12290 }, 12291 outputs: []outputInfo{ 12292 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12293 }, 12294 }, 12295 }, 12296 { 12297 name: "FCVTZUD", 12298 argLen: 1, 12299 asm: arm64.AFCVTZUD, 12300 reg: regInfo{ 12301 inputs: []inputInfo{ 12302 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12303 }, 12304 outputs: []outputInfo{ 12305 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12306 }, 12307 }, 12308 }, 12309 { 12310 name: "FCVTSD", 12311 argLen: 1, 12312 asm: arm64.AFCVTSD, 12313 reg: regInfo{ 12314 inputs: []inputInfo{ 12315 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12316 }, 12317 outputs: []outputInfo{ 12318 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12319 }, 12320 }, 12321 }, 12322 { 12323 name: "FCVTDS", 12324 argLen: 1, 12325 asm: arm64.AFCVTDS, 12326 reg: regInfo{ 12327 inputs: []inputInfo{ 12328 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12329 }, 12330 outputs: []outputInfo{ 12331 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12332 }, 12333 }, 12334 }, 12335 { 12336 name: "CSELULT", 12337 argLen: 3, 12338 asm: arm64.ACSEL, 12339 reg: regInfo{ 12340 inputs: []inputInfo{ 12341 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12342 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12343 }, 12344 outputs: []outputInfo{ 12345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12346 }, 12347 }, 12348 }, 12349 { 12350 name: "CSELULT0", 12351 argLen: 2, 12352 asm: arm64.ACSEL, 12353 reg: regInfo{ 12354 inputs: []inputInfo{ 12355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12356 }, 12357 outputs: []outputInfo{ 12358 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12359 }, 12360 }, 12361 }, 12362 { 12363 name: "CALLstatic", 12364 auxType: auxSymOff, 12365 argLen: 1, 12366 clobberFlags: true, 12367 call: true, 12368 reg: regInfo{ 12369 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12370 }, 12371 }, 12372 { 12373 name: "CALLclosure", 12374 auxType: auxInt64, 12375 argLen: 3, 12376 clobberFlags: true, 12377 call: true, 12378 reg: regInfo{ 12379 inputs: []inputInfo{ 12380 {1, 67108864}, // R26 12381 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 12382 }, 12383 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12384 }, 12385 }, 12386 { 12387 name: "CALLdefer", 12388 auxType: auxInt64, 12389 argLen: 1, 12390 clobberFlags: true, 12391 call: true, 12392 reg: regInfo{ 12393 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12394 }, 12395 }, 12396 { 12397 name: "CALLgo", 12398 auxType: auxInt64, 12399 argLen: 1, 12400 clobberFlags: true, 12401 call: true, 12402 reg: regInfo{ 12403 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12404 }, 12405 }, 12406 { 12407 name: "CALLinter", 12408 auxType: auxInt64, 12409 argLen: 2, 12410 clobberFlags: true, 12411 call: true, 12412 reg: regInfo{ 12413 inputs: []inputInfo{ 12414 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12415 }, 12416 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12417 }, 12418 }, 12419 { 12420 name: "LoweredNilCheck", 12421 argLen: 2, 12422 nilCheck: true, 12423 faultOnNilArg0: true, 12424 reg: regInfo{ 12425 inputs: []inputInfo{ 12426 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12427 }, 12428 }, 12429 }, 12430 { 12431 name: "Equal", 12432 argLen: 1, 12433 reg: regInfo{ 12434 outputs: []outputInfo{ 12435 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12436 }, 12437 }, 12438 }, 12439 { 12440 name: "NotEqual", 12441 argLen: 1, 12442 reg: regInfo{ 12443 outputs: []outputInfo{ 12444 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12445 }, 12446 }, 12447 }, 12448 { 12449 name: "LessThan", 12450 argLen: 1, 12451 reg: regInfo{ 12452 outputs: []outputInfo{ 12453 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12454 }, 12455 }, 12456 }, 12457 { 12458 name: "LessEqual", 12459 argLen: 1, 12460 reg: regInfo{ 12461 outputs: []outputInfo{ 12462 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12463 }, 12464 }, 12465 }, 12466 { 12467 name: "GreaterThan", 12468 argLen: 1, 12469 reg: regInfo{ 12470 outputs: []outputInfo{ 12471 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12472 }, 12473 }, 12474 }, 12475 { 12476 name: "GreaterEqual", 12477 argLen: 1, 12478 reg: regInfo{ 12479 outputs: []outputInfo{ 12480 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12481 }, 12482 }, 12483 }, 12484 { 12485 name: "LessThanU", 12486 argLen: 1, 12487 reg: regInfo{ 12488 outputs: []outputInfo{ 12489 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12490 }, 12491 }, 12492 }, 12493 { 12494 name: "LessEqualU", 12495 argLen: 1, 12496 reg: regInfo{ 12497 outputs: []outputInfo{ 12498 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12499 }, 12500 }, 12501 }, 12502 { 12503 name: "GreaterThanU", 12504 argLen: 1, 12505 reg: regInfo{ 12506 outputs: []outputInfo{ 12507 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12508 }, 12509 }, 12510 }, 12511 { 12512 name: "GreaterEqualU", 12513 argLen: 1, 12514 reg: regInfo{ 12515 outputs: []outputInfo{ 12516 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12517 }, 12518 }, 12519 }, 12520 { 12521 name: "DUFFZERO", 12522 auxType: auxInt64, 12523 argLen: 2, 12524 faultOnNilArg0: true, 12525 reg: regInfo{ 12526 inputs: []inputInfo{ 12527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12528 }, 12529 clobbers: 536936448, // R16 R30 12530 }, 12531 }, 12532 { 12533 name: "LoweredZero", 12534 argLen: 3, 12535 clobberFlags: true, 12536 faultOnNilArg0: true, 12537 reg: regInfo{ 12538 inputs: []inputInfo{ 12539 {0, 65536}, // R16 12540 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12541 }, 12542 clobbers: 65536, // R16 12543 }, 12544 }, 12545 { 12546 name: "DUFFCOPY", 12547 auxType: auxInt64, 12548 argLen: 3, 12549 faultOnNilArg0: true, 12550 faultOnNilArg1: true, 12551 reg: regInfo{ 12552 inputs: []inputInfo{ 12553 {0, 131072}, // R17 12554 {1, 65536}, // R16 12555 }, 12556 clobbers: 537067520, // R16 R17 R30 12557 }, 12558 }, 12559 { 12560 name: "LoweredMove", 12561 argLen: 4, 12562 clobberFlags: true, 12563 faultOnNilArg0: true, 12564 faultOnNilArg1: true, 12565 reg: regInfo{ 12566 inputs: []inputInfo{ 12567 {0, 131072}, // R17 12568 {1, 65536}, // R16 12569 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12570 }, 12571 clobbers: 196608, // R16 R17 12572 }, 12573 }, 12574 { 12575 name: "LoweredGetClosurePtr", 12576 argLen: 0, 12577 reg: regInfo{ 12578 outputs: []outputInfo{ 12579 {0, 67108864}, // R26 12580 }, 12581 }, 12582 }, 12583 { 12584 name: "MOVDconvert", 12585 argLen: 2, 12586 asm: arm64.AMOVD, 12587 reg: regInfo{ 12588 inputs: []inputInfo{ 12589 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12590 }, 12591 outputs: []outputInfo{ 12592 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12593 }, 12594 }, 12595 }, 12596 { 12597 name: "FlagEQ", 12598 argLen: 0, 12599 reg: regInfo{}, 12600 }, 12601 { 12602 name: "FlagLT_ULT", 12603 argLen: 0, 12604 reg: regInfo{}, 12605 }, 12606 { 12607 name: "FlagLT_UGT", 12608 argLen: 0, 12609 reg: regInfo{}, 12610 }, 12611 { 12612 name: "FlagGT_UGT", 12613 argLen: 0, 12614 reg: regInfo{}, 12615 }, 12616 { 12617 name: "FlagGT_ULT", 12618 argLen: 0, 12619 reg: regInfo{}, 12620 }, 12621 { 12622 name: "InvertFlags", 12623 argLen: 1, 12624 reg: regInfo{}, 12625 }, 12626 { 12627 name: "LDAR", 12628 argLen: 2, 12629 faultOnNilArg0: true, 12630 asm: arm64.ALDAR, 12631 reg: regInfo{ 12632 inputs: []inputInfo{ 12633 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12634 }, 12635 outputs: []outputInfo{ 12636 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12637 }, 12638 }, 12639 }, 12640 { 12641 name: "LDARW", 12642 argLen: 2, 12643 faultOnNilArg0: true, 12644 asm: arm64.ALDARW, 12645 reg: regInfo{ 12646 inputs: []inputInfo{ 12647 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12648 }, 12649 outputs: []outputInfo{ 12650 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12651 }, 12652 }, 12653 }, 12654 { 12655 name: "STLR", 12656 argLen: 3, 12657 faultOnNilArg0: true, 12658 asm: arm64.ASTLR, 12659 reg: regInfo{ 12660 inputs: []inputInfo{ 12661 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12662 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12663 }, 12664 }, 12665 }, 12666 { 12667 name: "STLRW", 12668 argLen: 3, 12669 faultOnNilArg0: true, 12670 asm: arm64.ASTLRW, 12671 reg: regInfo{ 12672 inputs: []inputInfo{ 12673 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12674 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12675 }, 12676 }, 12677 }, 12678 { 12679 name: "LoweredAtomicExchange64", 12680 argLen: 3, 12681 resultNotInArgs: true, 12682 faultOnNilArg0: true, 12683 reg: regInfo{ 12684 inputs: []inputInfo{ 12685 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12686 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12687 }, 12688 outputs: []outputInfo{ 12689 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12690 }, 12691 }, 12692 }, 12693 { 12694 name: "LoweredAtomicExchange32", 12695 argLen: 3, 12696 resultNotInArgs: true, 12697 faultOnNilArg0: true, 12698 reg: regInfo{ 12699 inputs: []inputInfo{ 12700 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12701 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12702 }, 12703 outputs: []outputInfo{ 12704 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12705 }, 12706 }, 12707 }, 12708 { 12709 name: "LoweredAtomicAdd64", 12710 argLen: 3, 12711 resultNotInArgs: true, 12712 faultOnNilArg0: true, 12713 reg: regInfo{ 12714 inputs: []inputInfo{ 12715 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12716 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12717 }, 12718 outputs: []outputInfo{ 12719 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12720 }, 12721 }, 12722 }, 12723 { 12724 name: "LoweredAtomicAdd32", 12725 argLen: 3, 12726 resultNotInArgs: true, 12727 faultOnNilArg0: true, 12728 reg: regInfo{ 12729 inputs: []inputInfo{ 12730 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12731 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12732 }, 12733 outputs: []outputInfo{ 12734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12735 }, 12736 }, 12737 }, 12738 { 12739 name: "LoweredAtomicCas64", 12740 argLen: 4, 12741 resultNotInArgs: true, 12742 clobberFlags: true, 12743 faultOnNilArg0: true, 12744 reg: regInfo{ 12745 inputs: []inputInfo{ 12746 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12747 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12748 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12749 }, 12750 outputs: []outputInfo{ 12751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12752 }, 12753 }, 12754 }, 12755 { 12756 name: "LoweredAtomicCas32", 12757 argLen: 4, 12758 resultNotInArgs: true, 12759 clobberFlags: true, 12760 faultOnNilArg0: true, 12761 reg: regInfo{ 12762 inputs: []inputInfo{ 12763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12764 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12765 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12766 }, 12767 outputs: []outputInfo{ 12768 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12769 }, 12770 }, 12771 }, 12772 { 12773 name: "LoweredAtomicAnd8", 12774 argLen: 3, 12775 faultOnNilArg0: true, 12776 asm: arm64.AAND, 12777 reg: regInfo{ 12778 inputs: []inputInfo{ 12779 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12780 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12781 }, 12782 }, 12783 }, 12784 { 12785 name: "LoweredAtomicOr8", 12786 argLen: 3, 12787 faultOnNilArg0: true, 12788 asm: arm64.AORR, 12789 reg: regInfo{ 12790 inputs: []inputInfo{ 12791 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12792 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 12793 }, 12794 }, 12795 }, 12796 12797 { 12798 name: "ADD", 12799 argLen: 2, 12800 commutative: true, 12801 asm: mips.AADDU, 12802 reg: regInfo{ 12803 inputs: []inputInfo{ 12804 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12805 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12806 }, 12807 outputs: []outputInfo{ 12808 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12809 }, 12810 }, 12811 }, 12812 { 12813 name: "ADDconst", 12814 auxType: auxInt32, 12815 argLen: 1, 12816 asm: mips.AADDU, 12817 reg: regInfo{ 12818 inputs: []inputInfo{ 12819 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 12820 }, 12821 outputs: []outputInfo{ 12822 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12823 }, 12824 }, 12825 }, 12826 { 12827 name: "SUB", 12828 argLen: 2, 12829 asm: mips.ASUBU, 12830 reg: regInfo{ 12831 inputs: []inputInfo{ 12832 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12833 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12834 }, 12835 outputs: []outputInfo{ 12836 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12837 }, 12838 }, 12839 }, 12840 { 12841 name: "SUBconst", 12842 auxType: auxInt32, 12843 argLen: 1, 12844 asm: mips.ASUBU, 12845 reg: regInfo{ 12846 inputs: []inputInfo{ 12847 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12848 }, 12849 outputs: []outputInfo{ 12850 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12851 }, 12852 }, 12853 }, 12854 { 12855 name: "MUL", 12856 argLen: 2, 12857 commutative: true, 12858 asm: mips.AMUL, 12859 reg: regInfo{ 12860 inputs: []inputInfo{ 12861 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12862 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12863 }, 12864 clobbers: 105553116266496, // HI LO 12865 outputs: []outputInfo{ 12866 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 12867 }, 12868 }, 12869 }, 12870 { 12871 name: "MULT", 12872 argLen: 2, 12873 commutative: true, 12874 asm: mips.AMUL, 12875 reg: regInfo{ 12876 inputs: []inputInfo{ 12877 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12878 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12879 }, 12880 outputs: []outputInfo{ 12881 {0, 35184372088832}, // HI 12882 {1, 70368744177664}, // LO 12883 }, 12884 }, 12885 }, 12886 { 12887 name: "MULTU", 12888 argLen: 2, 12889 commutative: true, 12890 asm: mips.AMULU, 12891 reg: regInfo{ 12892 inputs: []inputInfo{ 12893 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12894 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12895 }, 12896 outputs: []outputInfo{ 12897 {0, 35184372088832}, // HI 12898 {1, 70368744177664}, // LO 12899 }, 12900 }, 12901 }, 12902 { 12903 name: "DIV", 12904 argLen: 2, 12905 asm: mips.ADIV, 12906 reg: regInfo{ 12907 inputs: []inputInfo{ 12908 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12909 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12910 }, 12911 outputs: []outputInfo{ 12912 {0, 35184372088832}, // HI 12913 {1, 70368744177664}, // LO 12914 }, 12915 }, 12916 }, 12917 { 12918 name: "DIVU", 12919 argLen: 2, 12920 asm: mips.ADIVU, 12921 reg: regInfo{ 12922 inputs: []inputInfo{ 12923 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12924 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 12925 }, 12926 outputs: []outputInfo{ 12927 {0, 35184372088832}, // HI 12928 {1, 70368744177664}, // LO 12929 }, 12930 }, 12931 }, 12932 { 12933 name: "ADDF", 12934 argLen: 2, 12935 commutative: true, 12936 asm: mips.AADDF, 12937 reg: regInfo{ 12938 inputs: []inputInfo{ 12939 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12940 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12941 }, 12942 outputs: []outputInfo{ 12943 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12944 }, 12945 }, 12946 }, 12947 { 12948 name: "ADDD", 12949 argLen: 2, 12950 commutative: true, 12951 asm: mips.AADDD, 12952 reg: regInfo{ 12953 inputs: []inputInfo{ 12954 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12955 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12956 }, 12957 outputs: []outputInfo{ 12958 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12959 }, 12960 }, 12961 }, 12962 { 12963 name: "SUBF", 12964 argLen: 2, 12965 asm: mips.ASUBF, 12966 reg: regInfo{ 12967 inputs: []inputInfo{ 12968 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12969 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12970 }, 12971 outputs: []outputInfo{ 12972 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12973 }, 12974 }, 12975 }, 12976 { 12977 name: "SUBD", 12978 argLen: 2, 12979 asm: mips.ASUBD, 12980 reg: regInfo{ 12981 inputs: []inputInfo{ 12982 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12983 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12984 }, 12985 outputs: []outputInfo{ 12986 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12987 }, 12988 }, 12989 }, 12990 { 12991 name: "MULF", 12992 argLen: 2, 12993 commutative: true, 12994 asm: mips.AMULF, 12995 reg: regInfo{ 12996 inputs: []inputInfo{ 12997 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12998 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 12999 }, 13000 outputs: []outputInfo{ 13001 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13002 }, 13003 }, 13004 }, 13005 { 13006 name: "MULD", 13007 argLen: 2, 13008 commutative: true, 13009 asm: mips.AMULD, 13010 reg: regInfo{ 13011 inputs: []inputInfo{ 13012 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13013 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13014 }, 13015 outputs: []outputInfo{ 13016 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13017 }, 13018 }, 13019 }, 13020 { 13021 name: "DIVF", 13022 argLen: 2, 13023 asm: mips.ADIVF, 13024 reg: regInfo{ 13025 inputs: []inputInfo{ 13026 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13027 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13028 }, 13029 outputs: []outputInfo{ 13030 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13031 }, 13032 }, 13033 }, 13034 { 13035 name: "DIVD", 13036 argLen: 2, 13037 asm: mips.ADIVD, 13038 reg: regInfo{ 13039 inputs: []inputInfo{ 13040 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13041 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13042 }, 13043 outputs: []outputInfo{ 13044 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13045 }, 13046 }, 13047 }, 13048 { 13049 name: "AND", 13050 argLen: 2, 13051 commutative: true, 13052 asm: mips.AAND, 13053 reg: regInfo{ 13054 inputs: []inputInfo{ 13055 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13056 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13057 }, 13058 outputs: []outputInfo{ 13059 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13060 }, 13061 }, 13062 }, 13063 { 13064 name: "ANDconst", 13065 auxType: auxInt32, 13066 argLen: 1, 13067 asm: mips.AAND, 13068 reg: regInfo{ 13069 inputs: []inputInfo{ 13070 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13071 }, 13072 outputs: []outputInfo{ 13073 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13074 }, 13075 }, 13076 }, 13077 { 13078 name: "OR", 13079 argLen: 2, 13080 commutative: true, 13081 asm: mips.AOR, 13082 reg: regInfo{ 13083 inputs: []inputInfo{ 13084 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13085 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13086 }, 13087 outputs: []outputInfo{ 13088 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13089 }, 13090 }, 13091 }, 13092 { 13093 name: "ORconst", 13094 auxType: auxInt32, 13095 argLen: 1, 13096 asm: mips.AOR, 13097 reg: regInfo{ 13098 inputs: []inputInfo{ 13099 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13100 }, 13101 outputs: []outputInfo{ 13102 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13103 }, 13104 }, 13105 }, 13106 { 13107 name: "XOR", 13108 argLen: 2, 13109 commutative: true, 13110 asm: mips.AXOR, 13111 reg: regInfo{ 13112 inputs: []inputInfo{ 13113 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13114 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13115 }, 13116 outputs: []outputInfo{ 13117 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13118 }, 13119 }, 13120 }, 13121 { 13122 name: "XORconst", 13123 auxType: auxInt32, 13124 argLen: 1, 13125 asm: mips.AXOR, 13126 reg: regInfo{ 13127 inputs: []inputInfo{ 13128 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13129 }, 13130 outputs: []outputInfo{ 13131 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13132 }, 13133 }, 13134 }, 13135 { 13136 name: "NOR", 13137 argLen: 2, 13138 commutative: true, 13139 asm: mips.ANOR, 13140 reg: regInfo{ 13141 inputs: []inputInfo{ 13142 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13143 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13144 }, 13145 outputs: []outputInfo{ 13146 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13147 }, 13148 }, 13149 }, 13150 { 13151 name: "NORconst", 13152 auxType: auxInt32, 13153 argLen: 1, 13154 asm: mips.ANOR, 13155 reg: regInfo{ 13156 inputs: []inputInfo{ 13157 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13158 }, 13159 outputs: []outputInfo{ 13160 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13161 }, 13162 }, 13163 }, 13164 { 13165 name: "NEG", 13166 argLen: 1, 13167 reg: regInfo{ 13168 inputs: []inputInfo{ 13169 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13170 }, 13171 outputs: []outputInfo{ 13172 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13173 }, 13174 }, 13175 }, 13176 { 13177 name: "NEGF", 13178 argLen: 1, 13179 asm: mips.ANEGF, 13180 reg: regInfo{ 13181 inputs: []inputInfo{ 13182 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13183 }, 13184 outputs: []outputInfo{ 13185 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13186 }, 13187 }, 13188 }, 13189 { 13190 name: "NEGD", 13191 argLen: 1, 13192 asm: mips.ANEGD, 13193 reg: regInfo{ 13194 inputs: []inputInfo{ 13195 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13196 }, 13197 outputs: []outputInfo{ 13198 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13199 }, 13200 }, 13201 }, 13202 { 13203 name: "SQRTD", 13204 argLen: 1, 13205 asm: mips.ASQRTD, 13206 reg: regInfo{ 13207 inputs: []inputInfo{ 13208 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13209 }, 13210 outputs: []outputInfo{ 13211 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13212 }, 13213 }, 13214 }, 13215 { 13216 name: "SLL", 13217 argLen: 2, 13218 asm: mips.ASLL, 13219 reg: regInfo{ 13220 inputs: []inputInfo{ 13221 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13222 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13223 }, 13224 outputs: []outputInfo{ 13225 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13226 }, 13227 }, 13228 }, 13229 { 13230 name: "SLLconst", 13231 auxType: auxInt32, 13232 argLen: 1, 13233 asm: mips.ASLL, 13234 reg: regInfo{ 13235 inputs: []inputInfo{ 13236 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13237 }, 13238 outputs: []outputInfo{ 13239 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13240 }, 13241 }, 13242 }, 13243 { 13244 name: "SRL", 13245 argLen: 2, 13246 asm: mips.ASRL, 13247 reg: regInfo{ 13248 inputs: []inputInfo{ 13249 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13250 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13251 }, 13252 outputs: []outputInfo{ 13253 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13254 }, 13255 }, 13256 }, 13257 { 13258 name: "SRLconst", 13259 auxType: auxInt32, 13260 argLen: 1, 13261 asm: mips.ASRL, 13262 reg: regInfo{ 13263 inputs: []inputInfo{ 13264 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13265 }, 13266 outputs: []outputInfo{ 13267 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13268 }, 13269 }, 13270 }, 13271 { 13272 name: "SRA", 13273 argLen: 2, 13274 asm: mips.ASRA, 13275 reg: regInfo{ 13276 inputs: []inputInfo{ 13277 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13278 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13279 }, 13280 outputs: []outputInfo{ 13281 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13282 }, 13283 }, 13284 }, 13285 { 13286 name: "SRAconst", 13287 auxType: auxInt32, 13288 argLen: 1, 13289 asm: mips.ASRA, 13290 reg: regInfo{ 13291 inputs: []inputInfo{ 13292 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13293 }, 13294 outputs: []outputInfo{ 13295 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13296 }, 13297 }, 13298 }, 13299 { 13300 name: "CLZ", 13301 argLen: 1, 13302 asm: mips.ACLZ, 13303 reg: regInfo{ 13304 inputs: []inputInfo{ 13305 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13306 }, 13307 outputs: []outputInfo{ 13308 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13309 }, 13310 }, 13311 }, 13312 { 13313 name: "SGT", 13314 argLen: 2, 13315 asm: mips.ASGT, 13316 reg: regInfo{ 13317 inputs: []inputInfo{ 13318 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13319 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13320 }, 13321 outputs: []outputInfo{ 13322 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13323 }, 13324 }, 13325 }, 13326 { 13327 name: "SGTconst", 13328 auxType: auxInt32, 13329 argLen: 1, 13330 asm: mips.ASGT, 13331 reg: regInfo{ 13332 inputs: []inputInfo{ 13333 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13334 }, 13335 outputs: []outputInfo{ 13336 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13337 }, 13338 }, 13339 }, 13340 { 13341 name: "SGTzero", 13342 argLen: 1, 13343 asm: mips.ASGT, 13344 reg: regInfo{ 13345 inputs: []inputInfo{ 13346 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13347 }, 13348 outputs: []outputInfo{ 13349 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13350 }, 13351 }, 13352 }, 13353 { 13354 name: "SGTU", 13355 argLen: 2, 13356 asm: mips.ASGTU, 13357 reg: regInfo{ 13358 inputs: []inputInfo{ 13359 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13360 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13361 }, 13362 outputs: []outputInfo{ 13363 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13364 }, 13365 }, 13366 }, 13367 { 13368 name: "SGTUconst", 13369 auxType: auxInt32, 13370 argLen: 1, 13371 asm: mips.ASGTU, 13372 reg: regInfo{ 13373 inputs: []inputInfo{ 13374 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13375 }, 13376 outputs: []outputInfo{ 13377 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13378 }, 13379 }, 13380 }, 13381 { 13382 name: "SGTUzero", 13383 argLen: 1, 13384 asm: mips.ASGTU, 13385 reg: regInfo{ 13386 inputs: []inputInfo{ 13387 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13388 }, 13389 outputs: []outputInfo{ 13390 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13391 }, 13392 }, 13393 }, 13394 { 13395 name: "CMPEQF", 13396 argLen: 2, 13397 asm: mips.ACMPEQF, 13398 reg: regInfo{ 13399 inputs: []inputInfo{ 13400 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13401 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13402 }, 13403 }, 13404 }, 13405 { 13406 name: "CMPEQD", 13407 argLen: 2, 13408 asm: mips.ACMPEQD, 13409 reg: regInfo{ 13410 inputs: []inputInfo{ 13411 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13412 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13413 }, 13414 }, 13415 }, 13416 { 13417 name: "CMPGEF", 13418 argLen: 2, 13419 asm: mips.ACMPGEF, 13420 reg: regInfo{ 13421 inputs: []inputInfo{ 13422 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13423 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13424 }, 13425 }, 13426 }, 13427 { 13428 name: "CMPGED", 13429 argLen: 2, 13430 asm: mips.ACMPGED, 13431 reg: regInfo{ 13432 inputs: []inputInfo{ 13433 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13434 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13435 }, 13436 }, 13437 }, 13438 { 13439 name: "CMPGTF", 13440 argLen: 2, 13441 asm: mips.ACMPGTF, 13442 reg: regInfo{ 13443 inputs: []inputInfo{ 13444 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13445 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13446 }, 13447 }, 13448 }, 13449 { 13450 name: "CMPGTD", 13451 argLen: 2, 13452 asm: mips.ACMPGTD, 13453 reg: regInfo{ 13454 inputs: []inputInfo{ 13455 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13456 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13457 }, 13458 }, 13459 }, 13460 { 13461 name: "MOVWconst", 13462 auxType: auxInt32, 13463 argLen: 0, 13464 rematerializeable: true, 13465 asm: mips.AMOVW, 13466 reg: regInfo{ 13467 outputs: []outputInfo{ 13468 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13469 }, 13470 }, 13471 }, 13472 { 13473 name: "MOVFconst", 13474 auxType: auxFloat32, 13475 argLen: 0, 13476 rematerializeable: true, 13477 asm: mips.AMOVF, 13478 reg: regInfo{ 13479 outputs: []outputInfo{ 13480 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13481 }, 13482 }, 13483 }, 13484 { 13485 name: "MOVDconst", 13486 auxType: auxFloat64, 13487 argLen: 0, 13488 rematerializeable: true, 13489 asm: mips.AMOVD, 13490 reg: regInfo{ 13491 outputs: []outputInfo{ 13492 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13493 }, 13494 }, 13495 }, 13496 { 13497 name: "MOVWaddr", 13498 auxType: auxSymOff, 13499 argLen: 1, 13500 rematerializeable: true, 13501 asm: mips.AMOVW, 13502 reg: regInfo{ 13503 inputs: []inputInfo{ 13504 {0, 140737555464192}, // SP SB 13505 }, 13506 outputs: []outputInfo{ 13507 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13508 }, 13509 }, 13510 }, 13511 { 13512 name: "MOVBload", 13513 auxType: auxSymOff, 13514 argLen: 2, 13515 faultOnNilArg0: true, 13516 asm: mips.AMOVB, 13517 reg: regInfo{ 13518 inputs: []inputInfo{ 13519 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13520 }, 13521 outputs: []outputInfo{ 13522 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13523 }, 13524 }, 13525 }, 13526 { 13527 name: "MOVBUload", 13528 auxType: auxSymOff, 13529 argLen: 2, 13530 faultOnNilArg0: true, 13531 asm: mips.AMOVBU, 13532 reg: regInfo{ 13533 inputs: []inputInfo{ 13534 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13535 }, 13536 outputs: []outputInfo{ 13537 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13538 }, 13539 }, 13540 }, 13541 { 13542 name: "MOVHload", 13543 auxType: auxSymOff, 13544 argLen: 2, 13545 faultOnNilArg0: true, 13546 asm: mips.AMOVH, 13547 reg: regInfo{ 13548 inputs: []inputInfo{ 13549 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13550 }, 13551 outputs: []outputInfo{ 13552 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13553 }, 13554 }, 13555 }, 13556 { 13557 name: "MOVHUload", 13558 auxType: auxSymOff, 13559 argLen: 2, 13560 faultOnNilArg0: true, 13561 asm: mips.AMOVHU, 13562 reg: regInfo{ 13563 inputs: []inputInfo{ 13564 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13565 }, 13566 outputs: []outputInfo{ 13567 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13568 }, 13569 }, 13570 }, 13571 { 13572 name: "MOVWload", 13573 auxType: auxSymOff, 13574 argLen: 2, 13575 faultOnNilArg0: true, 13576 asm: mips.AMOVW, 13577 reg: regInfo{ 13578 inputs: []inputInfo{ 13579 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13580 }, 13581 outputs: []outputInfo{ 13582 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13583 }, 13584 }, 13585 }, 13586 { 13587 name: "MOVFload", 13588 auxType: auxSymOff, 13589 argLen: 2, 13590 faultOnNilArg0: true, 13591 asm: mips.AMOVF, 13592 reg: regInfo{ 13593 inputs: []inputInfo{ 13594 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13595 }, 13596 outputs: []outputInfo{ 13597 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13598 }, 13599 }, 13600 }, 13601 { 13602 name: "MOVDload", 13603 auxType: auxSymOff, 13604 argLen: 2, 13605 faultOnNilArg0: true, 13606 asm: mips.AMOVD, 13607 reg: regInfo{ 13608 inputs: []inputInfo{ 13609 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13610 }, 13611 outputs: []outputInfo{ 13612 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13613 }, 13614 }, 13615 }, 13616 { 13617 name: "MOVBstore", 13618 auxType: auxSymOff, 13619 argLen: 3, 13620 faultOnNilArg0: true, 13621 asm: mips.AMOVB, 13622 reg: regInfo{ 13623 inputs: []inputInfo{ 13624 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13625 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13626 }, 13627 }, 13628 }, 13629 { 13630 name: "MOVHstore", 13631 auxType: auxSymOff, 13632 argLen: 3, 13633 faultOnNilArg0: true, 13634 asm: mips.AMOVH, 13635 reg: regInfo{ 13636 inputs: []inputInfo{ 13637 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13638 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13639 }, 13640 }, 13641 }, 13642 { 13643 name: "MOVWstore", 13644 auxType: auxSymOff, 13645 argLen: 3, 13646 faultOnNilArg0: true, 13647 asm: mips.AMOVW, 13648 reg: regInfo{ 13649 inputs: []inputInfo{ 13650 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13651 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13652 }, 13653 }, 13654 }, 13655 { 13656 name: "MOVFstore", 13657 auxType: auxSymOff, 13658 argLen: 3, 13659 faultOnNilArg0: true, 13660 asm: mips.AMOVF, 13661 reg: regInfo{ 13662 inputs: []inputInfo{ 13663 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13664 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13665 }, 13666 }, 13667 }, 13668 { 13669 name: "MOVDstore", 13670 auxType: auxSymOff, 13671 argLen: 3, 13672 faultOnNilArg0: true, 13673 asm: mips.AMOVD, 13674 reg: regInfo{ 13675 inputs: []inputInfo{ 13676 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13677 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13678 }, 13679 }, 13680 }, 13681 { 13682 name: "MOVBstorezero", 13683 auxType: auxSymOff, 13684 argLen: 2, 13685 faultOnNilArg0: true, 13686 asm: mips.AMOVB, 13687 reg: regInfo{ 13688 inputs: []inputInfo{ 13689 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13690 }, 13691 }, 13692 }, 13693 { 13694 name: "MOVHstorezero", 13695 auxType: auxSymOff, 13696 argLen: 2, 13697 faultOnNilArg0: true, 13698 asm: mips.AMOVH, 13699 reg: regInfo{ 13700 inputs: []inputInfo{ 13701 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13702 }, 13703 }, 13704 }, 13705 { 13706 name: "MOVWstorezero", 13707 auxType: auxSymOff, 13708 argLen: 2, 13709 faultOnNilArg0: true, 13710 asm: mips.AMOVW, 13711 reg: regInfo{ 13712 inputs: []inputInfo{ 13713 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13714 }, 13715 }, 13716 }, 13717 { 13718 name: "MOVBreg", 13719 argLen: 1, 13720 asm: mips.AMOVB, 13721 reg: regInfo{ 13722 inputs: []inputInfo{ 13723 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13724 }, 13725 outputs: []outputInfo{ 13726 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13727 }, 13728 }, 13729 }, 13730 { 13731 name: "MOVBUreg", 13732 argLen: 1, 13733 asm: mips.AMOVBU, 13734 reg: regInfo{ 13735 inputs: []inputInfo{ 13736 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13737 }, 13738 outputs: []outputInfo{ 13739 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13740 }, 13741 }, 13742 }, 13743 { 13744 name: "MOVHreg", 13745 argLen: 1, 13746 asm: mips.AMOVH, 13747 reg: regInfo{ 13748 inputs: []inputInfo{ 13749 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13750 }, 13751 outputs: []outputInfo{ 13752 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13753 }, 13754 }, 13755 }, 13756 { 13757 name: "MOVHUreg", 13758 argLen: 1, 13759 asm: mips.AMOVHU, 13760 reg: regInfo{ 13761 inputs: []inputInfo{ 13762 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13763 }, 13764 outputs: []outputInfo{ 13765 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13766 }, 13767 }, 13768 }, 13769 { 13770 name: "MOVWreg", 13771 argLen: 1, 13772 asm: mips.AMOVW, 13773 reg: regInfo{ 13774 inputs: []inputInfo{ 13775 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13776 }, 13777 outputs: []outputInfo{ 13778 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13779 }, 13780 }, 13781 }, 13782 { 13783 name: "MOVWnop", 13784 argLen: 1, 13785 resultInArg0: true, 13786 reg: regInfo{ 13787 inputs: []inputInfo{ 13788 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13789 }, 13790 outputs: []outputInfo{ 13791 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13792 }, 13793 }, 13794 }, 13795 { 13796 name: "CMOVZ", 13797 argLen: 3, 13798 resultInArg0: true, 13799 asm: mips.ACMOVZ, 13800 reg: regInfo{ 13801 inputs: []inputInfo{ 13802 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13803 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13804 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13805 }, 13806 outputs: []outputInfo{ 13807 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13808 }, 13809 }, 13810 }, 13811 { 13812 name: "CMOVZzero", 13813 argLen: 2, 13814 resultInArg0: true, 13815 asm: mips.ACMOVZ, 13816 reg: regInfo{ 13817 inputs: []inputInfo{ 13818 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13819 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13820 }, 13821 outputs: []outputInfo{ 13822 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13823 }, 13824 }, 13825 }, 13826 { 13827 name: "MOVWF", 13828 argLen: 1, 13829 asm: mips.AMOVWF, 13830 reg: regInfo{ 13831 inputs: []inputInfo{ 13832 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13833 }, 13834 outputs: []outputInfo{ 13835 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13836 }, 13837 }, 13838 }, 13839 { 13840 name: "MOVWD", 13841 argLen: 1, 13842 asm: mips.AMOVWD, 13843 reg: regInfo{ 13844 inputs: []inputInfo{ 13845 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13846 }, 13847 outputs: []outputInfo{ 13848 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13849 }, 13850 }, 13851 }, 13852 { 13853 name: "TRUNCFW", 13854 argLen: 1, 13855 asm: mips.ATRUNCFW, 13856 reg: regInfo{ 13857 inputs: []inputInfo{ 13858 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13859 }, 13860 outputs: []outputInfo{ 13861 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13862 }, 13863 }, 13864 }, 13865 { 13866 name: "TRUNCDW", 13867 argLen: 1, 13868 asm: mips.ATRUNCDW, 13869 reg: regInfo{ 13870 inputs: []inputInfo{ 13871 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13872 }, 13873 outputs: []outputInfo{ 13874 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13875 }, 13876 }, 13877 }, 13878 { 13879 name: "MOVFD", 13880 argLen: 1, 13881 asm: mips.AMOVFD, 13882 reg: regInfo{ 13883 inputs: []inputInfo{ 13884 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13885 }, 13886 outputs: []outputInfo{ 13887 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13888 }, 13889 }, 13890 }, 13891 { 13892 name: "MOVDF", 13893 argLen: 1, 13894 asm: mips.AMOVDF, 13895 reg: regInfo{ 13896 inputs: []inputInfo{ 13897 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13898 }, 13899 outputs: []outputInfo{ 13900 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 13901 }, 13902 }, 13903 }, 13904 { 13905 name: "CALLstatic", 13906 auxType: auxSymOff, 13907 argLen: 1, 13908 clobberFlags: true, 13909 call: true, 13910 reg: regInfo{ 13911 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13912 }, 13913 }, 13914 { 13915 name: "CALLclosure", 13916 auxType: auxInt32, 13917 argLen: 3, 13918 clobberFlags: true, 13919 call: true, 13920 reg: regInfo{ 13921 inputs: []inputInfo{ 13922 {1, 4194304}, // R22 13923 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 13924 }, 13925 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13926 }, 13927 }, 13928 { 13929 name: "CALLdefer", 13930 auxType: auxInt32, 13931 argLen: 1, 13932 clobberFlags: true, 13933 call: true, 13934 reg: regInfo{ 13935 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13936 }, 13937 }, 13938 { 13939 name: "CALLgo", 13940 auxType: auxInt32, 13941 argLen: 1, 13942 clobberFlags: true, 13943 call: true, 13944 reg: regInfo{ 13945 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13946 }, 13947 }, 13948 { 13949 name: "CALLinter", 13950 auxType: auxInt32, 13951 argLen: 2, 13952 clobberFlags: true, 13953 call: true, 13954 reg: regInfo{ 13955 inputs: []inputInfo{ 13956 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13957 }, 13958 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 13959 }, 13960 }, 13961 { 13962 name: "LoweredAtomicLoad", 13963 argLen: 2, 13964 faultOnNilArg0: true, 13965 reg: regInfo{ 13966 inputs: []inputInfo{ 13967 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13968 }, 13969 outputs: []outputInfo{ 13970 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 13971 }, 13972 }, 13973 }, 13974 { 13975 name: "LoweredAtomicStore", 13976 argLen: 3, 13977 faultOnNilArg0: true, 13978 reg: regInfo{ 13979 inputs: []inputInfo{ 13980 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 13981 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13982 }, 13983 }, 13984 }, 13985 { 13986 name: "LoweredAtomicStorezero", 13987 argLen: 2, 13988 faultOnNilArg0: true, 13989 reg: regInfo{ 13990 inputs: []inputInfo{ 13991 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 13992 }, 13993 }, 13994 }, 13995 { 13996 name: "LoweredAtomicExchange", 13997 argLen: 3, 13998 resultNotInArgs: true, 13999 faultOnNilArg0: true, 14000 reg: regInfo{ 14001 inputs: []inputInfo{ 14002 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14003 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14004 }, 14005 outputs: []outputInfo{ 14006 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14007 }, 14008 }, 14009 }, 14010 { 14011 name: "LoweredAtomicAdd", 14012 argLen: 3, 14013 resultNotInArgs: true, 14014 faultOnNilArg0: true, 14015 reg: regInfo{ 14016 inputs: []inputInfo{ 14017 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14018 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14019 }, 14020 outputs: []outputInfo{ 14021 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14022 }, 14023 }, 14024 }, 14025 { 14026 name: "LoweredAtomicAddconst", 14027 auxType: auxInt32, 14028 argLen: 2, 14029 resultNotInArgs: true, 14030 faultOnNilArg0: true, 14031 reg: regInfo{ 14032 inputs: []inputInfo{ 14033 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14034 }, 14035 outputs: []outputInfo{ 14036 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14037 }, 14038 }, 14039 }, 14040 { 14041 name: "LoweredAtomicCas", 14042 argLen: 4, 14043 resultNotInArgs: true, 14044 faultOnNilArg0: true, 14045 reg: regInfo{ 14046 inputs: []inputInfo{ 14047 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14048 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14049 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14050 }, 14051 outputs: []outputInfo{ 14052 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14053 }, 14054 }, 14055 }, 14056 { 14057 name: "LoweredAtomicAnd", 14058 argLen: 3, 14059 faultOnNilArg0: true, 14060 asm: mips.AAND, 14061 reg: regInfo{ 14062 inputs: []inputInfo{ 14063 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14064 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14065 }, 14066 }, 14067 }, 14068 { 14069 name: "LoweredAtomicOr", 14070 argLen: 3, 14071 faultOnNilArg0: true, 14072 asm: mips.AOR, 14073 reg: regInfo{ 14074 inputs: []inputInfo{ 14075 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14076 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 14077 }, 14078 }, 14079 }, 14080 { 14081 name: "LoweredZero", 14082 auxType: auxInt32, 14083 argLen: 3, 14084 faultOnNilArg0: true, 14085 reg: regInfo{ 14086 inputs: []inputInfo{ 14087 {0, 2}, // R1 14088 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14089 }, 14090 clobbers: 2, // R1 14091 }, 14092 }, 14093 { 14094 name: "LoweredMove", 14095 auxType: auxInt32, 14096 argLen: 4, 14097 faultOnNilArg0: true, 14098 faultOnNilArg1: true, 14099 reg: regInfo{ 14100 inputs: []inputInfo{ 14101 {0, 4}, // R2 14102 {1, 2}, // R1 14103 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14104 }, 14105 clobbers: 6, // R1 R2 14106 }, 14107 }, 14108 { 14109 name: "LoweredNilCheck", 14110 argLen: 2, 14111 nilCheck: true, 14112 faultOnNilArg0: true, 14113 reg: regInfo{ 14114 inputs: []inputInfo{ 14115 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14116 }, 14117 }, 14118 }, 14119 { 14120 name: "FPFlagTrue", 14121 argLen: 1, 14122 reg: regInfo{ 14123 outputs: []outputInfo{ 14124 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14125 }, 14126 }, 14127 }, 14128 { 14129 name: "FPFlagFalse", 14130 argLen: 1, 14131 reg: regInfo{ 14132 outputs: []outputInfo{ 14133 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14134 }, 14135 }, 14136 }, 14137 { 14138 name: "LoweredGetClosurePtr", 14139 argLen: 0, 14140 reg: regInfo{ 14141 outputs: []outputInfo{ 14142 {0, 4194304}, // R22 14143 }, 14144 }, 14145 }, 14146 { 14147 name: "MOVWconvert", 14148 argLen: 2, 14149 asm: mips.AMOVW, 14150 reg: regInfo{ 14151 inputs: []inputInfo{ 14152 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14153 }, 14154 outputs: []outputInfo{ 14155 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14156 }, 14157 }, 14158 }, 14159 14160 { 14161 name: "ADDV", 14162 argLen: 2, 14163 commutative: true, 14164 asm: mips.AADDVU, 14165 reg: regInfo{ 14166 inputs: []inputInfo{ 14167 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14168 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14169 }, 14170 outputs: []outputInfo{ 14171 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14172 }, 14173 }, 14174 }, 14175 { 14176 name: "ADDVconst", 14177 auxType: auxInt64, 14178 argLen: 1, 14179 asm: mips.AADDVU, 14180 reg: regInfo{ 14181 inputs: []inputInfo{ 14182 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 14183 }, 14184 outputs: []outputInfo{ 14185 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14186 }, 14187 }, 14188 }, 14189 { 14190 name: "SUBV", 14191 argLen: 2, 14192 asm: mips.ASUBVU, 14193 reg: regInfo{ 14194 inputs: []inputInfo{ 14195 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14196 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14197 }, 14198 outputs: []outputInfo{ 14199 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14200 }, 14201 }, 14202 }, 14203 { 14204 name: "SUBVconst", 14205 auxType: auxInt64, 14206 argLen: 1, 14207 asm: mips.ASUBVU, 14208 reg: regInfo{ 14209 inputs: []inputInfo{ 14210 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14211 }, 14212 outputs: []outputInfo{ 14213 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14214 }, 14215 }, 14216 }, 14217 { 14218 name: "MULV", 14219 argLen: 2, 14220 commutative: true, 14221 asm: mips.AMULV, 14222 reg: regInfo{ 14223 inputs: []inputInfo{ 14224 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14225 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14226 }, 14227 outputs: []outputInfo{ 14228 {0, 1152921504606846976}, // HI 14229 {1, 2305843009213693952}, // LO 14230 }, 14231 }, 14232 }, 14233 { 14234 name: "MULVU", 14235 argLen: 2, 14236 commutative: true, 14237 asm: mips.AMULVU, 14238 reg: regInfo{ 14239 inputs: []inputInfo{ 14240 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14241 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14242 }, 14243 outputs: []outputInfo{ 14244 {0, 1152921504606846976}, // HI 14245 {1, 2305843009213693952}, // LO 14246 }, 14247 }, 14248 }, 14249 { 14250 name: "DIVV", 14251 argLen: 2, 14252 asm: mips.ADIVV, 14253 reg: regInfo{ 14254 inputs: []inputInfo{ 14255 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14256 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14257 }, 14258 outputs: []outputInfo{ 14259 {0, 1152921504606846976}, // HI 14260 {1, 2305843009213693952}, // LO 14261 }, 14262 }, 14263 }, 14264 { 14265 name: "DIVVU", 14266 argLen: 2, 14267 asm: mips.ADIVVU, 14268 reg: regInfo{ 14269 inputs: []inputInfo{ 14270 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14271 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14272 }, 14273 outputs: []outputInfo{ 14274 {0, 1152921504606846976}, // HI 14275 {1, 2305843009213693952}, // LO 14276 }, 14277 }, 14278 }, 14279 { 14280 name: "ADDF", 14281 argLen: 2, 14282 commutative: true, 14283 asm: mips.AADDF, 14284 reg: regInfo{ 14285 inputs: []inputInfo{ 14286 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14287 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14288 }, 14289 outputs: []outputInfo{ 14290 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14291 }, 14292 }, 14293 }, 14294 { 14295 name: "ADDD", 14296 argLen: 2, 14297 commutative: true, 14298 asm: mips.AADDD, 14299 reg: regInfo{ 14300 inputs: []inputInfo{ 14301 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14302 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14303 }, 14304 outputs: []outputInfo{ 14305 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14306 }, 14307 }, 14308 }, 14309 { 14310 name: "SUBF", 14311 argLen: 2, 14312 asm: mips.ASUBF, 14313 reg: regInfo{ 14314 inputs: []inputInfo{ 14315 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14316 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14317 }, 14318 outputs: []outputInfo{ 14319 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14320 }, 14321 }, 14322 }, 14323 { 14324 name: "SUBD", 14325 argLen: 2, 14326 asm: mips.ASUBD, 14327 reg: regInfo{ 14328 inputs: []inputInfo{ 14329 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14330 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14331 }, 14332 outputs: []outputInfo{ 14333 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14334 }, 14335 }, 14336 }, 14337 { 14338 name: "MULF", 14339 argLen: 2, 14340 commutative: true, 14341 asm: mips.AMULF, 14342 reg: regInfo{ 14343 inputs: []inputInfo{ 14344 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14345 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14346 }, 14347 outputs: []outputInfo{ 14348 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14349 }, 14350 }, 14351 }, 14352 { 14353 name: "MULD", 14354 argLen: 2, 14355 commutative: true, 14356 asm: mips.AMULD, 14357 reg: regInfo{ 14358 inputs: []inputInfo{ 14359 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14360 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14361 }, 14362 outputs: []outputInfo{ 14363 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14364 }, 14365 }, 14366 }, 14367 { 14368 name: "DIVF", 14369 argLen: 2, 14370 asm: mips.ADIVF, 14371 reg: regInfo{ 14372 inputs: []inputInfo{ 14373 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14374 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14375 }, 14376 outputs: []outputInfo{ 14377 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14378 }, 14379 }, 14380 }, 14381 { 14382 name: "DIVD", 14383 argLen: 2, 14384 asm: mips.ADIVD, 14385 reg: regInfo{ 14386 inputs: []inputInfo{ 14387 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14388 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14389 }, 14390 outputs: []outputInfo{ 14391 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14392 }, 14393 }, 14394 }, 14395 { 14396 name: "AND", 14397 argLen: 2, 14398 commutative: true, 14399 asm: mips.AAND, 14400 reg: regInfo{ 14401 inputs: []inputInfo{ 14402 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14403 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14404 }, 14405 outputs: []outputInfo{ 14406 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14407 }, 14408 }, 14409 }, 14410 { 14411 name: "ANDconst", 14412 auxType: auxInt64, 14413 argLen: 1, 14414 asm: mips.AAND, 14415 reg: regInfo{ 14416 inputs: []inputInfo{ 14417 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14418 }, 14419 outputs: []outputInfo{ 14420 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14421 }, 14422 }, 14423 }, 14424 { 14425 name: "OR", 14426 argLen: 2, 14427 commutative: true, 14428 asm: mips.AOR, 14429 reg: regInfo{ 14430 inputs: []inputInfo{ 14431 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14432 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14433 }, 14434 outputs: []outputInfo{ 14435 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14436 }, 14437 }, 14438 }, 14439 { 14440 name: "ORconst", 14441 auxType: auxInt64, 14442 argLen: 1, 14443 asm: mips.AOR, 14444 reg: regInfo{ 14445 inputs: []inputInfo{ 14446 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14447 }, 14448 outputs: []outputInfo{ 14449 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14450 }, 14451 }, 14452 }, 14453 { 14454 name: "XOR", 14455 argLen: 2, 14456 commutative: true, 14457 asm: mips.AXOR, 14458 reg: regInfo{ 14459 inputs: []inputInfo{ 14460 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14461 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14462 }, 14463 outputs: []outputInfo{ 14464 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14465 }, 14466 }, 14467 }, 14468 { 14469 name: "XORconst", 14470 auxType: auxInt64, 14471 argLen: 1, 14472 asm: mips.AXOR, 14473 reg: regInfo{ 14474 inputs: []inputInfo{ 14475 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14476 }, 14477 outputs: []outputInfo{ 14478 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14479 }, 14480 }, 14481 }, 14482 { 14483 name: "NOR", 14484 argLen: 2, 14485 commutative: true, 14486 asm: mips.ANOR, 14487 reg: regInfo{ 14488 inputs: []inputInfo{ 14489 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14490 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14491 }, 14492 outputs: []outputInfo{ 14493 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14494 }, 14495 }, 14496 }, 14497 { 14498 name: "NORconst", 14499 auxType: auxInt64, 14500 argLen: 1, 14501 asm: mips.ANOR, 14502 reg: regInfo{ 14503 inputs: []inputInfo{ 14504 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14505 }, 14506 outputs: []outputInfo{ 14507 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14508 }, 14509 }, 14510 }, 14511 { 14512 name: "NEGV", 14513 argLen: 1, 14514 reg: regInfo{ 14515 inputs: []inputInfo{ 14516 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14517 }, 14518 outputs: []outputInfo{ 14519 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14520 }, 14521 }, 14522 }, 14523 { 14524 name: "NEGF", 14525 argLen: 1, 14526 asm: mips.ANEGF, 14527 reg: regInfo{ 14528 inputs: []inputInfo{ 14529 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14530 }, 14531 outputs: []outputInfo{ 14532 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14533 }, 14534 }, 14535 }, 14536 { 14537 name: "NEGD", 14538 argLen: 1, 14539 asm: mips.ANEGD, 14540 reg: regInfo{ 14541 inputs: []inputInfo{ 14542 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14543 }, 14544 outputs: []outputInfo{ 14545 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14546 }, 14547 }, 14548 }, 14549 { 14550 name: "SLLV", 14551 argLen: 2, 14552 asm: mips.ASLLV, 14553 reg: regInfo{ 14554 inputs: []inputInfo{ 14555 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14556 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14557 }, 14558 outputs: []outputInfo{ 14559 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14560 }, 14561 }, 14562 }, 14563 { 14564 name: "SLLVconst", 14565 auxType: auxInt64, 14566 argLen: 1, 14567 asm: mips.ASLLV, 14568 reg: regInfo{ 14569 inputs: []inputInfo{ 14570 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14571 }, 14572 outputs: []outputInfo{ 14573 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14574 }, 14575 }, 14576 }, 14577 { 14578 name: "SRLV", 14579 argLen: 2, 14580 asm: mips.ASRLV, 14581 reg: regInfo{ 14582 inputs: []inputInfo{ 14583 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14584 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14585 }, 14586 outputs: []outputInfo{ 14587 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14588 }, 14589 }, 14590 }, 14591 { 14592 name: "SRLVconst", 14593 auxType: auxInt64, 14594 argLen: 1, 14595 asm: mips.ASRLV, 14596 reg: regInfo{ 14597 inputs: []inputInfo{ 14598 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14599 }, 14600 outputs: []outputInfo{ 14601 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14602 }, 14603 }, 14604 }, 14605 { 14606 name: "SRAV", 14607 argLen: 2, 14608 asm: mips.ASRAV, 14609 reg: regInfo{ 14610 inputs: []inputInfo{ 14611 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14612 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14613 }, 14614 outputs: []outputInfo{ 14615 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14616 }, 14617 }, 14618 }, 14619 { 14620 name: "SRAVconst", 14621 auxType: auxInt64, 14622 argLen: 1, 14623 asm: mips.ASRAV, 14624 reg: regInfo{ 14625 inputs: []inputInfo{ 14626 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14627 }, 14628 outputs: []outputInfo{ 14629 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14630 }, 14631 }, 14632 }, 14633 { 14634 name: "SGT", 14635 argLen: 2, 14636 asm: mips.ASGT, 14637 reg: regInfo{ 14638 inputs: []inputInfo{ 14639 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14640 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14641 }, 14642 outputs: []outputInfo{ 14643 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14644 }, 14645 }, 14646 }, 14647 { 14648 name: "SGTconst", 14649 auxType: auxInt64, 14650 argLen: 1, 14651 asm: mips.ASGT, 14652 reg: regInfo{ 14653 inputs: []inputInfo{ 14654 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14655 }, 14656 outputs: []outputInfo{ 14657 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14658 }, 14659 }, 14660 }, 14661 { 14662 name: "SGTU", 14663 argLen: 2, 14664 asm: mips.ASGTU, 14665 reg: regInfo{ 14666 inputs: []inputInfo{ 14667 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14668 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14669 }, 14670 outputs: []outputInfo{ 14671 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14672 }, 14673 }, 14674 }, 14675 { 14676 name: "SGTUconst", 14677 auxType: auxInt64, 14678 argLen: 1, 14679 asm: mips.ASGTU, 14680 reg: regInfo{ 14681 inputs: []inputInfo{ 14682 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14683 }, 14684 outputs: []outputInfo{ 14685 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14686 }, 14687 }, 14688 }, 14689 { 14690 name: "CMPEQF", 14691 argLen: 2, 14692 asm: mips.ACMPEQF, 14693 reg: regInfo{ 14694 inputs: []inputInfo{ 14695 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14696 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14697 }, 14698 }, 14699 }, 14700 { 14701 name: "CMPEQD", 14702 argLen: 2, 14703 asm: mips.ACMPEQD, 14704 reg: regInfo{ 14705 inputs: []inputInfo{ 14706 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14707 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14708 }, 14709 }, 14710 }, 14711 { 14712 name: "CMPGEF", 14713 argLen: 2, 14714 asm: mips.ACMPGEF, 14715 reg: regInfo{ 14716 inputs: []inputInfo{ 14717 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14718 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14719 }, 14720 }, 14721 }, 14722 { 14723 name: "CMPGED", 14724 argLen: 2, 14725 asm: mips.ACMPGED, 14726 reg: regInfo{ 14727 inputs: []inputInfo{ 14728 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14729 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14730 }, 14731 }, 14732 }, 14733 { 14734 name: "CMPGTF", 14735 argLen: 2, 14736 asm: mips.ACMPGTF, 14737 reg: regInfo{ 14738 inputs: []inputInfo{ 14739 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14740 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14741 }, 14742 }, 14743 }, 14744 { 14745 name: "CMPGTD", 14746 argLen: 2, 14747 asm: mips.ACMPGTD, 14748 reg: regInfo{ 14749 inputs: []inputInfo{ 14750 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14751 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14752 }, 14753 }, 14754 }, 14755 { 14756 name: "MOVVconst", 14757 auxType: auxInt64, 14758 argLen: 0, 14759 rematerializeable: true, 14760 asm: mips.AMOVV, 14761 reg: regInfo{ 14762 outputs: []outputInfo{ 14763 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14764 }, 14765 }, 14766 }, 14767 { 14768 name: "MOVFconst", 14769 auxType: auxFloat64, 14770 argLen: 0, 14771 rematerializeable: true, 14772 asm: mips.AMOVF, 14773 reg: regInfo{ 14774 outputs: []outputInfo{ 14775 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14776 }, 14777 }, 14778 }, 14779 { 14780 name: "MOVDconst", 14781 auxType: auxFloat64, 14782 argLen: 0, 14783 rematerializeable: true, 14784 asm: mips.AMOVD, 14785 reg: regInfo{ 14786 outputs: []outputInfo{ 14787 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14788 }, 14789 }, 14790 }, 14791 { 14792 name: "MOVVaddr", 14793 auxType: auxSymOff, 14794 argLen: 1, 14795 rematerializeable: true, 14796 asm: mips.AMOVV, 14797 reg: regInfo{ 14798 inputs: []inputInfo{ 14799 {0, 4611686018460942336}, // SP SB 14800 }, 14801 outputs: []outputInfo{ 14802 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14803 }, 14804 }, 14805 }, 14806 { 14807 name: "MOVBload", 14808 auxType: auxSymOff, 14809 argLen: 2, 14810 faultOnNilArg0: true, 14811 asm: mips.AMOVB, 14812 reg: regInfo{ 14813 inputs: []inputInfo{ 14814 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14815 }, 14816 outputs: []outputInfo{ 14817 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14818 }, 14819 }, 14820 }, 14821 { 14822 name: "MOVBUload", 14823 auxType: auxSymOff, 14824 argLen: 2, 14825 faultOnNilArg0: true, 14826 asm: mips.AMOVBU, 14827 reg: regInfo{ 14828 inputs: []inputInfo{ 14829 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14830 }, 14831 outputs: []outputInfo{ 14832 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14833 }, 14834 }, 14835 }, 14836 { 14837 name: "MOVHload", 14838 auxType: auxSymOff, 14839 argLen: 2, 14840 faultOnNilArg0: true, 14841 asm: mips.AMOVH, 14842 reg: regInfo{ 14843 inputs: []inputInfo{ 14844 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14845 }, 14846 outputs: []outputInfo{ 14847 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14848 }, 14849 }, 14850 }, 14851 { 14852 name: "MOVHUload", 14853 auxType: auxSymOff, 14854 argLen: 2, 14855 faultOnNilArg0: true, 14856 asm: mips.AMOVHU, 14857 reg: regInfo{ 14858 inputs: []inputInfo{ 14859 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14860 }, 14861 outputs: []outputInfo{ 14862 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14863 }, 14864 }, 14865 }, 14866 { 14867 name: "MOVWload", 14868 auxType: auxSymOff, 14869 argLen: 2, 14870 faultOnNilArg0: true, 14871 asm: mips.AMOVW, 14872 reg: regInfo{ 14873 inputs: []inputInfo{ 14874 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14875 }, 14876 outputs: []outputInfo{ 14877 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14878 }, 14879 }, 14880 }, 14881 { 14882 name: "MOVWUload", 14883 auxType: auxSymOff, 14884 argLen: 2, 14885 faultOnNilArg0: true, 14886 asm: mips.AMOVWU, 14887 reg: regInfo{ 14888 inputs: []inputInfo{ 14889 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14890 }, 14891 outputs: []outputInfo{ 14892 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14893 }, 14894 }, 14895 }, 14896 { 14897 name: "MOVVload", 14898 auxType: auxSymOff, 14899 argLen: 2, 14900 faultOnNilArg0: true, 14901 asm: mips.AMOVV, 14902 reg: regInfo{ 14903 inputs: []inputInfo{ 14904 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14905 }, 14906 outputs: []outputInfo{ 14907 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 14908 }, 14909 }, 14910 }, 14911 { 14912 name: "MOVFload", 14913 auxType: auxSymOff, 14914 argLen: 2, 14915 faultOnNilArg0: true, 14916 asm: mips.AMOVF, 14917 reg: regInfo{ 14918 inputs: []inputInfo{ 14919 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14920 }, 14921 outputs: []outputInfo{ 14922 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14923 }, 14924 }, 14925 }, 14926 { 14927 name: "MOVDload", 14928 auxType: auxSymOff, 14929 argLen: 2, 14930 faultOnNilArg0: true, 14931 asm: mips.AMOVD, 14932 reg: regInfo{ 14933 inputs: []inputInfo{ 14934 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14935 }, 14936 outputs: []outputInfo{ 14937 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14938 }, 14939 }, 14940 }, 14941 { 14942 name: "MOVBstore", 14943 auxType: auxSymOff, 14944 argLen: 3, 14945 faultOnNilArg0: true, 14946 asm: mips.AMOVB, 14947 reg: regInfo{ 14948 inputs: []inputInfo{ 14949 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14950 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14951 }, 14952 }, 14953 }, 14954 { 14955 name: "MOVHstore", 14956 auxType: auxSymOff, 14957 argLen: 3, 14958 faultOnNilArg0: true, 14959 asm: mips.AMOVH, 14960 reg: regInfo{ 14961 inputs: []inputInfo{ 14962 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14963 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14964 }, 14965 }, 14966 }, 14967 { 14968 name: "MOVWstore", 14969 auxType: auxSymOff, 14970 argLen: 3, 14971 faultOnNilArg0: true, 14972 asm: mips.AMOVW, 14973 reg: regInfo{ 14974 inputs: []inputInfo{ 14975 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14976 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14977 }, 14978 }, 14979 }, 14980 { 14981 name: "MOVVstore", 14982 auxType: auxSymOff, 14983 argLen: 3, 14984 faultOnNilArg0: true, 14985 asm: mips.AMOVV, 14986 reg: regInfo{ 14987 inputs: []inputInfo{ 14988 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 14989 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 14990 }, 14991 }, 14992 }, 14993 { 14994 name: "MOVFstore", 14995 auxType: auxSymOff, 14996 argLen: 3, 14997 faultOnNilArg0: true, 14998 asm: mips.AMOVF, 14999 reg: regInfo{ 15000 inputs: []inputInfo{ 15001 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15002 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15003 }, 15004 }, 15005 }, 15006 { 15007 name: "MOVDstore", 15008 auxType: auxSymOff, 15009 argLen: 3, 15010 faultOnNilArg0: true, 15011 asm: mips.AMOVD, 15012 reg: regInfo{ 15013 inputs: []inputInfo{ 15014 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15015 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15016 }, 15017 }, 15018 }, 15019 { 15020 name: "MOVBstorezero", 15021 auxType: auxSymOff, 15022 argLen: 2, 15023 faultOnNilArg0: true, 15024 asm: mips.AMOVB, 15025 reg: regInfo{ 15026 inputs: []inputInfo{ 15027 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15028 }, 15029 }, 15030 }, 15031 { 15032 name: "MOVHstorezero", 15033 auxType: auxSymOff, 15034 argLen: 2, 15035 faultOnNilArg0: true, 15036 asm: mips.AMOVH, 15037 reg: regInfo{ 15038 inputs: []inputInfo{ 15039 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15040 }, 15041 }, 15042 }, 15043 { 15044 name: "MOVWstorezero", 15045 auxType: auxSymOff, 15046 argLen: 2, 15047 faultOnNilArg0: true, 15048 asm: mips.AMOVW, 15049 reg: regInfo{ 15050 inputs: []inputInfo{ 15051 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15052 }, 15053 }, 15054 }, 15055 { 15056 name: "MOVVstorezero", 15057 auxType: auxSymOff, 15058 argLen: 2, 15059 faultOnNilArg0: true, 15060 asm: mips.AMOVV, 15061 reg: regInfo{ 15062 inputs: []inputInfo{ 15063 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 15064 }, 15065 }, 15066 }, 15067 { 15068 name: "MOVBreg", 15069 argLen: 1, 15070 asm: mips.AMOVB, 15071 reg: regInfo{ 15072 inputs: []inputInfo{ 15073 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15074 }, 15075 outputs: []outputInfo{ 15076 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15077 }, 15078 }, 15079 }, 15080 { 15081 name: "MOVBUreg", 15082 argLen: 1, 15083 asm: mips.AMOVBU, 15084 reg: regInfo{ 15085 inputs: []inputInfo{ 15086 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15087 }, 15088 outputs: []outputInfo{ 15089 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15090 }, 15091 }, 15092 }, 15093 { 15094 name: "MOVHreg", 15095 argLen: 1, 15096 asm: mips.AMOVH, 15097 reg: regInfo{ 15098 inputs: []inputInfo{ 15099 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15100 }, 15101 outputs: []outputInfo{ 15102 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15103 }, 15104 }, 15105 }, 15106 { 15107 name: "MOVHUreg", 15108 argLen: 1, 15109 asm: mips.AMOVHU, 15110 reg: regInfo{ 15111 inputs: []inputInfo{ 15112 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15113 }, 15114 outputs: []outputInfo{ 15115 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15116 }, 15117 }, 15118 }, 15119 { 15120 name: "MOVWreg", 15121 argLen: 1, 15122 asm: mips.AMOVW, 15123 reg: regInfo{ 15124 inputs: []inputInfo{ 15125 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15126 }, 15127 outputs: []outputInfo{ 15128 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15129 }, 15130 }, 15131 }, 15132 { 15133 name: "MOVWUreg", 15134 argLen: 1, 15135 asm: mips.AMOVWU, 15136 reg: regInfo{ 15137 inputs: []inputInfo{ 15138 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15139 }, 15140 outputs: []outputInfo{ 15141 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15142 }, 15143 }, 15144 }, 15145 { 15146 name: "MOVVreg", 15147 argLen: 1, 15148 asm: mips.AMOVV, 15149 reg: regInfo{ 15150 inputs: []inputInfo{ 15151 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15152 }, 15153 outputs: []outputInfo{ 15154 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15155 }, 15156 }, 15157 }, 15158 { 15159 name: "MOVVnop", 15160 argLen: 1, 15161 resultInArg0: true, 15162 reg: regInfo{ 15163 inputs: []inputInfo{ 15164 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15165 }, 15166 outputs: []outputInfo{ 15167 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15168 }, 15169 }, 15170 }, 15171 { 15172 name: "MOVWF", 15173 argLen: 1, 15174 asm: mips.AMOVWF, 15175 reg: regInfo{ 15176 inputs: []inputInfo{ 15177 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15178 }, 15179 outputs: []outputInfo{ 15180 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15181 }, 15182 }, 15183 }, 15184 { 15185 name: "MOVWD", 15186 argLen: 1, 15187 asm: mips.AMOVWD, 15188 reg: regInfo{ 15189 inputs: []inputInfo{ 15190 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15191 }, 15192 outputs: []outputInfo{ 15193 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15194 }, 15195 }, 15196 }, 15197 { 15198 name: "MOVVF", 15199 argLen: 1, 15200 asm: mips.AMOVVF, 15201 reg: regInfo{ 15202 inputs: []inputInfo{ 15203 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15204 }, 15205 outputs: []outputInfo{ 15206 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15207 }, 15208 }, 15209 }, 15210 { 15211 name: "MOVVD", 15212 argLen: 1, 15213 asm: mips.AMOVVD, 15214 reg: regInfo{ 15215 inputs: []inputInfo{ 15216 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15217 }, 15218 outputs: []outputInfo{ 15219 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15220 }, 15221 }, 15222 }, 15223 { 15224 name: "TRUNCFW", 15225 argLen: 1, 15226 asm: mips.ATRUNCFW, 15227 reg: regInfo{ 15228 inputs: []inputInfo{ 15229 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15230 }, 15231 outputs: []outputInfo{ 15232 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15233 }, 15234 }, 15235 }, 15236 { 15237 name: "TRUNCDW", 15238 argLen: 1, 15239 asm: mips.ATRUNCDW, 15240 reg: regInfo{ 15241 inputs: []inputInfo{ 15242 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15243 }, 15244 outputs: []outputInfo{ 15245 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15246 }, 15247 }, 15248 }, 15249 { 15250 name: "TRUNCFV", 15251 argLen: 1, 15252 asm: mips.ATRUNCFV, 15253 reg: regInfo{ 15254 inputs: []inputInfo{ 15255 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15256 }, 15257 outputs: []outputInfo{ 15258 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15259 }, 15260 }, 15261 }, 15262 { 15263 name: "TRUNCDV", 15264 argLen: 1, 15265 asm: mips.ATRUNCDV, 15266 reg: regInfo{ 15267 inputs: []inputInfo{ 15268 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15269 }, 15270 outputs: []outputInfo{ 15271 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15272 }, 15273 }, 15274 }, 15275 { 15276 name: "MOVFD", 15277 argLen: 1, 15278 asm: mips.AMOVFD, 15279 reg: regInfo{ 15280 inputs: []inputInfo{ 15281 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15282 }, 15283 outputs: []outputInfo{ 15284 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15285 }, 15286 }, 15287 }, 15288 { 15289 name: "MOVDF", 15290 argLen: 1, 15291 asm: mips.AMOVDF, 15292 reg: regInfo{ 15293 inputs: []inputInfo{ 15294 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15295 }, 15296 outputs: []outputInfo{ 15297 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15298 }, 15299 }, 15300 }, 15301 { 15302 name: "CALLstatic", 15303 auxType: auxSymOff, 15304 argLen: 1, 15305 clobberFlags: true, 15306 call: true, 15307 reg: regInfo{ 15308 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15309 }, 15310 }, 15311 { 15312 name: "CALLclosure", 15313 auxType: auxInt64, 15314 argLen: 3, 15315 clobberFlags: true, 15316 call: true, 15317 reg: regInfo{ 15318 inputs: []inputInfo{ 15319 {1, 4194304}, // R22 15320 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 15321 }, 15322 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15323 }, 15324 }, 15325 { 15326 name: "CALLdefer", 15327 auxType: auxInt64, 15328 argLen: 1, 15329 clobberFlags: true, 15330 call: true, 15331 reg: regInfo{ 15332 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15333 }, 15334 }, 15335 { 15336 name: "CALLgo", 15337 auxType: auxInt64, 15338 argLen: 1, 15339 clobberFlags: true, 15340 call: true, 15341 reg: regInfo{ 15342 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15343 }, 15344 }, 15345 { 15346 name: "CALLinter", 15347 auxType: auxInt64, 15348 argLen: 2, 15349 clobberFlags: true, 15350 call: true, 15351 reg: regInfo{ 15352 inputs: []inputInfo{ 15353 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15354 }, 15355 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 15356 }, 15357 }, 15358 { 15359 name: "DUFFZERO", 15360 auxType: auxInt64, 15361 argLen: 2, 15362 faultOnNilArg0: true, 15363 reg: regInfo{ 15364 inputs: []inputInfo{ 15365 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15366 }, 15367 clobbers: 134217730, // R1 R31 15368 }, 15369 }, 15370 { 15371 name: "LoweredZero", 15372 auxType: auxInt64, 15373 argLen: 3, 15374 clobberFlags: true, 15375 faultOnNilArg0: true, 15376 reg: regInfo{ 15377 inputs: []inputInfo{ 15378 {0, 2}, // R1 15379 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15380 }, 15381 clobbers: 2, // R1 15382 }, 15383 }, 15384 { 15385 name: "LoweredMove", 15386 auxType: auxInt64, 15387 argLen: 4, 15388 clobberFlags: true, 15389 faultOnNilArg0: true, 15390 faultOnNilArg1: true, 15391 reg: regInfo{ 15392 inputs: []inputInfo{ 15393 {0, 4}, // R2 15394 {1, 2}, // R1 15395 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15396 }, 15397 clobbers: 6, // R1 R2 15398 }, 15399 }, 15400 { 15401 name: "LoweredNilCheck", 15402 argLen: 2, 15403 nilCheck: true, 15404 faultOnNilArg0: true, 15405 reg: regInfo{ 15406 inputs: []inputInfo{ 15407 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15408 }, 15409 }, 15410 }, 15411 { 15412 name: "FPFlagTrue", 15413 argLen: 1, 15414 reg: regInfo{ 15415 outputs: []outputInfo{ 15416 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15417 }, 15418 }, 15419 }, 15420 { 15421 name: "FPFlagFalse", 15422 argLen: 1, 15423 reg: regInfo{ 15424 outputs: []outputInfo{ 15425 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15426 }, 15427 }, 15428 }, 15429 { 15430 name: "LoweredGetClosurePtr", 15431 argLen: 0, 15432 reg: regInfo{ 15433 outputs: []outputInfo{ 15434 {0, 4194304}, // R22 15435 }, 15436 }, 15437 }, 15438 { 15439 name: "MOVVconvert", 15440 argLen: 2, 15441 asm: mips.AMOVV, 15442 reg: regInfo{ 15443 inputs: []inputInfo{ 15444 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15445 }, 15446 outputs: []outputInfo{ 15447 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15448 }, 15449 }, 15450 }, 15451 15452 { 15453 name: "ADD", 15454 argLen: 2, 15455 commutative: true, 15456 asm: ppc64.AADD, 15457 reg: regInfo{ 15458 inputs: []inputInfo{ 15459 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15460 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15461 }, 15462 outputs: []outputInfo{ 15463 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15464 }, 15465 }, 15466 }, 15467 { 15468 name: "ADDconst", 15469 auxType: auxSymOff, 15470 argLen: 1, 15471 asm: ppc64.AADD, 15472 reg: regInfo{ 15473 inputs: []inputInfo{ 15474 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15475 }, 15476 outputs: []outputInfo{ 15477 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15478 }, 15479 }, 15480 }, 15481 { 15482 name: "FADD", 15483 argLen: 2, 15484 commutative: true, 15485 asm: ppc64.AFADD, 15486 reg: regInfo{ 15487 inputs: []inputInfo{ 15488 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15489 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15490 }, 15491 outputs: []outputInfo{ 15492 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15493 }, 15494 }, 15495 }, 15496 { 15497 name: "FADDS", 15498 argLen: 2, 15499 commutative: true, 15500 asm: ppc64.AFADDS, 15501 reg: regInfo{ 15502 inputs: []inputInfo{ 15503 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15504 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15505 }, 15506 outputs: []outputInfo{ 15507 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15508 }, 15509 }, 15510 }, 15511 { 15512 name: "SUB", 15513 argLen: 2, 15514 asm: ppc64.ASUB, 15515 reg: regInfo{ 15516 inputs: []inputInfo{ 15517 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15518 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15519 }, 15520 outputs: []outputInfo{ 15521 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15522 }, 15523 }, 15524 }, 15525 { 15526 name: "FSUB", 15527 argLen: 2, 15528 asm: ppc64.AFSUB, 15529 reg: regInfo{ 15530 inputs: []inputInfo{ 15531 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15532 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15533 }, 15534 outputs: []outputInfo{ 15535 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15536 }, 15537 }, 15538 }, 15539 { 15540 name: "FSUBS", 15541 argLen: 2, 15542 asm: ppc64.AFSUBS, 15543 reg: regInfo{ 15544 inputs: []inputInfo{ 15545 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15546 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15547 }, 15548 outputs: []outputInfo{ 15549 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15550 }, 15551 }, 15552 }, 15553 { 15554 name: "MULLD", 15555 argLen: 2, 15556 commutative: true, 15557 asm: ppc64.AMULLD, 15558 reg: regInfo{ 15559 inputs: []inputInfo{ 15560 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15561 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15562 }, 15563 outputs: []outputInfo{ 15564 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15565 }, 15566 }, 15567 }, 15568 { 15569 name: "MULLW", 15570 argLen: 2, 15571 commutative: true, 15572 asm: ppc64.AMULLW, 15573 reg: regInfo{ 15574 inputs: []inputInfo{ 15575 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15576 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15577 }, 15578 outputs: []outputInfo{ 15579 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15580 }, 15581 }, 15582 }, 15583 { 15584 name: "MULHD", 15585 argLen: 2, 15586 commutative: true, 15587 asm: ppc64.AMULHD, 15588 reg: regInfo{ 15589 inputs: []inputInfo{ 15590 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15591 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15592 }, 15593 outputs: []outputInfo{ 15594 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15595 }, 15596 }, 15597 }, 15598 { 15599 name: "MULHW", 15600 argLen: 2, 15601 commutative: true, 15602 asm: ppc64.AMULHW, 15603 reg: regInfo{ 15604 inputs: []inputInfo{ 15605 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15606 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15607 }, 15608 outputs: []outputInfo{ 15609 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15610 }, 15611 }, 15612 }, 15613 { 15614 name: "MULHDU", 15615 argLen: 2, 15616 commutative: true, 15617 asm: ppc64.AMULHDU, 15618 reg: regInfo{ 15619 inputs: []inputInfo{ 15620 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15621 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15622 }, 15623 outputs: []outputInfo{ 15624 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15625 }, 15626 }, 15627 }, 15628 { 15629 name: "MULHWU", 15630 argLen: 2, 15631 commutative: true, 15632 asm: ppc64.AMULHWU, 15633 reg: regInfo{ 15634 inputs: []inputInfo{ 15635 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15636 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15637 }, 15638 outputs: []outputInfo{ 15639 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15640 }, 15641 }, 15642 }, 15643 { 15644 name: "FMUL", 15645 argLen: 2, 15646 commutative: true, 15647 asm: ppc64.AFMUL, 15648 reg: regInfo{ 15649 inputs: []inputInfo{ 15650 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15651 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15652 }, 15653 outputs: []outputInfo{ 15654 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15655 }, 15656 }, 15657 }, 15658 { 15659 name: "FMULS", 15660 argLen: 2, 15661 commutative: true, 15662 asm: ppc64.AFMULS, 15663 reg: regInfo{ 15664 inputs: []inputInfo{ 15665 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15666 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15667 }, 15668 outputs: []outputInfo{ 15669 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15670 }, 15671 }, 15672 }, 15673 { 15674 name: "SRAD", 15675 argLen: 2, 15676 asm: ppc64.ASRAD, 15677 reg: regInfo{ 15678 inputs: []inputInfo{ 15679 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15680 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15681 }, 15682 outputs: []outputInfo{ 15683 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15684 }, 15685 }, 15686 }, 15687 { 15688 name: "SRAW", 15689 argLen: 2, 15690 asm: ppc64.ASRAW, 15691 reg: regInfo{ 15692 inputs: []inputInfo{ 15693 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15694 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15695 }, 15696 outputs: []outputInfo{ 15697 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15698 }, 15699 }, 15700 }, 15701 { 15702 name: "SRD", 15703 argLen: 2, 15704 asm: ppc64.ASRD, 15705 reg: regInfo{ 15706 inputs: []inputInfo{ 15707 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15708 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15709 }, 15710 outputs: []outputInfo{ 15711 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15712 }, 15713 }, 15714 }, 15715 { 15716 name: "SRW", 15717 argLen: 2, 15718 asm: ppc64.ASRW, 15719 reg: regInfo{ 15720 inputs: []inputInfo{ 15721 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15722 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15723 }, 15724 outputs: []outputInfo{ 15725 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15726 }, 15727 }, 15728 }, 15729 { 15730 name: "SLD", 15731 argLen: 2, 15732 asm: ppc64.ASLD, 15733 reg: regInfo{ 15734 inputs: []inputInfo{ 15735 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15736 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15737 }, 15738 outputs: []outputInfo{ 15739 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15740 }, 15741 }, 15742 }, 15743 { 15744 name: "SLW", 15745 argLen: 2, 15746 asm: ppc64.ASLW, 15747 reg: regInfo{ 15748 inputs: []inputInfo{ 15749 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15750 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15751 }, 15752 outputs: []outputInfo{ 15753 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15754 }, 15755 }, 15756 }, 15757 { 15758 name: "ADDconstForCarry", 15759 auxType: auxInt16, 15760 argLen: 1, 15761 asm: ppc64.AADDC, 15762 reg: regInfo{ 15763 inputs: []inputInfo{ 15764 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15765 }, 15766 clobbers: 2147483648, // R31 15767 }, 15768 }, 15769 { 15770 name: "MaskIfNotCarry", 15771 argLen: 1, 15772 asm: ppc64.AADDME, 15773 reg: regInfo{ 15774 outputs: []outputInfo{ 15775 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15776 }, 15777 }, 15778 }, 15779 { 15780 name: "SRADconst", 15781 auxType: auxInt64, 15782 argLen: 1, 15783 asm: ppc64.ASRAD, 15784 reg: regInfo{ 15785 inputs: []inputInfo{ 15786 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15787 }, 15788 outputs: []outputInfo{ 15789 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15790 }, 15791 }, 15792 }, 15793 { 15794 name: "SRAWconst", 15795 auxType: auxInt64, 15796 argLen: 1, 15797 asm: ppc64.ASRAW, 15798 reg: regInfo{ 15799 inputs: []inputInfo{ 15800 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15801 }, 15802 outputs: []outputInfo{ 15803 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15804 }, 15805 }, 15806 }, 15807 { 15808 name: "SRDconst", 15809 auxType: auxInt64, 15810 argLen: 1, 15811 asm: ppc64.ASRD, 15812 reg: regInfo{ 15813 inputs: []inputInfo{ 15814 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15815 }, 15816 outputs: []outputInfo{ 15817 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15818 }, 15819 }, 15820 }, 15821 { 15822 name: "SRWconst", 15823 auxType: auxInt64, 15824 argLen: 1, 15825 asm: ppc64.ASRW, 15826 reg: regInfo{ 15827 inputs: []inputInfo{ 15828 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15829 }, 15830 outputs: []outputInfo{ 15831 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15832 }, 15833 }, 15834 }, 15835 { 15836 name: "SLDconst", 15837 auxType: auxInt64, 15838 argLen: 1, 15839 asm: ppc64.ASLD, 15840 reg: regInfo{ 15841 inputs: []inputInfo{ 15842 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15843 }, 15844 outputs: []outputInfo{ 15845 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15846 }, 15847 }, 15848 }, 15849 { 15850 name: "SLWconst", 15851 auxType: auxInt64, 15852 argLen: 1, 15853 asm: ppc64.ASLW, 15854 reg: regInfo{ 15855 inputs: []inputInfo{ 15856 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15857 }, 15858 outputs: []outputInfo{ 15859 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15860 }, 15861 }, 15862 }, 15863 { 15864 name: "FDIV", 15865 argLen: 2, 15866 asm: ppc64.AFDIV, 15867 reg: regInfo{ 15868 inputs: []inputInfo{ 15869 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15870 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15871 }, 15872 outputs: []outputInfo{ 15873 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15874 }, 15875 }, 15876 }, 15877 { 15878 name: "FDIVS", 15879 argLen: 2, 15880 asm: ppc64.AFDIVS, 15881 reg: regInfo{ 15882 inputs: []inputInfo{ 15883 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15884 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15885 }, 15886 outputs: []outputInfo{ 15887 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15888 }, 15889 }, 15890 }, 15891 { 15892 name: "DIVD", 15893 argLen: 2, 15894 asm: ppc64.ADIVD, 15895 reg: regInfo{ 15896 inputs: []inputInfo{ 15897 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15898 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15899 }, 15900 outputs: []outputInfo{ 15901 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15902 }, 15903 }, 15904 }, 15905 { 15906 name: "DIVW", 15907 argLen: 2, 15908 asm: ppc64.ADIVW, 15909 reg: regInfo{ 15910 inputs: []inputInfo{ 15911 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15912 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15913 }, 15914 outputs: []outputInfo{ 15915 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15916 }, 15917 }, 15918 }, 15919 { 15920 name: "DIVDU", 15921 argLen: 2, 15922 asm: ppc64.ADIVDU, 15923 reg: regInfo{ 15924 inputs: []inputInfo{ 15925 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15926 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15927 }, 15928 outputs: []outputInfo{ 15929 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15930 }, 15931 }, 15932 }, 15933 { 15934 name: "DIVWU", 15935 argLen: 2, 15936 asm: ppc64.ADIVWU, 15937 reg: regInfo{ 15938 inputs: []inputInfo{ 15939 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15940 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15941 }, 15942 outputs: []outputInfo{ 15943 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 15944 }, 15945 }, 15946 }, 15947 { 15948 name: "FCTIDZ", 15949 argLen: 1, 15950 asm: ppc64.AFCTIDZ, 15951 reg: regInfo{ 15952 inputs: []inputInfo{ 15953 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15954 }, 15955 outputs: []outputInfo{ 15956 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15957 }, 15958 }, 15959 }, 15960 { 15961 name: "FCTIWZ", 15962 argLen: 1, 15963 asm: ppc64.AFCTIWZ, 15964 reg: regInfo{ 15965 inputs: []inputInfo{ 15966 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15967 }, 15968 outputs: []outputInfo{ 15969 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15970 }, 15971 }, 15972 }, 15973 { 15974 name: "FCFID", 15975 argLen: 1, 15976 asm: ppc64.AFCFID, 15977 reg: regInfo{ 15978 inputs: []inputInfo{ 15979 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15980 }, 15981 outputs: []outputInfo{ 15982 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15983 }, 15984 }, 15985 }, 15986 { 15987 name: "FRSP", 15988 argLen: 1, 15989 asm: ppc64.AFRSP, 15990 reg: regInfo{ 15991 inputs: []inputInfo{ 15992 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15993 }, 15994 outputs: []outputInfo{ 15995 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 15996 }, 15997 }, 15998 }, 15999 { 16000 name: "Xf2i64", 16001 argLen: 1, 16002 usesScratch: true, 16003 reg: regInfo{ 16004 inputs: []inputInfo{ 16005 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16006 }, 16007 outputs: []outputInfo{ 16008 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16009 }, 16010 }, 16011 }, 16012 { 16013 name: "Xi2f64", 16014 argLen: 1, 16015 usesScratch: true, 16016 reg: regInfo{ 16017 inputs: []inputInfo{ 16018 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16019 }, 16020 outputs: []outputInfo{ 16021 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16022 }, 16023 }, 16024 }, 16025 { 16026 name: "AND", 16027 argLen: 2, 16028 commutative: true, 16029 asm: ppc64.AAND, 16030 reg: regInfo{ 16031 inputs: []inputInfo{ 16032 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16033 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16034 }, 16035 outputs: []outputInfo{ 16036 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16037 }, 16038 }, 16039 }, 16040 { 16041 name: "ANDN", 16042 argLen: 2, 16043 asm: ppc64.AANDN, 16044 reg: regInfo{ 16045 inputs: []inputInfo{ 16046 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16047 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16048 }, 16049 outputs: []outputInfo{ 16050 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16051 }, 16052 }, 16053 }, 16054 { 16055 name: "OR", 16056 argLen: 2, 16057 commutative: true, 16058 asm: ppc64.AOR, 16059 reg: regInfo{ 16060 inputs: []inputInfo{ 16061 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16062 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16063 }, 16064 outputs: []outputInfo{ 16065 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16066 }, 16067 }, 16068 }, 16069 { 16070 name: "ORN", 16071 argLen: 2, 16072 asm: ppc64.AORN, 16073 reg: regInfo{ 16074 inputs: []inputInfo{ 16075 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16076 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16077 }, 16078 outputs: []outputInfo{ 16079 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16080 }, 16081 }, 16082 }, 16083 { 16084 name: "XOR", 16085 argLen: 2, 16086 commutative: true, 16087 asm: ppc64.AXOR, 16088 reg: regInfo{ 16089 inputs: []inputInfo{ 16090 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16091 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16092 }, 16093 outputs: []outputInfo{ 16094 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16095 }, 16096 }, 16097 }, 16098 { 16099 name: "EQV", 16100 argLen: 2, 16101 commutative: true, 16102 asm: ppc64.AEQV, 16103 reg: regInfo{ 16104 inputs: []inputInfo{ 16105 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16106 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16107 }, 16108 outputs: []outputInfo{ 16109 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16110 }, 16111 }, 16112 }, 16113 { 16114 name: "NEG", 16115 argLen: 1, 16116 asm: ppc64.ANEG, 16117 reg: regInfo{ 16118 inputs: []inputInfo{ 16119 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16120 }, 16121 outputs: []outputInfo{ 16122 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16123 }, 16124 }, 16125 }, 16126 { 16127 name: "FNEG", 16128 argLen: 1, 16129 asm: ppc64.AFNEG, 16130 reg: regInfo{ 16131 inputs: []inputInfo{ 16132 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16133 }, 16134 outputs: []outputInfo{ 16135 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16136 }, 16137 }, 16138 }, 16139 { 16140 name: "FSQRT", 16141 argLen: 1, 16142 asm: ppc64.AFSQRT, 16143 reg: regInfo{ 16144 inputs: []inputInfo{ 16145 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16146 }, 16147 outputs: []outputInfo{ 16148 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16149 }, 16150 }, 16151 }, 16152 { 16153 name: "FSQRTS", 16154 argLen: 1, 16155 asm: ppc64.AFSQRTS, 16156 reg: regInfo{ 16157 inputs: []inputInfo{ 16158 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16159 }, 16160 outputs: []outputInfo{ 16161 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16162 }, 16163 }, 16164 }, 16165 { 16166 name: "ORconst", 16167 auxType: auxInt64, 16168 argLen: 1, 16169 asm: ppc64.AOR, 16170 reg: regInfo{ 16171 inputs: []inputInfo{ 16172 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16173 }, 16174 outputs: []outputInfo{ 16175 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16176 }, 16177 }, 16178 }, 16179 { 16180 name: "XORconst", 16181 auxType: auxInt64, 16182 argLen: 1, 16183 asm: ppc64.AXOR, 16184 reg: regInfo{ 16185 inputs: []inputInfo{ 16186 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16187 }, 16188 outputs: []outputInfo{ 16189 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16190 }, 16191 }, 16192 }, 16193 { 16194 name: "ANDconst", 16195 auxType: auxInt64, 16196 argLen: 1, 16197 clobberFlags: true, 16198 asm: ppc64.AANDCC, 16199 reg: regInfo{ 16200 inputs: []inputInfo{ 16201 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16202 }, 16203 outputs: []outputInfo{ 16204 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16205 }, 16206 }, 16207 }, 16208 { 16209 name: "ANDCCconst", 16210 auxType: auxInt64, 16211 argLen: 1, 16212 asm: ppc64.AANDCC, 16213 reg: regInfo{ 16214 inputs: []inputInfo{ 16215 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16216 }, 16217 }, 16218 }, 16219 { 16220 name: "MOVBreg", 16221 argLen: 1, 16222 asm: ppc64.AMOVB, 16223 reg: regInfo{ 16224 inputs: []inputInfo{ 16225 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16226 }, 16227 outputs: []outputInfo{ 16228 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16229 }, 16230 }, 16231 }, 16232 { 16233 name: "MOVBZreg", 16234 argLen: 1, 16235 asm: ppc64.AMOVBZ, 16236 reg: regInfo{ 16237 inputs: []inputInfo{ 16238 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16239 }, 16240 outputs: []outputInfo{ 16241 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16242 }, 16243 }, 16244 }, 16245 { 16246 name: "MOVHreg", 16247 argLen: 1, 16248 asm: ppc64.AMOVH, 16249 reg: regInfo{ 16250 inputs: []inputInfo{ 16251 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16252 }, 16253 outputs: []outputInfo{ 16254 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16255 }, 16256 }, 16257 }, 16258 { 16259 name: "MOVHZreg", 16260 argLen: 1, 16261 asm: ppc64.AMOVHZ, 16262 reg: regInfo{ 16263 inputs: []inputInfo{ 16264 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16265 }, 16266 outputs: []outputInfo{ 16267 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16268 }, 16269 }, 16270 }, 16271 { 16272 name: "MOVWreg", 16273 argLen: 1, 16274 asm: ppc64.AMOVW, 16275 reg: regInfo{ 16276 inputs: []inputInfo{ 16277 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16278 }, 16279 outputs: []outputInfo{ 16280 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16281 }, 16282 }, 16283 }, 16284 { 16285 name: "MOVWZreg", 16286 argLen: 1, 16287 asm: ppc64.AMOVWZ, 16288 reg: regInfo{ 16289 inputs: []inputInfo{ 16290 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16291 }, 16292 outputs: []outputInfo{ 16293 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16294 }, 16295 }, 16296 }, 16297 { 16298 name: "MOVBZload", 16299 auxType: auxSymOff, 16300 argLen: 2, 16301 faultOnNilArg0: true, 16302 asm: ppc64.AMOVBZ, 16303 reg: regInfo{ 16304 inputs: []inputInfo{ 16305 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16306 }, 16307 outputs: []outputInfo{ 16308 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16309 }, 16310 }, 16311 }, 16312 { 16313 name: "MOVHload", 16314 auxType: auxSymOff, 16315 argLen: 2, 16316 faultOnNilArg0: true, 16317 asm: ppc64.AMOVH, 16318 reg: regInfo{ 16319 inputs: []inputInfo{ 16320 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16321 }, 16322 outputs: []outputInfo{ 16323 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16324 }, 16325 }, 16326 }, 16327 { 16328 name: "MOVHZload", 16329 auxType: auxSymOff, 16330 argLen: 2, 16331 faultOnNilArg0: true, 16332 asm: ppc64.AMOVHZ, 16333 reg: regInfo{ 16334 inputs: []inputInfo{ 16335 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16336 }, 16337 outputs: []outputInfo{ 16338 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16339 }, 16340 }, 16341 }, 16342 { 16343 name: "MOVWload", 16344 auxType: auxSymOff, 16345 argLen: 2, 16346 faultOnNilArg0: true, 16347 asm: ppc64.AMOVW, 16348 reg: regInfo{ 16349 inputs: []inputInfo{ 16350 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16351 }, 16352 outputs: []outputInfo{ 16353 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16354 }, 16355 }, 16356 }, 16357 { 16358 name: "MOVWZload", 16359 auxType: auxSymOff, 16360 argLen: 2, 16361 faultOnNilArg0: true, 16362 asm: ppc64.AMOVWZ, 16363 reg: regInfo{ 16364 inputs: []inputInfo{ 16365 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16366 }, 16367 outputs: []outputInfo{ 16368 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16369 }, 16370 }, 16371 }, 16372 { 16373 name: "MOVDload", 16374 auxType: auxSymOff, 16375 argLen: 2, 16376 faultOnNilArg0: true, 16377 asm: ppc64.AMOVD, 16378 reg: regInfo{ 16379 inputs: []inputInfo{ 16380 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16381 }, 16382 outputs: []outputInfo{ 16383 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16384 }, 16385 }, 16386 }, 16387 { 16388 name: "FMOVDload", 16389 auxType: auxSymOff, 16390 argLen: 2, 16391 faultOnNilArg0: true, 16392 asm: ppc64.AFMOVD, 16393 reg: regInfo{ 16394 inputs: []inputInfo{ 16395 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16396 }, 16397 outputs: []outputInfo{ 16398 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16399 }, 16400 }, 16401 }, 16402 { 16403 name: "FMOVSload", 16404 auxType: auxSymOff, 16405 argLen: 2, 16406 faultOnNilArg0: true, 16407 asm: ppc64.AFMOVS, 16408 reg: regInfo{ 16409 inputs: []inputInfo{ 16410 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16411 }, 16412 outputs: []outputInfo{ 16413 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16414 }, 16415 }, 16416 }, 16417 { 16418 name: "MOVBstore", 16419 auxType: auxSymOff, 16420 argLen: 3, 16421 faultOnNilArg0: true, 16422 asm: ppc64.AMOVB, 16423 reg: regInfo{ 16424 inputs: []inputInfo{ 16425 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16426 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16427 }, 16428 }, 16429 }, 16430 { 16431 name: "MOVHstore", 16432 auxType: auxSymOff, 16433 argLen: 3, 16434 faultOnNilArg0: true, 16435 asm: ppc64.AMOVH, 16436 reg: regInfo{ 16437 inputs: []inputInfo{ 16438 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16439 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16440 }, 16441 }, 16442 }, 16443 { 16444 name: "MOVWstore", 16445 auxType: auxSymOff, 16446 argLen: 3, 16447 faultOnNilArg0: true, 16448 asm: ppc64.AMOVW, 16449 reg: regInfo{ 16450 inputs: []inputInfo{ 16451 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16452 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16453 }, 16454 }, 16455 }, 16456 { 16457 name: "MOVDstore", 16458 auxType: auxSymOff, 16459 argLen: 3, 16460 faultOnNilArg0: true, 16461 asm: ppc64.AMOVD, 16462 reg: regInfo{ 16463 inputs: []inputInfo{ 16464 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16465 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16466 }, 16467 }, 16468 }, 16469 { 16470 name: "FMOVDstore", 16471 auxType: auxSymOff, 16472 argLen: 3, 16473 faultOnNilArg0: true, 16474 asm: ppc64.AFMOVD, 16475 reg: regInfo{ 16476 inputs: []inputInfo{ 16477 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16478 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16479 }, 16480 }, 16481 }, 16482 { 16483 name: "FMOVSstore", 16484 auxType: auxSymOff, 16485 argLen: 3, 16486 faultOnNilArg0: true, 16487 asm: ppc64.AFMOVS, 16488 reg: regInfo{ 16489 inputs: []inputInfo{ 16490 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16491 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16492 }, 16493 }, 16494 }, 16495 { 16496 name: "MOVBstorezero", 16497 auxType: auxSymOff, 16498 argLen: 2, 16499 faultOnNilArg0: true, 16500 asm: ppc64.AMOVB, 16501 reg: regInfo{ 16502 inputs: []inputInfo{ 16503 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16504 }, 16505 }, 16506 }, 16507 { 16508 name: "MOVHstorezero", 16509 auxType: auxSymOff, 16510 argLen: 2, 16511 faultOnNilArg0: true, 16512 asm: ppc64.AMOVH, 16513 reg: regInfo{ 16514 inputs: []inputInfo{ 16515 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16516 }, 16517 }, 16518 }, 16519 { 16520 name: "MOVWstorezero", 16521 auxType: auxSymOff, 16522 argLen: 2, 16523 faultOnNilArg0: true, 16524 asm: ppc64.AMOVW, 16525 reg: regInfo{ 16526 inputs: []inputInfo{ 16527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16528 }, 16529 }, 16530 }, 16531 { 16532 name: "MOVDstorezero", 16533 auxType: auxSymOff, 16534 argLen: 2, 16535 faultOnNilArg0: true, 16536 asm: ppc64.AMOVD, 16537 reg: regInfo{ 16538 inputs: []inputInfo{ 16539 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16540 }, 16541 }, 16542 }, 16543 { 16544 name: "MOVDaddr", 16545 auxType: auxSymOff, 16546 argLen: 1, 16547 rematerializeable: true, 16548 asm: ppc64.AMOVD, 16549 reg: regInfo{ 16550 inputs: []inputInfo{ 16551 {0, 6}, // SP SB 16552 }, 16553 outputs: []outputInfo{ 16554 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16555 }, 16556 }, 16557 }, 16558 { 16559 name: "MOVDconst", 16560 auxType: auxInt64, 16561 argLen: 0, 16562 rematerializeable: true, 16563 asm: ppc64.AMOVD, 16564 reg: regInfo{ 16565 outputs: []outputInfo{ 16566 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16567 }, 16568 }, 16569 }, 16570 { 16571 name: "FMOVDconst", 16572 auxType: auxFloat64, 16573 argLen: 0, 16574 rematerializeable: true, 16575 asm: ppc64.AFMOVD, 16576 reg: regInfo{ 16577 outputs: []outputInfo{ 16578 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16579 }, 16580 }, 16581 }, 16582 { 16583 name: "FMOVSconst", 16584 auxType: auxFloat32, 16585 argLen: 0, 16586 rematerializeable: true, 16587 asm: ppc64.AFMOVS, 16588 reg: regInfo{ 16589 outputs: []outputInfo{ 16590 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16591 }, 16592 }, 16593 }, 16594 { 16595 name: "FCMPU", 16596 argLen: 2, 16597 asm: ppc64.AFCMPU, 16598 reg: regInfo{ 16599 inputs: []inputInfo{ 16600 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16601 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16602 }, 16603 }, 16604 }, 16605 { 16606 name: "CMP", 16607 argLen: 2, 16608 asm: ppc64.ACMP, 16609 reg: regInfo{ 16610 inputs: []inputInfo{ 16611 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16612 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16613 }, 16614 }, 16615 }, 16616 { 16617 name: "CMPU", 16618 argLen: 2, 16619 asm: ppc64.ACMPU, 16620 reg: regInfo{ 16621 inputs: []inputInfo{ 16622 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16623 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16624 }, 16625 }, 16626 }, 16627 { 16628 name: "CMPW", 16629 argLen: 2, 16630 asm: ppc64.ACMPW, 16631 reg: regInfo{ 16632 inputs: []inputInfo{ 16633 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16634 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16635 }, 16636 }, 16637 }, 16638 { 16639 name: "CMPWU", 16640 argLen: 2, 16641 asm: ppc64.ACMPWU, 16642 reg: regInfo{ 16643 inputs: []inputInfo{ 16644 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16645 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16646 }, 16647 }, 16648 }, 16649 { 16650 name: "CMPconst", 16651 auxType: auxInt64, 16652 argLen: 1, 16653 asm: ppc64.ACMP, 16654 reg: regInfo{ 16655 inputs: []inputInfo{ 16656 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16657 }, 16658 }, 16659 }, 16660 { 16661 name: "CMPUconst", 16662 auxType: auxInt64, 16663 argLen: 1, 16664 asm: ppc64.ACMPU, 16665 reg: regInfo{ 16666 inputs: []inputInfo{ 16667 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16668 }, 16669 }, 16670 }, 16671 { 16672 name: "CMPWconst", 16673 auxType: auxInt32, 16674 argLen: 1, 16675 asm: ppc64.ACMPW, 16676 reg: regInfo{ 16677 inputs: []inputInfo{ 16678 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16679 }, 16680 }, 16681 }, 16682 { 16683 name: "CMPWUconst", 16684 auxType: auxInt32, 16685 argLen: 1, 16686 asm: ppc64.ACMPWU, 16687 reg: regInfo{ 16688 inputs: []inputInfo{ 16689 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16690 }, 16691 }, 16692 }, 16693 { 16694 name: "Equal", 16695 argLen: 1, 16696 reg: regInfo{ 16697 outputs: []outputInfo{ 16698 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16699 }, 16700 }, 16701 }, 16702 { 16703 name: "NotEqual", 16704 argLen: 1, 16705 reg: regInfo{ 16706 outputs: []outputInfo{ 16707 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16708 }, 16709 }, 16710 }, 16711 { 16712 name: "LessThan", 16713 argLen: 1, 16714 reg: regInfo{ 16715 outputs: []outputInfo{ 16716 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16717 }, 16718 }, 16719 }, 16720 { 16721 name: "FLessThan", 16722 argLen: 1, 16723 reg: regInfo{ 16724 outputs: []outputInfo{ 16725 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16726 }, 16727 }, 16728 }, 16729 { 16730 name: "LessEqual", 16731 argLen: 1, 16732 reg: regInfo{ 16733 outputs: []outputInfo{ 16734 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16735 }, 16736 }, 16737 }, 16738 { 16739 name: "FLessEqual", 16740 argLen: 1, 16741 reg: regInfo{ 16742 outputs: []outputInfo{ 16743 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16744 }, 16745 }, 16746 }, 16747 { 16748 name: "GreaterThan", 16749 argLen: 1, 16750 reg: regInfo{ 16751 outputs: []outputInfo{ 16752 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16753 }, 16754 }, 16755 }, 16756 { 16757 name: "FGreaterThan", 16758 argLen: 1, 16759 reg: regInfo{ 16760 outputs: []outputInfo{ 16761 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16762 }, 16763 }, 16764 }, 16765 { 16766 name: "GreaterEqual", 16767 argLen: 1, 16768 reg: regInfo{ 16769 outputs: []outputInfo{ 16770 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16771 }, 16772 }, 16773 }, 16774 { 16775 name: "FGreaterEqual", 16776 argLen: 1, 16777 reg: regInfo{ 16778 outputs: []outputInfo{ 16779 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16780 }, 16781 }, 16782 }, 16783 { 16784 name: "LoweredGetClosurePtr", 16785 argLen: 0, 16786 reg: regInfo{ 16787 outputs: []outputInfo{ 16788 {0, 2048}, // R11 16789 }, 16790 }, 16791 }, 16792 { 16793 name: "LoweredNilCheck", 16794 argLen: 2, 16795 clobberFlags: true, 16796 nilCheck: true, 16797 faultOnNilArg0: true, 16798 reg: regInfo{ 16799 inputs: []inputInfo{ 16800 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16801 }, 16802 clobbers: 2147483648, // R31 16803 }, 16804 }, 16805 { 16806 name: "MOVDconvert", 16807 argLen: 2, 16808 asm: ppc64.AMOVD, 16809 reg: regInfo{ 16810 inputs: []inputInfo{ 16811 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16812 }, 16813 outputs: []outputInfo{ 16814 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16815 }, 16816 }, 16817 }, 16818 { 16819 name: "CALLstatic", 16820 auxType: auxSymOff, 16821 argLen: 1, 16822 clobberFlags: true, 16823 call: true, 16824 reg: regInfo{ 16825 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16826 }, 16827 }, 16828 { 16829 name: "CALLclosure", 16830 auxType: auxInt64, 16831 argLen: 3, 16832 clobberFlags: true, 16833 call: true, 16834 reg: regInfo{ 16835 inputs: []inputInfo{ 16836 {1, 2048}, // R11 16837 {0, 1073733626}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16838 }, 16839 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16840 }, 16841 }, 16842 { 16843 name: "CALLdefer", 16844 auxType: auxInt64, 16845 argLen: 1, 16846 clobberFlags: true, 16847 call: true, 16848 reg: regInfo{ 16849 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16850 }, 16851 }, 16852 { 16853 name: "CALLgo", 16854 auxType: auxInt64, 16855 argLen: 1, 16856 clobberFlags: true, 16857 call: true, 16858 reg: regInfo{ 16859 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16860 }, 16861 }, 16862 { 16863 name: "CALLinter", 16864 auxType: auxInt64, 16865 argLen: 2, 16866 clobberFlags: true, 16867 call: true, 16868 reg: regInfo{ 16869 inputs: []inputInfo{ 16870 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16871 }, 16872 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 16873 }, 16874 }, 16875 { 16876 name: "LoweredZero", 16877 auxType: auxInt64, 16878 argLen: 3, 16879 clobberFlags: true, 16880 faultOnNilArg0: true, 16881 reg: regInfo{ 16882 inputs: []inputInfo{ 16883 {0, 8}, // R3 16884 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16885 }, 16886 clobbers: 8, // R3 16887 }, 16888 }, 16889 { 16890 name: "LoweredMove", 16891 auxType: auxInt64, 16892 argLen: 4, 16893 clobberFlags: true, 16894 faultOnNilArg0: true, 16895 faultOnNilArg1: true, 16896 reg: regInfo{ 16897 inputs: []inputInfo{ 16898 {0, 8}, // R3 16899 {1, 16}, // R4 16900 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 16901 }, 16902 clobbers: 24, // R3 R4 16903 }, 16904 }, 16905 { 16906 name: "InvertFlags", 16907 argLen: 1, 16908 reg: regInfo{}, 16909 }, 16910 { 16911 name: "FlagEQ", 16912 argLen: 0, 16913 reg: regInfo{}, 16914 }, 16915 { 16916 name: "FlagLT", 16917 argLen: 0, 16918 reg: regInfo{}, 16919 }, 16920 { 16921 name: "FlagGT", 16922 argLen: 0, 16923 reg: regInfo{}, 16924 }, 16925 16926 { 16927 name: "FADDS", 16928 argLen: 2, 16929 commutative: true, 16930 resultInArg0: true, 16931 clobberFlags: true, 16932 asm: s390x.AFADDS, 16933 reg: regInfo{ 16934 inputs: []inputInfo{ 16935 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16936 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16937 }, 16938 outputs: []outputInfo{ 16939 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16940 }, 16941 }, 16942 }, 16943 { 16944 name: "FADD", 16945 argLen: 2, 16946 commutative: true, 16947 resultInArg0: true, 16948 clobberFlags: true, 16949 asm: s390x.AFADD, 16950 reg: regInfo{ 16951 inputs: []inputInfo{ 16952 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16953 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16954 }, 16955 outputs: []outputInfo{ 16956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16957 }, 16958 }, 16959 }, 16960 { 16961 name: "FSUBS", 16962 argLen: 2, 16963 resultInArg0: true, 16964 clobberFlags: true, 16965 asm: s390x.AFSUBS, 16966 reg: regInfo{ 16967 inputs: []inputInfo{ 16968 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16969 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16970 }, 16971 outputs: []outputInfo{ 16972 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16973 }, 16974 }, 16975 }, 16976 { 16977 name: "FSUB", 16978 argLen: 2, 16979 resultInArg0: true, 16980 clobberFlags: true, 16981 asm: s390x.AFSUB, 16982 reg: regInfo{ 16983 inputs: []inputInfo{ 16984 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16985 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16986 }, 16987 outputs: []outputInfo{ 16988 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 16989 }, 16990 }, 16991 }, 16992 { 16993 name: "FMULS", 16994 argLen: 2, 16995 commutative: true, 16996 resultInArg0: true, 16997 asm: s390x.AFMULS, 16998 reg: regInfo{ 16999 inputs: []inputInfo{ 17000 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17001 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17002 }, 17003 outputs: []outputInfo{ 17004 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17005 }, 17006 }, 17007 }, 17008 { 17009 name: "FMUL", 17010 argLen: 2, 17011 commutative: true, 17012 resultInArg0: true, 17013 asm: s390x.AFMUL, 17014 reg: regInfo{ 17015 inputs: []inputInfo{ 17016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17017 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17018 }, 17019 outputs: []outputInfo{ 17020 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17021 }, 17022 }, 17023 }, 17024 { 17025 name: "FDIVS", 17026 argLen: 2, 17027 resultInArg0: true, 17028 asm: s390x.AFDIVS, 17029 reg: regInfo{ 17030 inputs: []inputInfo{ 17031 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17032 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17033 }, 17034 outputs: []outputInfo{ 17035 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17036 }, 17037 }, 17038 }, 17039 { 17040 name: "FDIV", 17041 argLen: 2, 17042 resultInArg0: true, 17043 asm: s390x.AFDIV, 17044 reg: regInfo{ 17045 inputs: []inputInfo{ 17046 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17047 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17048 }, 17049 outputs: []outputInfo{ 17050 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17051 }, 17052 }, 17053 }, 17054 { 17055 name: "FNEGS", 17056 argLen: 1, 17057 clobberFlags: true, 17058 asm: s390x.AFNEGS, 17059 reg: regInfo{ 17060 inputs: []inputInfo{ 17061 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17062 }, 17063 outputs: []outputInfo{ 17064 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17065 }, 17066 }, 17067 }, 17068 { 17069 name: "FNEG", 17070 argLen: 1, 17071 clobberFlags: true, 17072 asm: s390x.AFNEG, 17073 reg: regInfo{ 17074 inputs: []inputInfo{ 17075 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17076 }, 17077 outputs: []outputInfo{ 17078 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17079 }, 17080 }, 17081 }, 17082 { 17083 name: "FMOVSload", 17084 auxType: auxSymOff, 17085 argLen: 2, 17086 faultOnNilArg0: true, 17087 asm: s390x.AFMOVS, 17088 reg: regInfo{ 17089 inputs: []inputInfo{ 17090 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17091 }, 17092 outputs: []outputInfo{ 17093 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17094 }, 17095 }, 17096 }, 17097 { 17098 name: "FMOVDload", 17099 auxType: auxSymOff, 17100 argLen: 2, 17101 faultOnNilArg0: true, 17102 asm: s390x.AFMOVD, 17103 reg: regInfo{ 17104 inputs: []inputInfo{ 17105 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17106 }, 17107 outputs: []outputInfo{ 17108 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17109 }, 17110 }, 17111 }, 17112 { 17113 name: "FMOVSconst", 17114 auxType: auxFloat32, 17115 argLen: 0, 17116 rematerializeable: true, 17117 asm: s390x.AFMOVS, 17118 reg: regInfo{ 17119 outputs: []outputInfo{ 17120 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17121 }, 17122 }, 17123 }, 17124 { 17125 name: "FMOVDconst", 17126 auxType: auxFloat64, 17127 argLen: 0, 17128 rematerializeable: true, 17129 asm: s390x.AFMOVD, 17130 reg: regInfo{ 17131 outputs: []outputInfo{ 17132 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17133 }, 17134 }, 17135 }, 17136 { 17137 name: "FMOVSloadidx", 17138 auxType: auxSymOff, 17139 argLen: 3, 17140 asm: s390x.AFMOVS, 17141 reg: regInfo{ 17142 inputs: []inputInfo{ 17143 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17144 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17145 }, 17146 outputs: []outputInfo{ 17147 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17148 }, 17149 }, 17150 }, 17151 { 17152 name: "FMOVDloadidx", 17153 auxType: auxSymOff, 17154 argLen: 3, 17155 asm: s390x.AFMOVD, 17156 reg: regInfo{ 17157 inputs: []inputInfo{ 17158 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17159 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17160 }, 17161 outputs: []outputInfo{ 17162 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17163 }, 17164 }, 17165 }, 17166 { 17167 name: "FMOVSstore", 17168 auxType: auxSymOff, 17169 argLen: 3, 17170 faultOnNilArg0: true, 17171 asm: s390x.AFMOVS, 17172 reg: regInfo{ 17173 inputs: []inputInfo{ 17174 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17175 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17176 }, 17177 }, 17178 }, 17179 { 17180 name: "FMOVDstore", 17181 auxType: auxSymOff, 17182 argLen: 3, 17183 faultOnNilArg0: true, 17184 asm: s390x.AFMOVD, 17185 reg: regInfo{ 17186 inputs: []inputInfo{ 17187 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 17188 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17189 }, 17190 }, 17191 }, 17192 { 17193 name: "FMOVSstoreidx", 17194 auxType: auxSymOff, 17195 argLen: 4, 17196 asm: s390x.AFMOVS, 17197 reg: regInfo{ 17198 inputs: []inputInfo{ 17199 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17200 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17201 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17202 }, 17203 }, 17204 }, 17205 { 17206 name: "FMOVDstoreidx", 17207 auxType: auxSymOff, 17208 argLen: 4, 17209 asm: s390x.AFMOVD, 17210 reg: regInfo{ 17211 inputs: []inputInfo{ 17212 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17213 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17214 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17215 }, 17216 }, 17217 }, 17218 { 17219 name: "ADD", 17220 argLen: 2, 17221 commutative: true, 17222 clobberFlags: true, 17223 asm: s390x.AADD, 17224 reg: regInfo{ 17225 inputs: []inputInfo{ 17226 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17227 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17228 }, 17229 outputs: []outputInfo{ 17230 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17231 }, 17232 }, 17233 }, 17234 { 17235 name: "ADDW", 17236 argLen: 2, 17237 commutative: true, 17238 clobberFlags: true, 17239 asm: s390x.AADDW, 17240 reg: regInfo{ 17241 inputs: []inputInfo{ 17242 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17243 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17244 }, 17245 outputs: []outputInfo{ 17246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17247 }, 17248 }, 17249 }, 17250 { 17251 name: "ADDconst", 17252 auxType: auxInt64, 17253 argLen: 1, 17254 clobberFlags: true, 17255 asm: s390x.AADD, 17256 reg: regInfo{ 17257 inputs: []inputInfo{ 17258 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17259 }, 17260 outputs: []outputInfo{ 17261 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17262 }, 17263 }, 17264 }, 17265 { 17266 name: "ADDWconst", 17267 auxType: auxInt32, 17268 argLen: 1, 17269 clobberFlags: true, 17270 asm: s390x.AADDW, 17271 reg: regInfo{ 17272 inputs: []inputInfo{ 17273 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17274 }, 17275 outputs: []outputInfo{ 17276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17277 }, 17278 }, 17279 }, 17280 { 17281 name: "ADDload", 17282 auxType: auxSymOff, 17283 argLen: 3, 17284 resultInArg0: true, 17285 clobberFlags: true, 17286 faultOnNilArg1: true, 17287 asm: s390x.AADD, 17288 reg: regInfo{ 17289 inputs: []inputInfo{ 17290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17291 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17292 }, 17293 outputs: []outputInfo{ 17294 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17295 }, 17296 }, 17297 }, 17298 { 17299 name: "ADDWload", 17300 auxType: auxSymOff, 17301 argLen: 3, 17302 resultInArg0: true, 17303 clobberFlags: true, 17304 faultOnNilArg1: true, 17305 asm: s390x.AADDW, 17306 reg: regInfo{ 17307 inputs: []inputInfo{ 17308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17309 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17310 }, 17311 outputs: []outputInfo{ 17312 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17313 }, 17314 }, 17315 }, 17316 { 17317 name: "SUB", 17318 argLen: 2, 17319 clobberFlags: true, 17320 asm: s390x.ASUB, 17321 reg: regInfo{ 17322 inputs: []inputInfo{ 17323 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17324 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17325 }, 17326 outputs: []outputInfo{ 17327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17328 }, 17329 }, 17330 }, 17331 { 17332 name: "SUBW", 17333 argLen: 2, 17334 clobberFlags: true, 17335 asm: s390x.ASUBW, 17336 reg: regInfo{ 17337 inputs: []inputInfo{ 17338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17339 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17340 }, 17341 outputs: []outputInfo{ 17342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17343 }, 17344 }, 17345 }, 17346 { 17347 name: "SUBconst", 17348 auxType: auxInt64, 17349 argLen: 1, 17350 resultInArg0: true, 17351 clobberFlags: true, 17352 asm: s390x.ASUB, 17353 reg: regInfo{ 17354 inputs: []inputInfo{ 17355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17356 }, 17357 outputs: []outputInfo{ 17358 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17359 }, 17360 }, 17361 }, 17362 { 17363 name: "SUBWconst", 17364 auxType: auxInt32, 17365 argLen: 1, 17366 resultInArg0: true, 17367 clobberFlags: true, 17368 asm: s390x.ASUBW, 17369 reg: regInfo{ 17370 inputs: []inputInfo{ 17371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17372 }, 17373 outputs: []outputInfo{ 17374 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17375 }, 17376 }, 17377 }, 17378 { 17379 name: "SUBload", 17380 auxType: auxSymOff, 17381 argLen: 3, 17382 resultInArg0: true, 17383 clobberFlags: true, 17384 faultOnNilArg1: true, 17385 asm: s390x.ASUB, 17386 reg: regInfo{ 17387 inputs: []inputInfo{ 17388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17389 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17390 }, 17391 outputs: []outputInfo{ 17392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17393 }, 17394 }, 17395 }, 17396 { 17397 name: "SUBWload", 17398 auxType: auxSymOff, 17399 argLen: 3, 17400 resultInArg0: true, 17401 clobberFlags: true, 17402 faultOnNilArg1: true, 17403 asm: s390x.ASUBW, 17404 reg: regInfo{ 17405 inputs: []inputInfo{ 17406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17407 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17408 }, 17409 outputs: []outputInfo{ 17410 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17411 }, 17412 }, 17413 }, 17414 { 17415 name: "MULLD", 17416 argLen: 2, 17417 commutative: true, 17418 resultInArg0: true, 17419 clobberFlags: true, 17420 asm: s390x.AMULLD, 17421 reg: regInfo{ 17422 inputs: []inputInfo{ 17423 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17424 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17425 }, 17426 outputs: []outputInfo{ 17427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17428 }, 17429 }, 17430 }, 17431 { 17432 name: "MULLW", 17433 argLen: 2, 17434 commutative: true, 17435 resultInArg0: true, 17436 clobberFlags: true, 17437 asm: s390x.AMULLW, 17438 reg: regInfo{ 17439 inputs: []inputInfo{ 17440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17441 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17442 }, 17443 outputs: []outputInfo{ 17444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17445 }, 17446 }, 17447 }, 17448 { 17449 name: "MULLDconst", 17450 auxType: auxInt64, 17451 argLen: 1, 17452 resultInArg0: true, 17453 clobberFlags: true, 17454 asm: s390x.AMULLD, 17455 reg: regInfo{ 17456 inputs: []inputInfo{ 17457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17458 }, 17459 outputs: []outputInfo{ 17460 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17461 }, 17462 }, 17463 }, 17464 { 17465 name: "MULLWconst", 17466 auxType: auxInt32, 17467 argLen: 1, 17468 resultInArg0: true, 17469 clobberFlags: true, 17470 asm: s390x.AMULLW, 17471 reg: regInfo{ 17472 inputs: []inputInfo{ 17473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17474 }, 17475 outputs: []outputInfo{ 17476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17477 }, 17478 }, 17479 }, 17480 { 17481 name: "MULLDload", 17482 auxType: auxSymOff, 17483 argLen: 3, 17484 resultInArg0: true, 17485 clobberFlags: true, 17486 faultOnNilArg1: true, 17487 asm: s390x.AMULLD, 17488 reg: regInfo{ 17489 inputs: []inputInfo{ 17490 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17491 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17492 }, 17493 outputs: []outputInfo{ 17494 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17495 }, 17496 }, 17497 }, 17498 { 17499 name: "MULLWload", 17500 auxType: auxSymOff, 17501 argLen: 3, 17502 resultInArg0: true, 17503 clobberFlags: true, 17504 faultOnNilArg1: true, 17505 asm: s390x.AMULLW, 17506 reg: regInfo{ 17507 inputs: []inputInfo{ 17508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17509 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17510 }, 17511 outputs: []outputInfo{ 17512 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17513 }, 17514 }, 17515 }, 17516 { 17517 name: "MULHD", 17518 argLen: 2, 17519 resultInArg0: true, 17520 clobberFlags: true, 17521 asm: s390x.AMULHD, 17522 reg: regInfo{ 17523 inputs: []inputInfo{ 17524 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17525 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17526 }, 17527 outputs: []outputInfo{ 17528 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17529 }, 17530 }, 17531 }, 17532 { 17533 name: "MULHDU", 17534 argLen: 2, 17535 resultInArg0: true, 17536 clobberFlags: true, 17537 asm: s390x.AMULHDU, 17538 reg: regInfo{ 17539 inputs: []inputInfo{ 17540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17541 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17542 }, 17543 outputs: []outputInfo{ 17544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17545 }, 17546 }, 17547 }, 17548 { 17549 name: "DIVD", 17550 argLen: 2, 17551 resultInArg0: true, 17552 clobberFlags: true, 17553 asm: s390x.ADIVD, 17554 reg: regInfo{ 17555 inputs: []inputInfo{ 17556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17557 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17558 }, 17559 outputs: []outputInfo{ 17560 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17561 }, 17562 }, 17563 }, 17564 { 17565 name: "DIVW", 17566 argLen: 2, 17567 resultInArg0: true, 17568 clobberFlags: true, 17569 asm: s390x.ADIVW, 17570 reg: regInfo{ 17571 inputs: []inputInfo{ 17572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17573 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17574 }, 17575 outputs: []outputInfo{ 17576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17577 }, 17578 }, 17579 }, 17580 { 17581 name: "DIVDU", 17582 argLen: 2, 17583 resultInArg0: true, 17584 clobberFlags: true, 17585 asm: s390x.ADIVDU, 17586 reg: regInfo{ 17587 inputs: []inputInfo{ 17588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17589 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17590 }, 17591 outputs: []outputInfo{ 17592 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17593 }, 17594 }, 17595 }, 17596 { 17597 name: "DIVWU", 17598 argLen: 2, 17599 resultInArg0: true, 17600 clobberFlags: true, 17601 asm: s390x.ADIVWU, 17602 reg: regInfo{ 17603 inputs: []inputInfo{ 17604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17605 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17606 }, 17607 outputs: []outputInfo{ 17608 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17609 }, 17610 }, 17611 }, 17612 { 17613 name: "MODD", 17614 argLen: 2, 17615 resultInArg0: true, 17616 clobberFlags: true, 17617 asm: s390x.AMODD, 17618 reg: regInfo{ 17619 inputs: []inputInfo{ 17620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17621 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17622 }, 17623 outputs: []outputInfo{ 17624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17625 }, 17626 }, 17627 }, 17628 { 17629 name: "MODW", 17630 argLen: 2, 17631 resultInArg0: true, 17632 clobberFlags: true, 17633 asm: s390x.AMODW, 17634 reg: regInfo{ 17635 inputs: []inputInfo{ 17636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17637 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17638 }, 17639 outputs: []outputInfo{ 17640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17641 }, 17642 }, 17643 }, 17644 { 17645 name: "MODDU", 17646 argLen: 2, 17647 resultInArg0: true, 17648 clobberFlags: true, 17649 asm: s390x.AMODDU, 17650 reg: regInfo{ 17651 inputs: []inputInfo{ 17652 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17653 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17654 }, 17655 outputs: []outputInfo{ 17656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17657 }, 17658 }, 17659 }, 17660 { 17661 name: "MODWU", 17662 argLen: 2, 17663 resultInArg0: true, 17664 clobberFlags: true, 17665 asm: s390x.AMODWU, 17666 reg: regInfo{ 17667 inputs: []inputInfo{ 17668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17669 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17670 }, 17671 outputs: []outputInfo{ 17672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17673 }, 17674 }, 17675 }, 17676 { 17677 name: "AND", 17678 argLen: 2, 17679 commutative: true, 17680 clobberFlags: true, 17681 asm: s390x.AAND, 17682 reg: regInfo{ 17683 inputs: []inputInfo{ 17684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17685 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17686 }, 17687 outputs: []outputInfo{ 17688 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17689 }, 17690 }, 17691 }, 17692 { 17693 name: "ANDW", 17694 argLen: 2, 17695 commutative: true, 17696 clobberFlags: true, 17697 asm: s390x.AANDW, 17698 reg: regInfo{ 17699 inputs: []inputInfo{ 17700 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17701 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17702 }, 17703 outputs: []outputInfo{ 17704 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17705 }, 17706 }, 17707 }, 17708 { 17709 name: "ANDconst", 17710 auxType: auxInt64, 17711 argLen: 1, 17712 resultInArg0: true, 17713 clobberFlags: true, 17714 asm: s390x.AAND, 17715 reg: regInfo{ 17716 inputs: []inputInfo{ 17717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17718 }, 17719 outputs: []outputInfo{ 17720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17721 }, 17722 }, 17723 }, 17724 { 17725 name: "ANDWconst", 17726 auxType: auxInt32, 17727 argLen: 1, 17728 resultInArg0: true, 17729 clobberFlags: true, 17730 asm: s390x.AANDW, 17731 reg: regInfo{ 17732 inputs: []inputInfo{ 17733 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17734 }, 17735 outputs: []outputInfo{ 17736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17737 }, 17738 }, 17739 }, 17740 { 17741 name: "ANDload", 17742 auxType: auxSymOff, 17743 argLen: 3, 17744 resultInArg0: true, 17745 clobberFlags: true, 17746 faultOnNilArg1: true, 17747 asm: s390x.AAND, 17748 reg: regInfo{ 17749 inputs: []inputInfo{ 17750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17751 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17752 }, 17753 outputs: []outputInfo{ 17754 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17755 }, 17756 }, 17757 }, 17758 { 17759 name: "ANDWload", 17760 auxType: auxSymOff, 17761 argLen: 3, 17762 resultInArg0: true, 17763 clobberFlags: true, 17764 faultOnNilArg1: true, 17765 asm: s390x.AANDW, 17766 reg: regInfo{ 17767 inputs: []inputInfo{ 17768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17769 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17770 }, 17771 outputs: []outputInfo{ 17772 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17773 }, 17774 }, 17775 }, 17776 { 17777 name: "OR", 17778 argLen: 2, 17779 commutative: true, 17780 clobberFlags: true, 17781 asm: s390x.AOR, 17782 reg: regInfo{ 17783 inputs: []inputInfo{ 17784 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17785 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17786 }, 17787 outputs: []outputInfo{ 17788 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17789 }, 17790 }, 17791 }, 17792 { 17793 name: "ORW", 17794 argLen: 2, 17795 commutative: true, 17796 clobberFlags: true, 17797 asm: s390x.AORW, 17798 reg: regInfo{ 17799 inputs: []inputInfo{ 17800 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17801 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17802 }, 17803 outputs: []outputInfo{ 17804 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17805 }, 17806 }, 17807 }, 17808 { 17809 name: "ORconst", 17810 auxType: auxInt64, 17811 argLen: 1, 17812 resultInArg0: true, 17813 clobberFlags: true, 17814 asm: s390x.AOR, 17815 reg: regInfo{ 17816 inputs: []inputInfo{ 17817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17818 }, 17819 outputs: []outputInfo{ 17820 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17821 }, 17822 }, 17823 }, 17824 { 17825 name: "ORWconst", 17826 auxType: auxInt32, 17827 argLen: 1, 17828 resultInArg0: true, 17829 clobberFlags: true, 17830 asm: s390x.AORW, 17831 reg: regInfo{ 17832 inputs: []inputInfo{ 17833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17834 }, 17835 outputs: []outputInfo{ 17836 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17837 }, 17838 }, 17839 }, 17840 { 17841 name: "ORload", 17842 auxType: auxSymOff, 17843 argLen: 3, 17844 resultInArg0: true, 17845 clobberFlags: true, 17846 faultOnNilArg1: true, 17847 asm: s390x.AOR, 17848 reg: regInfo{ 17849 inputs: []inputInfo{ 17850 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17851 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17852 }, 17853 outputs: []outputInfo{ 17854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17855 }, 17856 }, 17857 }, 17858 { 17859 name: "ORWload", 17860 auxType: auxSymOff, 17861 argLen: 3, 17862 resultInArg0: true, 17863 clobberFlags: true, 17864 faultOnNilArg1: true, 17865 asm: s390x.AORW, 17866 reg: regInfo{ 17867 inputs: []inputInfo{ 17868 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17869 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17870 }, 17871 outputs: []outputInfo{ 17872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17873 }, 17874 }, 17875 }, 17876 { 17877 name: "XOR", 17878 argLen: 2, 17879 commutative: true, 17880 clobberFlags: true, 17881 asm: s390x.AXOR, 17882 reg: regInfo{ 17883 inputs: []inputInfo{ 17884 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17885 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17886 }, 17887 outputs: []outputInfo{ 17888 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17889 }, 17890 }, 17891 }, 17892 { 17893 name: "XORW", 17894 argLen: 2, 17895 commutative: true, 17896 clobberFlags: true, 17897 asm: s390x.AXORW, 17898 reg: regInfo{ 17899 inputs: []inputInfo{ 17900 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17901 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17902 }, 17903 outputs: []outputInfo{ 17904 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17905 }, 17906 }, 17907 }, 17908 { 17909 name: "XORconst", 17910 auxType: auxInt64, 17911 argLen: 1, 17912 resultInArg0: true, 17913 clobberFlags: true, 17914 asm: s390x.AXOR, 17915 reg: regInfo{ 17916 inputs: []inputInfo{ 17917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17918 }, 17919 outputs: []outputInfo{ 17920 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17921 }, 17922 }, 17923 }, 17924 { 17925 name: "XORWconst", 17926 auxType: auxInt32, 17927 argLen: 1, 17928 resultInArg0: true, 17929 clobberFlags: true, 17930 asm: s390x.AXORW, 17931 reg: regInfo{ 17932 inputs: []inputInfo{ 17933 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17934 }, 17935 outputs: []outputInfo{ 17936 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17937 }, 17938 }, 17939 }, 17940 { 17941 name: "XORload", 17942 auxType: auxSymOff, 17943 argLen: 3, 17944 resultInArg0: true, 17945 clobberFlags: true, 17946 faultOnNilArg1: true, 17947 asm: s390x.AXOR, 17948 reg: regInfo{ 17949 inputs: []inputInfo{ 17950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17951 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17952 }, 17953 outputs: []outputInfo{ 17954 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17955 }, 17956 }, 17957 }, 17958 { 17959 name: "XORWload", 17960 auxType: auxSymOff, 17961 argLen: 3, 17962 resultInArg0: true, 17963 clobberFlags: true, 17964 faultOnNilArg1: true, 17965 asm: s390x.AXORW, 17966 reg: regInfo{ 17967 inputs: []inputInfo{ 17968 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17969 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17970 }, 17971 outputs: []outputInfo{ 17972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17973 }, 17974 }, 17975 }, 17976 { 17977 name: "CMP", 17978 argLen: 2, 17979 asm: s390x.ACMP, 17980 reg: regInfo{ 17981 inputs: []inputInfo{ 17982 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17983 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17984 }, 17985 }, 17986 }, 17987 { 17988 name: "CMPW", 17989 argLen: 2, 17990 asm: s390x.ACMPW, 17991 reg: regInfo{ 17992 inputs: []inputInfo{ 17993 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17994 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 17995 }, 17996 }, 17997 }, 17998 { 17999 name: "CMPU", 18000 argLen: 2, 18001 asm: s390x.ACMPU, 18002 reg: regInfo{ 18003 inputs: []inputInfo{ 18004 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18005 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18006 }, 18007 }, 18008 }, 18009 { 18010 name: "CMPWU", 18011 argLen: 2, 18012 asm: s390x.ACMPWU, 18013 reg: regInfo{ 18014 inputs: []inputInfo{ 18015 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18016 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18017 }, 18018 }, 18019 }, 18020 { 18021 name: "CMPconst", 18022 auxType: auxInt64, 18023 argLen: 1, 18024 asm: s390x.ACMP, 18025 reg: regInfo{ 18026 inputs: []inputInfo{ 18027 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18028 }, 18029 }, 18030 }, 18031 { 18032 name: "CMPWconst", 18033 auxType: auxInt32, 18034 argLen: 1, 18035 asm: s390x.ACMPW, 18036 reg: regInfo{ 18037 inputs: []inputInfo{ 18038 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18039 }, 18040 }, 18041 }, 18042 { 18043 name: "CMPUconst", 18044 auxType: auxInt64, 18045 argLen: 1, 18046 asm: s390x.ACMPU, 18047 reg: regInfo{ 18048 inputs: []inputInfo{ 18049 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18050 }, 18051 }, 18052 }, 18053 { 18054 name: "CMPWUconst", 18055 auxType: auxInt32, 18056 argLen: 1, 18057 asm: s390x.ACMPWU, 18058 reg: regInfo{ 18059 inputs: []inputInfo{ 18060 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18061 }, 18062 }, 18063 }, 18064 { 18065 name: "FCMPS", 18066 argLen: 2, 18067 asm: s390x.ACEBR, 18068 reg: regInfo{ 18069 inputs: []inputInfo{ 18070 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18071 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18072 }, 18073 }, 18074 }, 18075 { 18076 name: "FCMP", 18077 argLen: 2, 18078 asm: s390x.AFCMPU, 18079 reg: regInfo{ 18080 inputs: []inputInfo{ 18081 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18082 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18083 }, 18084 }, 18085 }, 18086 { 18087 name: "SLD", 18088 argLen: 2, 18089 asm: s390x.ASLD, 18090 reg: regInfo{ 18091 inputs: []inputInfo{ 18092 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18093 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18094 }, 18095 outputs: []outputInfo{ 18096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18097 }, 18098 }, 18099 }, 18100 { 18101 name: "SLW", 18102 argLen: 2, 18103 asm: s390x.ASLW, 18104 reg: regInfo{ 18105 inputs: []inputInfo{ 18106 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18108 }, 18109 outputs: []outputInfo{ 18110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18111 }, 18112 }, 18113 }, 18114 { 18115 name: "SLDconst", 18116 auxType: auxInt64, 18117 argLen: 1, 18118 asm: s390x.ASLD, 18119 reg: regInfo{ 18120 inputs: []inputInfo{ 18121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18122 }, 18123 outputs: []outputInfo{ 18124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18125 }, 18126 }, 18127 }, 18128 { 18129 name: "SLWconst", 18130 auxType: auxInt32, 18131 argLen: 1, 18132 asm: s390x.ASLW, 18133 reg: regInfo{ 18134 inputs: []inputInfo{ 18135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18136 }, 18137 outputs: []outputInfo{ 18138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18139 }, 18140 }, 18141 }, 18142 { 18143 name: "SRD", 18144 argLen: 2, 18145 asm: s390x.ASRD, 18146 reg: regInfo{ 18147 inputs: []inputInfo{ 18148 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18150 }, 18151 outputs: []outputInfo{ 18152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18153 }, 18154 }, 18155 }, 18156 { 18157 name: "SRW", 18158 argLen: 2, 18159 asm: s390x.ASRW, 18160 reg: regInfo{ 18161 inputs: []inputInfo{ 18162 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18164 }, 18165 outputs: []outputInfo{ 18166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18167 }, 18168 }, 18169 }, 18170 { 18171 name: "SRDconst", 18172 auxType: auxInt64, 18173 argLen: 1, 18174 asm: s390x.ASRD, 18175 reg: regInfo{ 18176 inputs: []inputInfo{ 18177 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18178 }, 18179 outputs: []outputInfo{ 18180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18181 }, 18182 }, 18183 }, 18184 { 18185 name: "SRWconst", 18186 auxType: auxInt32, 18187 argLen: 1, 18188 asm: s390x.ASRW, 18189 reg: regInfo{ 18190 inputs: []inputInfo{ 18191 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18192 }, 18193 outputs: []outputInfo{ 18194 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18195 }, 18196 }, 18197 }, 18198 { 18199 name: "SRAD", 18200 argLen: 2, 18201 clobberFlags: true, 18202 asm: s390x.ASRAD, 18203 reg: regInfo{ 18204 inputs: []inputInfo{ 18205 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18207 }, 18208 outputs: []outputInfo{ 18209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18210 }, 18211 }, 18212 }, 18213 { 18214 name: "SRAW", 18215 argLen: 2, 18216 clobberFlags: true, 18217 asm: s390x.ASRAW, 18218 reg: regInfo{ 18219 inputs: []inputInfo{ 18220 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18221 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18222 }, 18223 outputs: []outputInfo{ 18224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18225 }, 18226 }, 18227 }, 18228 { 18229 name: "SRADconst", 18230 auxType: auxInt64, 18231 argLen: 1, 18232 clobberFlags: true, 18233 asm: s390x.ASRAD, 18234 reg: regInfo{ 18235 inputs: []inputInfo{ 18236 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18237 }, 18238 outputs: []outputInfo{ 18239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18240 }, 18241 }, 18242 }, 18243 { 18244 name: "SRAWconst", 18245 auxType: auxInt32, 18246 argLen: 1, 18247 clobberFlags: true, 18248 asm: s390x.ASRAW, 18249 reg: regInfo{ 18250 inputs: []inputInfo{ 18251 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18252 }, 18253 outputs: []outputInfo{ 18254 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18255 }, 18256 }, 18257 }, 18258 { 18259 name: "RLLGconst", 18260 auxType: auxInt64, 18261 argLen: 1, 18262 asm: s390x.ARLLG, 18263 reg: regInfo{ 18264 inputs: []inputInfo{ 18265 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18266 }, 18267 outputs: []outputInfo{ 18268 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18269 }, 18270 }, 18271 }, 18272 { 18273 name: "RLLconst", 18274 auxType: auxInt32, 18275 argLen: 1, 18276 asm: s390x.ARLL, 18277 reg: regInfo{ 18278 inputs: []inputInfo{ 18279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18280 }, 18281 outputs: []outputInfo{ 18282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18283 }, 18284 }, 18285 }, 18286 { 18287 name: "NEG", 18288 argLen: 1, 18289 clobberFlags: true, 18290 asm: s390x.ANEG, 18291 reg: regInfo{ 18292 inputs: []inputInfo{ 18293 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18294 }, 18295 outputs: []outputInfo{ 18296 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18297 }, 18298 }, 18299 }, 18300 { 18301 name: "NEGW", 18302 argLen: 1, 18303 clobberFlags: true, 18304 asm: s390x.ANEGW, 18305 reg: regInfo{ 18306 inputs: []inputInfo{ 18307 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18308 }, 18309 outputs: []outputInfo{ 18310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18311 }, 18312 }, 18313 }, 18314 { 18315 name: "NOT", 18316 argLen: 1, 18317 resultInArg0: true, 18318 clobberFlags: true, 18319 reg: regInfo{ 18320 inputs: []inputInfo{ 18321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18322 }, 18323 outputs: []outputInfo{ 18324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18325 }, 18326 }, 18327 }, 18328 { 18329 name: "NOTW", 18330 argLen: 1, 18331 resultInArg0: true, 18332 clobberFlags: true, 18333 reg: regInfo{ 18334 inputs: []inputInfo{ 18335 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18336 }, 18337 outputs: []outputInfo{ 18338 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18339 }, 18340 }, 18341 }, 18342 { 18343 name: "FSQRT", 18344 argLen: 1, 18345 asm: s390x.AFSQRT, 18346 reg: regInfo{ 18347 inputs: []inputInfo{ 18348 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18349 }, 18350 outputs: []outputInfo{ 18351 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18352 }, 18353 }, 18354 }, 18355 { 18356 name: "SUBEcarrymask", 18357 argLen: 1, 18358 asm: s390x.ASUBE, 18359 reg: regInfo{ 18360 outputs: []outputInfo{ 18361 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18362 }, 18363 }, 18364 }, 18365 { 18366 name: "SUBEWcarrymask", 18367 argLen: 1, 18368 asm: s390x.ASUBE, 18369 reg: regInfo{ 18370 outputs: []outputInfo{ 18371 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18372 }, 18373 }, 18374 }, 18375 { 18376 name: "MOVDEQ", 18377 argLen: 3, 18378 resultInArg0: true, 18379 asm: s390x.AMOVDEQ, 18380 reg: regInfo{ 18381 inputs: []inputInfo{ 18382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18383 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18384 }, 18385 outputs: []outputInfo{ 18386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18387 }, 18388 }, 18389 }, 18390 { 18391 name: "MOVDNE", 18392 argLen: 3, 18393 resultInArg0: true, 18394 asm: s390x.AMOVDNE, 18395 reg: regInfo{ 18396 inputs: []inputInfo{ 18397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18398 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18399 }, 18400 outputs: []outputInfo{ 18401 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18402 }, 18403 }, 18404 }, 18405 { 18406 name: "MOVDLT", 18407 argLen: 3, 18408 resultInArg0: true, 18409 asm: s390x.AMOVDLT, 18410 reg: regInfo{ 18411 inputs: []inputInfo{ 18412 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18413 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18414 }, 18415 outputs: []outputInfo{ 18416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18417 }, 18418 }, 18419 }, 18420 { 18421 name: "MOVDLE", 18422 argLen: 3, 18423 resultInArg0: true, 18424 asm: s390x.AMOVDLE, 18425 reg: regInfo{ 18426 inputs: []inputInfo{ 18427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18428 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18429 }, 18430 outputs: []outputInfo{ 18431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18432 }, 18433 }, 18434 }, 18435 { 18436 name: "MOVDGT", 18437 argLen: 3, 18438 resultInArg0: true, 18439 asm: s390x.AMOVDGT, 18440 reg: regInfo{ 18441 inputs: []inputInfo{ 18442 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18443 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18444 }, 18445 outputs: []outputInfo{ 18446 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18447 }, 18448 }, 18449 }, 18450 { 18451 name: "MOVDGE", 18452 argLen: 3, 18453 resultInArg0: true, 18454 asm: s390x.AMOVDGE, 18455 reg: regInfo{ 18456 inputs: []inputInfo{ 18457 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18458 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18459 }, 18460 outputs: []outputInfo{ 18461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18462 }, 18463 }, 18464 }, 18465 { 18466 name: "MOVDGTnoinv", 18467 argLen: 3, 18468 resultInArg0: true, 18469 asm: s390x.AMOVDGT, 18470 reg: regInfo{ 18471 inputs: []inputInfo{ 18472 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18473 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18474 }, 18475 outputs: []outputInfo{ 18476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18477 }, 18478 }, 18479 }, 18480 { 18481 name: "MOVDGEnoinv", 18482 argLen: 3, 18483 resultInArg0: true, 18484 asm: s390x.AMOVDGE, 18485 reg: regInfo{ 18486 inputs: []inputInfo{ 18487 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18488 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18489 }, 18490 outputs: []outputInfo{ 18491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18492 }, 18493 }, 18494 }, 18495 { 18496 name: "MOVBreg", 18497 argLen: 1, 18498 asm: s390x.AMOVB, 18499 reg: regInfo{ 18500 inputs: []inputInfo{ 18501 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18502 }, 18503 outputs: []outputInfo{ 18504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18505 }, 18506 }, 18507 }, 18508 { 18509 name: "MOVBZreg", 18510 argLen: 1, 18511 asm: s390x.AMOVBZ, 18512 reg: regInfo{ 18513 inputs: []inputInfo{ 18514 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18515 }, 18516 outputs: []outputInfo{ 18517 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18518 }, 18519 }, 18520 }, 18521 { 18522 name: "MOVHreg", 18523 argLen: 1, 18524 asm: s390x.AMOVH, 18525 reg: regInfo{ 18526 inputs: []inputInfo{ 18527 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18528 }, 18529 outputs: []outputInfo{ 18530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18531 }, 18532 }, 18533 }, 18534 { 18535 name: "MOVHZreg", 18536 argLen: 1, 18537 asm: s390x.AMOVHZ, 18538 reg: regInfo{ 18539 inputs: []inputInfo{ 18540 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18541 }, 18542 outputs: []outputInfo{ 18543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18544 }, 18545 }, 18546 }, 18547 { 18548 name: "MOVWreg", 18549 argLen: 1, 18550 asm: s390x.AMOVW, 18551 reg: regInfo{ 18552 inputs: []inputInfo{ 18553 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18554 }, 18555 outputs: []outputInfo{ 18556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18557 }, 18558 }, 18559 }, 18560 { 18561 name: "MOVWZreg", 18562 argLen: 1, 18563 asm: s390x.AMOVWZ, 18564 reg: regInfo{ 18565 inputs: []inputInfo{ 18566 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18567 }, 18568 outputs: []outputInfo{ 18569 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18570 }, 18571 }, 18572 }, 18573 { 18574 name: "MOVDconst", 18575 auxType: auxInt64, 18576 argLen: 0, 18577 rematerializeable: true, 18578 asm: s390x.AMOVD, 18579 reg: regInfo{ 18580 outputs: []outputInfo{ 18581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18582 }, 18583 }, 18584 }, 18585 { 18586 name: "CFDBRA", 18587 argLen: 1, 18588 asm: s390x.ACFDBRA, 18589 reg: regInfo{ 18590 inputs: []inputInfo{ 18591 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18592 }, 18593 outputs: []outputInfo{ 18594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18595 }, 18596 }, 18597 }, 18598 { 18599 name: "CGDBRA", 18600 argLen: 1, 18601 asm: s390x.ACGDBRA, 18602 reg: regInfo{ 18603 inputs: []inputInfo{ 18604 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18605 }, 18606 outputs: []outputInfo{ 18607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18608 }, 18609 }, 18610 }, 18611 { 18612 name: "CFEBRA", 18613 argLen: 1, 18614 asm: s390x.ACFEBRA, 18615 reg: regInfo{ 18616 inputs: []inputInfo{ 18617 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18618 }, 18619 outputs: []outputInfo{ 18620 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18621 }, 18622 }, 18623 }, 18624 { 18625 name: "CGEBRA", 18626 argLen: 1, 18627 asm: s390x.ACGEBRA, 18628 reg: regInfo{ 18629 inputs: []inputInfo{ 18630 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18631 }, 18632 outputs: []outputInfo{ 18633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18634 }, 18635 }, 18636 }, 18637 { 18638 name: "CEFBRA", 18639 argLen: 1, 18640 asm: s390x.ACEFBRA, 18641 reg: regInfo{ 18642 inputs: []inputInfo{ 18643 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18644 }, 18645 outputs: []outputInfo{ 18646 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18647 }, 18648 }, 18649 }, 18650 { 18651 name: "CDFBRA", 18652 argLen: 1, 18653 asm: s390x.ACDFBRA, 18654 reg: regInfo{ 18655 inputs: []inputInfo{ 18656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18657 }, 18658 outputs: []outputInfo{ 18659 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18660 }, 18661 }, 18662 }, 18663 { 18664 name: "CEGBRA", 18665 argLen: 1, 18666 asm: s390x.ACEGBRA, 18667 reg: regInfo{ 18668 inputs: []inputInfo{ 18669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18670 }, 18671 outputs: []outputInfo{ 18672 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18673 }, 18674 }, 18675 }, 18676 { 18677 name: "CDGBRA", 18678 argLen: 1, 18679 asm: s390x.ACDGBRA, 18680 reg: regInfo{ 18681 inputs: []inputInfo{ 18682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18683 }, 18684 outputs: []outputInfo{ 18685 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18686 }, 18687 }, 18688 }, 18689 { 18690 name: "LEDBR", 18691 argLen: 1, 18692 asm: s390x.ALEDBR, 18693 reg: regInfo{ 18694 inputs: []inputInfo{ 18695 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18696 }, 18697 outputs: []outputInfo{ 18698 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18699 }, 18700 }, 18701 }, 18702 { 18703 name: "LDEBR", 18704 argLen: 1, 18705 asm: s390x.ALDEBR, 18706 reg: regInfo{ 18707 inputs: []inputInfo{ 18708 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18709 }, 18710 outputs: []outputInfo{ 18711 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18712 }, 18713 }, 18714 }, 18715 { 18716 name: "MOVDaddr", 18717 auxType: auxSymOff, 18718 argLen: 1, 18719 rematerializeable: true, 18720 clobberFlags: true, 18721 reg: regInfo{ 18722 inputs: []inputInfo{ 18723 {0, 4295000064}, // SP SB 18724 }, 18725 outputs: []outputInfo{ 18726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18727 }, 18728 }, 18729 }, 18730 { 18731 name: "MOVDaddridx", 18732 auxType: auxSymOff, 18733 argLen: 2, 18734 clobberFlags: true, 18735 reg: regInfo{ 18736 inputs: []inputInfo{ 18737 {0, 4295000064}, // SP SB 18738 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18739 }, 18740 outputs: []outputInfo{ 18741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18742 }, 18743 }, 18744 }, 18745 { 18746 name: "MOVBZload", 18747 auxType: auxSymOff, 18748 argLen: 2, 18749 clobberFlags: true, 18750 faultOnNilArg0: true, 18751 asm: s390x.AMOVBZ, 18752 reg: regInfo{ 18753 inputs: []inputInfo{ 18754 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18755 }, 18756 outputs: []outputInfo{ 18757 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18758 }, 18759 }, 18760 }, 18761 { 18762 name: "MOVBload", 18763 auxType: auxSymOff, 18764 argLen: 2, 18765 clobberFlags: true, 18766 faultOnNilArg0: true, 18767 asm: s390x.AMOVB, 18768 reg: regInfo{ 18769 inputs: []inputInfo{ 18770 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18771 }, 18772 outputs: []outputInfo{ 18773 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18774 }, 18775 }, 18776 }, 18777 { 18778 name: "MOVHZload", 18779 auxType: auxSymOff, 18780 argLen: 2, 18781 clobberFlags: true, 18782 faultOnNilArg0: true, 18783 asm: s390x.AMOVHZ, 18784 reg: regInfo{ 18785 inputs: []inputInfo{ 18786 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18787 }, 18788 outputs: []outputInfo{ 18789 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18790 }, 18791 }, 18792 }, 18793 { 18794 name: "MOVHload", 18795 auxType: auxSymOff, 18796 argLen: 2, 18797 clobberFlags: true, 18798 faultOnNilArg0: true, 18799 asm: s390x.AMOVH, 18800 reg: regInfo{ 18801 inputs: []inputInfo{ 18802 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18803 }, 18804 outputs: []outputInfo{ 18805 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18806 }, 18807 }, 18808 }, 18809 { 18810 name: "MOVWZload", 18811 auxType: auxSymOff, 18812 argLen: 2, 18813 clobberFlags: true, 18814 faultOnNilArg0: true, 18815 asm: s390x.AMOVWZ, 18816 reg: regInfo{ 18817 inputs: []inputInfo{ 18818 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18819 }, 18820 outputs: []outputInfo{ 18821 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18822 }, 18823 }, 18824 }, 18825 { 18826 name: "MOVWload", 18827 auxType: auxSymOff, 18828 argLen: 2, 18829 clobberFlags: true, 18830 faultOnNilArg0: true, 18831 asm: s390x.AMOVW, 18832 reg: regInfo{ 18833 inputs: []inputInfo{ 18834 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18835 }, 18836 outputs: []outputInfo{ 18837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18838 }, 18839 }, 18840 }, 18841 { 18842 name: "MOVDload", 18843 auxType: auxSymOff, 18844 argLen: 2, 18845 clobberFlags: true, 18846 faultOnNilArg0: true, 18847 asm: s390x.AMOVD, 18848 reg: regInfo{ 18849 inputs: []inputInfo{ 18850 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18851 }, 18852 outputs: []outputInfo{ 18853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18854 }, 18855 }, 18856 }, 18857 { 18858 name: "MOVWBR", 18859 argLen: 1, 18860 asm: s390x.AMOVWBR, 18861 reg: regInfo{ 18862 inputs: []inputInfo{ 18863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18864 }, 18865 outputs: []outputInfo{ 18866 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18867 }, 18868 }, 18869 }, 18870 { 18871 name: "MOVDBR", 18872 argLen: 1, 18873 asm: s390x.AMOVDBR, 18874 reg: regInfo{ 18875 inputs: []inputInfo{ 18876 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18877 }, 18878 outputs: []outputInfo{ 18879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18880 }, 18881 }, 18882 }, 18883 { 18884 name: "MOVHBRload", 18885 auxType: auxSymOff, 18886 argLen: 2, 18887 clobberFlags: true, 18888 faultOnNilArg0: true, 18889 asm: s390x.AMOVHBR, 18890 reg: regInfo{ 18891 inputs: []inputInfo{ 18892 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18893 }, 18894 outputs: []outputInfo{ 18895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18896 }, 18897 }, 18898 }, 18899 { 18900 name: "MOVWBRload", 18901 auxType: auxSymOff, 18902 argLen: 2, 18903 clobberFlags: true, 18904 faultOnNilArg0: true, 18905 asm: s390x.AMOVWBR, 18906 reg: regInfo{ 18907 inputs: []inputInfo{ 18908 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18909 }, 18910 outputs: []outputInfo{ 18911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18912 }, 18913 }, 18914 }, 18915 { 18916 name: "MOVDBRload", 18917 auxType: auxSymOff, 18918 argLen: 2, 18919 clobberFlags: true, 18920 faultOnNilArg0: true, 18921 asm: s390x.AMOVDBR, 18922 reg: regInfo{ 18923 inputs: []inputInfo{ 18924 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18925 }, 18926 outputs: []outputInfo{ 18927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18928 }, 18929 }, 18930 }, 18931 { 18932 name: "MOVBstore", 18933 auxType: auxSymOff, 18934 argLen: 3, 18935 clobberFlags: true, 18936 faultOnNilArg0: true, 18937 asm: s390x.AMOVB, 18938 reg: regInfo{ 18939 inputs: []inputInfo{ 18940 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18941 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18942 }, 18943 }, 18944 }, 18945 { 18946 name: "MOVHstore", 18947 auxType: auxSymOff, 18948 argLen: 3, 18949 clobberFlags: true, 18950 faultOnNilArg0: true, 18951 asm: s390x.AMOVH, 18952 reg: regInfo{ 18953 inputs: []inputInfo{ 18954 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18955 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18956 }, 18957 }, 18958 }, 18959 { 18960 name: "MOVWstore", 18961 auxType: auxSymOff, 18962 argLen: 3, 18963 clobberFlags: true, 18964 faultOnNilArg0: true, 18965 asm: s390x.AMOVW, 18966 reg: regInfo{ 18967 inputs: []inputInfo{ 18968 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18969 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18970 }, 18971 }, 18972 }, 18973 { 18974 name: "MOVDstore", 18975 auxType: auxSymOff, 18976 argLen: 3, 18977 clobberFlags: true, 18978 faultOnNilArg0: true, 18979 asm: s390x.AMOVD, 18980 reg: regInfo{ 18981 inputs: []inputInfo{ 18982 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 18983 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18984 }, 18985 }, 18986 }, 18987 { 18988 name: "MOVHBRstore", 18989 auxType: auxSymOff, 18990 argLen: 3, 18991 clobberFlags: true, 18992 faultOnNilArg0: true, 18993 asm: s390x.AMOVHBR, 18994 reg: regInfo{ 18995 inputs: []inputInfo{ 18996 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18997 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 18998 }, 18999 }, 19000 }, 19001 { 19002 name: "MOVWBRstore", 19003 auxType: auxSymOff, 19004 argLen: 3, 19005 clobberFlags: true, 19006 faultOnNilArg0: true, 19007 asm: s390x.AMOVWBR, 19008 reg: regInfo{ 19009 inputs: []inputInfo{ 19010 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19011 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19012 }, 19013 }, 19014 }, 19015 { 19016 name: "MOVDBRstore", 19017 auxType: auxSymOff, 19018 argLen: 3, 19019 clobberFlags: true, 19020 faultOnNilArg0: true, 19021 asm: s390x.AMOVDBR, 19022 reg: regInfo{ 19023 inputs: []inputInfo{ 19024 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19025 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19026 }, 19027 }, 19028 }, 19029 { 19030 name: "MVC", 19031 auxType: auxSymValAndOff, 19032 argLen: 3, 19033 clobberFlags: true, 19034 faultOnNilArg0: true, 19035 faultOnNilArg1: true, 19036 asm: s390x.AMVC, 19037 reg: regInfo{ 19038 inputs: []inputInfo{ 19039 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19040 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19041 }, 19042 }, 19043 }, 19044 { 19045 name: "MOVBZloadidx", 19046 auxType: auxSymOff, 19047 argLen: 3, 19048 clobberFlags: true, 19049 asm: s390x.AMOVBZ, 19050 reg: regInfo{ 19051 inputs: []inputInfo{ 19052 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19053 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19054 }, 19055 outputs: []outputInfo{ 19056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19057 }, 19058 }, 19059 }, 19060 { 19061 name: "MOVHZloadidx", 19062 auxType: auxSymOff, 19063 argLen: 3, 19064 clobberFlags: true, 19065 asm: s390x.AMOVHZ, 19066 reg: regInfo{ 19067 inputs: []inputInfo{ 19068 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19069 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19070 }, 19071 outputs: []outputInfo{ 19072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19073 }, 19074 }, 19075 }, 19076 { 19077 name: "MOVWZloadidx", 19078 auxType: auxSymOff, 19079 argLen: 3, 19080 clobberFlags: true, 19081 asm: s390x.AMOVWZ, 19082 reg: regInfo{ 19083 inputs: []inputInfo{ 19084 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19085 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19086 }, 19087 outputs: []outputInfo{ 19088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19089 }, 19090 }, 19091 }, 19092 { 19093 name: "MOVDloadidx", 19094 auxType: auxSymOff, 19095 argLen: 3, 19096 clobberFlags: true, 19097 asm: s390x.AMOVD, 19098 reg: regInfo{ 19099 inputs: []inputInfo{ 19100 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19101 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19102 }, 19103 outputs: []outputInfo{ 19104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19105 }, 19106 }, 19107 }, 19108 { 19109 name: "MOVHBRloadidx", 19110 auxType: auxSymOff, 19111 argLen: 3, 19112 clobberFlags: true, 19113 asm: s390x.AMOVHBR, 19114 reg: regInfo{ 19115 inputs: []inputInfo{ 19116 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19117 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19118 }, 19119 outputs: []outputInfo{ 19120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19121 }, 19122 }, 19123 }, 19124 { 19125 name: "MOVWBRloadidx", 19126 auxType: auxSymOff, 19127 argLen: 3, 19128 clobberFlags: true, 19129 asm: s390x.AMOVWBR, 19130 reg: regInfo{ 19131 inputs: []inputInfo{ 19132 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19133 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19134 }, 19135 outputs: []outputInfo{ 19136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19137 }, 19138 }, 19139 }, 19140 { 19141 name: "MOVDBRloadidx", 19142 auxType: auxSymOff, 19143 argLen: 3, 19144 clobberFlags: true, 19145 asm: s390x.AMOVDBR, 19146 reg: regInfo{ 19147 inputs: []inputInfo{ 19148 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19149 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19150 }, 19151 outputs: []outputInfo{ 19152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19153 }, 19154 }, 19155 }, 19156 { 19157 name: "MOVBstoreidx", 19158 auxType: auxSymOff, 19159 argLen: 4, 19160 clobberFlags: true, 19161 asm: s390x.AMOVB, 19162 reg: regInfo{ 19163 inputs: []inputInfo{ 19164 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19165 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19166 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19167 }, 19168 }, 19169 }, 19170 { 19171 name: "MOVHstoreidx", 19172 auxType: auxSymOff, 19173 argLen: 4, 19174 clobberFlags: true, 19175 asm: s390x.AMOVH, 19176 reg: regInfo{ 19177 inputs: []inputInfo{ 19178 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19179 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19180 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19181 }, 19182 }, 19183 }, 19184 { 19185 name: "MOVWstoreidx", 19186 auxType: auxSymOff, 19187 argLen: 4, 19188 clobberFlags: true, 19189 asm: s390x.AMOVW, 19190 reg: regInfo{ 19191 inputs: []inputInfo{ 19192 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19193 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19194 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19195 }, 19196 }, 19197 }, 19198 { 19199 name: "MOVDstoreidx", 19200 auxType: auxSymOff, 19201 argLen: 4, 19202 clobberFlags: true, 19203 asm: s390x.AMOVD, 19204 reg: regInfo{ 19205 inputs: []inputInfo{ 19206 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19207 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19208 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19209 }, 19210 }, 19211 }, 19212 { 19213 name: "MOVHBRstoreidx", 19214 auxType: auxSymOff, 19215 argLen: 4, 19216 clobberFlags: true, 19217 asm: s390x.AMOVHBR, 19218 reg: regInfo{ 19219 inputs: []inputInfo{ 19220 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19221 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19222 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19223 }, 19224 }, 19225 }, 19226 { 19227 name: "MOVWBRstoreidx", 19228 auxType: auxSymOff, 19229 argLen: 4, 19230 clobberFlags: true, 19231 asm: s390x.AMOVWBR, 19232 reg: regInfo{ 19233 inputs: []inputInfo{ 19234 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19235 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19236 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19237 }, 19238 }, 19239 }, 19240 { 19241 name: "MOVDBRstoreidx", 19242 auxType: auxSymOff, 19243 argLen: 4, 19244 clobberFlags: true, 19245 asm: s390x.AMOVDBR, 19246 reg: regInfo{ 19247 inputs: []inputInfo{ 19248 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19249 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19250 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19251 }, 19252 }, 19253 }, 19254 { 19255 name: "MOVBstoreconst", 19256 auxType: auxSymValAndOff, 19257 argLen: 2, 19258 clobberFlags: true, 19259 faultOnNilArg0: true, 19260 asm: s390x.AMOVB, 19261 reg: regInfo{ 19262 inputs: []inputInfo{ 19263 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19264 }, 19265 }, 19266 }, 19267 { 19268 name: "MOVHstoreconst", 19269 auxType: auxSymValAndOff, 19270 argLen: 2, 19271 clobberFlags: true, 19272 faultOnNilArg0: true, 19273 asm: s390x.AMOVH, 19274 reg: regInfo{ 19275 inputs: []inputInfo{ 19276 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19277 }, 19278 }, 19279 }, 19280 { 19281 name: "MOVWstoreconst", 19282 auxType: auxSymValAndOff, 19283 argLen: 2, 19284 clobberFlags: true, 19285 faultOnNilArg0: true, 19286 asm: s390x.AMOVW, 19287 reg: regInfo{ 19288 inputs: []inputInfo{ 19289 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19290 }, 19291 }, 19292 }, 19293 { 19294 name: "MOVDstoreconst", 19295 auxType: auxSymValAndOff, 19296 argLen: 2, 19297 clobberFlags: true, 19298 faultOnNilArg0: true, 19299 asm: s390x.AMOVD, 19300 reg: regInfo{ 19301 inputs: []inputInfo{ 19302 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19303 }, 19304 }, 19305 }, 19306 { 19307 name: "CLEAR", 19308 auxType: auxSymValAndOff, 19309 argLen: 2, 19310 clobberFlags: true, 19311 faultOnNilArg0: true, 19312 asm: s390x.ACLEAR, 19313 reg: regInfo{ 19314 inputs: []inputInfo{ 19315 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19316 }, 19317 }, 19318 }, 19319 { 19320 name: "CALLstatic", 19321 auxType: auxSymOff, 19322 argLen: 1, 19323 clobberFlags: true, 19324 call: true, 19325 reg: regInfo{ 19326 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19327 }, 19328 }, 19329 { 19330 name: "CALLclosure", 19331 auxType: auxInt64, 19332 argLen: 3, 19333 clobberFlags: true, 19334 call: true, 19335 reg: regInfo{ 19336 inputs: []inputInfo{ 19337 {1, 4096}, // R12 19338 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19339 }, 19340 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19341 }, 19342 }, 19343 { 19344 name: "CALLdefer", 19345 auxType: auxInt64, 19346 argLen: 1, 19347 clobberFlags: true, 19348 call: true, 19349 reg: regInfo{ 19350 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19351 }, 19352 }, 19353 { 19354 name: "CALLgo", 19355 auxType: auxInt64, 19356 argLen: 1, 19357 clobberFlags: true, 19358 call: true, 19359 reg: regInfo{ 19360 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19361 }, 19362 }, 19363 { 19364 name: "CALLinter", 19365 auxType: auxInt64, 19366 argLen: 2, 19367 clobberFlags: true, 19368 call: true, 19369 reg: regInfo{ 19370 inputs: []inputInfo{ 19371 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19372 }, 19373 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19374 }, 19375 }, 19376 { 19377 name: "InvertFlags", 19378 argLen: 1, 19379 reg: regInfo{}, 19380 }, 19381 { 19382 name: "LoweredGetG", 19383 argLen: 1, 19384 reg: regInfo{ 19385 outputs: []outputInfo{ 19386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19387 }, 19388 }, 19389 }, 19390 { 19391 name: "LoweredGetClosurePtr", 19392 argLen: 0, 19393 reg: regInfo{ 19394 outputs: []outputInfo{ 19395 {0, 4096}, // R12 19396 }, 19397 }, 19398 }, 19399 { 19400 name: "LoweredNilCheck", 19401 argLen: 2, 19402 clobberFlags: true, 19403 nilCheck: true, 19404 faultOnNilArg0: true, 19405 reg: regInfo{ 19406 inputs: []inputInfo{ 19407 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19408 }, 19409 }, 19410 }, 19411 { 19412 name: "MOVDconvert", 19413 argLen: 2, 19414 asm: s390x.AMOVD, 19415 reg: regInfo{ 19416 inputs: []inputInfo{ 19417 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19418 }, 19419 outputs: []outputInfo{ 19420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19421 }, 19422 }, 19423 }, 19424 { 19425 name: "FlagEQ", 19426 argLen: 0, 19427 reg: regInfo{}, 19428 }, 19429 { 19430 name: "FlagLT", 19431 argLen: 0, 19432 reg: regInfo{}, 19433 }, 19434 { 19435 name: "FlagGT", 19436 argLen: 0, 19437 reg: regInfo{}, 19438 }, 19439 { 19440 name: "MOVWZatomicload", 19441 auxType: auxSymOff, 19442 argLen: 2, 19443 faultOnNilArg0: true, 19444 asm: s390x.AMOVWZ, 19445 reg: regInfo{ 19446 inputs: []inputInfo{ 19447 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19448 }, 19449 outputs: []outputInfo{ 19450 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19451 }, 19452 }, 19453 }, 19454 { 19455 name: "MOVDatomicload", 19456 auxType: auxSymOff, 19457 argLen: 2, 19458 faultOnNilArg0: true, 19459 asm: s390x.AMOVD, 19460 reg: regInfo{ 19461 inputs: []inputInfo{ 19462 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19463 }, 19464 outputs: []outputInfo{ 19465 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19466 }, 19467 }, 19468 }, 19469 { 19470 name: "MOVWatomicstore", 19471 auxType: auxSymOff, 19472 argLen: 3, 19473 clobberFlags: true, 19474 faultOnNilArg0: true, 19475 asm: s390x.AMOVW, 19476 reg: regInfo{ 19477 inputs: []inputInfo{ 19478 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19479 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19480 }, 19481 }, 19482 }, 19483 { 19484 name: "MOVDatomicstore", 19485 auxType: auxSymOff, 19486 argLen: 3, 19487 clobberFlags: true, 19488 faultOnNilArg0: true, 19489 asm: s390x.AMOVD, 19490 reg: regInfo{ 19491 inputs: []inputInfo{ 19492 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19493 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19494 }, 19495 }, 19496 }, 19497 { 19498 name: "LAA", 19499 auxType: auxSymOff, 19500 argLen: 3, 19501 faultOnNilArg0: true, 19502 asm: s390x.ALAA, 19503 reg: regInfo{ 19504 inputs: []inputInfo{ 19505 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19506 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19507 }, 19508 outputs: []outputInfo{ 19509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19510 }, 19511 }, 19512 }, 19513 { 19514 name: "LAAG", 19515 auxType: auxSymOff, 19516 argLen: 3, 19517 faultOnNilArg0: true, 19518 asm: s390x.ALAAG, 19519 reg: regInfo{ 19520 inputs: []inputInfo{ 19521 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19522 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19523 }, 19524 outputs: []outputInfo{ 19525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19526 }, 19527 }, 19528 }, 19529 { 19530 name: "AddTupleFirst32", 19531 argLen: 2, 19532 reg: regInfo{}, 19533 }, 19534 { 19535 name: "AddTupleFirst64", 19536 argLen: 2, 19537 reg: regInfo{}, 19538 }, 19539 { 19540 name: "LoweredAtomicCas32", 19541 auxType: auxSymOff, 19542 argLen: 4, 19543 clobberFlags: true, 19544 faultOnNilArg0: true, 19545 asm: s390x.ACS, 19546 reg: regInfo{ 19547 inputs: []inputInfo{ 19548 {1, 1}, // R0 19549 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19550 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19551 }, 19552 clobbers: 1, // R0 19553 outputs: []outputInfo{ 19554 {1, 0}, 19555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19556 }, 19557 }, 19558 }, 19559 { 19560 name: "LoweredAtomicCas64", 19561 auxType: auxSymOff, 19562 argLen: 4, 19563 clobberFlags: true, 19564 faultOnNilArg0: true, 19565 asm: s390x.ACSG, 19566 reg: regInfo{ 19567 inputs: []inputInfo{ 19568 {1, 1}, // R0 19569 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19570 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19571 }, 19572 clobbers: 1, // R0 19573 outputs: []outputInfo{ 19574 {1, 0}, 19575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19576 }, 19577 }, 19578 }, 19579 { 19580 name: "LoweredAtomicExchange32", 19581 auxType: auxSymOff, 19582 argLen: 3, 19583 clobberFlags: true, 19584 faultOnNilArg0: true, 19585 asm: s390x.ACS, 19586 reg: regInfo{ 19587 inputs: []inputInfo{ 19588 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19589 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19590 }, 19591 outputs: []outputInfo{ 19592 {1, 0}, 19593 {0, 1}, // R0 19594 }, 19595 }, 19596 }, 19597 { 19598 name: "LoweredAtomicExchange64", 19599 auxType: auxSymOff, 19600 argLen: 3, 19601 clobberFlags: true, 19602 faultOnNilArg0: true, 19603 asm: s390x.ACSG, 19604 reg: regInfo{ 19605 inputs: []inputInfo{ 19606 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19607 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19608 }, 19609 outputs: []outputInfo{ 19610 {1, 0}, 19611 {0, 1}, // R0 19612 }, 19613 }, 19614 }, 19615 { 19616 name: "FLOGR", 19617 argLen: 1, 19618 clobberFlags: true, 19619 asm: s390x.AFLOGR, 19620 reg: regInfo{ 19621 inputs: []inputInfo{ 19622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19623 }, 19624 clobbers: 2, // R1 19625 outputs: []outputInfo{ 19626 {0, 1}, // R0 19627 }, 19628 }, 19629 }, 19630 { 19631 name: "STMG2", 19632 auxType: auxSymOff, 19633 argLen: 4, 19634 faultOnNilArg0: true, 19635 asm: s390x.ASTMG, 19636 reg: regInfo{ 19637 inputs: []inputInfo{ 19638 {1, 2}, // R1 19639 {2, 4}, // R2 19640 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19641 }, 19642 }, 19643 }, 19644 { 19645 name: "STMG3", 19646 auxType: auxSymOff, 19647 argLen: 5, 19648 faultOnNilArg0: true, 19649 asm: s390x.ASTMG, 19650 reg: regInfo{ 19651 inputs: []inputInfo{ 19652 {1, 2}, // R1 19653 {2, 4}, // R2 19654 {3, 8}, // R3 19655 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19656 }, 19657 }, 19658 }, 19659 { 19660 name: "STMG4", 19661 auxType: auxSymOff, 19662 argLen: 6, 19663 faultOnNilArg0: true, 19664 asm: s390x.ASTMG, 19665 reg: regInfo{ 19666 inputs: []inputInfo{ 19667 {1, 2}, // R1 19668 {2, 4}, // R2 19669 {3, 8}, // R3 19670 {4, 16}, // R4 19671 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19672 }, 19673 }, 19674 }, 19675 { 19676 name: "STM2", 19677 auxType: auxSymOff, 19678 argLen: 4, 19679 faultOnNilArg0: true, 19680 asm: s390x.ASTMY, 19681 reg: regInfo{ 19682 inputs: []inputInfo{ 19683 {1, 2}, // R1 19684 {2, 4}, // R2 19685 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19686 }, 19687 }, 19688 }, 19689 { 19690 name: "STM3", 19691 auxType: auxSymOff, 19692 argLen: 5, 19693 faultOnNilArg0: true, 19694 asm: s390x.ASTMY, 19695 reg: regInfo{ 19696 inputs: []inputInfo{ 19697 {1, 2}, // R1 19698 {2, 4}, // R2 19699 {3, 8}, // R3 19700 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19701 }, 19702 }, 19703 }, 19704 { 19705 name: "STM4", 19706 auxType: auxSymOff, 19707 argLen: 6, 19708 faultOnNilArg0: true, 19709 asm: s390x.ASTMY, 19710 reg: regInfo{ 19711 inputs: []inputInfo{ 19712 {1, 2}, // R1 19713 {2, 4}, // R2 19714 {3, 8}, // R3 19715 {4, 16}, // R4 19716 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19717 }, 19718 }, 19719 }, 19720 { 19721 name: "LoweredMove", 19722 auxType: auxInt64, 19723 argLen: 4, 19724 clobberFlags: true, 19725 reg: regInfo{ 19726 inputs: []inputInfo{ 19727 {0, 2}, // R1 19728 {1, 4}, // R2 19729 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19730 }, 19731 clobbers: 6, // R1 R2 19732 }, 19733 }, 19734 { 19735 name: "LoweredZero", 19736 auxType: auxInt64, 19737 argLen: 3, 19738 clobberFlags: true, 19739 reg: regInfo{ 19740 inputs: []inputInfo{ 19741 {0, 2}, // R1 19742 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19743 }, 19744 clobbers: 2, // R1 19745 }, 19746 }, 19747 19748 { 19749 name: "Add8", 19750 argLen: 2, 19751 commutative: true, 19752 generic: true, 19753 }, 19754 { 19755 name: "Add16", 19756 argLen: 2, 19757 commutative: true, 19758 generic: true, 19759 }, 19760 { 19761 name: "Add32", 19762 argLen: 2, 19763 commutative: true, 19764 generic: true, 19765 }, 19766 { 19767 name: "Add64", 19768 argLen: 2, 19769 commutative: true, 19770 generic: true, 19771 }, 19772 { 19773 name: "AddPtr", 19774 argLen: 2, 19775 generic: true, 19776 }, 19777 { 19778 name: "Add32F", 19779 argLen: 2, 19780 generic: true, 19781 }, 19782 { 19783 name: "Add64F", 19784 argLen: 2, 19785 generic: true, 19786 }, 19787 { 19788 name: "Sub8", 19789 argLen: 2, 19790 generic: true, 19791 }, 19792 { 19793 name: "Sub16", 19794 argLen: 2, 19795 generic: true, 19796 }, 19797 { 19798 name: "Sub32", 19799 argLen: 2, 19800 generic: true, 19801 }, 19802 { 19803 name: "Sub64", 19804 argLen: 2, 19805 generic: true, 19806 }, 19807 { 19808 name: "SubPtr", 19809 argLen: 2, 19810 generic: true, 19811 }, 19812 { 19813 name: "Sub32F", 19814 argLen: 2, 19815 generic: true, 19816 }, 19817 { 19818 name: "Sub64F", 19819 argLen: 2, 19820 generic: true, 19821 }, 19822 { 19823 name: "Mul8", 19824 argLen: 2, 19825 commutative: true, 19826 generic: true, 19827 }, 19828 { 19829 name: "Mul16", 19830 argLen: 2, 19831 commutative: true, 19832 generic: true, 19833 }, 19834 { 19835 name: "Mul32", 19836 argLen: 2, 19837 commutative: true, 19838 generic: true, 19839 }, 19840 { 19841 name: "Mul64", 19842 argLen: 2, 19843 commutative: true, 19844 generic: true, 19845 }, 19846 { 19847 name: "Mul32F", 19848 argLen: 2, 19849 generic: true, 19850 }, 19851 { 19852 name: "Mul64F", 19853 argLen: 2, 19854 generic: true, 19855 }, 19856 { 19857 name: "Div32F", 19858 argLen: 2, 19859 generic: true, 19860 }, 19861 { 19862 name: "Div64F", 19863 argLen: 2, 19864 generic: true, 19865 }, 19866 { 19867 name: "Hmul8", 19868 argLen: 2, 19869 generic: true, 19870 }, 19871 { 19872 name: "Hmul8u", 19873 argLen: 2, 19874 generic: true, 19875 }, 19876 { 19877 name: "Hmul16", 19878 argLen: 2, 19879 generic: true, 19880 }, 19881 { 19882 name: "Hmul16u", 19883 argLen: 2, 19884 generic: true, 19885 }, 19886 { 19887 name: "Hmul32", 19888 argLen: 2, 19889 generic: true, 19890 }, 19891 { 19892 name: "Hmul32u", 19893 argLen: 2, 19894 generic: true, 19895 }, 19896 { 19897 name: "Hmul64", 19898 argLen: 2, 19899 generic: true, 19900 }, 19901 { 19902 name: "Hmul64u", 19903 argLen: 2, 19904 generic: true, 19905 }, 19906 { 19907 name: "Mul32uhilo", 19908 argLen: 2, 19909 generic: true, 19910 }, 19911 { 19912 name: "Mul64uhilo", 19913 argLen: 2, 19914 generic: true, 19915 }, 19916 { 19917 name: "Avg64u", 19918 argLen: 2, 19919 generic: true, 19920 }, 19921 { 19922 name: "Div8", 19923 argLen: 2, 19924 generic: true, 19925 }, 19926 { 19927 name: "Div8u", 19928 argLen: 2, 19929 generic: true, 19930 }, 19931 { 19932 name: "Div16", 19933 argLen: 2, 19934 generic: true, 19935 }, 19936 { 19937 name: "Div16u", 19938 argLen: 2, 19939 generic: true, 19940 }, 19941 { 19942 name: "Div32", 19943 argLen: 2, 19944 generic: true, 19945 }, 19946 { 19947 name: "Div32u", 19948 argLen: 2, 19949 generic: true, 19950 }, 19951 { 19952 name: "Div64", 19953 argLen: 2, 19954 generic: true, 19955 }, 19956 { 19957 name: "Div64u", 19958 argLen: 2, 19959 generic: true, 19960 }, 19961 { 19962 name: "Div128u", 19963 argLen: 3, 19964 generic: true, 19965 }, 19966 { 19967 name: "Mod8", 19968 argLen: 2, 19969 generic: true, 19970 }, 19971 { 19972 name: "Mod8u", 19973 argLen: 2, 19974 generic: true, 19975 }, 19976 { 19977 name: "Mod16", 19978 argLen: 2, 19979 generic: true, 19980 }, 19981 { 19982 name: "Mod16u", 19983 argLen: 2, 19984 generic: true, 19985 }, 19986 { 19987 name: "Mod32", 19988 argLen: 2, 19989 generic: true, 19990 }, 19991 { 19992 name: "Mod32u", 19993 argLen: 2, 19994 generic: true, 19995 }, 19996 { 19997 name: "Mod64", 19998 argLen: 2, 19999 generic: true, 20000 }, 20001 { 20002 name: "Mod64u", 20003 argLen: 2, 20004 generic: true, 20005 }, 20006 { 20007 name: "And8", 20008 argLen: 2, 20009 commutative: true, 20010 generic: true, 20011 }, 20012 { 20013 name: "And16", 20014 argLen: 2, 20015 commutative: true, 20016 generic: true, 20017 }, 20018 { 20019 name: "And32", 20020 argLen: 2, 20021 commutative: true, 20022 generic: true, 20023 }, 20024 { 20025 name: "And64", 20026 argLen: 2, 20027 commutative: true, 20028 generic: true, 20029 }, 20030 { 20031 name: "Or8", 20032 argLen: 2, 20033 commutative: true, 20034 generic: true, 20035 }, 20036 { 20037 name: "Or16", 20038 argLen: 2, 20039 commutative: true, 20040 generic: true, 20041 }, 20042 { 20043 name: "Or32", 20044 argLen: 2, 20045 commutative: true, 20046 generic: true, 20047 }, 20048 { 20049 name: "Or64", 20050 argLen: 2, 20051 commutative: true, 20052 generic: true, 20053 }, 20054 { 20055 name: "Xor8", 20056 argLen: 2, 20057 commutative: true, 20058 generic: true, 20059 }, 20060 { 20061 name: "Xor16", 20062 argLen: 2, 20063 commutative: true, 20064 generic: true, 20065 }, 20066 { 20067 name: "Xor32", 20068 argLen: 2, 20069 commutative: true, 20070 generic: true, 20071 }, 20072 { 20073 name: "Xor64", 20074 argLen: 2, 20075 commutative: true, 20076 generic: true, 20077 }, 20078 { 20079 name: "Lsh8x8", 20080 argLen: 2, 20081 generic: true, 20082 }, 20083 { 20084 name: "Lsh8x16", 20085 argLen: 2, 20086 generic: true, 20087 }, 20088 { 20089 name: "Lsh8x32", 20090 argLen: 2, 20091 generic: true, 20092 }, 20093 { 20094 name: "Lsh8x64", 20095 argLen: 2, 20096 generic: true, 20097 }, 20098 { 20099 name: "Lsh16x8", 20100 argLen: 2, 20101 generic: true, 20102 }, 20103 { 20104 name: "Lsh16x16", 20105 argLen: 2, 20106 generic: true, 20107 }, 20108 { 20109 name: "Lsh16x32", 20110 argLen: 2, 20111 generic: true, 20112 }, 20113 { 20114 name: "Lsh16x64", 20115 argLen: 2, 20116 generic: true, 20117 }, 20118 { 20119 name: "Lsh32x8", 20120 argLen: 2, 20121 generic: true, 20122 }, 20123 { 20124 name: "Lsh32x16", 20125 argLen: 2, 20126 generic: true, 20127 }, 20128 { 20129 name: "Lsh32x32", 20130 argLen: 2, 20131 generic: true, 20132 }, 20133 { 20134 name: "Lsh32x64", 20135 argLen: 2, 20136 generic: true, 20137 }, 20138 { 20139 name: "Lsh64x8", 20140 argLen: 2, 20141 generic: true, 20142 }, 20143 { 20144 name: "Lsh64x16", 20145 argLen: 2, 20146 generic: true, 20147 }, 20148 { 20149 name: "Lsh64x32", 20150 argLen: 2, 20151 generic: true, 20152 }, 20153 { 20154 name: "Lsh64x64", 20155 argLen: 2, 20156 generic: true, 20157 }, 20158 { 20159 name: "Rsh8x8", 20160 argLen: 2, 20161 generic: true, 20162 }, 20163 { 20164 name: "Rsh8x16", 20165 argLen: 2, 20166 generic: true, 20167 }, 20168 { 20169 name: "Rsh8x32", 20170 argLen: 2, 20171 generic: true, 20172 }, 20173 { 20174 name: "Rsh8x64", 20175 argLen: 2, 20176 generic: true, 20177 }, 20178 { 20179 name: "Rsh16x8", 20180 argLen: 2, 20181 generic: true, 20182 }, 20183 { 20184 name: "Rsh16x16", 20185 argLen: 2, 20186 generic: true, 20187 }, 20188 { 20189 name: "Rsh16x32", 20190 argLen: 2, 20191 generic: true, 20192 }, 20193 { 20194 name: "Rsh16x64", 20195 argLen: 2, 20196 generic: true, 20197 }, 20198 { 20199 name: "Rsh32x8", 20200 argLen: 2, 20201 generic: true, 20202 }, 20203 { 20204 name: "Rsh32x16", 20205 argLen: 2, 20206 generic: true, 20207 }, 20208 { 20209 name: "Rsh32x32", 20210 argLen: 2, 20211 generic: true, 20212 }, 20213 { 20214 name: "Rsh32x64", 20215 argLen: 2, 20216 generic: true, 20217 }, 20218 { 20219 name: "Rsh64x8", 20220 argLen: 2, 20221 generic: true, 20222 }, 20223 { 20224 name: "Rsh64x16", 20225 argLen: 2, 20226 generic: true, 20227 }, 20228 { 20229 name: "Rsh64x32", 20230 argLen: 2, 20231 generic: true, 20232 }, 20233 { 20234 name: "Rsh64x64", 20235 argLen: 2, 20236 generic: true, 20237 }, 20238 { 20239 name: "Rsh8Ux8", 20240 argLen: 2, 20241 generic: true, 20242 }, 20243 { 20244 name: "Rsh8Ux16", 20245 argLen: 2, 20246 generic: true, 20247 }, 20248 { 20249 name: "Rsh8Ux32", 20250 argLen: 2, 20251 generic: true, 20252 }, 20253 { 20254 name: "Rsh8Ux64", 20255 argLen: 2, 20256 generic: true, 20257 }, 20258 { 20259 name: "Rsh16Ux8", 20260 argLen: 2, 20261 generic: true, 20262 }, 20263 { 20264 name: "Rsh16Ux16", 20265 argLen: 2, 20266 generic: true, 20267 }, 20268 { 20269 name: "Rsh16Ux32", 20270 argLen: 2, 20271 generic: true, 20272 }, 20273 { 20274 name: "Rsh16Ux64", 20275 argLen: 2, 20276 generic: true, 20277 }, 20278 { 20279 name: "Rsh32Ux8", 20280 argLen: 2, 20281 generic: true, 20282 }, 20283 { 20284 name: "Rsh32Ux16", 20285 argLen: 2, 20286 generic: true, 20287 }, 20288 { 20289 name: "Rsh32Ux32", 20290 argLen: 2, 20291 generic: true, 20292 }, 20293 { 20294 name: "Rsh32Ux64", 20295 argLen: 2, 20296 generic: true, 20297 }, 20298 { 20299 name: "Rsh64Ux8", 20300 argLen: 2, 20301 generic: true, 20302 }, 20303 { 20304 name: "Rsh64Ux16", 20305 argLen: 2, 20306 generic: true, 20307 }, 20308 { 20309 name: "Rsh64Ux32", 20310 argLen: 2, 20311 generic: true, 20312 }, 20313 { 20314 name: "Rsh64Ux64", 20315 argLen: 2, 20316 generic: true, 20317 }, 20318 { 20319 name: "Lrot8", 20320 auxType: auxInt64, 20321 argLen: 1, 20322 generic: true, 20323 }, 20324 { 20325 name: "Lrot16", 20326 auxType: auxInt64, 20327 argLen: 1, 20328 generic: true, 20329 }, 20330 { 20331 name: "Lrot32", 20332 auxType: auxInt64, 20333 argLen: 1, 20334 generic: true, 20335 }, 20336 { 20337 name: "Lrot64", 20338 auxType: auxInt64, 20339 argLen: 1, 20340 generic: true, 20341 }, 20342 { 20343 name: "Eq8", 20344 argLen: 2, 20345 commutative: true, 20346 generic: true, 20347 }, 20348 { 20349 name: "Eq16", 20350 argLen: 2, 20351 commutative: true, 20352 generic: true, 20353 }, 20354 { 20355 name: "Eq32", 20356 argLen: 2, 20357 commutative: true, 20358 generic: true, 20359 }, 20360 { 20361 name: "Eq64", 20362 argLen: 2, 20363 commutative: true, 20364 generic: true, 20365 }, 20366 { 20367 name: "EqPtr", 20368 argLen: 2, 20369 commutative: true, 20370 generic: true, 20371 }, 20372 { 20373 name: "EqInter", 20374 argLen: 2, 20375 generic: true, 20376 }, 20377 { 20378 name: "EqSlice", 20379 argLen: 2, 20380 generic: true, 20381 }, 20382 { 20383 name: "Eq32F", 20384 argLen: 2, 20385 generic: true, 20386 }, 20387 { 20388 name: "Eq64F", 20389 argLen: 2, 20390 generic: true, 20391 }, 20392 { 20393 name: "Neq8", 20394 argLen: 2, 20395 commutative: true, 20396 generic: true, 20397 }, 20398 { 20399 name: "Neq16", 20400 argLen: 2, 20401 commutative: true, 20402 generic: true, 20403 }, 20404 { 20405 name: "Neq32", 20406 argLen: 2, 20407 commutative: true, 20408 generic: true, 20409 }, 20410 { 20411 name: "Neq64", 20412 argLen: 2, 20413 commutative: true, 20414 generic: true, 20415 }, 20416 { 20417 name: "NeqPtr", 20418 argLen: 2, 20419 commutative: true, 20420 generic: true, 20421 }, 20422 { 20423 name: "NeqInter", 20424 argLen: 2, 20425 generic: true, 20426 }, 20427 { 20428 name: "NeqSlice", 20429 argLen: 2, 20430 generic: true, 20431 }, 20432 { 20433 name: "Neq32F", 20434 argLen: 2, 20435 generic: true, 20436 }, 20437 { 20438 name: "Neq64F", 20439 argLen: 2, 20440 generic: true, 20441 }, 20442 { 20443 name: "Less8", 20444 argLen: 2, 20445 generic: true, 20446 }, 20447 { 20448 name: "Less8U", 20449 argLen: 2, 20450 generic: true, 20451 }, 20452 { 20453 name: "Less16", 20454 argLen: 2, 20455 generic: true, 20456 }, 20457 { 20458 name: "Less16U", 20459 argLen: 2, 20460 generic: true, 20461 }, 20462 { 20463 name: "Less32", 20464 argLen: 2, 20465 generic: true, 20466 }, 20467 { 20468 name: "Less32U", 20469 argLen: 2, 20470 generic: true, 20471 }, 20472 { 20473 name: "Less64", 20474 argLen: 2, 20475 generic: true, 20476 }, 20477 { 20478 name: "Less64U", 20479 argLen: 2, 20480 generic: true, 20481 }, 20482 { 20483 name: "Less32F", 20484 argLen: 2, 20485 generic: true, 20486 }, 20487 { 20488 name: "Less64F", 20489 argLen: 2, 20490 generic: true, 20491 }, 20492 { 20493 name: "Leq8", 20494 argLen: 2, 20495 generic: true, 20496 }, 20497 { 20498 name: "Leq8U", 20499 argLen: 2, 20500 generic: true, 20501 }, 20502 { 20503 name: "Leq16", 20504 argLen: 2, 20505 generic: true, 20506 }, 20507 { 20508 name: "Leq16U", 20509 argLen: 2, 20510 generic: true, 20511 }, 20512 { 20513 name: "Leq32", 20514 argLen: 2, 20515 generic: true, 20516 }, 20517 { 20518 name: "Leq32U", 20519 argLen: 2, 20520 generic: true, 20521 }, 20522 { 20523 name: "Leq64", 20524 argLen: 2, 20525 generic: true, 20526 }, 20527 { 20528 name: "Leq64U", 20529 argLen: 2, 20530 generic: true, 20531 }, 20532 { 20533 name: "Leq32F", 20534 argLen: 2, 20535 generic: true, 20536 }, 20537 { 20538 name: "Leq64F", 20539 argLen: 2, 20540 generic: true, 20541 }, 20542 { 20543 name: "Greater8", 20544 argLen: 2, 20545 generic: true, 20546 }, 20547 { 20548 name: "Greater8U", 20549 argLen: 2, 20550 generic: true, 20551 }, 20552 { 20553 name: "Greater16", 20554 argLen: 2, 20555 generic: true, 20556 }, 20557 { 20558 name: "Greater16U", 20559 argLen: 2, 20560 generic: true, 20561 }, 20562 { 20563 name: "Greater32", 20564 argLen: 2, 20565 generic: true, 20566 }, 20567 { 20568 name: "Greater32U", 20569 argLen: 2, 20570 generic: true, 20571 }, 20572 { 20573 name: "Greater64", 20574 argLen: 2, 20575 generic: true, 20576 }, 20577 { 20578 name: "Greater64U", 20579 argLen: 2, 20580 generic: true, 20581 }, 20582 { 20583 name: "Greater32F", 20584 argLen: 2, 20585 generic: true, 20586 }, 20587 { 20588 name: "Greater64F", 20589 argLen: 2, 20590 generic: true, 20591 }, 20592 { 20593 name: "Geq8", 20594 argLen: 2, 20595 generic: true, 20596 }, 20597 { 20598 name: "Geq8U", 20599 argLen: 2, 20600 generic: true, 20601 }, 20602 { 20603 name: "Geq16", 20604 argLen: 2, 20605 generic: true, 20606 }, 20607 { 20608 name: "Geq16U", 20609 argLen: 2, 20610 generic: true, 20611 }, 20612 { 20613 name: "Geq32", 20614 argLen: 2, 20615 generic: true, 20616 }, 20617 { 20618 name: "Geq32U", 20619 argLen: 2, 20620 generic: true, 20621 }, 20622 { 20623 name: "Geq64", 20624 argLen: 2, 20625 generic: true, 20626 }, 20627 { 20628 name: "Geq64U", 20629 argLen: 2, 20630 generic: true, 20631 }, 20632 { 20633 name: "Geq32F", 20634 argLen: 2, 20635 generic: true, 20636 }, 20637 { 20638 name: "Geq64F", 20639 argLen: 2, 20640 generic: true, 20641 }, 20642 { 20643 name: "AndB", 20644 argLen: 2, 20645 generic: true, 20646 }, 20647 { 20648 name: "OrB", 20649 argLen: 2, 20650 generic: true, 20651 }, 20652 { 20653 name: "EqB", 20654 argLen: 2, 20655 generic: true, 20656 }, 20657 { 20658 name: "NeqB", 20659 argLen: 2, 20660 generic: true, 20661 }, 20662 { 20663 name: "Not", 20664 argLen: 1, 20665 generic: true, 20666 }, 20667 { 20668 name: "Neg8", 20669 argLen: 1, 20670 generic: true, 20671 }, 20672 { 20673 name: "Neg16", 20674 argLen: 1, 20675 generic: true, 20676 }, 20677 { 20678 name: "Neg32", 20679 argLen: 1, 20680 generic: true, 20681 }, 20682 { 20683 name: "Neg64", 20684 argLen: 1, 20685 generic: true, 20686 }, 20687 { 20688 name: "Neg32F", 20689 argLen: 1, 20690 generic: true, 20691 }, 20692 { 20693 name: "Neg64F", 20694 argLen: 1, 20695 generic: true, 20696 }, 20697 { 20698 name: "Com8", 20699 argLen: 1, 20700 generic: true, 20701 }, 20702 { 20703 name: "Com16", 20704 argLen: 1, 20705 generic: true, 20706 }, 20707 { 20708 name: "Com32", 20709 argLen: 1, 20710 generic: true, 20711 }, 20712 { 20713 name: "Com64", 20714 argLen: 1, 20715 generic: true, 20716 }, 20717 { 20718 name: "Ctz32", 20719 argLen: 1, 20720 generic: true, 20721 }, 20722 { 20723 name: "Ctz64", 20724 argLen: 1, 20725 generic: true, 20726 }, 20727 { 20728 name: "Bswap32", 20729 argLen: 1, 20730 generic: true, 20731 }, 20732 { 20733 name: "Bswap64", 20734 argLen: 1, 20735 generic: true, 20736 }, 20737 { 20738 name: "Sqrt", 20739 argLen: 1, 20740 generic: true, 20741 }, 20742 { 20743 name: "Phi", 20744 argLen: -1, 20745 generic: true, 20746 }, 20747 { 20748 name: "Copy", 20749 argLen: 1, 20750 generic: true, 20751 }, 20752 { 20753 name: "Convert", 20754 argLen: 2, 20755 generic: true, 20756 }, 20757 { 20758 name: "ConstBool", 20759 auxType: auxBool, 20760 argLen: 0, 20761 generic: true, 20762 }, 20763 { 20764 name: "ConstString", 20765 auxType: auxString, 20766 argLen: 0, 20767 generic: true, 20768 }, 20769 { 20770 name: "ConstNil", 20771 argLen: 0, 20772 generic: true, 20773 }, 20774 { 20775 name: "Const8", 20776 auxType: auxInt8, 20777 argLen: 0, 20778 generic: true, 20779 }, 20780 { 20781 name: "Const16", 20782 auxType: auxInt16, 20783 argLen: 0, 20784 generic: true, 20785 }, 20786 { 20787 name: "Const32", 20788 auxType: auxInt32, 20789 argLen: 0, 20790 generic: true, 20791 }, 20792 { 20793 name: "Const64", 20794 auxType: auxInt64, 20795 argLen: 0, 20796 generic: true, 20797 }, 20798 { 20799 name: "Const32F", 20800 auxType: auxFloat32, 20801 argLen: 0, 20802 generic: true, 20803 }, 20804 { 20805 name: "Const64F", 20806 auxType: auxFloat64, 20807 argLen: 0, 20808 generic: true, 20809 }, 20810 { 20811 name: "ConstInterface", 20812 argLen: 0, 20813 generic: true, 20814 }, 20815 { 20816 name: "ConstSlice", 20817 argLen: 0, 20818 generic: true, 20819 }, 20820 { 20821 name: "InitMem", 20822 argLen: 0, 20823 generic: true, 20824 }, 20825 { 20826 name: "Arg", 20827 auxType: auxSymOff, 20828 argLen: 0, 20829 generic: true, 20830 }, 20831 { 20832 name: "Addr", 20833 auxType: auxSym, 20834 argLen: 1, 20835 generic: true, 20836 }, 20837 { 20838 name: "SP", 20839 argLen: 0, 20840 generic: true, 20841 }, 20842 { 20843 name: "SB", 20844 argLen: 0, 20845 generic: true, 20846 }, 20847 { 20848 name: "Func", 20849 auxType: auxSym, 20850 argLen: 0, 20851 generic: true, 20852 }, 20853 { 20854 name: "Load", 20855 argLen: 2, 20856 generic: true, 20857 }, 20858 { 20859 name: "Store", 20860 auxType: auxInt64, 20861 argLen: 3, 20862 generic: true, 20863 }, 20864 { 20865 name: "Move", 20866 auxType: auxSizeAndAlign, 20867 argLen: 3, 20868 generic: true, 20869 }, 20870 { 20871 name: "Zero", 20872 auxType: auxSizeAndAlign, 20873 argLen: 2, 20874 generic: true, 20875 }, 20876 { 20877 name: "StoreWB", 20878 auxType: auxInt64, 20879 argLen: 3, 20880 generic: true, 20881 }, 20882 { 20883 name: "MoveWB", 20884 auxType: auxSymSizeAndAlign, 20885 argLen: 3, 20886 generic: true, 20887 }, 20888 { 20889 name: "MoveWBVolatile", 20890 auxType: auxSymSizeAndAlign, 20891 argLen: 3, 20892 generic: true, 20893 }, 20894 { 20895 name: "ZeroWB", 20896 auxType: auxSymSizeAndAlign, 20897 argLen: 2, 20898 generic: true, 20899 }, 20900 { 20901 name: "ClosureCall", 20902 auxType: auxInt64, 20903 argLen: 3, 20904 call: true, 20905 generic: true, 20906 }, 20907 { 20908 name: "StaticCall", 20909 auxType: auxSymOff, 20910 argLen: 1, 20911 call: true, 20912 generic: true, 20913 }, 20914 { 20915 name: "DeferCall", 20916 auxType: auxInt64, 20917 argLen: 1, 20918 call: true, 20919 generic: true, 20920 }, 20921 { 20922 name: "GoCall", 20923 auxType: auxInt64, 20924 argLen: 1, 20925 call: true, 20926 generic: true, 20927 }, 20928 { 20929 name: "InterCall", 20930 auxType: auxInt64, 20931 argLen: 2, 20932 call: true, 20933 generic: true, 20934 }, 20935 { 20936 name: "SignExt8to16", 20937 argLen: 1, 20938 generic: true, 20939 }, 20940 { 20941 name: "SignExt8to32", 20942 argLen: 1, 20943 generic: true, 20944 }, 20945 { 20946 name: "SignExt8to64", 20947 argLen: 1, 20948 generic: true, 20949 }, 20950 { 20951 name: "SignExt16to32", 20952 argLen: 1, 20953 generic: true, 20954 }, 20955 { 20956 name: "SignExt16to64", 20957 argLen: 1, 20958 generic: true, 20959 }, 20960 { 20961 name: "SignExt32to64", 20962 argLen: 1, 20963 generic: true, 20964 }, 20965 { 20966 name: "ZeroExt8to16", 20967 argLen: 1, 20968 generic: true, 20969 }, 20970 { 20971 name: "ZeroExt8to32", 20972 argLen: 1, 20973 generic: true, 20974 }, 20975 { 20976 name: "ZeroExt8to64", 20977 argLen: 1, 20978 generic: true, 20979 }, 20980 { 20981 name: "ZeroExt16to32", 20982 argLen: 1, 20983 generic: true, 20984 }, 20985 { 20986 name: "ZeroExt16to64", 20987 argLen: 1, 20988 generic: true, 20989 }, 20990 { 20991 name: "ZeroExt32to64", 20992 argLen: 1, 20993 generic: true, 20994 }, 20995 { 20996 name: "Trunc16to8", 20997 argLen: 1, 20998 generic: true, 20999 }, 21000 { 21001 name: "Trunc32to8", 21002 argLen: 1, 21003 generic: true, 21004 }, 21005 { 21006 name: "Trunc32to16", 21007 argLen: 1, 21008 generic: true, 21009 }, 21010 { 21011 name: "Trunc64to8", 21012 argLen: 1, 21013 generic: true, 21014 }, 21015 { 21016 name: "Trunc64to16", 21017 argLen: 1, 21018 generic: true, 21019 }, 21020 { 21021 name: "Trunc64to32", 21022 argLen: 1, 21023 generic: true, 21024 }, 21025 { 21026 name: "Cvt32to32F", 21027 argLen: 1, 21028 generic: true, 21029 }, 21030 { 21031 name: "Cvt32to64F", 21032 argLen: 1, 21033 generic: true, 21034 }, 21035 { 21036 name: "Cvt64to32F", 21037 argLen: 1, 21038 generic: true, 21039 }, 21040 { 21041 name: "Cvt64to64F", 21042 argLen: 1, 21043 generic: true, 21044 }, 21045 { 21046 name: "Cvt32Fto32", 21047 argLen: 1, 21048 generic: true, 21049 }, 21050 { 21051 name: "Cvt32Fto64", 21052 argLen: 1, 21053 generic: true, 21054 }, 21055 { 21056 name: "Cvt64Fto32", 21057 argLen: 1, 21058 generic: true, 21059 }, 21060 { 21061 name: "Cvt64Fto64", 21062 argLen: 1, 21063 generic: true, 21064 }, 21065 { 21066 name: "Cvt32Fto64F", 21067 argLen: 1, 21068 generic: true, 21069 }, 21070 { 21071 name: "Cvt64Fto32F", 21072 argLen: 1, 21073 generic: true, 21074 }, 21075 { 21076 name: "IsNonNil", 21077 argLen: 1, 21078 generic: true, 21079 }, 21080 { 21081 name: "IsInBounds", 21082 argLen: 2, 21083 generic: true, 21084 }, 21085 { 21086 name: "IsSliceInBounds", 21087 argLen: 2, 21088 generic: true, 21089 }, 21090 { 21091 name: "NilCheck", 21092 argLen: 2, 21093 generic: true, 21094 }, 21095 { 21096 name: "GetG", 21097 argLen: 1, 21098 generic: true, 21099 }, 21100 { 21101 name: "GetClosurePtr", 21102 argLen: 0, 21103 generic: true, 21104 }, 21105 { 21106 name: "PtrIndex", 21107 argLen: 2, 21108 generic: true, 21109 }, 21110 { 21111 name: "OffPtr", 21112 auxType: auxInt64, 21113 argLen: 1, 21114 generic: true, 21115 }, 21116 { 21117 name: "SliceMake", 21118 argLen: 3, 21119 generic: true, 21120 }, 21121 { 21122 name: "SlicePtr", 21123 argLen: 1, 21124 generic: true, 21125 }, 21126 { 21127 name: "SliceLen", 21128 argLen: 1, 21129 generic: true, 21130 }, 21131 { 21132 name: "SliceCap", 21133 argLen: 1, 21134 generic: true, 21135 }, 21136 { 21137 name: "ComplexMake", 21138 argLen: 2, 21139 generic: true, 21140 }, 21141 { 21142 name: "ComplexReal", 21143 argLen: 1, 21144 generic: true, 21145 }, 21146 { 21147 name: "ComplexImag", 21148 argLen: 1, 21149 generic: true, 21150 }, 21151 { 21152 name: "StringMake", 21153 argLen: 2, 21154 generic: true, 21155 }, 21156 { 21157 name: "StringPtr", 21158 argLen: 1, 21159 generic: true, 21160 }, 21161 { 21162 name: "StringLen", 21163 argLen: 1, 21164 generic: true, 21165 }, 21166 { 21167 name: "IMake", 21168 argLen: 2, 21169 generic: true, 21170 }, 21171 { 21172 name: "ITab", 21173 argLen: 1, 21174 generic: true, 21175 }, 21176 { 21177 name: "IData", 21178 argLen: 1, 21179 generic: true, 21180 }, 21181 { 21182 name: "StructMake0", 21183 argLen: 0, 21184 generic: true, 21185 }, 21186 { 21187 name: "StructMake1", 21188 argLen: 1, 21189 generic: true, 21190 }, 21191 { 21192 name: "StructMake2", 21193 argLen: 2, 21194 generic: true, 21195 }, 21196 { 21197 name: "StructMake3", 21198 argLen: 3, 21199 generic: true, 21200 }, 21201 { 21202 name: "StructMake4", 21203 argLen: 4, 21204 generic: true, 21205 }, 21206 { 21207 name: "StructSelect", 21208 auxType: auxInt64, 21209 argLen: 1, 21210 generic: true, 21211 }, 21212 { 21213 name: "ArrayMake0", 21214 argLen: 0, 21215 generic: true, 21216 }, 21217 { 21218 name: "ArrayMake1", 21219 argLen: 1, 21220 generic: true, 21221 }, 21222 { 21223 name: "ArraySelect", 21224 auxType: auxInt64, 21225 argLen: 1, 21226 generic: true, 21227 }, 21228 { 21229 name: "StoreReg", 21230 argLen: 1, 21231 generic: true, 21232 }, 21233 { 21234 name: "LoadReg", 21235 argLen: 1, 21236 generic: true, 21237 }, 21238 { 21239 name: "FwdRef", 21240 auxType: auxSym, 21241 argLen: 0, 21242 generic: true, 21243 }, 21244 { 21245 name: "Unknown", 21246 argLen: 0, 21247 generic: true, 21248 }, 21249 { 21250 name: "VarDef", 21251 auxType: auxSym, 21252 argLen: 1, 21253 generic: true, 21254 }, 21255 { 21256 name: "VarKill", 21257 auxType: auxSym, 21258 argLen: 1, 21259 generic: true, 21260 }, 21261 { 21262 name: "VarLive", 21263 auxType: auxSym, 21264 argLen: 1, 21265 generic: true, 21266 }, 21267 { 21268 name: "KeepAlive", 21269 argLen: 2, 21270 generic: true, 21271 }, 21272 { 21273 name: "Int64Make", 21274 argLen: 2, 21275 generic: true, 21276 }, 21277 { 21278 name: "Int64Hi", 21279 argLen: 1, 21280 generic: true, 21281 }, 21282 { 21283 name: "Int64Lo", 21284 argLen: 1, 21285 generic: true, 21286 }, 21287 { 21288 name: "Add32carry", 21289 argLen: 2, 21290 commutative: true, 21291 generic: true, 21292 }, 21293 { 21294 name: "Add32withcarry", 21295 argLen: 3, 21296 commutative: true, 21297 generic: true, 21298 }, 21299 { 21300 name: "Sub32carry", 21301 argLen: 2, 21302 generic: true, 21303 }, 21304 { 21305 name: "Sub32withcarry", 21306 argLen: 3, 21307 generic: true, 21308 }, 21309 { 21310 name: "Signmask", 21311 argLen: 1, 21312 generic: true, 21313 }, 21314 { 21315 name: "Zeromask", 21316 argLen: 1, 21317 generic: true, 21318 }, 21319 { 21320 name: "Slicemask", 21321 argLen: 1, 21322 generic: true, 21323 }, 21324 { 21325 name: "Cvt32Uto32F", 21326 argLen: 1, 21327 generic: true, 21328 }, 21329 { 21330 name: "Cvt32Uto64F", 21331 argLen: 1, 21332 generic: true, 21333 }, 21334 { 21335 name: "Cvt32Fto32U", 21336 argLen: 1, 21337 generic: true, 21338 }, 21339 { 21340 name: "Cvt64Fto32U", 21341 argLen: 1, 21342 generic: true, 21343 }, 21344 { 21345 name: "Cvt64Uto32F", 21346 argLen: 1, 21347 generic: true, 21348 }, 21349 { 21350 name: "Cvt64Uto64F", 21351 argLen: 1, 21352 generic: true, 21353 }, 21354 { 21355 name: "Cvt32Fto64U", 21356 argLen: 1, 21357 generic: true, 21358 }, 21359 { 21360 name: "Cvt64Fto64U", 21361 argLen: 1, 21362 generic: true, 21363 }, 21364 { 21365 name: "Select0", 21366 argLen: 1, 21367 generic: true, 21368 }, 21369 { 21370 name: "Select1", 21371 argLen: 1, 21372 generic: true, 21373 }, 21374 { 21375 name: "AtomicLoad32", 21376 argLen: 2, 21377 generic: true, 21378 }, 21379 { 21380 name: "AtomicLoad64", 21381 argLen: 2, 21382 generic: true, 21383 }, 21384 { 21385 name: "AtomicLoadPtr", 21386 argLen: 2, 21387 generic: true, 21388 }, 21389 { 21390 name: "AtomicStore32", 21391 argLen: 3, 21392 generic: true, 21393 }, 21394 { 21395 name: "AtomicStore64", 21396 argLen: 3, 21397 generic: true, 21398 }, 21399 { 21400 name: "AtomicStorePtrNoWB", 21401 argLen: 3, 21402 generic: true, 21403 }, 21404 { 21405 name: "AtomicExchange32", 21406 argLen: 3, 21407 generic: true, 21408 }, 21409 { 21410 name: "AtomicExchange64", 21411 argLen: 3, 21412 generic: true, 21413 }, 21414 { 21415 name: "AtomicAdd32", 21416 argLen: 3, 21417 generic: true, 21418 }, 21419 { 21420 name: "AtomicAdd64", 21421 argLen: 3, 21422 generic: true, 21423 }, 21424 { 21425 name: "AtomicCompareAndSwap32", 21426 argLen: 4, 21427 generic: true, 21428 }, 21429 { 21430 name: "AtomicCompareAndSwap64", 21431 argLen: 4, 21432 generic: true, 21433 }, 21434 { 21435 name: "AtomicAnd8", 21436 argLen: 3, 21437 generic: true, 21438 }, 21439 { 21440 name: "AtomicOr8", 21441 argLen: 3, 21442 generic: true, 21443 }, 21444 } 21445 21446 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 21447 func (o Op) String() string { return opcodeTable[o].name } 21448 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 21449 21450 var registers386 = [...]Register{ 21451 {0, x86.REG_AX, "AX"}, 21452 {1, x86.REG_CX, "CX"}, 21453 {2, x86.REG_DX, "DX"}, 21454 {3, x86.REG_BX, "BX"}, 21455 {4, x86.REGSP, "SP"}, 21456 {5, x86.REG_BP, "BP"}, 21457 {6, x86.REG_SI, "SI"}, 21458 {7, x86.REG_DI, "DI"}, 21459 {8, x86.REG_X0, "X0"}, 21460 {9, x86.REG_X1, "X1"}, 21461 {10, x86.REG_X2, "X2"}, 21462 {11, x86.REG_X3, "X3"}, 21463 {12, x86.REG_X4, "X4"}, 21464 {13, x86.REG_X5, "X5"}, 21465 {14, x86.REG_X6, "X6"}, 21466 {15, x86.REG_X7, "X7"}, 21467 {16, 0, "SB"}, 21468 } 21469 var gpRegMask386 = regMask(239) 21470 var fpRegMask386 = regMask(65280) 21471 var specialRegMask386 = regMask(0) 21472 var framepointerReg386 = int8(5) 21473 var linkReg386 = int8(-1) 21474 var registersAMD64 = [...]Register{ 21475 {0, x86.REG_AX, "AX"}, 21476 {1, x86.REG_CX, "CX"}, 21477 {2, x86.REG_DX, "DX"}, 21478 {3, x86.REG_BX, "BX"}, 21479 {4, x86.REGSP, "SP"}, 21480 {5, x86.REG_BP, "BP"}, 21481 {6, x86.REG_SI, "SI"}, 21482 {7, x86.REG_DI, "DI"}, 21483 {8, x86.REG_R8, "R8"}, 21484 {9, x86.REG_R9, "R9"}, 21485 {10, x86.REG_R10, "R10"}, 21486 {11, x86.REG_R11, "R11"}, 21487 {12, x86.REG_R12, "R12"}, 21488 {13, x86.REG_R13, "R13"}, 21489 {14, x86.REG_R14, "R14"}, 21490 {15, x86.REG_R15, "R15"}, 21491 {16, x86.REG_X0, "X0"}, 21492 {17, x86.REG_X1, "X1"}, 21493 {18, x86.REG_X2, "X2"}, 21494 {19, x86.REG_X3, "X3"}, 21495 {20, x86.REG_X4, "X4"}, 21496 {21, x86.REG_X5, "X5"}, 21497 {22, x86.REG_X6, "X6"}, 21498 {23, x86.REG_X7, "X7"}, 21499 {24, x86.REG_X8, "X8"}, 21500 {25, x86.REG_X9, "X9"}, 21501 {26, x86.REG_X10, "X10"}, 21502 {27, x86.REG_X11, "X11"}, 21503 {28, x86.REG_X12, "X12"}, 21504 {29, x86.REG_X13, "X13"}, 21505 {30, x86.REG_X14, "X14"}, 21506 {31, x86.REG_X15, "X15"}, 21507 {32, 0, "SB"}, 21508 } 21509 var gpRegMaskAMD64 = regMask(65519) 21510 var fpRegMaskAMD64 = regMask(4294901760) 21511 var specialRegMaskAMD64 = regMask(0) 21512 var framepointerRegAMD64 = int8(5) 21513 var linkRegAMD64 = int8(-1) 21514 var registersARM = [...]Register{ 21515 {0, arm.REG_R0, "R0"}, 21516 {1, arm.REG_R1, "R1"}, 21517 {2, arm.REG_R2, "R2"}, 21518 {3, arm.REG_R3, "R3"}, 21519 {4, arm.REG_R4, "R4"}, 21520 {5, arm.REG_R5, "R5"}, 21521 {6, arm.REG_R6, "R6"}, 21522 {7, arm.REG_R7, "R7"}, 21523 {8, arm.REG_R8, "R8"}, 21524 {9, arm.REG_R9, "R9"}, 21525 {10, arm.REGG, "g"}, 21526 {11, arm.REG_R11, "R11"}, 21527 {12, arm.REG_R12, "R12"}, 21528 {13, arm.REGSP, "SP"}, 21529 {14, arm.REG_R14, "R14"}, 21530 {15, arm.REG_R15, "R15"}, 21531 {16, arm.REG_F0, "F0"}, 21532 {17, arm.REG_F1, "F1"}, 21533 {18, arm.REG_F2, "F2"}, 21534 {19, arm.REG_F3, "F3"}, 21535 {20, arm.REG_F4, "F4"}, 21536 {21, arm.REG_F5, "F5"}, 21537 {22, arm.REG_F6, "F6"}, 21538 {23, arm.REG_F7, "F7"}, 21539 {24, arm.REG_F8, "F8"}, 21540 {25, arm.REG_F9, "F9"}, 21541 {26, arm.REG_F10, "F10"}, 21542 {27, arm.REG_F11, "F11"}, 21543 {28, arm.REG_F12, "F12"}, 21544 {29, arm.REG_F13, "F13"}, 21545 {30, arm.REG_F14, "F14"}, 21546 {31, arm.REG_F15, "F15"}, 21547 {32, 0, "SB"}, 21548 } 21549 var gpRegMaskARM = regMask(21503) 21550 var fpRegMaskARM = regMask(4294901760) 21551 var specialRegMaskARM = regMask(0) 21552 var framepointerRegARM = int8(-1) 21553 var linkRegARM = int8(14) 21554 var registersARM64 = [...]Register{ 21555 {0, arm64.REG_R0, "R0"}, 21556 {1, arm64.REG_R1, "R1"}, 21557 {2, arm64.REG_R2, "R2"}, 21558 {3, arm64.REG_R3, "R3"}, 21559 {4, arm64.REG_R4, "R4"}, 21560 {5, arm64.REG_R5, "R5"}, 21561 {6, arm64.REG_R6, "R6"}, 21562 {7, arm64.REG_R7, "R7"}, 21563 {8, arm64.REG_R8, "R8"}, 21564 {9, arm64.REG_R9, "R9"}, 21565 {10, arm64.REG_R10, "R10"}, 21566 {11, arm64.REG_R11, "R11"}, 21567 {12, arm64.REG_R12, "R12"}, 21568 {13, arm64.REG_R13, "R13"}, 21569 {14, arm64.REG_R14, "R14"}, 21570 {15, arm64.REG_R15, "R15"}, 21571 {16, arm64.REG_R16, "R16"}, 21572 {17, arm64.REG_R17, "R17"}, 21573 {18, arm64.REG_R18, "R18"}, 21574 {19, arm64.REG_R19, "R19"}, 21575 {20, arm64.REG_R20, "R20"}, 21576 {21, arm64.REG_R21, "R21"}, 21577 {22, arm64.REG_R22, "R22"}, 21578 {23, arm64.REG_R23, "R23"}, 21579 {24, arm64.REG_R24, "R24"}, 21580 {25, arm64.REG_R25, "R25"}, 21581 {26, arm64.REG_R26, "R26"}, 21582 {27, arm64.REGG, "g"}, 21583 {28, arm64.REG_R29, "R29"}, 21584 {29, arm64.REG_R30, "R30"}, 21585 {30, arm64.REGSP, "SP"}, 21586 {31, arm64.REG_F0, "F0"}, 21587 {32, arm64.REG_F1, "F1"}, 21588 {33, arm64.REG_F2, "F2"}, 21589 {34, arm64.REG_F3, "F3"}, 21590 {35, arm64.REG_F4, "F4"}, 21591 {36, arm64.REG_F5, "F5"}, 21592 {37, arm64.REG_F6, "F6"}, 21593 {38, arm64.REG_F7, "F7"}, 21594 {39, arm64.REG_F8, "F8"}, 21595 {40, arm64.REG_F9, "F9"}, 21596 {41, arm64.REG_F10, "F10"}, 21597 {42, arm64.REG_F11, "F11"}, 21598 {43, arm64.REG_F12, "F12"}, 21599 {44, arm64.REG_F13, "F13"}, 21600 {45, arm64.REG_F14, "F14"}, 21601 {46, arm64.REG_F15, "F15"}, 21602 {47, arm64.REG_F16, "F16"}, 21603 {48, arm64.REG_F17, "F17"}, 21604 {49, arm64.REG_F18, "F18"}, 21605 {50, arm64.REG_F19, "F19"}, 21606 {51, arm64.REG_F20, "F20"}, 21607 {52, arm64.REG_F21, "F21"}, 21608 {53, arm64.REG_F22, "F22"}, 21609 {54, arm64.REG_F23, "F23"}, 21610 {55, arm64.REG_F24, "F24"}, 21611 {56, arm64.REG_F25, "F25"}, 21612 {57, arm64.REG_F26, "F26"}, 21613 {58, arm64.REG_F27, "F27"}, 21614 {59, arm64.REG_F28, "F28"}, 21615 {60, arm64.REG_F29, "F29"}, 21616 {61, arm64.REG_F30, "F30"}, 21617 {62, arm64.REG_F31, "F31"}, 21618 {63, 0, "SB"}, 21619 } 21620 var gpRegMaskARM64 = regMask(670826495) 21621 var fpRegMaskARM64 = regMask(9223372034707292160) 21622 var specialRegMaskARM64 = regMask(0) 21623 var framepointerRegARM64 = int8(-1) 21624 var linkRegARM64 = int8(29) 21625 var registersMIPS = [...]Register{ 21626 {0, mips.REG_R0, "R0"}, 21627 {1, mips.REG_R1, "R1"}, 21628 {2, mips.REG_R2, "R2"}, 21629 {3, mips.REG_R3, "R3"}, 21630 {4, mips.REG_R4, "R4"}, 21631 {5, mips.REG_R5, "R5"}, 21632 {6, mips.REG_R6, "R6"}, 21633 {7, mips.REG_R7, "R7"}, 21634 {8, mips.REG_R8, "R8"}, 21635 {9, mips.REG_R9, "R9"}, 21636 {10, mips.REG_R10, "R10"}, 21637 {11, mips.REG_R11, "R11"}, 21638 {12, mips.REG_R12, "R12"}, 21639 {13, mips.REG_R13, "R13"}, 21640 {14, mips.REG_R14, "R14"}, 21641 {15, mips.REG_R15, "R15"}, 21642 {16, mips.REG_R16, "R16"}, 21643 {17, mips.REG_R17, "R17"}, 21644 {18, mips.REG_R18, "R18"}, 21645 {19, mips.REG_R19, "R19"}, 21646 {20, mips.REG_R20, "R20"}, 21647 {21, mips.REG_R21, "R21"}, 21648 {22, mips.REG_R22, "R22"}, 21649 {23, mips.REG_R24, "R24"}, 21650 {24, mips.REG_R25, "R25"}, 21651 {25, mips.REG_R28, "R28"}, 21652 {26, mips.REGSP, "SP"}, 21653 {27, mips.REGG, "g"}, 21654 {28, mips.REG_R31, "R31"}, 21655 {29, mips.REG_F0, "F0"}, 21656 {30, mips.REG_F2, "F2"}, 21657 {31, mips.REG_F4, "F4"}, 21658 {32, mips.REG_F6, "F6"}, 21659 {33, mips.REG_F8, "F8"}, 21660 {34, mips.REG_F10, "F10"}, 21661 {35, mips.REG_F12, "F12"}, 21662 {36, mips.REG_F14, "F14"}, 21663 {37, mips.REG_F16, "F16"}, 21664 {38, mips.REG_F18, "F18"}, 21665 {39, mips.REG_F20, "F20"}, 21666 {40, mips.REG_F22, "F22"}, 21667 {41, mips.REG_F24, "F24"}, 21668 {42, mips.REG_F26, "F26"}, 21669 {43, mips.REG_F28, "F28"}, 21670 {44, mips.REG_F30, "F30"}, 21671 {45, mips.REG_HI, "HI"}, 21672 {46, mips.REG_LO, "LO"}, 21673 {47, 0, "SB"}, 21674 } 21675 var gpRegMaskMIPS = regMask(335544318) 21676 var fpRegMaskMIPS = regMask(35183835217920) 21677 var specialRegMaskMIPS = regMask(105553116266496) 21678 var framepointerRegMIPS = int8(-1) 21679 var linkRegMIPS = int8(28) 21680 var registersMIPS64 = [...]Register{ 21681 {0, mips.REG_R0, "R0"}, 21682 {1, mips.REG_R1, "R1"}, 21683 {2, mips.REG_R2, "R2"}, 21684 {3, mips.REG_R3, "R3"}, 21685 {4, mips.REG_R4, "R4"}, 21686 {5, mips.REG_R5, "R5"}, 21687 {6, mips.REG_R6, "R6"}, 21688 {7, mips.REG_R7, "R7"}, 21689 {8, mips.REG_R8, "R8"}, 21690 {9, mips.REG_R9, "R9"}, 21691 {10, mips.REG_R10, "R10"}, 21692 {11, mips.REG_R11, "R11"}, 21693 {12, mips.REG_R12, "R12"}, 21694 {13, mips.REG_R13, "R13"}, 21695 {14, mips.REG_R14, "R14"}, 21696 {15, mips.REG_R15, "R15"}, 21697 {16, mips.REG_R16, "R16"}, 21698 {17, mips.REG_R17, "R17"}, 21699 {18, mips.REG_R18, "R18"}, 21700 {19, mips.REG_R19, "R19"}, 21701 {20, mips.REG_R20, "R20"}, 21702 {21, mips.REG_R21, "R21"}, 21703 {22, mips.REG_R22, "R22"}, 21704 {23, mips.REG_R24, "R24"}, 21705 {24, mips.REG_R25, "R25"}, 21706 {25, mips.REGSP, "SP"}, 21707 {26, mips.REGG, "g"}, 21708 {27, mips.REG_R31, "R31"}, 21709 {28, mips.REG_F0, "F0"}, 21710 {29, mips.REG_F1, "F1"}, 21711 {30, mips.REG_F2, "F2"}, 21712 {31, mips.REG_F3, "F3"}, 21713 {32, mips.REG_F4, "F4"}, 21714 {33, mips.REG_F5, "F5"}, 21715 {34, mips.REG_F6, "F6"}, 21716 {35, mips.REG_F7, "F7"}, 21717 {36, mips.REG_F8, "F8"}, 21718 {37, mips.REG_F9, "F9"}, 21719 {38, mips.REG_F10, "F10"}, 21720 {39, mips.REG_F11, "F11"}, 21721 {40, mips.REG_F12, "F12"}, 21722 {41, mips.REG_F13, "F13"}, 21723 {42, mips.REG_F14, "F14"}, 21724 {43, mips.REG_F15, "F15"}, 21725 {44, mips.REG_F16, "F16"}, 21726 {45, mips.REG_F17, "F17"}, 21727 {46, mips.REG_F18, "F18"}, 21728 {47, mips.REG_F19, "F19"}, 21729 {48, mips.REG_F20, "F20"}, 21730 {49, mips.REG_F21, "F21"}, 21731 {50, mips.REG_F22, "F22"}, 21732 {51, mips.REG_F23, "F23"}, 21733 {52, mips.REG_F24, "F24"}, 21734 {53, mips.REG_F25, "F25"}, 21735 {54, mips.REG_F26, "F26"}, 21736 {55, mips.REG_F27, "F27"}, 21737 {56, mips.REG_F28, "F28"}, 21738 {57, mips.REG_F29, "F29"}, 21739 {58, mips.REG_F30, "F30"}, 21740 {59, mips.REG_F31, "F31"}, 21741 {60, mips.REG_HI, "HI"}, 21742 {61, mips.REG_LO, "LO"}, 21743 {62, 0, "SB"}, 21744 } 21745 var gpRegMaskMIPS64 = regMask(167772158) 21746 var fpRegMaskMIPS64 = regMask(1152921504338411520) 21747 var specialRegMaskMIPS64 = regMask(3458764513820540928) 21748 var framepointerRegMIPS64 = int8(-1) 21749 var linkRegMIPS64 = int8(27) 21750 var registersPPC64 = [...]Register{ 21751 {0, ppc64.REG_R0, "R0"}, 21752 {1, ppc64.REGSP, "SP"}, 21753 {2, 0, "SB"}, 21754 {3, ppc64.REG_R3, "R3"}, 21755 {4, ppc64.REG_R4, "R4"}, 21756 {5, ppc64.REG_R5, "R5"}, 21757 {6, ppc64.REG_R6, "R6"}, 21758 {7, ppc64.REG_R7, "R7"}, 21759 {8, ppc64.REG_R8, "R8"}, 21760 {9, ppc64.REG_R9, "R9"}, 21761 {10, ppc64.REG_R10, "R10"}, 21762 {11, ppc64.REG_R11, "R11"}, 21763 {12, ppc64.REG_R12, "R12"}, 21764 {13, ppc64.REG_R13, "R13"}, 21765 {14, ppc64.REG_R14, "R14"}, 21766 {15, ppc64.REG_R15, "R15"}, 21767 {16, ppc64.REG_R16, "R16"}, 21768 {17, ppc64.REG_R17, "R17"}, 21769 {18, ppc64.REG_R18, "R18"}, 21770 {19, ppc64.REG_R19, "R19"}, 21771 {20, ppc64.REG_R20, "R20"}, 21772 {21, ppc64.REG_R21, "R21"}, 21773 {22, ppc64.REG_R22, "R22"}, 21774 {23, ppc64.REG_R23, "R23"}, 21775 {24, ppc64.REG_R24, "R24"}, 21776 {25, ppc64.REG_R25, "R25"}, 21777 {26, ppc64.REG_R26, "R26"}, 21778 {27, ppc64.REG_R27, "R27"}, 21779 {28, ppc64.REG_R28, "R28"}, 21780 {29, ppc64.REG_R29, "R29"}, 21781 {30, ppc64.REGG, "g"}, 21782 {31, ppc64.REG_R31, "R31"}, 21783 {32, ppc64.REG_F0, "F0"}, 21784 {33, ppc64.REG_F1, "F1"}, 21785 {34, ppc64.REG_F2, "F2"}, 21786 {35, ppc64.REG_F3, "F3"}, 21787 {36, ppc64.REG_F4, "F4"}, 21788 {37, ppc64.REG_F5, "F5"}, 21789 {38, ppc64.REG_F6, "F6"}, 21790 {39, ppc64.REG_F7, "F7"}, 21791 {40, ppc64.REG_F8, "F8"}, 21792 {41, ppc64.REG_F9, "F9"}, 21793 {42, ppc64.REG_F10, "F10"}, 21794 {43, ppc64.REG_F11, "F11"}, 21795 {44, ppc64.REG_F12, "F12"}, 21796 {45, ppc64.REG_F13, "F13"}, 21797 {46, ppc64.REG_F14, "F14"}, 21798 {47, ppc64.REG_F15, "F15"}, 21799 {48, ppc64.REG_F16, "F16"}, 21800 {49, ppc64.REG_F17, "F17"}, 21801 {50, ppc64.REG_F18, "F18"}, 21802 {51, ppc64.REG_F19, "F19"}, 21803 {52, ppc64.REG_F20, "F20"}, 21804 {53, ppc64.REG_F21, "F21"}, 21805 {54, ppc64.REG_F22, "F22"}, 21806 {55, ppc64.REG_F23, "F23"}, 21807 {56, ppc64.REG_F24, "F24"}, 21808 {57, ppc64.REG_F25, "F25"}, 21809 {58, ppc64.REG_F26, "F26"}, 21810 {59, ppc64.REG_F27, "F27"}, 21811 {60, ppc64.REG_F28, "F28"}, 21812 {61, ppc64.REG_F29, "F29"}, 21813 {62, ppc64.REG_F30, "F30"}, 21814 {63, ppc64.REG_F31, "F31"}, 21815 } 21816 var gpRegMaskPPC64 = regMask(1073733624) 21817 var fpRegMaskPPC64 = regMask(576460743713488896) 21818 var specialRegMaskPPC64 = regMask(0) 21819 var framepointerRegPPC64 = int8(1) 21820 var linkRegPPC64 = int8(-1) 21821 var registersS390X = [...]Register{ 21822 {0, s390x.REG_R0, "R0"}, 21823 {1, s390x.REG_R1, "R1"}, 21824 {2, s390x.REG_R2, "R2"}, 21825 {3, s390x.REG_R3, "R3"}, 21826 {4, s390x.REG_R4, "R4"}, 21827 {5, s390x.REG_R5, "R5"}, 21828 {6, s390x.REG_R6, "R6"}, 21829 {7, s390x.REG_R7, "R7"}, 21830 {8, s390x.REG_R8, "R8"}, 21831 {9, s390x.REG_R9, "R9"}, 21832 {10, s390x.REG_R10, "R10"}, 21833 {11, s390x.REG_R11, "R11"}, 21834 {12, s390x.REG_R12, "R12"}, 21835 {13, s390x.REGG, "g"}, 21836 {14, s390x.REG_R14, "R14"}, 21837 {15, s390x.REGSP, "SP"}, 21838 {16, s390x.REG_F0, "F0"}, 21839 {17, s390x.REG_F1, "F1"}, 21840 {18, s390x.REG_F2, "F2"}, 21841 {19, s390x.REG_F3, "F3"}, 21842 {20, s390x.REG_F4, "F4"}, 21843 {21, s390x.REG_F5, "F5"}, 21844 {22, s390x.REG_F6, "F6"}, 21845 {23, s390x.REG_F7, "F7"}, 21846 {24, s390x.REG_F8, "F8"}, 21847 {25, s390x.REG_F9, "F9"}, 21848 {26, s390x.REG_F10, "F10"}, 21849 {27, s390x.REG_F11, "F11"}, 21850 {28, s390x.REG_F12, "F12"}, 21851 {29, s390x.REG_F13, "F13"}, 21852 {30, s390x.REG_F14, "F14"}, 21853 {31, s390x.REG_F15, "F15"}, 21854 {32, 0, "SB"}, 21855 } 21856 var gpRegMaskS390X = regMask(21503) 21857 var fpRegMaskS390X = regMask(4294901760) 21858 var specialRegMaskS390X = regMask(0) 21859 var framepointerRegS390X = int8(-1) 21860 var linkRegS390X = int8(14)