github.com/FenixAra/go@v0.0.0-20170127160404-96ea0918e670/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 /* F0=4128 ... F31=4159 */ 83 REG_F0 84 REG_F1 85 REG_F2 86 REG_F3 87 REG_F4 88 REG_F5 89 REG_F6 90 REG_F7 91 REG_F8 92 REG_F9 93 REG_F10 94 REG_F11 95 REG_F12 96 REG_F13 97 REG_F14 98 REG_F15 99 REG_F16 100 REG_F17 101 REG_F18 102 REG_F19 103 REG_F20 104 REG_F21 105 REG_F22 106 REG_F23 107 REG_F24 108 REG_F25 109 REG_F26 110 REG_F27 111 REG_F28 112 REG_F29 113 REG_F30 114 REG_F31 115 116 /* V0=4160 ... V31=4191 */ 117 REG_V0 118 REG_V1 119 REG_V2 120 REG_V3 121 REG_V4 122 REG_V5 123 REG_V6 124 REG_V7 125 REG_V8 126 REG_V9 127 REG_V10 128 REG_V11 129 REG_V12 130 REG_V13 131 REG_V14 132 REG_V15 133 REG_V16 134 REG_V17 135 REG_V18 136 REG_V19 137 REG_V20 138 REG_V21 139 REG_V22 140 REG_V23 141 REG_V24 142 REG_V25 143 REG_V26 144 REG_V27 145 REG_V28 146 REG_V29 147 REG_V30 148 REG_V31 149 150 /* VS0=4192 ... VS63=4255 */ 151 REG_VS0 152 REG_VS1 153 REG_VS2 154 REG_VS3 155 REG_VS4 156 REG_VS5 157 REG_VS6 158 REG_VS7 159 REG_VS8 160 REG_VS9 161 REG_VS10 162 REG_VS11 163 REG_VS12 164 REG_VS13 165 REG_VS14 166 REG_VS15 167 REG_VS16 168 REG_VS17 169 REG_VS18 170 REG_VS19 171 REG_VS20 172 REG_VS21 173 REG_VS22 174 REG_VS23 175 REG_VS24 176 REG_VS25 177 REG_VS26 178 REG_VS27 179 REG_VS28 180 REG_VS29 181 REG_VS30 182 REG_VS31 183 REG_VS32 184 REG_VS33 185 REG_VS34 186 REG_VS35 187 REG_VS36 188 REG_VS37 189 REG_VS38 190 REG_VS39 191 REG_VS40 192 REG_VS41 193 REG_VS42 194 REG_VS43 195 REG_VS44 196 REG_VS45 197 REG_VS46 198 REG_VS47 199 REG_VS48 200 REG_VS49 201 REG_VS50 202 REG_VS51 203 REG_VS52 204 REG_VS53 205 REG_VS54 206 REG_VS55 207 REG_VS56 208 REG_VS57 209 REG_VS58 210 REG_VS59 211 REG_VS60 212 REG_VS61 213 REG_VS62 214 REG_VS63 215 216 REG_CR0 217 REG_CR1 218 REG_CR2 219 REG_CR3 220 REG_CR4 221 REG_CR5 222 REG_CR6 223 REG_CR7 224 225 REG_MSR 226 REG_FPSCR 227 REG_CR 228 229 REG_SPECIAL = REG_CR0 230 231 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 232 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers 233 234 REG_XER = REG_SPR0 + 1 235 REG_LR = REG_SPR0 + 8 236 REG_CTR = REG_SPR0 + 9 237 238 REGZERO = REG_R0 /* set to zero */ 239 REGSP = REG_R1 240 REGSB = REG_R2 241 REGRET = REG_R3 242 REGARG = -1 /* -1 disables passing the first argument in register */ 243 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ 244 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ 245 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 246 REGCTXT = REG_R11 /* context for closures */ 247 REGTLS = REG_R13 /* C ABI TLS base pointer */ 248 REGMAX = REG_R27 249 REGEXT = REG_R30 /* external registers allocated from here down */ 250 REGG = REG_R30 /* G */ 251 REGTMP = REG_R31 /* used by the linker */ 252 FREGRET = REG_F0 253 FREGMIN = REG_F17 /* first register variable */ 254 FREGMAX = REG_F26 /* last register variable for 9g only */ 255 FREGEXT = REG_F26 /* first external register */ 256 ) 257 258 /* 259 * GENERAL: 260 * 261 * compiler allocates R3 up as temps 262 * compiler allocates register variables R7-R27 263 * compiler allocates external registers R30 down 264 * 265 * compiler allocates register variables F17-F26 266 * compiler allocates external registers F26 down 267 */ 268 const ( 269 BIG = 32768 - 8 270 ) 271 272 const ( 273 /* mark flags */ 274 LABEL = 1 << 0 275 LEAF = 1 << 1 276 FLOAT = 1 << 2 277 BRANCH = 1 << 3 278 LOAD = 1 << 4 279 FCMP = 1 << 5 280 SYNC = 1 << 6 281 LIST = 1 << 7 282 FOLL = 1 << 8 283 NOSCHED = 1 << 9 284 ) 285 286 // Values for use in branch instruction BC 287 // BC B0,BI,label 288 // BO is type of branch + likely bits described below 289 // BI is CR value + branch type 290 // ex: BEQ CR2,label is BC 12,10,label 291 // 12 = BO_BCR 292 // 10 = BI_CR2 + BI_EQ 293 294 const ( 295 BI_CR0 = 0 296 BI_CR1 = 4 297 BI_CR2 = 8 298 BI_CR3 = 12 299 BI_CR4 = 16 300 BI_CR5 = 20 301 BI_CR6 = 24 302 BI_CR7 = 28 303 BI_LT = 0 304 BI_GT = 1 305 BI_EQ = 2 306 BI_OVF = 3 307 ) 308 309 // Values for the BO field. Add the branch type to 310 // the likely bits, if a likely setting is known. 311 // If branch likely or unlikely is not known, don't set it. 312 // e.g. branch on cr+likely = 15 313 314 const ( 315 BO_BCTR = 16 // branch on ctr value 316 BO_BCR = 12 // branch on cr value 317 BO_BCRBCTR = 8 // branch on ctr and cr value 318 BO_NOTBCR = 4 // branch on not cr value 319 BO_UNLIKELY = 2 // value for unlikely 320 BO_LIKELY = 3 // value for likely 321 ) 322 323 // Bit settings from the CR 324 325 const ( 326 C_COND_LT = iota // 0 result is negative 327 C_COND_GT // 1 result is positive 328 C_COND_EQ // 2 result is zero 329 C_COND_SO // 3 summary overflow or FP compare w/ NaN 330 ) 331 332 const ( 333 C_NONE = iota 334 C_REG 335 C_FREG 336 C_VREG 337 C_VSREG 338 C_CREG 339 C_SPR /* special processor register */ 340 C_ZCON 341 C_SCON /* 16 bit signed */ 342 C_UCON /* 32 bit signed, low 16 bits 0 */ 343 C_ADDCON /* -0x8000 <= v < 0 */ 344 C_ANDCON /* 0 < v <= 0xFFFF */ 345 C_LCON /* other 32 */ 346 C_DCON /* other 64 (could subdivide further) */ 347 C_SACON /* $n(REG) where n <= int16 */ 348 C_SECON 349 C_LACON /* $n(REG) where int16 < n <= int32 */ 350 C_LECON 351 C_DACON /* $n(REG) where int32 < n */ 352 C_SBRA 353 C_LBRA 354 C_LBRAPIC 355 C_SAUTO 356 C_LAUTO 357 C_SEXT 358 C_LEXT 359 C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG 360 C_SOREG // register + signed offset 361 C_LOREG 362 C_FPSCR 363 C_MSR 364 C_XER 365 C_LR 366 C_CTR 367 C_ANY 368 C_GOK 369 C_ADDR 370 C_GOTADDR 371 C_TLS_LE 372 C_TLS_IE 373 C_TEXTSIZE 374 375 C_NCLASS /* must be the last */ 376 ) 377 378 const ( 379 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 380 AADDCC 381 AADDV 382 AADDVCC 383 AADDC 384 AADDCCC 385 AADDCV 386 AADDCVCC 387 AADDME 388 AADDMECC 389 AADDMEVCC 390 AADDMEV 391 AADDE 392 AADDECC 393 AADDEVCC 394 AADDEV 395 AADDZE 396 AADDZECC 397 AADDZEVCC 398 AADDZEV 399 AAND 400 AANDCC 401 AANDN 402 AANDNCC 403 ABC 404 ABCL 405 ABEQ 406 ABGE // not LT = G/E/U 407 ABGT 408 ABLE // not GT = L/E/U 409 ABLT 410 ABNE // not EQ = L/G/U 411 ABVC // Unordered-clear 412 ABVS // Unordered-set 413 ACMP 414 ACMPU 415 ACNTLZW 416 ACNTLZWCC 417 ACRAND 418 ACRANDN 419 ACREQV 420 ACRNAND 421 ACRNOR 422 ACROR 423 ACRORN 424 ACRXOR 425 ADIVW 426 ADIVWCC 427 ADIVWVCC 428 ADIVWV 429 ADIVWU 430 ADIVWUCC 431 ADIVWUVCC 432 ADIVWUV 433 AEQV 434 AEQVCC 435 AEXTSB 436 AEXTSBCC 437 AEXTSH 438 AEXTSHCC 439 AFABS 440 AFABSCC 441 AFADD 442 AFADDCC 443 AFADDS 444 AFADDSCC 445 AFCMPO 446 AFCMPU 447 AFCTIW 448 AFCTIWCC 449 AFCTIWZ 450 AFCTIWZCC 451 AFDIV 452 AFDIVCC 453 AFDIVS 454 AFDIVSCC 455 AFMADD 456 AFMADDCC 457 AFMADDS 458 AFMADDSCC 459 AFMOVD 460 AFMOVDCC 461 AFMOVDU 462 AFMOVS 463 AFMOVSU 464 AFMOVSX 465 AFMOVSZ 466 AFMSUB 467 AFMSUBCC 468 AFMSUBS 469 AFMSUBSCC 470 AFMUL 471 AFMULCC 472 AFMULS 473 AFMULSCC 474 AFNABS 475 AFNABSCC 476 AFNEG 477 AFNEGCC 478 AFNMADD 479 AFNMADDCC 480 AFNMADDS 481 AFNMADDSCC 482 AFNMSUB 483 AFNMSUBCC 484 AFNMSUBS 485 AFNMSUBSCC 486 AFRSP 487 AFRSPCC 488 AFSUB 489 AFSUBCC 490 AFSUBS 491 AFSUBSCC 492 AISEL 493 AMOVMW 494 ALBAR 495 ALSW 496 ALWAR 497 ALWSYNC 498 AMOVDBR 499 AMOVWBR 500 AMOVB 501 AMOVBU 502 AMOVBZ 503 AMOVBZU 504 AMOVH 505 AMOVHBR 506 AMOVHU 507 AMOVHZ 508 AMOVHZU 509 AMOVW 510 AMOVWU 511 AMOVFL 512 AMOVCRFS 513 AMTFSB0 514 AMTFSB0CC 515 AMTFSB1 516 AMTFSB1CC 517 AMULHW 518 AMULHWCC 519 AMULHWU 520 AMULHWUCC 521 AMULLW 522 AMULLWCC 523 AMULLWVCC 524 AMULLWV 525 ANAND 526 ANANDCC 527 ANEG 528 ANEGCC 529 ANEGVCC 530 ANEGV 531 ANOR 532 ANORCC 533 AOR 534 AORCC 535 AORN 536 AORNCC 537 AREM 538 AREMCC 539 AREMV 540 AREMVCC 541 AREMU 542 AREMUCC 543 AREMUV 544 AREMUVCC 545 ARFI 546 ARLWMI 547 ARLWMICC 548 ARLWNM 549 ARLWNMCC 550 ASLW 551 ASLWCC 552 ASRW 553 ASRAW 554 ASRAWCC 555 ASRWCC 556 ASTBCCC 557 ASTSW 558 ASTWCCC 559 ASUB 560 ASUBCC 561 ASUBVCC 562 ASUBC 563 ASUBCCC 564 ASUBCV 565 ASUBCVCC 566 ASUBME 567 ASUBMECC 568 ASUBMEVCC 569 ASUBMEV 570 ASUBV 571 ASUBE 572 ASUBECC 573 ASUBEV 574 ASUBEVCC 575 ASUBZE 576 ASUBZECC 577 ASUBZEVCC 578 ASUBZEV 579 ASYNC 580 AXOR 581 AXORCC 582 583 ADCBF 584 ADCBI 585 ADCBST 586 ADCBT 587 ADCBTST 588 ADCBZ 589 AECIWX 590 AECOWX 591 AEIEIO 592 AICBI 593 AISYNC 594 APTESYNC 595 ATLBIE 596 ATLBIEL 597 ATLBSYNC 598 ATW 599 600 ASYSCALL 601 AWORD 602 603 ARFCI 604 605 /* optional on 32-bit */ 606 AFRES 607 AFRESCC 608 AFRIM 609 AFRIMCC 610 AFRIP 611 AFRIPCC 612 AFRIZ 613 AFRIZCC 614 AFRSQRTE 615 AFRSQRTECC 616 AFSEL 617 AFSELCC 618 AFSQRT 619 AFSQRTCC 620 AFSQRTS 621 AFSQRTSCC 622 623 /* 64-bit */ 624 625 ACNTLZD 626 ACNTLZDCC 627 ACMPW /* CMP with L=0 */ 628 ACMPWU 629 ADIVD 630 ADIVDCC 631 ADIVDE 632 ADIVDECC 633 ADIVDEU 634 ADIVDEUCC 635 ADIVDVCC 636 ADIVDV 637 ADIVDU 638 ADIVDUCC 639 ADIVDUVCC 640 ADIVDUV 641 AEXTSW 642 AEXTSWCC 643 /* AFCFIW; AFCFIWCC */ 644 AFCFID 645 AFCFIDCC 646 AFCFIDU 647 AFCFIDUCC 648 AFCTID 649 AFCTIDCC 650 AFCTIDZ 651 AFCTIDZCC 652 ALDAR 653 AMOVD 654 AMOVDU 655 AMOVWZ 656 AMOVWZU 657 AMULHD 658 AMULHDCC 659 AMULHDU 660 AMULHDUCC 661 AMULLD 662 AMULLDCC 663 AMULLDVCC 664 AMULLDV 665 ARFID 666 ARLDMI 667 ARLDMICC 668 ARLDIMI 669 ARLDIMICC 670 ARLDC 671 ARLDCCC 672 ARLDCR 673 ARLDCRCC 674 ARLDICR 675 ARLDICRCC 676 ARLDCL 677 ARLDCLCC 678 ARLDICL 679 ARLDICLCC 680 ASLBIA 681 ASLBIE 682 ASLBMFEE 683 ASLBMFEV 684 ASLBMTE 685 ASLD 686 ASLDCC 687 ASRD 688 ASRAD 689 ASRADCC 690 ASRDCC 691 ASTDCCC 692 ATD 693 694 /* 64-bit pseudo operation */ 695 ADWORD 696 AREMD 697 AREMDCC 698 AREMDV 699 AREMDVCC 700 AREMDU 701 AREMDUCC 702 AREMDUV 703 AREMDUVCC 704 705 /* more 64-bit operations */ 706 AHRFID 707 708 /* Vector */ 709 ALV 710 ALVEBX 711 ALVEHX 712 ALVEWX 713 ALVX 714 ALVXL 715 ALVSL 716 ALVSR 717 ASTV 718 ASTVEBX 719 ASTVEHX 720 ASTVEWX 721 ASTVX 722 ASTVXL 723 AVAND 724 AVANDL 725 AVANDC 726 AVNAND 727 AVOR 728 AVORL 729 AVORC 730 AVNOR 731 AVXOR 732 AVEQV 733 AVADDUM 734 AVADDUBM 735 AVADDUHM 736 AVADDUWM 737 AVADDUDM 738 AVADDUQM 739 AVADDCU 740 AVADDCUQ 741 AVADDCUW 742 AVADDUS 743 AVADDUBS 744 AVADDUHS 745 AVADDUWS 746 AVADDSS 747 AVADDSBS 748 AVADDSHS 749 AVADDSWS 750 AVADDE 751 AVADDEUQM 752 AVADDECUQ 753 AVSUBUM 754 AVSUBUBM 755 AVSUBUHM 756 AVSUBUWM 757 AVSUBUDM 758 AVSUBUQM 759 AVSUBCU 760 AVSUBCUQ 761 AVSUBCUW 762 AVSUBUS 763 AVSUBUBS 764 AVSUBUHS 765 AVSUBUWS 766 AVSUBSS 767 AVSUBSBS 768 AVSUBSHS 769 AVSUBSWS 770 AVSUBE 771 AVSUBEUQM 772 AVSUBECUQ 773 AVR 774 AVRLB 775 AVRLH 776 AVRLW 777 AVRLD 778 AVS 779 AVSLB 780 AVSLH 781 AVSLW 782 AVSL 783 AVSLO 784 AVSRB 785 AVSRH 786 AVSRW 787 AVSR 788 AVSRO 789 AVSLD 790 AVSRD 791 AVSA 792 AVSRAB 793 AVSRAH 794 AVSRAW 795 AVSRAD 796 AVSOI 797 AVSLDOI 798 AVCLZ 799 AVCLZB 800 AVCLZH 801 AVCLZW 802 AVCLZD 803 AVPOPCNT 804 AVPOPCNTB 805 AVPOPCNTH 806 AVPOPCNTW 807 AVPOPCNTD 808 AVCMPEQ 809 AVCMPEQUB 810 AVCMPEQUBCC 811 AVCMPEQUH 812 AVCMPEQUHCC 813 AVCMPEQUW 814 AVCMPEQUWCC 815 AVCMPEQUD 816 AVCMPEQUDCC 817 AVCMPGT 818 AVCMPGTUB 819 AVCMPGTUBCC 820 AVCMPGTUH 821 AVCMPGTUHCC 822 AVCMPGTUW 823 AVCMPGTUWCC 824 AVCMPGTUD 825 AVCMPGTUDCC 826 AVCMPGTSB 827 AVCMPGTSBCC 828 AVCMPGTSH 829 AVCMPGTSHCC 830 AVCMPGTSW 831 AVCMPGTSWCC 832 AVCMPGTSD 833 AVCMPGTSDCC 834 AVPERM 835 AVSEL 836 AVSPLT 837 AVSPLTB 838 AVSPLTH 839 AVSPLTW 840 AVSPLTI 841 AVSPLTISB 842 AVSPLTISH 843 AVSPLTISW 844 AVCIPH 845 AVCIPHER 846 AVCIPHERLAST 847 AVNCIPH 848 AVNCIPHER 849 AVNCIPHERLAST 850 AVSBOX 851 AVSHASIGMA 852 AVSHASIGMAW 853 AVSHASIGMAD 854 855 /* VSX */ 856 ALXV 857 ALXVD2X 858 ALXVDSX 859 ALXVW4X 860 ASTXV 861 ASTXVD2X 862 ASTXVW4X 863 ALXS 864 ALXSDX 865 ASTXS 866 ASTXSDX 867 ALXSI 868 ALXSIWAX 869 ALXSIWZX 870 ASTXSI 871 ASTXSIWX 872 AMFVSR 873 AMFVSRD 874 AMFVSRWZ 875 AMTVSR 876 AMTVSRD 877 AMTVSRWA 878 AMTVSRWZ 879 AXXLAND 880 AXXLANDQ 881 AXXLANDC 882 AXXLEQV 883 AXXLNAND 884 AXXLOR 885 AXXLORC 886 AXXLNOR 887 AXXLORQ 888 AXXLXOR 889 AXXSEL 890 AXXMRG 891 AXXMRGHW 892 AXXMRGLW 893 AXXSPLT 894 AXXSPLTW 895 AXXPERM 896 AXXPERMDI 897 AXXSI 898 AXXSLDWI 899 AXSCV 900 AXSCVDPSP 901 AXSCVSPDP 902 AXSCVDPSPN 903 AXSCVSPDPN 904 AXVCV 905 AXVCVDPSP 906 AXVCVSPDP 907 AXSCVX 908 AXSCVDPSXDS 909 AXSCVDPSXWS 910 AXSCVDPUXDS 911 AXSCVDPUXWS 912 AXSCVXP 913 AXSCVSXDDP 914 AXSCVUXDDP 915 AXSCVSXDSP 916 AXSCVUXDSP 917 AXVCVX 918 AXVCVDPSXDS 919 AXVCVDPSXWS 920 AXVCVDPUXDS 921 AXVCVDPUXWS 922 AXVCVSPSXDS 923 AXVCVSPSXWS 924 AXVCVSPUXDS 925 AXVCVSPUXWS 926 AXVCVXP 927 AXVCVSXDDP 928 AXVCVSXWDP 929 AXVCVUXDDP 930 AXVCVUXWDP 931 AXVCVSXDSP 932 AXVCVSXWSP 933 AXVCVUXDSP 934 AXVCVUXWSP 935 936 ALAST 937 938 // aliases 939 ABR = obj.AJMP 940 ABL = obj.ACALL 941 )