github.com/FenixAra/go@v0.0.0-20170127160404-96ea0918e670/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "log" 35 "math" 36 "sort" 37 ) 38 39 // instruction layout. 40 const ( 41 funcAlign = 16 42 ) 43 44 type Optab struct { 45 as obj.As // opcode 46 a1 uint8 // From 47 a2 uint8 // Reg 48 a3 uint8 // From3 49 a4 uint8 // To 50 type_ int8 51 param int16 // REGSP for auto variables 52 } 53 54 var optab = []Optab{ 55 // instruction, From, Reg, From3, To, type, param 56 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 57 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 58 59 // move register 60 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 61 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 62 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 63 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 64 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 65 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 66 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 67 68 // load constant 69 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 70 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 71 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 72 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 73 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 74 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 75 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 76 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 77 78 // store constant 79 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 80 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 81 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 82 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 83 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 84 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 85 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 86 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 87 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 88 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 89 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 90 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 91 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 92 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 93 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 94 95 // store 96 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 97 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 98 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 99 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 100 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 101 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 102 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 103 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 104 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 105 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 106 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 107 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 108 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 109 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 110 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 111 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 112 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 113 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 114 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 115 116 // load 117 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 118 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 119 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 120 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 121 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 122 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 123 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 124 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 125 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 126 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 127 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 128 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 129 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 130 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 131 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 132 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 133 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 134 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 135 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 136 137 // interlocked load and op 138 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 139 140 // integer arithmetic 141 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 142 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 143 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 144 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 145 Optab{AADD, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 146 Optab{AADD, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 147 Optab{ASUB, C_LCON, C_REG, C_NONE, C_REG, 21, 0}, 148 Optab{ASUB, C_LCON, C_NONE, C_NONE, C_REG, 21, 0}, 149 Optab{ASUB, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 150 Optab{ASUB, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 151 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 152 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 153 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 154 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 155 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 156 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 157 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 158 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 159 160 // integer logical 161 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 162 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 163 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 164 Optab{AAND, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 165 Optab{AAND, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 166 Optab{AANDW, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 167 Optab{AANDW, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 168 Optab{AANDW, C_LCON, C_NONE, C_NONE, C_REG, 24, 0}, 169 Optab{AANDW, C_LOREG, C_NONE, C_NONE, C_REG, 12, 0}, 170 Optab{AANDW, C_LAUTO, C_NONE, C_NONE, C_REG, 12, REGSP}, 171 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 172 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 173 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 174 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 175 176 // compare and swap 177 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 178 179 // floating point 180 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 0}, 181 Optab{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 0}, 182 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 183 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 184 Optab{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 0}, 185 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 186 Optab{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 0}, 187 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 188 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 189 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 190 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 191 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 192 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 193 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 194 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 195 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 196 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 197 198 // load symbol address (plus offset) 199 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 200 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 201 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 202 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 203 204 // system call 205 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 206 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 207 208 // branch 209 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 210 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 211 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 212 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 213 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 214 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 215 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 216 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 217 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 218 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 219 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 220 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 221 222 // move on condition 223 Optab{AMOVDEQ, C_REG, C_NONE, C_NONE, C_REG, 17, 0}, 224 225 // find leftmost one 226 Optab{AFLOGR, C_REG, C_NONE, C_NONE, C_REG, 8, 0}, 227 228 // compare 229 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 230 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 231 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 232 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 233 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 234 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 235 236 // 32-bit access registers 237 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 238 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 239 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 240 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 241 242 // macros 243 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 244 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 245 246 // load/store multiple 247 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 248 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 249 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 250 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 251 252 // bytes 253 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 254 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 255 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 256 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 257 258 // fast synchronization 259 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0}, 260 261 // store clock 262 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 263 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 264 265 // storage and storage 266 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0}, 267 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 268 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 269 270 // address 271 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 272 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 273 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 274 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 275 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 276 277 // misc 278 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 279 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 280 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 281 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 282 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 283 284 // vector instructions 285 286 // VRX store 287 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 288 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 289 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0}, 290 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP}, 291 292 // VRX load 293 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 294 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 295 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0}, 296 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP}, 297 298 // VRV scatter 299 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0}, 300 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP}, 301 302 // VRV gather 303 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0}, 304 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP}, 305 306 // VRS element shift/rotate and load gr to/from vr element 307 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 308 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 309 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 310 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 311 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 312 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 313 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 314 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 315 316 // VRS store multiple 317 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 318 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 319 320 // VRS load multiple 321 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 322 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 323 324 // VRS store with length 325 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0}, 326 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP}, 327 328 // VRS load with length 329 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0}, 330 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP}, 331 332 // VRI-a 333 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 334 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 335 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 336 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 337 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0}, 338 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 339 340 // VRI-b generate mask 341 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 342 343 // VRI-c replicate 344 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 345 346 // VRI-d element rotate and insert under mask and 347 // shift left double by byte 348 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 349 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 350 351 // VRI-d fp test data class immediate 352 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 353 354 // VRR-a load reg 355 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 356 357 // VRR-a compare 358 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 359 360 // VRR-b 361 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 362 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 363 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 364 365 // VRR-c 366 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 367 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 368 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 369 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0}, 370 371 // VRR-c shifts 372 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 373 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 374 375 // VRR-d 376 // 2 3 1 4 377 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 378 379 // VRR-e 380 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 381 382 // VRR-f 383 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 384 } 385 386 var oprange [ALAST & obj.AMask][]Optab 387 388 var xcmp [C_NCLASS][C_NCLASS]bool 389 390 func spanz(ctxt *obj.Link, cursym *obj.LSym) { 391 p := cursym.Text 392 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 393 return 394 } 395 ctxt.Cursym = cursym 396 ctxt.Autosize = int32(p.To.Offset) 397 398 if oprange[AORW&obj.AMask] == nil { 399 buildop(ctxt) 400 } 401 402 buffer := make([]byte, 0) 403 changed := true 404 loop := 0 405 for changed { 406 if loop > 10 { 407 ctxt.Diag("stuck in spanz loop") 408 break 409 } 410 changed = false 411 buffer = buffer[:0] 412 ctxt.Cursym.R = make([]obj.Reloc, 0) 413 for p := cursym.Text; p != nil; p = p.Link { 414 pc := int64(len(buffer)) 415 if pc != p.Pc { 416 changed = true 417 } 418 p.Pc = pc 419 ctxt.Pc = p.Pc 420 ctxt.Curp = p 421 asmout(ctxt, &buffer) 422 if pc == int64(len(buffer)) { 423 switch p.As { 424 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 425 // ok 426 default: 427 ctxt.Diag("zero-width instruction\n%v", p) 428 } 429 } 430 } 431 loop++ 432 } 433 434 cursym.Size = int64(len(buffer)) 435 if cursym.Size%funcAlign != 0 { 436 cursym.Size += funcAlign - (cursym.Size % funcAlign) 437 } 438 cursym.Grow(cursym.Size) 439 copy(cursym.P, buffer) 440 } 441 442 func isint32(v int64) bool { 443 return int64(int32(v)) == v 444 } 445 446 func isuint32(v uint64) bool { 447 return uint64(uint32(v)) == v 448 } 449 450 func aclass(ctxt *obj.Link, a *obj.Addr) int { 451 switch a.Type { 452 case obj.TYPE_NONE: 453 return C_NONE 454 455 case obj.TYPE_REG: 456 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 457 return C_REG 458 } 459 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 460 return C_FREG 461 } 462 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 463 return C_AREG 464 } 465 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 466 return C_VREG 467 } 468 return C_GOK 469 470 case obj.TYPE_MEM: 471 switch a.Name { 472 case obj.NAME_EXTERN, 473 obj.NAME_STATIC: 474 if a.Sym == nil { 475 // must have a symbol 476 break 477 } 478 ctxt.Instoffset = a.Offset 479 if a.Sym.Type == obj.STLSBSS { 480 if ctxt.Flag_shared { 481 return C_TLS_IE // initial exec model 482 } 483 return C_TLS_LE // local exec model 484 } 485 return C_ADDR 486 487 case obj.NAME_GOTREF: 488 return C_GOTADDR 489 490 case obj.NAME_AUTO: 491 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 492 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 493 return C_SAUTO 494 } 495 return C_LAUTO 496 497 case obj.NAME_PARAM: 498 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 499 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 500 return C_SAUTO 501 } 502 return C_LAUTO 503 504 case obj.NAME_NONE: 505 ctxt.Instoffset = a.Offset 506 if ctxt.Instoffset == 0 { 507 return C_ZOREG 508 } 509 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 510 return C_SOREG 511 } 512 return C_LOREG 513 } 514 515 return C_GOK 516 517 case obj.TYPE_TEXTSIZE: 518 return C_TEXTSIZE 519 520 case obj.TYPE_FCONST: 521 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 522 return C_ZCON 523 } 524 ctxt.Diag("cannot handle the floating point constant %v", a.Val) 525 526 case obj.TYPE_CONST, 527 obj.TYPE_ADDR: 528 switch a.Name { 529 case obj.NAME_NONE: 530 ctxt.Instoffset = a.Offset 531 if a.Reg != 0 { 532 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 533 return C_SACON 534 } 535 if isint32(ctxt.Instoffset) { 536 return C_LACON 537 } 538 return C_DACON 539 } 540 goto consize 541 542 case obj.NAME_EXTERN, 543 obj.NAME_STATIC: 544 s := a.Sym 545 if s == nil { 546 break 547 } 548 ctxt.Instoffset = a.Offset 549 if s.Type == obj.SCONST { 550 goto consize 551 } 552 553 return C_SYMADDR 554 555 case obj.NAME_AUTO: 556 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 557 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 558 return C_SACON 559 } 560 return C_LACON 561 562 case obj.NAME_PARAM: 563 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 564 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 565 return C_SACON 566 } 567 return C_LACON 568 } 569 570 return C_GOK 571 572 consize: 573 if ctxt.Instoffset == 0 { 574 return C_ZCON 575 } 576 if ctxt.Instoffset >= 0 { 577 if ctxt.Instoffset <= 0x7fff { 578 return C_SCON 579 } 580 if ctxt.Instoffset <= 0xffff { 581 return C_ANDCON 582 } 583 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 584 return C_UCON 585 } 586 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 587 return C_LCON 588 } 589 return C_DCON 590 } 591 592 if ctxt.Instoffset >= -0x8000 { 593 return C_ADDCON 594 } 595 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 596 return C_UCON 597 } 598 if isint32(ctxt.Instoffset) { 599 return C_LCON 600 } 601 return C_DCON 602 603 case obj.TYPE_BRANCH: 604 return C_SBRA 605 } 606 607 return C_GOK 608 } 609 610 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 611 a1 := int(p.Optab) 612 if a1 != 0 { 613 return &optab[a1-1] 614 } 615 a1 = int(p.From.Class) 616 if a1 == 0 { 617 a1 = aclass(ctxt, &p.From) + 1 618 p.From.Class = int8(a1) 619 } 620 621 a1-- 622 a3 := C_NONE + 1 623 if p.From3 != nil { 624 a3 = int(p.From3.Class) 625 if a3 == 0 { 626 a3 = aclass(ctxt, p.From3) + 1 627 p.From3.Class = int8(a3) 628 } 629 } 630 631 a3-- 632 a4 := int(p.To.Class) 633 if a4 == 0 { 634 a4 = aclass(ctxt, &p.To) + 1 635 p.To.Class = int8(a4) 636 } 637 638 a4-- 639 a2 := C_NONE 640 if p.Reg != 0 { 641 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 642 a2 = C_REG 643 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 644 a2 = C_VREG 645 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 646 a2 = C_FREG 647 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 648 a2 = C_AREG 649 } 650 } 651 652 ops := oprange[p.As&obj.AMask] 653 c1 := &xcmp[a1] 654 c2 := &xcmp[a2] 655 c3 := &xcmp[a3] 656 c4 := &xcmp[a4] 657 for i := range ops { 658 op := &ops[i] 659 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 660 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 661 return op 662 } 663 } 664 665 // cannot find a case; abort 666 ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 667 ctxt.Diag("prog: %v\n", p) 668 return nil 669 } 670 671 func cmp(a int, b int) bool { 672 if a == b { 673 return true 674 } 675 switch a { 676 case C_DCON: 677 if b == C_LCON { 678 return true 679 } 680 fallthrough 681 case C_LCON: 682 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 683 return true 684 } 685 686 case C_ADDCON: 687 if b == C_ZCON || b == C_SCON { 688 return true 689 } 690 691 case C_ANDCON: 692 if b == C_ZCON || b == C_SCON { 693 return true 694 } 695 696 case C_UCON: 697 if b == C_ZCON || b == C_SCON { 698 return true 699 } 700 701 case C_SCON: 702 if b == C_ZCON { 703 return true 704 } 705 706 case C_LACON: 707 if b == C_SACON { 708 return true 709 } 710 711 case C_LBRA: 712 if b == C_SBRA { 713 return true 714 } 715 716 case C_LAUTO: 717 if b == C_SAUTO { 718 return true 719 } 720 721 case C_LOREG: 722 if b == C_ZOREG || b == C_SOREG { 723 return true 724 } 725 726 case C_SOREG: 727 if b == C_ZOREG { 728 return true 729 } 730 731 case C_ANY: 732 return true 733 } 734 735 return false 736 } 737 738 type ocmp []Optab 739 740 func (x ocmp) Len() int { 741 return len(x) 742 } 743 744 func (x ocmp) Swap(i, j int) { 745 x[i], x[j] = x[j], x[i] 746 } 747 748 func (x ocmp) Less(i, j int) bool { 749 p1 := &x[i] 750 p2 := &x[j] 751 n := int(p1.as) - int(p2.as) 752 if n != 0 { 753 return n < 0 754 } 755 n = int(p1.a1) - int(p2.a1) 756 if n != 0 { 757 return n < 0 758 } 759 n = int(p1.a2) - int(p2.a2) 760 if n != 0 { 761 return n < 0 762 } 763 n = int(p1.a3) - int(p2.a3) 764 if n != 0 { 765 return n < 0 766 } 767 n = int(p1.a4) - int(p2.a4) 768 if n != 0 { 769 return n < 0 770 } 771 return false 772 } 773 func opset(a, b obj.As) { 774 oprange[a&obj.AMask] = oprange[b&obj.AMask] 775 } 776 777 func buildop(ctxt *obj.Link) { 778 for i := 0; i < C_NCLASS; i++ { 779 for n := 0; n < C_NCLASS; n++ { 780 if cmp(n, i) { 781 xcmp[i][n] = true 782 } 783 } 784 } 785 sort.Sort(ocmp(optab)) 786 for i := 0; i < len(optab); i++ { 787 r := optab[i].as 788 start := i 789 for ; i+1 < len(optab); i++ { 790 if optab[i+1].as != r { 791 break 792 } 793 } 794 oprange[r&obj.AMask] = optab[start : i+1] 795 796 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 797 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 798 switch r { 799 case AADD: 800 opset(AADDC, r) 801 opset(AADDW, r) 802 opset(AMULLD, r) 803 opset(AMULLW, r) 804 case ADIVW: 805 opset(AADDE, r) 806 opset(ADIVD, r) 807 opset(ADIVDU, r) 808 opset(ADIVWU, r) 809 opset(AMODD, r) 810 opset(AMODDU, r) 811 opset(AMODW, r) 812 opset(AMODWU, r) 813 case AMULHD: 814 opset(AMULHDU, r) 815 case AMOVBZ: 816 opset(AMOVH, r) 817 opset(AMOVHZ, r) 818 case ALA: 819 opset(ALAY, r) 820 case AMVC: 821 opset(ACLC, r) 822 opset(AXC, r) 823 opset(AOC, r) 824 opset(ANC, r) 825 case ASTCK: 826 opset(ASTCKC, r) 827 opset(ASTCKE, r) 828 opset(ASTCKF, r) 829 case ALAAG: 830 opset(ALAA, r) 831 opset(ALAAL, r) 832 opset(ALAALG, r) 833 opset(ALAN, r) 834 opset(ALANG, r) 835 opset(ALAX, r) 836 opset(ALAXG, r) 837 opset(ALAO, r) 838 opset(ALAOG, r) 839 case ASTMG: 840 opset(ASTMY, r) 841 case ALMG: 842 opset(ALMY, r) 843 case ABEQ: 844 opset(ABGE, r) 845 opset(ABGT, r) 846 opset(ABLE, r) 847 opset(ABLT, r) 848 opset(ABNE, r) 849 opset(ABVC, r) 850 opset(ABVS, r) 851 opset(ABLEU, r) 852 opset(ABLTU, r) 853 case ABR: 854 opset(ABL, r) 855 case ABC: 856 opset(ABCL, r) 857 case AFABS: 858 opset(AFNABS, r) 859 opset(AFNEG, r) 860 opset(AFNEGS, r) 861 opset(ALEDBR, r) 862 opset(ALDEBR, r) 863 opset(AFSQRT, r) 864 opset(AFSQRTS, r) 865 case AFADD: 866 opset(AFADDS, r) 867 opset(AFDIV, r) 868 opset(AFDIVS, r) 869 opset(AFSUB, r) 870 opset(AFSUBS, r) 871 case AFMADD: 872 opset(AFMADDS, r) 873 opset(AFMSUB, r) 874 opset(AFMSUBS, r) 875 opset(AFNMADD, r) 876 opset(AFNMADDS, r) 877 opset(AFNMSUB, r) 878 opset(AFNMSUBS, r) 879 case AFMUL: 880 opset(AFMULS, r) 881 case AFCMPO: 882 opset(AFCMPU, r) 883 opset(ACEBR, r) 884 case AAND: 885 opset(AOR, r) 886 opset(AXOR, r) 887 case AANDW: 888 opset(AORW, r) 889 opset(AXORW, r) 890 case ASLD: 891 opset(ASRD, r) 892 opset(ASLW, r) 893 opset(ASRW, r) 894 opset(ASRAD, r) 895 opset(ASRAW, r) 896 opset(ARLL, r) 897 opset(ARLLG, r) 898 case ACSG: 899 opset(ACS, r) 900 case ASUB: 901 opset(ASUBC, r) 902 opset(ASUBE, r) 903 opset(ASUBW, r) 904 case ANEG: 905 opset(ANEGW, r) 906 case AFMOVD: 907 opset(AFMOVS, r) 908 case AMOVDBR: 909 opset(AMOVWBR, r) 910 case ACMP: 911 opset(ACMPW, r) 912 case ACMPU: 913 opset(ACMPWU, r) 914 case ACEFBRA: 915 opset(ACDFBRA, r) 916 opset(ACEGBRA, r) 917 opset(ACDGBRA, r) 918 opset(ACELFBR, r) 919 opset(ACDLFBR, r) 920 opset(ACELGBR, r) 921 opset(ACDLGBR, r) 922 case ACFEBRA: 923 opset(ACFDBRA, r) 924 opset(ACGEBRA, r) 925 opset(ACGDBRA, r) 926 opset(ACLFEBR, r) 927 opset(ACLFDBR, r) 928 opset(ACLGEBR, r) 929 opset(ACLGDBR, r) 930 case AFIEBR: 931 opset(AFIDBR, r) 932 case ACMPBEQ: 933 opset(ACMPBGE, r) 934 opset(ACMPBGT, r) 935 opset(ACMPBLE, r) 936 opset(ACMPBLT, r) 937 opset(ACMPBNE, r) 938 case ACMPUBEQ: 939 opset(ACMPUBGE, r) 940 opset(ACMPUBGT, r) 941 opset(ACMPUBLE, r) 942 opset(ACMPUBLT, r) 943 opset(ACMPUBNE, r) 944 case AMOVDEQ: 945 opset(AMOVDGE, r) 946 opset(AMOVDGT, r) 947 opset(AMOVDLE, r) 948 opset(AMOVDLT, r) 949 opset(AMOVDNE, r) 950 case AVL: 951 opset(AVLLEZB, r) 952 opset(AVLLEZH, r) 953 opset(AVLLEZF, r) 954 opset(AVLLEZG, r) 955 opset(AVLREPB, r) 956 opset(AVLREPH, r) 957 opset(AVLREPF, r) 958 opset(AVLREPG, r) 959 case AVLEG: 960 opset(AVLBB, r) 961 opset(AVLEB, r) 962 opset(AVLEH, r) 963 opset(AVLEF, r) 964 opset(AVLEG, r) 965 opset(AVLREP, r) 966 case AVSTEG: 967 opset(AVSTEB, r) 968 opset(AVSTEH, r) 969 opset(AVSTEF, r) 970 case AVSCEG: 971 opset(AVSCEF, r) 972 case AVGEG: 973 opset(AVGEF, r) 974 case AVESLG: 975 opset(AVESLB, r) 976 opset(AVESLH, r) 977 opset(AVESLF, r) 978 opset(AVERLLB, r) 979 opset(AVERLLH, r) 980 opset(AVERLLF, r) 981 opset(AVERLLG, r) 982 opset(AVESRAB, r) 983 opset(AVESRAH, r) 984 opset(AVESRAF, r) 985 opset(AVESRAG, r) 986 opset(AVESRLB, r) 987 opset(AVESRLH, r) 988 opset(AVESRLF, r) 989 opset(AVESRLG, r) 990 case AVLGVG: 991 opset(AVLGVB, r) 992 opset(AVLGVH, r) 993 opset(AVLGVF, r) 994 case AVLVGG: 995 opset(AVLVGB, r) 996 opset(AVLVGH, r) 997 opset(AVLVGF, r) 998 case AVZERO: 999 opset(AVONE, r) 1000 case AVREPIG: 1001 opset(AVREPIB, r) 1002 opset(AVREPIH, r) 1003 opset(AVREPIF, r) 1004 case AVLEIG: 1005 opset(AVLEIB, r) 1006 opset(AVLEIH, r) 1007 opset(AVLEIF, r) 1008 case AVGMG: 1009 opset(AVGMB, r) 1010 opset(AVGMH, r) 1011 opset(AVGMF, r) 1012 case AVREPG: 1013 opset(AVREPB, r) 1014 opset(AVREPH, r) 1015 opset(AVREPF, r) 1016 case AVERIMG: 1017 opset(AVERIMB, r) 1018 opset(AVERIMH, r) 1019 opset(AVERIMF, r) 1020 case AVFTCIDB: 1021 opset(AWFTCIDB, r) 1022 case AVLR: 1023 opset(AVUPHB, r) 1024 opset(AVUPHH, r) 1025 opset(AVUPHF, r) 1026 opset(AVUPLHB, r) 1027 opset(AVUPLHH, r) 1028 opset(AVUPLHF, r) 1029 opset(AVUPLB, r) 1030 opset(AVUPLHW, r) 1031 opset(AVUPLF, r) 1032 opset(AVUPLLB, r) 1033 opset(AVUPLLH, r) 1034 opset(AVUPLLF, r) 1035 opset(AVCLZB, r) 1036 opset(AVCLZH, r) 1037 opset(AVCLZF, r) 1038 opset(AVCLZG, r) 1039 opset(AVCTZB, r) 1040 opset(AVCTZH, r) 1041 opset(AVCTZF, r) 1042 opset(AVCTZG, r) 1043 opset(AVLDEB, r) 1044 opset(AWLDEB, r) 1045 opset(AVFLCDB, r) 1046 opset(AWFLCDB, r) 1047 opset(AVFLNDB, r) 1048 opset(AWFLNDB, r) 1049 opset(AVFLPDB, r) 1050 opset(AWFLPDB, r) 1051 opset(AVFSQDB, r) 1052 opset(AWFSQDB, r) 1053 opset(AVISTRB, r) 1054 opset(AVISTRH, r) 1055 opset(AVISTRF, r) 1056 opset(AVISTRBS, r) 1057 opset(AVISTRHS, r) 1058 opset(AVISTRFS, r) 1059 opset(AVLCB, r) 1060 opset(AVLCH, r) 1061 opset(AVLCF, r) 1062 opset(AVLCG, r) 1063 opset(AVLPB, r) 1064 opset(AVLPH, r) 1065 opset(AVLPF, r) 1066 opset(AVLPG, r) 1067 opset(AVPOPCT, r) 1068 opset(AVSEGB, r) 1069 opset(AVSEGH, r) 1070 opset(AVSEGF, r) 1071 case AVECG: 1072 opset(AVECB, r) 1073 opset(AVECH, r) 1074 opset(AVECF, r) 1075 opset(AVECLB, r) 1076 opset(AVECLH, r) 1077 opset(AVECLF, r) 1078 opset(AVECLG, r) 1079 opset(AWFCDB, r) 1080 opset(AWFKDB, r) 1081 case AVCEQG: 1082 opset(AVCEQB, r) 1083 opset(AVCEQH, r) 1084 opset(AVCEQF, r) 1085 opset(AVCEQBS, r) 1086 opset(AVCEQHS, r) 1087 opset(AVCEQFS, r) 1088 opset(AVCEQGS, r) 1089 opset(AVCHB, r) 1090 opset(AVCHH, r) 1091 opset(AVCHF, r) 1092 opset(AVCHG, r) 1093 opset(AVCHBS, r) 1094 opset(AVCHHS, r) 1095 opset(AVCHFS, r) 1096 opset(AVCHGS, r) 1097 opset(AVCHLB, r) 1098 opset(AVCHLH, r) 1099 opset(AVCHLF, r) 1100 opset(AVCHLG, r) 1101 opset(AVCHLBS, r) 1102 opset(AVCHLHS, r) 1103 opset(AVCHLFS, r) 1104 opset(AVCHLGS, r) 1105 case AVFAEF: 1106 opset(AVFAEB, r) 1107 opset(AVFAEH, r) 1108 opset(AVFAEBS, r) 1109 opset(AVFAEHS, r) 1110 opset(AVFAEFS, r) 1111 opset(AVFAEZB, r) 1112 opset(AVFAEZH, r) 1113 opset(AVFAEZF, r) 1114 opset(AVFAEZBS, r) 1115 opset(AVFAEZHS, r) 1116 opset(AVFAEZFS, r) 1117 opset(AVFEEB, r) 1118 opset(AVFEEH, r) 1119 opset(AVFEEF, r) 1120 opset(AVFEEBS, r) 1121 opset(AVFEEHS, r) 1122 opset(AVFEEFS, r) 1123 opset(AVFEEZB, r) 1124 opset(AVFEEZH, r) 1125 opset(AVFEEZF, r) 1126 opset(AVFEEZBS, r) 1127 opset(AVFEEZHS, r) 1128 opset(AVFEEZFS, r) 1129 opset(AVFENEB, r) 1130 opset(AVFENEH, r) 1131 opset(AVFENEF, r) 1132 opset(AVFENEBS, r) 1133 opset(AVFENEHS, r) 1134 opset(AVFENEFS, r) 1135 opset(AVFENEZB, r) 1136 opset(AVFENEZH, r) 1137 opset(AVFENEZF, r) 1138 opset(AVFENEZBS, r) 1139 opset(AVFENEZHS, r) 1140 opset(AVFENEZFS, r) 1141 case AVPKSG: 1142 opset(AVPKSH, r) 1143 opset(AVPKSF, r) 1144 opset(AVPKSHS, r) 1145 opset(AVPKSFS, r) 1146 opset(AVPKSGS, r) 1147 opset(AVPKLSH, r) 1148 opset(AVPKLSF, r) 1149 opset(AVPKLSG, r) 1150 opset(AVPKLSHS, r) 1151 opset(AVPKLSFS, r) 1152 opset(AVPKLSGS, r) 1153 case AVAQ: 1154 opset(AVAB, r) 1155 opset(AVAH, r) 1156 opset(AVAF, r) 1157 opset(AVAG, r) 1158 opset(AVACCB, r) 1159 opset(AVACCH, r) 1160 opset(AVACCF, r) 1161 opset(AVACCG, r) 1162 opset(AVACCQ, r) 1163 opset(AVN, r) 1164 opset(AVNC, r) 1165 opset(AVAVGB, r) 1166 opset(AVAVGH, r) 1167 opset(AVAVGF, r) 1168 opset(AVAVGG, r) 1169 opset(AVAVGLB, r) 1170 opset(AVAVGLH, r) 1171 opset(AVAVGLF, r) 1172 opset(AVAVGLG, r) 1173 opset(AVCKSM, r) 1174 opset(AVX, r) 1175 opset(AVFADB, r) 1176 opset(AWFADB, r) 1177 opset(AVFCEDB, r) 1178 opset(AVFCEDBS, r) 1179 opset(AWFCEDB, r) 1180 opset(AWFCEDBS, r) 1181 opset(AVFCHDB, r) 1182 opset(AVFCHDBS, r) 1183 opset(AWFCHDB, r) 1184 opset(AWFCHDBS, r) 1185 opset(AVFCHEDB, r) 1186 opset(AVFCHEDBS, r) 1187 opset(AWFCHEDB, r) 1188 opset(AWFCHEDBS, r) 1189 opset(AVFMDB, r) 1190 opset(AWFMDB, r) 1191 opset(AVGFMB, r) 1192 opset(AVGFMH, r) 1193 opset(AVGFMF, r) 1194 opset(AVGFMG, r) 1195 opset(AVMXB, r) 1196 opset(AVMXH, r) 1197 opset(AVMXF, r) 1198 opset(AVMXG, r) 1199 opset(AVMXLB, r) 1200 opset(AVMXLH, r) 1201 opset(AVMXLF, r) 1202 opset(AVMXLG, r) 1203 opset(AVMNB, r) 1204 opset(AVMNH, r) 1205 opset(AVMNF, r) 1206 opset(AVMNG, r) 1207 opset(AVMNLB, r) 1208 opset(AVMNLH, r) 1209 opset(AVMNLF, r) 1210 opset(AVMNLG, r) 1211 opset(AVMRHB, r) 1212 opset(AVMRHH, r) 1213 opset(AVMRHF, r) 1214 opset(AVMRHG, r) 1215 opset(AVMRLB, r) 1216 opset(AVMRLH, r) 1217 opset(AVMRLF, r) 1218 opset(AVMRLG, r) 1219 opset(AVMEB, r) 1220 opset(AVMEH, r) 1221 opset(AVMEF, r) 1222 opset(AVMLEB, r) 1223 opset(AVMLEH, r) 1224 opset(AVMLEF, r) 1225 opset(AVMOB, r) 1226 opset(AVMOH, r) 1227 opset(AVMOF, r) 1228 opset(AVMLOB, r) 1229 opset(AVMLOH, r) 1230 opset(AVMLOF, r) 1231 opset(AVMHB, r) 1232 opset(AVMHH, r) 1233 opset(AVMHF, r) 1234 opset(AVMLHB, r) 1235 opset(AVMLHH, r) 1236 opset(AVMLHF, r) 1237 opset(AVMLH, r) 1238 opset(AVMLHW, r) 1239 opset(AVMLF, r) 1240 opset(AVNO, r) 1241 opset(AVO, r) 1242 opset(AVPKH, r) 1243 opset(AVPKF, r) 1244 opset(AVPKG, r) 1245 opset(AVSUMGH, r) 1246 opset(AVSUMGF, r) 1247 opset(AVSUMQF, r) 1248 opset(AVSUMQG, r) 1249 opset(AVSUMB, r) 1250 opset(AVSUMH, r) 1251 case AVERLLVG: 1252 opset(AVERLLVB, r) 1253 opset(AVERLLVH, r) 1254 opset(AVERLLVF, r) 1255 opset(AVESLVB, r) 1256 opset(AVESLVH, r) 1257 opset(AVESLVF, r) 1258 opset(AVESLVG, r) 1259 opset(AVESRAVB, r) 1260 opset(AVESRAVH, r) 1261 opset(AVESRAVF, r) 1262 opset(AVESRAVG, r) 1263 opset(AVESRLVB, r) 1264 opset(AVESRLVH, r) 1265 opset(AVESRLVF, r) 1266 opset(AVESRLVG, r) 1267 opset(AVFDDB, r) 1268 opset(AWFDDB, r) 1269 opset(AVFSDB, r) 1270 opset(AWFSDB, r) 1271 opset(AVSL, r) 1272 opset(AVSLB, r) 1273 opset(AVSRA, r) 1274 opset(AVSRAB, r) 1275 opset(AVSRL, r) 1276 opset(AVSRLB, r) 1277 opset(AVSF, r) 1278 opset(AVSG, r) 1279 opset(AVSQ, r) 1280 opset(AVSCBIB, r) 1281 opset(AVSCBIH, r) 1282 opset(AVSCBIF, r) 1283 opset(AVSCBIG, r) 1284 opset(AVSCBIQ, r) 1285 case AVACQ: 1286 opset(AVACCCQ, r) 1287 opset(AVGFMAB, r) 1288 opset(AVGFMAH, r) 1289 opset(AVGFMAF, r) 1290 opset(AVGFMAG, r) 1291 opset(AVMALB, r) 1292 opset(AVMALHW, r) 1293 opset(AVMALF, r) 1294 opset(AVMAHB, r) 1295 opset(AVMAHH, r) 1296 opset(AVMAHF, r) 1297 opset(AVMALHB, r) 1298 opset(AVMALHH, r) 1299 opset(AVMALHF, r) 1300 opset(AVMAEB, r) 1301 opset(AVMAEH, r) 1302 opset(AVMAEF, r) 1303 opset(AVMALEB, r) 1304 opset(AVMALEH, r) 1305 opset(AVMALEF, r) 1306 opset(AVMAOB, r) 1307 opset(AVMAOH, r) 1308 opset(AVMAOF, r) 1309 opset(AVMALOB, r) 1310 opset(AVMALOH, r) 1311 opset(AVMALOF, r) 1312 opset(AVSTRCB, r) 1313 opset(AVSTRCH, r) 1314 opset(AVSTRCF, r) 1315 opset(AVSTRCBS, r) 1316 opset(AVSTRCHS, r) 1317 opset(AVSTRCFS, r) 1318 opset(AVSTRCZB, r) 1319 opset(AVSTRCZH, r) 1320 opset(AVSTRCZF, r) 1321 opset(AVSTRCZBS, r) 1322 opset(AVSTRCZHS, r) 1323 opset(AVSTRCZFS, r) 1324 opset(AVSBCBIQ, r) 1325 opset(AVSBIQ, r) 1326 case AVSEL: 1327 opset(AVFMADB, r) 1328 opset(AWFMADB, r) 1329 opset(AVFMSDB, r) 1330 opset(AWFMSDB, r) 1331 opset(AVPERM, r) 1332 } 1333 } 1334 } 1335 1336 const ( 1337 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1338 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1339 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1340 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1341 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1342 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1343 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1344 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1345 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1346 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1347 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1348 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1349 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1350 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1351 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1352 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1353 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1354 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1355 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1356 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1357 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1358 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1359 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1360 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1361 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1362 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1363 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1364 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1365 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1366 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1367 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1368 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1369 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1370 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1371 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1372 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1373 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1374 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1375 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1376 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1377 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1378 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1379 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1380 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1381 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1382 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1383 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1384 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1385 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1386 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1387 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1388 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1389 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1390 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1391 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1392 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1393 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1394 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1395 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1396 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1397 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1398 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1399 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1400 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1401 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1402 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1403 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1404 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1405 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1406 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1407 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1408 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1409 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1410 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1411 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1412 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1413 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1414 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1415 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1416 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1417 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1418 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1419 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1420 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1421 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1422 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1423 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1424 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1425 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1426 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1427 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1428 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1429 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1430 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1431 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1432 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1433 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1434 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1435 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1436 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1437 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1438 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1439 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1440 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1441 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1442 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1443 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1444 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1445 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1446 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1447 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1448 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1449 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1450 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1451 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1452 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1453 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1454 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1455 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1456 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1457 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1458 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1459 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1460 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1461 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1462 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1463 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1464 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1465 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1466 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1467 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1468 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1469 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1470 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1471 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1472 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1473 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1474 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1475 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1476 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1477 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1478 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1479 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1480 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1481 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1482 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1483 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1484 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1485 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1486 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1487 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1488 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1489 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1490 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1491 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1492 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1493 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1494 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1495 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1496 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1497 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1498 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1499 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1500 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1501 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1502 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1503 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1504 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1505 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1506 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1507 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1508 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1509 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1510 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1511 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1512 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1513 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1514 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1515 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1516 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1517 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1518 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1519 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1520 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1521 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1522 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1523 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1524 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1525 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1526 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1527 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1528 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1529 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1530 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1531 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1532 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1533 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1534 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1535 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1536 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1537 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1538 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1539 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1540 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1541 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1542 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1543 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1544 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1545 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1546 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1547 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1548 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1549 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1550 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1551 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1552 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1553 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1554 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1555 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1556 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1557 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1558 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1559 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1560 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1561 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1562 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1563 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1564 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1565 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1566 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1567 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1568 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1569 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1570 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1571 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1572 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1573 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1574 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1575 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1576 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1577 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1578 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1579 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1580 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1581 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1582 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1583 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1584 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1585 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1586 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1587 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1588 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1589 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1590 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1591 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1592 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1593 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1594 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1595 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1596 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1597 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1598 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1599 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1600 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1601 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1602 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1603 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1604 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1605 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1606 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1607 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1608 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1609 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1610 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1611 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1612 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1613 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1614 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1615 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1616 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1617 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1618 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1619 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1620 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1621 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1622 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1623 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1624 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1625 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1626 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1627 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1628 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1629 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1630 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1631 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1632 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1633 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1634 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1635 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1636 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1637 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1638 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1639 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1640 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1641 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1642 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1643 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1644 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1645 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1646 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1647 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1648 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1649 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1650 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1651 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1652 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1653 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1654 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1655 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1656 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1657 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1658 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1659 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1660 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1661 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1662 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1663 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1664 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1665 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1666 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1667 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1668 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1669 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1670 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1671 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1672 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1673 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1674 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1675 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1676 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1677 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1678 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1679 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1680 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1681 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1682 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1683 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1684 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1685 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1686 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1687 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1688 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1689 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1690 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1691 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1692 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1693 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1694 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1695 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1696 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1697 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1698 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1699 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1700 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1701 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1702 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1703 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1704 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1705 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1706 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1707 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1708 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1709 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1710 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1711 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1712 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1713 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1714 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1715 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1716 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1717 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1718 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1719 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1720 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1721 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1722 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1723 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1724 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1725 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1726 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1727 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1728 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1729 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1730 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1731 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1732 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1733 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1734 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1735 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1736 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1737 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1738 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1739 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1740 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1741 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1742 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1743 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1744 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1745 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1746 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1747 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1748 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1749 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1750 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1751 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1752 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1753 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1754 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1755 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1756 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1757 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1758 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1759 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1760 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1761 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1762 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1763 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1764 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1765 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1766 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1767 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1768 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1769 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1770 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1771 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1772 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1773 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1774 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1775 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1776 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1777 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1778 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1779 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1780 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1781 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1782 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1783 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1784 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1785 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1786 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1787 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1788 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1789 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1790 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1791 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1792 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1793 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1794 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1795 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1796 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1797 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1798 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1799 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1800 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1801 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1802 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1803 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1804 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1805 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1806 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1807 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1808 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1809 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1810 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1811 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1812 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1813 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1814 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1815 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1816 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1817 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1818 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1819 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1820 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1821 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1822 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1823 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1824 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1825 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1826 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1827 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1828 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1829 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1830 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1831 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1832 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1833 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1834 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1835 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1836 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1837 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1838 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1839 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1840 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1841 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1842 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1843 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1844 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1845 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1846 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1847 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1848 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1849 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1850 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1851 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1852 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1853 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1854 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1855 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1856 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1857 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1858 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1859 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1860 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1861 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1862 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1863 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1864 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1865 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1866 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1867 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1868 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1869 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1870 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1871 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1872 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1873 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1874 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1875 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1876 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1877 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1878 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1879 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1880 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1881 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1882 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1883 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1884 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1885 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1886 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1887 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1888 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1889 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1890 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1891 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1892 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1893 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1894 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1895 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1896 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1897 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1898 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1899 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1900 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1901 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1902 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1903 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1904 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1905 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1906 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1907 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1908 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1909 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1910 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1911 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1912 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1913 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1914 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1915 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1916 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1917 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1918 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1919 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1920 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1921 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1922 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1923 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1924 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1925 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1926 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1927 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1928 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1929 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1930 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1931 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1932 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1933 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1934 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1935 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1936 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1937 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1938 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1939 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1940 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1941 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1942 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1943 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1944 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1945 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1946 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1947 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1948 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1949 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1950 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1951 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1952 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1953 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1954 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1955 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1956 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1957 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1958 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1959 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1960 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1961 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1962 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1963 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1964 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1965 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1966 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1967 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1968 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1969 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1970 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1971 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1972 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1973 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1974 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1975 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1976 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1977 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1978 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1979 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1980 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1981 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1982 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1983 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1984 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 1985 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 1986 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 1987 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 1988 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 1989 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 1990 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 1991 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 1992 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 1993 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 1994 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 1995 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 1996 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 1997 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 1998 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 1999 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 2000 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 2001 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 2002 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 2003 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 2004 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 2005 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 2006 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 2007 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 2008 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 2009 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 2010 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 2011 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 2012 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 2013 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 2014 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 2015 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2016 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 2017 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 2018 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 2019 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2020 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2021 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2022 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2023 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2024 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2025 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2026 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2027 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2028 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2029 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2030 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2031 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2032 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2033 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2034 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2035 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2036 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2037 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2038 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2039 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2040 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2041 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2042 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2043 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2044 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2045 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2046 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2047 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2048 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2049 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2050 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2051 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2052 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2053 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2054 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2055 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2056 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2057 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2058 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2059 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2060 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2061 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2062 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2063 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2064 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2065 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2066 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2067 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2068 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2069 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2070 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2071 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2072 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2073 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2074 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2075 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2076 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2077 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2078 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2079 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2080 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2081 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2082 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2083 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2084 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2085 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2086 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2087 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2088 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2089 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2090 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2091 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2092 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2093 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2094 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2095 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2096 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2097 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2098 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2099 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2100 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2101 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2102 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2103 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2104 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2105 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2106 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2107 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2108 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2109 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2110 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2111 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2112 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2113 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2114 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2115 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2116 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2117 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2118 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2119 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2120 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2121 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2122 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2123 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2124 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2125 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2126 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2127 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2128 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2129 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2130 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2131 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2132 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2133 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2134 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2135 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2136 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2137 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2138 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2139 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2140 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2141 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2142 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2143 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2144 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2145 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2146 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2147 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2148 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2149 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2150 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2151 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2152 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2153 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2154 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2155 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2156 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2157 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2158 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2159 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2160 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2161 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2162 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2163 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2164 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2165 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2166 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2167 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2168 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2169 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2170 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2171 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2172 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2173 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2174 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2175 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2176 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2177 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2178 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2179 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2180 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2181 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2182 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2183 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2184 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2185 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2186 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2187 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2188 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2189 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2190 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2191 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2192 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2193 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2194 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2195 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2196 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2197 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2198 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2199 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2200 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2201 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2202 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2203 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2204 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2205 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2206 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2207 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2208 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2209 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2210 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2211 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2212 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2213 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2214 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2215 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2216 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2217 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2218 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2219 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2220 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2221 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2222 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2223 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2224 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2225 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2226 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2227 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2228 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2229 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2230 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2231 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2232 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2233 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2234 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2235 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2236 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2237 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2238 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2239 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2240 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2241 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2242 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2243 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2244 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2245 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2246 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2247 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2248 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2249 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2250 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2251 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2252 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2253 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2254 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2255 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2256 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2257 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2258 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2259 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2260 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2261 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2262 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2263 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2264 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2265 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2266 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2267 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2268 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2269 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2270 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2271 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2272 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2273 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2274 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2275 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2276 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2277 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2278 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2279 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2280 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2281 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2282 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2283 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2284 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2285 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2286 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2287 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2288 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2289 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2290 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2291 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2292 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2293 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2294 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2295 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2296 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2297 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2298 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2299 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2300 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2301 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2302 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2303 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2304 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2305 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2306 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2307 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2308 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2309 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2310 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2311 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2312 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2313 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2314 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2315 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2316 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2317 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2318 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2319 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2320 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2321 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2322 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2323 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2324 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2325 2326 // added in z13 2327 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2328 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2329 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2330 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2331 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2332 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2333 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2334 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2335 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2336 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2337 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2338 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2339 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2340 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2341 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2342 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2343 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2344 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2345 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2346 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2347 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2348 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2349 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2350 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2351 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2352 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2353 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2354 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2355 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2356 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2357 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2358 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2359 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2360 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2361 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2362 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2363 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2364 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2365 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2366 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2367 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2368 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2369 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2370 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2371 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2372 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2373 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2374 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2375 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2376 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2377 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2378 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2379 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2380 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2381 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2382 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2383 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2384 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2385 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2386 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2387 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2388 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2389 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2390 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2391 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2392 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2393 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2394 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2395 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2396 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2397 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2398 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2399 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2400 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2401 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2402 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2403 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2404 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2405 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2406 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2407 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2408 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2409 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2410 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2411 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2412 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2413 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2414 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2415 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2416 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2417 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2418 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2419 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2420 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2421 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2422 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2423 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2424 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2425 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2426 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2427 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2428 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2429 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2430 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2431 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2432 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2433 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2434 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2435 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2436 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2437 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2438 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2439 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2440 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2441 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2442 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2443 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2444 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2445 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2446 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2447 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2448 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2449 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2450 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2451 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2452 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2453 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2454 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2455 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2456 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2457 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2458 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2459 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2460 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2461 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2462 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2463 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2464 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2465 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2466 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2467 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2468 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2469 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2470 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2471 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2472 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2473 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2474 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2475 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2476 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2477 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2478 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2479 ) 2480 2481 func oclass(a *obj.Addr) int { 2482 return int(a.Class) - 1 2483 } 2484 2485 // Add a relocation for the immediate in a RIL style instruction. 2486 // The addend will be adjusted as required. 2487 func addrilreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2488 if sym == nil { 2489 ctxt.Diag("require symbol to apply relocation") 2490 } 2491 offset := int64(2) // relocation offset from start of instruction 2492 rel := obj.Addrel(ctxt.Cursym) 2493 rel.Off = int32(ctxt.Pc + offset) 2494 rel.Siz = 4 2495 rel.Sym = sym 2496 rel.Add = add + offset + int64(rel.Siz) 2497 rel.Type = obj.R_PCRELDBL 2498 return rel 2499 } 2500 2501 func addrilrelocoffset(ctxt *obj.Link, sym *obj.LSym, add, offset int64) *obj.Reloc { 2502 if sym == nil { 2503 ctxt.Diag("require symbol to apply relocation") 2504 } 2505 offset += int64(2) // relocation offset from start of instruction 2506 rel := obj.Addrel(ctxt.Cursym) 2507 rel.Off = int32(ctxt.Pc + offset) 2508 rel.Siz = 4 2509 rel.Sym = sym 2510 rel.Add = add + offset + int64(rel.Siz) 2511 rel.Type = obj.R_PCRELDBL 2512 return rel 2513 } 2514 2515 // Add a CALL relocation for the immediate in a RIL style instruction. 2516 // The addend will be adjusted as required. 2517 func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2518 if sym == nil { 2519 ctxt.Diag("require symbol to apply relocation") 2520 } 2521 offset := int64(2) // relocation offset from start of instruction 2522 rel := obj.Addrel(ctxt.Cursym) 2523 rel.Off = int32(ctxt.Pc + offset) 2524 rel.Siz = 4 2525 rel.Sym = sym 2526 rel.Add = add + offset + int64(rel.Siz) 2527 rel.Type = obj.R_CALL 2528 return rel 2529 } 2530 2531 func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 { 2532 switch p.As { 2533 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ: 2534 return 0x8 2535 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE: 2536 return 0xA 2537 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT: 2538 return 0x2 2539 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE: 2540 return 0xC 2541 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT: 2542 return 0x4 2543 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE: 2544 return 0x7 2545 case ABLEU: // LE or unordered 2546 return 0xD 2547 case ABLTU: // LT or unordered 2548 return 0x5 2549 case ABVC: 2550 return 0x0 // needs extra instruction 2551 case ABVS: 2552 return 0x1 // unordered 2553 } 2554 ctxt.Diag("unknown conditional branch %v", p.As) 2555 return 0xF 2556 } 2557 2558 func asmout(ctxt *obj.Link, asm *[]byte) { 2559 p := ctxt.Curp 2560 o := oplook(ctxt, p) 2561 ctxt.Printp = p 2562 2563 switch o.type_ { 2564 default: 2565 ctxt.Diag("unknown type %d", o.type_) 2566 2567 case 0: // PSEUDO OPS 2568 break 2569 2570 case 1: // mov reg reg 2571 switch p.As { 2572 default: 2573 ctxt.Diag("unhandled operation: %v", p.As) 2574 case AMOVD: 2575 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2576 // sign extend 2577 case AMOVW: 2578 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2579 case AMOVH: 2580 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2581 case AMOVB: 2582 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2583 // zero extend 2584 case AMOVWZ: 2585 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2586 case AMOVHZ: 2587 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2588 case AMOVBZ: 2589 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2590 // reverse bytes 2591 case AMOVDBR: 2592 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2593 case AMOVWBR: 2594 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2595 // floating point 2596 case AFMOVD, AFMOVS: 2597 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2598 } 2599 2600 case 2: // arithmetic op reg [reg] reg 2601 r := p.Reg 2602 if r == 0 { 2603 r = p.To.Reg 2604 } 2605 2606 var opcode uint32 2607 2608 switch p.As { 2609 default: 2610 ctxt.Diag("invalid opcode") 2611 case AADD: 2612 opcode = op_AGRK 2613 case AADDC: 2614 opcode = op_ALGRK 2615 case AADDE: 2616 opcode = op_ALCGR 2617 case AADDW: 2618 opcode = op_ARK 2619 case AMULLW: 2620 opcode = op_MSGFR 2621 case AMULLD: 2622 opcode = op_MSGR 2623 case ADIVW, AMODW: 2624 opcode = op_DSGFR 2625 case ADIVWU, AMODWU: 2626 opcode = op_DLR 2627 case ADIVD, AMODD: 2628 opcode = op_DSGR 2629 case ADIVDU, AMODDU: 2630 opcode = op_DLGR 2631 case AFADD: 2632 opcode = op_ADBR 2633 case AFADDS: 2634 opcode = op_AEBR 2635 case AFSUB: 2636 opcode = op_SDBR 2637 case AFSUBS: 2638 opcode = op_SEBR 2639 case AFDIV: 2640 opcode = op_DDBR 2641 case AFDIVS: 2642 opcode = op_DEBR 2643 } 2644 2645 switch p.As { 2646 default: 2647 2648 case AADD, AADDC, AADDW: 2649 if p.As == AADDW && r == p.To.Reg { 2650 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2651 } else { 2652 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2653 } 2654 2655 case AADDE, AMULLW, AMULLD: 2656 if r == p.To.Reg { 2657 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2658 } else if p.From.Reg == p.To.Reg { 2659 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2660 } else { 2661 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2662 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2663 } 2664 2665 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2666 if p.As == ADIVWU || p.As == ADIVDU { 2667 zRI(op_LGHI, REGTMP, 0, asm) 2668 } 2669 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2670 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2671 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2672 2673 case AMODW, AMODWU, AMODD, AMODDU: 2674 if p.As == AMODWU || p.As == AMODDU { 2675 zRI(op_LGHI, REGTMP, 0, asm) 2676 } 2677 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2678 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2679 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2680 2681 case AFADD, AFADDS: 2682 if r == p.To.Reg { 2683 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2684 } else if p.From.Reg == p.To.Reg { 2685 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2686 } else { 2687 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2688 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2689 } 2690 2691 case AFSUB, AFSUBS, AFDIV, AFDIVS: 2692 if r == p.To.Reg { 2693 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2694 } else if p.From.Reg == p.To.Reg { 2695 zRRE(op_LGDR, REGTMP, uint32(r), asm) 2696 zRRE(opcode, uint32(r), uint32(p.From.Reg), asm) 2697 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2698 zRRE(op_LDGR, uint32(r), REGTMP, asm) 2699 } else { 2700 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2701 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2702 } 2703 2704 } 2705 2706 case 3: // mov $constant reg 2707 v := vregoff(ctxt, &p.From) 2708 switch p.As { 2709 case AMOVBZ: 2710 v = int64(uint8(v)) 2711 case AMOVHZ: 2712 v = int64(uint16(v)) 2713 case AMOVWZ: 2714 v = int64(uint32(v)) 2715 case AMOVB: 2716 v = int64(int8(v)) 2717 case AMOVH: 2718 v = int64(int16(v)) 2719 case AMOVW: 2720 v = int64(int32(v)) 2721 } 2722 if int64(int16(v)) == v { 2723 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2724 } else if v&0xffff0000 == v { 2725 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2726 } else if v&0xffff00000000 == v { 2727 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2728 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2729 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2730 } else if int64(int32(v)) == v { 2731 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2732 } else if int64(uint32(v)) == v { 2733 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2734 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2735 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2736 } else { 2737 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2738 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2739 } 2740 2741 case 4: // multiply high (a*b)>>64 2742 r := p.Reg 2743 if r == 0 { 2744 r = p.To.Reg 2745 } 2746 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2747 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2748 switch p.As { 2749 case AMULHDU: 2750 // Unsigned: move result into correct register. 2751 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2752 case AMULHD: 2753 // Signed: need to convert result. 2754 // See Hacker's Delight 8-3. 2755 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2756 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2757 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2758 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2759 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2760 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2761 } 2762 2763 case 5: // syscall 2764 zI(op_SVC, 0, asm) 2765 2766 case 6: // logical op reg [reg] reg 2767 var oprr, oprre, oprrf uint32 2768 switch p.As { 2769 case AAND: 2770 oprre = op_NGR 2771 oprrf = op_NGRK 2772 case AANDW: 2773 oprr = op_NR 2774 oprrf = op_NRK 2775 case AOR: 2776 oprre = op_OGR 2777 oprrf = op_OGRK 2778 case AORW: 2779 oprr = op_OR 2780 oprrf = op_ORK 2781 case AXOR: 2782 oprre = op_XGR 2783 oprrf = op_XGRK 2784 case AXORW: 2785 oprr = op_XR 2786 oprrf = op_XRK 2787 } 2788 if p.Reg == 0 { 2789 if oprr != 0 { 2790 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2791 } else { 2792 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2793 } 2794 } else { 2795 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2796 } 2797 2798 case 7: // shift/rotate reg [reg] reg 2799 d2 := vregoff(ctxt, &p.From) 2800 b2 := p.From.Reg 2801 r3 := p.Reg 2802 if r3 == 0 { 2803 r3 = p.To.Reg 2804 } 2805 r1 := p.To.Reg 2806 var opcode uint32 2807 switch p.As { 2808 default: 2809 case ASLD: 2810 opcode = op_SLLG 2811 case ASRD: 2812 opcode = op_SRLG 2813 case ASLW: 2814 opcode = op_SLLK 2815 case ASRW: 2816 opcode = op_SRLK 2817 case ARLL: 2818 opcode = op_RLL 2819 case ARLLG: 2820 opcode = op_RLLG 2821 case ASRAW: 2822 opcode = op_SRAK 2823 case ASRAD: 2824 opcode = op_SRAG 2825 } 2826 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2827 2828 case 8: // find leftmost one 2829 if p.To.Reg&1 != 0 { 2830 ctxt.Diag("target must be an even-numbered register") 2831 } 2832 // FLOGR also writes a mask to p.To.Reg+1. 2833 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2834 2835 case 10: // subtract reg [reg] reg 2836 r := int(p.Reg) 2837 2838 switch p.As { 2839 default: 2840 case ASUB: 2841 if r == 0 { 2842 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2843 } else { 2844 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2845 } 2846 case ASUBC: 2847 if r == 0 { 2848 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2849 } else { 2850 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2851 } 2852 case ASUBE: 2853 if r == 0 { 2854 r = int(p.To.Reg) 2855 } 2856 if r == int(p.To.Reg) { 2857 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2858 } else if p.From.Reg == p.To.Reg { 2859 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2860 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2861 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2862 } else { 2863 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2864 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2865 } 2866 case ASUBW: 2867 if r == 0 { 2868 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2869 } else { 2870 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2871 } 2872 } 2873 2874 case 11: // br/bl 2875 v := int32(0) 2876 2877 if p.Pcond != nil { 2878 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2879 } 2880 2881 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2882 zRI(op_BRC, 0xF, uint32(v), asm) 2883 } else { 2884 if p.As == ABL { 2885 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2886 } else { 2887 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2888 } 2889 if p.To.Sym != nil { 2890 addcallreloc(ctxt, p.To.Sym, p.To.Offset) 2891 } 2892 } 2893 2894 case 12: 2895 r1 := p.To.Reg 2896 d2 := vregoff(ctxt, &p.From) 2897 b2 := p.From.Reg 2898 if b2 == 0 { 2899 b2 = o.param 2900 } 2901 x2 := p.From.Index 2902 if -DISP20/2 > d2 || d2 >= DISP20/2 { 2903 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 2904 if x2 != 0 { 2905 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 2906 } 2907 x2 = REGTMP 2908 d2 = 0 2909 } 2910 var opx, opxy uint32 2911 switch p.As { 2912 case AADD: 2913 opxy = op_AG 2914 case AADDC: 2915 opxy = op_ALG 2916 case AADDW: 2917 opx = op_A 2918 opxy = op_AY 2919 case AMULLW: 2920 opx = op_MS 2921 opxy = op_MSY 2922 case AMULLD: 2923 opxy = op_MSG 2924 case ASUB: 2925 opxy = op_SG 2926 case ASUBC: 2927 opxy = op_SLG 2928 case ASUBE: 2929 opxy = op_SLBG 2930 case ASUBW: 2931 opx = op_S 2932 opxy = op_SY 2933 case AAND: 2934 opxy = op_NG 2935 case AANDW: 2936 opx = op_N 2937 opxy = op_NY 2938 case AOR: 2939 opxy = op_OG 2940 case AORW: 2941 opx = op_O 2942 opxy = op_OY 2943 case AXOR: 2944 opxy = op_XG 2945 case AXORW: 2946 opx = op_X 2947 opxy = op_XY 2948 } 2949 if opx != 0 && 0 <= d2 && d2 < DISP12 { 2950 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2951 } else { 2952 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm) 2953 } 2954 2955 case 15: // br/bl (reg) 2956 r := p.To.Reg 2957 if p.As == ABCL || p.As == ABL { 2958 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2959 } else { 2960 zRR(op_BCR, 0xF, uint32(r), asm) 2961 } 2962 2963 case 16: // conditional branch 2964 v := int32(0) 2965 if p.Pcond != nil { 2966 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2967 } 2968 mask := branchMask(ctxt, p) 2969 if p.To.Sym == nil && int32(int16(v)) == v { 2970 zRI(op_BRC, mask, uint32(v), asm) 2971 } else { 2972 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2973 } 2974 if p.To.Sym != nil { 2975 addrilreloc(ctxt, p.To.Sym, p.To.Offset) 2976 } 2977 2978 case 17: // move on condition 2979 m3 := branchMask(ctxt, p) 2980 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2981 2982 case 18: // br/bl reg 2983 if p.As == ABL { 2984 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2985 } else { 2986 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2987 } 2988 2989 case 19: // mov $sym+n(SB) reg 2990 d := vregoff(ctxt, &p.From) 2991 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2992 if d&1 != 0 { 2993 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2994 d -= 1 2995 } 2996 addrilreloc(ctxt, p.From.Sym, d) 2997 2998 case 21: // subtract $constant [reg] reg 2999 v := vregoff(ctxt, &p.From) 3000 r := p.Reg 3001 if r == 0 { 3002 r = p.To.Reg 3003 } 3004 switch p.As { 3005 case ASUB: 3006 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm) 3007 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm) 3008 case ASUBC: 3009 if r != p.To.Reg { 3010 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3011 } 3012 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm) 3013 case ASUBW: 3014 if r != p.To.Reg { 3015 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3016 } 3017 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm) 3018 } 3019 3020 case 22: // add/multiply $constant [reg] reg 3021 v := vregoff(ctxt, &p.From) 3022 r := p.Reg 3023 if r == 0 { 3024 r = p.To.Reg 3025 } 3026 var opri, opril, oprie uint32 3027 switch p.As { 3028 case AADD: 3029 opri = op_AGHI 3030 opril = op_AGFI 3031 oprie = op_AGHIK 3032 case AADDC: 3033 opril = op_ALGFI 3034 oprie = op_ALGHSIK 3035 case AADDW: 3036 opri = op_AHI 3037 opril = op_AFI 3038 oprie = op_AHIK 3039 case AMULLW: 3040 opri = op_MHI 3041 opril = op_MSFI 3042 case AMULLD: 3043 opri = op_MGHI 3044 opril = op_MSGFI 3045 } 3046 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) { 3047 switch p.As { 3048 case AADD, AADDC, AMULLD: 3049 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 3050 case AADDW, AMULLW: 3051 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm) 3052 } 3053 r = p.To.Reg 3054 } 3055 if r == p.To.Reg { 3056 if opri != 0 && int64(int16(v)) == v { 3057 zRI(opri, uint32(p.To.Reg), uint32(v), asm) 3058 } else { 3059 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm) 3060 } 3061 } else { 3062 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 3063 } 3064 3065 case 23: // 64-bit logical op $constant reg 3066 // TODO(mundaym): merge with case 24. 3067 v := vregoff(ctxt, &p.From) 3068 switch p.As { 3069 default: 3070 ctxt.Diag("%v is not supported", p) 3071 case AAND: 3072 if v >= 0 { // needs zero extend 3073 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3074 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 3075 } else if int64(int16(v)) == v { 3076 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3077 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 3078 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3079 } 3080 case AOR: 3081 if int64(uint32(v)) != v { // needs sign extend 3082 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3083 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 3084 } else if int64(uint16(v)) == v { 3085 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3086 } else { 3087 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3088 } 3089 case AXOR: 3090 if int64(uint32(v)) != v { // needs sign extend 3091 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3092 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 3093 } else { 3094 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3095 } 3096 } 3097 3098 case 24: // 32-bit logical op $constant reg 3099 v := vregoff(ctxt, &p.From) 3100 switch p.As { 3101 case AANDW: 3102 if uint32(v&0xffff0000) == 0xffff0000 { 3103 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 3104 } else if uint32(v&0x0000ffff) == 0x0000ffff { 3105 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3106 } else { 3107 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 3108 } 3109 case AORW: 3110 if uint32(v&0xffff0000) == 0 { 3111 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 3112 } else if uint32(v&0x0000ffff) == 0 { 3113 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm) 3114 } else { 3115 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 3116 } 3117 case AXORW: 3118 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 3119 } 3120 3121 case 26: // MOVD $offset(base)(index), reg 3122 v := regoff(ctxt, &p.From) 3123 r := p.From.Reg 3124 if r == 0 { 3125 r = o.param 3126 } 3127 i := p.From.Index 3128 if v >= 0 && v < DISP12 { 3129 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3130 } else if v >= -DISP20/2 && v < DISP20/2 { 3131 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm) 3132 } else { 3133 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3134 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm) 3135 } 3136 3137 case 31: // dword 3138 wd := uint64(vregoff(ctxt, &p.From)) 3139 *asm = append(*asm, 3140 uint8(wd>>56), 3141 uint8(wd>>48), 3142 uint8(wd>>40), 3143 uint8(wd>>32), 3144 uint8(wd>>24), 3145 uint8(wd>>16), 3146 uint8(wd>>8), 3147 uint8(wd)) 3148 3149 case 32: // fmul freg [freg] freg 3150 r := int(p.Reg) 3151 if r == 0 { 3152 r = int(p.To.Reg) 3153 } 3154 3155 var opcode uint32 3156 3157 switch p.As { 3158 default: 3159 ctxt.Diag("invalid opcode") 3160 case AFMUL: 3161 opcode = op_MDBR 3162 case AFMULS: 3163 opcode = op_MEEBR 3164 } 3165 3166 if r == int(p.To.Reg) { 3167 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3168 } else if p.From.Reg == p.To.Reg { 3169 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3170 } else { 3171 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 3172 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3173 } 3174 3175 case 33: // float op [freg] freg 3176 r := p.From.Reg 3177 if oclass(&p.From) == C_NONE { 3178 r = p.To.Reg 3179 } 3180 var opcode uint32 3181 switch p.As { 3182 default: 3183 case AFABS: 3184 opcode = op_LPDBR 3185 case AFNABS: 3186 opcode = op_LNDBR 3187 case AFNEG: 3188 opcode = op_LCDFR 3189 case AFNEGS: 3190 opcode = op_LCEBR 3191 case ALEDBR: 3192 opcode = op_LEDBR 3193 case ALDEBR: 3194 opcode = op_LDEBR 3195 case AFSQRT: 3196 opcode = op_SQDBR 3197 case AFSQRTS: 3198 opcode = op_SQEBR 3199 } 3200 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3201 3202 case 34: // float multiply-add freg freg freg freg 3203 var opcode uint32 3204 3205 switch p.As { 3206 default: 3207 ctxt.Diag("invalid opcode") 3208 case AFMADD: 3209 opcode = op_MADBR 3210 case AFMADDS: 3211 opcode = op_MAEBR 3212 case AFMSUB: 3213 opcode = op_MSDBR 3214 case AFMSUBS: 3215 opcode = op_MSEBR 3216 case AFNMADD: 3217 opcode = op_MADBR 3218 case AFNMADDS: 3219 opcode = op_MAEBR 3220 case AFNMSUB: 3221 opcode = op_MSDBR 3222 case AFNMSUBS: 3223 opcode = op_MSEBR 3224 } 3225 3226 zRR(op_LDR, uint32(p.To.Reg), uint32(p.Reg), asm) 3227 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From3.Reg), asm) 3228 3229 if p.As == AFNMADD || p.As == AFNMADDS || p.As == AFNMSUB || p.As == AFNMSUBS { 3230 zRRE(op_LCDFR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 3231 } 3232 3233 case 35: // mov reg mem (no relocation) 3234 d2 := regoff(ctxt, &p.To) 3235 b2 := p.To.Reg 3236 if b2 == 0 { 3237 b2 = o.param 3238 } 3239 x2 := p.To.Index 3240 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3241 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3242 if x2 != 0 { 3243 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3244 } 3245 x2 = REGTMP 3246 d2 = 0 3247 } 3248 zRXY(zopstore(ctxt, p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3249 3250 case 36: // mov mem reg (no relocation) 3251 d2 := regoff(ctxt, &p.From) 3252 b2 := p.From.Reg 3253 if b2 == 0 { 3254 b2 = o.param 3255 } 3256 x2 := p.From.Index 3257 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3258 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3259 if x2 != 0 { 3260 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3261 } 3262 x2 = REGTMP 3263 d2 = 0 3264 } 3265 zRXY(zopload(ctxt, p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3266 3267 case 40: // word/byte 3268 wd := uint32(regoff(ctxt, &p.From)) 3269 if p.As == AWORD { //WORD 3270 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3271 } else { //BYTE 3272 *asm = append(*asm, uint8(wd)) 3273 } 3274 3275 case 47: // negate [reg] reg 3276 r := p.From.Reg 3277 if r == 0 { 3278 r = p.To.Reg 3279 } 3280 switch p.As { 3281 case ANEG: 3282 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3283 case ANEGW: 3284 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm) 3285 } 3286 3287 case 48: // floating-point round to integer 3288 m3 := vregoff(ctxt, &p.From) 3289 if 0 > m3 || m3 > 7 { 3290 ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3291 } 3292 var opcode uint32 3293 switch p.As { 3294 case AFIEBR: 3295 opcode = op_FIEBR 3296 case AFIDBR: 3297 opcode = op_FIDBR 3298 } 3299 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3300 3301 case 67: // fmov $0 freg 3302 var opcode uint32 3303 switch p.As { 3304 case AFMOVS: 3305 opcode = op_LZER 3306 case AFMOVD: 3307 opcode = op_LZDR 3308 } 3309 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3310 3311 case 68: // movw areg reg 3312 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3313 3314 case 69: // movw reg areg 3315 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3316 3317 case 70: // cmp reg reg 3318 if p.As == ACMPW || p.As == ACMPWU { 3319 zRR(zoprr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3320 } else { 3321 zRRE(zoprre(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3322 } 3323 3324 case 71: // cmp reg $constant 3325 v := vregoff(ctxt, &p.To) 3326 switch p.As { 3327 case ACMP, ACMPW: 3328 if int64(int32(v)) != v { 3329 ctxt.Diag("%v overflows an int32", v) 3330 } 3331 case ACMPU, ACMPWU: 3332 if int64(uint32(v)) != v { 3333 ctxt.Diag("%v overflows a uint32", v) 3334 } 3335 } 3336 if p.As == ACMP && int64(int16(v)) == v { 3337 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm) 3338 } else if p.As == ACMPW && int64(int16(v)) == v { 3339 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm) 3340 } else { 3341 zRIL(_a, zopril(ctxt, p.As), uint32(p.From.Reg), uint32(v), asm) 3342 } 3343 3344 case 72: // mov $constant mem 3345 v := regoff(ctxt, &p.From) 3346 d := regoff(ctxt, &p.To) 3347 r := p.To.Reg 3348 x := p.To.Index 3349 if r == 0 { 3350 r = o.param 3351 } 3352 if int32(int16(v)) == v && x == 0 { 3353 if d < 0 || d >= DISP12 { 3354 if r == REGTMP || r == REGTMP2 { 3355 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3356 } else { 3357 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3358 zRRE(op_AGR, REGTMP, uint32(r), asm) 3359 r = REGTMP 3360 } 3361 d = 0 3362 } 3363 var opcode uint32 3364 switch p.As { 3365 case AMOVD: 3366 opcode = op_MVGHI 3367 case AMOVW, AMOVWZ: 3368 opcode = op_MVHI 3369 case AMOVH, AMOVHZ: 3370 opcode = op_MVHHI 3371 case AMOVB, AMOVBZ: 3372 opcode = op_MVI 3373 } 3374 if opcode == op_MVI { 3375 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3376 } else { 3377 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3378 } 3379 } else { 3380 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3381 if d < -DISP20/2 || d >= DISP20/2 { 3382 if r == REGTMP { 3383 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3384 } else { 3385 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3386 if x != 0 { 3387 zRRE(op_AGR, REGTMP, uint32(x), asm) 3388 } 3389 x = REGTMP 3390 } 3391 d = 0 3392 } 3393 zRXY(zopstore(ctxt, p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3394 } 3395 3396 case 73: // mov $constant addr (including relocation) 3397 v := regoff(ctxt, &p.From) 3398 d := regoff(ctxt, &p.To) 3399 a := uint32(0) 3400 if d&1 != 0 { 3401 d -= 1 3402 a = 1 3403 } 3404 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3405 addrilreloc(ctxt, p.To.Sym, int64(d)) 3406 if int32(int16(v)) == v { 3407 var opcode uint32 3408 switch p.As { 3409 case AMOVD: 3410 opcode = op_MVGHI 3411 case AMOVW, AMOVWZ: 3412 opcode = op_MVHI 3413 case AMOVH, AMOVHZ: 3414 opcode = op_MVHHI 3415 case AMOVB, AMOVBZ: 3416 opcode = op_MVI 3417 } 3418 if opcode == op_MVI { 3419 zSI(opcode, uint32(v), REGTMP, a, asm) 3420 } else { 3421 zSIL(opcode, REGTMP, a, uint32(v), asm) 3422 } 3423 } else { 3424 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3425 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3426 } 3427 3428 case 74: // mov reg addr (including relocation) 3429 i2 := regoff(ctxt, &p.To) 3430 switch p.As { 3431 case AMOVD: 3432 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3433 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3434 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3435 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3436 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3437 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3438 zRIL(_b, op_LARL, REGTMP, 0, asm) 3439 adj := uint32(0) // adjustment needed for odd addresses 3440 if i2&1 != 0 { 3441 i2 -= 1 3442 adj = 1 3443 } 3444 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3445 case AFMOVD: 3446 zRIL(_b, op_LARL, REGTMP, 0, asm) 3447 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3448 case AFMOVS: 3449 zRIL(_b, op_LARL, REGTMP, 0, asm) 3450 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3451 } 3452 addrilreloc(ctxt, p.To.Sym, int64(i2)) 3453 3454 case 75: // mov addr reg (including relocation) 3455 i2 := regoff(ctxt, &p.From) 3456 switch p.As { 3457 case AMOVD: 3458 if i2&1 != 0 { 3459 zRIL(_b, op_LARL, REGTMP, 0, asm) 3460 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3461 i2 -= 1 3462 } else { 3463 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3464 } 3465 case AMOVW: 3466 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3467 case AMOVWZ: 3468 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3469 case AMOVH: 3470 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3471 case AMOVHZ: 3472 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3473 case AMOVB, AMOVBZ: 3474 zRIL(_b, op_LARL, REGTMP, 0, asm) 3475 adj := uint32(0) // adjustment needed for odd addresses 3476 if i2&1 != 0 { 3477 i2 -= 1 3478 adj = 1 3479 } 3480 switch p.As { 3481 case AMOVB: 3482 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3483 case AMOVBZ: 3484 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3485 } 3486 case AFMOVD: 3487 zRIL(_a, op_LARL, REGTMP, 0, asm) 3488 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3489 case AFMOVS: 3490 zRIL(_a, op_LARL, REGTMP, 0, asm) 3491 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3492 } 3493 addrilreloc(ctxt, p.From.Sym, int64(i2)) 3494 3495 case 77: // syscall $constant 3496 if p.From.Offset > 255 || p.From.Offset < 1 { 3497 ctxt.Diag("illegal system call; system call number out of range: %v", p) 3498 zE(op_TRAP2, asm) // trap always 3499 } else { 3500 zI(op_SVC, uint32(p.From.Offset), asm) 3501 } 3502 3503 case 78: // undef 3504 // "An instruction consisting entirely of binary 0s is guaranteed 3505 // always to be an illegal instruction." 3506 *asm = append(*asm, 0, 0, 0, 0) 3507 3508 case 79: // compare and swap reg reg reg 3509 v := regoff(ctxt, &p.To) 3510 if v < 0 { 3511 v = 0 3512 } 3513 if p.As == ACS { 3514 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3515 } else if p.As == ACSG { 3516 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3517 } 3518 3519 case 81: // sync 3520 zRR(op_BCR, 0xE, 0, asm) 3521 3522 case 82: // fixed to float conversion 3523 var opcode uint32 3524 switch p.As { 3525 default: 3526 log.Fatalf("unexpected opcode %v", p.As) 3527 case ACEFBRA: 3528 opcode = op_CEFBRA 3529 case ACDFBRA: 3530 opcode = op_CDFBRA 3531 case ACEGBRA: 3532 opcode = op_CEGBRA 3533 case ACDGBRA: 3534 opcode = op_CDGBRA 3535 case ACELFBR: 3536 opcode = op_CELFBR 3537 case ACDLFBR: 3538 opcode = op_CDLFBR 3539 case ACELGBR: 3540 opcode = op_CELGBR 3541 case ACDLGBR: 3542 opcode = op_CDLGBR 3543 } 3544 // set immediate operand M3 to 0 to use the default BFP rounding mode 3545 // (usually round to nearest, ties to even) 3546 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3547 // M4 is reserved and must be 0 3548 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3549 3550 case 83: // float to fixed conversion 3551 var opcode uint32 3552 switch p.As { 3553 default: 3554 log.Fatalf("unexpected opcode %v", p.As) 3555 case ACFEBRA: 3556 opcode = op_CFEBRA 3557 case ACFDBRA: 3558 opcode = op_CFDBRA 3559 case ACGEBRA: 3560 opcode = op_CGEBRA 3561 case ACGDBRA: 3562 opcode = op_CGDBRA 3563 case ACLFEBR: 3564 opcode = op_CLFEBR 3565 case ACLFDBR: 3566 opcode = op_CLFDBR 3567 case ACLGEBR: 3568 opcode = op_CLGEBR 3569 case ACLGDBR: 3570 opcode = op_CLGDBR 3571 } 3572 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3573 // M4 is reserved and must be 0 3574 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3575 3576 case 84: // storage-and-storage operations $length mem mem (length in From3) 3577 l := regoff(ctxt, p.From3) 3578 if l < 1 || l > 256 { 3579 ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3580 } 3581 if p.From.Index != 0 || p.To.Index != 0 { 3582 ctxt.Diag("cannot use index reg") 3583 } 3584 b1 := p.To.Reg 3585 b2 := p.From.Reg 3586 if b1 == 0 { 3587 b1 = o.param 3588 } 3589 if b2 == 0 { 3590 b2 = o.param 3591 } 3592 d1 := regoff(ctxt, &p.To) 3593 d2 := regoff(ctxt, &p.From) 3594 if d1 < 0 || d1 >= DISP12 { 3595 if b2 == REGTMP { 3596 ctxt.Diag("REGTMP conflict") 3597 } 3598 if b1 != REGTMP { 3599 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3600 } 3601 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3602 if d1 == d2 && b1 == b2 { 3603 d2 = 0 3604 b2 = REGTMP 3605 } 3606 d1 = 0 3607 b1 = REGTMP 3608 } 3609 if d2 < 0 || d2 >= DISP12 { 3610 if b1 == REGTMP2 { 3611 ctxt.Diag("REGTMP2 conflict") 3612 } 3613 if b2 != REGTMP2 { 3614 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3615 } 3616 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3617 d2 = 0 3618 b2 = REGTMP2 3619 } 3620 var opcode uint32 3621 switch p.As { 3622 default: 3623 ctxt.Diag("unexpected opcode %v", p.As) 3624 case AMVC: 3625 opcode = op_MVC 3626 case ACLC: 3627 opcode = op_CLC 3628 // swap operand order for CLC so that it matches CMP 3629 b1, b2 = b2, b1 3630 d1, d2 = d2, d1 3631 case AXC: 3632 opcode = op_XC 3633 case AOC: 3634 opcode = op_OC 3635 case ANC: 3636 opcode = op_NC 3637 } 3638 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3639 3640 case 85: // load address relative long 3641 v := regoff(ctxt, &p.From) 3642 if p.From.Sym == nil { 3643 if (v & 1) != 0 { 3644 ctxt.Diag("cannot use LARL with odd offset: %v", v) 3645 } 3646 } else { 3647 addrilreloc(ctxt, p.From.Sym, int64(v)) 3648 v = 0 3649 } 3650 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3651 3652 case 86: // load address 3653 d := vregoff(ctxt, &p.From) 3654 x := p.From.Index 3655 b := p.From.Reg 3656 if b == 0 { 3657 b = o.param 3658 } 3659 switch p.As { 3660 case ALA: 3661 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3662 case ALAY: 3663 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3664 } 3665 3666 case 87: // execute relative long 3667 v := vregoff(ctxt, &p.From) 3668 if p.From.Sym == nil { 3669 if v&1 != 0 { 3670 ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3671 } 3672 } else { 3673 addrilreloc(ctxt, p.From.Sym, v) 3674 v = 0 3675 } 3676 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3677 3678 case 88: // store clock 3679 var opcode uint32 3680 switch p.As { 3681 case ASTCK: 3682 opcode = op_STCK 3683 case ASTCKC: 3684 opcode = op_STCKC 3685 case ASTCKE: 3686 opcode = op_STCKE 3687 case ASTCKF: 3688 opcode = op_STCKF 3689 } 3690 v := vregoff(ctxt, &p.To) 3691 r := int(p.To.Reg) 3692 if r == 0 { 3693 r = int(o.param) 3694 } 3695 zS(opcode, uint32(r), uint32(v), asm) 3696 3697 case 89: // compare and branch reg reg 3698 var v int32 3699 if p.Pcond != nil { 3700 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3701 } 3702 var opcode, opcode2 uint32 3703 switch p.As { 3704 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3705 opcode = op_CGRJ 3706 opcode2 = op_CGR 3707 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3708 opcode = op_CLGRJ 3709 opcode2 = op_CLGR 3710 } 3711 mask := branchMask(ctxt, p) 3712 if int32(int16(v)) != v { 3713 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3714 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3715 } else { 3716 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3717 } 3718 3719 case 90: // compare and branch reg $constant 3720 var v int32 3721 if p.Pcond != nil { 3722 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3723 } 3724 var opcode, opcode2 uint32 3725 switch p.As { 3726 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3727 opcode = op_CGIJ 3728 opcode2 = op_CGFI 3729 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3730 opcode = op_CLGIJ 3731 opcode2 = op_CLGFI 3732 } 3733 mask := branchMask(ctxt, p) 3734 if int32(int16(v)) != v { 3735 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(regoff(ctxt, p.From3)), asm) 3736 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3737 } else { 3738 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(regoff(ctxt, p.From3)), asm) 3739 } 3740 3741 case 93: // GOT lookup 3742 v := vregoff(ctxt, &p.To) 3743 if v != 0 { 3744 ctxt.Diag("invalid offset against GOT slot %v", p) 3745 } 3746 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3747 rel := obj.Addrel(ctxt.Cursym) 3748 rel.Off = int32(ctxt.Pc + 2) 3749 rel.Siz = 4 3750 rel.Sym = p.From.Sym 3751 rel.Type = obj.R_GOTPCREL 3752 rel.Add = 2 + int64(rel.Siz) 3753 3754 case 94: // TLS local exec model 3755 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3756 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3757 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3758 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3759 rel := obj.Addrel(ctxt.Cursym) 3760 rel.Off = int32(ctxt.Pc + sizeRIL + sizeRXY + sizeRI) 3761 rel.Siz = 8 3762 rel.Sym = p.From.Sym 3763 rel.Type = obj.R_TLS_LE 3764 rel.Add = 0 3765 3766 case 95: // TLS initial exec model 3767 // Assembly | Relocation symbol | Done Here? 3768 // -------------------------------------------------------------- 3769 // ear %r11, %a0 | | 3770 // sllg %r11, %r11, 32 | | 3771 // ear %r11, %a1 | | 3772 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3773 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3774 // la %r10, 0(%r10, %r11) | | 3775 // -------------------------------------------------------------- 3776 3777 // R_390_TLS_IEENT 3778 zRIL(_b, op_LARL, REGTMP, 0, asm) 3779 ieent := obj.Addrel(ctxt.Cursym) 3780 ieent.Off = int32(ctxt.Pc + 2) 3781 ieent.Siz = 4 3782 ieent.Sym = p.From.Sym 3783 ieent.Type = obj.R_TLS_IE 3784 ieent.Add = 2 + int64(ieent.Siz) 3785 3786 // R_390_TLS_LOAD 3787 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3788 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3789 // not strictly required but might allow the linker to optimize 3790 3791 case 96: // clear macro 3792 length := vregoff(ctxt, &p.From) 3793 offset := vregoff(ctxt, &p.To) 3794 reg := p.To.Reg 3795 if reg == 0 { 3796 reg = o.param 3797 } 3798 if length <= 0 { 3799 ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3800 } 3801 for length > 0 { 3802 if offset < 0 || offset >= DISP12 { 3803 if offset >= -DISP20/2 && offset < DISP20/2 { 3804 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3805 } else { 3806 if reg != REGTMP { 3807 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3808 } 3809 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3810 } 3811 reg = REGTMP 3812 offset = 0 3813 } 3814 size := length 3815 if size > 256 { 3816 size = 256 3817 } 3818 3819 switch size { 3820 case 1: 3821 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3822 case 2: 3823 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3824 case 4: 3825 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3826 case 8: 3827 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3828 default: 3829 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3830 } 3831 3832 length -= size 3833 offset += size 3834 } 3835 3836 case 97: // store multiple 3837 rstart := p.From.Reg 3838 rend := p.Reg 3839 offset := regoff(ctxt, &p.To) 3840 reg := p.To.Reg 3841 if reg == 0 { 3842 reg = o.param 3843 } 3844 if offset < -DISP20/2 || offset >= DISP20/2 { 3845 if reg != REGTMP { 3846 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3847 } 3848 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3849 reg = REGTMP 3850 offset = 0 3851 } 3852 switch p.As { 3853 case ASTMY: 3854 if offset >= 0 && offset < DISP12 { 3855 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3856 } else { 3857 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3858 } 3859 case ASTMG: 3860 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3861 } 3862 3863 case 98: // load multiple 3864 rstart := p.Reg 3865 rend := p.To.Reg 3866 offset := regoff(ctxt, &p.From) 3867 reg := p.From.Reg 3868 if reg == 0 { 3869 reg = o.param 3870 } 3871 if offset < -DISP20/2 || offset >= DISP20/2 { 3872 if reg != REGTMP { 3873 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3874 } 3875 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3876 reg = REGTMP 3877 offset = 0 3878 } 3879 switch p.As { 3880 case ALMY: 3881 if offset >= 0 && offset < DISP12 { 3882 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3883 } else { 3884 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3885 } 3886 case ALMG: 3887 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3888 } 3889 3890 case 99: // interlocked load and op 3891 if p.To.Index != 0 { 3892 ctxt.Diag("cannot use indexed address") 3893 } 3894 offset := regoff(ctxt, &p.To) 3895 if offset < -DISP20/2 || offset >= DISP20/2 { 3896 ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3897 } 3898 var opcode uint32 3899 switch p.As { 3900 case ALAA: 3901 opcode = op_LAA 3902 case ALAAG: 3903 opcode = op_LAAG 3904 case ALAAL: 3905 opcode = op_LAAL 3906 case ALAALG: 3907 opcode = op_LAALG 3908 case ALAN: 3909 opcode = op_LAN 3910 case ALANG: 3911 opcode = op_LANG 3912 case ALAX: 3913 opcode = op_LAX 3914 case ALAXG: 3915 opcode = op_LAXG 3916 case ALAO: 3917 opcode = op_LAO 3918 case ALAOG: 3919 opcode = op_LAOG 3920 } 3921 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3922 3923 case 100: // VRX STORE 3924 op, m3, _ := vop(p.As) 3925 if p.From3 != nil { 3926 m3 = uint32(vregoff(ctxt, p.From3)) 3927 } 3928 b2 := p.To.Reg 3929 if b2 == 0 { 3930 b2 = o.param 3931 } 3932 d2 := uint32(vregoff(ctxt, &p.To)) 3933 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3934 3935 case 101: // VRX LOAD 3936 op, m3, _ := vop(p.As) 3937 if p.From3 != nil { 3938 m3 = uint32(vregoff(ctxt, p.From3)) 3939 } 3940 b2 := p.From.Reg 3941 if b2 == 0 { 3942 b2 = o.param 3943 } 3944 d2 := uint32(vregoff(ctxt, &p.From)) 3945 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3946 3947 case 102: // VRV SCATTER 3948 op, m3, _ := vop(p.As) 3949 if p.From3 != nil { 3950 m3 = uint32(vregoff(ctxt, p.From3)) 3951 } 3952 b2 := p.To.Reg 3953 if b2 == 0 { 3954 b2 = o.param 3955 } 3956 d2 := uint32(vregoff(ctxt, &p.To)) 3957 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3958 3959 case 103: // VRV GATHER 3960 op, m3, _ := vop(p.As) 3961 if p.From3 != nil { 3962 m3 = uint32(vregoff(ctxt, p.From3)) 3963 } 3964 b2 := p.From.Reg 3965 if b2 == 0 { 3966 b2 = o.param 3967 } 3968 d2 := uint32(vregoff(ctxt, &p.From)) 3969 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3970 3971 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3972 op, m4, _ := vop(p.As) 3973 fr := p.Reg 3974 if fr == 0 { 3975 fr = p.To.Reg 3976 } 3977 bits := uint32(vregoff(ctxt, &p.From)) 3978 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3979 3980 case 105: // VRS STORE MULTIPLE 3981 op, _, _ := vop(p.As) 3982 offset := uint32(vregoff(ctxt, &p.To)) 3983 reg := p.To.Reg 3984 if reg == 0 { 3985 reg = o.param 3986 } 3987 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3988 3989 case 106: // VRS LOAD MULTIPLE 3990 op, _, _ := vop(p.As) 3991 offset := uint32(vregoff(ctxt, &p.From)) 3992 reg := p.From.Reg 3993 if reg == 0 { 3994 reg = o.param 3995 } 3996 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3997 3998 case 107: // VRS STORE WITH LENGTH 3999 op, _, _ := vop(p.As) 4000 offset := uint32(vregoff(ctxt, &p.To)) 4001 reg := p.To.Reg 4002 if reg == 0 { 4003 reg = o.param 4004 } 4005 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 4006 4007 case 108: // VRS LOAD WITH LENGTH 4008 op, _, _ := vop(p.As) 4009 offset := uint32(vregoff(ctxt, &p.From)) 4010 reg := p.From.Reg 4011 if reg == 0 { 4012 reg = o.param 4013 } 4014 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 4015 4016 case 109: // VRI-a 4017 op, _, _ := vop(p.As) 4018 i2 := uint32(vregoff(ctxt, &p.From)) 4019 switch p.As { 4020 case AVZERO: 4021 i2 = 0 4022 case AVONE: 4023 i2 = 0xffff 4024 } 4025 m3 := uint32(0) 4026 if p.From3 != nil { 4027 m3 = uint32(vregoff(ctxt, p.From3)) 4028 } 4029 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 4030 4031 case 110: 4032 op, m4, _ := vop(p.As) 4033 i2 := uint32(vregoff(ctxt, p.From3)) 4034 i3 := uint32(vregoff(ctxt, &p.From)) 4035 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 4036 4037 case 111: 4038 op, m4, _ := vop(p.As) 4039 i2 := uint32(vregoff(ctxt, &p.From)) 4040 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 4041 4042 case 112: 4043 op, m5, _ := vop(p.As) 4044 i4 := uint32(vregoff(ctxt, p.From3)) 4045 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm) 4046 4047 case 113: 4048 op, m4, _ := vop(p.As) 4049 m5 := singleElementMask(p.As) 4050 i3 := uint32(vregoff(ctxt, &p.From)) 4051 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 4052 4053 case 114: // VRR-a 4054 op, m3, m5 := vop(p.As) 4055 m4 := singleElementMask(p.As) 4056 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4057 4058 case 115: // VRR-a COMPARE 4059 op, m3, m5 := vop(p.As) 4060 m4 := singleElementMask(p.As) 4061 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4062 4063 case 116: // VRR-a 4064 4065 case 117: // VRR-b 4066 op, m4, m5 := vop(p.As) 4067 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4068 4069 case 118: // VRR-c 4070 op, m4, m6 := vop(p.As) 4071 m5 := singleElementMask(p.As) 4072 v3 := p.Reg 4073 if v3 == 0 { 4074 v3 = p.To.Reg 4075 } 4076 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4077 4078 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4079 op, m4, m6 := vop(p.As) 4080 m5 := singleElementMask(p.As) 4081 v2 := p.Reg 4082 if v2 == 0 { 4083 v2 = p.To.Reg 4084 } 4085 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4086 4087 case 120: // VRR-d 4088 op, m6, _ := vop(p.As) 4089 m5 := singleElementMask(p.As) 4090 v1 := uint32(p.To.Reg) 4091 v2 := uint32(p.From3.Reg) 4092 v3 := uint32(p.From.Reg) 4093 v4 := uint32(p.Reg) 4094 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4095 4096 case 121: // VRR-e 4097 op, m6, _ := vop(p.As) 4098 m5 := singleElementMask(p.As) 4099 v1 := uint32(p.To.Reg) 4100 v2 := uint32(p.From3.Reg) 4101 v3 := uint32(p.From.Reg) 4102 v4 := uint32(p.Reg) 4103 zVRRe(op, v1, v2, v3, m6, m5, v4, asm) 4104 4105 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4106 op, _, _ := vop(p.As) 4107 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4108 4109 case 123: // VPDI $m4, V2, V3, V1 4110 op, _, _ := vop(p.As) 4111 m4 := regoff(ctxt, p.From3) 4112 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm) 4113 } 4114 } 4115 4116 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 4117 ctxt.Instoffset = 0 4118 if a != nil { 4119 aclass(ctxt, a) 4120 } 4121 return ctxt.Instoffset 4122 } 4123 4124 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 4125 return int32(vregoff(ctxt, a)) 4126 } 4127 4128 // zopload returns the RXY op for the given load 4129 func zopload(ctxt *obj.Link, a obj.As) uint32 { 4130 switch a { 4131 // fixed point load 4132 case AMOVD: 4133 return op_LG 4134 case AMOVW: 4135 return op_LGF 4136 case AMOVWZ: 4137 return op_LLGF 4138 case AMOVH: 4139 return op_LGH 4140 case AMOVHZ: 4141 return op_LLGH 4142 case AMOVB: 4143 return op_LGB 4144 case AMOVBZ: 4145 return op_LLGC 4146 4147 // floating point load 4148 case AFMOVD: 4149 return op_LDY 4150 case AFMOVS: 4151 return op_LEY 4152 4153 // byte reversed load 4154 case AMOVDBR: 4155 return op_LRVG 4156 case AMOVWBR: 4157 return op_LRV 4158 case AMOVHBR: 4159 return op_LRVH 4160 } 4161 4162 ctxt.Diag("unknown store opcode %v", a) 4163 return 0 4164 } 4165 4166 // zopstore returns the RXY op for the given store 4167 func zopstore(ctxt *obj.Link, a obj.As) uint32 { 4168 switch a { 4169 // fixed point store 4170 case AMOVD: 4171 return op_STG 4172 case AMOVW, AMOVWZ: 4173 return op_STY 4174 case AMOVH, AMOVHZ: 4175 return op_STHY 4176 case AMOVB, AMOVBZ: 4177 return op_STCY 4178 4179 // floating point store 4180 case AFMOVD: 4181 return op_STDY 4182 case AFMOVS: 4183 return op_STEY 4184 4185 // byte reversed store 4186 case AMOVDBR: 4187 return op_STRVG 4188 case AMOVWBR: 4189 return op_STRV 4190 case AMOVHBR: 4191 return op_STRVH 4192 } 4193 4194 ctxt.Diag("unknown store opcode %v", a) 4195 return 0 4196 } 4197 4198 // zoprre returns the RRE op for the given a 4199 func zoprre(ctxt *obj.Link, a obj.As) uint32 { 4200 switch a { 4201 case ACMP: 4202 return op_CGR 4203 case ACMPU: 4204 return op_CLGR 4205 case AFCMPO: //ordered 4206 return op_KDBR 4207 case AFCMPU: //unordered 4208 return op_CDBR 4209 case ACEBR: 4210 return op_CEBR 4211 } 4212 ctxt.Diag("unknown rre opcode %v", a) 4213 return 0 4214 } 4215 4216 // zoprr returns the RR op for the given a 4217 func zoprr(ctxt *obj.Link, a obj.As) uint32 { 4218 switch a { 4219 case ACMPW: 4220 return op_CR 4221 case ACMPWU: 4222 return op_CLR 4223 } 4224 ctxt.Diag("unknown rr opcode %v", a) 4225 return 0 4226 } 4227 4228 // zopril returns the RIL op for the given a 4229 func zopril(ctxt *obj.Link, a obj.As) uint32 { 4230 switch a { 4231 case ACMP: 4232 return op_CGFI 4233 case ACMPU: 4234 return op_CLGFI 4235 case ACMPW: 4236 return op_CFI 4237 case ACMPWU: 4238 return op_CLFI 4239 } 4240 ctxt.Diag("unknown ril opcode %v", a) 4241 return 0 4242 } 4243 4244 // z instructions sizes 4245 const ( 4246 sizeE = 2 4247 sizeI = 2 4248 sizeIE = 4 4249 sizeMII = 6 4250 sizeRI = 4 4251 sizeRI1 = 4 4252 sizeRI2 = 4 4253 sizeRI3 = 4 4254 sizeRIE = 6 4255 sizeRIE1 = 6 4256 sizeRIE2 = 6 4257 sizeRIE3 = 6 4258 sizeRIE4 = 6 4259 sizeRIE5 = 6 4260 sizeRIE6 = 6 4261 sizeRIL = 6 4262 sizeRIL1 = 6 4263 sizeRIL2 = 6 4264 sizeRIL3 = 6 4265 sizeRIS = 6 4266 sizeRR = 2 4267 sizeRRD = 4 4268 sizeRRE = 4 4269 sizeRRF = 4 4270 sizeRRF1 = 4 4271 sizeRRF2 = 4 4272 sizeRRF3 = 4 4273 sizeRRF4 = 4 4274 sizeRRF5 = 4 4275 sizeRRR = 2 4276 sizeRRS = 6 4277 sizeRS = 4 4278 sizeRS1 = 4 4279 sizeRS2 = 4 4280 sizeRSI = 4 4281 sizeRSL = 6 4282 sizeRSY = 6 4283 sizeRSY1 = 6 4284 sizeRSY2 = 6 4285 sizeRX = 4 4286 sizeRX1 = 4 4287 sizeRX2 = 4 4288 sizeRXE = 6 4289 sizeRXF = 6 4290 sizeRXY = 6 4291 sizeRXY1 = 6 4292 sizeRXY2 = 6 4293 sizeS = 4 4294 sizeSI = 4 4295 sizeSIL = 6 4296 sizeSIY = 6 4297 sizeSMI = 6 4298 sizeSS = 6 4299 sizeSS1 = 6 4300 sizeSS2 = 6 4301 sizeSS3 = 6 4302 sizeSS4 = 6 4303 sizeSS5 = 6 4304 sizeSS6 = 6 4305 sizeSSE = 6 4306 sizeSSF = 6 4307 ) 4308 4309 // instruction format variations 4310 type form int 4311 4312 const ( 4313 _a form = iota 4314 _b 4315 _c 4316 _d 4317 _e 4318 _f 4319 ) 4320 4321 func zE(op uint32, asm *[]byte) { 4322 *asm = append(*asm, uint8(op>>8), uint8(op)) 4323 } 4324 4325 func zI(op, i1 uint32, asm *[]byte) { 4326 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4327 } 4328 4329 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4330 *asm = append(*asm, 4331 uint8(op>>8), 4332 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4333 uint8(ri2), 4334 uint8(ri3>>16), 4335 uint8(ri3>>8), 4336 uint8(ri3)) 4337 } 4338 4339 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4340 *asm = append(*asm, 4341 uint8(op>>8), 4342 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4343 uint8(i2_ri2>>8), 4344 uint8(i2_ri2)) 4345 } 4346 4347 // Expected argument values for the instruction formats. 4348 // 4349 // Format a1 a2 a3 a4 a5 a6 a7 4350 // ------------------------------------ 4351 // a r1, 0, i2, 0, 0, m3, 0 4352 // b r1, r2, ri4, 0, 0, m3, 0 4353 // c r1, m3, ri4, 0, 0, 0, i2 4354 // d r1, r3, i2, 0, 0, 0, 0 4355 // e r1, r3, ri2, 0, 0, 0, 0 4356 // f r1, r2, 0, i3, i4, 0, i5 4357 // g r1, m3, i2, 0, 0, 0, 0 4358 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4359 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4360 4361 switch f { 4362 default: 4363 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4364 case _f: 4365 *asm = append(*asm, uint8(i3), uint8(i4)) 4366 } 4367 4368 switch f { 4369 case _a, _b: 4370 *asm = append(*asm, uint8(m3)<<4) 4371 default: 4372 *asm = append(*asm, uint8(i2_i5)) 4373 } 4374 4375 *asm = append(*asm, uint8(op)) 4376 } 4377 4378 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4379 if f == _a || f == _b { 4380 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4381 } 4382 *asm = append(*asm, 4383 uint8(op>>8), 4384 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4385 uint8(i2_ri2>>24), 4386 uint8(i2_ri2>>16), 4387 uint8(i2_ri2>>8), 4388 uint8(i2_ri2)) 4389 } 4390 4391 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4392 *asm = append(*asm, 4393 uint8(op>>8), 4394 (uint8(r1)<<4)|uint8(m3&0x0F), 4395 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4396 uint8(d4), 4397 uint8(i2), 4398 uint8(op)) 4399 } 4400 4401 func zRR(op, r1, r2 uint32, asm *[]byte) { 4402 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4403 } 4404 4405 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4406 *asm = append(*asm, 4407 uint8(op>>8), 4408 uint8(op), 4409 uint8(r1)<<4, 4410 (uint8(r3)<<4)|uint8(r2&0x0F)) 4411 } 4412 4413 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4414 *asm = append(*asm, 4415 uint8(op>>8), 4416 uint8(op), 4417 0, 4418 (uint8(r1)<<4)|uint8(r2&0x0F)) 4419 } 4420 4421 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4422 *asm = append(*asm, 4423 uint8(op>>8), 4424 uint8(op), 4425 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4426 (uint8(r1)<<4)|uint8(r2&0x0F)) 4427 } 4428 4429 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4430 *asm = append(*asm, 4431 uint8(op>>8), 4432 (uint8(r1)<<4)|uint8(r2&0x0F), 4433 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4434 uint8(d4), 4435 uint8(m3)<<4, 4436 uint8(op)) 4437 } 4438 4439 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4440 *asm = append(*asm, 4441 uint8(op>>8), 4442 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4443 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4444 uint8(d2)) 4445 } 4446 4447 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4448 *asm = append(*asm, 4449 uint8(op>>8), 4450 (uint8(r1)<<4)|uint8(r3&0x0F), 4451 uint8(ri2>>8), 4452 uint8(ri2)) 4453 } 4454 4455 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4456 *asm = append(*asm, 4457 uint8(op>>8), 4458 uint8(l1), 4459 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4460 uint8(d2), 4461 uint8(op)) 4462 } 4463 4464 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4465 dl2 := uint16(d2) & 0x0FFF 4466 *asm = append(*asm, 4467 uint8(op>>8), 4468 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4469 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4470 uint8(dl2), 4471 uint8(d2>>12), 4472 uint8(op)) 4473 } 4474 4475 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4476 *asm = append(*asm, 4477 uint8(op>>8), 4478 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4479 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4480 uint8(d2)) 4481 } 4482 4483 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4484 *asm = append(*asm, 4485 uint8(op>>8), 4486 (uint8(r1)<<4)|uint8(x2&0x0F), 4487 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4488 uint8(d2), 4489 uint8(m3)<<4, 4490 uint8(op)) 4491 } 4492 4493 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4494 *asm = append(*asm, 4495 uint8(op>>8), 4496 (uint8(r3)<<4)|uint8(x2&0x0F), 4497 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4498 uint8(d2), 4499 uint8(m1)<<4, 4500 uint8(op)) 4501 } 4502 4503 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4504 dl2 := uint16(d2) & 0x0FFF 4505 *asm = append(*asm, 4506 uint8(op>>8), 4507 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4508 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4509 uint8(dl2), 4510 uint8(d2>>12), 4511 uint8(op)) 4512 } 4513 4514 func zS(op, b2, d2 uint32, asm *[]byte) { 4515 *asm = append(*asm, 4516 uint8(op>>8), 4517 uint8(op), 4518 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4519 uint8(d2)) 4520 } 4521 4522 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4523 *asm = append(*asm, 4524 uint8(op>>8), 4525 uint8(i2), 4526 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4527 uint8(d1)) 4528 } 4529 4530 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4531 *asm = append(*asm, 4532 uint8(op>>8), 4533 uint8(op), 4534 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4535 uint8(d1), 4536 uint8(i2>>8), 4537 uint8(i2)) 4538 } 4539 4540 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4541 dl1 := uint16(d1) & 0x0FFF 4542 *asm = append(*asm, 4543 uint8(op>>8), 4544 uint8(i2), 4545 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4546 uint8(dl1), 4547 uint8(d1>>12), 4548 uint8(op)) 4549 } 4550 4551 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4552 *asm = append(*asm, 4553 uint8(op>>8), 4554 uint8(m1)<<4, 4555 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4556 uint8(d3), 4557 uint8(ri2>>8), 4558 uint8(ri2)) 4559 } 4560 4561 // Expected argument values for the instruction formats. 4562 // 4563 // Format a1 a2 a3 a4 a5 a6 4564 // ------------------------------- 4565 // a l1, 0, b1, d1, b2, d2 4566 // b l1, l2, b1, d1, b2, d2 4567 // c l1, i3, b1, d1, b2, d2 4568 // d r1, r3, b1, d1, b2, d2 4569 // e r1, r3, b2, d2, b4, d4 4570 // f 0, l2, b1, d1, b2, d2 4571 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4572 *asm = append(*asm, uint8(op>>8)) 4573 4574 switch f { 4575 case _a: 4576 *asm = append(*asm, uint8(l1_r1)) 4577 case _b, _c, _d, _e: 4578 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4579 case _f: 4580 *asm = append(*asm, uint8(l2_i3_r3)) 4581 } 4582 4583 *asm = append(*asm, 4584 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4585 uint8(d1_d2), 4586 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4587 uint8(d2_d4)) 4588 } 4589 4590 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4591 *asm = append(*asm, 4592 uint8(op>>8), 4593 uint8(op), 4594 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4595 uint8(d1), 4596 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4597 uint8(d2)) 4598 } 4599 4600 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4601 *asm = append(*asm, 4602 uint8(op>>8), 4603 (uint8(r3)<<4)|(uint8(op)&0x0F), 4604 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4605 uint8(d1), 4606 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4607 uint8(d2)) 4608 } 4609 4610 func rxb(va, vb, vc, vd uint32) uint8 { 4611 mask := uint8(0) 4612 if va >= REG_V16 && va <= REG_V31 { 4613 mask |= 0x8 4614 } 4615 if vb >= REG_V16 && vb <= REG_V31 { 4616 mask |= 0x4 4617 } 4618 if vc >= REG_V16 && vc <= REG_V31 { 4619 mask |= 0x2 4620 } 4621 if vd >= REG_V16 && vd <= REG_V31 { 4622 mask |= 0x1 4623 } 4624 return mask 4625 } 4626 4627 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4628 *asm = append(*asm, 4629 uint8(op>>8), 4630 (uint8(v1)<<4)|(uint8(x2)&0xf), 4631 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4632 uint8(d2), 4633 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4634 uint8(op)) 4635 } 4636 4637 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4638 *asm = append(*asm, 4639 uint8(op>>8), 4640 (uint8(v1)<<4)|(uint8(v2)&0xf), 4641 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4642 uint8(d2), 4643 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4644 uint8(op)) 4645 } 4646 4647 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4648 *asm = append(*asm, 4649 uint8(op>>8), 4650 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4651 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4652 uint8(d2), 4653 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4654 uint8(op)) 4655 } 4656 4657 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4658 *asm = append(*asm, 4659 uint8(op>>8), 4660 (uint8(v1)<<4)|(uint8(v2)&0xf), 4661 0, 4662 (uint8(m5)<<4)|(uint8(m4)&0xf), 4663 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4664 uint8(op)) 4665 } 4666 4667 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4668 *asm = append(*asm, 4669 uint8(op>>8), 4670 (uint8(v1)<<4)|(uint8(v2)&0xf), 4671 uint8(v3)<<4, 4672 uint8(m5)<<4, 4673 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4674 uint8(op)) 4675 } 4676 4677 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4678 *asm = append(*asm, 4679 uint8(op>>8), 4680 (uint8(v1)<<4)|(uint8(v2)&0xf), 4681 uint8(v3)<<4, 4682 (uint8(m6)<<4)|(uint8(m5)&0xf), 4683 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4684 uint8(op)) 4685 } 4686 4687 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4688 *asm = append(*asm, 4689 uint8(op>>8), 4690 (uint8(v1)<<4)|(uint8(v2)&0xf), 4691 (uint8(v3)<<4)|(uint8(m5)&0xf), 4692 uint8(m6)<<4, 4693 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4694 uint8(op)) 4695 } 4696 4697 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4698 *asm = append(*asm, 4699 uint8(op>>8), 4700 (uint8(v1)<<4)|(uint8(v2)&0xf), 4701 (uint8(v3)<<4)|(uint8(m6)&0xf), 4702 uint8(m5), 4703 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4704 uint8(op)) 4705 } 4706 4707 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4708 *asm = append(*asm, 4709 uint8(op>>8), 4710 (uint8(v1)<<4)|(uint8(r2)&0xf), 4711 uint8(r3)<<4, 4712 0, 4713 rxb(v1, 0, 0, 0), 4714 uint8(op)) 4715 } 4716 4717 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4718 *asm = append(*asm, 4719 uint8(op>>8), 4720 uint8(v1)<<4, 4721 uint8(i2>>8), 4722 uint8(i2), 4723 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4724 uint8(op)) 4725 } 4726 4727 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4728 *asm = append(*asm, 4729 uint8(op>>8), 4730 uint8(v1)<<4, 4731 uint8(i2), 4732 uint8(i3), 4733 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4734 uint8(op)) 4735 } 4736 4737 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4738 *asm = append(*asm, 4739 uint8(op>>8), 4740 (uint8(v1)<<4)|(uint8(v3)&0xf), 4741 uint8(i2>>8), 4742 uint8(i2), 4743 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4744 uint8(op)) 4745 } 4746 4747 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4748 *asm = append(*asm, 4749 uint8(op>>8), 4750 (uint8(v1)<<4)|(uint8(v2)&0xf), 4751 uint8(v3)<<4, 4752 uint8(i4), 4753 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4754 uint8(op)) 4755 } 4756 4757 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4758 *asm = append(*asm, 4759 uint8(op>>8), 4760 (uint8(v1)<<4)|(uint8(v2)&0xf), 4761 uint8(i3>>4), 4762 (uint8(i3)<<4)|(uint8(m5)&0xf), 4763 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4764 uint8(op)) 4765 }