github.com/MerlinKodo/gvisor@v0.0.0-20231110090155-957f62ecf90e/pkg/abi/nvgpu/uvm.go (about) 1 // Copyright 2023 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package nvgpu 16 17 // HasRMCtrlFD is a type constraint for UVM parameter structs containing a 18 // RMCtrlFD field. This is necessary because, as of this writing (Go 1.20), 19 // there is no way to enable field access using a Go type constraint. 20 type HasRMCtrlFD interface { 21 GetRMCtrlFD() int32 22 SetRMCtrlFD(int32) 23 } 24 25 // UVM ioctl commands. 26 const ( 27 // From kernel-open/nvidia-uvm/uvm_linux_ioctl.h: 28 UVM_INITIALIZE = 0x30000001 29 UVM_DEINITIALIZE = 0x30000002 30 31 // From kernel-open/nvidia-uvm/uvm_ioctl.h: 32 UVM_CREATE_RANGE_GROUP = 23 33 UVM_DESTROY_RANGE_GROUP = 24 34 UVM_REGISTER_GPU_VASPACE = 25 35 UVM_UNREGISTER_GPU_VASPACE = 26 36 UVM_REGISTER_CHANNEL = 27 37 UVM_UNREGISTER_CHANNEL = 28 38 UVM_MAP_EXTERNAL_ALLOCATION = 33 39 UVM_FREE = 34 40 UVM_REGISTER_GPU = 37 41 UVM_UNREGISTER_GPU = 38 42 UVM_PAGEABLE_MEM_ACCESS = 39 43 UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65 44 UVM_ALLOC_SEMAPHORE_POOL = 68 45 UVM_VALIDATE_VA_RANGE = 72 46 UVM_CREATE_EXTERNAL_RANGE = 73 47 ) 48 49 // +marshal 50 type UVM_INITIALIZE_PARAMS struct { 51 Flags uint64 52 RMStatus uint32 53 Pad0 [4]byte 54 } 55 56 // UVM_INITIALIZE_PARAMS flags, from kernel-open/nvidia-uvm/uvm_types.h. 57 const ( 58 UVM_INIT_FLAGS_MULTI_PROCESS_SHARING_MODE = 0x2 59 ) 60 61 // +marshal 62 type UVM_CREATE_RANGE_GROUP_PARAMS struct { 63 RangeGroupID uint64 64 RMStatus uint32 65 Pad0 [4]byte 66 } 67 68 // +marshal 69 type UVM_DESTROY_RANGE_GROUP_PARAMS struct { 70 RangeGroupID uint64 71 RMStatus uint32 72 Pad0 [4]byte 73 } 74 75 // +marshal 76 type UVM_REGISTER_GPU_VASPACE_PARAMS struct { 77 GPUUUID [16]uint8 78 RMCtrlFD int32 79 HClient Handle 80 HVASpace Handle 81 RMStatus uint32 82 } 83 84 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) GetRMCtrlFD() int32 { 85 return p.RMCtrlFD 86 } 87 88 func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetRMCtrlFD(fd int32) { 89 p.RMCtrlFD = fd 90 } 91 92 // +marshal 93 type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct { 94 GPUUUID [16]uint8 95 RMStatus uint32 96 } 97 98 // +marshal 99 type UVM_REGISTER_CHANNEL_PARAMS struct { 100 GPUUUID [16]uint8 101 RMCtrlFD int32 102 HClient Handle 103 HChannel Handle 104 Pad [4]byte 105 Base uint64 106 Length uint64 107 RMStatus uint32 108 Pad0 [4]byte 109 } 110 111 func (p *UVM_REGISTER_CHANNEL_PARAMS) GetRMCtrlFD() int32 { 112 return p.RMCtrlFD 113 } 114 115 func (p *UVM_REGISTER_CHANNEL_PARAMS) SetRMCtrlFD(fd int32) { 116 p.RMCtrlFD = fd 117 } 118 119 // +marshal 120 type UVM_UNREGISTER_CHANNEL_PARAMS struct { 121 GPUUUID [16]uint8 122 HClient Handle 123 HChannel Handle 124 RMStatus uint32 125 } 126 127 // +marshal 128 type UVM_MAP_EXTERNAL_ALLOCATION_PARAMS struct { 129 Base uint64 130 Length uint64 131 Offset uint64 132 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 133 GPUAttributesCount uint64 134 RMCtrlFD int32 135 HClient Handle 136 HMemory Handle 137 RMStatus uint32 138 } 139 140 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) GetRMCtrlFD() int32 { 141 return p.RMCtrlFD 142 } 143 144 func (p *UVM_MAP_EXTERNAL_ALLOCATION_PARAMS) SetRMCtrlFD(fd int32) { 145 p.RMCtrlFD = fd 146 } 147 148 // +marshal 149 type UVM_FREE_PARAMS struct { 150 Base uint64 151 Length uint64 152 RMStatus uint32 153 Pad0 [4]byte 154 } 155 156 // +marshal 157 type UVM_REGISTER_GPU_PARAMS struct { 158 GPUUUID [16]uint8 159 NumaEnabled uint8 160 Pad [3]byte 161 NumaNodeID int32 162 RMCtrlFD int32 163 HClient Handle 164 HSMCPartRef Handle 165 RMStatus uint32 166 } 167 168 func (p *UVM_REGISTER_GPU_PARAMS) GetRMCtrlFD() int32 { 169 return p.RMCtrlFD 170 } 171 172 func (p *UVM_REGISTER_GPU_PARAMS) SetRMCtrlFD(fd int32) { 173 p.RMCtrlFD = fd 174 } 175 176 // +marshal 177 type UVM_UNREGISTER_GPU_PARAMS struct { 178 GPUUUID [16]uint8 179 RMStatus uint32 180 } 181 182 // +marshal 183 type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct { 184 PageableMemAccess uint8 185 Pad [3]byte 186 RMStatus uint32 187 } 188 189 // +marshal 190 type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct { 191 Base uint64 192 Length uint64 193 GPUUUID [16]uint8 194 RMStatus uint32 195 Pad0 [4]byte 196 } 197 198 // +marshal 199 type UVM_ALLOC_SEMAPHORE_POOL_PARAMS struct { 200 Base uint64 201 Length uint64 202 PerGPUAttributes [UVM_MAX_GPUS]UvmGpuMappingAttributes 203 GPUAttributesCount uint64 204 RMStatus uint32 205 Pad0 [4]byte 206 } 207 208 // +marshal 209 type UVM_VALIDATE_VA_RANGE_PARAMS struct { 210 Base uint64 211 Length uint64 212 RMStatus uint32 213 Pad0 [4]byte 214 } 215 216 // +marshal 217 type UVM_CREATE_EXTERNAL_RANGE_PARAMS struct { 218 Base uint64 219 Length uint64 220 RMStatus uint32 221 Pad0 [4]byte 222 } 223 224 // From kernel-open/nvidia-uvm/uvm_types.h: 225 226 const UVM_MAX_GPUS = NV_MAX_DEVICES 227 228 // +marshal 229 type UvmGpuMappingAttributes struct { 230 GPUUUID [16]byte 231 GPUMappingType uint32 232 GPUCachingType uint32 233 GPUFormatType uint32 234 GPUElementBits uint32 235 GPUCompressionType uint32 236 }