github.com/SagerNet/gvisor@v0.0.0-20210707092255-7731c139d75c/pkg/sentry/arch/registers.proto (about)

     1  // Copyright 2018 The gVisor Authors.
     2  //
     3  // Licensed under the Apache License, Version 2.0 (the "License");
     4  // you may not use this file except in compliance with the License.
     5  // You may obtain a copy of the License at
     6  //
     7  //     http://www.apache.org/licenses/LICENSE-2.0
     8  //
     9  // Unless required by applicable law or agreed to in writing, software
    10  // distributed under the License is distributed on an "AS IS" BASIS,
    11  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    12  // See the License for the specific language governing permissions and
    13  // limitations under the License.
    14  
    15  syntax = "proto3";
    16  
    17  package gvisor;
    18  
    19  message AMD64Registers {
    20    uint64 rax = 1;
    21    uint64 rbx = 2;
    22    uint64 rcx = 3;
    23    uint64 rdx = 4;
    24    uint64 rsi = 5;
    25    uint64 rdi = 6;
    26    uint64 rsp = 7;
    27    uint64 rbp = 8;
    28  
    29    uint64 r8 = 9;
    30    uint64 r9 = 10;
    31    uint64 r10 = 11;
    32    uint64 r11 = 12;
    33    uint64 r12 = 13;
    34    uint64 r13 = 14;
    35    uint64 r14 = 15;
    36    uint64 r15 = 16;
    37  
    38    uint64 rip = 17;
    39    uint64 rflags = 18;
    40    uint64 orig_rax = 19;
    41    uint64 cs = 20;
    42    uint64 ds = 21;
    43    uint64 es = 22;
    44    uint64 fs = 23;
    45    uint64 gs = 24;
    46    uint64 ss = 25;
    47    uint64 fs_base = 26;
    48    uint64 gs_base = 27;
    49  }
    50  
    51  message ARM64Registers {
    52    uint64 r0 = 1;
    53    uint64 r1 = 2;
    54    uint64 r2 = 3;
    55    uint64 r3 = 4;
    56    uint64 r4 = 5;
    57    uint64 r5 = 6;
    58    uint64 r6 = 7;
    59    uint64 r7 = 8;
    60    uint64 r8 = 9;
    61    uint64 r9 = 10;
    62    uint64 r10 = 11;
    63    uint64 r11 = 12;
    64    uint64 r12 = 13;
    65    uint64 r13 = 14;
    66    uint64 r14 = 15;
    67    uint64 r15 = 16;
    68    uint64 r16 = 17;
    69    uint64 r17 = 18;
    70    uint64 r18 = 19;
    71    uint64 r19 = 20;
    72    uint64 r20 = 21;
    73    uint64 r21 = 22;
    74    uint64 r22 = 23;
    75    uint64 r23 = 24;
    76    uint64 r24 = 25;
    77    uint64 r25 = 26;
    78    uint64 r26 = 27;
    79    uint64 r27 = 28;
    80    uint64 r28 = 29;
    81    uint64 r29 = 30;
    82    uint64 r30 = 31;
    83    uint64 sp = 32;
    84    uint64 pc = 33;
    85    uint64 pstate = 34;
    86    uint64 tls = 35;
    87  }
    88  message Registers {
    89    oneof arch {
    90      AMD64Registers amd64 = 1;
    91      ARM64Registers arm64 = 2;
    92    }
    93  }