github.com/SagerNet/gvisor@v0.0.0-20210707092255-7731c139d75c/pkg/sentry/platform/kvm/kvm_const_arm64.go (about) 1 // Copyright 2019 The gVisor Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 package kvm 16 17 // KVM ioctls for Arm64. 18 const ( 19 _KVM_GET_ONE_REG = 0x4010aeab 20 _KVM_SET_ONE_REG = 0x4010aeac 21 22 _KVM_ARM_TARGET_GENERIC_V8 = 5 23 _KVM_ARM_PREFERRED_TARGET = 0x8020aeaf 24 _KVM_ARM_VCPU_INIT = 0x4020aeae 25 _KVM_ARM64_REGS_PSTATE = 0x6030000000100042 26 _KVM_ARM64_REGS_SP_EL1 = 0x6030000000100044 27 _KVM_ARM64_REGS_R0 = 0x6030000000100000 28 _KVM_ARM64_REGS_R1 = 0x6030000000100002 29 _KVM_ARM64_REGS_R2 = 0x6030000000100004 30 _KVM_ARM64_REGS_R3 = 0x6030000000100006 31 _KVM_ARM64_REGS_R8 = 0x6030000000100010 32 _KVM_ARM64_REGS_R18 = 0x6030000000100024 33 _KVM_ARM64_REGS_PC = 0x6030000000100040 34 _KVM_ARM64_REGS_MAIR_EL1 = 0x603000000013c510 35 _KVM_ARM64_REGS_TCR_EL1 = 0x603000000013c102 36 _KVM_ARM64_REGS_TTBR0_EL1 = 0x603000000013c100 37 _KVM_ARM64_REGS_TTBR1_EL1 = 0x603000000013c101 38 _KVM_ARM64_REGS_SCTLR_EL1 = 0x603000000013c080 39 _KVM_ARM64_REGS_CPACR_EL1 = 0x603000000013c082 40 _KVM_ARM64_REGS_VBAR_EL1 = 0x603000000013c600 41 _KVM_ARM64_REGS_TIMER_CNT = 0x603000000013df1a 42 _KVM_ARM64_REGS_CNTFRQ_EL0 = 0x603000000013df00 43 ) 44 45 // Arm64: Architectural Feature Access Control Register EL1. 46 const ( 47 _FPEN_NOTRAP = 3 48 _FPEN_SHIFT = 20 49 ) 50 51 // Arm64: System Control Register EL1. 52 const ( 53 _SCTLR_M = 1 << 0 54 _SCTLR_C = 1 << 2 55 _SCTLR_I = 1 << 12 56 ) 57 58 // Arm64: Translation Control Register EL1. 59 const ( 60 _TCR_IPS_40BITS = 2 << 32 // PA=40 61 _TCR_IPS_48BITS = 5 << 32 // PA=48 62 63 _TCR_T0SZ_OFFSET = 0 64 _TCR_T1SZ_OFFSET = 16 65 _TCR_IRGN0_SHIFT = 8 66 _TCR_IRGN1_SHIFT = 24 67 _TCR_ORGN0_SHIFT = 10 68 _TCR_ORGN1_SHIFT = 26 69 _TCR_SH0_SHIFT = 12 70 _TCR_SH1_SHIFT = 28 71 _TCR_TG0_SHIFT = 14 72 _TCR_TG1_SHIFT = 30 73 74 _TCR_T0SZ_VA48 = 64 - 48 // VA=48 75 _TCR_T1SZ_VA48 = 64 - 48 // VA=48 76 77 _TCR_A1 = 1 << 22 78 _TCR_ASID16 = 1 << 36 79 _TCR_TBI0 = 1 << 37 80 81 _TCR_TXSZ_VA48 = (_TCR_T0SZ_VA48 << _TCR_T0SZ_OFFSET) | (_TCR_T1SZ_VA48 << _TCR_T1SZ_OFFSET) 82 83 _TCR_TG0_4K = 0 << _TCR_TG0_SHIFT // 4K 84 _TCR_TG0_64K = 1 << _TCR_TG0_SHIFT // 64K 85 86 _TCR_TG1_4K = 2 << _TCR_TG1_SHIFT 87 88 _TCR_TG_FLAGS = _TCR_TG0_4K | _TCR_TG1_4K 89 90 _TCR_IRGN0_WBWA = 1 << _TCR_IRGN0_SHIFT 91 _TCR_IRGN1_WBWA = 1 << _TCR_IRGN1_SHIFT 92 _TCR_IRGN_WBWA = _TCR_IRGN0_WBWA | _TCR_IRGN1_WBWA 93 94 _TCR_ORGN0_WBWA = 1 << _TCR_ORGN0_SHIFT 95 _TCR_ORGN1_WBWA = 1 << _TCR_ORGN1_SHIFT 96 97 _TCR_ORGN_WBWA = _TCR_ORGN0_WBWA | _TCR_ORGN1_WBWA 98 99 _TCR_SHARED = (3 << _TCR_SH0_SHIFT) | (3 << _TCR_SH1_SHIFT) 100 101 _TCR_CACHE_FLAGS = _TCR_IRGN_WBWA | _TCR_ORGN_WBWA 102 ) 103 104 // Arm64: Memory Attribute Indirection Register EL1. 105 const ( 106 _MT_DEVICE_nGnRnE = 0 107 _MT_DEVICE_nGnRE = 1 108 _MT_DEVICE_GRE = 2 109 _MT_NORMAL_NC = 3 110 _MT_NORMAL = 4 111 _MT_NORMAL_WT = 5 112 _MT_ATTR_DEVICE_nGnRnE = 0x00 113 _MT_ATTR_DEVICE_nGnRE = 0x04 114 _MT_ATTR_DEVICE_GRE = 0x0c 115 _MT_ATTR_NORMAL_NC = 0x44 116 _MT_ATTR_NORMAL_WT = 0xbb 117 _MT_ATTR_NORMAL = 0xff 118 _MT_ATTR_MASK = 0xff 119 _MT_EL1_INIT = (_MT_ATTR_DEVICE_nGnRnE << (_MT_DEVICE_nGnRnE * 8)) | (_MT_ATTR_DEVICE_nGnRE << (_MT_DEVICE_nGnRE * 8)) | (_MT_ATTR_DEVICE_GRE << (_MT_DEVICE_GRE * 8)) | (_MT_ATTR_NORMAL_NC << (_MT_NORMAL_NC * 8)) | (_MT_ATTR_NORMAL << (_MT_NORMAL * 8)) | (_MT_ATTR_NORMAL_WT << (_MT_NORMAL_WT * 8)) 120 ) 121 122 const ( 123 _KVM_ARM_VCPU_POWER_OFF = 0 // CPU is started in OFF state 124 _KVM_ARM_VCPU_PSCI_0_2 = 2 // CPU uses PSCI v0.2 125 ) 126 127 // Arm64: Exception Syndrome Register EL1. 128 const ( 129 _ESR_ELx_EC_SHIFT = 26 130 _ESR_ELx_EC_MASK = 0x3F << _ESR_ELx_EC_SHIFT 131 132 _ESR_ELx_EC_IMP_DEF = 0x1f 133 _ESR_ELx_EC_IABT_LOW = 0x20 134 _ESR_ELx_EC_IABT_CUR = 0x21 135 _ESR_ELx_EC_PC_ALIGN = 0x22 136 137 _ESR_ELx_CM = 1 << 8 138 _ESR_ELx_WNR = 1 << 6 139 140 _ESR_ELx_FSC = 0x3F 141 142 _ESR_SEGV_MAPERR_L0 = 0x4 143 _ESR_SEGV_MAPERR_L1 = 0x5 144 _ESR_SEGV_MAPERR_L2 = 0x6 145 _ESR_SEGV_MAPERR_L3 = 0x7 146 147 _ESR_SEGV_ACCERR_L1 = 0x9 148 _ESR_SEGV_ACCERR_L2 = 0xa 149 _ESR_SEGV_ACCERR_L3 = 0xb 150 151 _ESR_SEGV_PEMERR_L1 = 0xd 152 _ESR_SEGV_PEMERR_L2 = 0xe 153 _ESR_SEGV_PEMERR_L3 = 0xf 154 155 // Custom ISS field definitions for system error. 156 _ESR_ELx_SERR_NMI = 0x1 157 ) 158 159 // Arm64: MMIO base address used to dispatch hypercalls. 160 const ( 161 // on Arm64, the MMIO address must be 64-bit aligned. 162 // Currently, we only need 1 hypercall: hypercall_vmexit. 163 _AARCH64_HYPERCALL_MMIO_SIZE = 1 << 3 164 )