github.com/TrenchBoot/u-root@v6.0.1-0.20200623220532-550e36da3258+incompatible/pkg/dt/testdata/fdt.dts (about) 1 /dts-v1/; 2 // magic: 0xd00dfeed 3 // totalsize: 0x100000 (1048576) 4 // off_dt_struct: 0x40 5 // off_dt_strings: 0x1aa0 6 // off_mem_rsvmap: 0x30 7 // version: 17 8 // last_comp_version: 16 9 // boot_cpuid_phys: 0x0 10 // size_dt_strings: 0x1cf 11 // size_dt_struct: 0x1a60 12 13 / { 14 interrupt-parent = <0x00008001>; 15 #size-cells = <0x00000002>; 16 #address-cells = <0x00000002>; 17 compatible = "linux,dummy-virt"; 18 psci { 19 migrate = <0x84000005>; 20 cpu_on = <0x84000003>; 21 cpu_off = <0x84000002>; 22 cpu_suspend = <0x84000001>; 23 method = "hvc"; 24 compatible = "arm,psci-0.2", "arm,psci"; 25 }; 26 memory@40000000 { 27 reg = <0x00000000 0x00000003 0x72790030 0x666f726d>; 28 device_type = "memory"; 29 }; 30 platform@c000000 { 31 interrupt-parent = <0x00008001>; 32 ranges = <0x00000000 0x00000003 0x00000003 0x00000003>; 33 #address-cells = <0x00000001>; 34 #size-cells = <0x00000001>; 35 compatible = "qemu,platform", "simple-bus"; 36 }; 37 fw-cfg@9020000 { 38 dma-coherent; 39 reg = <0x00000000 0x00000003 0x2c66772d 0x00000002>; 40 compatible = "qemu,fw-cfg-mmio"; 41 }; 42 virtio_mmio@a000000 { 43 dma-coherent; 44 interrupts = <0x00000000 0x00000010 0x00000000>; 45 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 46 compatible = "virtio,mmio"; 47 }; 48 virtio_mmio@a000200 { 49 dma-coherent; 50 interrupts = <0x00000000 0x00000010 0x00000000>; 51 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 52 compatible = "virtio,mmio"; 53 }; 54 virtio_mmio@a000400 { 55 dma-coherent; 56 interrupts = <0x00000000 0x00000010 0x00000000>; 57 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 58 compatible = "virtio,mmio"; 59 }; 60 virtio_mmio@a000600 { 61 dma-coherent; 62 interrupts = <0x00000000 0x00000010 0x00000000>; 63 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 64 compatible = "virtio,mmio"; 65 }; 66 virtio_mmio@a000800 { 67 dma-coherent; 68 interrupts = <0x00000000 0x00000010 0x00000000>; 69 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 70 compatible = "virtio,mmio"; 71 }; 72 virtio_mmio@a000a00 { 73 dma-coherent; 74 interrupts = <0x00000000 0x00000010 0x00000000>; 75 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 76 compatible = "virtio,mmio"; 77 }; 78 virtio_mmio@a000c00 { 79 dma-coherent; 80 interrupts = <0x00000000 0x00000010 0x00000000>; 81 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 82 compatible = "virtio,mmio"; 83 }; 84 virtio_mmio@a000e00 { 85 dma-coherent; 86 interrupts = <0x00000000 0x00000010 0x00000000>; 87 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 88 compatible = "virtio,mmio"; 89 }; 90 virtio_mmio@a001000 { 91 dma-coherent; 92 interrupts = <0x00000000 0x00000010 0x00000000>; 93 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 94 compatible = "virtio,mmio"; 95 }; 96 virtio_mmio@a001200 { 97 dma-coherent; 98 interrupts = <0x00000000 0x00000010 0x00000000>; 99 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 100 compatible = "virtio,mmio"; 101 }; 102 virtio_mmio@a001400 { 103 dma-coherent; 104 interrupts = <0x00000000 0x00000010 0x00000000>; 105 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 106 compatible = "virtio,mmio"; 107 }; 108 virtio_mmio@a001600 { 109 dma-coherent; 110 interrupts = <0x00000000 0x00000010 0x00000000>; 111 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 112 compatible = "virtio,mmio"; 113 }; 114 virtio_mmio@a001800 { 115 dma-coherent; 116 interrupts = <0x00000000 0x00000010 0x00000000>; 117 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 118 compatible = "virtio,mmio"; 119 }; 120 virtio_mmio@a001a00 { 121 dma-coherent; 122 interrupts = <0x00000000 0x00000010 0x00000000>; 123 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 124 compatible = "virtio,mmio"; 125 }; 126 virtio_mmio@a001c00 { 127 dma-coherent; 128 interrupts = <0x00000000 0x00000010 0x00000000>; 129 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 130 compatible = "virtio,mmio"; 131 }; 132 virtio_mmio@a001e00 { 133 dma-coherent; 134 interrupts = <0x00000000 0x00000010 0x00000000>; 135 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 136 compatible = "virtio,mmio"; 137 }; 138 virtio_mmio@a002000 { 139 dma-coherent; 140 interrupts = <0x00000000 0x00000010 0x00000000>; 141 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 142 compatible = "virtio,mmio"; 143 }; 144 virtio_mmio@a002200 { 145 dma-coherent; 146 interrupts = <0x00000000 0x00000010 0x00000000>; 147 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 148 compatible = "virtio,mmio"; 149 }; 150 virtio_mmio@a002400 { 151 dma-coherent; 152 interrupts = <0x00000000 0x00000010 0x00000000>; 153 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 154 compatible = "virtio,mmio"; 155 }; 156 virtio_mmio@a002600 { 157 dma-coherent; 158 interrupts = <0x00000000 0x00000010 0x00000000>; 159 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 160 compatible = "virtio,mmio"; 161 }; 162 virtio_mmio@a002800 { 163 dma-coherent; 164 interrupts = <0x00000000 0x00000010 0x00000000>; 165 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 166 compatible = "virtio,mmio"; 167 }; 168 virtio_mmio@a002a00 { 169 dma-coherent; 170 interrupts = <0x00000000 0x00000010 0x00000000>; 171 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 172 compatible = "virtio,mmio"; 173 }; 174 virtio_mmio@a002c00 { 175 dma-coherent; 176 interrupts = <0x00000000 0x00000010 0x00000000>; 177 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 178 compatible = "virtio,mmio"; 179 }; 180 virtio_mmio@a002e00 { 181 dma-coherent; 182 interrupts = <0x00000000 0x00000010 0x00000000>; 183 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 184 compatible = "virtio,mmio"; 185 }; 186 virtio_mmio@a003000 { 187 dma-coherent; 188 interrupts = <0x00000000 0x00000010 0x00000000>; 189 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 190 compatible = "virtio,mmio"; 191 }; 192 virtio_mmio@a003200 { 193 dma-coherent; 194 interrupts = <0x00000000 0x00000010 0x00000000>; 195 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 196 compatible = "virtio,mmio"; 197 }; 198 virtio_mmio@a003400 { 199 dma-coherent; 200 interrupts = <0x00000000 0x00000010 0x00000000>; 201 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 202 compatible = "virtio,mmio"; 203 }; 204 virtio_mmio@a003600 { 205 dma-coherent; 206 interrupts = <0x00000000 0x00000010 0x00000000>; 207 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 208 compatible = "virtio,mmio"; 209 }; 210 virtio_mmio@a003800 { 211 dma-coherent; 212 interrupts = <0x00000000 0x00000010 0x00000000>; 213 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 214 compatible = "virtio,mmio"; 215 }; 216 virtio_mmio@a003a00 { 217 dma-coherent; 218 interrupts = <0x00000000 0x00000010 0x00000000>; 219 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 220 compatible = "virtio,mmio"; 221 }; 222 virtio_mmio@a003c00 { 223 dma-coherent; 224 interrupts = <0x00000000 0x00000010 0x00000000>; 225 reg = <0x00000000 0x00000003 0x696f2c6d 0x76697274>; 226 compatible = "virtio,mmio"; 227 }; 228 virtio_mmio@a003e00 { 229 dma-coherent; 230 interrupts = <0x00000000 0x00000010 0x00000000>; 231 reg = <0x00000000 0x00000003 0x696f2c6d 0x6770696f>; 232 compatible = "virtio,mmio"; 233 }; 234 gpio-keys { 235 #address-cells = <0x00000001>; 236 #size-cells = <0x00000000>; 237 compatible = "gpio-keys"; 238 poweroff { 239 gpios = <0x00008003 0x00000004 0x00000012>; 240 linux,code = <0x00000074>; 241 label = "GPIO Key Poweroff"; 242 }; 243 }; 244 pl061@9030000 { 245 phandle = <0x00008003>; 246 clock-names = "apb_pclk"; 247 clocks = <0x00008000>; 248 interrupts = <0x00000000 0x00000000 0x0000014e>; 249 gpio-controller; 250 #gpio-cells = <0x00000002>; 251 compatible = "arm,pl061", "arm,primecell"; 252 reg = <0x00000000 0x00000002 0x30303030 0x0000013b>; 253 }; 254 pcie@10000000 { 255 interrupt-map-mask = <0x00001800 0x00000003 0x00000000 0x00000000>; 256 interrupt-map = <0x00000000 0x00008001 0x00000003 0x00000000 0x00000000 0x00000000 0x00008001 0x00000005 0x00000000 0x00000000 0x00000800 0x00008001 0x00000004 0x00000000 0x00000000 0x00000800 0x00008001 0x00000006 0x00000000 0x00000000 0x00001000 0x00008001 0x00000005 0x00000000 0x00000000 0x00001000 0x00008001 0x00000003 0x00000000 0x00000000 0x00001800 0x00008001 0x00000006 0x00000000 0x00000000 0x00001800 0x00008001 0x00000004 0x00000000 0x00000000 0x00000003 0x00000003 0x00000000 0x00000000 0x10000000 0x2eff0000 0x00000080 0x00000003 0x10000000 0x00000004 0x00000000 0x0000010b 0x00000004 0x00000004 0x00000004 0x00000004 0x00000016 0x2d656361 0x00000002 0x31303030 0x000000e2 0x00000003 0x00000003 0x00000002 0x0000007f 0x00001000 0x61726d2c 0x696d6563 0x706c3031 0x00000003 0x636c6b00 0x00000003 0x00008000 0x00000000 0x00000010 0x00000000 0x00000000 0x6d2c7072 0x00000001 0x00000000 0x00008001 0x00000000 0x00000000 0x00000003 0x636f7274 0x00000003 0x00000004 0x00000004 0x00000000 0x0000009f 0x38303230 0x00000056 0x0000007f 0x00001000 0x00000003 0x6769632d 0x00000002 0x68403000 0x00000004 0x00000000 0x00000000 0x00000003 0x666c6173 0x63707573 0x0000001a 0x0000000b 0x30000000 0x00000000 0x61726d2c 0x00000003 0x00000002 0x72000000 0x00000001 0x0000000e 0x00000104 0x00000003 0x00000010 0x372d7469 0x6170622d 0x00000004 0x00000009 0x00000004 0x016e3600 0x00000000 0x66697865 0x00000001 0x00000004 0x00000004 0x0000000f 0x30303030 0x00000009 0x61646472 0x697a652d 0x2d63656c 0x7175656e 0x7075742d 0x6500616c 0x72727570 0x70650072 0x6800696e 0x6e740023 0x6c6c7300 0x6e74726f 0x6d73692d 0x6c6f636b 0x73007374 0x6e75782c 0x75732d72 0x6572656e 0x00696e74 0x6e746572 0x6b002367 0x696f2d63 0x62656c00 0x70696f73 0x642d7374 0x69747264 0x6370755f 0x6f666600 0x74650000>; 257 #interrupt-cells = <0x00000001>; 258 ranges = <0x01000000 0x3eff0000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000040 0x00000003 0x00000003 0x00000008 0x00000003 0x00000003 0x00000003 0x00000003 0x00000003 0x686f7374 0x630000e2 0x31403930 0x00000009 0x0000000c 0x00008000>; 259 reg = <0x00000040 0x00000003 0x00000003 0x00000008>; 260 msi-parent = <0x00008002>; 261 dma-coherent; 262 bus-range = <0x00000000 0x000000fa>; 263 linux,pci-domain = <0x00000000>; 264 #size-cells = <0x00000002>; 265 #address-cells = <0x00000003>; 266 device_type = "pci"; 267 compatible = "pci-host-ecam-generic"; 268 }; 269 pl031@9010000 { 270 clock-names = "apb_pclk"; 271 clocks = <0x00008000>; 272 interrupts = <0x00000000 0x00000010 0x00000000>; 273 reg = <0x00000000 0x00000003 0x706c3033 0x656c6c00>; 274 compatible = "arm,pl031", "arm,primecell"; 275 }; 276 pl011@9000000 { 277 clock-names = "uartclk", "apb_pclk"; 278 clocks = <0x00008000 0x00000068>; 279 interrupts = <0x00000000 0x00000010 0x00000000>; 280 reg = <0x00000000 0x00000003 0x706c3031 0x656c6c00>; 281 compatible = "arm,pl011", "arm,primecell"; 282 }; 283 intc@8000000 { 284 phandle = <0x00008001>; 285 reg = <0x00000000 0x00000000 0x00000003 0x636f7274 0x00000003 0x00000004 0x00000004 0x00000000>; 286 compatible = "arm,cortex-a15-gic"; 287 ranges; 288 #size-cells = <0x00000002>; 289 #address-cells = <0x00000002>; 290 interrupt-controller; 291 #interrupt-cells = <0x00000003>; 292 v2m@8020000 { 293 phandle = <0x00008002>; 294 reg = <0x00000000 0x00000003 0x00000012 0x76326d2d>; 295 msi-controller; 296 compatible = "arm,gic-v2m-frame"; 297 }; 298 }; 299 flash@0 { 300 bank-width = <0x00000004>; 301 reg = <0x00000000 0x00000000 0x00000003 0x666c6173 0x63707573 0x0000001a 0x0000000b 0x30000000>; 302 compatible = "cfi-flash"; 303 }; 304 cpus { 305 #size-cells = <0x00000000>; 306 #address-cells = <0x00000001>; 307 cpu@0 { 308 reg = <0x00000000>; 309 compatible = "arm,cortex-a15"; 310 device_type = "cpu"; 311 }; 312 }; 313 timer { 314 interrupts = <0x00000001 0x0000000e 0x00000104 0x00000003 0x00000010 0x372d7469 0x6170622d 0x00000004 0x00000009 0x00000004 0x016e3600 0x00000000>; 315 always-on; 316 compatible = "arm,armv7-timer"; 317 }; 318 apb-pclk { 319 phandle = <0x00008000>; 320 clock-output-names = "clk24mhz"; 321 clock-frequency = <0x016e3600>; 322 #clock-cells = <0x00000000>; 323 compatible = "fixed-clock"; 324 }; 325 chosen { 326 linux,initrd-end = <0x44cb8fc4>; 327 linux,initrd-start = <0x44000000>; 328 stdout-path = "/pl011@9000000"; 329 }; 330 };