github.com/ader1990/go@v0.0.0-20140630135419-8c24447fa791/src/cmd/objdump/armasm.go (about) 1 // DO NOT EDIT. Generated by code.google.com/p/rsc/cmd/bundle 2 // bundle -p main -x arm_ rsc.io/arm/armasm 3 4 /* decode.go */ 5 6 // Copyright 2014 The Go Authors. All rights reserved. 7 // Use of this source code is governed by a BSD-style 8 // license that can be found in the LICENSE file. 9 10 package main 11 12 import ( 13 "bytes" 14 "encoding/binary" 15 "fmt" 16 "io" 17 "strings" 18 ) 19 20 // An instFormat describes the format of an instruction encoding. 21 // An instruction with 32-bit value x matches the format if x&mask == value 22 // and the condition matches. 23 // The condition matches if x>>28 == 0xF && value>>28==0xF 24 // or if x>>28 != 0xF and value>>28 == 0. 25 // If x matches the format, then the rest of the fields describe how to interpret x. 26 // The opBits describe bits that should be extracted from x and added to the opcode. 27 // For example opBits = 0x1234 means that the value 28 // (2 bits at offset 1) followed by (4 bits at offset 3) 29 // should be added to op. 30 // Finally the args describe how to decode the instruction arguments. 31 // args is stored as a fixed-size array; if there are fewer than len(args) arguments, 32 // args[i] == 0 marks the end of the argument list. 33 type arm_instFormat struct { 34 mask uint32 35 value uint32 36 priority int8 37 op arm_Op 38 opBits uint64 39 args arm_instArgs 40 } 41 42 type arm_instArgs [4]arm_instArg 43 44 var ( 45 arm_errMode = fmt.Errorf("unsupported execution mode") 46 arm_errShort = fmt.Errorf("truncated instruction") 47 arm_errUnknown = fmt.Errorf("unknown instruction") 48 ) 49 50 var arm_decoderCover []bool 51 52 // Decode decodes the leading bytes in src as a single instruction. 53 func arm_Decode(src []byte, mode arm_Mode) (inst arm_Inst, err error) { 54 if mode != arm_ModeARM { 55 return arm_Inst{}, arm_errMode 56 } 57 if len(src) < 4 { 58 return arm_Inst{}, arm_errShort 59 } 60 61 if arm_decoderCover == nil { 62 arm_decoderCover = make([]bool, len(arm_instFormats)) 63 } 64 65 x := binary.LittleEndian.Uint32(src) 66 67 // The instFormat table contains both conditional and unconditional instructions. 68 // Considering only the top 4 bits, the conditional instructions use mask=0, value=0, 69 // while the unconditional instructions use mask=f, value=f. 70 // Prepare a version of x with the condition cleared to 0 in conditional instructions 71 // and then assume mask=f during matching. 72 const condMask = 0xf0000000 73 xNoCond := x 74 if x&condMask != condMask { 75 xNoCond &^= condMask 76 } 77 var priority int8 78 Search: 79 for i := range arm_instFormats { 80 f := &arm_instFormats[i] 81 if xNoCond&(f.mask|condMask) != f.value || f.priority <= priority { 82 continue 83 } 84 delta := uint32(0) 85 deltaShift := uint(0) 86 for opBits := f.opBits; opBits != 0; opBits >>= 16 { 87 n := uint(opBits & 0xFF) 88 off := uint((opBits >> 8) & 0xFF) 89 delta |= (x >> off) & (1<<n - 1) << deltaShift 90 deltaShift += n 91 } 92 op := f.op + arm_Op(delta) 93 94 // Special case: BKPT encodes with condition but cannot have one. 95 if op&^15 == arm_BKPT_EQ && op != arm_BKPT { 96 continue Search 97 } 98 99 var args arm_Args 100 for j, aop := range f.args { 101 if aop == 0 { 102 break 103 } 104 arg := arm_decodeArg(aop, x) 105 if arg == nil { // cannot decode argument 106 continue Search 107 } 108 args[j] = arg 109 } 110 111 arm_decoderCover[i] = true 112 113 inst = arm_Inst{ 114 Op: op, 115 Args: args, 116 Enc: x, 117 Len: 4, 118 } 119 priority = f.priority 120 continue Search 121 } 122 if inst.Op != 0 { 123 return inst, nil 124 } 125 return arm_Inst{}, arm_errUnknown 126 } 127 128 // An instArg describes the encoding of a single argument. 129 // In the names used for arguments, _p_ means +, _m_ means -, 130 // _pm_ means ± (usually keyed by the U bit). 131 // The _W suffix indicates a general addressing mode based on the P and W bits. 132 // The _offset and _postindex suffixes force the given addressing mode. 133 // The rest should be somewhat self-explanatory, at least given 134 // the decodeArg function. 135 type arm_instArg uint8 136 137 const ( 138 _ arm_instArg = iota 139 arm_arg_APSR 140 arm_arg_FPSCR 141 arm_arg_Dn_half 142 arm_arg_R1_0 143 arm_arg_R1_12 144 arm_arg_R2_0 145 arm_arg_R2_12 146 arm_arg_R_0 147 arm_arg_R_12 148 arm_arg_R_12_nzcv 149 arm_arg_R_16 150 arm_arg_R_16_WB 151 arm_arg_R_8 152 arm_arg_R_rotate 153 arm_arg_R_shift_R 154 arm_arg_R_shift_imm 155 arm_arg_SP 156 arm_arg_Sd 157 arm_arg_Sd_Dd 158 arm_arg_Dd_Sd 159 arm_arg_Sm 160 arm_arg_Sm_Dm 161 arm_arg_Sn 162 arm_arg_Sn_Dn 163 arm_arg_const 164 arm_arg_endian 165 arm_arg_fbits 166 arm_arg_fp_0 167 arm_arg_imm24 168 arm_arg_imm5 169 arm_arg_imm5_32 170 arm_arg_imm5_nz 171 arm_arg_imm_12at8_4at0 172 arm_arg_imm_4at16_12at0 173 arm_arg_imm_vfp 174 arm_arg_label24 175 arm_arg_label24H 176 arm_arg_label_m_12 177 arm_arg_label_p_12 178 arm_arg_label_pm_12 179 arm_arg_label_pm_4_4 180 arm_arg_lsb_width 181 arm_arg_mem_R 182 arm_arg_mem_R_pm_R_W 183 arm_arg_mem_R_pm_R_postindex 184 arm_arg_mem_R_pm_R_shift_imm_W 185 arm_arg_mem_R_pm_R_shift_imm_offset 186 arm_arg_mem_R_pm_R_shift_imm_postindex 187 arm_arg_mem_R_pm_imm12_W 188 arm_arg_mem_R_pm_imm12_offset 189 arm_arg_mem_R_pm_imm12_postindex 190 arm_arg_mem_R_pm_imm8_W 191 arm_arg_mem_R_pm_imm8_postindex 192 arm_arg_mem_R_pm_imm8at0_offset 193 arm_arg_option 194 arm_arg_registers 195 arm_arg_registers1 196 arm_arg_registers2 197 arm_arg_satimm4 198 arm_arg_satimm5 199 arm_arg_satimm4m1 200 arm_arg_satimm5m1 201 arm_arg_widthm1 202 ) 203 204 // decodeArg decodes the arg described by aop from the instruction bits x. 205 // It returns nil if x cannot be decoded according to aop. 206 func arm_decodeArg(aop arm_instArg, x uint32) arm_Arg { 207 switch aop { 208 default: 209 return nil 210 211 case arm_arg_APSR: 212 return arm_APSR 213 case arm_arg_FPSCR: 214 return arm_FPSCR 215 216 case arm_arg_R_0: 217 return arm_Reg(x & (1<<4 - 1)) 218 case arm_arg_R_8: 219 return arm_Reg((x >> 8) & (1<<4 - 1)) 220 case arm_arg_R_12: 221 return arm_Reg((x >> 12) & (1<<4 - 1)) 222 case arm_arg_R_16: 223 return arm_Reg((x >> 16) & (1<<4 - 1)) 224 225 case arm_arg_R_12_nzcv: 226 r := arm_Reg((x >> 12) & (1<<4 - 1)) 227 if r == arm_R15 { 228 return arm_APSR_nzcv 229 } 230 return r 231 232 case arm_arg_R_16_WB: 233 mode := arm_AddrLDM 234 if (x>>21)&1 != 0 { 235 mode = arm_AddrLDM_WB 236 } 237 return arm_Mem{Base: arm_Reg((x >> 16) & (1<<4 - 1)), Mode: mode} 238 239 case arm_arg_R_rotate: 240 Rm := arm_Reg(x & (1<<4 - 1)) 241 typ, count := arm_decodeShift(x) 242 // ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1. 243 if typ == arm_RotateRightExt { 244 return arm_Reg(Rm) 245 } 246 return arm_RegShift{Rm, typ, uint8(count)} 247 248 case arm_arg_R_shift_R: 249 Rm := arm_Reg(x & (1<<4 - 1)) 250 Rs := arm_Reg((x >> 8) & (1<<4 - 1)) 251 typ := arm_Shift((x >> 5) & (1<<2 - 1)) 252 return arm_RegShiftReg{Rm, typ, Rs} 253 254 case arm_arg_R_shift_imm: 255 Rm := arm_Reg(x & (1<<4 - 1)) 256 typ, count := arm_decodeShift(x) 257 if typ == arm_ShiftLeft && count == 0 { 258 return arm_Reg(Rm) 259 } 260 return arm_RegShift{Rm, typ, uint8(count)} 261 262 case arm_arg_R1_0: 263 return arm_Reg((x & (1<<4 - 1))) 264 case arm_arg_R1_12: 265 return arm_Reg(((x >> 12) & (1<<4 - 1))) 266 case arm_arg_R2_0: 267 return arm_Reg((x & (1<<4 - 1)) | 1) 268 case arm_arg_R2_12: 269 return arm_Reg(((x >> 12) & (1<<4 - 1)) | 1) 270 271 case arm_arg_SP: 272 return arm_SP 273 274 case arm_arg_Sd_Dd: 275 v := (x >> 12) & (1<<4 - 1) 276 vx := (x >> 22) & 1 277 sz := (x >> 8) & 1 278 if sz != 0 { 279 return arm_D0 + arm_Reg(vx<<4+v) 280 } else { 281 return arm_S0 + arm_Reg(v<<1+vx) 282 } 283 284 case arm_arg_Dd_Sd: 285 return arm_decodeArg(arm_arg_Sd_Dd, x^(1<<8)) 286 287 case arm_arg_Sd: 288 v := (x >> 12) & (1<<4 - 1) 289 vx := (x >> 22) & 1 290 return arm_S0 + arm_Reg(v<<1+vx) 291 292 case arm_arg_Sm_Dm: 293 v := (x >> 0) & (1<<4 - 1) 294 vx := (x >> 5) & 1 295 sz := (x >> 8) & 1 296 if sz != 0 { 297 return arm_D0 + arm_Reg(vx<<4+v) 298 } else { 299 return arm_S0 + arm_Reg(v<<1+vx) 300 } 301 302 case arm_arg_Sm: 303 v := (x >> 0) & (1<<4 - 1) 304 vx := (x >> 5) & 1 305 return arm_S0 + arm_Reg(v<<1+vx) 306 307 case arm_arg_Dn_half: 308 v := (x >> 16) & (1<<4 - 1) 309 vx := (x >> 7) & 1 310 return arm_RegX{arm_D0 + arm_Reg(vx<<4+v), int((x >> 21) & 1)} 311 312 case arm_arg_Sn_Dn: 313 v := (x >> 16) & (1<<4 - 1) 314 vx := (x >> 7) & 1 315 sz := (x >> 8) & 1 316 if sz != 0 { 317 return arm_D0 + arm_Reg(vx<<4+v) 318 } else { 319 return arm_S0 + arm_Reg(v<<1+vx) 320 } 321 322 case arm_arg_Sn: 323 v := (x >> 16) & (1<<4 - 1) 324 vx := (x >> 7) & 1 325 return arm_S0 + arm_Reg(v<<1+vx) 326 327 case arm_arg_const: 328 v := x & (1<<8 - 1) 329 rot := (x >> 8) & (1<<4 - 1) * 2 330 if rot > 0 && v&3 == 0 { 331 // could rotate less 332 return arm_ImmAlt{uint8(v), uint8(rot)} 333 } 334 if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v { 335 // could wrap around to rot==0. 336 return arm_ImmAlt{uint8(v), uint8(rot)} 337 } 338 return arm_Imm(v>>rot | v<<(32-rot)) 339 340 case arm_arg_endian: 341 return arm_Endian((x >> 9) & 1) 342 343 case arm_arg_fbits: 344 return arm_Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1)) 345 346 case arm_arg_fp_0: 347 return arm_Imm(0) 348 349 case arm_arg_imm24: 350 return arm_Imm(x & (1<<24 - 1)) 351 352 case arm_arg_imm5: 353 return arm_Imm((x >> 7) & (1<<5 - 1)) 354 355 case arm_arg_imm5_32: 356 x = (x >> 7) & (1<<5 - 1) 357 if x == 0 { 358 x = 32 359 } 360 return arm_Imm(x) 361 362 case arm_arg_imm5_nz: 363 x = (x >> 7) & (1<<5 - 1) 364 if x == 0 { 365 return nil 366 } 367 return arm_Imm(x) 368 369 case arm_arg_imm_4at16_12at0: 370 return arm_Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1)) 371 372 case arm_arg_imm_12at8_4at0: 373 return arm_Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1)) 374 375 case arm_arg_imm_vfp: 376 x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1) 377 return arm_Imm(x) 378 379 case arm_arg_label24: 380 imm := (x & (1<<24 - 1)) << 2 381 return arm_PCRel(int32(imm<<6) >> 6) 382 383 case arm_arg_label24H: 384 h := (x >> 24) & 1 385 imm := (x&(1<<24-1))<<2 | h<<1 386 return arm_PCRel(int32(imm<<6) >> 6) 387 388 case arm_arg_label_m_12: 389 d := int32(x & (1<<12 - 1)) 390 return arm_Mem{Base: arm_PC, Mode: arm_AddrOffset, Offset: int16(-d)} 391 392 case arm_arg_label_p_12: 393 d := int32(x & (1<<12 - 1)) 394 return arm_Mem{Base: arm_PC, Mode: arm_AddrOffset, Offset: int16(d)} 395 396 case arm_arg_label_pm_12: 397 d := int32(x & (1<<12 - 1)) 398 u := (x >> 23) & 1 399 if u == 0 { 400 d = -d 401 } 402 return arm_Mem{Base: arm_PC, Mode: arm_AddrOffset, Offset: int16(d)} 403 404 case arm_arg_label_pm_4_4: 405 d := int32((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) 406 u := (x >> 23) & 1 407 if u == 0 { 408 d = -d 409 } 410 return arm_PCRel(d) 411 412 case arm_arg_lsb_width: 413 lsb := (x >> 7) & (1<<5 - 1) 414 msb := (x >> 16) & (1<<5 - 1) 415 if msb < lsb || msb >= 32 { 416 return nil 417 } 418 return arm_Imm(msb + 1 - lsb) 419 420 case arm_arg_mem_R: 421 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) 422 return arm_Mem{Base: Rn, Mode: arm_AddrOffset} 423 424 case arm_arg_mem_R_pm_R_postindex: 425 // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!} 426 // by forcing shift bits to <<0 and P=0, W=0 (postindex=true). 427 return arm_decodeArg(arm_arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5|1<<24|1<<21)) 428 429 case arm_arg_mem_R_pm_R_W: 430 // Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!} 431 // by forcing shift bits to <<0. 432 return arm_decodeArg(arm_arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5)) 433 434 case arm_arg_mem_R_pm_R_shift_imm_offset: 435 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!} 436 // by forcing P=1, W=0 (index=false, wback=false). 437 return arm_decodeArg(arm_arg_mem_R_pm_R_shift_imm_W, x&^(1<<21)|1<<24) 438 439 case arm_arg_mem_R_pm_R_shift_imm_postindex: 440 // Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!} 441 // by forcing P=0, W=0 (postindex=true). 442 return arm_decodeArg(arm_arg_mem_R_pm_R_shift_imm_W, x&^(1<<24|1<<21)) 443 444 case arm_arg_mem_R_pm_R_shift_imm_W: 445 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) 446 Rm := arm_Reg(x & (1<<4 - 1)) 447 typ, count := arm_decodeShift(x) 448 u := (x >> 23) & 1 449 w := (x >> 21) & 1 450 p := (x >> 24) & 1 451 if p == 0 && w == 1 { 452 return nil 453 } 454 sign := int8(+1) 455 if u == 0 { 456 sign = -1 457 } 458 mode := arm_AddrMode(uint8(p<<1) | uint8(w^1)) 459 return arm_Mem{Base: Rn, Mode: mode, Sign: sign, Index: Rm, Shift: typ, Count: count} 460 461 case arm_arg_mem_R_pm_imm12_offset: 462 // Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!} 463 // by forcing P=1, W=0 (index=false, wback=false). 464 return arm_decodeArg(arm_arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24) 465 466 case arm_arg_mem_R_pm_imm12_postindex: 467 // Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!} 468 // by forcing P=0, W=0 (postindex=true). 469 return arm_decodeArg(arm_arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21)) 470 471 case arm_arg_mem_R_pm_imm12_W: 472 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) 473 u := (x >> 23) & 1 474 w := (x >> 21) & 1 475 p := (x >> 24) & 1 476 if p == 0 && w == 1 { 477 return nil 478 } 479 sign := int8(+1) 480 if u == 0 { 481 sign = -1 482 } 483 imm := int16(x & (1<<12 - 1)) 484 mode := arm_AddrMode(uint8(p<<1) | uint8(w^1)) 485 return arm_Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} 486 487 case arm_arg_mem_R_pm_imm8_postindex: 488 // Treat [<Rn>],#+/-<imm8> like [<Rn>{,#+/-<imm8>}]{!} 489 // by forcing P=0, W=0 (postindex=true). 490 return arm_decodeArg(arm_arg_mem_R_pm_imm8_W, x&^(1<<24|1<<21)) 491 492 case arm_arg_mem_R_pm_imm8_W: 493 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) 494 u := (x >> 23) & 1 495 w := (x >> 21) & 1 496 p := (x >> 24) & 1 497 if p == 0 && w == 1 { 498 return nil 499 } 500 sign := int8(+1) 501 if u == 0 { 502 sign = -1 503 } 504 imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1)) 505 mode := arm_AddrMode(uint8(p<<1) | uint8(w^1)) 506 return arm_Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm} 507 508 case arm_arg_mem_R_pm_imm8at0_offset: 509 Rn := arm_Reg((x >> 16) & (1<<4 - 1)) 510 u := (x >> 23) & 1 511 sign := int8(+1) 512 if u == 0 { 513 sign = -1 514 } 515 imm := int16(x&(1<<8-1)) << 2 516 return arm_Mem{Base: Rn, Mode: arm_AddrOffset, Offset: int16(sign) * imm} 517 518 case arm_arg_option: 519 return arm_Imm(x & (1<<4 - 1)) 520 521 case arm_arg_registers: 522 return arm_RegList(x & (1<<16 - 1)) 523 524 case arm_arg_registers2: 525 x &= 1<<16 - 1 526 n := 0 527 for i := 0; i < 16; i++ { 528 if x>>uint(i)&1 != 0 { 529 n++ 530 } 531 } 532 if n < 2 { 533 return nil 534 } 535 return arm_RegList(x) 536 537 case arm_arg_registers1: 538 Rt := (x >> 12) & (1<<4 - 1) 539 return arm_RegList(1 << Rt) 540 541 case arm_arg_satimm4: 542 return arm_Imm((x >> 16) & (1<<4 - 1)) 543 544 case arm_arg_satimm5: 545 return arm_Imm((x >> 16) & (1<<5 - 1)) 546 547 case arm_arg_satimm4m1: 548 return arm_Imm((x>>16)&(1<<4-1) + 1) 549 550 case arm_arg_satimm5m1: 551 return arm_Imm((x>>16)&(1<<5-1) + 1) 552 553 case arm_arg_widthm1: 554 return arm_Imm((x>>16)&(1<<5-1) + 1) 555 556 } 557 } 558 559 // decodeShift decodes the shift-by-immediate encoded in x. 560 func arm_decodeShift(x uint32) (arm_Shift, uint8) { 561 count := (x >> 7) & (1<<5 - 1) 562 typ := arm_Shift((x >> 5) & (1<<2 - 1)) 563 switch typ { 564 case arm_ShiftRight, arm_ShiftRightSigned: 565 if count == 0 { 566 count = 32 567 } 568 case arm_RotateRight: 569 if count == 0 { 570 typ = arm_RotateRightExt 571 count = 1 572 } 573 } 574 return typ, uint8(count) 575 } 576 577 /* gnu.go */ 578 579 // Copyright 2014 The Go Authors. All rights reserved. 580 // Use of this source code is governed by a BSD-style 581 // license that can be found in the LICENSE file. 582 583 var arm_saveDot = strings.NewReplacer( 584 ".F16", "_dot_F16", 585 ".F32", "_dot_F32", 586 ".F64", "_dot_F64", 587 ".S32", "_dot_S32", 588 ".U32", "_dot_U32", 589 ".FXS", "_dot_S", 590 ".FXU", "_dot_U", 591 ".32", "_dot_32", 592 ) 593 594 // GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. 595 // This form typically matches the syntax defined in the ARM Reference Manual. 596 func arm_GNUSyntax(inst arm_Inst) string { 597 var buf bytes.Buffer 598 op := inst.Op.String() 599 op = arm_saveDot.Replace(op) 600 op = strings.Replace(op, ".", "", -1) 601 op = strings.Replace(op, "_dot_", ".", -1) 602 op = strings.ToLower(op) 603 buf.WriteString(op) 604 sep := " " 605 for i, arg := range inst.Args { 606 if arg == nil { 607 break 608 } 609 text := arm_gnuArg(&inst, i, arg) 610 if text == "" { 611 continue 612 } 613 buf.WriteString(sep) 614 sep = ", " 615 buf.WriteString(text) 616 } 617 return buf.String() 618 } 619 620 func arm_gnuArg(inst *arm_Inst, argIndex int, arg arm_Arg) string { 621 switch inst.Op &^ 15 { 622 case arm_LDRD_EQ, arm_LDREXD_EQ, arm_STRD_EQ: 623 if argIndex == 1 { 624 // second argument in consecutive pair not printed 625 return "" 626 } 627 case arm_STREXD_EQ: 628 if argIndex == 2 { 629 // second argument in consecutive pair not printed 630 return "" 631 } 632 } 633 634 switch arg := arg.(type) { 635 case arm_Imm: 636 switch inst.Op &^ 15 { 637 case arm_BKPT_EQ: 638 return fmt.Sprintf("%#04x", uint32(arg)) 639 case arm_SVC_EQ: 640 return fmt.Sprintf("%#08x", uint32(arg)) 641 } 642 return fmt.Sprintf("#%d", int32(arg)) 643 644 case arm_ImmAlt: 645 return fmt.Sprintf("#%d, %d", arg.Val, arg.Rot) 646 647 case arm_Mem: 648 R := arm_gnuArg(inst, -1, arg.Base) 649 X := "" 650 if arg.Sign != 0 { 651 X = "" 652 if arg.Sign < 0 { 653 X = "-" 654 } 655 X += arm_gnuArg(inst, -1, arg.Index) 656 if arg.Shift == arm_ShiftLeft && arg.Count == 0 { 657 // nothing 658 } else if arg.Shift == arm_RotateRightExt { 659 X += ", rrx" 660 } else { 661 X += fmt.Sprintf(", %s #%d", strings.ToLower(arg.Shift.String()), arg.Count) 662 } 663 } else { 664 X = fmt.Sprintf("#%d", arg.Offset) 665 } 666 667 switch arg.Mode { 668 case arm_AddrOffset: 669 if X == "#0" { 670 return fmt.Sprintf("[%s]", R) 671 } 672 return fmt.Sprintf("[%s, %s]", R, X) 673 case arm_AddrPreIndex: 674 return fmt.Sprintf("[%s, %s]!", R, X) 675 case arm_AddrPostIndex: 676 return fmt.Sprintf("[%s], %s", R, X) 677 case arm_AddrLDM: 678 if X == "#0" { 679 return R 680 } 681 case arm_AddrLDM_WB: 682 if X == "#0" { 683 return R + "!" 684 } 685 } 686 return fmt.Sprintf("[%s Mode(%d) %s]", R, int(arg.Mode), X) 687 688 case arm_PCRel: 689 return fmt.Sprintf(".%+#x", int32(arg)+4) 690 691 case arm_Reg: 692 switch inst.Op &^ 15 { 693 case arm_LDREX_EQ: 694 if argIndex == 0 { 695 return fmt.Sprintf("r%d", int32(arg)) 696 } 697 } 698 switch arg { 699 case arm_R10: 700 return "sl" 701 case arm_R11: 702 return "fp" 703 case arm_R12: 704 return "ip" 705 } 706 707 case arm_RegList: 708 var buf bytes.Buffer 709 fmt.Fprintf(&buf, "{") 710 sep := "" 711 for i := 0; i < 16; i++ { 712 if arg&(1<<uint(i)) != 0 { 713 fmt.Fprintf(&buf, "%s%s", sep, arm_gnuArg(inst, -1, arm_Reg(i))) 714 sep = ", " 715 } 716 } 717 fmt.Fprintf(&buf, "}") 718 return buf.String() 719 720 case arm_RegShift: 721 if arg.Shift == arm_ShiftLeft && arg.Count == 0 { 722 return arm_gnuArg(inst, -1, arg.Reg) 723 } 724 if arg.Shift == arm_RotateRightExt { 725 return arm_gnuArg(inst, -1, arg.Reg) + ", rrx" 726 } 727 return fmt.Sprintf("%s, %s #%d", arm_gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), arg.Count) 728 729 case arm_RegShiftReg: 730 return fmt.Sprintf("%s, %s %s", arm_gnuArg(inst, -1, arg.Reg), strings.ToLower(arg.Shift.String()), arm_gnuArg(inst, -1, arg.RegCount)) 731 732 } 733 return strings.ToLower(arg.String()) 734 } 735 736 /* inst.go */ 737 738 // Copyright 2014 The Go Authors. All rights reserved. 739 // Use of this source code is governed by a BSD-style 740 // license that can be found in the LICENSE file. 741 742 // A Mode is an instruction execution mode. 743 type arm_Mode int 744 745 const ( 746 _ arm_Mode = iota 747 arm_ModeARM 748 arm_ModeThumb 749 ) 750 751 func (m arm_Mode) String() string { 752 switch m { 753 case arm_ModeARM: 754 return "ARM" 755 case arm_ModeThumb: 756 return "Thumb" 757 } 758 return fmt.Sprintf("Mode(%d)", int(m)) 759 } 760 761 // An Op is an ARM opcode. 762 type arm_Op uint16 763 764 // NOTE: The actual Op values are defined in tables.go. 765 // They are chosen to simplify instruction decoding and 766 // are not a dense packing from 0 to N, although the 767 // density is high, probably at least 90%. 768 769 func (op arm_Op) String() string { 770 if op >= arm_Op(len(arm_opstr)) || arm_opstr[op] == "" { 771 return fmt.Sprintf("Op(%d)", int(op)) 772 } 773 return arm_opstr[op] 774 } 775 776 // An Inst is a single instruction. 777 type arm_Inst struct { 778 Op arm_Op // Opcode mnemonic 779 Enc uint32 // Raw encoding bits. 780 Len int // Length of encoding in bytes. 781 Args arm_Args // Instruction arguments, in ARM manual order. 782 } 783 784 func (i arm_Inst) String() string { 785 var buf bytes.Buffer 786 buf.WriteString(i.Op.String()) 787 for j, arg := range i.Args { 788 if arg == nil { 789 break 790 } 791 if j == 0 { 792 buf.WriteString(" ") 793 } else { 794 buf.WriteString(", ") 795 } 796 buf.WriteString(arg.String()) 797 } 798 return buf.String() 799 } 800 801 // An Args holds the instruction arguments. 802 // If an instruction has fewer than 4 arguments, 803 // the final elements in the array are nil. 804 type arm_Args [4]arm_Arg 805 806 // An Arg is a single instruction argument, one of these types: 807 // Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg. 808 type arm_Arg interface { 809 IsArg() 810 String() string 811 } 812 813 type arm_Float32Imm float32 814 815 func (arm_Float32Imm) IsArg() {} 816 817 func (f arm_Float32Imm) String() string { 818 return fmt.Sprintf("#%v", float32(f)) 819 } 820 821 type arm_Float64Imm float32 822 823 func (arm_Float64Imm) IsArg() {} 824 825 func (f arm_Float64Imm) String() string { 826 return fmt.Sprintf("#%v", float64(f)) 827 } 828 829 // An Imm is an integer constant. 830 type arm_Imm uint32 831 832 func (arm_Imm) IsArg() {} 833 834 func (i arm_Imm) String() string { 835 return fmt.Sprintf("#%#x", uint32(i)) 836 } 837 838 // A ImmAlt is an alternate encoding of an integer constant. 839 type arm_ImmAlt struct { 840 Val uint8 841 Rot uint8 842 } 843 844 func (arm_ImmAlt) IsArg() {} 845 846 func (i arm_ImmAlt) Imm() arm_Imm { 847 v := uint32(i.Val) 848 r := uint(i.Rot) 849 return arm_Imm(v>>r | v<<(32-r)) 850 } 851 852 func (i arm_ImmAlt) String() string { 853 return fmt.Sprintf("#%#x, %d", i.Val, i.Rot) 854 } 855 856 // A Label is a text (code) address. 857 type arm_Label uint32 858 859 func (arm_Label) IsArg() {} 860 861 func (i arm_Label) String() string { 862 return fmt.Sprintf("%#x", uint32(i)) 863 } 864 865 // A Reg is a single register. 866 // The zero value denotes R0, not the absence of a register. 867 type arm_Reg uint8 868 869 const ( 870 arm_R0 arm_Reg = iota 871 arm_R1 872 arm_R2 873 arm_R3 874 arm_R4 875 arm_R5 876 arm_R6 877 arm_R7 878 arm_R8 879 arm_R9 880 arm_R10 881 arm_R11 882 arm_R12 883 arm_R13 884 arm_R14 885 arm_R15 886 887 arm_S0 888 arm_S1 889 arm_S2 890 arm_S3 891 arm_S4 892 arm_S5 893 arm_S6 894 arm_S7 895 arm_S8 896 arm_S9 897 arm_S10 898 arm_S11 899 arm_S12 900 arm_S13 901 arm_S14 902 arm_S15 903 arm_S16 904 arm_S17 905 arm_S18 906 arm_S19 907 arm_S20 908 arm_S21 909 arm_S22 910 arm_S23 911 arm_S24 912 arm_S25 913 arm_S26 914 arm_S27 915 arm_S28 916 arm_S29 917 arm_S30 918 arm_S31 919 920 arm_D0 921 arm_D1 922 arm_D2 923 arm_D3 924 arm_D4 925 arm_D5 926 arm_D6 927 arm_D7 928 arm_D8 929 arm_D9 930 arm_D10 931 arm_D11 932 arm_D12 933 arm_D13 934 arm_D14 935 arm_D15 936 arm_D16 937 arm_D17 938 arm_D18 939 arm_D19 940 arm_D20 941 arm_D21 942 arm_D22 943 arm_D23 944 arm_D24 945 arm_D25 946 arm_D26 947 arm_D27 948 arm_D28 949 arm_D29 950 arm_D30 951 arm_D31 952 953 arm_APSR 954 arm_APSR_nzcv 955 arm_FPSCR 956 957 arm_SP = arm_R13 958 arm_LR = arm_R14 959 arm_PC = arm_R15 960 ) 961 962 func (arm_Reg) IsArg() {} 963 964 func (r arm_Reg) String() string { 965 switch r { 966 case arm_APSR: 967 return "APSR" 968 case arm_APSR_nzcv: 969 return "APSR_nzcv" 970 case arm_FPSCR: 971 return "FPSCR" 972 case arm_SP: 973 return "SP" 974 case arm_PC: 975 return "PC" 976 case arm_LR: 977 return "LR" 978 } 979 if arm_R0 <= r && r <= arm_R15 { 980 return fmt.Sprintf("R%d", int(r-arm_R0)) 981 } 982 if arm_S0 <= r && r <= arm_S31 { 983 return fmt.Sprintf("S%d", int(r-arm_S0)) 984 } 985 if arm_D0 <= r && r <= arm_D31 { 986 return fmt.Sprintf("D%d", int(r-arm_D0)) 987 } 988 return fmt.Sprintf("Reg(%d)", int(r)) 989 } 990 991 // A RegX represents a fraction of a multi-value register. 992 // The Index field specifies the index number, 993 // but the size of the fraction is not specified. 994 // It must be inferred from the instruction and the register type. 995 // For example, in a VMOV instruction, RegX{D5, 1} represents 996 // the top 32 bits of the 64-bit D5 register. 997 type arm_RegX struct { 998 Reg arm_Reg 999 Index int 1000 } 1001 1002 func (arm_RegX) IsArg() {} 1003 1004 func (r arm_RegX) String() string { 1005 return fmt.Sprintf("%s[%d]", r.Reg, r.Index) 1006 } 1007 1008 // A RegList is a register list. 1009 // Bits at indexes x = 0 through 15 indicate whether the corresponding Rx register is in the list. 1010 type arm_RegList uint16 1011 1012 func (arm_RegList) IsArg() {} 1013 1014 func (r arm_RegList) String() string { 1015 var buf bytes.Buffer 1016 fmt.Fprintf(&buf, "{") 1017 sep := "" 1018 for i := 0; i < 16; i++ { 1019 if r&(1<<uint(i)) != 0 { 1020 fmt.Fprintf(&buf, "%s%s", sep, arm_Reg(i).String()) 1021 sep = "," 1022 } 1023 } 1024 fmt.Fprintf(&buf, "}") 1025 return buf.String() 1026 } 1027 1028 // An Endian is the argument to the SETEND instruction. 1029 type arm_Endian uint8 1030 1031 const ( 1032 arm_LittleEndian arm_Endian = 0 1033 arm_BigEndian arm_Endian = 1 1034 ) 1035 1036 func (arm_Endian) IsArg() {} 1037 1038 func (e arm_Endian) String() string { 1039 if e != 0 { 1040 return "BE" 1041 } 1042 return "LE" 1043 } 1044 1045 // A Shift describes an ARM shift operation. 1046 type arm_Shift uint8 1047 1048 const ( 1049 arm_ShiftLeft arm_Shift = 0 // left shift 1050 arm_ShiftRight arm_Shift = 1 // logical (unsigned) right shift 1051 arm_ShiftRightSigned arm_Shift = 2 // arithmetic (signed) right shift 1052 arm_RotateRight arm_Shift = 3 // right rotate 1053 arm_RotateRightExt arm_Shift = 4 // right rotate through carry (Count will always be 1) 1054 ) 1055 1056 var arm_shiftName = [...]string{ 1057 "LSL", "LSR", "ASR", "ROR", "RRX", 1058 } 1059 1060 func (s arm_Shift) String() string { 1061 if s < 5 { 1062 return arm_shiftName[s] 1063 } 1064 return fmt.Sprintf("Shift(%d)", int(s)) 1065 } 1066 1067 // A RegShift is a register shifted by a constant. 1068 type arm_RegShift struct { 1069 Reg arm_Reg 1070 Shift arm_Shift 1071 Count uint8 1072 } 1073 1074 func (arm_RegShift) IsArg() {} 1075 1076 func (r arm_RegShift) String() string { 1077 return fmt.Sprintf("%s %s #%d", r.Reg, r.Shift, r.Count) 1078 } 1079 1080 // A RegShiftReg is a register shifted by a register. 1081 type arm_RegShiftReg struct { 1082 Reg arm_Reg 1083 Shift arm_Shift 1084 RegCount arm_Reg 1085 } 1086 1087 func (arm_RegShiftReg) IsArg() {} 1088 1089 func (r arm_RegShiftReg) String() string { 1090 return fmt.Sprintf("%s %s %s", r.Reg, r.Shift, r.RegCount) 1091 } 1092 1093 // A PCRel describes a memory address (usually a code label) 1094 // as a distance relative to the program counter. 1095 // TODO(rsc): Define which program counter (PC+4? PC+8? PC?). 1096 type arm_PCRel int32 1097 1098 func (arm_PCRel) IsArg() {} 1099 1100 func (r arm_PCRel) String() string { 1101 return fmt.Sprintf("PC%+#x", int32(r)) 1102 } 1103 1104 // An AddrMode is an ARM addressing mode. 1105 type arm_AddrMode uint8 1106 1107 const ( 1108 _ arm_AddrMode = iota 1109 arm_AddrPostIndex // [R], X – use address R, set R = R + X 1110 arm_AddrPreIndex // [R, X]! – use address R + X, set R = R + X 1111 arm_AddrOffset // [R, X] – use address R + X 1112 arm_AddrLDM // R – [R] but formats as R, for LDM/STM only 1113 arm_AddrLDM_WB // R! - [R], X where X is instruction-specific amount, for LDM/STM only 1114 ) 1115 1116 // A Mem is a memory reference made up of a base R and index expression X. 1117 // The effective memory address is R or R+X depending on AddrMode. 1118 // The index expression is X = Sign*(Index Shift Count) + Offset, 1119 // but in any instruction either Sign = 0 or Offset = 0. 1120 type arm_Mem struct { 1121 Base arm_Reg 1122 Mode arm_AddrMode 1123 Sign int8 1124 Index arm_Reg 1125 Shift arm_Shift 1126 Count uint8 1127 Offset int16 1128 } 1129 1130 func (arm_Mem) IsArg() {} 1131 1132 func (m arm_Mem) String() string { 1133 R := m.Base.String() 1134 X := "" 1135 if m.Sign != 0 { 1136 X = "+" 1137 if m.Sign < 0 { 1138 X = "-" 1139 } 1140 X += m.Index.String() 1141 if m.Shift != arm_ShiftLeft || m.Count != 0 { 1142 X += fmt.Sprintf(", %s #%d", m.Shift, m.Count) 1143 } 1144 } else { 1145 X = fmt.Sprintf("#%d", m.Offset) 1146 } 1147 1148 switch m.Mode { 1149 case arm_AddrOffset: 1150 if X == "#0" { 1151 return fmt.Sprintf("[%s]", R) 1152 } 1153 return fmt.Sprintf("[%s, %s]", R, X) 1154 case arm_AddrPreIndex: 1155 return fmt.Sprintf("[%s, %s]!", R, X) 1156 case arm_AddrPostIndex: 1157 return fmt.Sprintf("[%s], %s", R, X) 1158 case arm_AddrLDM: 1159 if X == "#0" { 1160 return R 1161 } 1162 case arm_AddrLDM_WB: 1163 if X == "#0" { 1164 return R + "!" 1165 } 1166 } 1167 return fmt.Sprintf("[%s Mode(%d) %s]", R, int(m.Mode), X) 1168 } 1169 1170 /* plan9x.go */ 1171 1172 // Copyright 2014 The Go Authors. All rights reserved. 1173 // Use of this source code is governed by a BSD-style 1174 // license that can be found in the LICENSE file. 1175 1176 // plan9Syntax returns the Go assembler syntax for the instruction. 1177 // The syntax was originally defined by Plan 9. 1178 // The pc is the program counter of the instruction, used for expanding 1179 // PC-relative addresses into absolute ones. 1180 // The symname function queries the symbol table for the program 1181 // being disassembled. Given a target address it returns the name and base 1182 // address of the symbol containing the target, if any; otherwise it returns "", 0. 1183 // The reader r should read from the text segment using text addresses 1184 // as offsets; it is used to display pc-relative loads as constant loads. 1185 func arm_plan9Syntax(inst arm_Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string { 1186 if symname == nil { 1187 symname = func(uint64) (string, uint64) { return "", 0 } 1188 } 1189 1190 var args []string 1191 for _, a := range inst.Args { 1192 if a == nil { 1193 break 1194 } 1195 args = append(args, arm_plan9Arg(&inst, pc, symname, a)) 1196 } 1197 1198 op := inst.Op.String() 1199 1200 switch inst.Op &^ 15 { 1201 case arm_LDR_EQ, arm_LDRB_EQ, arm_LDRH_EQ: 1202 // Check for RET 1203 reg, _ := inst.Args[0].(arm_Reg) 1204 mem, _ := inst.Args[1].(arm_Mem) 1205 if inst.Op&^15 == arm_LDR_EQ && reg == arm_R15 && mem.Base == arm_SP && mem.Sign == 0 && mem.Mode == arm_AddrPostIndex { 1206 return fmt.Sprintf("RET%s #%d", op[3:], mem.Offset) 1207 } 1208 1209 // Check for PC-relative load. 1210 if mem.Base == arm_PC && mem.Sign == 0 && mem.Mode == arm_AddrOffset && text != nil { 1211 addr := uint32(pc) + 8 + uint32(mem.Offset) 1212 buf := make([]byte, 4) 1213 switch inst.Op &^ 15 { 1214 case arm_LDRB_EQ: 1215 if _, err := text.ReadAt(buf[:1], int64(addr)); err != nil { 1216 break 1217 } 1218 args[1] = fmt.Sprintf("$%#x", buf[0]) 1219 1220 case arm_LDRH_EQ: 1221 if _, err := text.ReadAt(buf[:2], int64(addr)); err != nil { 1222 break 1223 } 1224 args[1] = fmt.Sprintf("$%#x", binary.LittleEndian.Uint16(buf)) 1225 1226 case arm_LDR_EQ: 1227 if _, err := text.ReadAt(buf, int64(addr)); err != nil { 1228 break 1229 } 1230 x := binary.LittleEndian.Uint32(buf) 1231 if s, base := symname(uint64(x)); s != "" && uint64(x) == base { 1232 args[1] = fmt.Sprintf("$%s(SB)", s) 1233 } else { 1234 args[1] = fmt.Sprintf("$%#x", x) 1235 } 1236 } 1237 } 1238 } 1239 1240 // Move addressing mode into opcode suffix. 1241 suffix := "" 1242 switch inst.Op &^ 15 { 1243 case arm_LDR_EQ, arm_LDRB_EQ, arm_LDRH_EQ, arm_STR_EQ, arm_STRB_EQ, arm_STRH_EQ: 1244 mem, _ := inst.Args[1].(arm_Mem) 1245 switch mem.Mode { 1246 case arm_AddrOffset, arm_AddrLDM: 1247 // no suffix 1248 case arm_AddrPreIndex, arm_AddrLDM_WB: 1249 suffix = ".W" 1250 case arm_AddrPostIndex: 1251 suffix = ".P" 1252 } 1253 off := "" 1254 if mem.Offset != 0 { 1255 off = fmt.Sprintf("%#x", mem.Offset) 1256 } 1257 base := fmt.Sprintf("(R%d)", int(mem.Base)) 1258 index := "" 1259 if mem.Sign != 0 { 1260 sign := "" 1261 if mem.Sign < 0 { 1262 sign = "" 1263 } 1264 shift := "" 1265 if mem.Count != 0 { 1266 shift = fmt.Sprintf("%s%d", arm_plan9Shift[mem.Shift], mem.Count) 1267 } 1268 index = fmt.Sprintf("(%sR%d%s)", sign, int(mem.Index), shift) 1269 } 1270 args[1] = off + base + index 1271 } 1272 1273 // Reverse args, placing dest last. 1274 for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { 1275 args[i], args[j] = args[j], args[i] 1276 } 1277 1278 switch inst.Op &^ 15 { 1279 case arm_MOV_EQ: 1280 op = "MOVW" + op[3:] 1281 1282 case arm_LDR_EQ: 1283 op = "MOVW" + op[3:] + suffix 1284 case arm_LDRB_EQ: 1285 op = "MOVB" + op[4:] + suffix 1286 case arm_LDRH_EQ: 1287 op = "MOVH" + op[4:] + suffix 1288 1289 case arm_STR_EQ: 1290 op = "MOVW" + op[3:] + suffix 1291 args[0], args[1] = args[1], args[0] 1292 case arm_STRB_EQ: 1293 op = "MOVB" + op[4:] + suffix 1294 args[0], args[1] = args[1], args[0] 1295 case arm_STRH_EQ: 1296 op = "MOVH" + op[4:] + suffix 1297 args[0], args[1] = args[1], args[0] 1298 } 1299 1300 if args != nil { 1301 op += " " + strings.Join(args, ", ") 1302 } 1303 1304 return op 1305 } 1306 1307 // assembler syntax for the various shifts. 1308 // @x> is a lie; the assembler uses @> 0 1309 // instead of @x> 1, but i wanted to be clear that it 1310 // was a different operation (rotate right extended, not rotate right). 1311 var arm_plan9Shift = []string{"<<", ">>", "->", "@>", "@x>"} 1312 1313 func arm_plan9Arg(inst *arm_Inst, pc uint64, symname func(uint64) (string, uint64), arg arm_Arg) string { 1314 switch a := arg.(type) { 1315 case arm_Endian: 1316 1317 case arm_Imm: 1318 return fmt.Sprintf("$%d", int(a)) 1319 1320 case arm_Mem: 1321 1322 case arm_PCRel: 1323 addr := uint32(pc) + 8 + uint32(a) 1324 if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base { 1325 return fmt.Sprintf("%s(SB)", s) 1326 } 1327 return fmt.Sprintf("%#x", addr) 1328 1329 case arm_Reg: 1330 if a < 16 { 1331 return fmt.Sprintf("R%d", int(a)) 1332 } 1333 1334 case arm_RegList: 1335 var buf bytes.Buffer 1336 start := -2 1337 end := -2 1338 fmt.Fprintf(&buf, "[") 1339 flush := func() { 1340 if start >= 0 { 1341 if buf.Len() > 1 { 1342 fmt.Fprintf(&buf, ",") 1343 } 1344 if start == end { 1345 fmt.Fprintf(&buf, "R%d", start) 1346 } else { 1347 fmt.Fprintf(&buf, "R%d-R%d", start, end) 1348 } 1349 } 1350 } 1351 for i := 0; i < 16; i++ { 1352 if a&(1<<uint(i)) != 0 { 1353 if i == end+1 { 1354 end++ 1355 continue 1356 } 1357 start = i 1358 end = i 1359 } 1360 } 1361 flush() 1362 fmt.Fprintf(&buf, "]") 1363 return buf.String() 1364 1365 case arm_RegShift: 1366 return fmt.Sprintf("R%d%s$%d", int(a.Reg), arm_plan9Shift[a.Shift], int(a.Count)) 1367 1368 case arm_RegShiftReg: 1369 return fmt.Sprintf("R%d%sR%d", int(a.Reg), arm_plan9Shift[a.Shift], int(a.RegCount)) 1370 } 1371 return strings.ToUpper(arg.String()) 1372 } 1373 1374 /* tables.go */ 1375 1376 const ( 1377 _ arm_Op = iota 1378 _ 1379 _ 1380 _ 1381 _ 1382 _ 1383 _ 1384 _ 1385 _ 1386 _ 1387 _ 1388 _ 1389 _ 1390 _ 1391 _ 1392 _ 1393 arm_ADC_EQ 1394 arm_ADC_NE 1395 arm_ADC_CS 1396 arm_ADC_CC 1397 arm_ADC_MI 1398 arm_ADC_PL 1399 arm_ADC_VS 1400 arm_ADC_VC 1401 arm_ADC_HI 1402 arm_ADC_LS 1403 arm_ADC_GE 1404 arm_ADC_LT 1405 arm_ADC_GT 1406 arm_ADC_LE 1407 arm_ADC 1408 arm_ADC_ZZ 1409 arm_ADC_S_EQ 1410 arm_ADC_S_NE 1411 arm_ADC_S_CS 1412 arm_ADC_S_CC 1413 arm_ADC_S_MI 1414 arm_ADC_S_PL 1415 arm_ADC_S_VS 1416 arm_ADC_S_VC 1417 arm_ADC_S_HI 1418 arm_ADC_S_LS 1419 arm_ADC_S_GE 1420 arm_ADC_S_LT 1421 arm_ADC_S_GT 1422 arm_ADC_S_LE 1423 arm_ADC_S 1424 arm_ADC_S_ZZ 1425 arm_ADD_EQ 1426 arm_ADD_NE 1427 arm_ADD_CS 1428 arm_ADD_CC 1429 arm_ADD_MI 1430 arm_ADD_PL 1431 arm_ADD_VS 1432 arm_ADD_VC 1433 arm_ADD_HI 1434 arm_ADD_LS 1435 arm_ADD_GE 1436 arm_ADD_LT 1437 arm_ADD_GT 1438 arm_ADD_LE 1439 arm_ADD 1440 arm_ADD_ZZ 1441 arm_ADD_S_EQ 1442 arm_ADD_S_NE 1443 arm_ADD_S_CS 1444 arm_ADD_S_CC 1445 arm_ADD_S_MI 1446 arm_ADD_S_PL 1447 arm_ADD_S_VS 1448 arm_ADD_S_VC 1449 arm_ADD_S_HI 1450 arm_ADD_S_LS 1451 arm_ADD_S_GE 1452 arm_ADD_S_LT 1453 arm_ADD_S_GT 1454 arm_ADD_S_LE 1455 arm_ADD_S 1456 arm_ADD_S_ZZ 1457 arm_AND_EQ 1458 arm_AND_NE 1459 arm_AND_CS 1460 arm_AND_CC 1461 arm_AND_MI 1462 arm_AND_PL 1463 arm_AND_VS 1464 arm_AND_VC 1465 arm_AND_HI 1466 arm_AND_LS 1467 arm_AND_GE 1468 arm_AND_LT 1469 arm_AND_GT 1470 arm_AND_LE 1471 arm_AND 1472 arm_AND_ZZ 1473 arm_AND_S_EQ 1474 arm_AND_S_NE 1475 arm_AND_S_CS 1476 arm_AND_S_CC 1477 arm_AND_S_MI 1478 arm_AND_S_PL 1479 arm_AND_S_VS 1480 arm_AND_S_VC 1481 arm_AND_S_HI 1482 arm_AND_S_LS 1483 arm_AND_S_GE 1484 arm_AND_S_LT 1485 arm_AND_S_GT 1486 arm_AND_S_LE 1487 arm_AND_S 1488 arm_AND_S_ZZ 1489 arm_ASR_EQ 1490 arm_ASR_NE 1491 arm_ASR_CS 1492 arm_ASR_CC 1493 arm_ASR_MI 1494 arm_ASR_PL 1495 arm_ASR_VS 1496 arm_ASR_VC 1497 arm_ASR_HI 1498 arm_ASR_LS 1499 arm_ASR_GE 1500 arm_ASR_LT 1501 arm_ASR_GT 1502 arm_ASR_LE 1503 arm_ASR 1504 arm_ASR_ZZ 1505 arm_ASR_S_EQ 1506 arm_ASR_S_NE 1507 arm_ASR_S_CS 1508 arm_ASR_S_CC 1509 arm_ASR_S_MI 1510 arm_ASR_S_PL 1511 arm_ASR_S_VS 1512 arm_ASR_S_VC 1513 arm_ASR_S_HI 1514 arm_ASR_S_LS 1515 arm_ASR_S_GE 1516 arm_ASR_S_LT 1517 arm_ASR_S_GT 1518 arm_ASR_S_LE 1519 arm_ASR_S 1520 arm_ASR_S_ZZ 1521 arm_B_EQ 1522 arm_B_NE 1523 arm_B_CS 1524 arm_B_CC 1525 arm_B_MI 1526 arm_B_PL 1527 arm_B_VS 1528 arm_B_VC 1529 arm_B_HI 1530 arm_B_LS 1531 arm_B_GE 1532 arm_B_LT 1533 arm_B_GT 1534 arm_B_LE 1535 arm_B 1536 arm_B_ZZ 1537 arm_BFC_EQ 1538 arm_BFC_NE 1539 arm_BFC_CS 1540 arm_BFC_CC 1541 arm_BFC_MI 1542 arm_BFC_PL 1543 arm_BFC_VS 1544 arm_BFC_VC 1545 arm_BFC_HI 1546 arm_BFC_LS 1547 arm_BFC_GE 1548 arm_BFC_LT 1549 arm_BFC_GT 1550 arm_BFC_LE 1551 arm_BFC 1552 arm_BFC_ZZ 1553 arm_BFI_EQ 1554 arm_BFI_NE 1555 arm_BFI_CS 1556 arm_BFI_CC 1557 arm_BFI_MI 1558 arm_BFI_PL 1559 arm_BFI_VS 1560 arm_BFI_VC 1561 arm_BFI_HI 1562 arm_BFI_LS 1563 arm_BFI_GE 1564 arm_BFI_LT 1565 arm_BFI_GT 1566 arm_BFI_LE 1567 arm_BFI 1568 arm_BFI_ZZ 1569 arm_BIC_EQ 1570 arm_BIC_NE 1571 arm_BIC_CS 1572 arm_BIC_CC 1573 arm_BIC_MI 1574 arm_BIC_PL 1575 arm_BIC_VS 1576 arm_BIC_VC 1577 arm_BIC_HI 1578 arm_BIC_LS 1579 arm_BIC_GE 1580 arm_BIC_LT 1581 arm_BIC_GT 1582 arm_BIC_LE 1583 arm_BIC 1584 arm_BIC_ZZ 1585 arm_BIC_S_EQ 1586 arm_BIC_S_NE 1587 arm_BIC_S_CS 1588 arm_BIC_S_CC 1589 arm_BIC_S_MI 1590 arm_BIC_S_PL 1591 arm_BIC_S_VS 1592 arm_BIC_S_VC 1593 arm_BIC_S_HI 1594 arm_BIC_S_LS 1595 arm_BIC_S_GE 1596 arm_BIC_S_LT 1597 arm_BIC_S_GT 1598 arm_BIC_S_LE 1599 arm_BIC_S 1600 arm_BIC_S_ZZ 1601 arm_BKPT_EQ 1602 arm_BKPT_NE 1603 arm_BKPT_CS 1604 arm_BKPT_CC 1605 arm_BKPT_MI 1606 arm_BKPT_PL 1607 arm_BKPT_VS 1608 arm_BKPT_VC 1609 arm_BKPT_HI 1610 arm_BKPT_LS 1611 arm_BKPT_GE 1612 arm_BKPT_LT 1613 arm_BKPT_GT 1614 arm_BKPT_LE 1615 arm_BKPT 1616 arm_BKPT_ZZ 1617 arm_BL_EQ 1618 arm_BL_NE 1619 arm_BL_CS 1620 arm_BL_CC 1621 arm_BL_MI 1622 arm_BL_PL 1623 arm_BL_VS 1624 arm_BL_VC 1625 arm_BL_HI 1626 arm_BL_LS 1627 arm_BL_GE 1628 arm_BL_LT 1629 arm_BL_GT 1630 arm_BL_LE 1631 arm_BL 1632 arm_BL_ZZ 1633 arm_BLX_EQ 1634 arm_BLX_NE 1635 arm_BLX_CS 1636 arm_BLX_CC 1637 arm_BLX_MI 1638 arm_BLX_PL 1639 arm_BLX_VS 1640 arm_BLX_VC 1641 arm_BLX_HI 1642 arm_BLX_LS 1643 arm_BLX_GE 1644 arm_BLX_LT 1645 arm_BLX_GT 1646 arm_BLX_LE 1647 arm_BLX 1648 arm_BLX_ZZ 1649 arm_BX_EQ 1650 arm_BX_NE 1651 arm_BX_CS 1652 arm_BX_CC 1653 arm_BX_MI 1654 arm_BX_PL 1655 arm_BX_VS 1656 arm_BX_VC 1657 arm_BX_HI 1658 arm_BX_LS 1659 arm_BX_GE 1660 arm_BX_LT 1661 arm_BX_GT 1662 arm_BX_LE 1663 arm_BX 1664 arm_BX_ZZ 1665 arm_BXJ_EQ 1666 arm_BXJ_NE 1667 arm_BXJ_CS 1668 arm_BXJ_CC 1669 arm_BXJ_MI 1670 arm_BXJ_PL 1671 arm_BXJ_VS 1672 arm_BXJ_VC 1673 arm_BXJ_HI 1674 arm_BXJ_LS 1675 arm_BXJ_GE 1676 arm_BXJ_LT 1677 arm_BXJ_GT 1678 arm_BXJ_LE 1679 arm_BXJ 1680 arm_BXJ_ZZ 1681 arm_CLREX 1682 _ 1683 _ 1684 _ 1685 _ 1686 _ 1687 _ 1688 _ 1689 _ 1690 _ 1691 _ 1692 _ 1693 _ 1694 _ 1695 _ 1696 _ 1697 arm_CLZ_EQ 1698 arm_CLZ_NE 1699 arm_CLZ_CS 1700 arm_CLZ_CC 1701 arm_CLZ_MI 1702 arm_CLZ_PL 1703 arm_CLZ_VS 1704 arm_CLZ_VC 1705 arm_CLZ_HI 1706 arm_CLZ_LS 1707 arm_CLZ_GE 1708 arm_CLZ_LT 1709 arm_CLZ_GT 1710 arm_CLZ_LE 1711 arm_CLZ 1712 arm_CLZ_ZZ 1713 arm_CMN_EQ 1714 arm_CMN_NE 1715 arm_CMN_CS 1716 arm_CMN_CC 1717 arm_CMN_MI 1718 arm_CMN_PL 1719 arm_CMN_VS 1720 arm_CMN_VC 1721 arm_CMN_HI 1722 arm_CMN_LS 1723 arm_CMN_GE 1724 arm_CMN_LT 1725 arm_CMN_GT 1726 arm_CMN_LE 1727 arm_CMN 1728 arm_CMN_ZZ 1729 arm_CMP_EQ 1730 arm_CMP_NE 1731 arm_CMP_CS 1732 arm_CMP_CC 1733 arm_CMP_MI 1734 arm_CMP_PL 1735 arm_CMP_VS 1736 arm_CMP_VC 1737 arm_CMP_HI 1738 arm_CMP_LS 1739 arm_CMP_GE 1740 arm_CMP_LT 1741 arm_CMP_GT 1742 arm_CMP_LE 1743 arm_CMP 1744 arm_CMP_ZZ 1745 arm_DBG_EQ 1746 arm_DBG_NE 1747 arm_DBG_CS 1748 arm_DBG_CC 1749 arm_DBG_MI 1750 arm_DBG_PL 1751 arm_DBG_VS 1752 arm_DBG_VC 1753 arm_DBG_HI 1754 arm_DBG_LS 1755 arm_DBG_GE 1756 arm_DBG_LT 1757 arm_DBG_GT 1758 arm_DBG_LE 1759 arm_DBG 1760 arm_DBG_ZZ 1761 arm_DMB 1762 arm_DSB 1763 _ 1764 _ 1765 _ 1766 _ 1767 _ 1768 _ 1769 _ 1770 _ 1771 _ 1772 _ 1773 _ 1774 _ 1775 _ 1776 _ 1777 arm_EOR_EQ 1778 arm_EOR_NE 1779 arm_EOR_CS 1780 arm_EOR_CC 1781 arm_EOR_MI 1782 arm_EOR_PL 1783 arm_EOR_VS 1784 arm_EOR_VC 1785 arm_EOR_HI 1786 arm_EOR_LS 1787 arm_EOR_GE 1788 arm_EOR_LT 1789 arm_EOR_GT 1790 arm_EOR_LE 1791 arm_EOR 1792 arm_EOR_ZZ 1793 arm_EOR_S_EQ 1794 arm_EOR_S_NE 1795 arm_EOR_S_CS 1796 arm_EOR_S_CC 1797 arm_EOR_S_MI 1798 arm_EOR_S_PL 1799 arm_EOR_S_VS 1800 arm_EOR_S_VC 1801 arm_EOR_S_HI 1802 arm_EOR_S_LS 1803 arm_EOR_S_GE 1804 arm_EOR_S_LT 1805 arm_EOR_S_GT 1806 arm_EOR_S_LE 1807 arm_EOR_S 1808 arm_EOR_S_ZZ 1809 arm_ISB 1810 _ 1811 _ 1812 _ 1813 _ 1814 _ 1815 _ 1816 _ 1817 _ 1818 _ 1819 _ 1820 _ 1821 _ 1822 _ 1823 _ 1824 _ 1825 arm_LDM_EQ 1826 arm_LDM_NE 1827 arm_LDM_CS 1828 arm_LDM_CC 1829 arm_LDM_MI 1830 arm_LDM_PL 1831 arm_LDM_VS 1832 arm_LDM_VC 1833 arm_LDM_HI 1834 arm_LDM_LS 1835 arm_LDM_GE 1836 arm_LDM_LT 1837 arm_LDM_GT 1838 arm_LDM_LE 1839 arm_LDM 1840 arm_LDM_ZZ 1841 arm_LDMDA_EQ 1842 arm_LDMDA_NE 1843 arm_LDMDA_CS 1844 arm_LDMDA_CC 1845 arm_LDMDA_MI 1846 arm_LDMDA_PL 1847 arm_LDMDA_VS 1848 arm_LDMDA_VC 1849 arm_LDMDA_HI 1850 arm_LDMDA_LS 1851 arm_LDMDA_GE 1852 arm_LDMDA_LT 1853 arm_LDMDA_GT 1854 arm_LDMDA_LE 1855 arm_LDMDA 1856 arm_LDMDA_ZZ 1857 arm_LDMDB_EQ 1858 arm_LDMDB_NE 1859 arm_LDMDB_CS 1860 arm_LDMDB_CC 1861 arm_LDMDB_MI 1862 arm_LDMDB_PL 1863 arm_LDMDB_VS 1864 arm_LDMDB_VC 1865 arm_LDMDB_HI 1866 arm_LDMDB_LS 1867 arm_LDMDB_GE 1868 arm_LDMDB_LT 1869 arm_LDMDB_GT 1870 arm_LDMDB_LE 1871 arm_LDMDB 1872 arm_LDMDB_ZZ 1873 arm_LDMIB_EQ 1874 arm_LDMIB_NE 1875 arm_LDMIB_CS 1876 arm_LDMIB_CC 1877 arm_LDMIB_MI 1878 arm_LDMIB_PL 1879 arm_LDMIB_VS 1880 arm_LDMIB_VC 1881 arm_LDMIB_HI 1882 arm_LDMIB_LS 1883 arm_LDMIB_GE 1884 arm_LDMIB_LT 1885 arm_LDMIB_GT 1886 arm_LDMIB_LE 1887 arm_LDMIB 1888 arm_LDMIB_ZZ 1889 arm_LDR_EQ 1890 arm_LDR_NE 1891 arm_LDR_CS 1892 arm_LDR_CC 1893 arm_LDR_MI 1894 arm_LDR_PL 1895 arm_LDR_VS 1896 arm_LDR_VC 1897 arm_LDR_HI 1898 arm_LDR_LS 1899 arm_LDR_GE 1900 arm_LDR_LT 1901 arm_LDR_GT 1902 arm_LDR_LE 1903 arm_LDR 1904 arm_LDR_ZZ 1905 arm_LDRB_EQ 1906 arm_LDRB_NE 1907 arm_LDRB_CS 1908 arm_LDRB_CC 1909 arm_LDRB_MI 1910 arm_LDRB_PL 1911 arm_LDRB_VS 1912 arm_LDRB_VC 1913 arm_LDRB_HI 1914 arm_LDRB_LS 1915 arm_LDRB_GE 1916 arm_LDRB_LT 1917 arm_LDRB_GT 1918 arm_LDRB_LE 1919 arm_LDRB 1920 arm_LDRB_ZZ 1921 arm_LDRBT_EQ 1922 arm_LDRBT_NE 1923 arm_LDRBT_CS 1924 arm_LDRBT_CC 1925 arm_LDRBT_MI 1926 arm_LDRBT_PL 1927 arm_LDRBT_VS 1928 arm_LDRBT_VC 1929 arm_LDRBT_HI 1930 arm_LDRBT_LS 1931 arm_LDRBT_GE 1932 arm_LDRBT_LT 1933 arm_LDRBT_GT 1934 arm_LDRBT_LE 1935 arm_LDRBT 1936 arm_LDRBT_ZZ 1937 arm_LDRD_EQ 1938 arm_LDRD_NE 1939 arm_LDRD_CS 1940 arm_LDRD_CC 1941 arm_LDRD_MI 1942 arm_LDRD_PL 1943 arm_LDRD_VS 1944 arm_LDRD_VC 1945 arm_LDRD_HI 1946 arm_LDRD_LS 1947 arm_LDRD_GE 1948 arm_LDRD_LT 1949 arm_LDRD_GT 1950 arm_LDRD_LE 1951 arm_LDRD 1952 arm_LDRD_ZZ 1953 arm_LDREX_EQ 1954 arm_LDREX_NE 1955 arm_LDREX_CS 1956 arm_LDREX_CC 1957 arm_LDREX_MI 1958 arm_LDREX_PL 1959 arm_LDREX_VS 1960 arm_LDREX_VC 1961 arm_LDREX_HI 1962 arm_LDREX_LS 1963 arm_LDREX_GE 1964 arm_LDREX_LT 1965 arm_LDREX_GT 1966 arm_LDREX_LE 1967 arm_LDREX 1968 arm_LDREX_ZZ 1969 arm_LDREXB_EQ 1970 arm_LDREXB_NE 1971 arm_LDREXB_CS 1972 arm_LDREXB_CC 1973 arm_LDREXB_MI 1974 arm_LDREXB_PL 1975 arm_LDREXB_VS 1976 arm_LDREXB_VC 1977 arm_LDREXB_HI 1978 arm_LDREXB_LS 1979 arm_LDREXB_GE 1980 arm_LDREXB_LT 1981 arm_LDREXB_GT 1982 arm_LDREXB_LE 1983 arm_LDREXB 1984 arm_LDREXB_ZZ 1985 arm_LDREXD_EQ 1986 arm_LDREXD_NE 1987 arm_LDREXD_CS 1988 arm_LDREXD_CC 1989 arm_LDREXD_MI 1990 arm_LDREXD_PL 1991 arm_LDREXD_VS 1992 arm_LDREXD_VC 1993 arm_LDREXD_HI 1994 arm_LDREXD_LS 1995 arm_LDREXD_GE 1996 arm_LDREXD_LT 1997 arm_LDREXD_GT 1998 arm_LDREXD_LE 1999 arm_LDREXD 2000 arm_LDREXD_ZZ 2001 arm_LDREXH_EQ 2002 arm_LDREXH_NE 2003 arm_LDREXH_CS 2004 arm_LDREXH_CC 2005 arm_LDREXH_MI 2006 arm_LDREXH_PL 2007 arm_LDREXH_VS 2008 arm_LDREXH_VC 2009 arm_LDREXH_HI 2010 arm_LDREXH_LS 2011 arm_LDREXH_GE 2012 arm_LDREXH_LT 2013 arm_LDREXH_GT 2014 arm_LDREXH_LE 2015 arm_LDREXH 2016 arm_LDREXH_ZZ 2017 arm_LDRH_EQ 2018 arm_LDRH_NE 2019 arm_LDRH_CS 2020 arm_LDRH_CC 2021 arm_LDRH_MI 2022 arm_LDRH_PL 2023 arm_LDRH_VS 2024 arm_LDRH_VC 2025 arm_LDRH_HI 2026 arm_LDRH_LS 2027 arm_LDRH_GE 2028 arm_LDRH_LT 2029 arm_LDRH_GT 2030 arm_LDRH_LE 2031 arm_LDRH 2032 arm_LDRH_ZZ 2033 arm_LDRHT_EQ 2034 arm_LDRHT_NE 2035 arm_LDRHT_CS 2036 arm_LDRHT_CC 2037 arm_LDRHT_MI 2038 arm_LDRHT_PL 2039 arm_LDRHT_VS 2040 arm_LDRHT_VC 2041 arm_LDRHT_HI 2042 arm_LDRHT_LS 2043 arm_LDRHT_GE 2044 arm_LDRHT_LT 2045 arm_LDRHT_GT 2046 arm_LDRHT_LE 2047 arm_LDRHT 2048 arm_LDRHT_ZZ 2049 arm_LDRSB_EQ 2050 arm_LDRSB_NE 2051 arm_LDRSB_CS 2052 arm_LDRSB_CC 2053 arm_LDRSB_MI 2054 arm_LDRSB_PL 2055 arm_LDRSB_VS 2056 arm_LDRSB_VC 2057 arm_LDRSB_HI 2058 arm_LDRSB_LS 2059 arm_LDRSB_GE 2060 arm_LDRSB_LT 2061 arm_LDRSB_GT 2062 arm_LDRSB_LE 2063 arm_LDRSB 2064 arm_LDRSB_ZZ 2065 arm_LDRSBT_EQ 2066 arm_LDRSBT_NE 2067 arm_LDRSBT_CS 2068 arm_LDRSBT_CC 2069 arm_LDRSBT_MI 2070 arm_LDRSBT_PL 2071 arm_LDRSBT_VS 2072 arm_LDRSBT_VC 2073 arm_LDRSBT_HI 2074 arm_LDRSBT_LS 2075 arm_LDRSBT_GE 2076 arm_LDRSBT_LT 2077 arm_LDRSBT_GT 2078 arm_LDRSBT_LE 2079 arm_LDRSBT 2080 arm_LDRSBT_ZZ 2081 arm_LDRSH_EQ 2082 arm_LDRSH_NE 2083 arm_LDRSH_CS 2084 arm_LDRSH_CC 2085 arm_LDRSH_MI 2086 arm_LDRSH_PL 2087 arm_LDRSH_VS 2088 arm_LDRSH_VC 2089 arm_LDRSH_HI 2090 arm_LDRSH_LS 2091 arm_LDRSH_GE 2092 arm_LDRSH_LT 2093 arm_LDRSH_GT 2094 arm_LDRSH_LE 2095 arm_LDRSH 2096 arm_LDRSH_ZZ 2097 arm_LDRSHT_EQ 2098 arm_LDRSHT_NE 2099 arm_LDRSHT_CS 2100 arm_LDRSHT_CC 2101 arm_LDRSHT_MI 2102 arm_LDRSHT_PL 2103 arm_LDRSHT_VS 2104 arm_LDRSHT_VC 2105 arm_LDRSHT_HI 2106 arm_LDRSHT_LS 2107 arm_LDRSHT_GE 2108 arm_LDRSHT_LT 2109 arm_LDRSHT_GT 2110 arm_LDRSHT_LE 2111 arm_LDRSHT 2112 arm_LDRSHT_ZZ 2113 arm_LDRT_EQ 2114 arm_LDRT_NE 2115 arm_LDRT_CS 2116 arm_LDRT_CC 2117 arm_LDRT_MI 2118 arm_LDRT_PL 2119 arm_LDRT_VS 2120 arm_LDRT_VC 2121 arm_LDRT_HI 2122 arm_LDRT_LS 2123 arm_LDRT_GE 2124 arm_LDRT_LT 2125 arm_LDRT_GT 2126 arm_LDRT_LE 2127 arm_LDRT 2128 arm_LDRT_ZZ 2129 arm_LSL_EQ 2130 arm_LSL_NE 2131 arm_LSL_CS 2132 arm_LSL_CC 2133 arm_LSL_MI 2134 arm_LSL_PL 2135 arm_LSL_VS 2136 arm_LSL_VC 2137 arm_LSL_HI 2138 arm_LSL_LS 2139 arm_LSL_GE 2140 arm_LSL_LT 2141 arm_LSL_GT 2142 arm_LSL_LE 2143 arm_LSL 2144 arm_LSL_ZZ 2145 arm_LSL_S_EQ 2146 arm_LSL_S_NE 2147 arm_LSL_S_CS 2148 arm_LSL_S_CC 2149 arm_LSL_S_MI 2150 arm_LSL_S_PL 2151 arm_LSL_S_VS 2152 arm_LSL_S_VC 2153 arm_LSL_S_HI 2154 arm_LSL_S_LS 2155 arm_LSL_S_GE 2156 arm_LSL_S_LT 2157 arm_LSL_S_GT 2158 arm_LSL_S_LE 2159 arm_LSL_S 2160 arm_LSL_S_ZZ 2161 arm_LSR_EQ 2162 arm_LSR_NE 2163 arm_LSR_CS 2164 arm_LSR_CC 2165 arm_LSR_MI 2166 arm_LSR_PL 2167 arm_LSR_VS 2168 arm_LSR_VC 2169 arm_LSR_HI 2170 arm_LSR_LS 2171 arm_LSR_GE 2172 arm_LSR_LT 2173 arm_LSR_GT 2174 arm_LSR_LE 2175 arm_LSR 2176 arm_LSR_ZZ 2177 arm_LSR_S_EQ 2178 arm_LSR_S_NE 2179 arm_LSR_S_CS 2180 arm_LSR_S_CC 2181 arm_LSR_S_MI 2182 arm_LSR_S_PL 2183 arm_LSR_S_VS 2184 arm_LSR_S_VC 2185 arm_LSR_S_HI 2186 arm_LSR_S_LS 2187 arm_LSR_S_GE 2188 arm_LSR_S_LT 2189 arm_LSR_S_GT 2190 arm_LSR_S_LE 2191 arm_LSR_S 2192 arm_LSR_S_ZZ 2193 arm_MLA_EQ 2194 arm_MLA_NE 2195 arm_MLA_CS 2196 arm_MLA_CC 2197 arm_MLA_MI 2198 arm_MLA_PL 2199 arm_MLA_VS 2200 arm_MLA_VC 2201 arm_MLA_HI 2202 arm_MLA_LS 2203 arm_MLA_GE 2204 arm_MLA_LT 2205 arm_MLA_GT 2206 arm_MLA_LE 2207 arm_MLA 2208 arm_MLA_ZZ 2209 arm_MLA_S_EQ 2210 arm_MLA_S_NE 2211 arm_MLA_S_CS 2212 arm_MLA_S_CC 2213 arm_MLA_S_MI 2214 arm_MLA_S_PL 2215 arm_MLA_S_VS 2216 arm_MLA_S_VC 2217 arm_MLA_S_HI 2218 arm_MLA_S_LS 2219 arm_MLA_S_GE 2220 arm_MLA_S_LT 2221 arm_MLA_S_GT 2222 arm_MLA_S_LE 2223 arm_MLA_S 2224 arm_MLA_S_ZZ 2225 arm_MLS_EQ 2226 arm_MLS_NE 2227 arm_MLS_CS 2228 arm_MLS_CC 2229 arm_MLS_MI 2230 arm_MLS_PL 2231 arm_MLS_VS 2232 arm_MLS_VC 2233 arm_MLS_HI 2234 arm_MLS_LS 2235 arm_MLS_GE 2236 arm_MLS_LT 2237 arm_MLS_GT 2238 arm_MLS_LE 2239 arm_MLS 2240 arm_MLS_ZZ 2241 arm_MOV_EQ 2242 arm_MOV_NE 2243 arm_MOV_CS 2244 arm_MOV_CC 2245 arm_MOV_MI 2246 arm_MOV_PL 2247 arm_MOV_VS 2248 arm_MOV_VC 2249 arm_MOV_HI 2250 arm_MOV_LS 2251 arm_MOV_GE 2252 arm_MOV_LT 2253 arm_MOV_GT 2254 arm_MOV_LE 2255 arm_MOV 2256 arm_MOV_ZZ 2257 arm_MOV_S_EQ 2258 arm_MOV_S_NE 2259 arm_MOV_S_CS 2260 arm_MOV_S_CC 2261 arm_MOV_S_MI 2262 arm_MOV_S_PL 2263 arm_MOV_S_VS 2264 arm_MOV_S_VC 2265 arm_MOV_S_HI 2266 arm_MOV_S_LS 2267 arm_MOV_S_GE 2268 arm_MOV_S_LT 2269 arm_MOV_S_GT 2270 arm_MOV_S_LE 2271 arm_MOV_S 2272 arm_MOV_S_ZZ 2273 arm_MOVT_EQ 2274 arm_MOVT_NE 2275 arm_MOVT_CS 2276 arm_MOVT_CC 2277 arm_MOVT_MI 2278 arm_MOVT_PL 2279 arm_MOVT_VS 2280 arm_MOVT_VC 2281 arm_MOVT_HI 2282 arm_MOVT_LS 2283 arm_MOVT_GE 2284 arm_MOVT_LT 2285 arm_MOVT_GT 2286 arm_MOVT_LE 2287 arm_MOVT 2288 arm_MOVT_ZZ 2289 arm_MOVW_EQ 2290 arm_MOVW_NE 2291 arm_MOVW_CS 2292 arm_MOVW_CC 2293 arm_MOVW_MI 2294 arm_MOVW_PL 2295 arm_MOVW_VS 2296 arm_MOVW_VC 2297 arm_MOVW_HI 2298 arm_MOVW_LS 2299 arm_MOVW_GE 2300 arm_MOVW_LT 2301 arm_MOVW_GT 2302 arm_MOVW_LE 2303 arm_MOVW 2304 arm_MOVW_ZZ 2305 arm_MRS_EQ 2306 arm_MRS_NE 2307 arm_MRS_CS 2308 arm_MRS_CC 2309 arm_MRS_MI 2310 arm_MRS_PL 2311 arm_MRS_VS 2312 arm_MRS_VC 2313 arm_MRS_HI 2314 arm_MRS_LS 2315 arm_MRS_GE 2316 arm_MRS_LT 2317 arm_MRS_GT 2318 arm_MRS_LE 2319 arm_MRS 2320 arm_MRS_ZZ 2321 arm_MUL_EQ 2322 arm_MUL_NE 2323 arm_MUL_CS 2324 arm_MUL_CC 2325 arm_MUL_MI 2326 arm_MUL_PL 2327 arm_MUL_VS 2328 arm_MUL_VC 2329 arm_MUL_HI 2330 arm_MUL_LS 2331 arm_MUL_GE 2332 arm_MUL_LT 2333 arm_MUL_GT 2334 arm_MUL_LE 2335 arm_MUL 2336 arm_MUL_ZZ 2337 arm_MUL_S_EQ 2338 arm_MUL_S_NE 2339 arm_MUL_S_CS 2340 arm_MUL_S_CC 2341 arm_MUL_S_MI 2342 arm_MUL_S_PL 2343 arm_MUL_S_VS 2344 arm_MUL_S_VC 2345 arm_MUL_S_HI 2346 arm_MUL_S_LS 2347 arm_MUL_S_GE 2348 arm_MUL_S_LT 2349 arm_MUL_S_GT 2350 arm_MUL_S_LE 2351 arm_MUL_S 2352 arm_MUL_S_ZZ 2353 arm_MVN_EQ 2354 arm_MVN_NE 2355 arm_MVN_CS 2356 arm_MVN_CC 2357 arm_MVN_MI 2358 arm_MVN_PL 2359 arm_MVN_VS 2360 arm_MVN_VC 2361 arm_MVN_HI 2362 arm_MVN_LS 2363 arm_MVN_GE 2364 arm_MVN_LT 2365 arm_MVN_GT 2366 arm_MVN_LE 2367 arm_MVN 2368 arm_MVN_ZZ 2369 arm_MVN_S_EQ 2370 arm_MVN_S_NE 2371 arm_MVN_S_CS 2372 arm_MVN_S_CC 2373 arm_MVN_S_MI 2374 arm_MVN_S_PL 2375 arm_MVN_S_VS 2376 arm_MVN_S_VC 2377 arm_MVN_S_HI 2378 arm_MVN_S_LS 2379 arm_MVN_S_GE 2380 arm_MVN_S_LT 2381 arm_MVN_S_GT 2382 arm_MVN_S_LE 2383 arm_MVN_S 2384 arm_MVN_S_ZZ 2385 arm_NOP_EQ 2386 arm_NOP_NE 2387 arm_NOP_CS 2388 arm_NOP_CC 2389 arm_NOP_MI 2390 arm_NOP_PL 2391 arm_NOP_VS 2392 arm_NOP_VC 2393 arm_NOP_HI 2394 arm_NOP_LS 2395 arm_NOP_GE 2396 arm_NOP_LT 2397 arm_NOP_GT 2398 arm_NOP_LE 2399 arm_NOP 2400 arm_NOP_ZZ 2401 arm_ORR_EQ 2402 arm_ORR_NE 2403 arm_ORR_CS 2404 arm_ORR_CC 2405 arm_ORR_MI 2406 arm_ORR_PL 2407 arm_ORR_VS 2408 arm_ORR_VC 2409 arm_ORR_HI 2410 arm_ORR_LS 2411 arm_ORR_GE 2412 arm_ORR_LT 2413 arm_ORR_GT 2414 arm_ORR_LE 2415 arm_ORR 2416 arm_ORR_ZZ 2417 arm_ORR_S_EQ 2418 arm_ORR_S_NE 2419 arm_ORR_S_CS 2420 arm_ORR_S_CC 2421 arm_ORR_S_MI 2422 arm_ORR_S_PL 2423 arm_ORR_S_VS 2424 arm_ORR_S_VC 2425 arm_ORR_S_HI 2426 arm_ORR_S_LS 2427 arm_ORR_S_GE 2428 arm_ORR_S_LT 2429 arm_ORR_S_GT 2430 arm_ORR_S_LE 2431 arm_ORR_S 2432 arm_ORR_S_ZZ 2433 arm_PKHBT_EQ 2434 arm_PKHBT_NE 2435 arm_PKHBT_CS 2436 arm_PKHBT_CC 2437 arm_PKHBT_MI 2438 arm_PKHBT_PL 2439 arm_PKHBT_VS 2440 arm_PKHBT_VC 2441 arm_PKHBT_HI 2442 arm_PKHBT_LS 2443 arm_PKHBT_GE 2444 arm_PKHBT_LT 2445 arm_PKHBT_GT 2446 arm_PKHBT_LE 2447 arm_PKHBT 2448 arm_PKHBT_ZZ 2449 arm_PKHTB_EQ 2450 arm_PKHTB_NE 2451 arm_PKHTB_CS 2452 arm_PKHTB_CC 2453 arm_PKHTB_MI 2454 arm_PKHTB_PL 2455 arm_PKHTB_VS 2456 arm_PKHTB_VC 2457 arm_PKHTB_HI 2458 arm_PKHTB_LS 2459 arm_PKHTB_GE 2460 arm_PKHTB_LT 2461 arm_PKHTB_GT 2462 arm_PKHTB_LE 2463 arm_PKHTB 2464 arm_PKHTB_ZZ 2465 arm_PLD_W 2466 arm_PLD 2467 arm_PLI 2468 _ 2469 _ 2470 _ 2471 _ 2472 _ 2473 _ 2474 _ 2475 _ 2476 _ 2477 _ 2478 _ 2479 _ 2480 _ 2481 arm_POP_EQ 2482 arm_POP_NE 2483 arm_POP_CS 2484 arm_POP_CC 2485 arm_POP_MI 2486 arm_POP_PL 2487 arm_POP_VS 2488 arm_POP_VC 2489 arm_POP_HI 2490 arm_POP_LS 2491 arm_POP_GE 2492 arm_POP_LT 2493 arm_POP_GT 2494 arm_POP_LE 2495 arm_POP 2496 arm_POP_ZZ 2497 arm_PUSH_EQ 2498 arm_PUSH_NE 2499 arm_PUSH_CS 2500 arm_PUSH_CC 2501 arm_PUSH_MI 2502 arm_PUSH_PL 2503 arm_PUSH_VS 2504 arm_PUSH_VC 2505 arm_PUSH_HI 2506 arm_PUSH_LS 2507 arm_PUSH_GE 2508 arm_PUSH_LT 2509 arm_PUSH_GT 2510 arm_PUSH_LE 2511 arm_PUSH 2512 arm_PUSH_ZZ 2513 arm_QADD_EQ 2514 arm_QADD_NE 2515 arm_QADD_CS 2516 arm_QADD_CC 2517 arm_QADD_MI 2518 arm_QADD_PL 2519 arm_QADD_VS 2520 arm_QADD_VC 2521 arm_QADD_HI 2522 arm_QADD_LS 2523 arm_QADD_GE 2524 arm_QADD_LT 2525 arm_QADD_GT 2526 arm_QADD_LE 2527 arm_QADD 2528 arm_QADD_ZZ 2529 arm_QADD16_EQ 2530 arm_QADD16_NE 2531 arm_QADD16_CS 2532 arm_QADD16_CC 2533 arm_QADD16_MI 2534 arm_QADD16_PL 2535 arm_QADD16_VS 2536 arm_QADD16_VC 2537 arm_QADD16_HI 2538 arm_QADD16_LS 2539 arm_QADD16_GE 2540 arm_QADD16_LT 2541 arm_QADD16_GT 2542 arm_QADD16_LE 2543 arm_QADD16 2544 arm_QADD16_ZZ 2545 arm_QADD8_EQ 2546 arm_QADD8_NE 2547 arm_QADD8_CS 2548 arm_QADD8_CC 2549 arm_QADD8_MI 2550 arm_QADD8_PL 2551 arm_QADD8_VS 2552 arm_QADD8_VC 2553 arm_QADD8_HI 2554 arm_QADD8_LS 2555 arm_QADD8_GE 2556 arm_QADD8_LT 2557 arm_QADD8_GT 2558 arm_QADD8_LE 2559 arm_QADD8 2560 arm_QADD8_ZZ 2561 arm_QASX_EQ 2562 arm_QASX_NE 2563 arm_QASX_CS 2564 arm_QASX_CC 2565 arm_QASX_MI 2566 arm_QASX_PL 2567 arm_QASX_VS 2568 arm_QASX_VC 2569 arm_QASX_HI 2570 arm_QASX_LS 2571 arm_QASX_GE 2572 arm_QASX_LT 2573 arm_QASX_GT 2574 arm_QASX_LE 2575 arm_QASX 2576 arm_QASX_ZZ 2577 arm_QDADD_EQ 2578 arm_QDADD_NE 2579 arm_QDADD_CS 2580 arm_QDADD_CC 2581 arm_QDADD_MI 2582 arm_QDADD_PL 2583 arm_QDADD_VS 2584 arm_QDADD_VC 2585 arm_QDADD_HI 2586 arm_QDADD_LS 2587 arm_QDADD_GE 2588 arm_QDADD_LT 2589 arm_QDADD_GT 2590 arm_QDADD_LE 2591 arm_QDADD 2592 arm_QDADD_ZZ 2593 arm_QDSUB_EQ 2594 arm_QDSUB_NE 2595 arm_QDSUB_CS 2596 arm_QDSUB_CC 2597 arm_QDSUB_MI 2598 arm_QDSUB_PL 2599 arm_QDSUB_VS 2600 arm_QDSUB_VC 2601 arm_QDSUB_HI 2602 arm_QDSUB_LS 2603 arm_QDSUB_GE 2604 arm_QDSUB_LT 2605 arm_QDSUB_GT 2606 arm_QDSUB_LE 2607 arm_QDSUB 2608 arm_QDSUB_ZZ 2609 arm_QSAX_EQ 2610 arm_QSAX_NE 2611 arm_QSAX_CS 2612 arm_QSAX_CC 2613 arm_QSAX_MI 2614 arm_QSAX_PL 2615 arm_QSAX_VS 2616 arm_QSAX_VC 2617 arm_QSAX_HI 2618 arm_QSAX_LS 2619 arm_QSAX_GE 2620 arm_QSAX_LT 2621 arm_QSAX_GT 2622 arm_QSAX_LE 2623 arm_QSAX 2624 arm_QSAX_ZZ 2625 arm_QSUB_EQ 2626 arm_QSUB_NE 2627 arm_QSUB_CS 2628 arm_QSUB_CC 2629 arm_QSUB_MI 2630 arm_QSUB_PL 2631 arm_QSUB_VS 2632 arm_QSUB_VC 2633 arm_QSUB_HI 2634 arm_QSUB_LS 2635 arm_QSUB_GE 2636 arm_QSUB_LT 2637 arm_QSUB_GT 2638 arm_QSUB_LE 2639 arm_QSUB 2640 arm_QSUB_ZZ 2641 arm_QSUB16_EQ 2642 arm_QSUB16_NE 2643 arm_QSUB16_CS 2644 arm_QSUB16_CC 2645 arm_QSUB16_MI 2646 arm_QSUB16_PL 2647 arm_QSUB16_VS 2648 arm_QSUB16_VC 2649 arm_QSUB16_HI 2650 arm_QSUB16_LS 2651 arm_QSUB16_GE 2652 arm_QSUB16_LT 2653 arm_QSUB16_GT 2654 arm_QSUB16_LE 2655 arm_QSUB16 2656 arm_QSUB16_ZZ 2657 arm_QSUB8_EQ 2658 arm_QSUB8_NE 2659 arm_QSUB8_CS 2660 arm_QSUB8_CC 2661 arm_QSUB8_MI 2662 arm_QSUB8_PL 2663 arm_QSUB8_VS 2664 arm_QSUB8_VC 2665 arm_QSUB8_HI 2666 arm_QSUB8_LS 2667 arm_QSUB8_GE 2668 arm_QSUB8_LT 2669 arm_QSUB8_GT 2670 arm_QSUB8_LE 2671 arm_QSUB8 2672 arm_QSUB8_ZZ 2673 arm_RBIT_EQ 2674 arm_RBIT_NE 2675 arm_RBIT_CS 2676 arm_RBIT_CC 2677 arm_RBIT_MI 2678 arm_RBIT_PL 2679 arm_RBIT_VS 2680 arm_RBIT_VC 2681 arm_RBIT_HI 2682 arm_RBIT_LS 2683 arm_RBIT_GE 2684 arm_RBIT_LT 2685 arm_RBIT_GT 2686 arm_RBIT_LE 2687 arm_RBIT 2688 arm_RBIT_ZZ 2689 arm_REV_EQ 2690 arm_REV_NE 2691 arm_REV_CS 2692 arm_REV_CC 2693 arm_REV_MI 2694 arm_REV_PL 2695 arm_REV_VS 2696 arm_REV_VC 2697 arm_REV_HI 2698 arm_REV_LS 2699 arm_REV_GE 2700 arm_REV_LT 2701 arm_REV_GT 2702 arm_REV_LE 2703 arm_REV 2704 arm_REV_ZZ 2705 arm_REV16_EQ 2706 arm_REV16_NE 2707 arm_REV16_CS 2708 arm_REV16_CC 2709 arm_REV16_MI 2710 arm_REV16_PL 2711 arm_REV16_VS 2712 arm_REV16_VC 2713 arm_REV16_HI 2714 arm_REV16_LS 2715 arm_REV16_GE 2716 arm_REV16_LT 2717 arm_REV16_GT 2718 arm_REV16_LE 2719 arm_REV16 2720 arm_REV16_ZZ 2721 arm_REVSH_EQ 2722 arm_REVSH_NE 2723 arm_REVSH_CS 2724 arm_REVSH_CC 2725 arm_REVSH_MI 2726 arm_REVSH_PL 2727 arm_REVSH_VS 2728 arm_REVSH_VC 2729 arm_REVSH_HI 2730 arm_REVSH_LS 2731 arm_REVSH_GE 2732 arm_REVSH_LT 2733 arm_REVSH_GT 2734 arm_REVSH_LE 2735 arm_REVSH 2736 arm_REVSH_ZZ 2737 arm_ROR_EQ 2738 arm_ROR_NE 2739 arm_ROR_CS 2740 arm_ROR_CC 2741 arm_ROR_MI 2742 arm_ROR_PL 2743 arm_ROR_VS 2744 arm_ROR_VC 2745 arm_ROR_HI 2746 arm_ROR_LS 2747 arm_ROR_GE 2748 arm_ROR_LT 2749 arm_ROR_GT 2750 arm_ROR_LE 2751 arm_ROR 2752 arm_ROR_ZZ 2753 arm_ROR_S_EQ 2754 arm_ROR_S_NE 2755 arm_ROR_S_CS 2756 arm_ROR_S_CC 2757 arm_ROR_S_MI 2758 arm_ROR_S_PL 2759 arm_ROR_S_VS 2760 arm_ROR_S_VC 2761 arm_ROR_S_HI 2762 arm_ROR_S_LS 2763 arm_ROR_S_GE 2764 arm_ROR_S_LT 2765 arm_ROR_S_GT 2766 arm_ROR_S_LE 2767 arm_ROR_S 2768 arm_ROR_S_ZZ 2769 arm_RRX_EQ 2770 arm_RRX_NE 2771 arm_RRX_CS 2772 arm_RRX_CC 2773 arm_RRX_MI 2774 arm_RRX_PL 2775 arm_RRX_VS 2776 arm_RRX_VC 2777 arm_RRX_HI 2778 arm_RRX_LS 2779 arm_RRX_GE 2780 arm_RRX_LT 2781 arm_RRX_GT 2782 arm_RRX_LE 2783 arm_RRX 2784 arm_RRX_ZZ 2785 arm_RRX_S_EQ 2786 arm_RRX_S_NE 2787 arm_RRX_S_CS 2788 arm_RRX_S_CC 2789 arm_RRX_S_MI 2790 arm_RRX_S_PL 2791 arm_RRX_S_VS 2792 arm_RRX_S_VC 2793 arm_RRX_S_HI 2794 arm_RRX_S_LS 2795 arm_RRX_S_GE 2796 arm_RRX_S_LT 2797 arm_RRX_S_GT 2798 arm_RRX_S_LE 2799 arm_RRX_S 2800 arm_RRX_S_ZZ 2801 arm_RSB_EQ 2802 arm_RSB_NE 2803 arm_RSB_CS 2804 arm_RSB_CC 2805 arm_RSB_MI 2806 arm_RSB_PL 2807 arm_RSB_VS 2808 arm_RSB_VC 2809 arm_RSB_HI 2810 arm_RSB_LS 2811 arm_RSB_GE 2812 arm_RSB_LT 2813 arm_RSB_GT 2814 arm_RSB_LE 2815 arm_RSB 2816 arm_RSB_ZZ 2817 arm_RSB_S_EQ 2818 arm_RSB_S_NE 2819 arm_RSB_S_CS 2820 arm_RSB_S_CC 2821 arm_RSB_S_MI 2822 arm_RSB_S_PL 2823 arm_RSB_S_VS 2824 arm_RSB_S_VC 2825 arm_RSB_S_HI 2826 arm_RSB_S_LS 2827 arm_RSB_S_GE 2828 arm_RSB_S_LT 2829 arm_RSB_S_GT 2830 arm_RSB_S_LE 2831 arm_RSB_S 2832 arm_RSB_S_ZZ 2833 arm_RSC_EQ 2834 arm_RSC_NE 2835 arm_RSC_CS 2836 arm_RSC_CC 2837 arm_RSC_MI 2838 arm_RSC_PL 2839 arm_RSC_VS 2840 arm_RSC_VC 2841 arm_RSC_HI 2842 arm_RSC_LS 2843 arm_RSC_GE 2844 arm_RSC_LT 2845 arm_RSC_GT 2846 arm_RSC_LE 2847 arm_RSC 2848 arm_RSC_ZZ 2849 arm_RSC_S_EQ 2850 arm_RSC_S_NE 2851 arm_RSC_S_CS 2852 arm_RSC_S_CC 2853 arm_RSC_S_MI 2854 arm_RSC_S_PL 2855 arm_RSC_S_VS 2856 arm_RSC_S_VC 2857 arm_RSC_S_HI 2858 arm_RSC_S_LS 2859 arm_RSC_S_GE 2860 arm_RSC_S_LT 2861 arm_RSC_S_GT 2862 arm_RSC_S_LE 2863 arm_RSC_S 2864 arm_RSC_S_ZZ 2865 arm_SADD16_EQ 2866 arm_SADD16_NE 2867 arm_SADD16_CS 2868 arm_SADD16_CC 2869 arm_SADD16_MI 2870 arm_SADD16_PL 2871 arm_SADD16_VS 2872 arm_SADD16_VC 2873 arm_SADD16_HI 2874 arm_SADD16_LS 2875 arm_SADD16_GE 2876 arm_SADD16_LT 2877 arm_SADD16_GT 2878 arm_SADD16_LE 2879 arm_SADD16 2880 arm_SADD16_ZZ 2881 arm_SADD8_EQ 2882 arm_SADD8_NE 2883 arm_SADD8_CS 2884 arm_SADD8_CC 2885 arm_SADD8_MI 2886 arm_SADD8_PL 2887 arm_SADD8_VS 2888 arm_SADD8_VC 2889 arm_SADD8_HI 2890 arm_SADD8_LS 2891 arm_SADD8_GE 2892 arm_SADD8_LT 2893 arm_SADD8_GT 2894 arm_SADD8_LE 2895 arm_SADD8 2896 arm_SADD8_ZZ 2897 arm_SASX_EQ 2898 arm_SASX_NE 2899 arm_SASX_CS 2900 arm_SASX_CC 2901 arm_SASX_MI 2902 arm_SASX_PL 2903 arm_SASX_VS 2904 arm_SASX_VC 2905 arm_SASX_HI 2906 arm_SASX_LS 2907 arm_SASX_GE 2908 arm_SASX_LT 2909 arm_SASX_GT 2910 arm_SASX_LE 2911 arm_SASX 2912 arm_SASX_ZZ 2913 arm_SBC_EQ 2914 arm_SBC_NE 2915 arm_SBC_CS 2916 arm_SBC_CC 2917 arm_SBC_MI 2918 arm_SBC_PL 2919 arm_SBC_VS 2920 arm_SBC_VC 2921 arm_SBC_HI 2922 arm_SBC_LS 2923 arm_SBC_GE 2924 arm_SBC_LT 2925 arm_SBC_GT 2926 arm_SBC_LE 2927 arm_SBC 2928 arm_SBC_ZZ 2929 arm_SBC_S_EQ 2930 arm_SBC_S_NE 2931 arm_SBC_S_CS 2932 arm_SBC_S_CC 2933 arm_SBC_S_MI 2934 arm_SBC_S_PL 2935 arm_SBC_S_VS 2936 arm_SBC_S_VC 2937 arm_SBC_S_HI 2938 arm_SBC_S_LS 2939 arm_SBC_S_GE 2940 arm_SBC_S_LT 2941 arm_SBC_S_GT 2942 arm_SBC_S_LE 2943 arm_SBC_S 2944 arm_SBC_S_ZZ 2945 arm_SBFX_EQ 2946 arm_SBFX_NE 2947 arm_SBFX_CS 2948 arm_SBFX_CC 2949 arm_SBFX_MI 2950 arm_SBFX_PL 2951 arm_SBFX_VS 2952 arm_SBFX_VC 2953 arm_SBFX_HI 2954 arm_SBFX_LS 2955 arm_SBFX_GE 2956 arm_SBFX_LT 2957 arm_SBFX_GT 2958 arm_SBFX_LE 2959 arm_SBFX 2960 arm_SBFX_ZZ 2961 arm_SEL_EQ 2962 arm_SEL_NE 2963 arm_SEL_CS 2964 arm_SEL_CC 2965 arm_SEL_MI 2966 arm_SEL_PL 2967 arm_SEL_VS 2968 arm_SEL_VC 2969 arm_SEL_HI 2970 arm_SEL_LS 2971 arm_SEL_GE 2972 arm_SEL_LT 2973 arm_SEL_GT 2974 arm_SEL_LE 2975 arm_SEL 2976 arm_SEL_ZZ 2977 arm_SETEND 2978 _ 2979 _ 2980 _ 2981 _ 2982 _ 2983 _ 2984 _ 2985 _ 2986 _ 2987 _ 2988 _ 2989 _ 2990 _ 2991 _ 2992 _ 2993 arm_SEV_EQ 2994 arm_SEV_NE 2995 arm_SEV_CS 2996 arm_SEV_CC 2997 arm_SEV_MI 2998 arm_SEV_PL 2999 arm_SEV_VS 3000 arm_SEV_VC 3001 arm_SEV_HI 3002 arm_SEV_LS 3003 arm_SEV_GE 3004 arm_SEV_LT 3005 arm_SEV_GT 3006 arm_SEV_LE 3007 arm_SEV 3008 arm_SEV_ZZ 3009 arm_SHADD16_EQ 3010 arm_SHADD16_NE 3011 arm_SHADD16_CS 3012 arm_SHADD16_CC 3013 arm_SHADD16_MI 3014 arm_SHADD16_PL 3015 arm_SHADD16_VS 3016 arm_SHADD16_VC 3017 arm_SHADD16_HI 3018 arm_SHADD16_LS 3019 arm_SHADD16_GE 3020 arm_SHADD16_LT 3021 arm_SHADD16_GT 3022 arm_SHADD16_LE 3023 arm_SHADD16 3024 arm_SHADD16_ZZ 3025 arm_SHADD8_EQ 3026 arm_SHADD8_NE 3027 arm_SHADD8_CS 3028 arm_SHADD8_CC 3029 arm_SHADD8_MI 3030 arm_SHADD8_PL 3031 arm_SHADD8_VS 3032 arm_SHADD8_VC 3033 arm_SHADD8_HI 3034 arm_SHADD8_LS 3035 arm_SHADD8_GE 3036 arm_SHADD8_LT 3037 arm_SHADD8_GT 3038 arm_SHADD8_LE 3039 arm_SHADD8 3040 arm_SHADD8_ZZ 3041 arm_SHASX_EQ 3042 arm_SHASX_NE 3043 arm_SHASX_CS 3044 arm_SHASX_CC 3045 arm_SHASX_MI 3046 arm_SHASX_PL 3047 arm_SHASX_VS 3048 arm_SHASX_VC 3049 arm_SHASX_HI 3050 arm_SHASX_LS 3051 arm_SHASX_GE 3052 arm_SHASX_LT 3053 arm_SHASX_GT 3054 arm_SHASX_LE 3055 arm_SHASX 3056 arm_SHASX_ZZ 3057 arm_SHSAX_EQ 3058 arm_SHSAX_NE 3059 arm_SHSAX_CS 3060 arm_SHSAX_CC 3061 arm_SHSAX_MI 3062 arm_SHSAX_PL 3063 arm_SHSAX_VS 3064 arm_SHSAX_VC 3065 arm_SHSAX_HI 3066 arm_SHSAX_LS 3067 arm_SHSAX_GE 3068 arm_SHSAX_LT 3069 arm_SHSAX_GT 3070 arm_SHSAX_LE 3071 arm_SHSAX 3072 arm_SHSAX_ZZ 3073 arm_SHSUB16_EQ 3074 arm_SHSUB16_NE 3075 arm_SHSUB16_CS 3076 arm_SHSUB16_CC 3077 arm_SHSUB16_MI 3078 arm_SHSUB16_PL 3079 arm_SHSUB16_VS 3080 arm_SHSUB16_VC 3081 arm_SHSUB16_HI 3082 arm_SHSUB16_LS 3083 arm_SHSUB16_GE 3084 arm_SHSUB16_LT 3085 arm_SHSUB16_GT 3086 arm_SHSUB16_LE 3087 arm_SHSUB16 3088 arm_SHSUB16_ZZ 3089 arm_SHSUB8_EQ 3090 arm_SHSUB8_NE 3091 arm_SHSUB8_CS 3092 arm_SHSUB8_CC 3093 arm_SHSUB8_MI 3094 arm_SHSUB8_PL 3095 arm_SHSUB8_VS 3096 arm_SHSUB8_VC 3097 arm_SHSUB8_HI 3098 arm_SHSUB8_LS 3099 arm_SHSUB8_GE 3100 arm_SHSUB8_LT 3101 arm_SHSUB8_GT 3102 arm_SHSUB8_LE 3103 arm_SHSUB8 3104 arm_SHSUB8_ZZ 3105 arm_SMLABB_EQ 3106 arm_SMLABB_NE 3107 arm_SMLABB_CS 3108 arm_SMLABB_CC 3109 arm_SMLABB_MI 3110 arm_SMLABB_PL 3111 arm_SMLABB_VS 3112 arm_SMLABB_VC 3113 arm_SMLABB_HI 3114 arm_SMLABB_LS 3115 arm_SMLABB_GE 3116 arm_SMLABB_LT 3117 arm_SMLABB_GT 3118 arm_SMLABB_LE 3119 arm_SMLABB 3120 arm_SMLABB_ZZ 3121 arm_SMLABT_EQ 3122 arm_SMLABT_NE 3123 arm_SMLABT_CS 3124 arm_SMLABT_CC 3125 arm_SMLABT_MI 3126 arm_SMLABT_PL 3127 arm_SMLABT_VS 3128 arm_SMLABT_VC 3129 arm_SMLABT_HI 3130 arm_SMLABT_LS 3131 arm_SMLABT_GE 3132 arm_SMLABT_LT 3133 arm_SMLABT_GT 3134 arm_SMLABT_LE 3135 arm_SMLABT 3136 arm_SMLABT_ZZ 3137 arm_SMLATB_EQ 3138 arm_SMLATB_NE 3139 arm_SMLATB_CS 3140 arm_SMLATB_CC 3141 arm_SMLATB_MI 3142 arm_SMLATB_PL 3143 arm_SMLATB_VS 3144 arm_SMLATB_VC 3145 arm_SMLATB_HI 3146 arm_SMLATB_LS 3147 arm_SMLATB_GE 3148 arm_SMLATB_LT 3149 arm_SMLATB_GT 3150 arm_SMLATB_LE 3151 arm_SMLATB 3152 arm_SMLATB_ZZ 3153 arm_SMLATT_EQ 3154 arm_SMLATT_NE 3155 arm_SMLATT_CS 3156 arm_SMLATT_CC 3157 arm_SMLATT_MI 3158 arm_SMLATT_PL 3159 arm_SMLATT_VS 3160 arm_SMLATT_VC 3161 arm_SMLATT_HI 3162 arm_SMLATT_LS 3163 arm_SMLATT_GE 3164 arm_SMLATT_LT 3165 arm_SMLATT_GT 3166 arm_SMLATT_LE 3167 arm_SMLATT 3168 arm_SMLATT_ZZ 3169 arm_SMLAD_EQ 3170 arm_SMLAD_NE 3171 arm_SMLAD_CS 3172 arm_SMLAD_CC 3173 arm_SMLAD_MI 3174 arm_SMLAD_PL 3175 arm_SMLAD_VS 3176 arm_SMLAD_VC 3177 arm_SMLAD_HI 3178 arm_SMLAD_LS 3179 arm_SMLAD_GE 3180 arm_SMLAD_LT 3181 arm_SMLAD_GT 3182 arm_SMLAD_LE 3183 arm_SMLAD 3184 arm_SMLAD_ZZ 3185 arm_SMLAD_X_EQ 3186 arm_SMLAD_X_NE 3187 arm_SMLAD_X_CS 3188 arm_SMLAD_X_CC 3189 arm_SMLAD_X_MI 3190 arm_SMLAD_X_PL 3191 arm_SMLAD_X_VS 3192 arm_SMLAD_X_VC 3193 arm_SMLAD_X_HI 3194 arm_SMLAD_X_LS 3195 arm_SMLAD_X_GE 3196 arm_SMLAD_X_LT 3197 arm_SMLAD_X_GT 3198 arm_SMLAD_X_LE 3199 arm_SMLAD_X 3200 arm_SMLAD_X_ZZ 3201 arm_SMLAL_EQ 3202 arm_SMLAL_NE 3203 arm_SMLAL_CS 3204 arm_SMLAL_CC 3205 arm_SMLAL_MI 3206 arm_SMLAL_PL 3207 arm_SMLAL_VS 3208 arm_SMLAL_VC 3209 arm_SMLAL_HI 3210 arm_SMLAL_LS 3211 arm_SMLAL_GE 3212 arm_SMLAL_LT 3213 arm_SMLAL_GT 3214 arm_SMLAL_LE 3215 arm_SMLAL 3216 arm_SMLAL_ZZ 3217 arm_SMLAL_S_EQ 3218 arm_SMLAL_S_NE 3219 arm_SMLAL_S_CS 3220 arm_SMLAL_S_CC 3221 arm_SMLAL_S_MI 3222 arm_SMLAL_S_PL 3223 arm_SMLAL_S_VS 3224 arm_SMLAL_S_VC 3225 arm_SMLAL_S_HI 3226 arm_SMLAL_S_LS 3227 arm_SMLAL_S_GE 3228 arm_SMLAL_S_LT 3229 arm_SMLAL_S_GT 3230 arm_SMLAL_S_LE 3231 arm_SMLAL_S 3232 arm_SMLAL_S_ZZ 3233 arm_SMLALBB_EQ 3234 arm_SMLALBB_NE 3235 arm_SMLALBB_CS 3236 arm_SMLALBB_CC 3237 arm_SMLALBB_MI 3238 arm_SMLALBB_PL 3239 arm_SMLALBB_VS 3240 arm_SMLALBB_VC 3241 arm_SMLALBB_HI 3242 arm_SMLALBB_LS 3243 arm_SMLALBB_GE 3244 arm_SMLALBB_LT 3245 arm_SMLALBB_GT 3246 arm_SMLALBB_LE 3247 arm_SMLALBB 3248 arm_SMLALBB_ZZ 3249 arm_SMLALBT_EQ 3250 arm_SMLALBT_NE 3251 arm_SMLALBT_CS 3252 arm_SMLALBT_CC 3253 arm_SMLALBT_MI 3254 arm_SMLALBT_PL 3255 arm_SMLALBT_VS 3256 arm_SMLALBT_VC 3257 arm_SMLALBT_HI 3258 arm_SMLALBT_LS 3259 arm_SMLALBT_GE 3260 arm_SMLALBT_LT 3261 arm_SMLALBT_GT 3262 arm_SMLALBT_LE 3263 arm_SMLALBT 3264 arm_SMLALBT_ZZ 3265 arm_SMLALTB_EQ 3266 arm_SMLALTB_NE 3267 arm_SMLALTB_CS 3268 arm_SMLALTB_CC 3269 arm_SMLALTB_MI 3270 arm_SMLALTB_PL 3271 arm_SMLALTB_VS 3272 arm_SMLALTB_VC 3273 arm_SMLALTB_HI 3274 arm_SMLALTB_LS 3275 arm_SMLALTB_GE 3276 arm_SMLALTB_LT 3277 arm_SMLALTB_GT 3278 arm_SMLALTB_LE 3279 arm_SMLALTB 3280 arm_SMLALTB_ZZ 3281 arm_SMLALTT_EQ 3282 arm_SMLALTT_NE 3283 arm_SMLALTT_CS 3284 arm_SMLALTT_CC 3285 arm_SMLALTT_MI 3286 arm_SMLALTT_PL 3287 arm_SMLALTT_VS 3288 arm_SMLALTT_VC 3289 arm_SMLALTT_HI 3290 arm_SMLALTT_LS 3291 arm_SMLALTT_GE 3292 arm_SMLALTT_LT 3293 arm_SMLALTT_GT 3294 arm_SMLALTT_LE 3295 arm_SMLALTT 3296 arm_SMLALTT_ZZ 3297 arm_SMLALD_EQ 3298 arm_SMLALD_NE 3299 arm_SMLALD_CS 3300 arm_SMLALD_CC 3301 arm_SMLALD_MI 3302 arm_SMLALD_PL 3303 arm_SMLALD_VS 3304 arm_SMLALD_VC 3305 arm_SMLALD_HI 3306 arm_SMLALD_LS 3307 arm_SMLALD_GE 3308 arm_SMLALD_LT 3309 arm_SMLALD_GT 3310 arm_SMLALD_LE 3311 arm_SMLALD 3312 arm_SMLALD_ZZ 3313 arm_SMLALD_X_EQ 3314 arm_SMLALD_X_NE 3315 arm_SMLALD_X_CS 3316 arm_SMLALD_X_CC 3317 arm_SMLALD_X_MI 3318 arm_SMLALD_X_PL 3319 arm_SMLALD_X_VS 3320 arm_SMLALD_X_VC 3321 arm_SMLALD_X_HI 3322 arm_SMLALD_X_LS 3323 arm_SMLALD_X_GE 3324 arm_SMLALD_X_LT 3325 arm_SMLALD_X_GT 3326 arm_SMLALD_X_LE 3327 arm_SMLALD_X 3328 arm_SMLALD_X_ZZ 3329 arm_SMLAWB_EQ 3330 arm_SMLAWB_NE 3331 arm_SMLAWB_CS 3332 arm_SMLAWB_CC 3333 arm_SMLAWB_MI 3334 arm_SMLAWB_PL 3335 arm_SMLAWB_VS 3336 arm_SMLAWB_VC 3337 arm_SMLAWB_HI 3338 arm_SMLAWB_LS 3339 arm_SMLAWB_GE 3340 arm_SMLAWB_LT 3341 arm_SMLAWB_GT 3342 arm_SMLAWB_LE 3343 arm_SMLAWB 3344 arm_SMLAWB_ZZ 3345 arm_SMLAWT_EQ 3346 arm_SMLAWT_NE 3347 arm_SMLAWT_CS 3348 arm_SMLAWT_CC 3349 arm_SMLAWT_MI 3350 arm_SMLAWT_PL 3351 arm_SMLAWT_VS 3352 arm_SMLAWT_VC 3353 arm_SMLAWT_HI 3354 arm_SMLAWT_LS 3355 arm_SMLAWT_GE 3356 arm_SMLAWT_LT 3357 arm_SMLAWT_GT 3358 arm_SMLAWT_LE 3359 arm_SMLAWT 3360 arm_SMLAWT_ZZ 3361 arm_SMLSD_EQ 3362 arm_SMLSD_NE 3363 arm_SMLSD_CS 3364 arm_SMLSD_CC 3365 arm_SMLSD_MI 3366 arm_SMLSD_PL 3367 arm_SMLSD_VS 3368 arm_SMLSD_VC 3369 arm_SMLSD_HI 3370 arm_SMLSD_LS 3371 arm_SMLSD_GE 3372 arm_SMLSD_LT 3373 arm_SMLSD_GT 3374 arm_SMLSD_LE 3375 arm_SMLSD 3376 arm_SMLSD_ZZ 3377 arm_SMLSD_X_EQ 3378 arm_SMLSD_X_NE 3379 arm_SMLSD_X_CS 3380 arm_SMLSD_X_CC 3381 arm_SMLSD_X_MI 3382 arm_SMLSD_X_PL 3383 arm_SMLSD_X_VS 3384 arm_SMLSD_X_VC 3385 arm_SMLSD_X_HI 3386 arm_SMLSD_X_LS 3387 arm_SMLSD_X_GE 3388 arm_SMLSD_X_LT 3389 arm_SMLSD_X_GT 3390 arm_SMLSD_X_LE 3391 arm_SMLSD_X 3392 arm_SMLSD_X_ZZ 3393 arm_SMLSLD_EQ 3394 arm_SMLSLD_NE 3395 arm_SMLSLD_CS 3396 arm_SMLSLD_CC 3397 arm_SMLSLD_MI 3398 arm_SMLSLD_PL 3399 arm_SMLSLD_VS 3400 arm_SMLSLD_VC 3401 arm_SMLSLD_HI 3402 arm_SMLSLD_LS 3403 arm_SMLSLD_GE 3404 arm_SMLSLD_LT 3405 arm_SMLSLD_GT 3406 arm_SMLSLD_LE 3407 arm_SMLSLD 3408 arm_SMLSLD_ZZ 3409 arm_SMLSLD_X_EQ 3410 arm_SMLSLD_X_NE 3411 arm_SMLSLD_X_CS 3412 arm_SMLSLD_X_CC 3413 arm_SMLSLD_X_MI 3414 arm_SMLSLD_X_PL 3415 arm_SMLSLD_X_VS 3416 arm_SMLSLD_X_VC 3417 arm_SMLSLD_X_HI 3418 arm_SMLSLD_X_LS 3419 arm_SMLSLD_X_GE 3420 arm_SMLSLD_X_LT 3421 arm_SMLSLD_X_GT 3422 arm_SMLSLD_X_LE 3423 arm_SMLSLD_X 3424 arm_SMLSLD_X_ZZ 3425 arm_SMMLA_EQ 3426 arm_SMMLA_NE 3427 arm_SMMLA_CS 3428 arm_SMMLA_CC 3429 arm_SMMLA_MI 3430 arm_SMMLA_PL 3431 arm_SMMLA_VS 3432 arm_SMMLA_VC 3433 arm_SMMLA_HI 3434 arm_SMMLA_LS 3435 arm_SMMLA_GE 3436 arm_SMMLA_LT 3437 arm_SMMLA_GT 3438 arm_SMMLA_LE 3439 arm_SMMLA 3440 arm_SMMLA_ZZ 3441 arm_SMMLA_R_EQ 3442 arm_SMMLA_R_NE 3443 arm_SMMLA_R_CS 3444 arm_SMMLA_R_CC 3445 arm_SMMLA_R_MI 3446 arm_SMMLA_R_PL 3447 arm_SMMLA_R_VS 3448 arm_SMMLA_R_VC 3449 arm_SMMLA_R_HI 3450 arm_SMMLA_R_LS 3451 arm_SMMLA_R_GE 3452 arm_SMMLA_R_LT 3453 arm_SMMLA_R_GT 3454 arm_SMMLA_R_LE 3455 arm_SMMLA_R 3456 arm_SMMLA_R_ZZ 3457 arm_SMMLS_EQ 3458 arm_SMMLS_NE 3459 arm_SMMLS_CS 3460 arm_SMMLS_CC 3461 arm_SMMLS_MI 3462 arm_SMMLS_PL 3463 arm_SMMLS_VS 3464 arm_SMMLS_VC 3465 arm_SMMLS_HI 3466 arm_SMMLS_LS 3467 arm_SMMLS_GE 3468 arm_SMMLS_LT 3469 arm_SMMLS_GT 3470 arm_SMMLS_LE 3471 arm_SMMLS 3472 arm_SMMLS_ZZ 3473 arm_SMMLS_R_EQ 3474 arm_SMMLS_R_NE 3475 arm_SMMLS_R_CS 3476 arm_SMMLS_R_CC 3477 arm_SMMLS_R_MI 3478 arm_SMMLS_R_PL 3479 arm_SMMLS_R_VS 3480 arm_SMMLS_R_VC 3481 arm_SMMLS_R_HI 3482 arm_SMMLS_R_LS 3483 arm_SMMLS_R_GE 3484 arm_SMMLS_R_LT 3485 arm_SMMLS_R_GT 3486 arm_SMMLS_R_LE 3487 arm_SMMLS_R 3488 arm_SMMLS_R_ZZ 3489 arm_SMMUL_EQ 3490 arm_SMMUL_NE 3491 arm_SMMUL_CS 3492 arm_SMMUL_CC 3493 arm_SMMUL_MI 3494 arm_SMMUL_PL 3495 arm_SMMUL_VS 3496 arm_SMMUL_VC 3497 arm_SMMUL_HI 3498 arm_SMMUL_LS 3499 arm_SMMUL_GE 3500 arm_SMMUL_LT 3501 arm_SMMUL_GT 3502 arm_SMMUL_LE 3503 arm_SMMUL 3504 arm_SMMUL_ZZ 3505 arm_SMMUL_R_EQ 3506 arm_SMMUL_R_NE 3507 arm_SMMUL_R_CS 3508 arm_SMMUL_R_CC 3509 arm_SMMUL_R_MI 3510 arm_SMMUL_R_PL 3511 arm_SMMUL_R_VS 3512 arm_SMMUL_R_VC 3513 arm_SMMUL_R_HI 3514 arm_SMMUL_R_LS 3515 arm_SMMUL_R_GE 3516 arm_SMMUL_R_LT 3517 arm_SMMUL_R_GT 3518 arm_SMMUL_R_LE 3519 arm_SMMUL_R 3520 arm_SMMUL_R_ZZ 3521 arm_SMUAD_EQ 3522 arm_SMUAD_NE 3523 arm_SMUAD_CS 3524 arm_SMUAD_CC 3525 arm_SMUAD_MI 3526 arm_SMUAD_PL 3527 arm_SMUAD_VS 3528 arm_SMUAD_VC 3529 arm_SMUAD_HI 3530 arm_SMUAD_LS 3531 arm_SMUAD_GE 3532 arm_SMUAD_LT 3533 arm_SMUAD_GT 3534 arm_SMUAD_LE 3535 arm_SMUAD 3536 arm_SMUAD_ZZ 3537 arm_SMUAD_X_EQ 3538 arm_SMUAD_X_NE 3539 arm_SMUAD_X_CS 3540 arm_SMUAD_X_CC 3541 arm_SMUAD_X_MI 3542 arm_SMUAD_X_PL 3543 arm_SMUAD_X_VS 3544 arm_SMUAD_X_VC 3545 arm_SMUAD_X_HI 3546 arm_SMUAD_X_LS 3547 arm_SMUAD_X_GE 3548 arm_SMUAD_X_LT 3549 arm_SMUAD_X_GT 3550 arm_SMUAD_X_LE 3551 arm_SMUAD_X 3552 arm_SMUAD_X_ZZ 3553 arm_SMULBB_EQ 3554 arm_SMULBB_NE 3555 arm_SMULBB_CS 3556 arm_SMULBB_CC 3557 arm_SMULBB_MI 3558 arm_SMULBB_PL 3559 arm_SMULBB_VS 3560 arm_SMULBB_VC 3561 arm_SMULBB_HI 3562 arm_SMULBB_LS 3563 arm_SMULBB_GE 3564 arm_SMULBB_LT 3565 arm_SMULBB_GT 3566 arm_SMULBB_LE 3567 arm_SMULBB 3568 arm_SMULBB_ZZ 3569 arm_SMULBT_EQ 3570 arm_SMULBT_NE 3571 arm_SMULBT_CS 3572 arm_SMULBT_CC 3573 arm_SMULBT_MI 3574 arm_SMULBT_PL 3575 arm_SMULBT_VS 3576 arm_SMULBT_VC 3577 arm_SMULBT_HI 3578 arm_SMULBT_LS 3579 arm_SMULBT_GE 3580 arm_SMULBT_LT 3581 arm_SMULBT_GT 3582 arm_SMULBT_LE 3583 arm_SMULBT 3584 arm_SMULBT_ZZ 3585 arm_SMULTB_EQ 3586 arm_SMULTB_NE 3587 arm_SMULTB_CS 3588 arm_SMULTB_CC 3589 arm_SMULTB_MI 3590 arm_SMULTB_PL 3591 arm_SMULTB_VS 3592 arm_SMULTB_VC 3593 arm_SMULTB_HI 3594 arm_SMULTB_LS 3595 arm_SMULTB_GE 3596 arm_SMULTB_LT 3597 arm_SMULTB_GT 3598 arm_SMULTB_LE 3599 arm_SMULTB 3600 arm_SMULTB_ZZ 3601 arm_SMULTT_EQ 3602 arm_SMULTT_NE 3603 arm_SMULTT_CS 3604 arm_SMULTT_CC 3605 arm_SMULTT_MI 3606 arm_SMULTT_PL 3607 arm_SMULTT_VS 3608 arm_SMULTT_VC 3609 arm_SMULTT_HI 3610 arm_SMULTT_LS 3611 arm_SMULTT_GE 3612 arm_SMULTT_LT 3613 arm_SMULTT_GT 3614 arm_SMULTT_LE 3615 arm_SMULTT 3616 arm_SMULTT_ZZ 3617 arm_SMULL_EQ 3618 arm_SMULL_NE 3619 arm_SMULL_CS 3620 arm_SMULL_CC 3621 arm_SMULL_MI 3622 arm_SMULL_PL 3623 arm_SMULL_VS 3624 arm_SMULL_VC 3625 arm_SMULL_HI 3626 arm_SMULL_LS 3627 arm_SMULL_GE 3628 arm_SMULL_LT 3629 arm_SMULL_GT 3630 arm_SMULL_LE 3631 arm_SMULL 3632 arm_SMULL_ZZ 3633 arm_SMULL_S_EQ 3634 arm_SMULL_S_NE 3635 arm_SMULL_S_CS 3636 arm_SMULL_S_CC 3637 arm_SMULL_S_MI 3638 arm_SMULL_S_PL 3639 arm_SMULL_S_VS 3640 arm_SMULL_S_VC 3641 arm_SMULL_S_HI 3642 arm_SMULL_S_LS 3643 arm_SMULL_S_GE 3644 arm_SMULL_S_LT 3645 arm_SMULL_S_GT 3646 arm_SMULL_S_LE 3647 arm_SMULL_S 3648 arm_SMULL_S_ZZ 3649 arm_SMULWB_EQ 3650 arm_SMULWB_NE 3651 arm_SMULWB_CS 3652 arm_SMULWB_CC 3653 arm_SMULWB_MI 3654 arm_SMULWB_PL 3655 arm_SMULWB_VS 3656 arm_SMULWB_VC 3657 arm_SMULWB_HI 3658 arm_SMULWB_LS 3659 arm_SMULWB_GE 3660 arm_SMULWB_LT 3661 arm_SMULWB_GT 3662 arm_SMULWB_LE 3663 arm_SMULWB 3664 arm_SMULWB_ZZ 3665 arm_SMULWT_EQ 3666 arm_SMULWT_NE 3667 arm_SMULWT_CS 3668 arm_SMULWT_CC 3669 arm_SMULWT_MI 3670 arm_SMULWT_PL 3671 arm_SMULWT_VS 3672 arm_SMULWT_VC 3673 arm_SMULWT_HI 3674 arm_SMULWT_LS 3675 arm_SMULWT_GE 3676 arm_SMULWT_LT 3677 arm_SMULWT_GT 3678 arm_SMULWT_LE 3679 arm_SMULWT 3680 arm_SMULWT_ZZ 3681 arm_SMUSD_EQ 3682 arm_SMUSD_NE 3683 arm_SMUSD_CS 3684 arm_SMUSD_CC 3685 arm_SMUSD_MI 3686 arm_SMUSD_PL 3687 arm_SMUSD_VS 3688 arm_SMUSD_VC 3689 arm_SMUSD_HI 3690 arm_SMUSD_LS 3691 arm_SMUSD_GE 3692 arm_SMUSD_LT 3693 arm_SMUSD_GT 3694 arm_SMUSD_LE 3695 arm_SMUSD 3696 arm_SMUSD_ZZ 3697 arm_SMUSD_X_EQ 3698 arm_SMUSD_X_NE 3699 arm_SMUSD_X_CS 3700 arm_SMUSD_X_CC 3701 arm_SMUSD_X_MI 3702 arm_SMUSD_X_PL 3703 arm_SMUSD_X_VS 3704 arm_SMUSD_X_VC 3705 arm_SMUSD_X_HI 3706 arm_SMUSD_X_LS 3707 arm_SMUSD_X_GE 3708 arm_SMUSD_X_LT 3709 arm_SMUSD_X_GT 3710 arm_SMUSD_X_LE 3711 arm_SMUSD_X 3712 arm_SMUSD_X_ZZ 3713 arm_SSAT_EQ 3714 arm_SSAT_NE 3715 arm_SSAT_CS 3716 arm_SSAT_CC 3717 arm_SSAT_MI 3718 arm_SSAT_PL 3719 arm_SSAT_VS 3720 arm_SSAT_VC 3721 arm_SSAT_HI 3722 arm_SSAT_LS 3723 arm_SSAT_GE 3724 arm_SSAT_LT 3725 arm_SSAT_GT 3726 arm_SSAT_LE 3727 arm_SSAT 3728 arm_SSAT_ZZ 3729 arm_SSAT16_EQ 3730 arm_SSAT16_NE 3731 arm_SSAT16_CS 3732 arm_SSAT16_CC 3733 arm_SSAT16_MI 3734 arm_SSAT16_PL 3735 arm_SSAT16_VS 3736 arm_SSAT16_VC 3737 arm_SSAT16_HI 3738 arm_SSAT16_LS 3739 arm_SSAT16_GE 3740 arm_SSAT16_LT 3741 arm_SSAT16_GT 3742 arm_SSAT16_LE 3743 arm_SSAT16 3744 arm_SSAT16_ZZ 3745 arm_SSAX_EQ 3746 arm_SSAX_NE 3747 arm_SSAX_CS 3748 arm_SSAX_CC 3749 arm_SSAX_MI 3750 arm_SSAX_PL 3751 arm_SSAX_VS 3752 arm_SSAX_VC 3753 arm_SSAX_HI 3754 arm_SSAX_LS 3755 arm_SSAX_GE 3756 arm_SSAX_LT 3757 arm_SSAX_GT 3758 arm_SSAX_LE 3759 arm_SSAX 3760 arm_SSAX_ZZ 3761 arm_SSUB16_EQ 3762 arm_SSUB16_NE 3763 arm_SSUB16_CS 3764 arm_SSUB16_CC 3765 arm_SSUB16_MI 3766 arm_SSUB16_PL 3767 arm_SSUB16_VS 3768 arm_SSUB16_VC 3769 arm_SSUB16_HI 3770 arm_SSUB16_LS 3771 arm_SSUB16_GE 3772 arm_SSUB16_LT 3773 arm_SSUB16_GT 3774 arm_SSUB16_LE 3775 arm_SSUB16 3776 arm_SSUB16_ZZ 3777 arm_SSUB8_EQ 3778 arm_SSUB8_NE 3779 arm_SSUB8_CS 3780 arm_SSUB8_CC 3781 arm_SSUB8_MI 3782 arm_SSUB8_PL 3783 arm_SSUB8_VS 3784 arm_SSUB8_VC 3785 arm_SSUB8_HI 3786 arm_SSUB8_LS 3787 arm_SSUB8_GE 3788 arm_SSUB8_LT 3789 arm_SSUB8_GT 3790 arm_SSUB8_LE 3791 arm_SSUB8 3792 arm_SSUB8_ZZ 3793 arm_STM_EQ 3794 arm_STM_NE 3795 arm_STM_CS 3796 arm_STM_CC 3797 arm_STM_MI 3798 arm_STM_PL 3799 arm_STM_VS 3800 arm_STM_VC 3801 arm_STM_HI 3802 arm_STM_LS 3803 arm_STM_GE 3804 arm_STM_LT 3805 arm_STM_GT 3806 arm_STM_LE 3807 arm_STM 3808 arm_STM_ZZ 3809 arm_STMDA_EQ 3810 arm_STMDA_NE 3811 arm_STMDA_CS 3812 arm_STMDA_CC 3813 arm_STMDA_MI 3814 arm_STMDA_PL 3815 arm_STMDA_VS 3816 arm_STMDA_VC 3817 arm_STMDA_HI 3818 arm_STMDA_LS 3819 arm_STMDA_GE 3820 arm_STMDA_LT 3821 arm_STMDA_GT 3822 arm_STMDA_LE 3823 arm_STMDA 3824 arm_STMDA_ZZ 3825 arm_STMDB_EQ 3826 arm_STMDB_NE 3827 arm_STMDB_CS 3828 arm_STMDB_CC 3829 arm_STMDB_MI 3830 arm_STMDB_PL 3831 arm_STMDB_VS 3832 arm_STMDB_VC 3833 arm_STMDB_HI 3834 arm_STMDB_LS 3835 arm_STMDB_GE 3836 arm_STMDB_LT 3837 arm_STMDB_GT 3838 arm_STMDB_LE 3839 arm_STMDB 3840 arm_STMDB_ZZ 3841 arm_STMIB_EQ 3842 arm_STMIB_NE 3843 arm_STMIB_CS 3844 arm_STMIB_CC 3845 arm_STMIB_MI 3846 arm_STMIB_PL 3847 arm_STMIB_VS 3848 arm_STMIB_VC 3849 arm_STMIB_HI 3850 arm_STMIB_LS 3851 arm_STMIB_GE 3852 arm_STMIB_LT 3853 arm_STMIB_GT 3854 arm_STMIB_LE 3855 arm_STMIB 3856 arm_STMIB_ZZ 3857 arm_STR_EQ 3858 arm_STR_NE 3859 arm_STR_CS 3860 arm_STR_CC 3861 arm_STR_MI 3862 arm_STR_PL 3863 arm_STR_VS 3864 arm_STR_VC 3865 arm_STR_HI 3866 arm_STR_LS 3867 arm_STR_GE 3868 arm_STR_LT 3869 arm_STR_GT 3870 arm_STR_LE 3871 arm_STR 3872 arm_STR_ZZ 3873 arm_STRB_EQ 3874 arm_STRB_NE 3875 arm_STRB_CS 3876 arm_STRB_CC 3877 arm_STRB_MI 3878 arm_STRB_PL 3879 arm_STRB_VS 3880 arm_STRB_VC 3881 arm_STRB_HI 3882 arm_STRB_LS 3883 arm_STRB_GE 3884 arm_STRB_LT 3885 arm_STRB_GT 3886 arm_STRB_LE 3887 arm_STRB 3888 arm_STRB_ZZ 3889 arm_STRBT_EQ 3890 arm_STRBT_NE 3891 arm_STRBT_CS 3892 arm_STRBT_CC 3893 arm_STRBT_MI 3894 arm_STRBT_PL 3895 arm_STRBT_VS 3896 arm_STRBT_VC 3897 arm_STRBT_HI 3898 arm_STRBT_LS 3899 arm_STRBT_GE 3900 arm_STRBT_LT 3901 arm_STRBT_GT 3902 arm_STRBT_LE 3903 arm_STRBT 3904 arm_STRBT_ZZ 3905 arm_STRD_EQ 3906 arm_STRD_NE 3907 arm_STRD_CS 3908 arm_STRD_CC 3909 arm_STRD_MI 3910 arm_STRD_PL 3911 arm_STRD_VS 3912 arm_STRD_VC 3913 arm_STRD_HI 3914 arm_STRD_LS 3915 arm_STRD_GE 3916 arm_STRD_LT 3917 arm_STRD_GT 3918 arm_STRD_LE 3919 arm_STRD 3920 arm_STRD_ZZ 3921 arm_STREX_EQ 3922 arm_STREX_NE 3923 arm_STREX_CS 3924 arm_STREX_CC 3925 arm_STREX_MI 3926 arm_STREX_PL 3927 arm_STREX_VS 3928 arm_STREX_VC 3929 arm_STREX_HI 3930 arm_STREX_LS 3931 arm_STREX_GE 3932 arm_STREX_LT 3933 arm_STREX_GT 3934 arm_STREX_LE 3935 arm_STREX 3936 arm_STREX_ZZ 3937 arm_STREXB_EQ 3938 arm_STREXB_NE 3939 arm_STREXB_CS 3940 arm_STREXB_CC 3941 arm_STREXB_MI 3942 arm_STREXB_PL 3943 arm_STREXB_VS 3944 arm_STREXB_VC 3945 arm_STREXB_HI 3946 arm_STREXB_LS 3947 arm_STREXB_GE 3948 arm_STREXB_LT 3949 arm_STREXB_GT 3950 arm_STREXB_LE 3951 arm_STREXB 3952 arm_STREXB_ZZ 3953 arm_STREXD_EQ 3954 arm_STREXD_NE 3955 arm_STREXD_CS 3956 arm_STREXD_CC 3957 arm_STREXD_MI 3958 arm_STREXD_PL 3959 arm_STREXD_VS 3960 arm_STREXD_VC 3961 arm_STREXD_HI 3962 arm_STREXD_LS 3963 arm_STREXD_GE 3964 arm_STREXD_LT 3965 arm_STREXD_GT 3966 arm_STREXD_LE 3967 arm_STREXD 3968 arm_STREXD_ZZ 3969 arm_STREXH_EQ 3970 arm_STREXH_NE 3971 arm_STREXH_CS 3972 arm_STREXH_CC 3973 arm_STREXH_MI 3974 arm_STREXH_PL 3975 arm_STREXH_VS 3976 arm_STREXH_VC 3977 arm_STREXH_HI 3978 arm_STREXH_LS 3979 arm_STREXH_GE 3980 arm_STREXH_LT 3981 arm_STREXH_GT 3982 arm_STREXH_LE 3983 arm_STREXH 3984 arm_STREXH_ZZ 3985 arm_STRH_EQ 3986 arm_STRH_NE 3987 arm_STRH_CS 3988 arm_STRH_CC 3989 arm_STRH_MI 3990 arm_STRH_PL 3991 arm_STRH_VS 3992 arm_STRH_VC 3993 arm_STRH_HI 3994 arm_STRH_LS 3995 arm_STRH_GE 3996 arm_STRH_LT 3997 arm_STRH_GT 3998 arm_STRH_LE 3999 arm_STRH 4000 arm_STRH_ZZ 4001 arm_STRHT_EQ 4002 arm_STRHT_NE 4003 arm_STRHT_CS 4004 arm_STRHT_CC 4005 arm_STRHT_MI 4006 arm_STRHT_PL 4007 arm_STRHT_VS 4008 arm_STRHT_VC 4009 arm_STRHT_HI 4010 arm_STRHT_LS 4011 arm_STRHT_GE 4012 arm_STRHT_LT 4013 arm_STRHT_GT 4014 arm_STRHT_LE 4015 arm_STRHT 4016 arm_STRHT_ZZ 4017 arm_STRT_EQ 4018 arm_STRT_NE 4019 arm_STRT_CS 4020 arm_STRT_CC 4021 arm_STRT_MI 4022 arm_STRT_PL 4023 arm_STRT_VS 4024 arm_STRT_VC 4025 arm_STRT_HI 4026 arm_STRT_LS 4027 arm_STRT_GE 4028 arm_STRT_LT 4029 arm_STRT_GT 4030 arm_STRT_LE 4031 arm_STRT 4032 arm_STRT_ZZ 4033 arm_SUB_EQ 4034 arm_SUB_NE 4035 arm_SUB_CS 4036 arm_SUB_CC 4037 arm_SUB_MI 4038 arm_SUB_PL 4039 arm_SUB_VS 4040 arm_SUB_VC 4041 arm_SUB_HI 4042 arm_SUB_LS 4043 arm_SUB_GE 4044 arm_SUB_LT 4045 arm_SUB_GT 4046 arm_SUB_LE 4047 arm_SUB 4048 arm_SUB_ZZ 4049 arm_SUB_S_EQ 4050 arm_SUB_S_NE 4051 arm_SUB_S_CS 4052 arm_SUB_S_CC 4053 arm_SUB_S_MI 4054 arm_SUB_S_PL 4055 arm_SUB_S_VS 4056 arm_SUB_S_VC 4057 arm_SUB_S_HI 4058 arm_SUB_S_LS 4059 arm_SUB_S_GE 4060 arm_SUB_S_LT 4061 arm_SUB_S_GT 4062 arm_SUB_S_LE 4063 arm_SUB_S 4064 arm_SUB_S_ZZ 4065 arm_SVC_EQ 4066 arm_SVC_NE 4067 arm_SVC_CS 4068 arm_SVC_CC 4069 arm_SVC_MI 4070 arm_SVC_PL 4071 arm_SVC_VS 4072 arm_SVC_VC 4073 arm_SVC_HI 4074 arm_SVC_LS 4075 arm_SVC_GE 4076 arm_SVC_LT 4077 arm_SVC_GT 4078 arm_SVC_LE 4079 arm_SVC 4080 arm_SVC_ZZ 4081 arm_SWP_EQ 4082 arm_SWP_NE 4083 arm_SWP_CS 4084 arm_SWP_CC 4085 arm_SWP_MI 4086 arm_SWP_PL 4087 arm_SWP_VS 4088 arm_SWP_VC 4089 arm_SWP_HI 4090 arm_SWP_LS 4091 arm_SWP_GE 4092 arm_SWP_LT 4093 arm_SWP_GT 4094 arm_SWP_LE 4095 arm_SWP 4096 arm_SWP_ZZ 4097 arm_SWP_B_EQ 4098 arm_SWP_B_NE 4099 arm_SWP_B_CS 4100 arm_SWP_B_CC 4101 arm_SWP_B_MI 4102 arm_SWP_B_PL 4103 arm_SWP_B_VS 4104 arm_SWP_B_VC 4105 arm_SWP_B_HI 4106 arm_SWP_B_LS 4107 arm_SWP_B_GE 4108 arm_SWP_B_LT 4109 arm_SWP_B_GT 4110 arm_SWP_B_LE 4111 arm_SWP_B 4112 arm_SWP_B_ZZ 4113 arm_SXTAB_EQ 4114 arm_SXTAB_NE 4115 arm_SXTAB_CS 4116 arm_SXTAB_CC 4117 arm_SXTAB_MI 4118 arm_SXTAB_PL 4119 arm_SXTAB_VS 4120 arm_SXTAB_VC 4121 arm_SXTAB_HI 4122 arm_SXTAB_LS 4123 arm_SXTAB_GE 4124 arm_SXTAB_LT 4125 arm_SXTAB_GT 4126 arm_SXTAB_LE 4127 arm_SXTAB 4128 arm_SXTAB_ZZ 4129 arm_SXTAB16_EQ 4130 arm_SXTAB16_NE 4131 arm_SXTAB16_CS 4132 arm_SXTAB16_CC 4133 arm_SXTAB16_MI 4134 arm_SXTAB16_PL 4135 arm_SXTAB16_VS 4136 arm_SXTAB16_VC 4137 arm_SXTAB16_HI 4138 arm_SXTAB16_LS 4139 arm_SXTAB16_GE 4140 arm_SXTAB16_LT 4141 arm_SXTAB16_GT 4142 arm_SXTAB16_LE 4143 arm_SXTAB16 4144 arm_SXTAB16_ZZ 4145 arm_SXTAH_EQ 4146 arm_SXTAH_NE 4147 arm_SXTAH_CS 4148 arm_SXTAH_CC 4149 arm_SXTAH_MI 4150 arm_SXTAH_PL 4151 arm_SXTAH_VS 4152 arm_SXTAH_VC 4153 arm_SXTAH_HI 4154 arm_SXTAH_LS 4155 arm_SXTAH_GE 4156 arm_SXTAH_LT 4157 arm_SXTAH_GT 4158 arm_SXTAH_LE 4159 arm_SXTAH 4160 arm_SXTAH_ZZ 4161 arm_SXTB_EQ 4162 arm_SXTB_NE 4163 arm_SXTB_CS 4164 arm_SXTB_CC 4165 arm_SXTB_MI 4166 arm_SXTB_PL 4167 arm_SXTB_VS 4168 arm_SXTB_VC 4169 arm_SXTB_HI 4170 arm_SXTB_LS 4171 arm_SXTB_GE 4172 arm_SXTB_LT 4173 arm_SXTB_GT 4174 arm_SXTB_LE 4175 arm_SXTB 4176 arm_SXTB_ZZ 4177 arm_SXTB16_EQ 4178 arm_SXTB16_NE 4179 arm_SXTB16_CS 4180 arm_SXTB16_CC 4181 arm_SXTB16_MI 4182 arm_SXTB16_PL 4183 arm_SXTB16_VS 4184 arm_SXTB16_VC 4185 arm_SXTB16_HI 4186 arm_SXTB16_LS 4187 arm_SXTB16_GE 4188 arm_SXTB16_LT 4189 arm_SXTB16_GT 4190 arm_SXTB16_LE 4191 arm_SXTB16 4192 arm_SXTB16_ZZ 4193 arm_SXTH_EQ 4194 arm_SXTH_NE 4195 arm_SXTH_CS 4196 arm_SXTH_CC 4197 arm_SXTH_MI 4198 arm_SXTH_PL 4199 arm_SXTH_VS 4200 arm_SXTH_VC 4201 arm_SXTH_HI 4202 arm_SXTH_LS 4203 arm_SXTH_GE 4204 arm_SXTH_LT 4205 arm_SXTH_GT 4206 arm_SXTH_LE 4207 arm_SXTH 4208 arm_SXTH_ZZ 4209 arm_TEQ_EQ 4210 arm_TEQ_NE 4211 arm_TEQ_CS 4212 arm_TEQ_CC 4213 arm_TEQ_MI 4214 arm_TEQ_PL 4215 arm_TEQ_VS 4216 arm_TEQ_VC 4217 arm_TEQ_HI 4218 arm_TEQ_LS 4219 arm_TEQ_GE 4220 arm_TEQ_LT 4221 arm_TEQ_GT 4222 arm_TEQ_LE 4223 arm_TEQ 4224 arm_TEQ_ZZ 4225 arm_TST_EQ 4226 arm_TST_NE 4227 arm_TST_CS 4228 arm_TST_CC 4229 arm_TST_MI 4230 arm_TST_PL 4231 arm_TST_VS 4232 arm_TST_VC 4233 arm_TST_HI 4234 arm_TST_LS 4235 arm_TST_GE 4236 arm_TST_LT 4237 arm_TST_GT 4238 arm_TST_LE 4239 arm_TST 4240 arm_TST_ZZ 4241 arm_UADD16_EQ 4242 arm_UADD16_NE 4243 arm_UADD16_CS 4244 arm_UADD16_CC 4245 arm_UADD16_MI 4246 arm_UADD16_PL 4247 arm_UADD16_VS 4248 arm_UADD16_VC 4249 arm_UADD16_HI 4250 arm_UADD16_LS 4251 arm_UADD16_GE 4252 arm_UADD16_LT 4253 arm_UADD16_GT 4254 arm_UADD16_LE 4255 arm_UADD16 4256 arm_UADD16_ZZ 4257 arm_UADD8_EQ 4258 arm_UADD8_NE 4259 arm_UADD8_CS 4260 arm_UADD8_CC 4261 arm_UADD8_MI 4262 arm_UADD8_PL 4263 arm_UADD8_VS 4264 arm_UADD8_VC 4265 arm_UADD8_HI 4266 arm_UADD8_LS 4267 arm_UADD8_GE 4268 arm_UADD8_LT 4269 arm_UADD8_GT 4270 arm_UADD8_LE 4271 arm_UADD8 4272 arm_UADD8_ZZ 4273 arm_UASX_EQ 4274 arm_UASX_NE 4275 arm_UASX_CS 4276 arm_UASX_CC 4277 arm_UASX_MI 4278 arm_UASX_PL 4279 arm_UASX_VS 4280 arm_UASX_VC 4281 arm_UASX_HI 4282 arm_UASX_LS 4283 arm_UASX_GE 4284 arm_UASX_LT 4285 arm_UASX_GT 4286 arm_UASX_LE 4287 arm_UASX 4288 arm_UASX_ZZ 4289 arm_UBFX_EQ 4290 arm_UBFX_NE 4291 arm_UBFX_CS 4292 arm_UBFX_CC 4293 arm_UBFX_MI 4294 arm_UBFX_PL 4295 arm_UBFX_VS 4296 arm_UBFX_VC 4297 arm_UBFX_HI 4298 arm_UBFX_LS 4299 arm_UBFX_GE 4300 arm_UBFX_LT 4301 arm_UBFX_GT 4302 arm_UBFX_LE 4303 arm_UBFX 4304 arm_UBFX_ZZ 4305 arm_UHADD16_EQ 4306 arm_UHADD16_NE 4307 arm_UHADD16_CS 4308 arm_UHADD16_CC 4309 arm_UHADD16_MI 4310 arm_UHADD16_PL 4311 arm_UHADD16_VS 4312 arm_UHADD16_VC 4313 arm_UHADD16_HI 4314 arm_UHADD16_LS 4315 arm_UHADD16_GE 4316 arm_UHADD16_LT 4317 arm_UHADD16_GT 4318 arm_UHADD16_LE 4319 arm_UHADD16 4320 arm_UHADD16_ZZ 4321 arm_UHADD8_EQ 4322 arm_UHADD8_NE 4323 arm_UHADD8_CS 4324 arm_UHADD8_CC 4325 arm_UHADD8_MI 4326 arm_UHADD8_PL 4327 arm_UHADD8_VS 4328 arm_UHADD8_VC 4329 arm_UHADD8_HI 4330 arm_UHADD8_LS 4331 arm_UHADD8_GE 4332 arm_UHADD8_LT 4333 arm_UHADD8_GT 4334 arm_UHADD8_LE 4335 arm_UHADD8 4336 arm_UHADD8_ZZ 4337 arm_UHASX_EQ 4338 arm_UHASX_NE 4339 arm_UHASX_CS 4340 arm_UHASX_CC 4341 arm_UHASX_MI 4342 arm_UHASX_PL 4343 arm_UHASX_VS 4344 arm_UHASX_VC 4345 arm_UHASX_HI 4346 arm_UHASX_LS 4347 arm_UHASX_GE 4348 arm_UHASX_LT 4349 arm_UHASX_GT 4350 arm_UHASX_LE 4351 arm_UHASX 4352 arm_UHASX_ZZ 4353 arm_UHSAX_EQ 4354 arm_UHSAX_NE 4355 arm_UHSAX_CS 4356 arm_UHSAX_CC 4357 arm_UHSAX_MI 4358 arm_UHSAX_PL 4359 arm_UHSAX_VS 4360 arm_UHSAX_VC 4361 arm_UHSAX_HI 4362 arm_UHSAX_LS 4363 arm_UHSAX_GE 4364 arm_UHSAX_LT 4365 arm_UHSAX_GT 4366 arm_UHSAX_LE 4367 arm_UHSAX 4368 arm_UHSAX_ZZ 4369 arm_UHSUB16_EQ 4370 arm_UHSUB16_NE 4371 arm_UHSUB16_CS 4372 arm_UHSUB16_CC 4373 arm_UHSUB16_MI 4374 arm_UHSUB16_PL 4375 arm_UHSUB16_VS 4376 arm_UHSUB16_VC 4377 arm_UHSUB16_HI 4378 arm_UHSUB16_LS 4379 arm_UHSUB16_GE 4380 arm_UHSUB16_LT 4381 arm_UHSUB16_GT 4382 arm_UHSUB16_LE 4383 arm_UHSUB16 4384 arm_UHSUB16_ZZ 4385 arm_UHSUB8_EQ 4386 arm_UHSUB8_NE 4387 arm_UHSUB8_CS 4388 arm_UHSUB8_CC 4389 arm_UHSUB8_MI 4390 arm_UHSUB8_PL 4391 arm_UHSUB8_VS 4392 arm_UHSUB8_VC 4393 arm_UHSUB8_HI 4394 arm_UHSUB8_LS 4395 arm_UHSUB8_GE 4396 arm_UHSUB8_LT 4397 arm_UHSUB8_GT 4398 arm_UHSUB8_LE 4399 arm_UHSUB8 4400 arm_UHSUB8_ZZ 4401 arm_UMAAL_EQ 4402 arm_UMAAL_NE 4403 arm_UMAAL_CS 4404 arm_UMAAL_CC 4405 arm_UMAAL_MI 4406 arm_UMAAL_PL 4407 arm_UMAAL_VS 4408 arm_UMAAL_VC 4409 arm_UMAAL_HI 4410 arm_UMAAL_LS 4411 arm_UMAAL_GE 4412 arm_UMAAL_LT 4413 arm_UMAAL_GT 4414 arm_UMAAL_LE 4415 arm_UMAAL 4416 arm_UMAAL_ZZ 4417 arm_UMLAL_EQ 4418 arm_UMLAL_NE 4419 arm_UMLAL_CS 4420 arm_UMLAL_CC 4421 arm_UMLAL_MI 4422 arm_UMLAL_PL 4423 arm_UMLAL_VS 4424 arm_UMLAL_VC 4425 arm_UMLAL_HI 4426 arm_UMLAL_LS 4427 arm_UMLAL_GE 4428 arm_UMLAL_LT 4429 arm_UMLAL_GT 4430 arm_UMLAL_LE 4431 arm_UMLAL 4432 arm_UMLAL_ZZ 4433 arm_UMLAL_S_EQ 4434 arm_UMLAL_S_NE 4435 arm_UMLAL_S_CS 4436 arm_UMLAL_S_CC 4437 arm_UMLAL_S_MI 4438 arm_UMLAL_S_PL 4439 arm_UMLAL_S_VS 4440 arm_UMLAL_S_VC 4441 arm_UMLAL_S_HI 4442 arm_UMLAL_S_LS 4443 arm_UMLAL_S_GE 4444 arm_UMLAL_S_LT 4445 arm_UMLAL_S_GT 4446 arm_UMLAL_S_LE 4447 arm_UMLAL_S 4448 arm_UMLAL_S_ZZ 4449 arm_UMULL_EQ 4450 arm_UMULL_NE 4451 arm_UMULL_CS 4452 arm_UMULL_CC 4453 arm_UMULL_MI 4454 arm_UMULL_PL 4455 arm_UMULL_VS 4456 arm_UMULL_VC 4457 arm_UMULL_HI 4458 arm_UMULL_LS 4459 arm_UMULL_GE 4460 arm_UMULL_LT 4461 arm_UMULL_GT 4462 arm_UMULL_LE 4463 arm_UMULL 4464 arm_UMULL_ZZ 4465 arm_UMULL_S_EQ 4466 arm_UMULL_S_NE 4467 arm_UMULL_S_CS 4468 arm_UMULL_S_CC 4469 arm_UMULL_S_MI 4470 arm_UMULL_S_PL 4471 arm_UMULL_S_VS 4472 arm_UMULL_S_VC 4473 arm_UMULL_S_HI 4474 arm_UMULL_S_LS 4475 arm_UMULL_S_GE 4476 arm_UMULL_S_LT 4477 arm_UMULL_S_GT 4478 arm_UMULL_S_LE 4479 arm_UMULL_S 4480 arm_UMULL_S_ZZ 4481 arm_UNDEF 4482 _ 4483 _ 4484 _ 4485 _ 4486 _ 4487 _ 4488 _ 4489 _ 4490 _ 4491 _ 4492 _ 4493 _ 4494 _ 4495 _ 4496 _ 4497 arm_UQADD16_EQ 4498 arm_UQADD16_NE 4499 arm_UQADD16_CS 4500 arm_UQADD16_CC 4501 arm_UQADD16_MI 4502 arm_UQADD16_PL 4503 arm_UQADD16_VS 4504 arm_UQADD16_VC 4505 arm_UQADD16_HI 4506 arm_UQADD16_LS 4507 arm_UQADD16_GE 4508 arm_UQADD16_LT 4509 arm_UQADD16_GT 4510 arm_UQADD16_LE 4511 arm_UQADD16 4512 arm_UQADD16_ZZ 4513 arm_UQADD8_EQ 4514 arm_UQADD8_NE 4515 arm_UQADD8_CS 4516 arm_UQADD8_CC 4517 arm_UQADD8_MI 4518 arm_UQADD8_PL 4519 arm_UQADD8_VS 4520 arm_UQADD8_VC 4521 arm_UQADD8_HI 4522 arm_UQADD8_LS 4523 arm_UQADD8_GE 4524 arm_UQADD8_LT 4525 arm_UQADD8_GT 4526 arm_UQADD8_LE 4527 arm_UQADD8 4528 arm_UQADD8_ZZ 4529 arm_UQASX_EQ 4530 arm_UQASX_NE 4531 arm_UQASX_CS 4532 arm_UQASX_CC 4533 arm_UQASX_MI 4534 arm_UQASX_PL 4535 arm_UQASX_VS 4536 arm_UQASX_VC 4537 arm_UQASX_HI 4538 arm_UQASX_LS 4539 arm_UQASX_GE 4540 arm_UQASX_LT 4541 arm_UQASX_GT 4542 arm_UQASX_LE 4543 arm_UQASX 4544 arm_UQASX_ZZ 4545 arm_UQSAX_EQ 4546 arm_UQSAX_NE 4547 arm_UQSAX_CS 4548 arm_UQSAX_CC 4549 arm_UQSAX_MI 4550 arm_UQSAX_PL 4551 arm_UQSAX_VS 4552 arm_UQSAX_VC 4553 arm_UQSAX_HI 4554 arm_UQSAX_LS 4555 arm_UQSAX_GE 4556 arm_UQSAX_LT 4557 arm_UQSAX_GT 4558 arm_UQSAX_LE 4559 arm_UQSAX 4560 arm_UQSAX_ZZ 4561 arm_UQSUB16_EQ 4562 arm_UQSUB16_NE 4563 arm_UQSUB16_CS 4564 arm_UQSUB16_CC 4565 arm_UQSUB16_MI 4566 arm_UQSUB16_PL 4567 arm_UQSUB16_VS 4568 arm_UQSUB16_VC 4569 arm_UQSUB16_HI 4570 arm_UQSUB16_LS 4571 arm_UQSUB16_GE 4572 arm_UQSUB16_LT 4573 arm_UQSUB16_GT 4574 arm_UQSUB16_LE 4575 arm_UQSUB16 4576 arm_UQSUB16_ZZ 4577 arm_UQSUB8_EQ 4578 arm_UQSUB8_NE 4579 arm_UQSUB8_CS 4580 arm_UQSUB8_CC 4581 arm_UQSUB8_MI 4582 arm_UQSUB8_PL 4583 arm_UQSUB8_VS 4584 arm_UQSUB8_VC 4585 arm_UQSUB8_HI 4586 arm_UQSUB8_LS 4587 arm_UQSUB8_GE 4588 arm_UQSUB8_LT 4589 arm_UQSUB8_GT 4590 arm_UQSUB8_LE 4591 arm_UQSUB8 4592 arm_UQSUB8_ZZ 4593 arm_USAD8_EQ 4594 arm_USAD8_NE 4595 arm_USAD8_CS 4596 arm_USAD8_CC 4597 arm_USAD8_MI 4598 arm_USAD8_PL 4599 arm_USAD8_VS 4600 arm_USAD8_VC 4601 arm_USAD8_HI 4602 arm_USAD8_LS 4603 arm_USAD8_GE 4604 arm_USAD8_LT 4605 arm_USAD8_GT 4606 arm_USAD8_LE 4607 arm_USAD8 4608 arm_USAD8_ZZ 4609 arm_USADA8_EQ 4610 arm_USADA8_NE 4611 arm_USADA8_CS 4612 arm_USADA8_CC 4613 arm_USADA8_MI 4614 arm_USADA8_PL 4615 arm_USADA8_VS 4616 arm_USADA8_VC 4617 arm_USADA8_HI 4618 arm_USADA8_LS 4619 arm_USADA8_GE 4620 arm_USADA8_LT 4621 arm_USADA8_GT 4622 arm_USADA8_LE 4623 arm_USADA8 4624 arm_USADA8_ZZ 4625 arm_USAT_EQ 4626 arm_USAT_NE 4627 arm_USAT_CS 4628 arm_USAT_CC 4629 arm_USAT_MI 4630 arm_USAT_PL 4631 arm_USAT_VS 4632 arm_USAT_VC 4633 arm_USAT_HI 4634 arm_USAT_LS 4635 arm_USAT_GE 4636 arm_USAT_LT 4637 arm_USAT_GT 4638 arm_USAT_LE 4639 arm_USAT 4640 arm_USAT_ZZ 4641 arm_USAT16_EQ 4642 arm_USAT16_NE 4643 arm_USAT16_CS 4644 arm_USAT16_CC 4645 arm_USAT16_MI 4646 arm_USAT16_PL 4647 arm_USAT16_VS 4648 arm_USAT16_VC 4649 arm_USAT16_HI 4650 arm_USAT16_LS 4651 arm_USAT16_GE 4652 arm_USAT16_LT 4653 arm_USAT16_GT 4654 arm_USAT16_LE 4655 arm_USAT16 4656 arm_USAT16_ZZ 4657 arm_USAX_EQ 4658 arm_USAX_NE 4659 arm_USAX_CS 4660 arm_USAX_CC 4661 arm_USAX_MI 4662 arm_USAX_PL 4663 arm_USAX_VS 4664 arm_USAX_VC 4665 arm_USAX_HI 4666 arm_USAX_LS 4667 arm_USAX_GE 4668 arm_USAX_LT 4669 arm_USAX_GT 4670 arm_USAX_LE 4671 arm_USAX 4672 arm_USAX_ZZ 4673 arm_USUB16_EQ 4674 arm_USUB16_NE 4675 arm_USUB16_CS 4676 arm_USUB16_CC 4677 arm_USUB16_MI 4678 arm_USUB16_PL 4679 arm_USUB16_VS 4680 arm_USUB16_VC 4681 arm_USUB16_HI 4682 arm_USUB16_LS 4683 arm_USUB16_GE 4684 arm_USUB16_LT 4685 arm_USUB16_GT 4686 arm_USUB16_LE 4687 arm_USUB16 4688 arm_USUB16_ZZ 4689 arm_USUB8_EQ 4690 arm_USUB8_NE 4691 arm_USUB8_CS 4692 arm_USUB8_CC 4693 arm_USUB8_MI 4694 arm_USUB8_PL 4695 arm_USUB8_VS 4696 arm_USUB8_VC 4697 arm_USUB8_HI 4698 arm_USUB8_LS 4699 arm_USUB8_GE 4700 arm_USUB8_LT 4701 arm_USUB8_GT 4702 arm_USUB8_LE 4703 arm_USUB8 4704 arm_USUB8_ZZ 4705 arm_UXTAB_EQ 4706 arm_UXTAB_NE 4707 arm_UXTAB_CS 4708 arm_UXTAB_CC 4709 arm_UXTAB_MI 4710 arm_UXTAB_PL 4711 arm_UXTAB_VS 4712 arm_UXTAB_VC 4713 arm_UXTAB_HI 4714 arm_UXTAB_LS 4715 arm_UXTAB_GE 4716 arm_UXTAB_LT 4717 arm_UXTAB_GT 4718 arm_UXTAB_LE 4719 arm_UXTAB 4720 arm_UXTAB_ZZ 4721 arm_UXTAB16_EQ 4722 arm_UXTAB16_NE 4723 arm_UXTAB16_CS 4724 arm_UXTAB16_CC 4725 arm_UXTAB16_MI 4726 arm_UXTAB16_PL 4727 arm_UXTAB16_VS 4728 arm_UXTAB16_VC 4729 arm_UXTAB16_HI 4730 arm_UXTAB16_LS 4731 arm_UXTAB16_GE 4732 arm_UXTAB16_LT 4733 arm_UXTAB16_GT 4734 arm_UXTAB16_LE 4735 arm_UXTAB16 4736 arm_UXTAB16_ZZ 4737 arm_UXTAH_EQ 4738 arm_UXTAH_NE 4739 arm_UXTAH_CS 4740 arm_UXTAH_CC 4741 arm_UXTAH_MI 4742 arm_UXTAH_PL 4743 arm_UXTAH_VS 4744 arm_UXTAH_VC 4745 arm_UXTAH_HI 4746 arm_UXTAH_LS 4747 arm_UXTAH_GE 4748 arm_UXTAH_LT 4749 arm_UXTAH_GT 4750 arm_UXTAH_LE 4751 arm_UXTAH 4752 arm_UXTAH_ZZ 4753 arm_UXTB_EQ 4754 arm_UXTB_NE 4755 arm_UXTB_CS 4756 arm_UXTB_CC 4757 arm_UXTB_MI 4758 arm_UXTB_PL 4759 arm_UXTB_VS 4760 arm_UXTB_VC 4761 arm_UXTB_HI 4762 arm_UXTB_LS 4763 arm_UXTB_GE 4764 arm_UXTB_LT 4765 arm_UXTB_GT 4766 arm_UXTB_LE 4767 arm_UXTB 4768 arm_UXTB_ZZ 4769 arm_UXTB16_EQ 4770 arm_UXTB16_NE 4771 arm_UXTB16_CS 4772 arm_UXTB16_CC 4773 arm_UXTB16_MI 4774 arm_UXTB16_PL 4775 arm_UXTB16_VS 4776 arm_UXTB16_VC 4777 arm_UXTB16_HI 4778 arm_UXTB16_LS 4779 arm_UXTB16_GE 4780 arm_UXTB16_LT 4781 arm_UXTB16_GT 4782 arm_UXTB16_LE 4783 arm_UXTB16 4784 arm_UXTB16_ZZ 4785 arm_UXTH_EQ 4786 arm_UXTH_NE 4787 arm_UXTH_CS 4788 arm_UXTH_CC 4789 arm_UXTH_MI 4790 arm_UXTH_PL 4791 arm_UXTH_VS 4792 arm_UXTH_VC 4793 arm_UXTH_HI 4794 arm_UXTH_LS 4795 arm_UXTH_GE 4796 arm_UXTH_LT 4797 arm_UXTH_GT 4798 arm_UXTH_LE 4799 arm_UXTH 4800 arm_UXTH_ZZ 4801 arm_VABS_EQ_F32 4802 arm_VABS_NE_F32 4803 arm_VABS_CS_F32 4804 arm_VABS_CC_F32 4805 arm_VABS_MI_F32 4806 arm_VABS_PL_F32 4807 arm_VABS_VS_F32 4808 arm_VABS_VC_F32 4809 arm_VABS_HI_F32 4810 arm_VABS_LS_F32 4811 arm_VABS_GE_F32 4812 arm_VABS_LT_F32 4813 arm_VABS_GT_F32 4814 arm_VABS_LE_F32 4815 arm_VABS_F32 4816 arm_VABS_ZZ_F32 4817 arm_VABS_EQ_F64 4818 arm_VABS_NE_F64 4819 arm_VABS_CS_F64 4820 arm_VABS_CC_F64 4821 arm_VABS_MI_F64 4822 arm_VABS_PL_F64 4823 arm_VABS_VS_F64 4824 arm_VABS_VC_F64 4825 arm_VABS_HI_F64 4826 arm_VABS_LS_F64 4827 arm_VABS_GE_F64 4828 arm_VABS_LT_F64 4829 arm_VABS_GT_F64 4830 arm_VABS_LE_F64 4831 arm_VABS_F64 4832 arm_VABS_ZZ_F64 4833 arm_VADD_EQ_F32 4834 arm_VADD_NE_F32 4835 arm_VADD_CS_F32 4836 arm_VADD_CC_F32 4837 arm_VADD_MI_F32 4838 arm_VADD_PL_F32 4839 arm_VADD_VS_F32 4840 arm_VADD_VC_F32 4841 arm_VADD_HI_F32 4842 arm_VADD_LS_F32 4843 arm_VADD_GE_F32 4844 arm_VADD_LT_F32 4845 arm_VADD_GT_F32 4846 arm_VADD_LE_F32 4847 arm_VADD_F32 4848 arm_VADD_ZZ_F32 4849 arm_VADD_EQ_F64 4850 arm_VADD_NE_F64 4851 arm_VADD_CS_F64 4852 arm_VADD_CC_F64 4853 arm_VADD_MI_F64 4854 arm_VADD_PL_F64 4855 arm_VADD_VS_F64 4856 arm_VADD_VC_F64 4857 arm_VADD_HI_F64 4858 arm_VADD_LS_F64 4859 arm_VADD_GE_F64 4860 arm_VADD_LT_F64 4861 arm_VADD_GT_F64 4862 arm_VADD_LE_F64 4863 arm_VADD_F64 4864 arm_VADD_ZZ_F64 4865 arm_VCMP_EQ_F32 4866 arm_VCMP_NE_F32 4867 arm_VCMP_CS_F32 4868 arm_VCMP_CC_F32 4869 arm_VCMP_MI_F32 4870 arm_VCMP_PL_F32 4871 arm_VCMP_VS_F32 4872 arm_VCMP_VC_F32 4873 arm_VCMP_HI_F32 4874 arm_VCMP_LS_F32 4875 arm_VCMP_GE_F32 4876 arm_VCMP_LT_F32 4877 arm_VCMP_GT_F32 4878 arm_VCMP_LE_F32 4879 arm_VCMP_F32 4880 arm_VCMP_ZZ_F32 4881 arm_VCMP_EQ_F64 4882 arm_VCMP_NE_F64 4883 arm_VCMP_CS_F64 4884 arm_VCMP_CC_F64 4885 arm_VCMP_MI_F64 4886 arm_VCMP_PL_F64 4887 arm_VCMP_VS_F64 4888 arm_VCMP_VC_F64 4889 arm_VCMP_HI_F64 4890 arm_VCMP_LS_F64 4891 arm_VCMP_GE_F64 4892 arm_VCMP_LT_F64 4893 arm_VCMP_GT_F64 4894 arm_VCMP_LE_F64 4895 arm_VCMP_F64 4896 arm_VCMP_ZZ_F64 4897 arm_VCMP_E_EQ_F32 4898 arm_VCMP_E_NE_F32 4899 arm_VCMP_E_CS_F32 4900 arm_VCMP_E_CC_F32 4901 arm_VCMP_E_MI_F32 4902 arm_VCMP_E_PL_F32 4903 arm_VCMP_E_VS_F32 4904 arm_VCMP_E_VC_F32 4905 arm_VCMP_E_HI_F32 4906 arm_VCMP_E_LS_F32 4907 arm_VCMP_E_GE_F32 4908 arm_VCMP_E_LT_F32 4909 arm_VCMP_E_GT_F32 4910 arm_VCMP_E_LE_F32 4911 arm_VCMP_E_F32 4912 arm_VCMP_E_ZZ_F32 4913 arm_VCMP_E_EQ_F64 4914 arm_VCMP_E_NE_F64 4915 arm_VCMP_E_CS_F64 4916 arm_VCMP_E_CC_F64 4917 arm_VCMP_E_MI_F64 4918 arm_VCMP_E_PL_F64 4919 arm_VCMP_E_VS_F64 4920 arm_VCMP_E_VC_F64 4921 arm_VCMP_E_HI_F64 4922 arm_VCMP_E_LS_F64 4923 arm_VCMP_E_GE_F64 4924 arm_VCMP_E_LT_F64 4925 arm_VCMP_E_GT_F64 4926 arm_VCMP_E_LE_F64 4927 arm_VCMP_E_F64 4928 arm_VCMP_E_ZZ_F64 4929 arm_VCVT_EQ_F32_FXS16 4930 arm_VCVT_NE_F32_FXS16 4931 arm_VCVT_CS_F32_FXS16 4932 arm_VCVT_CC_F32_FXS16 4933 arm_VCVT_MI_F32_FXS16 4934 arm_VCVT_PL_F32_FXS16 4935 arm_VCVT_VS_F32_FXS16 4936 arm_VCVT_VC_F32_FXS16 4937 arm_VCVT_HI_F32_FXS16 4938 arm_VCVT_LS_F32_FXS16 4939 arm_VCVT_GE_F32_FXS16 4940 arm_VCVT_LT_F32_FXS16 4941 arm_VCVT_GT_F32_FXS16 4942 arm_VCVT_LE_F32_FXS16 4943 arm_VCVT_F32_FXS16 4944 arm_VCVT_ZZ_F32_FXS16 4945 arm_VCVT_EQ_F32_FXS32 4946 arm_VCVT_NE_F32_FXS32 4947 arm_VCVT_CS_F32_FXS32 4948 arm_VCVT_CC_F32_FXS32 4949 arm_VCVT_MI_F32_FXS32 4950 arm_VCVT_PL_F32_FXS32 4951 arm_VCVT_VS_F32_FXS32 4952 arm_VCVT_VC_F32_FXS32 4953 arm_VCVT_HI_F32_FXS32 4954 arm_VCVT_LS_F32_FXS32 4955 arm_VCVT_GE_F32_FXS32 4956 arm_VCVT_LT_F32_FXS32 4957 arm_VCVT_GT_F32_FXS32 4958 arm_VCVT_LE_F32_FXS32 4959 arm_VCVT_F32_FXS32 4960 arm_VCVT_ZZ_F32_FXS32 4961 arm_VCVT_EQ_F32_FXU16 4962 arm_VCVT_NE_F32_FXU16 4963 arm_VCVT_CS_F32_FXU16 4964 arm_VCVT_CC_F32_FXU16 4965 arm_VCVT_MI_F32_FXU16 4966 arm_VCVT_PL_F32_FXU16 4967 arm_VCVT_VS_F32_FXU16 4968 arm_VCVT_VC_F32_FXU16 4969 arm_VCVT_HI_F32_FXU16 4970 arm_VCVT_LS_F32_FXU16 4971 arm_VCVT_GE_F32_FXU16 4972 arm_VCVT_LT_F32_FXU16 4973 arm_VCVT_GT_F32_FXU16 4974 arm_VCVT_LE_F32_FXU16 4975 arm_VCVT_F32_FXU16 4976 arm_VCVT_ZZ_F32_FXU16 4977 arm_VCVT_EQ_F32_FXU32 4978 arm_VCVT_NE_F32_FXU32 4979 arm_VCVT_CS_F32_FXU32 4980 arm_VCVT_CC_F32_FXU32 4981 arm_VCVT_MI_F32_FXU32 4982 arm_VCVT_PL_F32_FXU32 4983 arm_VCVT_VS_F32_FXU32 4984 arm_VCVT_VC_F32_FXU32 4985 arm_VCVT_HI_F32_FXU32 4986 arm_VCVT_LS_F32_FXU32 4987 arm_VCVT_GE_F32_FXU32 4988 arm_VCVT_LT_F32_FXU32 4989 arm_VCVT_GT_F32_FXU32 4990 arm_VCVT_LE_F32_FXU32 4991 arm_VCVT_F32_FXU32 4992 arm_VCVT_ZZ_F32_FXU32 4993 arm_VCVT_EQ_F64_FXS16 4994 arm_VCVT_NE_F64_FXS16 4995 arm_VCVT_CS_F64_FXS16 4996 arm_VCVT_CC_F64_FXS16 4997 arm_VCVT_MI_F64_FXS16 4998 arm_VCVT_PL_F64_FXS16 4999 arm_VCVT_VS_F64_FXS16 5000 arm_VCVT_VC_F64_FXS16 5001 arm_VCVT_HI_F64_FXS16 5002 arm_VCVT_LS_F64_FXS16 5003 arm_VCVT_GE_F64_FXS16 5004 arm_VCVT_LT_F64_FXS16 5005 arm_VCVT_GT_F64_FXS16 5006 arm_VCVT_LE_F64_FXS16 5007 arm_VCVT_F64_FXS16 5008 arm_VCVT_ZZ_F64_FXS16 5009 arm_VCVT_EQ_F64_FXS32 5010 arm_VCVT_NE_F64_FXS32 5011 arm_VCVT_CS_F64_FXS32 5012 arm_VCVT_CC_F64_FXS32 5013 arm_VCVT_MI_F64_FXS32 5014 arm_VCVT_PL_F64_FXS32 5015 arm_VCVT_VS_F64_FXS32 5016 arm_VCVT_VC_F64_FXS32 5017 arm_VCVT_HI_F64_FXS32 5018 arm_VCVT_LS_F64_FXS32 5019 arm_VCVT_GE_F64_FXS32 5020 arm_VCVT_LT_F64_FXS32 5021 arm_VCVT_GT_F64_FXS32 5022 arm_VCVT_LE_F64_FXS32 5023 arm_VCVT_F64_FXS32 5024 arm_VCVT_ZZ_F64_FXS32 5025 arm_VCVT_EQ_F64_FXU16 5026 arm_VCVT_NE_F64_FXU16 5027 arm_VCVT_CS_F64_FXU16 5028 arm_VCVT_CC_F64_FXU16 5029 arm_VCVT_MI_F64_FXU16 5030 arm_VCVT_PL_F64_FXU16 5031 arm_VCVT_VS_F64_FXU16 5032 arm_VCVT_VC_F64_FXU16 5033 arm_VCVT_HI_F64_FXU16 5034 arm_VCVT_LS_F64_FXU16 5035 arm_VCVT_GE_F64_FXU16 5036 arm_VCVT_LT_F64_FXU16 5037 arm_VCVT_GT_F64_FXU16 5038 arm_VCVT_LE_F64_FXU16 5039 arm_VCVT_F64_FXU16 5040 arm_VCVT_ZZ_F64_FXU16 5041 arm_VCVT_EQ_F64_FXU32 5042 arm_VCVT_NE_F64_FXU32 5043 arm_VCVT_CS_F64_FXU32 5044 arm_VCVT_CC_F64_FXU32 5045 arm_VCVT_MI_F64_FXU32 5046 arm_VCVT_PL_F64_FXU32 5047 arm_VCVT_VS_F64_FXU32 5048 arm_VCVT_VC_F64_FXU32 5049 arm_VCVT_HI_F64_FXU32 5050 arm_VCVT_LS_F64_FXU32 5051 arm_VCVT_GE_F64_FXU32 5052 arm_VCVT_LT_F64_FXU32 5053 arm_VCVT_GT_F64_FXU32 5054 arm_VCVT_LE_F64_FXU32 5055 arm_VCVT_F64_FXU32 5056 arm_VCVT_ZZ_F64_FXU32 5057 arm_VCVT_EQ_F32_U32 5058 arm_VCVT_NE_F32_U32 5059 arm_VCVT_CS_F32_U32 5060 arm_VCVT_CC_F32_U32 5061 arm_VCVT_MI_F32_U32 5062 arm_VCVT_PL_F32_U32 5063 arm_VCVT_VS_F32_U32 5064 arm_VCVT_VC_F32_U32 5065 arm_VCVT_HI_F32_U32 5066 arm_VCVT_LS_F32_U32 5067 arm_VCVT_GE_F32_U32 5068 arm_VCVT_LT_F32_U32 5069 arm_VCVT_GT_F32_U32 5070 arm_VCVT_LE_F32_U32 5071 arm_VCVT_F32_U32 5072 arm_VCVT_ZZ_F32_U32 5073 arm_VCVT_EQ_F32_S32 5074 arm_VCVT_NE_F32_S32 5075 arm_VCVT_CS_F32_S32 5076 arm_VCVT_CC_F32_S32 5077 arm_VCVT_MI_F32_S32 5078 arm_VCVT_PL_F32_S32 5079 arm_VCVT_VS_F32_S32 5080 arm_VCVT_VC_F32_S32 5081 arm_VCVT_HI_F32_S32 5082 arm_VCVT_LS_F32_S32 5083 arm_VCVT_GE_F32_S32 5084 arm_VCVT_LT_F32_S32 5085 arm_VCVT_GT_F32_S32 5086 arm_VCVT_LE_F32_S32 5087 arm_VCVT_F32_S32 5088 arm_VCVT_ZZ_F32_S32 5089 arm_VCVT_EQ_F64_U32 5090 arm_VCVT_NE_F64_U32 5091 arm_VCVT_CS_F64_U32 5092 arm_VCVT_CC_F64_U32 5093 arm_VCVT_MI_F64_U32 5094 arm_VCVT_PL_F64_U32 5095 arm_VCVT_VS_F64_U32 5096 arm_VCVT_VC_F64_U32 5097 arm_VCVT_HI_F64_U32 5098 arm_VCVT_LS_F64_U32 5099 arm_VCVT_GE_F64_U32 5100 arm_VCVT_LT_F64_U32 5101 arm_VCVT_GT_F64_U32 5102 arm_VCVT_LE_F64_U32 5103 arm_VCVT_F64_U32 5104 arm_VCVT_ZZ_F64_U32 5105 arm_VCVT_EQ_F64_S32 5106 arm_VCVT_NE_F64_S32 5107 arm_VCVT_CS_F64_S32 5108 arm_VCVT_CC_F64_S32 5109 arm_VCVT_MI_F64_S32 5110 arm_VCVT_PL_F64_S32 5111 arm_VCVT_VS_F64_S32 5112 arm_VCVT_VC_F64_S32 5113 arm_VCVT_HI_F64_S32 5114 arm_VCVT_LS_F64_S32 5115 arm_VCVT_GE_F64_S32 5116 arm_VCVT_LT_F64_S32 5117 arm_VCVT_GT_F64_S32 5118 arm_VCVT_LE_F64_S32 5119 arm_VCVT_F64_S32 5120 arm_VCVT_ZZ_F64_S32 5121 arm_VCVT_EQ_F64_F32 5122 arm_VCVT_NE_F64_F32 5123 arm_VCVT_CS_F64_F32 5124 arm_VCVT_CC_F64_F32 5125 arm_VCVT_MI_F64_F32 5126 arm_VCVT_PL_F64_F32 5127 arm_VCVT_VS_F64_F32 5128 arm_VCVT_VC_F64_F32 5129 arm_VCVT_HI_F64_F32 5130 arm_VCVT_LS_F64_F32 5131 arm_VCVT_GE_F64_F32 5132 arm_VCVT_LT_F64_F32 5133 arm_VCVT_GT_F64_F32 5134 arm_VCVT_LE_F64_F32 5135 arm_VCVT_F64_F32 5136 arm_VCVT_ZZ_F64_F32 5137 arm_VCVT_EQ_F32_F64 5138 arm_VCVT_NE_F32_F64 5139 arm_VCVT_CS_F32_F64 5140 arm_VCVT_CC_F32_F64 5141 arm_VCVT_MI_F32_F64 5142 arm_VCVT_PL_F32_F64 5143 arm_VCVT_VS_F32_F64 5144 arm_VCVT_VC_F32_F64 5145 arm_VCVT_HI_F32_F64 5146 arm_VCVT_LS_F32_F64 5147 arm_VCVT_GE_F32_F64 5148 arm_VCVT_LT_F32_F64 5149 arm_VCVT_GT_F32_F64 5150 arm_VCVT_LE_F32_F64 5151 arm_VCVT_F32_F64 5152 arm_VCVT_ZZ_F32_F64 5153 arm_VCVT_EQ_FXS16_F32 5154 arm_VCVT_NE_FXS16_F32 5155 arm_VCVT_CS_FXS16_F32 5156 arm_VCVT_CC_FXS16_F32 5157 arm_VCVT_MI_FXS16_F32 5158 arm_VCVT_PL_FXS16_F32 5159 arm_VCVT_VS_FXS16_F32 5160 arm_VCVT_VC_FXS16_F32 5161 arm_VCVT_HI_FXS16_F32 5162 arm_VCVT_LS_FXS16_F32 5163 arm_VCVT_GE_FXS16_F32 5164 arm_VCVT_LT_FXS16_F32 5165 arm_VCVT_GT_FXS16_F32 5166 arm_VCVT_LE_FXS16_F32 5167 arm_VCVT_FXS16_F32 5168 arm_VCVT_ZZ_FXS16_F32 5169 arm_VCVT_EQ_FXS16_F64 5170 arm_VCVT_NE_FXS16_F64 5171 arm_VCVT_CS_FXS16_F64 5172 arm_VCVT_CC_FXS16_F64 5173 arm_VCVT_MI_FXS16_F64 5174 arm_VCVT_PL_FXS16_F64 5175 arm_VCVT_VS_FXS16_F64 5176 arm_VCVT_VC_FXS16_F64 5177 arm_VCVT_HI_FXS16_F64 5178 arm_VCVT_LS_FXS16_F64 5179 arm_VCVT_GE_FXS16_F64 5180 arm_VCVT_LT_FXS16_F64 5181 arm_VCVT_GT_FXS16_F64 5182 arm_VCVT_LE_FXS16_F64 5183 arm_VCVT_FXS16_F64 5184 arm_VCVT_ZZ_FXS16_F64 5185 arm_VCVT_EQ_FXS32_F32 5186 arm_VCVT_NE_FXS32_F32 5187 arm_VCVT_CS_FXS32_F32 5188 arm_VCVT_CC_FXS32_F32 5189 arm_VCVT_MI_FXS32_F32 5190 arm_VCVT_PL_FXS32_F32 5191 arm_VCVT_VS_FXS32_F32 5192 arm_VCVT_VC_FXS32_F32 5193 arm_VCVT_HI_FXS32_F32 5194 arm_VCVT_LS_FXS32_F32 5195 arm_VCVT_GE_FXS32_F32 5196 arm_VCVT_LT_FXS32_F32 5197 arm_VCVT_GT_FXS32_F32 5198 arm_VCVT_LE_FXS32_F32 5199 arm_VCVT_FXS32_F32 5200 arm_VCVT_ZZ_FXS32_F32 5201 arm_VCVT_EQ_FXS32_F64 5202 arm_VCVT_NE_FXS32_F64 5203 arm_VCVT_CS_FXS32_F64 5204 arm_VCVT_CC_FXS32_F64 5205 arm_VCVT_MI_FXS32_F64 5206 arm_VCVT_PL_FXS32_F64 5207 arm_VCVT_VS_FXS32_F64 5208 arm_VCVT_VC_FXS32_F64 5209 arm_VCVT_HI_FXS32_F64 5210 arm_VCVT_LS_FXS32_F64 5211 arm_VCVT_GE_FXS32_F64 5212 arm_VCVT_LT_FXS32_F64 5213 arm_VCVT_GT_FXS32_F64 5214 arm_VCVT_LE_FXS32_F64 5215 arm_VCVT_FXS32_F64 5216 arm_VCVT_ZZ_FXS32_F64 5217 arm_VCVT_EQ_FXU16_F32 5218 arm_VCVT_NE_FXU16_F32 5219 arm_VCVT_CS_FXU16_F32 5220 arm_VCVT_CC_FXU16_F32 5221 arm_VCVT_MI_FXU16_F32 5222 arm_VCVT_PL_FXU16_F32 5223 arm_VCVT_VS_FXU16_F32 5224 arm_VCVT_VC_FXU16_F32 5225 arm_VCVT_HI_FXU16_F32 5226 arm_VCVT_LS_FXU16_F32 5227 arm_VCVT_GE_FXU16_F32 5228 arm_VCVT_LT_FXU16_F32 5229 arm_VCVT_GT_FXU16_F32 5230 arm_VCVT_LE_FXU16_F32 5231 arm_VCVT_FXU16_F32 5232 arm_VCVT_ZZ_FXU16_F32 5233 arm_VCVT_EQ_FXU16_F64 5234 arm_VCVT_NE_FXU16_F64 5235 arm_VCVT_CS_FXU16_F64 5236 arm_VCVT_CC_FXU16_F64 5237 arm_VCVT_MI_FXU16_F64 5238 arm_VCVT_PL_FXU16_F64 5239 arm_VCVT_VS_FXU16_F64 5240 arm_VCVT_VC_FXU16_F64 5241 arm_VCVT_HI_FXU16_F64 5242 arm_VCVT_LS_FXU16_F64 5243 arm_VCVT_GE_FXU16_F64 5244 arm_VCVT_LT_FXU16_F64 5245 arm_VCVT_GT_FXU16_F64 5246 arm_VCVT_LE_FXU16_F64 5247 arm_VCVT_FXU16_F64 5248 arm_VCVT_ZZ_FXU16_F64 5249 arm_VCVT_EQ_FXU32_F32 5250 arm_VCVT_NE_FXU32_F32 5251 arm_VCVT_CS_FXU32_F32 5252 arm_VCVT_CC_FXU32_F32 5253 arm_VCVT_MI_FXU32_F32 5254 arm_VCVT_PL_FXU32_F32 5255 arm_VCVT_VS_FXU32_F32 5256 arm_VCVT_VC_FXU32_F32 5257 arm_VCVT_HI_FXU32_F32 5258 arm_VCVT_LS_FXU32_F32 5259 arm_VCVT_GE_FXU32_F32 5260 arm_VCVT_LT_FXU32_F32 5261 arm_VCVT_GT_FXU32_F32 5262 arm_VCVT_LE_FXU32_F32 5263 arm_VCVT_FXU32_F32 5264 arm_VCVT_ZZ_FXU32_F32 5265 arm_VCVT_EQ_FXU32_F64 5266 arm_VCVT_NE_FXU32_F64 5267 arm_VCVT_CS_FXU32_F64 5268 arm_VCVT_CC_FXU32_F64 5269 arm_VCVT_MI_FXU32_F64 5270 arm_VCVT_PL_FXU32_F64 5271 arm_VCVT_VS_FXU32_F64 5272 arm_VCVT_VC_FXU32_F64 5273 arm_VCVT_HI_FXU32_F64 5274 arm_VCVT_LS_FXU32_F64 5275 arm_VCVT_GE_FXU32_F64 5276 arm_VCVT_LT_FXU32_F64 5277 arm_VCVT_GT_FXU32_F64 5278 arm_VCVT_LE_FXU32_F64 5279 arm_VCVT_FXU32_F64 5280 arm_VCVT_ZZ_FXU32_F64 5281 arm_VCVTB_EQ_F32_F16 5282 arm_VCVTB_NE_F32_F16 5283 arm_VCVTB_CS_F32_F16 5284 arm_VCVTB_CC_F32_F16 5285 arm_VCVTB_MI_F32_F16 5286 arm_VCVTB_PL_F32_F16 5287 arm_VCVTB_VS_F32_F16 5288 arm_VCVTB_VC_F32_F16 5289 arm_VCVTB_HI_F32_F16 5290 arm_VCVTB_LS_F32_F16 5291 arm_VCVTB_GE_F32_F16 5292 arm_VCVTB_LT_F32_F16 5293 arm_VCVTB_GT_F32_F16 5294 arm_VCVTB_LE_F32_F16 5295 arm_VCVTB_F32_F16 5296 arm_VCVTB_ZZ_F32_F16 5297 arm_VCVTB_EQ_F16_F32 5298 arm_VCVTB_NE_F16_F32 5299 arm_VCVTB_CS_F16_F32 5300 arm_VCVTB_CC_F16_F32 5301 arm_VCVTB_MI_F16_F32 5302 arm_VCVTB_PL_F16_F32 5303 arm_VCVTB_VS_F16_F32 5304 arm_VCVTB_VC_F16_F32 5305 arm_VCVTB_HI_F16_F32 5306 arm_VCVTB_LS_F16_F32 5307 arm_VCVTB_GE_F16_F32 5308 arm_VCVTB_LT_F16_F32 5309 arm_VCVTB_GT_F16_F32 5310 arm_VCVTB_LE_F16_F32 5311 arm_VCVTB_F16_F32 5312 arm_VCVTB_ZZ_F16_F32 5313 arm_VCVTT_EQ_F32_F16 5314 arm_VCVTT_NE_F32_F16 5315 arm_VCVTT_CS_F32_F16 5316 arm_VCVTT_CC_F32_F16 5317 arm_VCVTT_MI_F32_F16 5318 arm_VCVTT_PL_F32_F16 5319 arm_VCVTT_VS_F32_F16 5320 arm_VCVTT_VC_F32_F16 5321 arm_VCVTT_HI_F32_F16 5322 arm_VCVTT_LS_F32_F16 5323 arm_VCVTT_GE_F32_F16 5324 arm_VCVTT_LT_F32_F16 5325 arm_VCVTT_GT_F32_F16 5326 arm_VCVTT_LE_F32_F16 5327 arm_VCVTT_F32_F16 5328 arm_VCVTT_ZZ_F32_F16 5329 arm_VCVTT_EQ_F16_F32 5330 arm_VCVTT_NE_F16_F32 5331 arm_VCVTT_CS_F16_F32 5332 arm_VCVTT_CC_F16_F32 5333 arm_VCVTT_MI_F16_F32 5334 arm_VCVTT_PL_F16_F32 5335 arm_VCVTT_VS_F16_F32 5336 arm_VCVTT_VC_F16_F32 5337 arm_VCVTT_HI_F16_F32 5338 arm_VCVTT_LS_F16_F32 5339 arm_VCVTT_GE_F16_F32 5340 arm_VCVTT_LT_F16_F32 5341 arm_VCVTT_GT_F16_F32 5342 arm_VCVTT_LE_F16_F32 5343 arm_VCVTT_F16_F32 5344 arm_VCVTT_ZZ_F16_F32 5345 arm_VCVTR_EQ_U32_F32 5346 arm_VCVTR_NE_U32_F32 5347 arm_VCVTR_CS_U32_F32 5348 arm_VCVTR_CC_U32_F32 5349 arm_VCVTR_MI_U32_F32 5350 arm_VCVTR_PL_U32_F32 5351 arm_VCVTR_VS_U32_F32 5352 arm_VCVTR_VC_U32_F32 5353 arm_VCVTR_HI_U32_F32 5354 arm_VCVTR_LS_U32_F32 5355 arm_VCVTR_GE_U32_F32 5356 arm_VCVTR_LT_U32_F32 5357 arm_VCVTR_GT_U32_F32 5358 arm_VCVTR_LE_U32_F32 5359 arm_VCVTR_U32_F32 5360 arm_VCVTR_ZZ_U32_F32 5361 arm_VCVTR_EQ_U32_F64 5362 arm_VCVTR_NE_U32_F64 5363 arm_VCVTR_CS_U32_F64 5364 arm_VCVTR_CC_U32_F64 5365 arm_VCVTR_MI_U32_F64 5366 arm_VCVTR_PL_U32_F64 5367 arm_VCVTR_VS_U32_F64 5368 arm_VCVTR_VC_U32_F64 5369 arm_VCVTR_HI_U32_F64 5370 arm_VCVTR_LS_U32_F64 5371 arm_VCVTR_GE_U32_F64 5372 arm_VCVTR_LT_U32_F64 5373 arm_VCVTR_GT_U32_F64 5374 arm_VCVTR_LE_U32_F64 5375 arm_VCVTR_U32_F64 5376 arm_VCVTR_ZZ_U32_F64 5377 arm_VCVTR_EQ_S32_F32 5378 arm_VCVTR_NE_S32_F32 5379 arm_VCVTR_CS_S32_F32 5380 arm_VCVTR_CC_S32_F32 5381 arm_VCVTR_MI_S32_F32 5382 arm_VCVTR_PL_S32_F32 5383 arm_VCVTR_VS_S32_F32 5384 arm_VCVTR_VC_S32_F32 5385 arm_VCVTR_HI_S32_F32 5386 arm_VCVTR_LS_S32_F32 5387 arm_VCVTR_GE_S32_F32 5388 arm_VCVTR_LT_S32_F32 5389 arm_VCVTR_GT_S32_F32 5390 arm_VCVTR_LE_S32_F32 5391 arm_VCVTR_S32_F32 5392 arm_VCVTR_ZZ_S32_F32 5393 arm_VCVTR_EQ_S32_F64 5394 arm_VCVTR_NE_S32_F64 5395 arm_VCVTR_CS_S32_F64 5396 arm_VCVTR_CC_S32_F64 5397 arm_VCVTR_MI_S32_F64 5398 arm_VCVTR_PL_S32_F64 5399 arm_VCVTR_VS_S32_F64 5400 arm_VCVTR_VC_S32_F64 5401 arm_VCVTR_HI_S32_F64 5402 arm_VCVTR_LS_S32_F64 5403 arm_VCVTR_GE_S32_F64 5404 arm_VCVTR_LT_S32_F64 5405 arm_VCVTR_GT_S32_F64 5406 arm_VCVTR_LE_S32_F64 5407 arm_VCVTR_S32_F64 5408 arm_VCVTR_ZZ_S32_F64 5409 arm_VCVT_EQ_U32_F32 5410 arm_VCVT_NE_U32_F32 5411 arm_VCVT_CS_U32_F32 5412 arm_VCVT_CC_U32_F32 5413 arm_VCVT_MI_U32_F32 5414 arm_VCVT_PL_U32_F32 5415 arm_VCVT_VS_U32_F32 5416 arm_VCVT_VC_U32_F32 5417 arm_VCVT_HI_U32_F32 5418 arm_VCVT_LS_U32_F32 5419 arm_VCVT_GE_U32_F32 5420 arm_VCVT_LT_U32_F32 5421 arm_VCVT_GT_U32_F32 5422 arm_VCVT_LE_U32_F32 5423 arm_VCVT_U32_F32 5424 arm_VCVT_ZZ_U32_F32 5425 arm_VCVT_EQ_U32_F64 5426 arm_VCVT_NE_U32_F64 5427 arm_VCVT_CS_U32_F64 5428 arm_VCVT_CC_U32_F64 5429 arm_VCVT_MI_U32_F64 5430 arm_VCVT_PL_U32_F64 5431 arm_VCVT_VS_U32_F64 5432 arm_VCVT_VC_U32_F64 5433 arm_VCVT_HI_U32_F64 5434 arm_VCVT_LS_U32_F64 5435 arm_VCVT_GE_U32_F64 5436 arm_VCVT_LT_U32_F64 5437 arm_VCVT_GT_U32_F64 5438 arm_VCVT_LE_U32_F64 5439 arm_VCVT_U32_F64 5440 arm_VCVT_ZZ_U32_F64 5441 arm_VCVT_EQ_S32_F32 5442 arm_VCVT_NE_S32_F32 5443 arm_VCVT_CS_S32_F32 5444 arm_VCVT_CC_S32_F32 5445 arm_VCVT_MI_S32_F32 5446 arm_VCVT_PL_S32_F32 5447 arm_VCVT_VS_S32_F32 5448 arm_VCVT_VC_S32_F32 5449 arm_VCVT_HI_S32_F32 5450 arm_VCVT_LS_S32_F32 5451 arm_VCVT_GE_S32_F32 5452 arm_VCVT_LT_S32_F32 5453 arm_VCVT_GT_S32_F32 5454 arm_VCVT_LE_S32_F32 5455 arm_VCVT_S32_F32 5456 arm_VCVT_ZZ_S32_F32 5457 arm_VCVT_EQ_S32_F64 5458 arm_VCVT_NE_S32_F64 5459 arm_VCVT_CS_S32_F64 5460 arm_VCVT_CC_S32_F64 5461 arm_VCVT_MI_S32_F64 5462 arm_VCVT_PL_S32_F64 5463 arm_VCVT_VS_S32_F64 5464 arm_VCVT_VC_S32_F64 5465 arm_VCVT_HI_S32_F64 5466 arm_VCVT_LS_S32_F64 5467 arm_VCVT_GE_S32_F64 5468 arm_VCVT_LT_S32_F64 5469 arm_VCVT_GT_S32_F64 5470 arm_VCVT_LE_S32_F64 5471 arm_VCVT_S32_F64 5472 arm_VCVT_ZZ_S32_F64 5473 arm_VDIV_EQ_F32 5474 arm_VDIV_NE_F32 5475 arm_VDIV_CS_F32 5476 arm_VDIV_CC_F32 5477 arm_VDIV_MI_F32 5478 arm_VDIV_PL_F32 5479 arm_VDIV_VS_F32 5480 arm_VDIV_VC_F32 5481 arm_VDIV_HI_F32 5482 arm_VDIV_LS_F32 5483 arm_VDIV_GE_F32 5484 arm_VDIV_LT_F32 5485 arm_VDIV_GT_F32 5486 arm_VDIV_LE_F32 5487 arm_VDIV_F32 5488 arm_VDIV_ZZ_F32 5489 arm_VDIV_EQ_F64 5490 arm_VDIV_NE_F64 5491 arm_VDIV_CS_F64 5492 arm_VDIV_CC_F64 5493 arm_VDIV_MI_F64 5494 arm_VDIV_PL_F64 5495 arm_VDIV_VS_F64 5496 arm_VDIV_VC_F64 5497 arm_VDIV_HI_F64 5498 arm_VDIV_LS_F64 5499 arm_VDIV_GE_F64 5500 arm_VDIV_LT_F64 5501 arm_VDIV_GT_F64 5502 arm_VDIV_LE_F64 5503 arm_VDIV_F64 5504 arm_VDIV_ZZ_F64 5505 arm_VLDR_EQ 5506 arm_VLDR_NE 5507 arm_VLDR_CS 5508 arm_VLDR_CC 5509 arm_VLDR_MI 5510 arm_VLDR_PL 5511 arm_VLDR_VS 5512 arm_VLDR_VC 5513 arm_VLDR_HI 5514 arm_VLDR_LS 5515 arm_VLDR_GE 5516 arm_VLDR_LT 5517 arm_VLDR_GT 5518 arm_VLDR_LE 5519 arm_VLDR 5520 arm_VLDR_ZZ 5521 arm_VMLA_EQ_F32 5522 arm_VMLA_NE_F32 5523 arm_VMLA_CS_F32 5524 arm_VMLA_CC_F32 5525 arm_VMLA_MI_F32 5526 arm_VMLA_PL_F32 5527 arm_VMLA_VS_F32 5528 arm_VMLA_VC_F32 5529 arm_VMLA_HI_F32 5530 arm_VMLA_LS_F32 5531 arm_VMLA_GE_F32 5532 arm_VMLA_LT_F32 5533 arm_VMLA_GT_F32 5534 arm_VMLA_LE_F32 5535 arm_VMLA_F32 5536 arm_VMLA_ZZ_F32 5537 arm_VMLA_EQ_F64 5538 arm_VMLA_NE_F64 5539 arm_VMLA_CS_F64 5540 arm_VMLA_CC_F64 5541 arm_VMLA_MI_F64 5542 arm_VMLA_PL_F64 5543 arm_VMLA_VS_F64 5544 arm_VMLA_VC_F64 5545 arm_VMLA_HI_F64 5546 arm_VMLA_LS_F64 5547 arm_VMLA_GE_F64 5548 arm_VMLA_LT_F64 5549 arm_VMLA_GT_F64 5550 arm_VMLA_LE_F64 5551 arm_VMLA_F64 5552 arm_VMLA_ZZ_F64 5553 arm_VMLS_EQ_F32 5554 arm_VMLS_NE_F32 5555 arm_VMLS_CS_F32 5556 arm_VMLS_CC_F32 5557 arm_VMLS_MI_F32 5558 arm_VMLS_PL_F32 5559 arm_VMLS_VS_F32 5560 arm_VMLS_VC_F32 5561 arm_VMLS_HI_F32 5562 arm_VMLS_LS_F32 5563 arm_VMLS_GE_F32 5564 arm_VMLS_LT_F32 5565 arm_VMLS_GT_F32 5566 arm_VMLS_LE_F32 5567 arm_VMLS_F32 5568 arm_VMLS_ZZ_F32 5569 arm_VMLS_EQ_F64 5570 arm_VMLS_NE_F64 5571 arm_VMLS_CS_F64 5572 arm_VMLS_CC_F64 5573 arm_VMLS_MI_F64 5574 arm_VMLS_PL_F64 5575 arm_VMLS_VS_F64 5576 arm_VMLS_VC_F64 5577 arm_VMLS_HI_F64 5578 arm_VMLS_LS_F64 5579 arm_VMLS_GE_F64 5580 arm_VMLS_LT_F64 5581 arm_VMLS_GT_F64 5582 arm_VMLS_LE_F64 5583 arm_VMLS_F64 5584 arm_VMLS_ZZ_F64 5585 arm_VMOV_EQ 5586 arm_VMOV_NE 5587 arm_VMOV_CS 5588 arm_VMOV_CC 5589 arm_VMOV_MI 5590 arm_VMOV_PL 5591 arm_VMOV_VS 5592 arm_VMOV_VC 5593 arm_VMOV_HI 5594 arm_VMOV_LS 5595 arm_VMOV_GE 5596 arm_VMOV_LT 5597 arm_VMOV_GT 5598 arm_VMOV_LE 5599 arm_VMOV 5600 arm_VMOV_ZZ 5601 arm_VMOV_EQ_32 5602 arm_VMOV_NE_32 5603 arm_VMOV_CS_32 5604 arm_VMOV_CC_32 5605 arm_VMOV_MI_32 5606 arm_VMOV_PL_32 5607 arm_VMOV_VS_32 5608 arm_VMOV_VC_32 5609 arm_VMOV_HI_32 5610 arm_VMOV_LS_32 5611 arm_VMOV_GE_32 5612 arm_VMOV_LT_32 5613 arm_VMOV_GT_32 5614 arm_VMOV_LE_32 5615 arm_VMOV_32 5616 arm_VMOV_ZZ_32 5617 arm_VMOV_EQ_F32 5618 arm_VMOV_NE_F32 5619 arm_VMOV_CS_F32 5620 arm_VMOV_CC_F32 5621 arm_VMOV_MI_F32 5622 arm_VMOV_PL_F32 5623 arm_VMOV_VS_F32 5624 arm_VMOV_VC_F32 5625 arm_VMOV_HI_F32 5626 arm_VMOV_LS_F32 5627 arm_VMOV_GE_F32 5628 arm_VMOV_LT_F32 5629 arm_VMOV_GT_F32 5630 arm_VMOV_LE_F32 5631 arm_VMOV_F32 5632 arm_VMOV_ZZ_F32 5633 arm_VMOV_EQ_F64 5634 arm_VMOV_NE_F64 5635 arm_VMOV_CS_F64 5636 arm_VMOV_CC_F64 5637 arm_VMOV_MI_F64 5638 arm_VMOV_PL_F64 5639 arm_VMOV_VS_F64 5640 arm_VMOV_VC_F64 5641 arm_VMOV_HI_F64 5642 arm_VMOV_LS_F64 5643 arm_VMOV_GE_F64 5644 arm_VMOV_LT_F64 5645 arm_VMOV_GT_F64 5646 arm_VMOV_LE_F64 5647 arm_VMOV_F64 5648 arm_VMOV_ZZ_F64 5649 arm_VMRS_EQ 5650 arm_VMRS_NE 5651 arm_VMRS_CS 5652 arm_VMRS_CC 5653 arm_VMRS_MI 5654 arm_VMRS_PL 5655 arm_VMRS_VS 5656 arm_VMRS_VC 5657 arm_VMRS_HI 5658 arm_VMRS_LS 5659 arm_VMRS_GE 5660 arm_VMRS_LT 5661 arm_VMRS_GT 5662 arm_VMRS_LE 5663 arm_VMRS 5664 arm_VMRS_ZZ 5665 arm_VMSR_EQ 5666 arm_VMSR_NE 5667 arm_VMSR_CS 5668 arm_VMSR_CC 5669 arm_VMSR_MI 5670 arm_VMSR_PL 5671 arm_VMSR_VS 5672 arm_VMSR_VC 5673 arm_VMSR_HI 5674 arm_VMSR_LS 5675 arm_VMSR_GE 5676 arm_VMSR_LT 5677 arm_VMSR_GT 5678 arm_VMSR_LE 5679 arm_VMSR 5680 arm_VMSR_ZZ 5681 arm_VMUL_EQ_F32 5682 arm_VMUL_NE_F32 5683 arm_VMUL_CS_F32 5684 arm_VMUL_CC_F32 5685 arm_VMUL_MI_F32 5686 arm_VMUL_PL_F32 5687 arm_VMUL_VS_F32 5688 arm_VMUL_VC_F32 5689 arm_VMUL_HI_F32 5690 arm_VMUL_LS_F32 5691 arm_VMUL_GE_F32 5692 arm_VMUL_LT_F32 5693 arm_VMUL_GT_F32 5694 arm_VMUL_LE_F32 5695 arm_VMUL_F32 5696 arm_VMUL_ZZ_F32 5697 arm_VMUL_EQ_F64 5698 arm_VMUL_NE_F64 5699 arm_VMUL_CS_F64 5700 arm_VMUL_CC_F64 5701 arm_VMUL_MI_F64 5702 arm_VMUL_PL_F64 5703 arm_VMUL_VS_F64 5704 arm_VMUL_VC_F64 5705 arm_VMUL_HI_F64 5706 arm_VMUL_LS_F64 5707 arm_VMUL_GE_F64 5708 arm_VMUL_LT_F64 5709 arm_VMUL_GT_F64 5710 arm_VMUL_LE_F64 5711 arm_VMUL_F64 5712 arm_VMUL_ZZ_F64 5713 arm_VNEG_EQ_F32 5714 arm_VNEG_NE_F32 5715 arm_VNEG_CS_F32 5716 arm_VNEG_CC_F32 5717 arm_VNEG_MI_F32 5718 arm_VNEG_PL_F32 5719 arm_VNEG_VS_F32 5720 arm_VNEG_VC_F32 5721 arm_VNEG_HI_F32 5722 arm_VNEG_LS_F32 5723 arm_VNEG_GE_F32 5724 arm_VNEG_LT_F32 5725 arm_VNEG_GT_F32 5726 arm_VNEG_LE_F32 5727 arm_VNEG_F32 5728 arm_VNEG_ZZ_F32 5729 arm_VNEG_EQ_F64 5730 arm_VNEG_NE_F64 5731 arm_VNEG_CS_F64 5732 arm_VNEG_CC_F64 5733 arm_VNEG_MI_F64 5734 arm_VNEG_PL_F64 5735 arm_VNEG_VS_F64 5736 arm_VNEG_VC_F64 5737 arm_VNEG_HI_F64 5738 arm_VNEG_LS_F64 5739 arm_VNEG_GE_F64 5740 arm_VNEG_LT_F64 5741 arm_VNEG_GT_F64 5742 arm_VNEG_LE_F64 5743 arm_VNEG_F64 5744 arm_VNEG_ZZ_F64 5745 arm_VNMLS_EQ_F32 5746 arm_VNMLS_NE_F32 5747 arm_VNMLS_CS_F32 5748 arm_VNMLS_CC_F32 5749 arm_VNMLS_MI_F32 5750 arm_VNMLS_PL_F32 5751 arm_VNMLS_VS_F32 5752 arm_VNMLS_VC_F32 5753 arm_VNMLS_HI_F32 5754 arm_VNMLS_LS_F32 5755 arm_VNMLS_GE_F32 5756 arm_VNMLS_LT_F32 5757 arm_VNMLS_GT_F32 5758 arm_VNMLS_LE_F32 5759 arm_VNMLS_F32 5760 arm_VNMLS_ZZ_F32 5761 arm_VNMLS_EQ_F64 5762 arm_VNMLS_NE_F64 5763 arm_VNMLS_CS_F64 5764 arm_VNMLS_CC_F64 5765 arm_VNMLS_MI_F64 5766 arm_VNMLS_PL_F64 5767 arm_VNMLS_VS_F64 5768 arm_VNMLS_VC_F64 5769 arm_VNMLS_HI_F64 5770 arm_VNMLS_LS_F64 5771 arm_VNMLS_GE_F64 5772 arm_VNMLS_LT_F64 5773 arm_VNMLS_GT_F64 5774 arm_VNMLS_LE_F64 5775 arm_VNMLS_F64 5776 arm_VNMLS_ZZ_F64 5777 arm_VNMLA_EQ_F32 5778 arm_VNMLA_NE_F32 5779 arm_VNMLA_CS_F32 5780 arm_VNMLA_CC_F32 5781 arm_VNMLA_MI_F32 5782 arm_VNMLA_PL_F32 5783 arm_VNMLA_VS_F32 5784 arm_VNMLA_VC_F32 5785 arm_VNMLA_HI_F32 5786 arm_VNMLA_LS_F32 5787 arm_VNMLA_GE_F32 5788 arm_VNMLA_LT_F32 5789 arm_VNMLA_GT_F32 5790 arm_VNMLA_LE_F32 5791 arm_VNMLA_F32 5792 arm_VNMLA_ZZ_F32 5793 arm_VNMLA_EQ_F64 5794 arm_VNMLA_NE_F64 5795 arm_VNMLA_CS_F64 5796 arm_VNMLA_CC_F64 5797 arm_VNMLA_MI_F64 5798 arm_VNMLA_PL_F64 5799 arm_VNMLA_VS_F64 5800 arm_VNMLA_VC_F64 5801 arm_VNMLA_HI_F64 5802 arm_VNMLA_LS_F64 5803 arm_VNMLA_GE_F64 5804 arm_VNMLA_LT_F64 5805 arm_VNMLA_GT_F64 5806 arm_VNMLA_LE_F64 5807 arm_VNMLA_F64 5808 arm_VNMLA_ZZ_F64 5809 arm_VNMUL_EQ_F32 5810 arm_VNMUL_NE_F32 5811 arm_VNMUL_CS_F32 5812 arm_VNMUL_CC_F32 5813 arm_VNMUL_MI_F32 5814 arm_VNMUL_PL_F32 5815 arm_VNMUL_VS_F32 5816 arm_VNMUL_VC_F32 5817 arm_VNMUL_HI_F32 5818 arm_VNMUL_LS_F32 5819 arm_VNMUL_GE_F32 5820 arm_VNMUL_LT_F32 5821 arm_VNMUL_GT_F32 5822 arm_VNMUL_LE_F32 5823 arm_VNMUL_F32 5824 arm_VNMUL_ZZ_F32 5825 arm_VNMUL_EQ_F64 5826 arm_VNMUL_NE_F64 5827 arm_VNMUL_CS_F64 5828 arm_VNMUL_CC_F64 5829 arm_VNMUL_MI_F64 5830 arm_VNMUL_PL_F64 5831 arm_VNMUL_VS_F64 5832 arm_VNMUL_VC_F64 5833 arm_VNMUL_HI_F64 5834 arm_VNMUL_LS_F64 5835 arm_VNMUL_GE_F64 5836 arm_VNMUL_LT_F64 5837 arm_VNMUL_GT_F64 5838 arm_VNMUL_LE_F64 5839 arm_VNMUL_F64 5840 arm_VNMUL_ZZ_F64 5841 arm_VSQRT_EQ_F32 5842 arm_VSQRT_NE_F32 5843 arm_VSQRT_CS_F32 5844 arm_VSQRT_CC_F32 5845 arm_VSQRT_MI_F32 5846 arm_VSQRT_PL_F32 5847 arm_VSQRT_VS_F32 5848 arm_VSQRT_VC_F32 5849 arm_VSQRT_HI_F32 5850 arm_VSQRT_LS_F32 5851 arm_VSQRT_GE_F32 5852 arm_VSQRT_LT_F32 5853 arm_VSQRT_GT_F32 5854 arm_VSQRT_LE_F32 5855 arm_VSQRT_F32 5856 arm_VSQRT_ZZ_F32 5857 arm_VSQRT_EQ_F64 5858 arm_VSQRT_NE_F64 5859 arm_VSQRT_CS_F64 5860 arm_VSQRT_CC_F64 5861 arm_VSQRT_MI_F64 5862 arm_VSQRT_PL_F64 5863 arm_VSQRT_VS_F64 5864 arm_VSQRT_VC_F64 5865 arm_VSQRT_HI_F64 5866 arm_VSQRT_LS_F64 5867 arm_VSQRT_GE_F64 5868 arm_VSQRT_LT_F64 5869 arm_VSQRT_GT_F64 5870 arm_VSQRT_LE_F64 5871 arm_VSQRT_F64 5872 arm_VSQRT_ZZ_F64 5873 arm_VSTR_EQ 5874 arm_VSTR_NE 5875 arm_VSTR_CS 5876 arm_VSTR_CC 5877 arm_VSTR_MI 5878 arm_VSTR_PL 5879 arm_VSTR_VS 5880 arm_VSTR_VC 5881 arm_VSTR_HI 5882 arm_VSTR_LS 5883 arm_VSTR_GE 5884 arm_VSTR_LT 5885 arm_VSTR_GT 5886 arm_VSTR_LE 5887 arm_VSTR 5888 arm_VSTR_ZZ 5889 arm_VSUB_EQ_F32 5890 arm_VSUB_NE_F32 5891 arm_VSUB_CS_F32 5892 arm_VSUB_CC_F32 5893 arm_VSUB_MI_F32 5894 arm_VSUB_PL_F32 5895 arm_VSUB_VS_F32 5896 arm_VSUB_VC_F32 5897 arm_VSUB_HI_F32 5898 arm_VSUB_LS_F32 5899 arm_VSUB_GE_F32 5900 arm_VSUB_LT_F32 5901 arm_VSUB_GT_F32 5902 arm_VSUB_LE_F32 5903 arm_VSUB_F32 5904 arm_VSUB_ZZ_F32 5905 arm_VSUB_EQ_F64 5906 arm_VSUB_NE_F64 5907 arm_VSUB_CS_F64 5908 arm_VSUB_CC_F64 5909 arm_VSUB_MI_F64 5910 arm_VSUB_PL_F64 5911 arm_VSUB_VS_F64 5912 arm_VSUB_VC_F64 5913 arm_VSUB_HI_F64 5914 arm_VSUB_LS_F64 5915 arm_VSUB_GE_F64 5916 arm_VSUB_LT_F64 5917 arm_VSUB_GT_F64 5918 arm_VSUB_LE_F64 5919 arm_VSUB_F64 5920 arm_VSUB_ZZ_F64 5921 arm_WFE_EQ 5922 arm_WFE_NE 5923 arm_WFE_CS 5924 arm_WFE_CC 5925 arm_WFE_MI 5926 arm_WFE_PL 5927 arm_WFE_VS 5928 arm_WFE_VC 5929 arm_WFE_HI 5930 arm_WFE_LS 5931 arm_WFE_GE 5932 arm_WFE_LT 5933 arm_WFE_GT 5934 arm_WFE_LE 5935 arm_WFE 5936 arm_WFE_ZZ 5937 arm_WFI_EQ 5938 arm_WFI_NE 5939 arm_WFI_CS 5940 arm_WFI_CC 5941 arm_WFI_MI 5942 arm_WFI_PL 5943 arm_WFI_VS 5944 arm_WFI_VC 5945 arm_WFI_HI 5946 arm_WFI_LS 5947 arm_WFI_GE 5948 arm_WFI_LT 5949 arm_WFI_GT 5950 arm_WFI_LE 5951 arm_WFI 5952 arm_WFI_ZZ 5953 arm_YIELD_EQ 5954 arm_YIELD_NE 5955 arm_YIELD_CS 5956 arm_YIELD_CC 5957 arm_YIELD_MI 5958 arm_YIELD_PL 5959 arm_YIELD_VS 5960 arm_YIELD_VC 5961 arm_YIELD_HI 5962 arm_YIELD_LS 5963 arm_YIELD_GE 5964 arm_YIELD_LT 5965 arm_YIELD_GT 5966 arm_YIELD_LE 5967 arm_YIELD 5968 arm_YIELD_ZZ 5969 ) 5970 5971 var arm_opstr = [...]string{ 5972 arm_ADC_EQ: "ADC.EQ", 5973 arm_ADC_NE: "ADC.NE", 5974 arm_ADC_CS: "ADC.CS", 5975 arm_ADC_CC: "ADC.CC", 5976 arm_ADC_MI: "ADC.MI", 5977 arm_ADC_PL: "ADC.PL", 5978 arm_ADC_VS: "ADC.VS", 5979 arm_ADC_VC: "ADC.VC", 5980 arm_ADC_HI: "ADC.HI", 5981 arm_ADC_LS: "ADC.LS", 5982 arm_ADC_GE: "ADC.GE", 5983 arm_ADC_LT: "ADC.LT", 5984 arm_ADC_GT: "ADC.GT", 5985 arm_ADC_LE: "ADC.LE", 5986 arm_ADC: "ADC", 5987 arm_ADC_ZZ: "ADC.ZZ", 5988 arm_ADC_S_EQ: "ADC.S.EQ", 5989 arm_ADC_S_NE: "ADC.S.NE", 5990 arm_ADC_S_CS: "ADC.S.CS", 5991 arm_ADC_S_CC: "ADC.S.CC", 5992 arm_ADC_S_MI: "ADC.S.MI", 5993 arm_ADC_S_PL: "ADC.S.PL", 5994 arm_ADC_S_VS: "ADC.S.VS", 5995 arm_ADC_S_VC: "ADC.S.VC", 5996 arm_ADC_S_HI: "ADC.S.HI", 5997 arm_ADC_S_LS: "ADC.S.LS", 5998 arm_ADC_S_GE: "ADC.S.GE", 5999 arm_ADC_S_LT: "ADC.S.LT", 6000 arm_ADC_S_GT: "ADC.S.GT", 6001 arm_ADC_S_LE: "ADC.S.LE", 6002 arm_ADC_S: "ADC.S", 6003 arm_ADC_S_ZZ: "ADC.S.ZZ", 6004 arm_ADD_EQ: "ADD.EQ", 6005 arm_ADD_NE: "ADD.NE", 6006 arm_ADD_CS: "ADD.CS", 6007 arm_ADD_CC: "ADD.CC", 6008 arm_ADD_MI: "ADD.MI", 6009 arm_ADD_PL: "ADD.PL", 6010 arm_ADD_VS: "ADD.VS", 6011 arm_ADD_VC: "ADD.VC", 6012 arm_ADD_HI: "ADD.HI", 6013 arm_ADD_LS: "ADD.LS", 6014 arm_ADD_GE: "ADD.GE", 6015 arm_ADD_LT: "ADD.LT", 6016 arm_ADD_GT: "ADD.GT", 6017 arm_ADD_LE: "ADD.LE", 6018 arm_ADD: "ADD", 6019 arm_ADD_ZZ: "ADD.ZZ", 6020 arm_ADD_S_EQ: "ADD.S.EQ", 6021 arm_ADD_S_NE: "ADD.S.NE", 6022 arm_ADD_S_CS: "ADD.S.CS", 6023 arm_ADD_S_CC: "ADD.S.CC", 6024 arm_ADD_S_MI: "ADD.S.MI", 6025 arm_ADD_S_PL: "ADD.S.PL", 6026 arm_ADD_S_VS: "ADD.S.VS", 6027 arm_ADD_S_VC: "ADD.S.VC", 6028 arm_ADD_S_HI: "ADD.S.HI", 6029 arm_ADD_S_LS: "ADD.S.LS", 6030 arm_ADD_S_GE: "ADD.S.GE", 6031 arm_ADD_S_LT: "ADD.S.LT", 6032 arm_ADD_S_GT: "ADD.S.GT", 6033 arm_ADD_S_LE: "ADD.S.LE", 6034 arm_ADD_S: "ADD.S", 6035 arm_ADD_S_ZZ: "ADD.S.ZZ", 6036 arm_AND_EQ: "AND.EQ", 6037 arm_AND_NE: "AND.NE", 6038 arm_AND_CS: "AND.CS", 6039 arm_AND_CC: "AND.CC", 6040 arm_AND_MI: "AND.MI", 6041 arm_AND_PL: "AND.PL", 6042 arm_AND_VS: "AND.VS", 6043 arm_AND_VC: "AND.VC", 6044 arm_AND_HI: "AND.HI", 6045 arm_AND_LS: "AND.LS", 6046 arm_AND_GE: "AND.GE", 6047 arm_AND_LT: "AND.LT", 6048 arm_AND_GT: "AND.GT", 6049 arm_AND_LE: "AND.LE", 6050 arm_AND: "AND", 6051 arm_AND_ZZ: "AND.ZZ", 6052 arm_AND_S_EQ: "AND.S.EQ", 6053 arm_AND_S_NE: "AND.S.NE", 6054 arm_AND_S_CS: "AND.S.CS", 6055 arm_AND_S_CC: "AND.S.CC", 6056 arm_AND_S_MI: "AND.S.MI", 6057 arm_AND_S_PL: "AND.S.PL", 6058 arm_AND_S_VS: "AND.S.VS", 6059 arm_AND_S_VC: "AND.S.VC", 6060 arm_AND_S_HI: "AND.S.HI", 6061 arm_AND_S_LS: "AND.S.LS", 6062 arm_AND_S_GE: "AND.S.GE", 6063 arm_AND_S_LT: "AND.S.LT", 6064 arm_AND_S_GT: "AND.S.GT", 6065 arm_AND_S_LE: "AND.S.LE", 6066 arm_AND_S: "AND.S", 6067 arm_AND_S_ZZ: "AND.S.ZZ", 6068 arm_ASR_EQ: "ASR.EQ", 6069 arm_ASR_NE: "ASR.NE", 6070 arm_ASR_CS: "ASR.CS", 6071 arm_ASR_CC: "ASR.CC", 6072 arm_ASR_MI: "ASR.MI", 6073 arm_ASR_PL: "ASR.PL", 6074 arm_ASR_VS: "ASR.VS", 6075 arm_ASR_VC: "ASR.VC", 6076 arm_ASR_HI: "ASR.HI", 6077 arm_ASR_LS: "ASR.LS", 6078 arm_ASR_GE: "ASR.GE", 6079 arm_ASR_LT: "ASR.LT", 6080 arm_ASR_GT: "ASR.GT", 6081 arm_ASR_LE: "ASR.LE", 6082 arm_ASR: "ASR", 6083 arm_ASR_ZZ: "ASR.ZZ", 6084 arm_ASR_S_EQ: "ASR.S.EQ", 6085 arm_ASR_S_NE: "ASR.S.NE", 6086 arm_ASR_S_CS: "ASR.S.CS", 6087 arm_ASR_S_CC: "ASR.S.CC", 6088 arm_ASR_S_MI: "ASR.S.MI", 6089 arm_ASR_S_PL: "ASR.S.PL", 6090 arm_ASR_S_VS: "ASR.S.VS", 6091 arm_ASR_S_VC: "ASR.S.VC", 6092 arm_ASR_S_HI: "ASR.S.HI", 6093 arm_ASR_S_LS: "ASR.S.LS", 6094 arm_ASR_S_GE: "ASR.S.GE", 6095 arm_ASR_S_LT: "ASR.S.LT", 6096 arm_ASR_S_GT: "ASR.S.GT", 6097 arm_ASR_S_LE: "ASR.S.LE", 6098 arm_ASR_S: "ASR.S", 6099 arm_ASR_S_ZZ: "ASR.S.ZZ", 6100 arm_B_EQ: "B.EQ", 6101 arm_B_NE: "B.NE", 6102 arm_B_CS: "B.CS", 6103 arm_B_CC: "B.CC", 6104 arm_B_MI: "B.MI", 6105 arm_B_PL: "B.PL", 6106 arm_B_VS: "B.VS", 6107 arm_B_VC: "B.VC", 6108 arm_B_HI: "B.HI", 6109 arm_B_LS: "B.LS", 6110 arm_B_GE: "B.GE", 6111 arm_B_LT: "B.LT", 6112 arm_B_GT: "B.GT", 6113 arm_B_LE: "B.LE", 6114 arm_B: "B", 6115 arm_B_ZZ: "B.ZZ", 6116 arm_BFC_EQ: "BFC.EQ", 6117 arm_BFC_NE: "BFC.NE", 6118 arm_BFC_CS: "BFC.CS", 6119 arm_BFC_CC: "BFC.CC", 6120 arm_BFC_MI: "BFC.MI", 6121 arm_BFC_PL: "BFC.PL", 6122 arm_BFC_VS: "BFC.VS", 6123 arm_BFC_VC: "BFC.VC", 6124 arm_BFC_HI: "BFC.HI", 6125 arm_BFC_LS: "BFC.LS", 6126 arm_BFC_GE: "BFC.GE", 6127 arm_BFC_LT: "BFC.LT", 6128 arm_BFC_GT: "BFC.GT", 6129 arm_BFC_LE: "BFC.LE", 6130 arm_BFC: "BFC", 6131 arm_BFC_ZZ: "BFC.ZZ", 6132 arm_BFI_EQ: "BFI.EQ", 6133 arm_BFI_NE: "BFI.NE", 6134 arm_BFI_CS: "BFI.CS", 6135 arm_BFI_CC: "BFI.CC", 6136 arm_BFI_MI: "BFI.MI", 6137 arm_BFI_PL: "BFI.PL", 6138 arm_BFI_VS: "BFI.VS", 6139 arm_BFI_VC: "BFI.VC", 6140 arm_BFI_HI: "BFI.HI", 6141 arm_BFI_LS: "BFI.LS", 6142 arm_BFI_GE: "BFI.GE", 6143 arm_BFI_LT: "BFI.LT", 6144 arm_BFI_GT: "BFI.GT", 6145 arm_BFI_LE: "BFI.LE", 6146 arm_BFI: "BFI", 6147 arm_BFI_ZZ: "BFI.ZZ", 6148 arm_BIC_EQ: "BIC.EQ", 6149 arm_BIC_NE: "BIC.NE", 6150 arm_BIC_CS: "BIC.CS", 6151 arm_BIC_CC: "BIC.CC", 6152 arm_BIC_MI: "BIC.MI", 6153 arm_BIC_PL: "BIC.PL", 6154 arm_BIC_VS: "BIC.VS", 6155 arm_BIC_VC: "BIC.VC", 6156 arm_BIC_HI: "BIC.HI", 6157 arm_BIC_LS: "BIC.LS", 6158 arm_BIC_GE: "BIC.GE", 6159 arm_BIC_LT: "BIC.LT", 6160 arm_BIC_GT: "BIC.GT", 6161 arm_BIC_LE: "BIC.LE", 6162 arm_BIC: "BIC", 6163 arm_BIC_ZZ: "BIC.ZZ", 6164 arm_BIC_S_EQ: "BIC.S.EQ", 6165 arm_BIC_S_NE: "BIC.S.NE", 6166 arm_BIC_S_CS: "BIC.S.CS", 6167 arm_BIC_S_CC: "BIC.S.CC", 6168 arm_BIC_S_MI: "BIC.S.MI", 6169 arm_BIC_S_PL: "BIC.S.PL", 6170 arm_BIC_S_VS: "BIC.S.VS", 6171 arm_BIC_S_VC: "BIC.S.VC", 6172 arm_BIC_S_HI: "BIC.S.HI", 6173 arm_BIC_S_LS: "BIC.S.LS", 6174 arm_BIC_S_GE: "BIC.S.GE", 6175 arm_BIC_S_LT: "BIC.S.LT", 6176 arm_BIC_S_GT: "BIC.S.GT", 6177 arm_BIC_S_LE: "BIC.S.LE", 6178 arm_BIC_S: "BIC.S", 6179 arm_BIC_S_ZZ: "BIC.S.ZZ", 6180 arm_BKPT_EQ: "BKPT.EQ", 6181 arm_BKPT_NE: "BKPT.NE", 6182 arm_BKPT_CS: "BKPT.CS", 6183 arm_BKPT_CC: "BKPT.CC", 6184 arm_BKPT_MI: "BKPT.MI", 6185 arm_BKPT_PL: "BKPT.PL", 6186 arm_BKPT_VS: "BKPT.VS", 6187 arm_BKPT_VC: "BKPT.VC", 6188 arm_BKPT_HI: "BKPT.HI", 6189 arm_BKPT_LS: "BKPT.LS", 6190 arm_BKPT_GE: "BKPT.GE", 6191 arm_BKPT_LT: "BKPT.LT", 6192 arm_BKPT_GT: "BKPT.GT", 6193 arm_BKPT_LE: "BKPT.LE", 6194 arm_BKPT: "BKPT", 6195 arm_BKPT_ZZ: "BKPT.ZZ", 6196 arm_BL_EQ: "BL.EQ", 6197 arm_BL_NE: "BL.NE", 6198 arm_BL_CS: "BL.CS", 6199 arm_BL_CC: "BL.CC", 6200 arm_BL_MI: "BL.MI", 6201 arm_BL_PL: "BL.PL", 6202 arm_BL_VS: "BL.VS", 6203 arm_BL_VC: "BL.VC", 6204 arm_BL_HI: "BL.HI", 6205 arm_BL_LS: "BL.LS", 6206 arm_BL_GE: "BL.GE", 6207 arm_BL_LT: "BL.LT", 6208 arm_BL_GT: "BL.GT", 6209 arm_BL_LE: "BL.LE", 6210 arm_BL: "BL", 6211 arm_BL_ZZ: "BL.ZZ", 6212 arm_BLX_EQ: "BLX.EQ", 6213 arm_BLX_NE: "BLX.NE", 6214 arm_BLX_CS: "BLX.CS", 6215 arm_BLX_CC: "BLX.CC", 6216 arm_BLX_MI: "BLX.MI", 6217 arm_BLX_PL: "BLX.PL", 6218 arm_BLX_VS: "BLX.VS", 6219 arm_BLX_VC: "BLX.VC", 6220 arm_BLX_HI: "BLX.HI", 6221 arm_BLX_LS: "BLX.LS", 6222 arm_BLX_GE: "BLX.GE", 6223 arm_BLX_LT: "BLX.LT", 6224 arm_BLX_GT: "BLX.GT", 6225 arm_BLX_LE: "BLX.LE", 6226 arm_BLX: "BLX", 6227 arm_BLX_ZZ: "BLX.ZZ", 6228 arm_BX_EQ: "BX.EQ", 6229 arm_BX_NE: "BX.NE", 6230 arm_BX_CS: "BX.CS", 6231 arm_BX_CC: "BX.CC", 6232 arm_BX_MI: "BX.MI", 6233 arm_BX_PL: "BX.PL", 6234 arm_BX_VS: "BX.VS", 6235 arm_BX_VC: "BX.VC", 6236 arm_BX_HI: "BX.HI", 6237 arm_BX_LS: "BX.LS", 6238 arm_BX_GE: "BX.GE", 6239 arm_BX_LT: "BX.LT", 6240 arm_BX_GT: "BX.GT", 6241 arm_BX_LE: "BX.LE", 6242 arm_BX: "BX", 6243 arm_BX_ZZ: "BX.ZZ", 6244 arm_BXJ_EQ: "BXJ.EQ", 6245 arm_BXJ_NE: "BXJ.NE", 6246 arm_BXJ_CS: "BXJ.CS", 6247 arm_BXJ_CC: "BXJ.CC", 6248 arm_BXJ_MI: "BXJ.MI", 6249 arm_BXJ_PL: "BXJ.PL", 6250 arm_BXJ_VS: "BXJ.VS", 6251 arm_BXJ_VC: "BXJ.VC", 6252 arm_BXJ_HI: "BXJ.HI", 6253 arm_BXJ_LS: "BXJ.LS", 6254 arm_BXJ_GE: "BXJ.GE", 6255 arm_BXJ_LT: "BXJ.LT", 6256 arm_BXJ_GT: "BXJ.GT", 6257 arm_BXJ_LE: "BXJ.LE", 6258 arm_BXJ: "BXJ", 6259 arm_BXJ_ZZ: "BXJ.ZZ", 6260 arm_CLREX: "CLREX", 6261 arm_CLZ_EQ: "CLZ.EQ", 6262 arm_CLZ_NE: "CLZ.NE", 6263 arm_CLZ_CS: "CLZ.CS", 6264 arm_CLZ_CC: "CLZ.CC", 6265 arm_CLZ_MI: "CLZ.MI", 6266 arm_CLZ_PL: "CLZ.PL", 6267 arm_CLZ_VS: "CLZ.VS", 6268 arm_CLZ_VC: "CLZ.VC", 6269 arm_CLZ_HI: "CLZ.HI", 6270 arm_CLZ_LS: "CLZ.LS", 6271 arm_CLZ_GE: "CLZ.GE", 6272 arm_CLZ_LT: "CLZ.LT", 6273 arm_CLZ_GT: "CLZ.GT", 6274 arm_CLZ_LE: "CLZ.LE", 6275 arm_CLZ: "CLZ", 6276 arm_CLZ_ZZ: "CLZ.ZZ", 6277 arm_CMN_EQ: "CMN.EQ", 6278 arm_CMN_NE: "CMN.NE", 6279 arm_CMN_CS: "CMN.CS", 6280 arm_CMN_CC: "CMN.CC", 6281 arm_CMN_MI: "CMN.MI", 6282 arm_CMN_PL: "CMN.PL", 6283 arm_CMN_VS: "CMN.VS", 6284 arm_CMN_VC: "CMN.VC", 6285 arm_CMN_HI: "CMN.HI", 6286 arm_CMN_LS: "CMN.LS", 6287 arm_CMN_GE: "CMN.GE", 6288 arm_CMN_LT: "CMN.LT", 6289 arm_CMN_GT: "CMN.GT", 6290 arm_CMN_LE: "CMN.LE", 6291 arm_CMN: "CMN", 6292 arm_CMN_ZZ: "CMN.ZZ", 6293 arm_CMP_EQ: "CMP.EQ", 6294 arm_CMP_NE: "CMP.NE", 6295 arm_CMP_CS: "CMP.CS", 6296 arm_CMP_CC: "CMP.CC", 6297 arm_CMP_MI: "CMP.MI", 6298 arm_CMP_PL: "CMP.PL", 6299 arm_CMP_VS: "CMP.VS", 6300 arm_CMP_VC: "CMP.VC", 6301 arm_CMP_HI: "CMP.HI", 6302 arm_CMP_LS: "CMP.LS", 6303 arm_CMP_GE: "CMP.GE", 6304 arm_CMP_LT: "CMP.LT", 6305 arm_CMP_GT: "CMP.GT", 6306 arm_CMP_LE: "CMP.LE", 6307 arm_CMP: "CMP", 6308 arm_CMP_ZZ: "CMP.ZZ", 6309 arm_DBG_EQ: "DBG.EQ", 6310 arm_DBG_NE: "DBG.NE", 6311 arm_DBG_CS: "DBG.CS", 6312 arm_DBG_CC: "DBG.CC", 6313 arm_DBG_MI: "DBG.MI", 6314 arm_DBG_PL: "DBG.PL", 6315 arm_DBG_VS: "DBG.VS", 6316 arm_DBG_VC: "DBG.VC", 6317 arm_DBG_HI: "DBG.HI", 6318 arm_DBG_LS: "DBG.LS", 6319 arm_DBG_GE: "DBG.GE", 6320 arm_DBG_LT: "DBG.LT", 6321 arm_DBG_GT: "DBG.GT", 6322 arm_DBG_LE: "DBG.LE", 6323 arm_DBG: "DBG", 6324 arm_DBG_ZZ: "DBG.ZZ", 6325 arm_DMB: "DMB", 6326 arm_DSB: "DSB", 6327 arm_EOR_EQ: "EOR.EQ", 6328 arm_EOR_NE: "EOR.NE", 6329 arm_EOR_CS: "EOR.CS", 6330 arm_EOR_CC: "EOR.CC", 6331 arm_EOR_MI: "EOR.MI", 6332 arm_EOR_PL: "EOR.PL", 6333 arm_EOR_VS: "EOR.VS", 6334 arm_EOR_VC: "EOR.VC", 6335 arm_EOR_HI: "EOR.HI", 6336 arm_EOR_LS: "EOR.LS", 6337 arm_EOR_GE: "EOR.GE", 6338 arm_EOR_LT: "EOR.LT", 6339 arm_EOR_GT: "EOR.GT", 6340 arm_EOR_LE: "EOR.LE", 6341 arm_EOR: "EOR", 6342 arm_EOR_ZZ: "EOR.ZZ", 6343 arm_EOR_S_EQ: "EOR.S.EQ", 6344 arm_EOR_S_NE: "EOR.S.NE", 6345 arm_EOR_S_CS: "EOR.S.CS", 6346 arm_EOR_S_CC: "EOR.S.CC", 6347 arm_EOR_S_MI: "EOR.S.MI", 6348 arm_EOR_S_PL: "EOR.S.PL", 6349 arm_EOR_S_VS: "EOR.S.VS", 6350 arm_EOR_S_VC: "EOR.S.VC", 6351 arm_EOR_S_HI: "EOR.S.HI", 6352 arm_EOR_S_LS: "EOR.S.LS", 6353 arm_EOR_S_GE: "EOR.S.GE", 6354 arm_EOR_S_LT: "EOR.S.LT", 6355 arm_EOR_S_GT: "EOR.S.GT", 6356 arm_EOR_S_LE: "EOR.S.LE", 6357 arm_EOR_S: "EOR.S", 6358 arm_EOR_S_ZZ: "EOR.S.ZZ", 6359 arm_ISB: "ISB", 6360 arm_LDM_EQ: "LDM.EQ", 6361 arm_LDM_NE: "LDM.NE", 6362 arm_LDM_CS: "LDM.CS", 6363 arm_LDM_CC: "LDM.CC", 6364 arm_LDM_MI: "LDM.MI", 6365 arm_LDM_PL: "LDM.PL", 6366 arm_LDM_VS: "LDM.VS", 6367 arm_LDM_VC: "LDM.VC", 6368 arm_LDM_HI: "LDM.HI", 6369 arm_LDM_LS: "LDM.LS", 6370 arm_LDM_GE: "LDM.GE", 6371 arm_LDM_LT: "LDM.LT", 6372 arm_LDM_GT: "LDM.GT", 6373 arm_LDM_LE: "LDM.LE", 6374 arm_LDM: "LDM", 6375 arm_LDM_ZZ: "LDM.ZZ", 6376 arm_LDMDA_EQ: "LDMDA.EQ", 6377 arm_LDMDA_NE: "LDMDA.NE", 6378 arm_LDMDA_CS: "LDMDA.CS", 6379 arm_LDMDA_CC: "LDMDA.CC", 6380 arm_LDMDA_MI: "LDMDA.MI", 6381 arm_LDMDA_PL: "LDMDA.PL", 6382 arm_LDMDA_VS: "LDMDA.VS", 6383 arm_LDMDA_VC: "LDMDA.VC", 6384 arm_LDMDA_HI: "LDMDA.HI", 6385 arm_LDMDA_LS: "LDMDA.LS", 6386 arm_LDMDA_GE: "LDMDA.GE", 6387 arm_LDMDA_LT: "LDMDA.LT", 6388 arm_LDMDA_GT: "LDMDA.GT", 6389 arm_LDMDA_LE: "LDMDA.LE", 6390 arm_LDMDA: "LDMDA", 6391 arm_LDMDA_ZZ: "LDMDA.ZZ", 6392 arm_LDMDB_EQ: "LDMDB.EQ", 6393 arm_LDMDB_NE: "LDMDB.NE", 6394 arm_LDMDB_CS: "LDMDB.CS", 6395 arm_LDMDB_CC: "LDMDB.CC", 6396 arm_LDMDB_MI: "LDMDB.MI", 6397 arm_LDMDB_PL: "LDMDB.PL", 6398 arm_LDMDB_VS: "LDMDB.VS", 6399 arm_LDMDB_VC: "LDMDB.VC", 6400 arm_LDMDB_HI: "LDMDB.HI", 6401 arm_LDMDB_LS: "LDMDB.LS", 6402 arm_LDMDB_GE: "LDMDB.GE", 6403 arm_LDMDB_LT: "LDMDB.LT", 6404 arm_LDMDB_GT: "LDMDB.GT", 6405 arm_LDMDB_LE: "LDMDB.LE", 6406 arm_LDMDB: "LDMDB", 6407 arm_LDMDB_ZZ: "LDMDB.ZZ", 6408 arm_LDMIB_EQ: "LDMIB.EQ", 6409 arm_LDMIB_NE: "LDMIB.NE", 6410 arm_LDMIB_CS: "LDMIB.CS", 6411 arm_LDMIB_CC: "LDMIB.CC", 6412 arm_LDMIB_MI: "LDMIB.MI", 6413 arm_LDMIB_PL: "LDMIB.PL", 6414 arm_LDMIB_VS: "LDMIB.VS", 6415 arm_LDMIB_VC: "LDMIB.VC", 6416 arm_LDMIB_HI: "LDMIB.HI", 6417 arm_LDMIB_LS: "LDMIB.LS", 6418 arm_LDMIB_GE: "LDMIB.GE", 6419 arm_LDMIB_LT: "LDMIB.LT", 6420 arm_LDMIB_GT: "LDMIB.GT", 6421 arm_LDMIB_LE: "LDMIB.LE", 6422 arm_LDMIB: "LDMIB", 6423 arm_LDMIB_ZZ: "LDMIB.ZZ", 6424 arm_LDR_EQ: "LDR.EQ", 6425 arm_LDR_NE: "LDR.NE", 6426 arm_LDR_CS: "LDR.CS", 6427 arm_LDR_CC: "LDR.CC", 6428 arm_LDR_MI: "LDR.MI", 6429 arm_LDR_PL: "LDR.PL", 6430 arm_LDR_VS: "LDR.VS", 6431 arm_LDR_VC: "LDR.VC", 6432 arm_LDR_HI: "LDR.HI", 6433 arm_LDR_LS: "LDR.LS", 6434 arm_LDR_GE: "LDR.GE", 6435 arm_LDR_LT: "LDR.LT", 6436 arm_LDR_GT: "LDR.GT", 6437 arm_LDR_LE: "LDR.LE", 6438 arm_LDR: "LDR", 6439 arm_LDR_ZZ: "LDR.ZZ", 6440 arm_LDRB_EQ: "LDRB.EQ", 6441 arm_LDRB_NE: "LDRB.NE", 6442 arm_LDRB_CS: "LDRB.CS", 6443 arm_LDRB_CC: "LDRB.CC", 6444 arm_LDRB_MI: "LDRB.MI", 6445 arm_LDRB_PL: "LDRB.PL", 6446 arm_LDRB_VS: "LDRB.VS", 6447 arm_LDRB_VC: "LDRB.VC", 6448 arm_LDRB_HI: "LDRB.HI", 6449 arm_LDRB_LS: "LDRB.LS", 6450 arm_LDRB_GE: "LDRB.GE", 6451 arm_LDRB_LT: "LDRB.LT", 6452 arm_LDRB_GT: "LDRB.GT", 6453 arm_LDRB_LE: "LDRB.LE", 6454 arm_LDRB: "LDRB", 6455 arm_LDRB_ZZ: "LDRB.ZZ", 6456 arm_LDRBT_EQ: "LDRBT.EQ", 6457 arm_LDRBT_NE: "LDRBT.NE", 6458 arm_LDRBT_CS: "LDRBT.CS", 6459 arm_LDRBT_CC: "LDRBT.CC", 6460 arm_LDRBT_MI: "LDRBT.MI", 6461 arm_LDRBT_PL: "LDRBT.PL", 6462 arm_LDRBT_VS: "LDRBT.VS", 6463 arm_LDRBT_VC: "LDRBT.VC", 6464 arm_LDRBT_HI: "LDRBT.HI", 6465 arm_LDRBT_LS: "LDRBT.LS", 6466 arm_LDRBT_GE: "LDRBT.GE", 6467 arm_LDRBT_LT: "LDRBT.LT", 6468 arm_LDRBT_GT: "LDRBT.GT", 6469 arm_LDRBT_LE: "LDRBT.LE", 6470 arm_LDRBT: "LDRBT", 6471 arm_LDRBT_ZZ: "LDRBT.ZZ", 6472 arm_LDRD_EQ: "LDRD.EQ", 6473 arm_LDRD_NE: "LDRD.NE", 6474 arm_LDRD_CS: "LDRD.CS", 6475 arm_LDRD_CC: "LDRD.CC", 6476 arm_LDRD_MI: "LDRD.MI", 6477 arm_LDRD_PL: "LDRD.PL", 6478 arm_LDRD_VS: "LDRD.VS", 6479 arm_LDRD_VC: "LDRD.VC", 6480 arm_LDRD_HI: "LDRD.HI", 6481 arm_LDRD_LS: "LDRD.LS", 6482 arm_LDRD_GE: "LDRD.GE", 6483 arm_LDRD_LT: "LDRD.LT", 6484 arm_LDRD_GT: "LDRD.GT", 6485 arm_LDRD_LE: "LDRD.LE", 6486 arm_LDRD: "LDRD", 6487 arm_LDRD_ZZ: "LDRD.ZZ", 6488 arm_LDREX_EQ: "LDREX.EQ", 6489 arm_LDREX_NE: "LDREX.NE", 6490 arm_LDREX_CS: "LDREX.CS", 6491 arm_LDREX_CC: "LDREX.CC", 6492 arm_LDREX_MI: "LDREX.MI", 6493 arm_LDREX_PL: "LDREX.PL", 6494 arm_LDREX_VS: "LDREX.VS", 6495 arm_LDREX_VC: "LDREX.VC", 6496 arm_LDREX_HI: "LDREX.HI", 6497 arm_LDREX_LS: "LDREX.LS", 6498 arm_LDREX_GE: "LDREX.GE", 6499 arm_LDREX_LT: "LDREX.LT", 6500 arm_LDREX_GT: "LDREX.GT", 6501 arm_LDREX_LE: "LDREX.LE", 6502 arm_LDREX: "LDREX", 6503 arm_LDREX_ZZ: "LDREX.ZZ", 6504 arm_LDREXB_EQ: "LDREXB.EQ", 6505 arm_LDREXB_NE: "LDREXB.NE", 6506 arm_LDREXB_CS: "LDREXB.CS", 6507 arm_LDREXB_CC: "LDREXB.CC", 6508 arm_LDREXB_MI: "LDREXB.MI", 6509 arm_LDREXB_PL: "LDREXB.PL", 6510 arm_LDREXB_VS: "LDREXB.VS", 6511 arm_LDREXB_VC: "LDREXB.VC", 6512 arm_LDREXB_HI: "LDREXB.HI", 6513 arm_LDREXB_LS: "LDREXB.LS", 6514 arm_LDREXB_GE: "LDREXB.GE", 6515 arm_LDREXB_LT: "LDREXB.LT", 6516 arm_LDREXB_GT: "LDREXB.GT", 6517 arm_LDREXB_LE: "LDREXB.LE", 6518 arm_LDREXB: "LDREXB", 6519 arm_LDREXB_ZZ: "LDREXB.ZZ", 6520 arm_LDREXD_EQ: "LDREXD.EQ", 6521 arm_LDREXD_NE: "LDREXD.NE", 6522 arm_LDREXD_CS: "LDREXD.CS", 6523 arm_LDREXD_CC: "LDREXD.CC", 6524 arm_LDREXD_MI: "LDREXD.MI", 6525 arm_LDREXD_PL: "LDREXD.PL", 6526 arm_LDREXD_VS: "LDREXD.VS", 6527 arm_LDREXD_VC: "LDREXD.VC", 6528 arm_LDREXD_HI: "LDREXD.HI", 6529 arm_LDREXD_LS: "LDREXD.LS", 6530 arm_LDREXD_GE: "LDREXD.GE", 6531 arm_LDREXD_LT: "LDREXD.LT", 6532 arm_LDREXD_GT: "LDREXD.GT", 6533 arm_LDREXD_LE: "LDREXD.LE", 6534 arm_LDREXD: "LDREXD", 6535 arm_LDREXD_ZZ: "LDREXD.ZZ", 6536 arm_LDREXH_EQ: "LDREXH.EQ", 6537 arm_LDREXH_NE: "LDREXH.NE", 6538 arm_LDREXH_CS: "LDREXH.CS", 6539 arm_LDREXH_CC: "LDREXH.CC", 6540 arm_LDREXH_MI: "LDREXH.MI", 6541 arm_LDREXH_PL: "LDREXH.PL", 6542 arm_LDREXH_VS: "LDREXH.VS", 6543 arm_LDREXH_VC: "LDREXH.VC", 6544 arm_LDREXH_HI: "LDREXH.HI", 6545 arm_LDREXH_LS: "LDREXH.LS", 6546 arm_LDREXH_GE: "LDREXH.GE", 6547 arm_LDREXH_LT: "LDREXH.LT", 6548 arm_LDREXH_GT: "LDREXH.GT", 6549 arm_LDREXH_LE: "LDREXH.LE", 6550 arm_LDREXH: "LDREXH", 6551 arm_LDREXH_ZZ: "LDREXH.ZZ", 6552 arm_LDRH_EQ: "LDRH.EQ", 6553 arm_LDRH_NE: "LDRH.NE", 6554 arm_LDRH_CS: "LDRH.CS", 6555 arm_LDRH_CC: "LDRH.CC", 6556 arm_LDRH_MI: "LDRH.MI", 6557 arm_LDRH_PL: "LDRH.PL", 6558 arm_LDRH_VS: "LDRH.VS", 6559 arm_LDRH_VC: "LDRH.VC", 6560 arm_LDRH_HI: "LDRH.HI", 6561 arm_LDRH_LS: "LDRH.LS", 6562 arm_LDRH_GE: "LDRH.GE", 6563 arm_LDRH_LT: "LDRH.LT", 6564 arm_LDRH_GT: "LDRH.GT", 6565 arm_LDRH_LE: "LDRH.LE", 6566 arm_LDRH: "LDRH", 6567 arm_LDRH_ZZ: "LDRH.ZZ", 6568 arm_LDRHT_EQ: "LDRHT.EQ", 6569 arm_LDRHT_NE: "LDRHT.NE", 6570 arm_LDRHT_CS: "LDRHT.CS", 6571 arm_LDRHT_CC: "LDRHT.CC", 6572 arm_LDRHT_MI: "LDRHT.MI", 6573 arm_LDRHT_PL: "LDRHT.PL", 6574 arm_LDRHT_VS: "LDRHT.VS", 6575 arm_LDRHT_VC: "LDRHT.VC", 6576 arm_LDRHT_HI: "LDRHT.HI", 6577 arm_LDRHT_LS: "LDRHT.LS", 6578 arm_LDRHT_GE: "LDRHT.GE", 6579 arm_LDRHT_LT: "LDRHT.LT", 6580 arm_LDRHT_GT: "LDRHT.GT", 6581 arm_LDRHT_LE: "LDRHT.LE", 6582 arm_LDRHT: "LDRHT", 6583 arm_LDRHT_ZZ: "LDRHT.ZZ", 6584 arm_LDRSB_EQ: "LDRSB.EQ", 6585 arm_LDRSB_NE: "LDRSB.NE", 6586 arm_LDRSB_CS: "LDRSB.CS", 6587 arm_LDRSB_CC: "LDRSB.CC", 6588 arm_LDRSB_MI: "LDRSB.MI", 6589 arm_LDRSB_PL: "LDRSB.PL", 6590 arm_LDRSB_VS: "LDRSB.VS", 6591 arm_LDRSB_VC: "LDRSB.VC", 6592 arm_LDRSB_HI: "LDRSB.HI", 6593 arm_LDRSB_LS: "LDRSB.LS", 6594 arm_LDRSB_GE: "LDRSB.GE", 6595 arm_LDRSB_LT: "LDRSB.LT", 6596 arm_LDRSB_GT: "LDRSB.GT", 6597 arm_LDRSB_LE: "LDRSB.LE", 6598 arm_LDRSB: "LDRSB", 6599 arm_LDRSB_ZZ: "LDRSB.ZZ", 6600 arm_LDRSBT_EQ: "LDRSBT.EQ", 6601 arm_LDRSBT_NE: "LDRSBT.NE", 6602 arm_LDRSBT_CS: "LDRSBT.CS", 6603 arm_LDRSBT_CC: "LDRSBT.CC", 6604 arm_LDRSBT_MI: "LDRSBT.MI", 6605 arm_LDRSBT_PL: "LDRSBT.PL", 6606 arm_LDRSBT_VS: "LDRSBT.VS", 6607 arm_LDRSBT_VC: "LDRSBT.VC", 6608 arm_LDRSBT_HI: "LDRSBT.HI", 6609 arm_LDRSBT_LS: "LDRSBT.LS", 6610 arm_LDRSBT_GE: "LDRSBT.GE", 6611 arm_LDRSBT_LT: "LDRSBT.LT", 6612 arm_LDRSBT_GT: "LDRSBT.GT", 6613 arm_LDRSBT_LE: "LDRSBT.LE", 6614 arm_LDRSBT: "LDRSBT", 6615 arm_LDRSBT_ZZ: "LDRSBT.ZZ", 6616 arm_LDRSH_EQ: "LDRSH.EQ", 6617 arm_LDRSH_NE: "LDRSH.NE", 6618 arm_LDRSH_CS: "LDRSH.CS", 6619 arm_LDRSH_CC: "LDRSH.CC", 6620 arm_LDRSH_MI: "LDRSH.MI", 6621 arm_LDRSH_PL: "LDRSH.PL", 6622 arm_LDRSH_VS: "LDRSH.VS", 6623 arm_LDRSH_VC: "LDRSH.VC", 6624 arm_LDRSH_HI: "LDRSH.HI", 6625 arm_LDRSH_LS: "LDRSH.LS", 6626 arm_LDRSH_GE: "LDRSH.GE", 6627 arm_LDRSH_LT: "LDRSH.LT", 6628 arm_LDRSH_GT: "LDRSH.GT", 6629 arm_LDRSH_LE: "LDRSH.LE", 6630 arm_LDRSH: "LDRSH", 6631 arm_LDRSH_ZZ: "LDRSH.ZZ", 6632 arm_LDRSHT_EQ: "LDRSHT.EQ", 6633 arm_LDRSHT_NE: "LDRSHT.NE", 6634 arm_LDRSHT_CS: "LDRSHT.CS", 6635 arm_LDRSHT_CC: "LDRSHT.CC", 6636 arm_LDRSHT_MI: "LDRSHT.MI", 6637 arm_LDRSHT_PL: "LDRSHT.PL", 6638 arm_LDRSHT_VS: "LDRSHT.VS", 6639 arm_LDRSHT_VC: "LDRSHT.VC", 6640 arm_LDRSHT_HI: "LDRSHT.HI", 6641 arm_LDRSHT_LS: "LDRSHT.LS", 6642 arm_LDRSHT_GE: "LDRSHT.GE", 6643 arm_LDRSHT_LT: "LDRSHT.LT", 6644 arm_LDRSHT_GT: "LDRSHT.GT", 6645 arm_LDRSHT_LE: "LDRSHT.LE", 6646 arm_LDRSHT: "LDRSHT", 6647 arm_LDRSHT_ZZ: "LDRSHT.ZZ", 6648 arm_LDRT_EQ: "LDRT.EQ", 6649 arm_LDRT_NE: "LDRT.NE", 6650 arm_LDRT_CS: "LDRT.CS", 6651 arm_LDRT_CC: "LDRT.CC", 6652 arm_LDRT_MI: "LDRT.MI", 6653 arm_LDRT_PL: "LDRT.PL", 6654 arm_LDRT_VS: "LDRT.VS", 6655 arm_LDRT_VC: "LDRT.VC", 6656 arm_LDRT_HI: "LDRT.HI", 6657 arm_LDRT_LS: "LDRT.LS", 6658 arm_LDRT_GE: "LDRT.GE", 6659 arm_LDRT_LT: "LDRT.LT", 6660 arm_LDRT_GT: "LDRT.GT", 6661 arm_LDRT_LE: "LDRT.LE", 6662 arm_LDRT: "LDRT", 6663 arm_LDRT_ZZ: "LDRT.ZZ", 6664 arm_LSL_EQ: "LSL.EQ", 6665 arm_LSL_NE: "LSL.NE", 6666 arm_LSL_CS: "LSL.CS", 6667 arm_LSL_CC: "LSL.CC", 6668 arm_LSL_MI: "LSL.MI", 6669 arm_LSL_PL: "LSL.PL", 6670 arm_LSL_VS: "LSL.VS", 6671 arm_LSL_VC: "LSL.VC", 6672 arm_LSL_HI: "LSL.HI", 6673 arm_LSL_LS: "LSL.LS", 6674 arm_LSL_GE: "LSL.GE", 6675 arm_LSL_LT: "LSL.LT", 6676 arm_LSL_GT: "LSL.GT", 6677 arm_LSL_LE: "LSL.LE", 6678 arm_LSL: "LSL", 6679 arm_LSL_ZZ: "LSL.ZZ", 6680 arm_LSL_S_EQ: "LSL.S.EQ", 6681 arm_LSL_S_NE: "LSL.S.NE", 6682 arm_LSL_S_CS: "LSL.S.CS", 6683 arm_LSL_S_CC: "LSL.S.CC", 6684 arm_LSL_S_MI: "LSL.S.MI", 6685 arm_LSL_S_PL: "LSL.S.PL", 6686 arm_LSL_S_VS: "LSL.S.VS", 6687 arm_LSL_S_VC: "LSL.S.VC", 6688 arm_LSL_S_HI: "LSL.S.HI", 6689 arm_LSL_S_LS: "LSL.S.LS", 6690 arm_LSL_S_GE: "LSL.S.GE", 6691 arm_LSL_S_LT: "LSL.S.LT", 6692 arm_LSL_S_GT: "LSL.S.GT", 6693 arm_LSL_S_LE: "LSL.S.LE", 6694 arm_LSL_S: "LSL.S", 6695 arm_LSL_S_ZZ: "LSL.S.ZZ", 6696 arm_LSR_EQ: "LSR.EQ", 6697 arm_LSR_NE: "LSR.NE", 6698 arm_LSR_CS: "LSR.CS", 6699 arm_LSR_CC: "LSR.CC", 6700 arm_LSR_MI: "LSR.MI", 6701 arm_LSR_PL: "LSR.PL", 6702 arm_LSR_VS: "LSR.VS", 6703 arm_LSR_VC: "LSR.VC", 6704 arm_LSR_HI: "LSR.HI", 6705 arm_LSR_LS: "LSR.LS", 6706 arm_LSR_GE: "LSR.GE", 6707 arm_LSR_LT: "LSR.LT", 6708 arm_LSR_GT: "LSR.GT", 6709 arm_LSR_LE: "LSR.LE", 6710 arm_LSR: "LSR", 6711 arm_LSR_ZZ: "LSR.ZZ", 6712 arm_LSR_S_EQ: "LSR.S.EQ", 6713 arm_LSR_S_NE: "LSR.S.NE", 6714 arm_LSR_S_CS: "LSR.S.CS", 6715 arm_LSR_S_CC: "LSR.S.CC", 6716 arm_LSR_S_MI: "LSR.S.MI", 6717 arm_LSR_S_PL: "LSR.S.PL", 6718 arm_LSR_S_VS: "LSR.S.VS", 6719 arm_LSR_S_VC: "LSR.S.VC", 6720 arm_LSR_S_HI: "LSR.S.HI", 6721 arm_LSR_S_LS: "LSR.S.LS", 6722 arm_LSR_S_GE: "LSR.S.GE", 6723 arm_LSR_S_LT: "LSR.S.LT", 6724 arm_LSR_S_GT: "LSR.S.GT", 6725 arm_LSR_S_LE: "LSR.S.LE", 6726 arm_LSR_S: "LSR.S", 6727 arm_LSR_S_ZZ: "LSR.S.ZZ", 6728 arm_MLA_EQ: "MLA.EQ", 6729 arm_MLA_NE: "MLA.NE", 6730 arm_MLA_CS: "MLA.CS", 6731 arm_MLA_CC: "MLA.CC", 6732 arm_MLA_MI: "MLA.MI", 6733 arm_MLA_PL: "MLA.PL", 6734 arm_MLA_VS: "MLA.VS", 6735 arm_MLA_VC: "MLA.VC", 6736 arm_MLA_HI: "MLA.HI", 6737 arm_MLA_LS: "MLA.LS", 6738 arm_MLA_GE: "MLA.GE", 6739 arm_MLA_LT: "MLA.LT", 6740 arm_MLA_GT: "MLA.GT", 6741 arm_MLA_LE: "MLA.LE", 6742 arm_MLA: "MLA", 6743 arm_MLA_ZZ: "MLA.ZZ", 6744 arm_MLA_S_EQ: "MLA.S.EQ", 6745 arm_MLA_S_NE: "MLA.S.NE", 6746 arm_MLA_S_CS: "MLA.S.CS", 6747 arm_MLA_S_CC: "MLA.S.CC", 6748 arm_MLA_S_MI: "MLA.S.MI", 6749 arm_MLA_S_PL: "MLA.S.PL", 6750 arm_MLA_S_VS: "MLA.S.VS", 6751 arm_MLA_S_VC: "MLA.S.VC", 6752 arm_MLA_S_HI: "MLA.S.HI", 6753 arm_MLA_S_LS: "MLA.S.LS", 6754 arm_MLA_S_GE: "MLA.S.GE", 6755 arm_MLA_S_LT: "MLA.S.LT", 6756 arm_MLA_S_GT: "MLA.S.GT", 6757 arm_MLA_S_LE: "MLA.S.LE", 6758 arm_MLA_S: "MLA.S", 6759 arm_MLA_S_ZZ: "MLA.S.ZZ", 6760 arm_MLS_EQ: "MLS.EQ", 6761 arm_MLS_NE: "MLS.NE", 6762 arm_MLS_CS: "MLS.CS", 6763 arm_MLS_CC: "MLS.CC", 6764 arm_MLS_MI: "MLS.MI", 6765 arm_MLS_PL: "MLS.PL", 6766 arm_MLS_VS: "MLS.VS", 6767 arm_MLS_VC: "MLS.VC", 6768 arm_MLS_HI: "MLS.HI", 6769 arm_MLS_LS: "MLS.LS", 6770 arm_MLS_GE: "MLS.GE", 6771 arm_MLS_LT: "MLS.LT", 6772 arm_MLS_GT: "MLS.GT", 6773 arm_MLS_LE: "MLS.LE", 6774 arm_MLS: "MLS", 6775 arm_MLS_ZZ: "MLS.ZZ", 6776 arm_MOV_EQ: "MOV.EQ", 6777 arm_MOV_NE: "MOV.NE", 6778 arm_MOV_CS: "MOV.CS", 6779 arm_MOV_CC: "MOV.CC", 6780 arm_MOV_MI: "MOV.MI", 6781 arm_MOV_PL: "MOV.PL", 6782 arm_MOV_VS: "MOV.VS", 6783 arm_MOV_VC: "MOV.VC", 6784 arm_MOV_HI: "MOV.HI", 6785 arm_MOV_LS: "MOV.LS", 6786 arm_MOV_GE: "MOV.GE", 6787 arm_MOV_LT: "MOV.LT", 6788 arm_MOV_GT: "MOV.GT", 6789 arm_MOV_LE: "MOV.LE", 6790 arm_MOV: "MOV", 6791 arm_MOV_ZZ: "MOV.ZZ", 6792 arm_MOV_S_EQ: "MOV.S.EQ", 6793 arm_MOV_S_NE: "MOV.S.NE", 6794 arm_MOV_S_CS: "MOV.S.CS", 6795 arm_MOV_S_CC: "MOV.S.CC", 6796 arm_MOV_S_MI: "MOV.S.MI", 6797 arm_MOV_S_PL: "MOV.S.PL", 6798 arm_MOV_S_VS: "MOV.S.VS", 6799 arm_MOV_S_VC: "MOV.S.VC", 6800 arm_MOV_S_HI: "MOV.S.HI", 6801 arm_MOV_S_LS: "MOV.S.LS", 6802 arm_MOV_S_GE: "MOV.S.GE", 6803 arm_MOV_S_LT: "MOV.S.LT", 6804 arm_MOV_S_GT: "MOV.S.GT", 6805 arm_MOV_S_LE: "MOV.S.LE", 6806 arm_MOV_S: "MOV.S", 6807 arm_MOV_S_ZZ: "MOV.S.ZZ", 6808 arm_MOVT_EQ: "MOVT.EQ", 6809 arm_MOVT_NE: "MOVT.NE", 6810 arm_MOVT_CS: "MOVT.CS", 6811 arm_MOVT_CC: "MOVT.CC", 6812 arm_MOVT_MI: "MOVT.MI", 6813 arm_MOVT_PL: "MOVT.PL", 6814 arm_MOVT_VS: "MOVT.VS", 6815 arm_MOVT_VC: "MOVT.VC", 6816 arm_MOVT_HI: "MOVT.HI", 6817 arm_MOVT_LS: "MOVT.LS", 6818 arm_MOVT_GE: "MOVT.GE", 6819 arm_MOVT_LT: "MOVT.LT", 6820 arm_MOVT_GT: "MOVT.GT", 6821 arm_MOVT_LE: "MOVT.LE", 6822 arm_MOVT: "MOVT", 6823 arm_MOVT_ZZ: "MOVT.ZZ", 6824 arm_MOVW_EQ: "MOVW.EQ", 6825 arm_MOVW_NE: "MOVW.NE", 6826 arm_MOVW_CS: "MOVW.CS", 6827 arm_MOVW_CC: "MOVW.CC", 6828 arm_MOVW_MI: "MOVW.MI", 6829 arm_MOVW_PL: "MOVW.PL", 6830 arm_MOVW_VS: "MOVW.VS", 6831 arm_MOVW_VC: "MOVW.VC", 6832 arm_MOVW_HI: "MOVW.HI", 6833 arm_MOVW_LS: "MOVW.LS", 6834 arm_MOVW_GE: "MOVW.GE", 6835 arm_MOVW_LT: "MOVW.LT", 6836 arm_MOVW_GT: "MOVW.GT", 6837 arm_MOVW_LE: "MOVW.LE", 6838 arm_MOVW: "MOVW", 6839 arm_MOVW_ZZ: "MOVW.ZZ", 6840 arm_MRS_EQ: "MRS.EQ", 6841 arm_MRS_NE: "MRS.NE", 6842 arm_MRS_CS: "MRS.CS", 6843 arm_MRS_CC: "MRS.CC", 6844 arm_MRS_MI: "MRS.MI", 6845 arm_MRS_PL: "MRS.PL", 6846 arm_MRS_VS: "MRS.VS", 6847 arm_MRS_VC: "MRS.VC", 6848 arm_MRS_HI: "MRS.HI", 6849 arm_MRS_LS: "MRS.LS", 6850 arm_MRS_GE: "MRS.GE", 6851 arm_MRS_LT: "MRS.LT", 6852 arm_MRS_GT: "MRS.GT", 6853 arm_MRS_LE: "MRS.LE", 6854 arm_MRS: "MRS", 6855 arm_MRS_ZZ: "MRS.ZZ", 6856 arm_MUL_EQ: "MUL.EQ", 6857 arm_MUL_NE: "MUL.NE", 6858 arm_MUL_CS: "MUL.CS", 6859 arm_MUL_CC: "MUL.CC", 6860 arm_MUL_MI: "MUL.MI", 6861 arm_MUL_PL: "MUL.PL", 6862 arm_MUL_VS: "MUL.VS", 6863 arm_MUL_VC: "MUL.VC", 6864 arm_MUL_HI: "MUL.HI", 6865 arm_MUL_LS: "MUL.LS", 6866 arm_MUL_GE: "MUL.GE", 6867 arm_MUL_LT: "MUL.LT", 6868 arm_MUL_GT: "MUL.GT", 6869 arm_MUL_LE: "MUL.LE", 6870 arm_MUL: "MUL", 6871 arm_MUL_ZZ: "MUL.ZZ", 6872 arm_MUL_S_EQ: "MUL.S.EQ", 6873 arm_MUL_S_NE: "MUL.S.NE", 6874 arm_MUL_S_CS: "MUL.S.CS", 6875 arm_MUL_S_CC: "MUL.S.CC", 6876 arm_MUL_S_MI: "MUL.S.MI", 6877 arm_MUL_S_PL: "MUL.S.PL", 6878 arm_MUL_S_VS: "MUL.S.VS", 6879 arm_MUL_S_VC: "MUL.S.VC", 6880 arm_MUL_S_HI: "MUL.S.HI", 6881 arm_MUL_S_LS: "MUL.S.LS", 6882 arm_MUL_S_GE: "MUL.S.GE", 6883 arm_MUL_S_LT: "MUL.S.LT", 6884 arm_MUL_S_GT: "MUL.S.GT", 6885 arm_MUL_S_LE: "MUL.S.LE", 6886 arm_MUL_S: "MUL.S", 6887 arm_MUL_S_ZZ: "MUL.S.ZZ", 6888 arm_MVN_EQ: "MVN.EQ", 6889 arm_MVN_NE: "MVN.NE", 6890 arm_MVN_CS: "MVN.CS", 6891 arm_MVN_CC: "MVN.CC", 6892 arm_MVN_MI: "MVN.MI", 6893 arm_MVN_PL: "MVN.PL", 6894 arm_MVN_VS: "MVN.VS", 6895 arm_MVN_VC: "MVN.VC", 6896 arm_MVN_HI: "MVN.HI", 6897 arm_MVN_LS: "MVN.LS", 6898 arm_MVN_GE: "MVN.GE", 6899 arm_MVN_LT: "MVN.LT", 6900 arm_MVN_GT: "MVN.GT", 6901 arm_MVN_LE: "MVN.LE", 6902 arm_MVN: "MVN", 6903 arm_MVN_ZZ: "MVN.ZZ", 6904 arm_MVN_S_EQ: "MVN.S.EQ", 6905 arm_MVN_S_NE: "MVN.S.NE", 6906 arm_MVN_S_CS: "MVN.S.CS", 6907 arm_MVN_S_CC: "MVN.S.CC", 6908 arm_MVN_S_MI: "MVN.S.MI", 6909 arm_MVN_S_PL: "MVN.S.PL", 6910 arm_MVN_S_VS: "MVN.S.VS", 6911 arm_MVN_S_VC: "MVN.S.VC", 6912 arm_MVN_S_HI: "MVN.S.HI", 6913 arm_MVN_S_LS: "MVN.S.LS", 6914 arm_MVN_S_GE: "MVN.S.GE", 6915 arm_MVN_S_LT: "MVN.S.LT", 6916 arm_MVN_S_GT: "MVN.S.GT", 6917 arm_MVN_S_LE: "MVN.S.LE", 6918 arm_MVN_S: "MVN.S", 6919 arm_MVN_S_ZZ: "MVN.S.ZZ", 6920 arm_NOP_EQ: "NOP.EQ", 6921 arm_NOP_NE: "NOP.NE", 6922 arm_NOP_CS: "NOP.CS", 6923 arm_NOP_CC: "NOP.CC", 6924 arm_NOP_MI: "NOP.MI", 6925 arm_NOP_PL: "NOP.PL", 6926 arm_NOP_VS: "NOP.VS", 6927 arm_NOP_VC: "NOP.VC", 6928 arm_NOP_HI: "NOP.HI", 6929 arm_NOP_LS: "NOP.LS", 6930 arm_NOP_GE: "NOP.GE", 6931 arm_NOP_LT: "NOP.LT", 6932 arm_NOP_GT: "NOP.GT", 6933 arm_NOP_LE: "NOP.LE", 6934 arm_NOP: "NOP", 6935 arm_NOP_ZZ: "NOP.ZZ", 6936 arm_ORR_EQ: "ORR.EQ", 6937 arm_ORR_NE: "ORR.NE", 6938 arm_ORR_CS: "ORR.CS", 6939 arm_ORR_CC: "ORR.CC", 6940 arm_ORR_MI: "ORR.MI", 6941 arm_ORR_PL: "ORR.PL", 6942 arm_ORR_VS: "ORR.VS", 6943 arm_ORR_VC: "ORR.VC", 6944 arm_ORR_HI: "ORR.HI", 6945 arm_ORR_LS: "ORR.LS", 6946 arm_ORR_GE: "ORR.GE", 6947 arm_ORR_LT: "ORR.LT", 6948 arm_ORR_GT: "ORR.GT", 6949 arm_ORR_LE: "ORR.LE", 6950 arm_ORR: "ORR", 6951 arm_ORR_ZZ: "ORR.ZZ", 6952 arm_ORR_S_EQ: "ORR.S.EQ", 6953 arm_ORR_S_NE: "ORR.S.NE", 6954 arm_ORR_S_CS: "ORR.S.CS", 6955 arm_ORR_S_CC: "ORR.S.CC", 6956 arm_ORR_S_MI: "ORR.S.MI", 6957 arm_ORR_S_PL: "ORR.S.PL", 6958 arm_ORR_S_VS: "ORR.S.VS", 6959 arm_ORR_S_VC: "ORR.S.VC", 6960 arm_ORR_S_HI: "ORR.S.HI", 6961 arm_ORR_S_LS: "ORR.S.LS", 6962 arm_ORR_S_GE: "ORR.S.GE", 6963 arm_ORR_S_LT: "ORR.S.LT", 6964 arm_ORR_S_GT: "ORR.S.GT", 6965 arm_ORR_S_LE: "ORR.S.LE", 6966 arm_ORR_S: "ORR.S", 6967 arm_ORR_S_ZZ: "ORR.S.ZZ", 6968 arm_PKHBT_EQ: "PKHBT.EQ", 6969 arm_PKHBT_NE: "PKHBT.NE", 6970 arm_PKHBT_CS: "PKHBT.CS", 6971 arm_PKHBT_CC: "PKHBT.CC", 6972 arm_PKHBT_MI: "PKHBT.MI", 6973 arm_PKHBT_PL: "PKHBT.PL", 6974 arm_PKHBT_VS: "PKHBT.VS", 6975 arm_PKHBT_VC: "PKHBT.VC", 6976 arm_PKHBT_HI: "PKHBT.HI", 6977 arm_PKHBT_LS: "PKHBT.LS", 6978 arm_PKHBT_GE: "PKHBT.GE", 6979 arm_PKHBT_LT: "PKHBT.LT", 6980 arm_PKHBT_GT: "PKHBT.GT", 6981 arm_PKHBT_LE: "PKHBT.LE", 6982 arm_PKHBT: "PKHBT", 6983 arm_PKHBT_ZZ: "PKHBT.ZZ", 6984 arm_PKHTB_EQ: "PKHTB.EQ", 6985 arm_PKHTB_NE: "PKHTB.NE", 6986 arm_PKHTB_CS: "PKHTB.CS", 6987 arm_PKHTB_CC: "PKHTB.CC", 6988 arm_PKHTB_MI: "PKHTB.MI", 6989 arm_PKHTB_PL: "PKHTB.PL", 6990 arm_PKHTB_VS: "PKHTB.VS", 6991 arm_PKHTB_VC: "PKHTB.VC", 6992 arm_PKHTB_HI: "PKHTB.HI", 6993 arm_PKHTB_LS: "PKHTB.LS", 6994 arm_PKHTB_GE: "PKHTB.GE", 6995 arm_PKHTB_LT: "PKHTB.LT", 6996 arm_PKHTB_GT: "PKHTB.GT", 6997 arm_PKHTB_LE: "PKHTB.LE", 6998 arm_PKHTB: "PKHTB", 6999 arm_PKHTB_ZZ: "PKHTB.ZZ", 7000 arm_PLD_W: "PLD.W", 7001 arm_PLD: "PLD", 7002 arm_PLI: "PLI", 7003 arm_POP_EQ: "POP.EQ", 7004 arm_POP_NE: "POP.NE", 7005 arm_POP_CS: "POP.CS", 7006 arm_POP_CC: "POP.CC", 7007 arm_POP_MI: "POP.MI", 7008 arm_POP_PL: "POP.PL", 7009 arm_POP_VS: "POP.VS", 7010 arm_POP_VC: "POP.VC", 7011 arm_POP_HI: "POP.HI", 7012 arm_POP_LS: "POP.LS", 7013 arm_POP_GE: "POP.GE", 7014 arm_POP_LT: "POP.LT", 7015 arm_POP_GT: "POP.GT", 7016 arm_POP_LE: "POP.LE", 7017 arm_POP: "POP", 7018 arm_POP_ZZ: "POP.ZZ", 7019 arm_PUSH_EQ: "PUSH.EQ", 7020 arm_PUSH_NE: "PUSH.NE", 7021 arm_PUSH_CS: "PUSH.CS", 7022 arm_PUSH_CC: "PUSH.CC", 7023 arm_PUSH_MI: "PUSH.MI", 7024 arm_PUSH_PL: "PUSH.PL", 7025 arm_PUSH_VS: "PUSH.VS", 7026 arm_PUSH_VC: "PUSH.VC", 7027 arm_PUSH_HI: "PUSH.HI", 7028 arm_PUSH_LS: "PUSH.LS", 7029 arm_PUSH_GE: "PUSH.GE", 7030 arm_PUSH_LT: "PUSH.LT", 7031 arm_PUSH_GT: "PUSH.GT", 7032 arm_PUSH_LE: "PUSH.LE", 7033 arm_PUSH: "PUSH", 7034 arm_PUSH_ZZ: "PUSH.ZZ", 7035 arm_QADD_EQ: "QADD.EQ", 7036 arm_QADD_NE: "QADD.NE", 7037 arm_QADD_CS: "QADD.CS", 7038 arm_QADD_CC: "QADD.CC", 7039 arm_QADD_MI: "QADD.MI", 7040 arm_QADD_PL: "QADD.PL", 7041 arm_QADD_VS: "QADD.VS", 7042 arm_QADD_VC: "QADD.VC", 7043 arm_QADD_HI: "QADD.HI", 7044 arm_QADD_LS: "QADD.LS", 7045 arm_QADD_GE: "QADD.GE", 7046 arm_QADD_LT: "QADD.LT", 7047 arm_QADD_GT: "QADD.GT", 7048 arm_QADD_LE: "QADD.LE", 7049 arm_QADD: "QADD", 7050 arm_QADD_ZZ: "QADD.ZZ", 7051 arm_QADD16_EQ: "QADD16.EQ", 7052 arm_QADD16_NE: "QADD16.NE", 7053 arm_QADD16_CS: "QADD16.CS", 7054 arm_QADD16_CC: "QADD16.CC", 7055 arm_QADD16_MI: "QADD16.MI", 7056 arm_QADD16_PL: "QADD16.PL", 7057 arm_QADD16_VS: "QADD16.VS", 7058 arm_QADD16_VC: "QADD16.VC", 7059 arm_QADD16_HI: "QADD16.HI", 7060 arm_QADD16_LS: "QADD16.LS", 7061 arm_QADD16_GE: "QADD16.GE", 7062 arm_QADD16_LT: "QADD16.LT", 7063 arm_QADD16_GT: "QADD16.GT", 7064 arm_QADD16_LE: "QADD16.LE", 7065 arm_QADD16: "QADD16", 7066 arm_QADD16_ZZ: "QADD16.ZZ", 7067 arm_QADD8_EQ: "QADD8.EQ", 7068 arm_QADD8_NE: "QADD8.NE", 7069 arm_QADD8_CS: "QADD8.CS", 7070 arm_QADD8_CC: "QADD8.CC", 7071 arm_QADD8_MI: "QADD8.MI", 7072 arm_QADD8_PL: "QADD8.PL", 7073 arm_QADD8_VS: "QADD8.VS", 7074 arm_QADD8_VC: "QADD8.VC", 7075 arm_QADD8_HI: "QADD8.HI", 7076 arm_QADD8_LS: "QADD8.LS", 7077 arm_QADD8_GE: "QADD8.GE", 7078 arm_QADD8_LT: "QADD8.LT", 7079 arm_QADD8_GT: "QADD8.GT", 7080 arm_QADD8_LE: "QADD8.LE", 7081 arm_QADD8: "QADD8", 7082 arm_QADD8_ZZ: "QADD8.ZZ", 7083 arm_QASX_EQ: "QASX.EQ", 7084 arm_QASX_NE: "QASX.NE", 7085 arm_QASX_CS: "QASX.CS", 7086 arm_QASX_CC: "QASX.CC", 7087 arm_QASX_MI: "QASX.MI", 7088 arm_QASX_PL: "QASX.PL", 7089 arm_QASX_VS: "QASX.VS", 7090 arm_QASX_VC: "QASX.VC", 7091 arm_QASX_HI: "QASX.HI", 7092 arm_QASX_LS: "QASX.LS", 7093 arm_QASX_GE: "QASX.GE", 7094 arm_QASX_LT: "QASX.LT", 7095 arm_QASX_GT: "QASX.GT", 7096 arm_QASX_LE: "QASX.LE", 7097 arm_QASX: "QASX", 7098 arm_QASX_ZZ: "QASX.ZZ", 7099 arm_QDADD_EQ: "QDADD.EQ", 7100 arm_QDADD_NE: "QDADD.NE", 7101 arm_QDADD_CS: "QDADD.CS", 7102 arm_QDADD_CC: "QDADD.CC", 7103 arm_QDADD_MI: "QDADD.MI", 7104 arm_QDADD_PL: "QDADD.PL", 7105 arm_QDADD_VS: "QDADD.VS", 7106 arm_QDADD_VC: "QDADD.VC", 7107 arm_QDADD_HI: "QDADD.HI", 7108 arm_QDADD_LS: "QDADD.LS", 7109 arm_QDADD_GE: "QDADD.GE", 7110 arm_QDADD_LT: "QDADD.LT", 7111 arm_QDADD_GT: "QDADD.GT", 7112 arm_QDADD_LE: "QDADD.LE", 7113 arm_QDADD: "QDADD", 7114 arm_QDADD_ZZ: "QDADD.ZZ", 7115 arm_QDSUB_EQ: "QDSUB.EQ", 7116 arm_QDSUB_NE: "QDSUB.NE", 7117 arm_QDSUB_CS: "QDSUB.CS", 7118 arm_QDSUB_CC: "QDSUB.CC", 7119 arm_QDSUB_MI: "QDSUB.MI", 7120 arm_QDSUB_PL: "QDSUB.PL", 7121 arm_QDSUB_VS: "QDSUB.VS", 7122 arm_QDSUB_VC: "QDSUB.VC", 7123 arm_QDSUB_HI: "QDSUB.HI", 7124 arm_QDSUB_LS: "QDSUB.LS", 7125 arm_QDSUB_GE: "QDSUB.GE", 7126 arm_QDSUB_LT: "QDSUB.LT", 7127 arm_QDSUB_GT: "QDSUB.GT", 7128 arm_QDSUB_LE: "QDSUB.LE", 7129 arm_QDSUB: "QDSUB", 7130 arm_QDSUB_ZZ: "QDSUB.ZZ", 7131 arm_QSAX_EQ: "QSAX.EQ", 7132 arm_QSAX_NE: "QSAX.NE", 7133 arm_QSAX_CS: "QSAX.CS", 7134 arm_QSAX_CC: "QSAX.CC", 7135 arm_QSAX_MI: "QSAX.MI", 7136 arm_QSAX_PL: "QSAX.PL", 7137 arm_QSAX_VS: "QSAX.VS", 7138 arm_QSAX_VC: "QSAX.VC", 7139 arm_QSAX_HI: "QSAX.HI", 7140 arm_QSAX_LS: "QSAX.LS", 7141 arm_QSAX_GE: "QSAX.GE", 7142 arm_QSAX_LT: "QSAX.LT", 7143 arm_QSAX_GT: "QSAX.GT", 7144 arm_QSAX_LE: "QSAX.LE", 7145 arm_QSAX: "QSAX", 7146 arm_QSAX_ZZ: "QSAX.ZZ", 7147 arm_QSUB_EQ: "QSUB.EQ", 7148 arm_QSUB_NE: "QSUB.NE", 7149 arm_QSUB_CS: "QSUB.CS", 7150 arm_QSUB_CC: "QSUB.CC", 7151 arm_QSUB_MI: "QSUB.MI", 7152 arm_QSUB_PL: "QSUB.PL", 7153 arm_QSUB_VS: "QSUB.VS", 7154 arm_QSUB_VC: "QSUB.VC", 7155 arm_QSUB_HI: "QSUB.HI", 7156 arm_QSUB_LS: "QSUB.LS", 7157 arm_QSUB_GE: "QSUB.GE", 7158 arm_QSUB_LT: "QSUB.LT", 7159 arm_QSUB_GT: "QSUB.GT", 7160 arm_QSUB_LE: "QSUB.LE", 7161 arm_QSUB: "QSUB", 7162 arm_QSUB_ZZ: "QSUB.ZZ", 7163 arm_QSUB16_EQ: "QSUB16.EQ", 7164 arm_QSUB16_NE: "QSUB16.NE", 7165 arm_QSUB16_CS: "QSUB16.CS", 7166 arm_QSUB16_CC: "QSUB16.CC", 7167 arm_QSUB16_MI: "QSUB16.MI", 7168 arm_QSUB16_PL: "QSUB16.PL", 7169 arm_QSUB16_VS: "QSUB16.VS", 7170 arm_QSUB16_VC: "QSUB16.VC", 7171 arm_QSUB16_HI: "QSUB16.HI", 7172 arm_QSUB16_LS: "QSUB16.LS", 7173 arm_QSUB16_GE: "QSUB16.GE", 7174 arm_QSUB16_LT: "QSUB16.LT", 7175 arm_QSUB16_GT: "QSUB16.GT", 7176 arm_QSUB16_LE: "QSUB16.LE", 7177 arm_QSUB16: "QSUB16", 7178 arm_QSUB16_ZZ: "QSUB16.ZZ", 7179 arm_QSUB8_EQ: "QSUB8.EQ", 7180 arm_QSUB8_NE: "QSUB8.NE", 7181 arm_QSUB8_CS: "QSUB8.CS", 7182 arm_QSUB8_CC: "QSUB8.CC", 7183 arm_QSUB8_MI: "QSUB8.MI", 7184 arm_QSUB8_PL: "QSUB8.PL", 7185 arm_QSUB8_VS: "QSUB8.VS", 7186 arm_QSUB8_VC: "QSUB8.VC", 7187 arm_QSUB8_HI: "QSUB8.HI", 7188 arm_QSUB8_LS: "QSUB8.LS", 7189 arm_QSUB8_GE: "QSUB8.GE", 7190 arm_QSUB8_LT: "QSUB8.LT", 7191 arm_QSUB8_GT: "QSUB8.GT", 7192 arm_QSUB8_LE: "QSUB8.LE", 7193 arm_QSUB8: "QSUB8", 7194 arm_QSUB8_ZZ: "QSUB8.ZZ", 7195 arm_RBIT_EQ: "RBIT.EQ", 7196 arm_RBIT_NE: "RBIT.NE", 7197 arm_RBIT_CS: "RBIT.CS", 7198 arm_RBIT_CC: "RBIT.CC", 7199 arm_RBIT_MI: "RBIT.MI", 7200 arm_RBIT_PL: "RBIT.PL", 7201 arm_RBIT_VS: "RBIT.VS", 7202 arm_RBIT_VC: "RBIT.VC", 7203 arm_RBIT_HI: "RBIT.HI", 7204 arm_RBIT_LS: "RBIT.LS", 7205 arm_RBIT_GE: "RBIT.GE", 7206 arm_RBIT_LT: "RBIT.LT", 7207 arm_RBIT_GT: "RBIT.GT", 7208 arm_RBIT_LE: "RBIT.LE", 7209 arm_RBIT: "RBIT", 7210 arm_RBIT_ZZ: "RBIT.ZZ", 7211 arm_REV_EQ: "REV.EQ", 7212 arm_REV_NE: "REV.NE", 7213 arm_REV_CS: "REV.CS", 7214 arm_REV_CC: "REV.CC", 7215 arm_REV_MI: "REV.MI", 7216 arm_REV_PL: "REV.PL", 7217 arm_REV_VS: "REV.VS", 7218 arm_REV_VC: "REV.VC", 7219 arm_REV_HI: "REV.HI", 7220 arm_REV_LS: "REV.LS", 7221 arm_REV_GE: "REV.GE", 7222 arm_REV_LT: "REV.LT", 7223 arm_REV_GT: "REV.GT", 7224 arm_REV_LE: "REV.LE", 7225 arm_REV: "REV", 7226 arm_REV_ZZ: "REV.ZZ", 7227 arm_REV16_EQ: "REV16.EQ", 7228 arm_REV16_NE: "REV16.NE", 7229 arm_REV16_CS: "REV16.CS", 7230 arm_REV16_CC: "REV16.CC", 7231 arm_REV16_MI: "REV16.MI", 7232 arm_REV16_PL: "REV16.PL", 7233 arm_REV16_VS: "REV16.VS", 7234 arm_REV16_VC: "REV16.VC", 7235 arm_REV16_HI: "REV16.HI", 7236 arm_REV16_LS: "REV16.LS", 7237 arm_REV16_GE: "REV16.GE", 7238 arm_REV16_LT: "REV16.LT", 7239 arm_REV16_GT: "REV16.GT", 7240 arm_REV16_LE: "REV16.LE", 7241 arm_REV16: "REV16", 7242 arm_REV16_ZZ: "REV16.ZZ", 7243 arm_REVSH_EQ: "REVSH.EQ", 7244 arm_REVSH_NE: "REVSH.NE", 7245 arm_REVSH_CS: "REVSH.CS", 7246 arm_REVSH_CC: "REVSH.CC", 7247 arm_REVSH_MI: "REVSH.MI", 7248 arm_REVSH_PL: "REVSH.PL", 7249 arm_REVSH_VS: "REVSH.VS", 7250 arm_REVSH_VC: "REVSH.VC", 7251 arm_REVSH_HI: "REVSH.HI", 7252 arm_REVSH_LS: "REVSH.LS", 7253 arm_REVSH_GE: "REVSH.GE", 7254 arm_REVSH_LT: "REVSH.LT", 7255 arm_REVSH_GT: "REVSH.GT", 7256 arm_REVSH_LE: "REVSH.LE", 7257 arm_REVSH: "REVSH", 7258 arm_REVSH_ZZ: "REVSH.ZZ", 7259 arm_ROR_EQ: "ROR.EQ", 7260 arm_ROR_NE: "ROR.NE", 7261 arm_ROR_CS: "ROR.CS", 7262 arm_ROR_CC: "ROR.CC", 7263 arm_ROR_MI: "ROR.MI", 7264 arm_ROR_PL: "ROR.PL", 7265 arm_ROR_VS: "ROR.VS", 7266 arm_ROR_VC: "ROR.VC", 7267 arm_ROR_HI: "ROR.HI", 7268 arm_ROR_LS: "ROR.LS", 7269 arm_ROR_GE: "ROR.GE", 7270 arm_ROR_LT: "ROR.LT", 7271 arm_ROR_GT: "ROR.GT", 7272 arm_ROR_LE: "ROR.LE", 7273 arm_ROR: "ROR", 7274 arm_ROR_ZZ: "ROR.ZZ", 7275 arm_ROR_S_EQ: "ROR.S.EQ", 7276 arm_ROR_S_NE: "ROR.S.NE", 7277 arm_ROR_S_CS: "ROR.S.CS", 7278 arm_ROR_S_CC: "ROR.S.CC", 7279 arm_ROR_S_MI: "ROR.S.MI", 7280 arm_ROR_S_PL: "ROR.S.PL", 7281 arm_ROR_S_VS: "ROR.S.VS", 7282 arm_ROR_S_VC: "ROR.S.VC", 7283 arm_ROR_S_HI: "ROR.S.HI", 7284 arm_ROR_S_LS: "ROR.S.LS", 7285 arm_ROR_S_GE: "ROR.S.GE", 7286 arm_ROR_S_LT: "ROR.S.LT", 7287 arm_ROR_S_GT: "ROR.S.GT", 7288 arm_ROR_S_LE: "ROR.S.LE", 7289 arm_ROR_S: "ROR.S", 7290 arm_ROR_S_ZZ: "ROR.S.ZZ", 7291 arm_RRX_EQ: "RRX.EQ", 7292 arm_RRX_NE: "RRX.NE", 7293 arm_RRX_CS: "RRX.CS", 7294 arm_RRX_CC: "RRX.CC", 7295 arm_RRX_MI: "RRX.MI", 7296 arm_RRX_PL: "RRX.PL", 7297 arm_RRX_VS: "RRX.VS", 7298 arm_RRX_VC: "RRX.VC", 7299 arm_RRX_HI: "RRX.HI", 7300 arm_RRX_LS: "RRX.LS", 7301 arm_RRX_GE: "RRX.GE", 7302 arm_RRX_LT: "RRX.LT", 7303 arm_RRX_GT: "RRX.GT", 7304 arm_RRX_LE: "RRX.LE", 7305 arm_RRX: "RRX", 7306 arm_RRX_ZZ: "RRX.ZZ", 7307 arm_RRX_S_EQ: "RRX.S.EQ", 7308 arm_RRX_S_NE: "RRX.S.NE", 7309 arm_RRX_S_CS: "RRX.S.CS", 7310 arm_RRX_S_CC: "RRX.S.CC", 7311 arm_RRX_S_MI: "RRX.S.MI", 7312 arm_RRX_S_PL: "RRX.S.PL", 7313 arm_RRX_S_VS: "RRX.S.VS", 7314 arm_RRX_S_VC: "RRX.S.VC", 7315 arm_RRX_S_HI: "RRX.S.HI", 7316 arm_RRX_S_LS: "RRX.S.LS", 7317 arm_RRX_S_GE: "RRX.S.GE", 7318 arm_RRX_S_LT: "RRX.S.LT", 7319 arm_RRX_S_GT: "RRX.S.GT", 7320 arm_RRX_S_LE: "RRX.S.LE", 7321 arm_RRX_S: "RRX.S", 7322 arm_RRX_S_ZZ: "RRX.S.ZZ", 7323 arm_RSB_EQ: "RSB.EQ", 7324 arm_RSB_NE: "RSB.NE", 7325 arm_RSB_CS: "RSB.CS", 7326 arm_RSB_CC: "RSB.CC", 7327 arm_RSB_MI: "RSB.MI", 7328 arm_RSB_PL: "RSB.PL", 7329 arm_RSB_VS: "RSB.VS", 7330 arm_RSB_VC: "RSB.VC", 7331 arm_RSB_HI: "RSB.HI", 7332 arm_RSB_LS: "RSB.LS", 7333 arm_RSB_GE: "RSB.GE", 7334 arm_RSB_LT: "RSB.LT", 7335 arm_RSB_GT: "RSB.GT", 7336 arm_RSB_LE: "RSB.LE", 7337 arm_RSB: "RSB", 7338 arm_RSB_ZZ: "RSB.ZZ", 7339 arm_RSB_S_EQ: "RSB.S.EQ", 7340 arm_RSB_S_NE: "RSB.S.NE", 7341 arm_RSB_S_CS: "RSB.S.CS", 7342 arm_RSB_S_CC: "RSB.S.CC", 7343 arm_RSB_S_MI: "RSB.S.MI", 7344 arm_RSB_S_PL: "RSB.S.PL", 7345 arm_RSB_S_VS: "RSB.S.VS", 7346 arm_RSB_S_VC: "RSB.S.VC", 7347 arm_RSB_S_HI: "RSB.S.HI", 7348 arm_RSB_S_LS: "RSB.S.LS", 7349 arm_RSB_S_GE: "RSB.S.GE", 7350 arm_RSB_S_LT: "RSB.S.LT", 7351 arm_RSB_S_GT: "RSB.S.GT", 7352 arm_RSB_S_LE: "RSB.S.LE", 7353 arm_RSB_S: "RSB.S", 7354 arm_RSB_S_ZZ: "RSB.S.ZZ", 7355 arm_RSC_EQ: "RSC.EQ", 7356 arm_RSC_NE: "RSC.NE", 7357 arm_RSC_CS: "RSC.CS", 7358 arm_RSC_CC: "RSC.CC", 7359 arm_RSC_MI: "RSC.MI", 7360 arm_RSC_PL: "RSC.PL", 7361 arm_RSC_VS: "RSC.VS", 7362 arm_RSC_VC: "RSC.VC", 7363 arm_RSC_HI: "RSC.HI", 7364 arm_RSC_LS: "RSC.LS", 7365 arm_RSC_GE: "RSC.GE", 7366 arm_RSC_LT: "RSC.LT", 7367 arm_RSC_GT: "RSC.GT", 7368 arm_RSC_LE: "RSC.LE", 7369 arm_RSC: "RSC", 7370 arm_RSC_ZZ: "RSC.ZZ", 7371 arm_RSC_S_EQ: "RSC.S.EQ", 7372 arm_RSC_S_NE: "RSC.S.NE", 7373 arm_RSC_S_CS: "RSC.S.CS", 7374 arm_RSC_S_CC: "RSC.S.CC", 7375 arm_RSC_S_MI: "RSC.S.MI", 7376 arm_RSC_S_PL: "RSC.S.PL", 7377 arm_RSC_S_VS: "RSC.S.VS", 7378 arm_RSC_S_VC: "RSC.S.VC", 7379 arm_RSC_S_HI: "RSC.S.HI", 7380 arm_RSC_S_LS: "RSC.S.LS", 7381 arm_RSC_S_GE: "RSC.S.GE", 7382 arm_RSC_S_LT: "RSC.S.LT", 7383 arm_RSC_S_GT: "RSC.S.GT", 7384 arm_RSC_S_LE: "RSC.S.LE", 7385 arm_RSC_S: "RSC.S", 7386 arm_RSC_S_ZZ: "RSC.S.ZZ", 7387 arm_SADD16_EQ: "SADD16.EQ", 7388 arm_SADD16_NE: "SADD16.NE", 7389 arm_SADD16_CS: "SADD16.CS", 7390 arm_SADD16_CC: "SADD16.CC", 7391 arm_SADD16_MI: "SADD16.MI", 7392 arm_SADD16_PL: "SADD16.PL", 7393 arm_SADD16_VS: "SADD16.VS", 7394 arm_SADD16_VC: "SADD16.VC", 7395 arm_SADD16_HI: "SADD16.HI", 7396 arm_SADD16_LS: "SADD16.LS", 7397 arm_SADD16_GE: "SADD16.GE", 7398 arm_SADD16_LT: "SADD16.LT", 7399 arm_SADD16_GT: "SADD16.GT", 7400 arm_SADD16_LE: "SADD16.LE", 7401 arm_SADD16: "SADD16", 7402 arm_SADD16_ZZ: "SADD16.ZZ", 7403 arm_SADD8_EQ: "SADD8.EQ", 7404 arm_SADD8_NE: "SADD8.NE", 7405 arm_SADD8_CS: "SADD8.CS", 7406 arm_SADD8_CC: "SADD8.CC", 7407 arm_SADD8_MI: "SADD8.MI", 7408 arm_SADD8_PL: "SADD8.PL", 7409 arm_SADD8_VS: "SADD8.VS", 7410 arm_SADD8_VC: "SADD8.VC", 7411 arm_SADD8_HI: "SADD8.HI", 7412 arm_SADD8_LS: "SADD8.LS", 7413 arm_SADD8_GE: "SADD8.GE", 7414 arm_SADD8_LT: "SADD8.LT", 7415 arm_SADD8_GT: "SADD8.GT", 7416 arm_SADD8_LE: "SADD8.LE", 7417 arm_SADD8: "SADD8", 7418 arm_SADD8_ZZ: "SADD8.ZZ", 7419 arm_SASX_EQ: "SASX.EQ", 7420 arm_SASX_NE: "SASX.NE", 7421 arm_SASX_CS: "SASX.CS", 7422 arm_SASX_CC: "SASX.CC", 7423 arm_SASX_MI: "SASX.MI", 7424 arm_SASX_PL: "SASX.PL", 7425 arm_SASX_VS: "SASX.VS", 7426 arm_SASX_VC: "SASX.VC", 7427 arm_SASX_HI: "SASX.HI", 7428 arm_SASX_LS: "SASX.LS", 7429 arm_SASX_GE: "SASX.GE", 7430 arm_SASX_LT: "SASX.LT", 7431 arm_SASX_GT: "SASX.GT", 7432 arm_SASX_LE: "SASX.LE", 7433 arm_SASX: "SASX", 7434 arm_SASX_ZZ: "SASX.ZZ", 7435 arm_SBC_EQ: "SBC.EQ", 7436 arm_SBC_NE: "SBC.NE", 7437 arm_SBC_CS: "SBC.CS", 7438 arm_SBC_CC: "SBC.CC", 7439 arm_SBC_MI: "SBC.MI", 7440 arm_SBC_PL: "SBC.PL", 7441 arm_SBC_VS: "SBC.VS", 7442 arm_SBC_VC: "SBC.VC", 7443 arm_SBC_HI: "SBC.HI", 7444 arm_SBC_LS: "SBC.LS", 7445 arm_SBC_GE: "SBC.GE", 7446 arm_SBC_LT: "SBC.LT", 7447 arm_SBC_GT: "SBC.GT", 7448 arm_SBC_LE: "SBC.LE", 7449 arm_SBC: "SBC", 7450 arm_SBC_ZZ: "SBC.ZZ", 7451 arm_SBC_S_EQ: "SBC.S.EQ", 7452 arm_SBC_S_NE: "SBC.S.NE", 7453 arm_SBC_S_CS: "SBC.S.CS", 7454 arm_SBC_S_CC: "SBC.S.CC", 7455 arm_SBC_S_MI: "SBC.S.MI", 7456 arm_SBC_S_PL: "SBC.S.PL", 7457 arm_SBC_S_VS: "SBC.S.VS", 7458 arm_SBC_S_VC: "SBC.S.VC", 7459 arm_SBC_S_HI: "SBC.S.HI", 7460 arm_SBC_S_LS: "SBC.S.LS", 7461 arm_SBC_S_GE: "SBC.S.GE", 7462 arm_SBC_S_LT: "SBC.S.LT", 7463 arm_SBC_S_GT: "SBC.S.GT", 7464 arm_SBC_S_LE: "SBC.S.LE", 7465 arm_SBC_S: "SBC.S", 7466 arm_SBC_S_ZZ: "SBC.S.ZZ", 7467 arm_SBFX_EQ: "SBFX.EQ", 7468 arm_SBFX_NE: "SBFX.NE", 7469 arm_SBFX_CS: "SBFX.CS", 7470 arm_SBFX_CC: "SBFX.CC", 7471 arm_SBFX_MI: "SBFX.MI", 7472 arm_SBFX_PL: "SBFX.PL", 7473 arm_SBFX_VS: "SBFX.VS", 7474 arm_SBFX_VC: "SBFX.VC", 7475 arm_SBFX_HI: "SBFX.HI", 7476 arm_SBFX_LS: "SBFX.LS", 7477 arm_SBFX_GE: "SBFX.GE", 7478 arm_SBFX_LT: "SBFX.LT", 7479 arm_SBFX_GT: "SBFX.GT", 7480 arm_SBFX_LE: "SBFX.LE", 7481 arm_SBFX: "SBFX", 7482 arm_SBFX_ZZ: "SBFX.ZZ", 7483 arm_SEL_EQ: "SEL.EQ", 7484 arm_SEL_NE: "SEL.NE", 7485 arm_SEL_CS: "SEL.CS", 7486 arm_SEL_CC: "SEL.CC", 7487 arm_SEL_MI: "SEL.MI", 7488 arm_SEL_PL: "SEL.PL", 7489 arm_SEL_VS: "SEL.VS", 7490 arm_SEL_VC: "SEL.VC", 7491 arm_SEL_HI: "SEL.HI", 7492 arm_SEL_LS: "SEL.LS", 7493 arm_SEL_GE: "SEL.GE", 7494 arm_SEL_LT: "SEL.LT", 7495 arm_SEL_GT: "SEL.GT", 7496 arm_SEL_LE: "SEL.LE", 7497 arm_SEL: "SEL", 7498 arm_SEL_ZZ: "SEL.ZZ", 7499 arm_SETEND: "SETEND", 7500 arm_SEV_EQ: "SEV.EQ", 7501 arm_SEV_NE: "SEV.NE", 7502 arm_SEV_CS: "SEV.CS", 7503 arm_SEV_CC: "SEV.CC", 7504 arm_SEV_MI: "SEV.MI", 7505 arm_SEV_PL: "SEV.PL", 7506 arm_SEV_VS: "SEV.VS", 7507 arm_SEV_VC: "SEV.VC", 7508 arm_SEV_HI: "SEV.HI", 7509 arm_SEV_LS: "SEV.LS", 7510 arm_SEV_GE: "SEV.GE", 7511 arm_SEV_LT: "SEV.LT", 7512 arm_SEV_GT: "SEV.GT", 7513 arm_SEV_LE: "SEV.LE", 7514 arm_SEV: "SEV", 7515 arm_SEV_ZZ: "SEV.ZZ", 7516 arm_SHADD16_EQ: "SHADD16.EQ", 7517 arm_SHADD16_NE: "SHADD16.NE", 7518 arm_SHADD16_CS: "SHADD16.CS", 7519 arm_SHADD16_CC: "SHADD16.CC", 7520 arm_SHADD16_MI: "SHADD16.MI", 7521 arm_SHADD16_PL: "SHADD16.PL", 7522 arm_SHADD16_VS: "SHADD16.VS", 7523 arm_SHADD16_VC: "SHADD16.VC", 7524 arm_SHADD16_HI: "SHADD16.HI", 7525 arm_SHADD16_LS: "SHADD16.LS", 7526 arm_SHADD16_GE: "SHADD16.GE", 7527 arm_SHADD16_LT: "SHADD16.LT", 7528 arm_SHADD16_GT: "SHADD16.GT", 7529 arm_SHADD16_LE: "SHADD16.LE", 7530 arm_SHADD16: "SHADD16", 7531 arm_SHADD16_ZZ: "SHADD16.ZZ", 7532 arm_SHADD8_EQ: "SHADD8.EQ", 7533 arm_SHADD8_NE: "SHADD8.NE", 7534 arm_SHADD8_CS: "SHADD8.CS", 7535 arm_SHADD8_CC: "SHADD8.CC", 7536 arm_SHADD8_MI: "SHADD8.MI", 7537 arm_SHADD8_PL: "SHADD8.PL", 7538 arm_SHADD8_VS: "SHADD8.VS", 7539 arm_SHADD8_VC: "SHADD8.VC", 7540 arm_SHADD8_HI: "SHADD8.HI", 7541 arm_SHADD8_LS: "SHADD8.LS", 7542 arm_SHADD8_GE: "SHADD8.GE", 7543 arm_SHADD8_LT: "SHADD8.LT", 7544 arm_SHADD8_GT: "SHADD8.GT", 7545 arm_SHADD8_LE: "SHADD8.LE", 7546 arm_SHADD8: "SHADD8", 7547 arm_SHADD8_ZZ: "SHADD8.ZZ", 7548 arm_SHASX_EQ: "SHASX.EQ", 7549 arm_SHASX_NE: "SHASX.NE", 7550 arm_SHASX_CS: "SHASX.CS", 7551 arm_SHASX_CC: "SHASX.CC", 7552 arm_SHASX_MI: "SHASX.MI", 7553 arm_SHASX_PL: "SHASX.PL", 7554 arm_SHASX_VS: "SHASX.VS", 7555 arm_SHASX_VC: "SHASX.VC", 7556 arm_SHASX_HI: "SHASX.HI", 7557 arm_SHASX_LS: "SHASX.LS", 7558 arm_SHASX_GE: "SHASX.GE", 7559 arm_SHASX_LT: "SHASX.LT", 7560 arm_SHASX_GT: "SHASX.GT", 7561 arm_SHASX_LE: "SHASX.LE", 7562 arm_SHASX: "SHASX", 7563 arm_SHASX_ZZ: "SHASX.ZZ", 7564 arm_SHSAX_EQ: "SHSAX.EQ", 7565 arm_SHSAX_NE: "SHSAX.NE", 7566 arm_SHSAX_CS: "SHSAX.CS", 7567 arm_SHSAX_CC: "SHSAX.CC", 7568 arm_SHSAX_MI: "SHSAX.MI", 7569 arm_SHSAX_PL: "SHSAX.PL", 7570 arm_SHSAX_VS: "SHSAX.VS", 7571 arm_SHSAX_VC: "SHSAX.VC", 7572 arm_SHSAX_HI: "SHSAX.HI", 7573 arm_SHSAX_LS: "SHSAX.LS", 7574 arm_SHSAX_GE: "SHSAX.GE", 7575 arm_SHSAX_LT: "SHSAX.LT", 7576 arm_SHSAX_GT: "SHSAX.GT", 7577 arm_SHSAX_LE: "SHSAX.LE", 7578 arm_SHSAX: "SHSAX", 7579 arm_SHSAX_ZZ: "SHSAX.ZZ", 7580 arm_SHSUB16_EQ: "SHSUB16.EQ", 7581 arm_SHSUB16_NE: "SHSUB16.NE", 7582 arm_SHSUB16_CS: "SHSUB16.CS", 7583 arm_SHSUB16_CC: "SHSUB16.CC", 7584 arm_SHSUB16_MI: "SHSUB16.MI", 7585 arm_SHSUB16_PL: "SHSUB16.PL", 7586 arm_SHSUB16_VS: "SHSUB16.VS", 7587 arm_SHSUB16_VC: "SHSUB16.VC", 7588 arm_SHSUB16_HI: "SHSUB16.HI", 7589 arm_SHSUB16_LS: "SHSUB16.LS", 7590 arm_SHSUB16_GE: "SHSUB16.GE", 7591 arm_SHSUB16_LT: "SHSUB16.LT", 7592 arm_SHSUB16_GT: "SHSUB16.GT", 7593 arm_SHSUB16_LE: "SHSUB16.LE", 7594 arm_SHSUB16: "SHSUB16", 7595 arm_SHSUB16_ZZ: "SHSUB16.ZZ", 7596 arm_SHSUB8_EQ: "SHSUB8.EQ", 7597 arm_SHSUB8_NE: "SHSUB8.NE", 7598 arm_SHSUB8_CS: "SHSUB8.CS", 7599 arm_SHSUB8_CC: "SHSUB8.CC", 7600 arm_SHSUB8_MI: "SHSUB8.MI", 7601 arm_SHSUB8_PL: "SHSUB8.PL", 7602 arm_SHSUB8_VS: "SHSUB8.VS", 7603 arm_SHSUB8_VC: "SHSUB8.VC", 7604 arm_SHSUB8_HI: "SHSUB8.HI", 7605 arm_SHSUB8_LS: "SHSUB8.LS", 7606 arm_SHSUB8_GE: "SHSUB8.GE", 7607 arm_SHSUB8_LT: "SHSUB8.LT", 7608 arm_SHSUB8_GT: "SHSUB8.GT", 7609 arm_SHSUB8_LE: "SHSUB8.LE", 7610 arm_SHSUB8: "SHSUB8", 7611 arm_SHSUB8_ZZ: "SHSUB8.ZZ", 7612 arm_SMLABB_EQ: "SMLABB.EQ", 7613 arm_SMLABB_NE: "SMLABB.NE", 7614 arm_SMLABB_CS: "SMLABB.CS", 7615 arm_SMLABB_CC: "SMLABB.CC", 7616 arm_SMLABB_MI: "SMLABB.MI", 7617 arm_SMLABB_PL: "SMLABB.PL", 7618 arm_SMLABB_VS: "SMLABB.VS", 7619 arm_SMLABB_VC: "SMLABB.VC", 7620 arm_SMLABB_HI: "SMLABB.HI", 7621 arm_SMLABB_LS: "SMLABB.LS", 7622 arm_SMLABB_GE: "SMLABB.GE", 7623 arm_SMLABB_LT: "SMLABB.LT", 7624 arm_SMLABB_GT: "SMLABB.GT", 7625 arm_SMLABB_LE: "SMLABB.LE", 7626 arm_SMLABB: "SMLABB", 7627 arm_SMLABB_ZZ: "SMLABB.ZZ", 7628 arm_SMLABT_EQ: "SMLABT.EQ", 7629 arm_SMLABT_NE: "SMLABT.NE", 7630 arm_SMLABT_CS: "SMLABT.CS", 7631 arm_SMLABT_CC: "SMLABT.CC", 7632 arm_SMLABT_MI: "SMLABT.MI", 7633 arm_SMLABT_PL: "SMLABT.PL", 7634 arm_SMLABT_VS: "SMLABT.VS", 7635 arm_SMLABT_VC: "SMLABT.VC", 7636 arm_SMLABT_HI: "SMLABT.HI", 7637 arm_SMLABT_LS: "SMLABT.LS", 7638 arm_SMLABT_GE: "SMLABT.GE", 7639 arm_SMLABT_LT: "SMLABT.LT", 7640 arm_SMLABT_GT: "SMLABT.GT", 7641 arm_SMLABT_LE: "SMLABT.LE", 7642 arm_SMLABT: "SMLABT", 7643 arm_SMLABT_ZZ: "SMLABT.ZZ", 7644 arm_SMLATB_EQ: "SMLATB.EQ", 7645 arm_SMLATB_NE: "SMLATB.NE", 7646 arm_SMLATB_CS: "SMLATB.CS", 7647 arm_SMLATB_CC: "SMLATB.CC", 7648 arm_SMLATB_MI: "SMLATB.MI", 7649 arm_SMLATB_PL: "SMLATB.PL", 7650 arm_SMLATB_VS: "SMLATB.VS", 7651 arm_SMLATB_VC: "SMLATB.VC", 7652 arm_SMLATB_HI: "SMLATB.HI", 7653 arm_SMLATB_LS: "SMLATB.LS", 7654 arm_SMLATB_GE: "SMLATB.GE", 7655 arm_SMLATB_LT: "SMLATB.LT", 7656 arm_SMLATB_GT: "SMLATB.GT", 7657 arm_SMLATB_LE: "SMLATB.LE", 7658 arm_SMLATB: "SMLATB", 7659 arm_SMLATB_ZZ: "SMLATB.ZZ", 7660 arm_SMLATT_EQ: "SMLATT.EQ", 7661 arm_SMLATT_NE: "SMLATT.NE", 7662 arm_SMLATT_CS: "SMLATT.CS", 7663 arm_SMLATT_CC: "SMLATT.CC", 7664 arm_SMLATT_MI: "SMLATT.MI", 7665 arm_SMLATT_PL: "SMLATT.PL", 7666 arm_SMLATT_VS: "SMLATT.VS", 7667 arm_SMLATT_VC: "SMLATT.VC", 7668 arm_SMLATT_HI: "SMLATT.HI", 7669 arm_SMLATT_LS: "SMLATT.LS", 7670 arm_SMLATT_GE: "SMLATT.GE", 7671 arm_SMLATT_LT: "SMLATT.LT", 7672 arm_SMLATT_GT: "SMLATT.GT", 7673 arm_SMLATT_LE: "SMLATT.LE", 7674 arm_SMLATT: "SMLATT", 7675 arm_SMLATT_ZZ: "SMLATT.ZZ", 7676 arm_SMLAD_EQ: "SMLAD.EQ", 7677 arm_SMLAD_NE: "SMLAD.NE", 7678 arm_SMLAD_CS: "SMLAD.CS", 7679 arm_SMLAD_CC: "SMLAD.CC", 7680 arm_SMLAD_MI: "SMLAD.MI", 7681 arm_SMLAD_PL: "SMLAD.PL", 7682 arm_SMLAD_VS: "SMLAD.VS", 7683 arm_SMLAD_VC: "SMLAD.VC", 7684 arm_SMLAD_HI: "SMLAD.HI", 7685 arm_SMLAD_LS: "SMLAD.LS", 7686 arm_SMLAD_GE: "SMLAD.GE", 7687 arm_SMLAD_LT: "SMLAD.LT", 7688 arm_SMLAD_GT: "SMLAD.GT", 7689 arm_SMLAD_LE: "SMLAD.LE", 7690 arm_SMLAD: "SMLAD", 7691 arm_SMLAD_ZZ: "SMLAD.ZZ", 7692 arm_SMLAD_X_EQ: "SMLAD.X.EQ", 7693 arm_SMLAD_X_NE: "SMLAD.X.NE", 7694 arm_SMLAD_X_CS: "SMLAD.X.CS", 7695 arm_SMLAD_X_CC: "SMLAD.X.CC", 7696 arm_SMLAD_X_MI: "SMLAD.X.MI", 7697 arm_SMLAD_X_PL: "SMLAD.X.PL", 7698 arm_SMLAD_X_VS: "SMLAD.X.VS", 7699 arm_SMLAD_X_VC: "SMLAD.X.VC", 7700 arm_SMLAD_X_HI: "SMLAD.X.HI", 7701 arm_SMLAD_X_LS: "SMLAD.X.LS", 7702 arm_SMLAD_X_GE: "SMLAD.X.GE", 7703 arm_SMLAD_X_LT: "SMLAD.X.LT", 7704 arm_SMLAD_X_GT: "SMLAD.X.GT", 7705 arm_SMLAD_X_LE: "SMLAD.X.LE", 7706 arm_SMLAD_X: "SMLAD.X", 7707 arm_SMLAD_X_ZZ: "SMLAD.X.ZZ", 7708 arm_SMLAL_EQ: "SMLAL.EQ", 7709 arm_SMLAL_NE: "SMLAL.NE", 7710 arm_SMLAL_CS: "SMLAL.CS", 7711 arm_SMLAL_CC: "SMLAL.CC", 7712 arm_SMLAL_MI: "SMLAL.MI", 7713 arm_SMLAL_PL: "SMLAL.PL", 7714 arm_SMLAL_VS: "SMLAL.VS", 7715 arm_SMLAL_VC: "SMLAL.VC", 7716 arm_SMLAL_HI: "SMLAL.HI", 7717 arm_SMLAL_LS: "SMLAL.LS", 7718 arm_SMLAL_GE: "SMLAL.GE", 7719 arm_SMLAL_LT: "SMLAL.LT", 7720 arm_SMLAL_GT: "SMLAL.GT", 7721 arm_SMLAL_LE: "SMLAL.LE", 7722 arm_SMLAL: "SMLAL", 7723 arm_SMLAL_ZZ: "SMLAL.ZZ", 7724 arm_SMLAL_S_EQ: "SMLAL.S.EQ", 7725 arm_SMLAL_S_NE: "SMLAL.S.NE", 7726 arm_SMLAL_S_CS: "SMLAL.S.CS", 7727 arm_SMLAL_S_CC: "SMLAL.S.CC", 7728 arm_SMLAL_S_MI: "SMLAL.S.MI", 7729 arm_SMLAL_S_PL: "SMLAL.S.PL", 7730 arm_SMLAL_S_VS: "SMLAL.S.VS", 7731 arm_SMLAL_S_VC: "SMLAL.S.VC", 7732 arm_SMLAL_S_HI: "SMLAL.S.HI", 7733 arm_SMLAL_S_LS: "SMLAL.S.LS", 7734 arm_SMLAL_S_GE: "SMLAL.S.GE", 7735 arm_SMLAL_S_LT: "SMLAL.S.LT", 7736 arm_SMLAL_S_GT: "SMLAL.S.GT", 7737 arm_SMLAL_S_LE: "SMLAL.S.LE", 7738 arm_SMLAL_S: "SMLAL.S", 7739 arm_SMLAL_S_ZZ: "SMLAL.S.ZZ", 7740 arm_SMLALBB_EQ: "SMLALBB.EQ", 7741 arm_SMLALBB_NE: "SMLALBB.NE", 7742 arm_SMLALBB_CS: "SMLALBB.CS", 7743 arm_SMLALBB_CC: "SMLALBB.CC", 7744 arm_SMLALBB_MI: "SMLALBB.MI", 7745 arm_SMLALBB_PL: "SMLALBB.PL", 7746 arm_SMLALBB_VS: "SMLALBB.VS", 7747 arm_SMLALBB_VC: "SMLALBB.VC", 7748 arm_SMLALBB_HI: "SMLALBB.HI", 7749 arm_SMLALBB_LS: "SMLALBB.LS", 7750 arm_SMLALBB_GE: "SMLALBB.GE", 7751 arm_SMLALBB_LT: "SMLALBB.LT", 7752 arm_SMLALBB_GT: "SMLALBB.GT", 7753 arm_SMLALBB_LE: "SMLALBB.LE", 7754 arm_SMLALBB: "SMLALBB", 7755 arm_SMLALBB_ZZ: "SMLALBB.ZZ", 7756 arm_SMLALBT_EQ: "SMLALBT.EQ", 7757 arm_SMLALBT_NE: "SMLALBT.NE", 7758 arm_SMLALBT_CS: "SMLALBT.CS", 7759 arm_SMLALBT_CC: "SMLALBT.CC", 7760 arm_SMLALBT_MI: "SMLALBT.MI", 7761 arm_SMLALBT_PL: "SMLALBT.PL", 7762 arm_SMLALBT_VS: "SMLALBT.VS", 7763 arm_SMLALBT_VC: "SMLALBT.VC", 7764 arm_SMLALBT_HI: "SMLALBT.HI", 7765 arm_SMLALBT_LS: "SMLALBT.LS", 7766 arm_SMLALBT_GE: "SMLALBT.GE", 7767 arm_SMLALBT_LT: "SMLALBT.LT", 7768 arm_SMLALBT_GT: "SMLALBT.GT", 7769 arm_SMLALBT_LE: "SMLALBT.LE", 7770 arm_SMLALBT: "SMLALBT", 7771 arm_SMLALBT_ZZ: "SMLALBT.ZZ", 7772 arm_SMLALTB_EQ: "SMLALTB.EQ", 7773 arm_SMLALTB_NE: "SMLALTB.NE", 7774 arm_SMLALTB_CS: "SMLALTB.CS", 7775 arm_SMLALTB_CC: "SMLALTB.CC", 7776 arm_SMLALTB_MI: "SMLALTB.MI", 7777 arm_SMLALTB_PL: "SMLALTB.PL", 7778 arm_SMLALTB_VS: "SMLALTB.VS", 7779 arm_SMLALTB_VC: "SMLALTB.VC", 7780 arm_SMLALTB_HI: "SMLALTB.HI", 7781 arm_SMLALTB_LS: "SMLALTB.LS", 7782 arm_SMLALTB_GE: "SMLALTB.GE", 7783 arm_SMLALTB_LT: "SMLALTB.LT", 7784 arm_SMLALTB_GT: "SMLALTB.GT", 7785 arm_SMLALTB_LE: "SMLALTB.LE", 7786 arm_SMLALTB: "SMLALTB", 7787 arm_SMLALTB_ZZ: "SMLALTB.ZZ", 7788 arm_SMLALTT_EQ: "SMLALTT.EQ", 7789 arm_SMLALTT_NE: "SMLALTT.NE", 7790 arm_SMLALTT_CS: "SMLALTT.CS", 7791 arm_SMLALTT_CC: "SMLALTT.CC", 7792 arm_SMLALTT_MI: "SMLALTT.MI", 7793 arm_SMLALTT_PL: "SMLALTT.PL", 7794 arm_SMLALTT_VS: "SMLALTT.VS", 7795 arm_SMLALTT_VC: "SMLALTT.VC", 7796 arm_SMLALTT_HI: "SMLALTT.HI", 7797 arm_SMLALTT_LS: "SMLALTT.LS", 7798 arm_SMLALTT_GE: "SMLALTT.GE", 7799 arm_SMLALTT_LT: "SMLALTT.LT", 7800 arm_SMLALTT_GT: "SMLALTT.GT", 7801 arm_SMLALTT_LE: "SMLALTT.LE", 7802 arm_SMLALTT: "SMLALTT", 7803 arm_SMLALTT_ZZ: "SMLALTT.ZZ", 7804 arm_SMLALD_EQ: "SMLALD.EQ", 7805 arm_SMLALD_NE: "SMLALD.NE", 7806 arm_SMLALD_CS: "SMLALD.CS", 7807 arm_SMLALD_CC: "SMLALD.CC", 7808 arm_SMLALD_MI: "SMLALD.MI", 7809 arm_SMLALD_PL: "SMLALD.PL", 7810 arm_SMLALD_VS: "SMLALD.VS", 7811 arm_SMLALD_VC: "SMLALD.VC", 7812 arm_SMLALD_HI: "SMLALD.HI", 7813 arm_SMLALD_LS: "SMLALD.LS", 7814 arm_SMLALD_GE: "SMLALD.GE", 7815 arm_SMLALD_LT: "SMLALD.LT", 7816 arm_SMLALD_GT: "SMLALD.GT", 7817 arm_SMLALD_LE: "SMLALD.LE", 7818 arm_SMLALD: "SMLALD", 7819 arm_SMLALD_ZZ: "SMLALD.ZZ", 7820 arm_SMLALD_X_EQ: "SMLALD.X.EQ", 7821 arm_SMLALD_X_NE: "SMLALD.X.NE", 7822 arm_SMLALD_X_CS: "SMLALD.X.CS", 7823 arm_SMLALD_X_CC: "SMLALD.X.CC", 7824 arm_SMLALD_X_MI: "SMLALD.X.MI", 7825 arm_SMLALD_X_PL: "SMLALD.X.PL", 7826 arm_SMLALD_X_VS: "SMLALD.X.VS", 7827 arm_SMLALD_X_VC: "SMLALD.X.VC", 7828 arm_SMLALD_X_HI: "SMLALD.X.HI", 7829 arm_SMLALD_X_LS: "SMLALD.X.LS", 7830 arm_SMLALD_X_GE: "SMLALD.X.GE", 7831 arm_SMLALD_X_LT: "SMLALD.X.LT", 7832 arm_SMLALD_X_GT: "SMLALD.X.GT", 7833 arm_SMLALD_X_LE: "SMLALD.X.LE", 7834 arm_SMLALD_X: "SMLALD.X", 7835 arm_SMLALD_X_ZZ: "SMLALD.X.ZZ", 7836 arm_SMLAWB_EQ: "SMLAWB.EQ", 7837 arm_SMLAWB_NE: "SMLAWB.NE", 7838 arm_SMLAWB_CS: "SMLAWB.CS", 7839 arm_SMLAWB_CC: "SMLAWB.CC", 7840 arm_SMLAWB_MI: "SMLAWB.MI", 7841 arm_SMLAWB_PL: "SMLAWB.PL", 7842 arm_SMLAWB_VS: "SMLAWB.VS", 7843 arm_SMLAWB_VC: "SMLAWB.VC", 7844 arm_SMLAWB_HI: "SMLAWB.HI", 7845 arm_SMLAWB_LS: "SMLAWB.LS", 7846 arm_SMLAWB_GE: "SMLAWB.GE", 7847 arm_SMLAWB_LT: "SMLAWB.LT", 7848 arm_SMLAWB_GT: "SMLAWB.GT", 7849 arm_SMLAWB_LE: "SMLAWB.LE", 7850 arm_SMLAWB: "SMLAWB", 7851 arm_SMLAWB_ZZ: "SMLAWB.ZZ", 7852 arm_SMLAWT_EQ: "SMLAWT.EQ", 7853 arm_SMLAWT_NE: "SMLAWT.NE", 7854 arm_SMLAWT_CS: "SMLAWT.CS", 7855 arm_SMLAWT_CC: "SMLAWT.CC", 7856 arm_SMLAWT_MI: "SMLAWT.MI", 7857 arm_SMLAWT_PL: "SMLAWT.PL", 7858 arm_SMLAWT_VS: "SMLAWT.VS", 7859 arm_SMLAWT_VC: "SMLAWT.VC", 7860 arm_SMLAWT_HI: "SMLAWT.HI", 7861 arm_SMLAWT_LS: "SMLAWT.LS", 7862 arm_SMLAWT_GE: "SMLAWT.GE", 7863 arm_SMLAWT_LT: "SMLAWT.LT", 7864 arm_SMLAWT_GT: "SMLAWT.GT", 7865 arm_SMLAWT_LE: "SMLAWT.LE", 7866 arm_SMLAWT: "SMLAWT", 7867 arm_SMLAWT_ZZ: "SMLAWT.ZZ", 7868 arm_SMLSD_EQ: "SMLSD.EQ", 7869 arm_SMLSD_NE: "SMLSD.NE", 7870 arm_SMLSD_CS: "SMLSD.CS", 7871 arm_SMLSD_CC: "SMLSD.CC", 7872 arm_SMLSD_MI: "SMLSD.MI", 7873 arm_SMLSD_PL: "SMLSD.PL", 7874 arm_SMLSD_VS: "SMLSD.VS", 7875 arm_SMLSD_VC: "SMLSD.VC", 7876 arm_SMLSD_HI: "SMLSD.HI", 7877 arm_SMLSD_LS: "SMLSD.LS", 7878 arm_SMLSD_GE: "SMLSD.GE", 7879 arm_SMLSD_LT: "SMLSD.LT", 7880 arm_SMLSD_GT: "SMLSD.GT", 7881 arm_SMLSD_LE: "SMLSD.LE", 7882 arm_SMLSD: "SMLSD", 7883 arm_SMLSD_ZZ: "SMLSD.ZZ", 7884 arm_SMLSD_X_EQ: "SMLSD.X.EQ", 7885 arm_SMLSD_X_NE: "SMLSD.X.NE", 7886 arm_SMLSD_X_CS: "SMLSD.X.CS", 7887 arm_SMLSD_X_CC: "SMLSD.X.CC", 7888 arm_SMLSD_X_MI: "SMLSD.X.MI", 7889 arm_SMLSD_X_PL: "SMLSD.X.PL", 7890 arm_SMLSD_X_VS: "SMLSD.X.VS", 7891 arm_SMLSD_X_VC: "SMLSD.X.VC", 7892 arm_SMLSD_X_HI: "SMLSD.X.HI", 7893 arm_SMLSD_X_LS: "SMLSD.X.LS", 7894 arm_SMLSD_X_GE: "SMLSD.X.GE", 7895 arm_SMLSD_X_LT: "SMLSD.X.LT", 7896 arm_SMLSD_X_GT: "SMLSD.X.GT", 7897 arm_SMLSD_X_LE: "SMLSD.X.LE", 7898 arm_SMLSD_X: "SMLSD.X", 7899 arm_SMLSD_X_ZZ: "SMLSD.X.ZZ", 7900 arm_SMLSLD_EQ: "SMLSLD.EQ", 7901 arm_SMLSLD_NE: "SMLSLD.NE", 7902 arm_SMLSLD_CS: "SMLSLD.CS", 7903 arm_SMLSLD_CC: "SMLSLD.CC", 7904 arm_SMLSLD_MI: "SMLSLD.MI", 7905 arm_SMLSLD_PL: "SMLSLD.PL", 7906 arm_SMLSLD_VS: "SMLSLD.VS", 7907 arm_SMLSLD_VC: "SMLSLD.VC", 7908 arm_SMLSLD_HI: "SMLSLD.HI", 7909 arm_SMLSLD_LS: "SMLSLD.LS", 7910 arm_SMLSLD_GE: "SMLSLD.GE", 7911 arm_SMLSLD_LT: "SMLSLD.LT", 7912 arm_SMLSLD_GT: "SMLSLD.GT", 7913 arm_SMLSLD_LE: "SMLSLD.LE", 7914 arm_SMLSLD: "SMLSLD", 7915 arm_SMLSLD_ZZ: "SMLSLD.ZZ", 7916 arm_SMLSLD_X_EQ: "SMLSLD.X.EQ", 7917 arm_SMLSLD_X_NE: "SMLSLD.X.NE", 7918 arm_SMLSLD_X_CS: "SMLSLD.X.CS", 7919 arm_SMLSLD_X_CC: "SMLSLD.X.CC", 7920 arm_SMLSLD_X_MI: "SMLSLD.X.MI", 7921 arm_SMLSLD_X_PL: "SMLSLD.X.PL", 7922 arm_SMLSLD_X_VS: "SMLSLD.X.VS", 7923 arm_SMLSLD_X_VC: "SMLSLD.X.VC", 7924 arm_SMLSLD_X_HI: "SMLSLD.X.HI", 7925 arm_SMLSLD_X_LS: "SMLSLD.X.LS", 7926 arm_SMLSLD_X_GE: "SMLSLD.X.GE", 7927 arm_SMLSLD_X_LT: "SMLSLD.X.LT", 7928 arm_SMLSLD_X_GT: "SMLSLD.X.GT", 7929 arm_SMLSLD_X_LE: "SMLSLD.X.LE", 7930 arm_SMLSLD_X: "SMLSLD.X", 7931 arm_SMLSLD_X_ZZ: "SMLSLD.X.ZZ", 7932 arm_SMMLA_EQ: "SMMLA.EQ", 7933 arm_SMMLA_NE: "SMMLA.NE", 7934 arm_SMMLA_CS: "SMMLA.CS", 7935 arm_SMMLA_CC: "SMMLA.CC", 7936 arm_SMMLA_MI: "SMMLA.MI", 7937 arm_SMMLA_PL: "SMMLA.PL", 7938 arm_SMMLA_VS: "SMMLA.VS", 7939 arm_SMMLA_VC: "SMMLA.VC", 7940 arm_SMMLA_HI: "SMMLA.HI", 7941 arm_SMMLA_LS: "SMMLA.LS", 7942 arm_SMMLA_GE: "SMMLA.GE", 7943 arm_SMMLA_LT: "SMMLA.LT", 7944 arm_SMMLA_GT: "SMMLA.GT", 7945 arm_SMMLA_LE: "SMMLA.LE", 7946 arm_SMMLA: "SMMLA", 7947 arm_SMMLA_ZZ: "SMMLA.ZZ", 7948 arm_SMMLA_R_EQ: "SMMLA.R.EQ", 7949 arm_SMMLA_R_NE: "SMMLA.R.NE", 7950 arm_SMMLA_R_CS: "SMMLA.R.CS", 7951 arm_SMMLA_R_CC: "SMMLA.R.CC", 7952 arm_SMMLA_R_MI: "SMMLA.R.MI", 7953 arm_SMMLA_R_PL: "SMMLA.R.PL", 7954 arm_SMMLA_R_VS: "SMMLA.R.VS", 7955 arm_SMMLA_R_VC: "SMMLA.R.VC", 7956 arm_SMMLA_R_HI: "SMMLA.R.HI", 7957 arm_SMMLA_R_LS: "SMMLA.R.LS", 7958 arm_SMMLA_R_GE: "SMMLA.R.GE", 7959 arm_SMMLA_R_LT: "SMMLA.R.LT", 7960 arm_SMMLA_R_GT: "SMMLA.R.GT", 7961 arm_SMMLA_R_LE: "SMMLA.R.LE", 7962 arm_SMMLA_R: "SMMLA.R", 7963 arm_SMMLA_R_ZZ: "SMMLA.R.ZZ", 7964 arm_SMMLS_EQ: "SMMLS.EQ", 7965 arm_SMMLS_NE: "SMMLS.NE", 7966 arm_SMMLS_CS: "SMMLS.CS", 7967 arm_SMMLS_CC: "SMMLS.CC", 7968 arm_SMMLS_MI: "SMMLS.MI", 7969 arm_SMMLS_PL: "SMMLS.PL", 7970 arm_SMMLS_VS: "SMMLS.VS", 7971 arm_SMMLS_VC: "SMMLS.VC", 7972 arm_SMMLS_HI: "SMMLS.HI", 7973 arm_SMMLS_LS: "SMMLS.LS", 7974 arm_SMMLS_GE: "SMMLS.GE", 7975 arm_SMMLS_LT: "SMMLS.LT", 7976 arm_SMMLS_GT: "SMMLS.GT", 7977 arm_SMMLS_LE: "SMMLS.LE", 7978 arm_SMMLS: "SMMLS", 7979 arm_SMMLS_ZZ: "SMMLS.ZZ", 7980 arm_SMMLS_R_EQ: "SMMLS.R.EQ", 7981 arm_SMMLS_R_NE: "SMMLS.R.NE", 7982 arm_SMMLS_R_CS: "SMMLS.R.CS", 7983 arm_SMMLS_R_CC: "SMMLS.R.CC", 7984 arm_SMMLS_R_MI: "SMMLS.R.MI", 7985 arm_SMMLS_R_PL: "SMMLS.R.PL", 7986 arm_SMMLS_R_VS: "SMMLS.R.VS", 7987 arm_SMMLS_R_VC: "SMMLS.R.VC", 7988 arm_SMMLS_R_HI: "SMMLS.R.HI", 7989 arm_SMMLS_R_LS: "SMMLS.R.LS", 7990 arm_SMMLS_R_GE: "SMMLS.R.GE", 7991 arm_SMMLS_R_LT: "SMMLS.R.LT", 7992 arm_SMMLS_R_GT: "SMMLS.R.GT", 7993 arm_SMMLS_R_LE: "SMMLS.R.LE", 7994 arm_SMMLS_R: "SMMLS.R", 7995 arm_SMMLS_R_ZZ: "SMMLS.R.ZZ", 7996 arm_SMMUL_EQ: "SMMUL.EQ", 7997 arm_SMMUL_NE: "SMMUL.NE", 7998 arm_SMMUL_CS: "SMMUL.CS", 7999 arm_SMMUL_CC: "SMMUL.CC", 8000 arm_SMMUL_MI: "SMMUL.MI", 8001 arm_SMMUL_PL: "SMMUL.PL", 8002 arm_SMMUL_VS: "SMMUL.VS", 8003 arm_SMMUL_VC: "SMMUL.VC", 8004 arm_SMMUL_HI: "SMMUL.HI", 8005 arm_SMMUL_LS: "SMMUL.LS", 8006 arm_SMMUL_GE: "SMMUL.GE", 8007 arm_SMMUL_LT: "SMMUL.LT", 8008 arm_SMMUL_GT: "SMMUL.GT", 8009 arm_SMMUL_LE: "SMMUL.LE", 8010 arm_SMMUL: "SMMUL", 8011 arm_SMMUL_ZZ: "SMMUL.ZZ", 8012 arm_SMMUL_R_EQ: "SMMUL.R.EQ", 8013 arm_SMMUL_R_NE: "SMMUL.R.NE", 8014 arm_SMMUL_R_CS: "SMMUL.R.CS", 8015 arm_SMMUL_R_CC: "SMMUL.R.CC", 8016 arm_SMMUL_R_MI: "SMMUL.R.MI", 8017 arm_SMMUL_R_PL: "SMMUL.R.PL", 8018 arm_SMMUL_R_VS: "SMMUL.R.VS", 8019 arm_SMMUL_R_VC: "SMMUL.R.VC", 8020 arm_SMMUL_R_HI: "SMMUL.R.HI", 8021 arm_SMMUL_R_LS: "SMMUL.R.LS", 8022 arm_SMMUL_R_GE: "SMMUL.R.GE", 8023 arm_SMMUL_R_LT: "SMMUL.R.LT", 8024 arm_SMMUL_R_GT: "SMMUL.R.GT", 8025 arm_SMMUL_R_LE: "SMMUL.R.LE", 8026 arm_SMMUL_R: "SMMUL.R", 8027 arm_SMMUL_R_ZZ: "SMMUL.R.ZZ", 8028 arm_SMUAD_EQ: "SMUAD.EQ", 8029 arm_SMUAD_NE: "SMUAD.NE", 8030 arm_SMUAD_CS: "SMUAD.CS", 8031 arm_SMUAD_CC: "SMUAD.CC", 8032 arm_SMUAD_MI: "SMUAD.MI", 8033 arm_SMUAD_PL: "SMUAD.PL", 8034 arm_SMUAD_VS: "SMUAD.VS", 8035 arm_SMUAD_VC: "SMUAD.VC", 8036 arm_SMUAD_HI: "SMUAD.HI", 8037 arm_SMUAD_LS: "SMUAD.LS", 8038 arm_SMUAD_GE: "SMUAD.GE", 8039 arm_SMUAD_LT: "SMUAD.LT", 8040 arm_SMUAD_GT: "SMUAD.GT", 8041 arm_SMUAD_LE: "SMUAD.LE", 8042 arm_SMUAD: "SMUAD", 8043 arm_SMUAD_ZZ: "SMUAD.ZZ", 8044 arm_SMUAD_X_EQ: "SMUAD.X.EQ", 8045 arm_SMUAD_X_NE: "SMUAD.X.NE", 8046 arm_SMUAD_X_CS: "SMUAD.X.CS", 8047 arm_SMUAD_X_CC: "SMUAD.X.CC", 8048 arm_SMUAD_X_MI: "SMUAD.X.MI", 8049 arm_SMUAD_X_PL: "SMUAD.X.PL", 8050 arm_SMUAD_X_VS: "SMUAD.X.VS", 8051 arm_SMUAD_X_VC: "SMUAD.X.VC", 8052 arm_SMUAD_X_HI: "SMUAD.X.HI", 8053 arm_SMUAD_X_LS: "SMUAD.X.LS", 8054 arm_SMUAD_X_GE: "SMUAD.X.GE", 8055 arm_SMUAD_X_LT: "SMUAD.X.LT", 8056 arm_SMUAD_X_GT: "SMUAD.X.GT", 8057 arm_SMUAD_X_LE: "SMUAD.X.LE", 8058 arm_SMUAD_X: "SMUAD.X", 8059 arm_SMUAD_X_ZZ: "SMUAD.X.ZZ", 8060 arm_SMULBB_EQ: "SMULBB.EQ", 8061 arm_SMULBB_NE: "SMULBB.NE", 8062 arm_SMULBB_CS: "SMULBB.CS", 8063 arm_SMULBB_CC: "SMULBB.CC", 8064 arm_SMULBB_MI: "SMULBB.MI", 8065 arm_SMULBB_PL: "SMULBB.PL", 8066 arm_SMULBB_VS: "SMULBB.VS", 8067 arm_SMULBB_VC: "SMULBB.VC", 8068 arm_SMULBB_HI: "SMULBB.HI", 8069 arm_SMULBB_LS: "SMULBB.LS", 8070 arm_SMULBB_GE: "SMULBB.GE", 8071 arm_SMULBB_LT: "SMULBB.LT", 8072 arm_SMULBB_GT: "SMULBB.GT", 8073 arm_SMULBB_LE: "SMULBB.LE", 8074 arm_SMULBB: "SMULBB", 8075 arm_SMULBB_ZZ: "SMULBB.ZZ", 8076 arm_SMULBT_EQ: "SMULBT.EQ", 8077 arm_SMULBT_NE: "SMULBT.NE", 8078 arm_SMULBT_CS: "SMULBT.CS", 8079 arm_SMULBT_CC: "SMULBT.CC", 8080 arm_SMULBT_MI: "SMULBT.MI", 8081 arm_SMULBT_PL: "SMULBT.PL", 8082 arm_SMULBT_VS: "SMULBT.VS", 8083 arm_SMULBT_VC: "SMULBT.VC", 8084 arm_SMULBT_HI: "SMULBT.HI", 8085 arm_SMULBT_LS: "SMULBT.LS", 8086 arm_SMULBT_GE: "SMULBT.GE", 8087 arm_SMULBT_LT: "SMULBT.LT", 8088 arm_SMULBT_GT: "SMULBT.GT", 8089 arm_SMULBT_LE: "SMULBT.LE", 8090 arm_SMULBT: "SMULBT", 8091 arm_SMULBT_ZZ: "SMULBT.ZZ", 8092 arm_SMULTB_EQ: "SMULTB.EQ", 8093 arm_SMULTB_NE: "SMULTB.NE", 8094 arm_SMULTB_CS: "SMULTB.CS", 8095 arm_SMULTB_CC: "SMULTB.CC", 8096 arm_SMULTB_MI: "SMULTB.MI", 8097 arm_SMULTB_PL: "SMULTB.PL", 8098 arm_SMULTB_VS: "SMULTB.VS", 8099 arm_SMULTB_VC: "SMULTB.VC", 8100 arm_SMULTB_HI: "SMULTB.HI", 8101 arm_SMULTB_LS: "SMULTB.LS", 8102 arm_SMULTB_GE: "SMULTB.GE", 8103 arm_SMULTB_LT: "SMULTB.LT", 8104 arm_SMULTB_GT: "SMULTB.GT", 8105 arm_SMULTB_LE: "SMULTB.LE", 8106 arm_SMULTB: "SMULTB", 8107 arm_SMULTB_ZZ: "SMULTB.ZZ", 8108 arm_SMULTT_EQ: "SMULTT.EQ", 8109 arm_SMULTT_NE: "SMULTT.NE", 8110 arm_SMULTT_CS: "SMULTT.CS", 8111 arm_SMULTT_CC: "SMULTT.CC", 8112 arm_SMULTT_MI: "SMULTT.MI", 8113 arm_SMULTT_PL: "SMULTT.PL", 8114 arm_SMULTT_VS: "SMULTT.VS", 8115 arm_SMULTT_VC: "SMULTT.VC", 8116 arm_SMULTT_HI: "SMULTT.HI", 8117 arm_SMULTT_LS: "SMULTT.LS", 8118 arm_SMULTT_GE: "SMULTT.GE", 8119 arm_SMULTT_LT: "SMULTT.LT", 8120 arm_SMULTT_GT: "SMULTT.GT", 8121 arm_SMULTT_LE: "SMULTT.LE", 8122 arm_SMULTT: "SMULTT", 8123 arm_SMULTT_ZZ: "SMULTT.ZZ", 8124 arm_SMULL_EQ: "SMULL.EQ", 8125 arm_SMULL_NE: "SMULL.NE", 8126 arm_SMULL_CS: "SMULL.CS", 8127 arm_SMULL_CC: "SMULL.CC", 8128 arm_SMULL_MI: "SMULL.MI", 8129 arm_SMULL_PL: "SMULL.PL", 8130 arm_SMULL_VS: "SMULL.VS", 8131 arm_SMULL_VC: "SMULL.VC", 8132 arm_SMULL_HI: "SMULL.HI", 8133 arm_SMULL_LS: "SMULL.LS", 8134 arm_SMULL_GE: "SMULL.GE", 8135 arm_SMULL_LT: "SMULL.LT", 8136 arm_SMULL_GT: "SMULL.GT", 8137 arm_SMULL_LE: "SMULL.LE", 8138 arm_SMULL: "SMULL", 8139 arm_SMULL_ZZ: "SMULL.ZZ", 8140 arm_SMULL_S_EQ: "SMULL.S.EQ", 8141 arm_SMULL_S_NE: "SMULL.S.NE", 8142 arm_SMULL_S_CS: "SMULL.S.CS", 8143 arm_SMULL_S_CC: "SMULL.S.CC", 8144 arm_SMULL_S_MI: "SMULL.S.MI", 8145 arm_SMULL_S_PL: "SMULL.S.PL", 8146 arm_SMULL_S_VS: "SMULL.S.VS", 8147 arm_SMULL_S_VC: "SMULL.S.VC", 8148 arm_SMULL_S_HI: "SMULL.S.HI", 8149 arm_SMULL_S_LS: "SMULL.S.LS", 8150 arm_SMULL_S_GE: "SMULL.S.GE", 8151 arm_SMULL_S_LT: "SMULL.S.LT", 8152 arm_SMULL_S_GT: "SMULL.S.GT", 8153 arm_SMULL_S_LE: "SMULL.S.LE", 8154 arm_SMULL_S: "SMULL.S", 8155 arm_SMULL_S_ZZ: "SMULL.S.ZZ", 8156 arm_SMULWB_EQ: "SMULWB.EQ", 8157 arm_SMULWB_NE: "SMULWB.NE", 8158 arm_SMULWB_CS: "SMULWB.CS", 8159 arm_SMULWB_CC: "SMULWB.CC", 8160 arm_SMULWB_MI: "SMULWB.MI", 8161 arm_SMULWB_PL: "SMULWB.PL", 8162 arm_SMULWB_VS: "SMULWB.VS", 8163 arm_SMULWB_VC: "SMULWB.VC", 8164 arm_SMULWB_HI: "SMULWB.HI", 8165 arm_SMULWB_LS: "SMULWB.LS", 8166 arm_SMULWB_GE: "SMULWB.GE", 8167 arm_SMULWB_LT: "SMULWB.LT", 8168 arm_SMULWB_GT: "SMULWB.GT", 8169 arm_SMULWB_LE: "SMULWB.LE", 8170 arm_SMULWB: "SMULWB", 8171 arm_SMULWB_ZZ: "SMULWB.ZZ", 8172 arm_SMULWT_EQ: "SMULWT.EQ", 8173 arm_SMULWT_NE: "SMULWT.NE", 8174 arm_SMULWT_CS: "SMULWT.CS", 8175 arm_SMULWT_CC: "SMULWT.CC", 8176 arm_SMULWT_MI: "SMULWT.MI", 8177 arm_SMULWT_PL: "SMULWT.PL", 8178 arm_SMULWT_VS: "SMULWT.VS", 8179 arm_SMULWT_VC: "SMULWT.VC", 8180 arm_SMULWT_HI: "SMULWT.HI", 8181 arm_SMULWT_LS: "SMULWT.LS", 8182 arm_SMULWT_GE: "SMULWT.GE", 8183 arm_SMULWT_LT: "SMULWT.LT", 8184 arm_SMULWT_GT: "SMULWT.GT", 8185 arm_SMULWT_LE: "SMULWT.LE", 8186 arm_SMULWT: "SMULWT", 8187 arm_SMULWT_ZZ: "SMULWT.ZZ", 8188 arm_SMUSD_EQ: "SMUSD.EQ", 8189 arm_SMUSD_NE: "SMUSD.NE", 8190 arm_SMUSD_CS: "SMUSD.CS", 8191 arm_SMUSD_CC: "SMUSD.CC", 8192 arm_SMUSD_MI: "SMUSD.MI", 8193 arm_SMUSD_PL: "SMUSD.PL", 8194 arm_SMUSD_VS: "SMUSD.VS", 8195 arm_SMUSD_VC: "SMUSD.VC", 8196 arm_SMUSD_HI: "SMUSD.HI", 8197 arm_SMUSD_LS: "SMUSD.LS", 8198 arm_SMUSD_GE: "SMUSD.GE", 8199 arm_SMUSD_LT: "SMUSD.LT", 8200 arm_SMUSD_GT: "SMUSD.GT", 8201 arm_SMUSD_LE: "SMUSD.LE", 8202 arm_SMUSD: "SMUSD", 8203 arm_SMUSD_ZZ: "SMUSD.ZZ", 8204 arm_SMUSD_X_EQ: "SMUSD.X.EQ", 8205 arm_SMUSD_X_NE: "SMUSD.X.NE", 8206 arm_SMUSD_X_CS: "SMUSD.X.CS", 8207 arm_SMUSD_X_CC: "SMUSD.X.CC", 8208 arm_SMUSD_X_MI: "SMUSD.X.MI", 8209 arm_SMUSD_X_PL: "SMUSD.X.PL", 8210 arm_SMUSD_X_VS: "SMUSD.X.VS", 8211 arm_SMUSD_X_VC: "SMUSD.X.VC", 8212 arm_SMUSD_X_HI: "SMUSD.X.HI", 8213 arm_SMUSD_X_LS: "SMUSD.X.LS", 8214 arm_SMUSD_X_GE: "SMUSD.X.GE", 8215 arm_SMUSD_X_LT: "SMUSD.X.LT", 8216 arm_SMUSD_X_GT: "SMUSD.X.GT", 8217 arm_SMUSD_X_LE: "SMUSD.X.LE", 8218 arm_SMUSD_X: "SMUSD.X", 8219 arm_SMUSD_X_ZZ: "SMUSD.X.ZZ", 8220 arm_SSAT_EQ: "SSAT.EQ", 8221 arm_SSAT_NE: "SSAT.NE", 8222 arm_SSAT_CS: "SSAT.CS", 8223 arm_SSAT_CC: "SSAT.CC", 8224 arm_SSAT_MI: "SSAT.MI", 8225 arm_SSAT_PL: "SSAT.PL", 8226 arm_SSAT_VS: "SSAT.VS", 8227 arm_SSAT_VC: "SSAT.VC", 8228 arm_SSAT_HI: "SSAT.HI", 8229 arm_SSAT_LS: "SSAT.LS", 8230 arm_SSAT_GE: "SSAT.GE", 8231 arm_SSAT_LT: "SSAT.LT", 8232 arm_SSAT_GT: "SSAT.GT", 8233 arm_SSAT_LE: "SSAT.LE", 8234 arm_SSAT: "SSAT", 8235 arm_SSAT_ZZ: "SSAT.ZZ", 8236 arm_SSAT16_EQ: "SSAT16.EQ", 8237 arm_SSAT16_NE: "SSAT16.NE", 8238 arm_SSAT16_CS: "SSAT16.CS", 8239 arm_SSAT16_CC: "SSAT16.CC", 8240 arm_SSAT16_MI: "SSAT16.MI", 8241 arm_SSAT16_PL: "SSAT16.PL", 8242 arm_SSAT16_VS: "SSAT16.VS", 8243 arm_SSAT16_VC: "SSAT16.VC", 8244 arm_SSAT16_HI: "SSAT16.HI", 8245 arm_SSAT16_LS: "SSAT16.LS", 8246 arm_SSAT16_GE: "SSAT16.GE", 8247 arm_SSAT16_LT: "SSAT16.LT", 8248 arm_SSAT16_GT: "SSAT16.GT", 8249 arm_SSAT16_LE: "SSAT16.LE", 8250 arm_SSAT16: "SSAT16", 8251 arm_SSAT16_ZZ: "SSAT16.ZZ", 8252 arm_SSAX_EQ: "SSAX.EQ", 8253 arm_SSAX_NE: "SSAX.NE", 8254 arm_SSAX_CS: "SSAX.CS", 8255 arm_SSAX_CC: "SSAX.CC", 8256 arm_SSAX_MI: "SSAX.MI", 8257 arm_SSAX_PL: "SSAX.PL", 8258 arm_SSAX_VS: "SSAX.VS", 8259 arm_SSAX_VC: "SSAX.VC", 8260 arm_SSAX_HI: "SSAX.HI", 8261 arm_SSAX_LS: "SSAX.LS", 8262 arm_SSAX_GE: "SSAX.GE", 8263 arm_SSAX_LT: "SSAX.LT", 8264 arm_SSAX_GT: "SSAX.GT", 8265 arm_SSAX_LE: "SSAX.LE", 8266 arm_SSAX: "SSAX", 8267 arm_SSAX_ZZ: "SSAX.ZZ", 8268 arm_SSUB16_EQ: "SSUB16.EQ", 8269 arm_SSUB16_NE: "SSUB16.NE", 8270 arm_SSUB16_CS: "SSUB16.CS", 8271 arm_SSUB16_CC: "SSUB16.CC", 8272 arm_SSUB16_MI: "SSUB16.MI", 8273 arm_SSUB16_PL: "SSUB16.PL", 8274 arm_SSUB16_VS: "SSUB16.VS", 8275 arm_SSUB16_VC: "SSUB16.VC", 8276 arm_SSUB16_HI: "SSUB16.HI", 8277 arm_SSUB16_LS: "SSUB16.LS", 8278 arm_SSUB16_GE: "SSUB16.GE", 8279 arm_SSUB16_LT: "SSUB16.LT", 8280 arm_SSUB16_GT: "SSUB16.GT", 8281 arm_SSUB16_LE: "SSUB16.LE", 8282 arm_SSUB16: "SSUB16", 8283 arm_SSUB16_ZZ: "SSUB16.ZZ", 8284 arm_SSUB8_EQ: "SSUB8.EQ", 8285 arm_SSUB8_NE: "SSUB8.NE", 8286 arm_SSUB8_CS: "SSUB8.CS", 8287 arm_SSUB8_CC: "SSUB8.CC", 8288 arm_SSUB8_MI: "SSUB8.MI", 8289 arm_SSUB8_PL: "SSUB8.PL", 8290 arm_SSUB8_VS: "SSUB8.VS", 8291 arm_SSUB8_VC: "SSUB8.VC", 8292 arm_SSUB8_HI: "SSUB8.HI", 8293 arm_SSUB8_LS: "SSUB8.LS", 8294 arm_SSUB8_GE: "SSUB8.GE", 8295 arm_SSUB8_LT: "SSUB8.LT", 8296 arm_SSUB8_GT: "SSUB8.GT", 8297 arm_SSUB8_LE: "SSUB8.LE", 8298 arm_SSUB8: "SSUB8", 8299 arm_SSUB8_ZZ: "SSUB8.ZZ", 8300 arm_STM_EQ: "STM.EQ", 8301 arm_STM_NE: "STM.NE", 8302 arm_STM_CS: "STM.CS", 8303 arm_STM_CC: "STM.CC", 8304 arm_STM_MI: "STM.MI", 8305 arm_STM_PL: "STM.PL", 8306 arm_STM_VS: "STM.VS", 8307 arm_STM_VC: "STM.VC", 8308 arm_STM_HI: "STM.HI", 8309 arm_STM_LS: "STM.LS", 8310 arm_STM_GE: "STM.GE", 8311 arm_STM_LT: "STM.LT", 8312 arm_STM_GT: "STM.GT", 8313 arm_STM_LE: "STM.LE", 8314 arm_STM: "STM", 8315 arm_STM_ZZ: "STM.ZZ", 8316 arm_STMDA_EQ: "STMDA.EQ", 8317 arm_STMDA_NE: "STMDA.NE", 8318 arm_STMDA_CS: "STMDA.CS", 8319 arm_STMDA_CC: "STMDA.CC", 8320 arm_STMDA_MI: "STMDA.MI", 8321 arm_STMDA_PL: "STMDA.PL", 8322 arm_STMDA_VS: "STMDA.VS", 8323 arm_STMDA_VC: "STMDA.VC", 8324 arm_STMDA_HI: "STMDA.HI", 8325 arm_STMDA_LS: "STMDA.LS", 8326 arm_STMDA_GE: "STMDA.GE", 8327 arm_STMDA_LT: "STMDA.LT", 8328 arm_STMDA_GT: "STMDA.GT", 8329 arm_STMDA_LE: "STMDA.LE", 8330 arm_STMDA: "STMDA", 8331 arm_STMDA_ZZ: "STMDA.ZZ", 8332 arm_STMDB_EQ: "STMDB.EQ", 8333 arm_STMDB_NE: "STMDB.NE", 8334 arm_STMDB_CS: "STMDB.CS", 8335 arm_STMDB_CC: "STMDB.CC", 8336 arm_STMDB_MI: "STMDB.MI", 8337 arm_STMDB_PL: "STMDB.PL", 8338 arm_STMDB_VS: "STMDB.VS", 8339 arm_STMDB_VC: "STMDB.VC", 8340 arm_STMDB_HI: "STMDB.HI", 8341 arm_STMDB_LS: "STMDB.LS", 8342 arm_STMDB_GE: "STMDB.GE", 8343 arm_STMDB_LT: "STMDB.LT", 8344 arm_STMDB_GT: "STMDB.GT", 8345 arm_STMDB_LE: "STMDB.LE", 8346 arm_STMDB: "STMDB", 8347 arm_STMDB_ZZ: "STMDB.ZZ", 8348 arm_STMIB_EQ: "STMIB.EQ", 8349 arm_STMIB_NE: "STMIB.NE", 8350 arm_STMIB_CS: "STMIB.CS", 8351 arm_STMIB_CC: "STMIB.CC", 8352 arm_STMIB_MI: "STMIB.MI", 8353 arm_STMIB_PL: "STMIB.PL", 8354 arm_STMIB_VS: "STMIB.VS", 8355 arm_STMIB_VC: "STMIB.VC", 8356 arm_STMIB_HI: "STMIB.HI", 8357 arm_STMIB_LS: "STMIB.LS", 8358 arm_STMIB_GE: "STMIB.GE", 8359 arm_STMIB_LT: "STMIB.LT", 8360 arm_STMIB_GT: "STMIB.GT", 8361 arm_STMIB_LE: "STMIB.LE", 8362 arm_STMIB: "STMIB", 8363 arm_STMIB_ZZ: "STMIB.ZZ", 8364 arm_STR_EQ: "STR.EQ", 8365 arm_STR_NE: "STR.NE", 8366 arm_STR_CS: "STR.CS", 8367 arm_STR_CC: "STR.CC", 8368 arm_STR_MI: "STR.MI", 8369 arm_STR_PL: "STR.PL", 8370 arm_STR_VS: "STR.VS", 8371 arm_STR_VC: "STR.VC", 8372 arm_STR_HI: "STR.HI", 8373 arm_STR_LS: "STR.LS", 8374 arm_STR_GE: "STR.GE", 8375 arm_STR_LT: "STR.LT", 8376 arm_STR_GT: "STR.GT", 8377 arm_STR_LE: "STR.LE", 8378 arm_STR: "STR", 8379 arm_STR_ZZ: "STR.ZZ", 8380 arm_STRB_EQ: "STRB.EQ", 8381 arm_STRB_NE: "STRB.NE", 8382 arm_STRB_CS: "STRB.CS", 8383 arm_STRB_CC: "STRB.CC", 8384 arm_STRB_MI: "STRB.MI", 8385 arm_STRB_PL: "STRB.PL", 8386 arm_STRB_VS: "STRB.VS", 8387 arm_STRB_VC: "STRB.VC", 8388 arm_STRB_HI: "STRB.HI", 8389 arm_STRB_LS: "STRB.LS", 8390 arm_STRB_GE: "STRB.GE", 8391 arm_STRB_LT: "STRB.LT", 8392 arm_STRB_GT: "STRB.GT", 8393 arm_STRB_LE: "STRB.LE", 8394 arm_STRB: "STRB", 8395 arm_STRB_ZZ: "STRB.ZZ", 8396 arm_STRBT_EQ: "STRBT.EQ", 8397 arm_STRBT_NE: "STRBT.NE", 8398 arm_STRBT_CS: "STRBT.CS", 8399 arm_STRBT_CC: "STRBT.CC", 8400 arm_STRBT_MI: "STRBT.MI", 8401 arm_STRBT_PL: "STRBT.PL", 8402 arm_STRBT_VS: "STRBT.VS", 8403 arm_STRBT_VC: "STRBT.VC", 8404 arm_STRBT_HI: "STRBT.HI", 8405 arm_STRBT_LS: "STRBT.LS", 8406 arm_STRBT_GE: "STRBT.GE", 8407 arm_STRBT_LT: "STRBT.LT", 8408 arm_STRBT_GT: "STRBT.GT", 8409 arm_STRBT_LE: "STRBT.LE", 8410 arm_STRBT: "STRBT", 8411 arm_STRBT_ZZ: "STRBT.ZZ", 8412 arm_STRD_EQ: "STRD.EQ", 8413 arm_STRD_NE: "STRD.NE", 8414 arm_STRD_CS: "STRD.CS", 8415 arm_STRD_CC: "STRD.CC", 8416 arm_STRD_MI: "STRD.MI", 8417 arm_STRD_PL: "STRD.PL", 8418 arm_STRD_VS: "STRD.VS", 8419 arm_STRD_VC: "STRD.VC", 8420 arm_STRD_HI: "STRD.HI", 8421 arm_STRD_LS: "STRD.LS", 8422 arm_STRD_GE: "STRD.GE", 8423 arm_STRD_LT: "STRD.LT", 8424 arm_STRD_GT: "STRD.GT", 8425 arm_STRD_LE: "STRD.LE", 8426 arm_STRD: "STRD", 8427 arm_STRD_ZZ: "STRD.ZZ", 8428 arm_STREX_EQ: "STREX.EQ", 8429 arm_STREX_NE: "STREX.NE", 8430 arm_STREX_CS: "STREX.CS", 8431 arm_STREX_CC: "STREX.CC", 8432 arm_STREX_MI: "STREX.MI", 8433 arm_STREX_PL: "STREX.PL", 8434 arm_STREX_VS: "STREX.VS", 8435 arm_STREX_VC: "STREX.VC", 8436 arm_STREX_HI: "STREX.HI", 8437 arm_STREX_LS: "STREX.LS", 8438 arm_STREX_GE: "STREX.GE", 8439 arm_STREX_LT: "STREX.LT", 8440 arm_STREX_GT: "STREX.GT", 8441 arm_STREX_LE: "STREX.LE", 8442 arm_STREX: "STREX", 8443 arm_STREX_ZZ: "STREX.ZZ", 8444 arm_STREXB_EQ: "STREXB.EQ", 8445 arm_STREXB_NE: "STREXB.NE", 8446 arm_STREXB_CS: "STREXB.CS", 8447 arm_STREXB_CC: "STREXB.CC", 8448 arm_STREXB_MI: "STREXB.MI", 8449 arm_STREXB_PL: "STREXB.PL", 8450 arm_STREXB_VS: "STREXB.VS", 8451 arm_STREXB_VC: "STREXB.VC", 8452 arm_STREXB_HI: "STREXB.HI", 8453 arm_STREXB_LS: "STREXB.LS", 8454 arm_STREXB_GE: "STREXB.GE", 8455 arm_STREXB_LT: "STREXB.LT", 8456 arm_STREXB_GT: "STREXB.GT", 8457 arm_STREXB_LE: "STREXB.LE", 8458 arm_STREXB: "STREXB", 8459 arm_STREXB_ZZ: "STREXB.ZZ", 8460 arm_STREXD_EQ: "STREXD.EQ", 8461 arm_STREXD_NE: "STREXD.NE", 8462 arm_STREXD_CS: "STREXD.CS", 8463 arm_STREXD_CC: "STREXD.CC", 8464 arm_STREXD_MI: "STREXD.MI", 8465 arm_STREXD_PL: "STREXD.PL", 8466 arm_STREXD_VS: "STREXD.VS", 8467 arm_STREXD_VC: "STREXD.VC", 8468 arm_STREXD_HI: "STREXD.HI", 8469 arm_STREXD_LS: "STREXD.LS", 8470 arm_STREXD_GE: "STREXD.GE", 8471 arm_STREXD_LT: "STREXD.LT", 8472 arm_STREXD_GT: "STREXD.GT", 8473 arm_STREXD_LE: "STREXD.LE", 8474 arm_STREXD: "STREXD", 8475 arm_STREXD_ZZ: "STREXD.ZZ", 8476 arm_STREXH_EQ: "STREXH.EQ", 8477 arm_STREXH_NE: "STREXH.NE", 8478 arm_STREXH_CS: "STREXH.CS", 8479 arm_STREXH_CC: "STREXH.CC", 8480 arm_STREXH_MI: "STREXH.MI", 8481 arm_STREXH_PL: "STREXH.PL", 8482 arm_STREXH_VS: "STREXH.VS", 8483 arm_STREXH_VC: "STREXH.VC", 8484 arm_STREXH_HI: "STREXH.HI", 8485 arm_STREXH_LS: "STREXH.LS", 8486 arm_STREXH_GE: "STREXH.GE", 8487 arm_STREXH_LT: "STREXH.LT", 8488 arm_STREXH_GT: "STREXH.GT", 8489 arm_STREXH_LE: "STREXH.LE", 8490 arm_STREXH: "STREXH", 8491 arm_STREXH_ZZ: "STREXH.ZZ", 8492 arm_STRH_EQ: "STRH.EQ", 8493 arm_STRH_NE: "STRH.NE", 8494 arm_STRH_CS: "STRH.CS", 8495 arm_STRH_CC: "STRH.CC", 8496 arm_STRH_MI: "STRH.MI", 8497 arm_STRH_PL: "STRH.PL", 8498 arm_STRH_VS: "STRH.VS", 8499 arm_STRH_VC: "STRH.VC", 8500 arm_STRH_HI: "STRH.HI", 8501 arm_STRH_LS: "STRH.LS", 8502 arm_STRH_GE: "STRH.GE", 8503 arm_STRH_LT: "STRH.LT", 8504 arm_STRH_GT: "STRH.GT", 8505 arm_STRH_LE: "STRH.LE", 8506 arm_STRH: "STRH", 8507 arm_STRH_ZZ: "STRH.ZZ", 8508 arm_STRHT_EQ: "STRHT.EQ", 8509 arm_STRHT_NE: "STRHT.NE", 8510 arm_STRHT_CS: "STRHT.CS", 8511 arm_STRHT_CC: "STRHT.CC", 8512 arm_STRHT_MI: "STRHT.MI", 8513 arm_STRHT_PL: "STRHT.PL", 8514 arm_STRHT_VS: "STRHT.VS", 8515 arm_STRHT_VC: "STRHT.VC", 8516 arm_STRHT_HI: "STRHT.HI", 8517 arm_STRHT_LS: "STRHT.LS", 8518 arm_STRHT_GE: "STRHT.GE", 8519 arm_STRHT_LT: "STRHT.LT", 8520 arm_STRHT_GT: "STRHT.GT", 8521 arm_STRHT_LE: "STRHT.LE", 8522 arm_STRHT: "STRHT", 8523 arm_STRHT_ZZ: "STRHT.ZZ", 8524 arm_STRT_EQ: "STRT.EQ", 8525 arm_STRT_NE: "STRT.NE", 8526 arm_STRT_CS: "STRT.CS", 8527 arm_STRT_CC: "STRT.CC", 8528 arm_STRT_MI: "STRT.MI", 8529 arm_STRT_PL: "STRT.PL", 8530 arm_STRT_VS: "STRT.VS", 8531 arm_STRT_VC: "STRT.VC", 8532 arm_STRT_HI: "STRT.HI", 8533 arm_STRT_LS: "STRT.LS", 8534 arm_STRT_GE: "STRT.GE", 8535 arm_STRT_LT: "STRT.LT", 8536 arm_STRT_GT: "STRT.GT", 8537 arm_STRT_LE: "STRT.LE", 8538 arm_STRT: "STRT", 8539 arm_STRT_ZZ: "STRT.ZZ", 8540 arm_SUB_EQ: "SUB.EQ", 8541 arm_SUB_NE: "SUB.NE", 8542 arm_SUB_CS: "SUB.CS", 8543 arm_SUB_CC: "SUB.CC", 8544 arm_SUB_MI: "SUB.MI", 8545 arm_SUB_PL: "SUB.PL", 8546 arm_SUB_VS: "SUB.VS", 8547 arm_SUB_VC: "SUB.VC", 8548 arm_SUB_HI: "SUB.HI", 8549 arm_SUB_LS: "SUB.LS", 8550 arm_SUB_GE: "SUB.GE", 8551 arm_SUB_LT: "SUB.LT", 8552 arm_SUB_GT: "SUB.GT", 8553 arm_SUB_LE: "SUB.LE", 8554 arm_SUB: "SUB", 8555 arm_SUB_ZZ: "SUB.ZZ", 8556 arm_SUB_S_EQ: "SUB.S.EQ", 8557 arm_SUB_S_NE: "SUB.S.NE", 8558 arm_SUB_S_CS: "SUB.S.CS", 8559 arm_SUB_S_CC: "SUB.S.CC", 8560 arm_SUB_S_MI: "SUB.S.MI", 8561 arm_SUB_S_PL: "SUB.S.PL", 8562 arm_SUB_S_VS: "SUB.S.VS", 8563 arm_SUB_S_VC: "SUB.S.VC", 8564 arm_SUB_S_HI: "SUB.S.HI", 8565 arm_SUB_S_LS: "SUB.S.LS", 8566 arm_SUB_S_GE: "SUB.S.GE", 8567 arm_SUB_S_LT: "SUB.S.LT", 8568 arm_SUB_S_GT: "SUB.S.GT", 8569 arm_SUB_S_LE: "SUB.S.LE", 8570 arm_SUB_S: "SUB.S", 8571 arm_SUB_S_ZZ: "SUB.S.ZZ", 8572 arm_SVC_EQ: "SVC.EQ", 8573 arm_SVC_NE: "SVC.NE", 8574 arm_SVC_CS: "SVC.CS", 8575 arm_SVC_CC: "SVC.CC", 8576 arm_SVC_MI: "SVC.MI", 8577 arm_SVC_PL: "SVC.PL", 8578 arm_SVC_VS: "SVC.VS", 8579 arm_SVC_VC: "SVC.VC", 8580 arm_SVC_HI: "SVC.HI", 8581 arm_SVC_LS: "SVC.LS", 8582 arm_SVC_GE: "SVC.GE", 8583 arm_SVC_LT: "SVC.LT", 8584 arm_SVC_GT: "SVC.GT", 8585 arm_SVC_LE: "SVC.LE", 8586 arm_SVC: "SVC", 8587 arm_SVC_ZZ: "SVC.ZZ", 8588 arm_SWP_EQ: "SWP.EQ", 8589 arm_SWP_NE: "SWP.NE", 8590 arm_SWP_CS: "SWP.CS", 8591 arm_SWP_CC: "SWP.CC", 8592 arm_SWP_MI: "SWP.MI", 8593 arm_SWP_PL: "SWP.PL", 8594 arm_SWP_VS: "SWP.VS", 8595 arm_SWP_VC: "SWP.VC", 8596 arm_SWP_HI: "SWP.HI", 8597 arm_SWP_LS: "SWP.LS", 8598 arm_SWP_GE: "SWP.GE", 8599 arm_SWP_LT: "SWP.LT", 8600 arm_SWP_GT: "SWP.GT", 8601 arm_SWP_LE: "SWP.LE", 8602 arm_SWP: "SWP", 8603 arm_SWP_ZZ: "SWP.ZZ", 8604 arm_SWP_B_EQ: "SWP.B.EQ", 8605 arm_SWP_B_NE: "SWP.B.NE", 8606 arm_SWP_B_CS: "SWP.B.CS", 8607 arm_SWP_B_CC: "SWP.B.CC", 8608 arm_SWP_B_MI: "SWP.B.MI", 8609 arm_SWP_B_PL: "SWP.B.PL", 8610 arm_SWP_B_VS: "SWP.B.VS", 8611 arm_SWP_B_VC: "SWP.B.VC", 8612 arm_SWP_B_HI: "SWP.B.HI", 8613 arm_SWP_B_LS: "SWP.B.LS", 8614 arm_SWP_B_GE: "SWP.B.GE", 8615 arm_SWP_B_LT: "SWP.B.LT", 8616 arm_SWP_B_GT: "SWP.B.GT", 8617 arm_SWP_B_LE: "SWP.B.LE", 8618 arm_SWP_B: "SWP.B", 8619 arm_SWP_B_ZZ: "SWP.B.ZZ", 8620 arm_SXTAB_EQ: "SXTAB.EQ", 8621 arm_SXTAB_NE: "SXTAB.NE", 8622 arm_SXTAB_CS: "SXTAB.CS", 8623 arm_SXTAB_CC: "SXTAB.CC", 8624 arm_SXTAB_MI: "SXTAB.MI", 8625 arm_SXTAB_PL: "SXTAB.PL", 8626 arm_SXTAB_VS: "SXTAB.VS", 8627 arm_SXTAB_VC: "SXTAB.VC", 8628 arm_SXTAB_HI: "SXTAB.HI", 8629 arm_SXTAB_LS: "SXTAB.LS", 8630 arm_SXTAB_GE: "SXTAB.GE", 8631 arm_SXTAB_LT: "SXTAB.LT", 8632 arm_SXTAB_GT: "SXTAB.GT", 8633 arm_SXTAB_LE: "SXTAB.LE", 8634 arm_SXTAB: "SXTAB", 8635 arm_SXTAB_ZZ: "SXTAB.ZZ", 8636 arm_SXTAB16_EQ: "SXTAB16.EQ", 8637 arm_SXTAB16_NE: "SXTAB16.NE", 8638 arm_SXTAB16_CS: "SXTAB16.CS", 8639 arm_SXTAB16_CC: "SXTAB16.CC", 8640 arm_SXTAB16_MI: "SXTAB16.MI", 8641 arm_SXTAB16_PL: "SXTAB16.PL", 8642 arm_SXTAB16_VS: "SXTAB16.VS", 8643 arm_SXTAB16_VC: "SXTAB16.VC", 8644 arm_SXTAB16_HI: "SXTAB16.HI", 8645 arm_SXTAB16_LS: "SXTAB16.LS", 8646 arm_SXTAB16_GE: "SXTAB16.GE", 8647 arm_SXTAB16_LT: "SXTAB16.LT", 8648 arm_SXTAB16_GT: "SXTAB16.GT", 8649 arm_SXTAB16_LE: "SXTAB16.LE", 8650 arm_SXTAB16: "SXTAB16", 8651 arm_SXTAB16_ZZ: "SXTAB16.ZZ", 8652 arm_SXTAH_EQ: "SXTAH.EQ", 8653 arm_SXTAH_NE: "SXTAH.NE", 8654 arm_SXTAH_CS: "SXTAH.CS", 8655 arm_SXTAH_CC: "SXTAH.CC", 8656 arm_SXTAH_MI: "SXTAH.MI", 8657 arm_SXTAH_PL: "SXTAH.PL", 8658 arm_SXTAH_VS: "SXTAH.VS", 8659 arm_SXTAH_VC: "SXTAH.VC", 8660 arm_SXTAH_HI: "SXTAH.HI", 8661 arm_SXTAH_LS: "SXTAH.LS", 8662 arm_SXTAH_GE: "SXTAH.GE", 8663 arm_SXTAH_LT: "SXTAH.LT", 8664 arm_SXTAH_GT: "SXTAH.GT", 8665 arm_SXTAH_LE: "SXTAH.LE", 8666 arm_SXTAH: "SXTAH", 8667 arm_SXTAH_ZZ: "SXTAH.ZZ", 8668 arm_SXTB_EQ: "SXTB.EQ", 8669 arm_SXTB_NE: "SXTB.NE", 8670 arm_SXTB_CS: "SXTB.CS", 8671 arm_SXTB_CC: "SXTB.CC", 8672 arm_SXTB_MI: "SXTB.MI", 8673 arm_SXTB_PL: "SXTB.PL", 8674 arm_SXTB_VS: "SXTB.VS", 8675 arm_SXTB_VC: "SXTB.VC", 8676 arm_SXTB_HI: "SXTB.HI", 8677 arm_SXTB_LS: "SXTB.LS", 8678 arm_SXTB_GE: "SXTB.GE", 8679 arm_SXTB_LT: "SXTB.LT", 8680 arm_SXTB_GT: "SXTB.GT", 8681 arm_SXTB_LE: "SXTB.LE", 8682 arm_SXTB: "SXTB", 8683 arm_SXTB_ZZ: "SXTB.ZZ", 8684 arm_SXTB16_EQ: "SXTB16.EQ", 8685 arm_SXTB16_NE: "SXTB16.NE", 8686 arm_SXTB16_CS: "SXTB16.CS", 8687 arm_SXTB16_CC: "SXTB16.CC", 8688 arm_SXTB16_MI: "SXTB16.MI", 8689 arm_SXTB16_PL: "SXTB16.PL", 8690 arm_SXTB16_VS: "SXTB16.VS", 8691 arm_SXTB16_VC: "SXTB16.VC", 8692 arm_SXTB16_HI: "SXTB16.HI", 8693 arm_SXTB16_LS: "SXTB16.LS", 8694 arm_SXTB16_GE: "SXTB16.GE", 8695 arm_SXTB16_LT: "SXTB16.LT", 8696 arm_SXTB16_GT: "SXTB16.GT", 8697 arm_SXTB16_LE: "SXTB16.LE", 8698 arm_SXTB16: "SXTB16", 8699 arm_SXTB16_ZZ: "SXTB16.ZZ", 8700 arm_SXTH_EQ: "SXTH.EQ", 8701 arm_SXTH_NE: "SXTH.NE", 8702 arm_SXTH_CS: "SXTH.CS", 8703 arm_SXTH_CC: "SXTH.CC", 8704 arm_SXTH_MI: "SXTH.MI", 8705 arm_SXTH_PL: "SXTH.PL", 8706 arm_SXTH_VS: "SXTH.VS", 8707 arm_SXTH_VC: "SXTH.VC", 8708 arm_SXTH_HI: "SXTH.HI", 8709 arm_SXTH_LS: "SXTH.LS", 8710 arm_SXTH_GE: "SXTH.GE", 8711 arm_SXTH_LT: "SXTH.LT", 8712 arm_SXTH_GT: "SXTH.GT", 8713 arm_SXTH_LE: "SXTH.LE", 8714 arm_SXTH: "SXTH", 8715 arm_SXTH_ZZ: "SXTH.ZZ", 8716 arm_TEQ_EQ: "TEQ.EQ", 8717 arm_TEQ_NE: "TEQ.NE", 8718 arm_TEQ_CS: "TEQ.CS", 8719 arm_TEQ_CC: "TEQ.CC", 8720 arm_TEQ_MI: "TEQ.MI", 8721 arm_TEQ_PL: "TEQ.PL", 8722 arm_TEQ_VS: "TEQ.VS", 8723 arm_TEQ_VC: "TEQ.VC", 8724 arm_TEQ_HI: "TEQ.HI", 8725 arm_TEQ_LS: "TEQ.LS", 8726 arm_TEQ_GE: "TEQ.GE", 8727 arm_TEQ_LT: "TEQ.LT", 8728 arm_TEQ_GT: "TEQ.GT", 8729 arm_TEQ_LE: "TEQ.LE", 8730 arm_TEQ: "TEQ", 8731 arm_TEQ_ZZ: "TEQ.ZZ", 8732 arm_TST_EQ: "TST.EQ", 8733 arm_TST_NE: "TST.NE", 8734 arm_TST_CS: "TST.CS", 8735 arm_TST_CC: "TST.CC", 8736 arm_TST_MI: "TST.MI", 8737 arm_TST_PL: "TST.PL", 8738 arm_TST_VS: "TST.VS", 8739 arm_TST_VC: "TST.VC", 8740 arm_TST_HI: "TST.HI", 8741 arm_TST_LS: "TST.LS", 8742 arm_TST_GE: "TST.GE", 8743 arm_TST_LT: "TST.LT", 8744 arm_TST_GT: "TST.GT", 8745 arm_TST_LE: "TST.LE", 8746 arm_TST: "TST", 8747 arm_TST_ZZ: "TST.ZZ", 8748 arm_UADD16_EQ: "UADD16.EQ", 8749 arm_UADD16_NE: "UADD16.NE", 8750 arm_UADD16_CS: "UADD16.CS", 8751 arm_UADD16_CC: "UADD16.CC", 8752 arm_UADD16_MI: "UADD16.MI", 8753 arm_UADD16_PL: "UADD16.PL", 8754 arm_UADD16_VS: "UADD16.VS", 8755 arm_UADD16_VC: "UADD16.VC", 8756 arm_UADD16_HI: "UADD16.HI", 8757 arm_UADD16_LS: "UADD16.LS", 8758 arm_UADD16_GE: "UADD16.GE", 8759 arm_UADD16_LT: "UADD16.LT", 8760 arm_UADD16_GT: "UADD16.GT", 8761 arm_UADD16_LE: "UADD16.LE", 8762 arm_UADD16: "UADD16", 8763 arm_UADD16_ZZ: "UADD16.ZZ", 8764 arm_UADD8_EQ: "UADD8.EQ", 8765 arm_UADD8_NE: "UADD8.NE", 8766 arm_UADD8_CS: "UADD8.CS", 8767 arm_UADD8_CC: "UADD8.CC", 8768 arm_UADD8_MI: "UADD8.MI", 8769 arm_UADD8_PL: "UADD8.PL", 8770 arm_UADD8_VS: "UADD8.VS", 8771 arm_UADD8_VC: "UADD8.VC", 8772 arm_UADD8_HI: "UADD8.HI", 8773 arm_UADD8_LS: "UADD8.LS", 8774 arm_UADD8_GE: "UADD8.GE", 8775 arm_UADD8_LT: "UADD8.LT", 8776 arm_UADD8_GT: "UADD8.GT", 8777 arm_UADD8_LE: "UADD8.LE", 8778 arm_UADD8: "UADD8", 8779 arm_UADD8_ZZ: "UADD8.ZZ", 8780 arm_UASX_EQ: "UASX.EQ", 8781 arm_UASX_NE: "UASX.NE", 8782 arm_UASX_CS: "UASX.CS", 8783 arm_UASX_CC: "UASX.CC", 8784 arm_UASX_MI: "UASX.MI", 8785 arm_UASX_PL: "UASX.PL", 8786 arm_UASX_VS: "UASX.VS", 8787 arm_UASX_VC: "UASX.VC", 8788 arm_UASX_HI: "UASX.HI", 8789 arm_UASX_LS: "UASX.LS", 8790 arm_UASX_GE: "UASX.GE", 8791 arm_UASX_LT: "UASX.LT", 8792 arm_UASX_GT: "UASX.GT", 8793 arm_UASX_LE: "UASX.LE", 8794 arm_UASX: "UASX", 8795 arm_UASX_ZZ: "UASX.ZZ", 8796 arm_UBFX_EQ: "UBFX.EQ", 8797 arm_UBFX_NE: "UBFX.NE", 8798 arm_UBFX_CS: "UBFX.CS", 8799 arm_UBFX_CC: "UBFX.CC", 8800 arm_UBFX_MI: "UBFX.MI", 8801 arm_UBFX_PL: "UBFX.PL", 8802 arm_UBFX_VS: "UBFX.VS", 8803 arm_UBFX_VC: "UBFX.VC", 8804 arm_UBFX_HI: "UBFX.HI", 8805 arm_UBFX_LS: "UBFX.LS", 8806 arm_UBFX_GE: "UBFX.GE", 8807 arm_UBFX_LT: "UBFX.LT", 8808 arm_UBFX_GT: "UBFX.GT", 8809 arm_UBFX_LE: "UBFX.LE", 8810 arm_UBFX: "UBFX", 8811 arm_UBFX_ZZ: "UBFX.ZZ", 8812 arm_UHADD16_EQ: "UHADD16.EQ", 8813 arm_UHADD16_NE: "UHADD16.NE", 8814 arm_UHADD16_CS: "UHADD16.CS", 8815 arm_UHADD16_CC: "UHADD16.CC", 8816 arm_UHADD16_MI: "UHADD16.MI", 8817 arm_UHADD16_PL: "UHADD16.PL", 8818 arm_UHADD16_VS: "UHADD16.VS", 8819 arm_UHADD16_VC: "UHADD16.VC", 8820 arm_UHADD16_HI: "UHADD16.HI", 8821 arm_UHADD16_LS: "UHADD16.LS", 8822 arm_UHADD16_GE: "UHADD16.GE", 8823 arm_UHADD16_LT: "UHADD16.LT", 8824 arm_UHADD16_GT: "UHADD16.GT", 8825 arm_UHADD16_LE: "UHADD16.LE", 8826 arm_UHADD16: "UHADD16", 8827 arm_UHADD16_ZZ: "UHADD16.ZZ", 8828 arm_UHADD8_EQ: "UHADD8.EQ", 8829 arm_UHADD8_NE: "UHADD8.NE", 8830 arm_UHADD8_CS: "UHADD8.CS", 8831 arm_UHADD8_CC: "UHADD8.CC", 8832 arm_UHADD8_MI: "UHADD8.MI", 8833 arm_UHADD8_PL: "UHADD8.PL", 8834 arm_UHADD8_VS: "UHADD8.VS", 8835 arm_UHADD8_VC: "UHADD8.VC", 8836 arm_UHADD8_HI: "UHADD8.HI", 8837 arm_UHADD8_LS: "UHADD8.LS", 8838 arm_UHADD8_GE: "UHADD8.GE", 8839 arm_UHADD8_LT: "UHADD8.LT", 8840 arm_UHADD8_GT: "UHADD8.GT", 8841 arm_UHADD8_LE: "UHADD8.LE", 8842 arm_UHADD8: "UHADD8", 8843 arm_UHADD8_ZZ: "UHADD8.ZZ", 8844 arm_UHASX_EQ: "UHASX.EQ", 8845 arm_UHASX_NE: "UHASX.NE", 8846 arm_UHASX_CS: "UHASX.CS", 8847 arm_UHASX_CC: "UHASX.CC", 8848 arm_UHASX_MI: "UHASX.MI", 8849 arm_UHASX_PL: "UHASX.PL", 8850 arm_UHASX_VS: "UHASX.VS", 8851 arm_UHASX_VC: "UHASX.VC", 8852 arm_UHASX_HI: "UHASX.HI", 8853 arm_UHASX_LS: "UHASX.LS", 8854 arm_UHASX_GE: "UHASX.GE", 8855 arm_UHASX_LT: "UHASX.LT", 8856 arm_UHASX_GT: "UHASX.GT", 8857 arm_UHASX_LE: "UHASX.LE", 8858 arm_UHASX: "UHASX", 8859 arm_UHASX_ZZ: "UHASX.ZZ", 8860 arm_UHSAX_EQ: "UHSAX.EQ", 8861 arm_UHSAX_NE: "UHSAX.NE", 8862 arm_UHSAX_CS: "UHSAX.CS", 8863 arm_UHSAX_CC: "UHSAX.CC", 8864 arm_UHSAX_MI: "UHSAX.MI", 8865 arm_UHSAX_PL: "UHSAX.PL", 8866 arm_UHSAX_VS: "UHSAX.VS", 8867 arm_UHSAX_VC: "UHSAX.VC", 8868 arm_UHSAX_HI: "UHSAX.HI", 8869 arm_UHSAX_LS: "UHSAX.LS", 8870 arm_UHSAX_GE: "UHSAX.GE", 8871 arm_UHSAX_LT: "UHSAX.LT", 8872 arm_UHSAX_GT: "UHSAX.GT", 8873 arm_UHSAX_LE: "UHSAX.LE", 8874 arm_UHSAX: "UHSAX", 8875 arm_UHSAX_ZZ: "UHSAX.ZZ", 8876 arm_UHSUB16_EQ: "UHSUB16.EQ", 8877 arm_UHSUB16_NE: "UHSUB16.NE", 8878 arm_UHSUB16_CS: "UHSUB16.CS", 8879 arm_UHSUB16_CC: "UHSUB16.CC", 8880 arm_UHSUB16_MI: "UHSUB16.MI", 8881 arm_UHSUB16_PL: "UHSUB16.PL", 8882 arm_UHSUB16_VS: "UHSUB16.VS", 8883 arm_UHSUB16_VC: "UHSUB16.VC", 8884 arm_UHSUB16_HI: "UHSUB16.HI", 8885 arm_UHSUB16_LS: "UHSUB16.LS", 8886 arm_UHSUB16_GE: "UHSUB16.GE", 8887 arm_UHSUB16_LT: "UHSUB16.LT", 8888 arm_UHSUB16_GT: "UHSUB16.GT", 8889 arm_UHSUB16_LE: "UHSUB16.LE", 8890 arm_UHSUB16: "UHSUB16", 8891 arm_UHSUB16_ZZ: "UHSUB16.ZZ", 8892 arm_UHSUB8_EQ: "UHSUB8.EQ", 8893 arm_UHSUB8_NE: "UHSUB8.NE", 8894 arm_UHSUB8_CS: "UHSUB8.CS", 8895 arm_UHSUB8_CC: "UHSUB8.CC", 8896 arm_UHSUB8_MI: "UHSUB8.MI", 8897 arm_UHSUB8_PL: "UHSUB8.PL", 8898 arm_UHSUB8_VS: "UHSUB8.VS", 8899 arm_UHSUB8_VC: "UHSUB8.VC", 8900 arm_UHSUB8_HI: "UHSUB8.HI", 8901 arm_UHSUB8_LS: "UHSUB8.LS", 8902 arm_UHSUB8_GE: "UHSUB8.GE", 8903 arm_UHSUB8_LT: "UHSUB8.LT", 8904 arm_UHSUB8_GT: "UHSUB8.GT", 8905 arm_UHSUB8_LE: "UHSUB8.LE", 8906 arm_UHSUB8: "UHSUB8", 8907 arm_UHSUB8_ZZ: "UHSUB8.ZZ", 8908 arm_UMAAL_EQ: "UMAAL.EQ", 8909 arm_UMAAL_NE: "UMAAL.NE", 8910 arm_UMAAL_CS: "UMAAL.CS", 8911 arm_UMAAL_CC: "UMAAL.CC", 8912 arm_UMAAL_MI: "UMAAL.MI", 8913 arm_UMAAL_PL: "UMAAL.PL", 8914 arm_UMAAL_VS: "UMAAL.VS", 8915 arm_UMAAL_VC: "UMAAL.VC", 8916 arm_UMAAL_HI: "UMAAL.HI", 8917 arm_UMAAL_LS: "UMAAL.LS", 8918 arm_UMAAL_GE: "UMAAL.GE", 8919 arm_UMAAL_LT: "UMAAL.LT", 8920 arm_UMAAL_GT: "UMAAL.GT", 8921 arm_UMAAL_LE: "UMAAL.LE", 8922 arm_UMAAL: "UMAAL", 8923 arm_UMAAL_ZZ: "UMAAL.ZZ", 8924 arm_UMLAL_EQ: "UMLAL.EQ", 8925 arm_UMLAL_NE: "UMLAL.NE", 8926 arm_UMLAL_CS: "UMLAL.CS", 8927 arm_UMLAL_CC: "UMLAL.CC", 8928 arm_UMLAL_MI: "UMLAL.MI", 8929 arm_UMLAL_PL: "UMLAL.PL", 8930 arm_UMLAL_VS: "UMLAL.VS", 8931 arm_UMLAL_VC: "UMLAL.VC", 8932 arm_UMLAL_HI: "UMLAL.HI", 8933 arm_UMLAL_LS: "UMLAL.LS", 8934 arm_UMLAL_GE: "UMLAL.GE", 8935 arm_UMLAL_LT: "UMLAL.LT", 8936 arm_UMLAL_GT: "UMLAL.GT", 8937 arm_UMLAL_LE: "UMLAL.LE", 8938 arm_UMLAL: "UMLAL", 8939 arm_UMLAL_ZZ: "UMLAL.ZZ", 8940 arm_UMLAL_S_EQ: "UMLAL.S.EQ", 8941 arm_UMLAL_S_NE: "UMLAL.S.NE", 8942 arm_UMLAL_S_CS: "UMLAL.S.CS", 8943 arm_UMLAL_S_CC: "UMLAL.S.CC", 8944 arm_UMLAL_S_MI: "UMLAL.S.MI", 8945 arm_UMLAL_S_PL: "UMLAL.S.PL", 8946 arm_UMLAL_S_VS: "UMLAL.S.VS", 8947 arm_UMLAL_S_VC: "UMLAL.S.VC", 8948 arm_UMLAL_S_HI: "UMLAL.S.HI", 8949 arm_UMLAL_S_LS: "UMLAL.S.LS", 8950 arm_UMLAL_S_GE: "UMLAL.S.GE", 8951 arm_UMLAL_S_LT: "UMLAL.S.LT", 8952 arm_UMLAL_S_GT: "UMLAL.S.GT", 8953 arm_UMLAL_S_LE: "UMLAL.S.LE", 8954 arm_UMLAL_S: "UMLAL.S", 8955 arm_UMLAL_S_ZZ: "UMLAL.S.ZZ", 8956 arm_UMULL_EQ: "UMULL.EQ", 8957 arm_UMULL_NE: "UMULL.NE", 8958 arm_UMULL_CS: "UMULL.CS", 8959 arm_UMULL_CC: "UMULL.CC", 8960 arm_UMULL_MI: "UMULL.MI", 8961 arm_UMULL_PL: "UMULL.PL", 8962 arm_UMULL_VS: "UMULL.VS", 8963 arm_UMULL_VC: "UMULL.VC", 8964 arm_UMULL_HI: "UMULL.HI", 8965 arm_UMULL_LS: "UMULL.LS", 8966 arm_UMULL_GE: "UMULL.GE", 8967 arm_UMULL_LT: "UMULL.LT", 8968 arm_UMULL_GT: "UMULL.GT", 8969 arm_UMULL_LE: "UMULL.LE", 8970 arm_UMULL: "UMULL", 8971 arm_UMULL_ZZ: "UMULL.ZZ", 8972 arm_UMULL_S_EQ: "UMULL.S.EQ", 8973 arm_UMULL_S_NE: "UMULL.S.NE", 8974 arm_UMULL_S_CS: "UMULL.S.CS", 8975 arm_UMULL_S_CC: "UMULL.S.CC", 8976 arm_UMULL_S_MI: "UMULL.S.MI", 8977 arm_UMULL_S_PL: "UMULL.S.PL", 8978 arm_UMULL_S_VS: "UMULL.S.VS", 8979 arm_UMULL_S_VC: "UMULL.S.VC", 8980 arm_UMULL_S_HI: "UMULL.S.HI", 8981 arm_UMULL_S_LS: "UMULL.S.LS", 8982 arm_UMULL_S_GE: "UMULL.S.GE", 8983 arm_UMULL_S_LT: "UMULL.S.LT", 8984 arm_UMULL_S_GT: "UMULL.S.GT", 8985 arm_UMULL_S_LE: "UMULL.S.LE", 8986 arm_UMULL_S: "UMULL.S", 8987 arm_UMULL_S_ZZ: "UMULL.S.ZZ", 8988 arm_UNDEF: "UNDEF", 8989 arm_UQADD16_EQ: "UQADD16.EQ", 8990 arm_UQADD16_NE: "UQADD16.NE", 8991 arm_UQADD16_CS: "UQADD16.CS", 8992 arm_UQADD16_CC: "UQADD16.CC", 8993 arm_UQADD16_MI: "UQADD16.MI", 8994 arm_UQADD16_PL: "UQADD16.PL", 8995 arm_UQADD16_VS: "UQADD16.VS", 8996 arm_UQADD16_VC: "UQADD16.VC", 8997 arm_UQADD16_HI: "UQADD16.HI", 8998 arm_UQADD16_LS: "UQADD16.LS", 8999 arm_UQADD16_GE: "UQADD16.GE", 9000 arm_UQADD16_LT: "UQADD16.LT", 9001 arm_UQADD16_GT: "UQADD16.GT", 9002 arm_UQADD16_LE: "UQADD16.LE", 9003 arm_UQADD16: "UQADD16", 9004 arm_UQADD16_ZZ: "UQADD16.ZZ", 9005 arm_UQADD8_EQ: "UQADD8.EQ", 9006 arm_UQADD8_NE: "UQADD8.NE", 9007 arm_UQADD8_CS: "UQADD8.CS", 9008 arm_UQADD8_CC: "UQADD8.CC", 9009 arm_UQADD8_MI: "UQADD8.MI", 9010 arm_UQADD8_PL: "UQADD8.PL", 9011 arm_UQADD8_VS: "UQADD8.VS", 9012 arm_UQADD8_VC: "UQADD8.VC", 9013 arm_UQADD8_HI: "UQADD8.HI", 9014 arm_UQADD8_LS: "UQADD8.LS", 9015 arm_UQADD8_GE: "UQADD8.GE", 9016 arm_UQADD8_LT: "UQADD8.LT", 9017 arm_UQADD8_GT: "UQADD8.GT", 9018 arm_UQADD8_LE: "UQADD8.LE", 9019 arm_UQADD8: "UQADD8", 9020 arm_UQADD8_ZZ: "UQADD8.ZZ", 9021 arm_UQASX_EQ: "UQASX.EQ", 9022 arm_UQASX_NE: "UQASX.NE", 9023 arm_UQASX_CS: "UQASX.CS", 9024 arm_UQASX_CC: "UQASX.CC", 9025 arm_UQASX_MI: "UQASX.MI", 9026 arm_UQASX_PL: "UQASX.PL", 9027 arm_UQASX_VS: "UQASX.VS", 9028 arm_UQASX_VC: "UQASX.VC", 9029 arm_UQASX_HI: "UQASX.HI", 9030 arm_UQASX_LS: "UQASX.LS", 9031 arm_UQASX_GE: "UQASX.GE", 9032 arm_UQASX_LT: "UQASX.LT", 9033 arm_UQASX_GT: "UQASX.GT", 9034 arm_UQASX_LE: "UQASX.LE", 9035 arm_UQASX: "UQASX", 9036 arm_UQASX_ZZ: "UQASX.ZZ", 9037 arm_UQSAX_EQ: "UQSAX.EQ", 9038 arm_UQSAX_NE: "UQSAX.NE", 9039 arm_UQSAX_CS: "UQSAX.CS", 9040 arm_UQSAX_CC: "UQSAX.CC", 9041 arm_UQSAX_MI: "UQSAX.MI", 9042 arm_UQSAX_PL: "UQSAX.PL", 9043 arm_UQSAX_VS: "UQSAX.VS", 9044 arm_UQSAX_VC: "UQSAX.VC", 9045 arm_UQSAX_HI: "UQSAX.HI", 9046 arm_UQSAX_LS: "UQSAX.LS", 9047 arm_UQSAX_GE: "UQSAX.GE", 9048 arm_UQSAX_LT: "UQSAX.LT", 9049 arm_UQSAX_GT: "UQSAX.GT", 9050 arm_UQSAX_LE: "UQSAX.LE", 9051 arm_UQSAX: "UQSAX", 9052 arm_UQSAX_ZZ: "UQSAX.ZZ", 9053 arm_UQSUB16_EQ: "UQSUB16.EQ", 9054 arm_UQSUB16_NE: "UQSUB16.NE", 9055 arm_UQSUB16_CS: "UQSUB16.CS", 9056 arm_UQSUB16_CC: "UQSUB16.CC", 9057 arm_UQSUB16_MI: "UQSUB16.MI", 9058 arm_UQSUB16_PL: "UQSUB16.PL", 9059 arm_UQSUB16_VS: "UQSUB16.VS", 9060 arm_UQSUB16_VC: "UQSUB16.VC", 9061 arm_UQSUB16_HI: "UQSUB16.HI", 9062 arm_UQSUB16_LS: "UQSUB16.LS", 9063 arm_UQSUB16_GE: "UQSUB16.GE", 9064 arm_UQSUB16_LT: "UQSUB16.LT", 9065 arm_UQSUB16_GT: "UQSUB16.GT", 9066 arm_UQSUB16_LE: "UQSUB16.LE", 9067 arm_UQSUB16: "UQSUB16", 9068 arm_UQSUB16_ZZ: "UQSUB16.ZZ", 9069 arm_UQSUB8_EQ: "UQSUB8.EQ", 9070 arm_UQSUB8_NE: "UQSUB8.NE", 9071 arm_UQSUB8_CS: "UQSUB8.CS", 9072 arm_UQSUB8_CC: "UQSUB8.CC", 9073 arm_UQSUB8_MI: "UQSUB8.MI", 9074 arm_UQSUB8_PL: "UQSUB8.PL", 9075 arm_UQSUB8_VS: "UQSUB8.VS", 9076 arm_UQSUB8_VC: "UQSUB8.VC", 9077 arm_UQSUB8_HI: "UQSUB8.HI", 9078 arm_UQSUB8_LS: "UQSUB8.LS", 9079 arm_UQSUB8_GE: "UQSUB8.GE", 9080 arm_UQSUB8_LT: "UQSUB8.LT", 9081 arm_UQSUB8_GT: "UQSUB8.GT", 9082 arm_UQSUB8_LE: "UQSUB8.LE", 9083 arm_UQSUB8: "UQSUB8", 9084 arm_UQSUB8_ZZ: "UQSUB8.ZZ", 9085 arm_USAD8_EQ: "USAD8.EQ", 9086 arm_USAD8_NE: "USAD8.NE", 9087 arm_USAD8_CS: "USAD8.CS", 9088 arm_USAD8_CC: "USAD8.CC", 9089 arm_USAD8_MI: "USAD8.MI", 9090 arm_USAD8_PL: "USAD8.PL", 9091 arm_USAD8_VS: "USAD8.VS", 9092 arm_USAD8_VC: "USAD8.VC", 9093 arm_USAD8_HI: "USAD8.HI", 9094 arm_USAD8_LS: "USAD8.LS", 9095 arm_USAD8_GE: "USAD8.GE", 9096 arm_USAD8_LT: "USAD8.LT", 9097 arm_USAD8_GT: "USAD8.GT", 9098 arm_USAD8_LE: "USAD8.LE", 9099 arm_USAD8: "USAD8", 9100 arm_USAD8_ZZ: "USAD8.ZZ", 9101 arm_USADA8_EQ: "USADA8.EQ", 9102 arm_USADA8_NE: "USADA8.NE", 9103 arm_USADA8_CS: "USADA8.CS", 9104 arm_USADA8_CC: "USADA8.CC", 9105 arm_USADA8_MI: "USADA8.MI", 9106 arm_USADA8_PL: "USADA8.PL", 9107 arm_USADA8_VS: "USADA8.VS", 9108 arm_USADA8_VC: "USADA8.VC", 9109 arm_USADA8_HI: "USADA8.HI", 9110 arm_USADA8_LS: "USADA8.LS", 9111 arm_USADA8_GE: "USADA8.GE", 9112 arm_USADA8_LT: "USADA8.LT", 9113 arm_USADA8_GT: "USADA8.GT", 9114 arm_USADA8_LE: "USADA8.LE", 9115 arm_USADA8: "USADA8", 9116 arm_USADA8_ZZ: "USADA8.ZZ", 9117 arm_USAT_EQ: "USAT.EQ", 9118 arm_USAT_NE: "USAT.NE", 9119 arm_USAT_CS: "USAT.CS", 9120 arm_USAT_CC: "USAT.CC", 9121 arm_USAT_MI: "USAT.MI", 9122 arm_USAT_PL: "USAT.PL", 9123 arm_USAT_VS: "USAT.VS", 9124 arm_USAT_VC: "USAT.VC", 9125 arm_USAT_HI: "USAT.HI", 9126 arm_USAT_LS: "USAT.LS", 9127 arm_USAT_GE: "USAT.GE", 9128 arm_USAT_LT: "USAT.LT", 9129 arm_USAT_GT: "USAT.GT", 9130 arm_USAT_LE: "USAT.LE", 9131 arm_USAT: "USAT", 9132 arm_USAT_ZZ: "USAT.ZZ", 9133 arm_USAT16_EQ: "USAT16.EQ", 9134 arm_USAT16_NE: "USAT16.NE", 9135 arm_USAT16_CS: "USAT16.CS", 9136 arm_USAT16_CC: "USAT16.CC", 9137 arm_USAT16_MI: "USAT16.MI", 9138 arm_USAT16_PL: "USAT16.PL", 9139 arm_USAT16_VS: "USAT16.VS", 9140 arm_USAT16_VC: "USAT16.VC", 9141 arm_USAT16_HI: "USAT16.HI", 9142 arm_USAT16_LS: "USAT16.LS", 9143 arm_USAT16_GE: "USAT16.GE", 9144 arm_USAT16_LT: "USAT16.LT", 9145 arm_USAT16_GT: "USAT16.GT", 9146 arm_USAT16_LE: "USAT16.LE", 9147 arm_USAT16: "USAT16", 9148 arm_USAT16_ZZ: "USAT16.ZZ", 9149 arm_USAX_EQ: "USAX.EQ", 9150 arm_USAX_NE: "USAX.NE", 9151 arm_USAX_CS: "USAX.CS", 9152 arm_USAX_CC: "USAX.CC", 9153 arm_USAX_MI: "USAX.MI", 9154 arm_USAX_PL: "USAX.PL", 9155 arm_USAX_VS: "USAX.VS", 9156 arm_USAX_VC: "USAX.VC", 9157 arm_USAX_HI: "USAX.HI", 9158 arm_USAX_LS: "USAX.LS", 9159 arm_USAX_GE: "USAX.GE", 9160 arm_USAX_LT: "USAX.LT", 9161 arm_USAX_GT: "USAX.GT", 9162 arm_USAX_LE: "USAX.LE", 9163 arm_USAX: "USAX", 9164 arm_USAX_ZZ: "USAX.ZZ", 9165 arm_USUB16_EQ: "USUB16.EQ", 9166 arm_USUB16_NE: "USUB16.NE", 9167 arm_USUB16_CS: "USUB16.CS", 9168 arm_USUB16_CC: "USUB16.CC", 9169 arm_USUB16_MI: "USUB16.MI", 9170 arm_USUB16_PL: "USUB16.PL", 9171 arm_USUB16_VS: "USUB16.VS", 9172 arm_USUB16_VC: "USUB16.VC", 9173 arm_USUB16_HI: "USUB16.HI", 9174 arm_USUB16_LS: "USUB16.LS", 9175 arm_USUB16_GE: "USUB16.GE", 9176 arm_USUB16_LT: "USUB16.LT", 9177 arm_USUB16_GT: "USUB16.GT", 9178 arm_USUB16_LE: "USUB16.LE", 9179 arm_USUB16: "USUB16", 9180 arm_USUB16_ZZ: "USUB16.ZZ", 9181 arm_USUB8_EQ: "USUB8.EQ", 9182 arm_USUB8_NE: "USUB8.NE", 9183 arm_USUB8_CS: "USUB8.CS", 9184 arm_USUB8_CC: "USUB8.CC", 9185 arm_USUB8_MI: "USUB8.MI", 9186 arm_USUB8_PL: "USUB8.PL", 9187 arm_USUB8_VS: "USUB8.VS", 9188 arm_USUB8_VC: "USUB8.VC", 9189 arm_USUB8_HI: "USUB8.HI", 9190 arm_USUB8_LS: "USUB8.LS", 9191 arm_USUB8_GE: "USUB8.GE", 9192 arm_USUB8_LT: "USUB8.LT", 9193 arm_USUB8_GT: "USUB8.GT", 9194 arm_USUB8_LE: "USUB8.LE", 9195 arm_USUB8: "USUB8", 9196 arm_USUB8_ZZ: "USUB8.ZZ", 9197 arm_UXTAB_EQ: "UXTAB.EQ", 9198 arm_UXTAB_NE: "UXTAB.NE", 9199 arm_UXTAB_CS: "UXTAB.CS", 9200 arm_UXTAB_CC: "UXTAB.CC", 9201 arm_UXTAB_MI: "UXTAB.MI", 9202 arm_UXTAB_PL: "UXTAB.PL", 9203 arm_UXTAB_VS: "UXTAB.VS", 9204 arm_UXTAB_VC: "UXTAB.VC", 9205 arm_UXTAB_HI: "UXTAB.HI", 9206 arm_UXTAB_LS: "UXTAB.LS", 9207 arm_UXTAB_GE: "UXTAB.GE", 9208 arm_UXTAB_LT: "UXTAB.LT", 9209 arm_UXTAB_GT: "UXTAB.GT", 9210 arm_UXTAB_LE: "UXTAB.LE", 9211 arm_UXTAB: "UXTAB", 9212 arm_UXTAB_ZZ: "UXTAB.ZZ", 9213 arm_UXTAB16_EQ: "UXTAB16.EQ", 9214 arm_UXTAB16_NE: "UXTAB16.NE", 9215 arm_UXTAB16_CS: "UXTAB16.CS", 9216 arm_UXTAB16_CC: "UXTAB16.CC", 9217 arm_UXTAB16_MI: "UXTAB16.MI", 9218 arm_UXTAB16_PL: "UXTAB16.PL", 9219 arm_UXTAB16_VS: "UXTAB16.VS", 9220 arm_UXTAB16_VC: "UXTAB16.VC", 9221 arm_UXTAB16_HI: "UXTAB16.HI", 9222 arm_UXTAB16_LS: "UXTAB16.LS", 9223 arm_UXTAB16_GE: "UXTAB16.GE", 9224 arm_UXTAB16_LT: "UXTAB16.LT", 9225 arm_UXTAB16_GT: "UXTAB16.GT", 9226 arm_UXTAB16_LE: "UXTAB16.LE", 9227 arm_UXTAB16: "UXTAB16", 9228 arm_UXTAB16_ZZ: "UXTAB16.ZZ", 9229 arm_UXTAH_EQ: "UXTAH.EQ", 9230 arm_UXTAH_NE: "UXTAH.NE", 9231 arm_UXTAH_CS: "UXTAH.CS", 9232 arm_UXTAH_CC: "UXTAH.CC", 9233 arm_UXTAH_MI: "UXTAH.MI", 9234 arm_UXTAH_PL: "UXTAH.PL", 9235 arm_UXTAH_VS: "UXTAH.VS", 9236 arm_UXTAH_VC: "UXTAH.VC", 9237 arm_UXTAH_HI: "UXTAH.HI", 9238 arm_UXTAH_LS: "UXTAH.LS", 9239 arm_UXTAH_GE: "UXTAH.GE", 9240 arm_UXTAH_LT: "UXTAH.LT", 9241 arm_UXTAH_GT: "UXTAH.GT", 9242 arm_UXTAH_LE: "UXTAH.LE", 9243 arm_UXTAH: "UXTAH", 9244 arm_UXTAH_ZZ: "UXTAH.ZZ", 9245 arm_UXTB_EQ: "UXTB.EQ", 9246 arm_UXTB_NE: "UXTB.NE", 9247 arm_UXTB_CS: "UXTB.CS", 9248 arm_UXTB_CC: "UXTB.CC", 9249 arm_UXTB_MI: "UXTB.MI", 9250 arm_UXTB_PL: "UXTB.PL", 9251 arm_UXTB_VS: "UXTB.VS", 9252 arm_UXTB_VC: "UXTB.VC", 9253 arm_UXTB_HI: "UXTB.HI", 9254 arm_UXTB_LS: "UXTB.LS", 9255 arm_UXTB_GE: "UXTB.GE", 9256 arm_UXTB_LT: "UXTB.LT", 9257 arm_UXTB_GT: "UXTB.GT", 9258 arm_UXTB_LE: "UXTB.LE", 9259 arm_UXTB: "UXTB", 9260 arm_UXTB_ZZ: "UXTB.ZZ", 9261 arm_UXTB16_EQ: "UXTB16.EQ", 9262 arm_UXTB16_NE: "UXTB16.NE", 9263 arm_UXTB16_CS: "UXTB16.CS", 9264 arm_UXTB16_CC: "UXTB16.CC", 9265 arm_UXTB16_MI: "UXTB16.MI", 9266 arm_UXTB16_PL: "UXTB16.PL", 9267 arm_UXTB16_VS: "UXTB16.VS", 9268 arm_UXTB16_VC: "UXTB16.VC", 9269 arm_UXTB16_HI: "UXTB16.HI", 9270 arm_UXTB16_LS: "UXTB16.LS", 9271 arm_UXTB16_GE: "UXTB16.GE", 9272 arm_UXTB16_LT: "UXTB16.LT", 9273 arm_UXTB16_GT: "UXTB16.GT", 9274 arm_UXTB16_LE: "UXTB16.LE", 9275 arm_UXTB16: "UXTB16", 9276 arm_UXTB16_ZZ: "UXTB16.ZZ", 9277 arm_UXTH_EQ: "UXTH.EQ", 9278 arm_UXTH_NE: "UXTH.NE", 9279 arm_UXTH_CS: "UXTH.CS", 9280 arm_UXTH_CC: "UXTH.CC", 9281 arm_UXTH_MI: "UXTH.MI", 9282 arm_UXTH_PL: "UXTH.PL", 9283 arm_UXTH_VS: "UXTH.VS", 9284 arm_UXTH_VC: "UXTH.VC", 9285 arm_UXTH_HI: "UXTH.HI", 9286 arm_UXTH_LS: "UXTH.LS", 9287 arm_UXTH_GE: "UXTH.GE", 9288 arm_UXTH_LT: "UXTH.LT", 9289 arm_UXTH_GT: "UXTH.GT", 9290 arm_UXTH_LE: "UXTH.LE", 9291 arm_UXTH: "UXTH", 9292 arm_UXTH_ZZ: "UXTH.ZZ", 9293 arm_VABS_EQ_F32: "VABS.EQ.F32", 9294 arm_VABS_NE_F32: "VABS.NE.F32", 9295 arm_VABS_CS_F32: "VABS.CS.F32", 9296 arm_VABS_CC_F32: "VABS.CC.F32", 9297 arm_VABS_MI_F32: "VABS.MI.F32", 9298 arm_VABS_PL_F32: "VABS.PL.F32", 9299 arm_VABS_VS_F32: "VABS.VS.F32", 9300 arm_VABS_VC_F32: "VABS.VC.F32", 9301 arm_VABS_HI_F32: "VABS.HI.F32", 9302 arm_VABS_LS_F32: "VABS.LS.F32", 9303 arm_VABS_GE_F32: "VABS.GE.F32", 9304 arm_VABS_LT_F32: "VABS.LT.F32", 9305 arm_VABS_GT_F32: "VABS.GT.F32", 9306 arm_VABS_LE_F32: "VABS.LE.F32", 9307 arm_VABS_F32: "VABS.F32", 9308 arm_VABS_ZZ_F32: "VABS.ZZ.F32", 9309 arm_VABS_EQ_F64: "VABS.EQ.F64", 9310 arm_VABS_NE_F64: "VABS.NE.F64", 9311 arm_VABS_CS_F64: "VABS.CS.F64", 9312 arm_VABS_CC_F64: "VABS.CC.F64", 9313 arm_VABS_MI_F64: "VABS.MI.F64", 9314 arm_VABS_PL_F64: "VABS.PL.F64", 9315 arm_VABS_VS_F64: "VABS.VS.F64", 9316 arm_VABS_VC_F64: "VABS.VC.F64", 9317 arm_VABS_HI_F64: "VABS.HI.F64", 9318 arm_VABS_LS_F64: "VABS.LS.F64", 9319 arm_VABS_GE_F64: "VABS.GE.F64", 9320 arm_VABS_LT_F64: "VABS.LT.F64", 9321 arm_VABS_GT_F64: "VABS.GT.F64", 9322 arm_VABS_LE_F64: "VABS.LE.F64", 9323 arm_VABS_F64: "VABS.F64", 9324 arm_VABS_ZZ_F64: "VABS.ZZ.F64", 9325 arm_VADD_EQ_F32: "VADD.EQ.F32", 9326 arm_VADD_NE_F32: "VADD.NE.F32", 9327 arm_VADD_CS_F32: "VADD.CS.F32", 9328 arm_VADD_CC_F32: "VADD.CC.F32", 9329 arm_VADD_MI_F32: "VADD.MI.F32", 9330 arm_VADD_PL_F32: "VADD.PL.F32", 9331 arm_VADD_VS_F32: "VADD.VS.F32", 9332 arm_VADD_VC_F32: "VADD.VC.F32", 9333 arm_VADD_HI_F32: "VADD.HI.F32", 9334 arm_VADD_LS_F32: "VADD.LS.F32", 9335 arm_VADD_GE_F32: "VADD.GE.F32", 9336 arm_VADD_LT_F32: "VADD.LT.F32", 9337 arm_VADD_GT_F32: "VADD.GT.F32", 9338 arm_VADD_LE_F32: "VADD.LE.F32", 9339 arm_VADD_F32: "VADD.F32", 9340 arm_VADD_ZZ_F32: "VADD.ZZ.F32", 9341 arm_VADD_EQ_F64: "VADD.EQ.F64", 9342 arm_VADD_NE_F64: "VADD.NE.F64", 9343 arm_VADD_CS_F64: "VADD.CS.F64", 9344 arm_VADD_CC_F64: "VADD.CC.F64", 9345 arm_VADD_MI_F64: "VADD.MI.F64", 9346 arm_VADD_PL_F64: "VADD.PL.F64", 9347 arm_VADD_VS_F64: "VADD.VS.F64", 9348 arm_VADD_VC_F64: "VADD.VC.F64", 9349 arm_VADD_HI_F64: "VADD.HI.F64", 9350 arm_VADD_LS_F64: "VADD.LS.F64", 9351 arm_VADD_GE_F64: "VADD.GE.F64", 9352 arm_VADD_LT_F64: "VADD.LT.F64", 9353 arm_VADD_GT_F64: "VADD.GT.F64", 9354 arm_VADD_LE_F64: "VADD.LE.F64", 9355 arm_VADD_F64: "VADD.F64", 9356 arm_VADD_ZZ_F64: "VADD.ZZ.F64", 9357 arm_VCMP_EQ_F32: "VCMP.EQ.F32", 9358 arm_VCMP_NE_F32: "VCMP.NE.F32", 9359 arm_VCMP_CS_F32: "VCMP.CS.F32", 9360 arm_VCMP_CC_F32: "VCMP.CC.F32", 9361 arm_VCMP_MI_F32: "VCMP.MI.F32", 9362 arm_VCMP_PL_F32: "VCMP.PL.F32", 9363 arm_VCMP_VS_F32: "VCMP.VS.F32", 9364 arm_VCMP_VC_F32: "VCMP.VC.F32", 9365 arm_VCMP_HI_F32: "VCMP.HI.F32", 9366 arm_VCMP_LS_F32: "VCMP.LS.F32", 9367 arm_VCMP_GE_F32: "VCMP.GE.F32", 9368 arm_VCMP_LT_F32: "VCMP.LT.F32", 9369 arm_VCMP_GT_F32: "VCMP.GT.F32", 9370 arm_VCMP_LE_F32: "VCMP.LE.F32", 9371 arm_VCMP_F32: "VCMP.F32", 9372 arm_VCMP_ZZ_F32: "VCMP.ZZ.F32", 9373 arm_VCMP_EQ_F64: "VCMP.EQ.F64", 9374 arm_VCMP_NE_F64: "VCMP.NE.F64", 9375 arm_VCMP_CS_F64: "VCMP.CS.F64", 9376 arm_VCMP_CC_F64: "VCMP.CC.F64", 9377 arm_VCMP_MI_F64: "VCMP.MI.F64", 9378 arm_VCMP_PL_F64: "VCMP.PL.F64", 9379 arm_VCMP_VS_F64: "VCMP.VS.F64", 9380 arm_VCMP_VC_F64: "VCMP.VC.F64", 9381 arm_VCMP_HI_F64: "VCMP.HI.F64", 9382 arm_VCMP_LS_F64: "VCMP.LS.F64", 9383 arm_VCMP_GE_F64: "VCMP.GE.F64", 9384 arm_VCMP_LT_F64: "VCMP.LT.F64", 9385 arm_VCMP_GT_F64: "VCMP.GT.F64", 9386 arm_VCMP_LE_F64: "VCMP.LE.F64", 9387 arm_VCMP_F64: "VCMP.F64", 9388 arm_VCMP_ZZ_F64: "VCMP.ZZ.F64", 9389 arm_VCMP_E_EQ_F32: "VCMP.E.EQ.F32", 9390 arm_VCMP_E_NE_F32: "VCMP.E.NE.F32", 9391 arm_VCMP_E_CS_F32: "VCMP.E.CS.F32", 9392 arm_VCMP_E_CC_F32: "VCMP.E.CC.F32", 9393 arm_VCMP_E_MI_F32: "VCMP.E.MI.F32", 9394 arm_VCMP_E_PL_F32: "VCMP.E.PL.F32", 9395 arm_VCMP_E_VS_F32: "VCMP.E.VS.F32", 9396 arm_VCMP_E_VC_F32: "VCMP.E.VC.F32", 9397 arm_VCMP_E_HI_F32: "VCMP.E.HI.F32", 9398 arm_VCMP_E_LS_F32: "VCMP.E.LS.F32", 9399 arm_VCMP_E_GE_F32: "VCMP.E.GE.F32", 9400 arm_VCMP_E_LT_F32: "VCMP.E.LT.F32", 9401 arm_VCMP_E_GT_F32: "VCMP.E.GT.F32", 9402 arm_VCMP_E_LE_F32: "VCMP.E.LE.F32", 9403 arm_VCMP_E_F32: "VCMP.E.F32", 9404 arm_VCMP_E_ZZ_F32: "VCMP.E.ZZ.F32", 9405 arm_VCMP_E_EQ_F64: "VCMP.E.EQ.F64", 9406 arm_VCMP_E_NE_F64: "VCMP.E.NE.F64", 9407 arm_VCMP_E_CS_F64: "VCMP.E.CS.F64", 9408 arm_VCMP_E_CC_F64: "VCMP.E.CC.F64", 9409 arm_VCMP_E_MI_F64: "VCMP.E.MI.F64", 9410 arm_VCMP_E_PL_F64: "VCMP.E.PL.F64", 9411 arm_VCMP_E_VS_F64: "VCMP.E.VS.F64", 9412 arm_VCMP_E_VC_F64: "VCMP.E.VC.F64", 9413 arm_VCMP_E_HI_F64: "VCMP.E.HI.F64", 9414 arm_VCMP_E_LS_F64: "VCMP.E.LS.F64", 9415 arm_VCMP_E_GE_F64: "VCMP.E.GE.F64", 9416 arm_VCMP_E_LT_F64: "VCMP.E.LT.F64", 9417 arm_VCMP_E_GT_F64: "VCMP.E.GT.F64", 9418 arm_VCMP_E_LE_F64: "VCMP.E.LE.F64", 9419 arm_VCMP_E_F64: "VCMP.E.F64", 9420 arm_VCMP_E_ZZ_F64: "VCMP.E.ZZ.F64", 9421 arm_VCVT_EQ_F32_FXS16: "VCVT.EQ.F32.FXS16", 9422 arm_VCVT_NE_F32_FXS16: "VCVT.NE.F32.FXS16", 9423 arm_VCVT_CS_F32_FXS16: "VCVT.CS.F32.FXS16", 9424 arm_VCVT_CC_F32_FXS16: "VCVT.CC.F32.FXS16", 9425 arm_VCVT_MI_F32_FXS16: "VCVT.MI.F32.FXS16", 9426 arm_VCVT_PL_F32_FXS16: "VCVT.PL.F32.FXS16", 9427 arm_VCVT_VS_F32_FXS16: "VCVT.VS.F32.FXS16", 9428 arm_VCVT_VC_F32_FXS16: "VCVT.VC.F32.FXS16", 9429 arm_VCVT_HI_F32_FXS16: "VCVT.HI.F32.FXS16", 9430 arm_VCVT_LS_F32_FXS16: "VCVT.LS.F32.FXS16", 9431 arm_VCVT_GE_F32_FXS16: "VCVT.GE.F32.FXS16", 9432 arm_VCVT_LT_F32_FXS16: "VCVT.LT.F32.FXS16", 9433 arm_VCVT_GT_F32_FXS16: "VCVT.GT.F32.FXS16", 9434 arm_VCVT_LE_F32_FXS16: "VCVT.LE.F32.FXS16", 9435 arm_VCVT_F32_FXS16: "VCVT.F32.FXS16", 9436 arm_VCVT_ZZ_F32_FXS16: "VCVT.ZZ.F32.FXS16", 9437 arm_VCVT_EQ_F32_FXS32: "VCVT.EQ.F32.FXS32", 9438 arm_VCVT_NE_F32_FXS32: "VCVT.NE.F32.FXS32", 9439 arm_VCVT_CS_F32_FXS32: "VCVT.CS.F32.FXS32", 9440 arm_VCVT_CC_F32_FXS32: "VCVT.CC.F32.FXS32", 9441 arm_VCVT_MI_F32_FXS32: "VCVT.MI.F32.FXS32", 9442 arm_VCVT_PL_F32_FXS32: "VCVT.PL.F32.FXS32", 9443 arm_VCVT_VS_F32_FXS32: "VCVT.VS.F32.FXS32", 9444 arm_VCVT_VC_F32_FXS32: "VCVT.VC.F32.FXS32", 9445 arm_VCVT_HI_F32_FXS32: "VCVT.HI.F32.FXS32", 9446 arm_VCVT_LS_F32_FXS32: "VCVT.LS.F32.FXS32", 9447 arm_VCVT_GE_F32_FXS32: "VCVT.GE.F32.FXS32", 9448 arm_VCVT_LT_F32_FXS32: "VCVT.LT.F32.FXS32", 9449 arm_VCVT_GT_F32_FXS32: "VCVT.GT.F32.FXS32", 9450 arm_VCVT_LE_F32_FXS32: "VCVT.LE.F32.FXS32", 9451 arm_VCVT_F32_FXS32: "VCVT.F32.FXS32", 9452 arm_VCVT_ZZ_F32_FXS32: "VCVT.ZZ.F32.FXS32", 9453 arm_VCVT_EQ_F32_FXU16: "VCVT.EQ.F32.FXU16", 9454 arm_VCVT_NE_F32_FXU16: "VCVT.NE.F32.FXU16", 9455 arm_VCVT_CS_F32_FXU16: "VCVT.CS.F32.FXU16", 9456 arm_VCVT_CC_F32_FXU16: "VCVT.CC.F32.FXU16", 9457 arm_VCVT_MI_F32_FXU16: "VCVT.MI.F32.FXU16", 9458 arm_VCVT_PL_F32_FXU16: "VCVT.PL.F32.FXU16", 9459 arm_VCVT_VS_F32_FXU16: "VCVT.VS.F32.FXU16", 9460 arm_VCVT_VC_F32_FXU16: "VCVT.VC.F32.FXU16", 9461 arm_VCVT_HI_F32_FXU16: "VCVT.HI.F32.FXU16", 9462 arm_VCVT_LS_F32_FXU16: "VCVT.LS.F32.FXU16", 9463 arm_VCVT_GE_F32_FXU16: "VCVT.GE.F32.FXU16", 9464 arm_VCVT_LT_F32_FXU16: "VCVT.LT.F32.FXU16", 9465 arm_VCVT_GT_F32_FXU16: "VCVT.GT.F32.FXU16", 9466 arm_VCVT_LE_F32_FXU16: "VCVT.LE.F32.FXU16", 9467 arm_VCVT_F32_FXU16: "VCVT.F32.FXU16", 9468 arm_VCVT_ZZ_F32_FXU16: "VCVT.ZZ.F32.FXU16", 9469 arm_VCVT_EQ_F32_FXU32: "VCVT.EQ.F32.FXU32", 9470 arm_VCVT_NE_F32_FXU32: "VCVT.NE.F32.FXU32", 9471 arm_VCVT_CS_F32_FXU32: "VCVT.CS.F32.FXU32", 9472 arm_VCVT_CC_F32_FXU32: "VCVT.CC.F32.FXU32", 9473 arm_VCVT_MI_F32_FXU32: "VCVT.MI.F32.FXU32", 9474 arm_VCVT_PL_F32_FXU32: "VCVT.PL.F32.FXU32", 9475 arm_VCVT_VS_F32_FXU32: "VCVT.VS.F32.FXU32", 9476 arm_VCVT_VC_F32_FXU32: "VCVT.VC.F32.FXU32", 9477 arm_VCVT_HI_F32_FXU32: "VCVT.HI.F32.FXU32", 9478 arm_VCVT_LS_F32_FXU32: "VCVT.LS.F32.FXU32", 9479 arm_VCVT_GE_F32_FXU32: "VCVT.GE.F32.FXU32", 9480 arm_VCVT_LT_F32_FXU32: "VCVT.LT.F32.FXU32", 9481 arm_VCVT_GT_F32_FXU32: "VCVT.GT.F32.FXU32", 9482 arm_VCVT_LE_F32_FXU32: "VCVT.LE.F32.FXU32", 9483 arm_VCVT_F32_FXU32: "VCVT.F32.FXU32", 9484 arm_VCVT_ZZ_F32_FXU32: "VCVT.ZZ.F32.FXU32", 9485 arm_VCVT_EQ_F64_FXS16: "VCVT.EQ.F64.FXS16", 9486 arm_VCVT_NE_F64_FXS16: "VCVT.NE.F64.FXS16", 9487 arm_VCVT_CS_F64_FXS16: "VCVT.CS.F64.FXS16", 9488 arm_VCVT_CC_F64_FXS16: "VCVT.CC.F64.FXS16", 9489 arm_VCVT_MI_F64_FXS16: "VCVT.MI.F64.FXS16", 9490 arm_VCVT_PL_F64_FXS16: "VCVT.PL.F64.FXS16", 9491 arm_VCVT_VS_F64_FXS16: "VCVT.VS.F64.FXS16", 9492 arm_VCVT_VC_F64_FXS16: "VCVT.VC.F64.FXS16", 9493 arm_VCVT_HI_F64_FXS16: "VCVT.HI.F64.FXS16", 9494 arm_VCVT_LS_F64_FXS16: "VCVT.LS.F64.FXS16", 9495 arm_VCVT_GE_F64_FXS16: "VCVT.GE.F64.FXS16", 9496 arm_VCVT_LT_F64_FXS16: "VCVT.LT.F64.FXS16", 9497 arm_VCVT_GT_F64_FXS16: "VCVT.GT.F64.FXS16", 9498 arm_VCVT_LE_F64_FXS16: "VCVT.LE.F64.FXS16", 9499 arm_VCVT_F64_FXS16: "VCVT.F64.FXS16", 9500 arm_VCVT_ZZ_F64_FXS16: "VCVT.ZZ.F64.FXS16", 9501 arm_VCVT_EQ_F64_FXS32: "VCVT.EQ.F64.FXS32", 9502 arm_VCVT_NE_F64_FXS32: "VCVT.NE.F64.FXS32", 9503 arm_VCVT_CS_F64_FXS32: "VCVT.CS.F64.FXS32", 9504 arm_VCVT_CC_F64_FXS32: "VCVT.CC.F64.FXS32", 9505 arm_VCVT_MI_F64_FXS32: "VCVT.MI.F64.FXS32", 9506 arm_VCVT_PL_F64_FXS32: "VCVT.PL.F64.FXS32", 9507 arm_VCVT_VS_F64_FXS32: "VCVT.VS.F64.FXS32", 9508 arm_VCVT_VC_F64_FXS32: "VCVT.VC.F64.FXS32", 9509 arm_VCVT_HI_F64_FXS32: "VCVT.HI.F64.FXS32", 9510 arm_VCVT_LS_F64_FXS32: "VCVT.LS.F64.FXS32", 9511 arm_VCVT_GE_F64_FXS32: "VCVT.GE.F64.FXS32", 9512 arm_VCVT_LT_F64_FXS32: "VCVT.LT.F64.FXS32", 9513 arm_VCVT_GT_F64_FXS32: "VCVT.GT.F64.FXS32", 9514 arm_VCVT_LE_F64_FXS32: "VCVT.LE.F64.FXS32", 9515 arm_VCVT_F64_FXS32: "VCVT.F64.FXS32", 9516 arm_VCVT_ZZ_F64_FXS32: "VCVT.ZZ.F64.FXS32", 9517 arm_VCVT_EQ_F64_FXU16: "VCVT.EQ.F64.FXU16", 9518 arm_VCVT_NE_F64_FXU16: "VCVT.NE.F64.FXU16", 9519 arm_VCVT_CS_F64_FXU16: "VCVT.CS.F64.FXU16", 9520 arm_VCVT_CC_F64_FXU16: "VCVT.CC.F64.FXU16", 9521 arm_VCVT_MI_F64_FXU16: "VCVT.MI.F64.FXU16", 9522 arm_VCVT_PL_F64_FXU16: "VCVT.PL.F64.FXU16", 9523 arm_VCVT_VS_F64_FXU16: "VCVT.VS.F64.FXU16", 9524 arm_VCVT_VC_F64_FXU16: "VCVT.VC.F64.FXU16", 9525 arm_VCVT_HI_F64_FXU16: "VCVT.HI.F64.FXU16", 9526 arm_VCVT_LS_F64_FXU16: "VCVT.LS.F64.FXU16", 9527 arm_VCVT_GE_F64_FXU16: "VCVT.GE.F64.FXU16", 9528 arm_VCVT_LT_F64_FXU16: "VCVT.LT.F64.FXU16", 9529 arm_VCVT_GT_F64_FXU16: "VCVT.GT.F64.FXU16", 9530 arm_VCVT_LE_F64_FXU16: "VCVT.LE.F64.FXU16", 9531 arm_VCVT_F64_FXU16: "VCVT.F64.FXU16", 9532 arm_VCVT_ZZ_F64_FXU16: "VCVT.ZZ.F64.FXU16", 9533 arm_VCVT_EQ_F64_FXU32: "VCVT.EQ.F64.FXU32", 9534 arm_VCVT_NE_F64_FXU32: "VCVT.NE.F64.FXU32", 9535 arm_VCVT_CS_F64_FXU32: "VCVT.CS.F64.FXU32", 9536 arm_VCVT_CC_F64_FXU32: "VCVT.CC.F64.FXU32", 9537 arm_VCVT_MI_F64_FXU32: "VCVT.MI.F64.FXU32", 9538 arm_VCVT_PL_F64_FXU32: "VCVT.PL.F64.FXU32", 9539 arm_VCVT_VS_F64_FXU32: "VCVT.VS.F64.FXU32", 9540 arm_VCVT_VC_F64_FXU32: "VCVT.VC.F64.FXU32", 9541 arm_VCVT_HI_F64_FXU32: "VCVT.HI.F64.FXU32", 9542 arm_VCVT_LS_F64_FXU32: "VCVT.LS.F64.FXU32", 9543 arm_VCVT_GE_F64_FXU32: "VCVT.GE.F64.FXU32", 9544 arm_VCVT_LT_F64_FXU32: "VCVT.LT.F64.FXU32", 9545 arm_VCVT_GT_F64_FXU32: "VCVT.GT.F64.FXU32", 9546 arm_VCVT_LE_F64_FXU32: "VCVT.LE.F64.FXU32", 9547 arm_VCVT_F64_FXU32: "VCVT.F64.FXU32", 9548 arm_VCVT_ZZ_F64_FXU32: "VCVT.ZZ.F64.FXU32", 9549 arm_VCVT_EQ_F32_U32: "VCVT.EQ.F32.U32", 9550 arm_VCVT_NE_F32_U32: "VCVT.NE.F32.U32", 9551 arm_VCVT_CS_F32_U32: "VCVT.CS.F32.U32", 9552 arm_VCVT_CC_F32_U32: "VCVT.CC.F32.U32", 9553 arm_VCVT_MI_F32_U32: "VCVT.MI.F32.U32", 9554 arm_VCVT_PL_F32_U32: "VCVT.PL.F32.U32", 9555 arm_VCVT_VS_F32_U32: "VCVT.VS.F32.U32", 9556 arm_VCVT_VC_F32_U32: "VCVT.VC.F32.U32", 9557 arm_VCVT_HI_F32_U32: "VCVT.HI.F32.U32", 9558 arm_VCVT_LS_F32_U32: "VCVT.LS.F32.U32", 9559 arm_VCVT_GE_F32_U32: "VCVT.GE.F32.U32", 9560 arm_VCVT_LT_F32_U32: "VCVT.LT.F32.U32", 9561 arm_VCVT_GT_F32_U32: "VCVT.GT.F32.U32", 9562 arm_VCVT_LE_F32_U32: "VCVT.LE.F32.U32", 9563 arm_VCVT_F32_U32: "VCVT.F32.U32", 9564 arm_VCVT_ZZ_F32_U32: "VCVT.ZZ.F32.U32", 9565 arm_VCVT_EQ_F32_S32: "VCVT.EQ.F32.S32", 9566 arm_VCVT_NE_F32_S32: "VCVT.NE.F32.S32", 9567 arm_VCVT_CS_F32_S32: "VCVT.CS.F32.S32", 9568 arm_VCVT_CC_F32_S32: "VCVT.CC.F32.S32", 9569 arm_VCVT_MI_F32_S32: "VCVT.MI.F32.S32", 9570 arm_VCVT_PL_F32_S32: "VCVT.PL.F32.S32", 9571 arm_VCVT_VS_F32_S32: "VCVT.VS.F32.S32", 9572 arm_VCVT_VC_F32_S32: "VCVT.VC.F32.S32", 9573 arm_VCVT_HI_F32_S32: "VCVT.HI.F32.S32", 9574 arm_VCVT_LS_F32_S32: "VCVT.LS.F32.S32", 9575 arm_VCVT_GE_F32_S32: "VCVT.GE.F32.S32", 9576 arm_VCVT_LT_F32_S32: "VCVT.LT.F32.S32", 9577 arm_VCVT_GT_F32_S32: "VCVT.GT.F32.S32", 9578 arm_VCVT_LE_F32_S32: "VCVT.LE.F32.S32", 9579 arm_VCVT_F32_S32: "VCVT.F32.S32", 9580 arm_VCVT_ZZ_F32_S32: "VCVT.ZZ.F32.S32", 9581 arm_VCVT_EQ_F64_U32: "VCVT.EQ.F64.U32", 9582 arm_VCVT_NE_F64_U32: "VCVT.NE.F64.U32", 9583 arm_VCVT_CS_F64_U32: "VCVT.CS.F64.U32", 9584 arm_VCVT_CC_F64_U32: "VCVT.CC.F64.U32", 9585 arm_VCVT_MI_F64_U32: "VCVT.MI.F64.U32", 9586 arm_VCVT_PL_F64_U32: "VCVT.PL.F64.U32", 9587 arm_VCVT_VS_F64_U32: "VCVT.VS.F64.U32", 9588 arm_VCVT_VC_F64_U32: "VCVT.VC.F64.U32", 9589 arm_VCVT_HI_F64_U32: "VCVT.HI.F64.U32", 9590 arm_VCVT_LS_F64_U32: "VCVT.LS.F64.U32", 9591 arm_VCVT_GE_F64_U32: "VCVT.GE.F64.U32", 9592 arm_VCVT_LT_F64_U32: "VCVT.LT.F64.U32", 9593 arm_VCVT_GT_F64_U32: "VCVT.GT.F64.U32", 9594 arm_VCVT_LE_F64_U32: "VCVT.LE.F64.U32", 9595 arm_VCVT_F64_U32: "VCVT.F64.U32", 9596 arm_VCVT_ZZ_F64_U32: "VCVT.ZZ.F64.U32", 9597 arm_VCVT_EQ_F64_S32: "VCVT.EQ.F64.S32", 9598 arm_VCVT_NE_F64_S32: "VCVT.NE.F64.S32", 9599 arm_VCVT_CS_F64_S32: "VCVT.CS.F64.S32", 9600 arm_VCVT_CC_F64_S32: "VCVT.CC.F64.S32", 9601 arm_VCVT_MI_F64_S32: "VCVT.MI.F64.S32", 9602 arm_VCVT_PL_F64_S32: "VCVT.PL.F64.S32", 9603 arm_VCVT_VS_F64_S32: "VCVT.VS.F64.S32", 9604 arm_VCVT_VC_F64_S32: "VCVT.VC.F64.S32", 9605 arm_VCVT_HI_F64_S32: "VCVT.HI.F64.S32", 9606 arm_VCVT_LS_F64_S32: "VCVT.LS.F64.S32", 9607 arm_VCVT_GE_F64_S32: "VCVT.GE.F64.S32", 9608 arm_VCVT_LT_F64_S32: "VCVT.LT.F64.S32", 9609 arm_VCVT_GT_F64_S32: "VCVT.GT.F64.S32", 9610 arm_VCVT_LE_F64_S32: "VCVT.LE.F64.S32", 9611 arm_VCVT_F64_S32: "VCVT.F64.S32", 9612 arm_VCVT_ZZ_F64_S32: "VCVT.ZZ.F64.S32", 9613 arm_VCVT_EQ_F64_F32: "VCVT.EQ.F64.F32", 9614 arm_VCVT_NE_F64_F32: "VCVT.NE.F64.F32", 9615 arm_VCVT_CS_F64_F32: "VCVT.CS.F64.F32", 9616 arm_VCVT_CC_F64_F32: "VCVT.CC.F64.F32", 9617 arm_VCVT_MI_F64_F32: "VCVT.MI.F64.F32", 9618 arm_VCVT_PL_F64_F32: "VCVT.PL.F64.F32", 9619 arm_VCVT_VS_F64_F32: "VCVT.VS.F64.F32", 9620 arm_VCVT_VC_F64_F32: "VCVT.VC.F64.F32", 9621 arm_VCVT_HI_F64_F32: "VCVT.HI.F64.F32", 9622 arm_VCVT_LS_F64_F32: "VCVT.LS.F64.F32", 9623 arm_VCVT_GE_F64_F32: "VCVT.GE.F64.F32", 9624 arm_VCVT_LT_F64_F32: "VCVT.LT.F64.F32", 9625 arm_VCVT_GT_F64_F32: "VCVT.GT.F64.F32", 9626 arm_VCVT_LE_F64_F32: "VCVT.LE.F64.F32", 9627 arm_VCVT_F64_F32: "VCVT.F64.F32", 9628 arm_VCVT_ZZ_F64_F32: "VCVT.ZZ.F64.F32", 9629 arm_VCVT_EQ_F32_F64: "VCVT.EQ.F32.F64", 9630 arm_VCVT_NE_F32_F64: "VCVT.NE.F32.F64", 9631 arm_VCVT_CS_F32_F64: "VCVT.CS.F32.F64", 9632 arm_VCVT_CC_F32_F64: "VCVT.CC.F32.F64", 9633 arm_VCVT_MI_F32_F64: "VCVT.MI.F32.F64", 9634 arm_VCVT_PL_F32_F64: "VCVT.PL.F32.F64", 9635 arm_VCVT_VS_F32_F64: "VCVT.VS.F32.F64", 9636 arm_VCVT_VC_F32_F64: "VCVT.VC.F32.F64", 9637 arm_VCVT_HI_F32_F64: "VCVT.HI.F32.F64", 9638 arm_VCVT_LS_F32_F64: "VCVT.LS.F32.F64", 9639 arm_VCVT_GE_F32_F64: "VCVT.GE.F32.F64", 9640 arm_VCVT_LT_F32_F64: "VCVT.LT.F32.F64", 9641 arm_VCVT_GT_F32_F64: "VCVT.GT.F32.F64", 9642 arm_VCVT_LE_F32_F64: "VCVT.LE.F32.F64", 9643 arm_VCVT_F32_F64: "VCVT.F32.F64", 9644 arm_VCVT_ZZ_F32_F64: "VCVT.ZZ.F32.F64", 9645 arm_VCVT_EQ_FXS16_F32: "VCVT.EQ.FXS16.F32", 9646 arm_VCVT_NE_FXS16_F32: "VCVT.NE.FXS16.F32", 9647 arm_VCVT_CS_FXS16_F32: "VCVT.CS.FXS16.F32", 9648 arm_VCVT_CC_FXS16_F32: "VCVT.CC.FXS16.F32", 9649 arm_VCVT_MI_FXS16_F32: "VCVT.MI.FXS16.F32", 9650 arm_VCVT_PL_FXS16_F32: "VCVT.PL.FXS16.F32", 9651 arm_VCVT_VS_FXS16_F32: "VCVT.VS.FXS16.F32", 9652 arm_VCVT_VC_FXS16_F32: "VCVT.VC.FXS16.F32", 9653 arm_VCVT_HI_FXS16_F32: "VCVT.HI.FXS16.F32", 9654 arm_VCVT_LS_FXS16_F32: "VCVT.LS.FXS16.F32", 9655 arm_VCVT_GE_FXS16_F32: "VCVT.GE.FXS16.F32", 9656 arm_VCVT_LT_FXS16_F32: "VCVT.LT.FXS16.F32", 9657 arm_VCVT_GT_FXS16_F32: "VCVT.GT.FXS16.F32", 9658 arm_VCVT_LE_FXS16_F32: "VCVT.LE.FXS16.F32", 9659 arm_VCVT_FXS16_F32: "VCVT.FXS16.F32", 9660 arm_VCVT_ZZ_FXS16_F32: "VCVT.ZZ.FXS16.F32", 9661 arm_VCVT_EQ_FXS16_F64: "VCVT.EQ.FXS16.F64", 9662 arm_VCVT_NE_FXS16_F64: "VCVT.NE.FXS16.F64", 9663 arm_VCVT_CS_FXS16_F64: "VCVT.CS.FXS16.F64", 9664 arm_VCVT_CC_FXS16_F64: "VCVT.CC.FXS16.F64", 9665 arm_VCVT_MI_FXS16_F64: "VCVT.MI.FXS16.F64", 9666 arm_VCVT_PL_FXS16_F64: "VCVT.PL.FXS16.F64", 9667 arm_VCVT_VS_FXS16_F64: "VCVT.VS.FXS16.F64", 9668 arm_VCVT_VC_FXS16_F64: "VCVT.VC.FXS16.F64", 9669 arm_VCVT_HI_FXS16_F64: "VCVT.HI.FXS16.F64", 9670 arm_VCVT_LS_FXS16_F64: "VCVT.LS.FXS16.F64", 9671 arm_VCVT_GE_FXS16_F64: "VCVT.GE.FXS16.F64", 9672 arm_VCVT_LT_FXS16_F64: "VCVT.LT.FXS16.F64", 9673 arm_VCVT_GT_FXS16_F64: "VCVT.GT.FXS16.F64", 9674 arm_VCVT_LE_FXS16_F64: "VCVT.LE.FXS16.F64", 9675 arm_VCVT_FXS16_F64: "VCVT.FXS16.F64", 9676 arm_VCVT_ZZ_FXS16_F64: "VCVT.ZZ.FXS16.F64", 9677 arm_VCVT_EQ_FXS32_F32: "VCVT.EQ.FXS32.F32", 9678 arm_VCVT_NE_FXS32_F32: "VCVT.NE.FXS32.F32", 9679 arm_VCVT_CS_FXS32_F32: "VCVT.CS.FXS32.F32", 9680 arm_VCVT_CC_FXS32_F32: "VCVT.CC.FXS32.F32", 9681 arm_VCVT_MI_FXS32_F32: "VCVT.MI.FXS32.F32", 9682 arm_VCVT_PL_FXS32_F32: "VCVT.PL.FXS32.F32", 9683 arm_VCVT_VS_FXS32_F32: "VCVT.VS.FXS32.F32", 9684 arm_VCVT_VC_FXS32_F32: "VCVT.VC.FXS32.F32", 9685 arm_VCVT_HI_FXS32_F32: "VCVT.HI.FXS32.F32", 9686 arm_VCVT_LS_FXS32_F32: "VCVT.LS.FXS32.F32", 9687 arm_VCVT_GE_FXS32_F32: "VCVT.GE.FXS32.F32", 9688 arm_VCVT_LT_FXS32_F32: "VCVT.LT.FXS32.F32", 9689 arm_VCVT_GT_FXS32_F32: "VCVT.GT.FXS32.F32", 9690 arm_VCVT_LE_FXS32_F32: "VCVT.LE.FXS32.F32", 9691 arm_VCVT_FXS32_F32: "VCVT.FXS32.F32", 9692 arm_VCVT_ZZ_FXS32_F32: "VCVT.ZZ.FXS32.F32", 9693 arm_VCVT_EQ_FXS32_F64: "VCVT.EQ.FXS32.F64", 9694 arm_VCVT_NE_FXS32_F64: "VCVT.NE.FXS32.F64", 9695 arm_VCVT_CS_FXS32_F64: "VCVT.CS.FXS32.F64", 9696 arm_VCVT_CC_FXS32_F64: "VCVT.CC.FXS32.F64", 9697 arm_VCVT_MI_FXS32_F64: "VCVT.MI.FXS32.F64", 9698 arm_VCVT_PL_FXS32_F64: "VCVT.PL.FXS32.F64", 9699 arm_VCVT_VS_FXS32_F64: "VCVT.VS.FXS32.F64", 9700 arm_VCVT_VC_FXS32_F64: "VCVT.VC.FXS32.F64", 9701 arm_VCVT_HI_FXS32_F64: "VCVT.HI.FXS32.F64", 9702 arm_VCVT_LS_FXS32_F64: "VCVT.LS.FXS32.F64", 9703 arm_VCVT_GE_FXS32_F64: "VCVT.GE.FXS32.F64", 9704 arm_VCVT_LT_FXS32_F64: "VCVT.LT.FXS32.F64", 9705 arm_VCVT_GT_FXS32_F64: "VCVT.GT.FXS32.F64", 9706 arm_VCVT_LE_FXS32_F64: "VCVT.LE.FXS32.F64", 9707 arm_VCVT_FXS32_F64: "VCVT.FXS32.F64", 9708 arm_VCVT_ZZ_FXS32_F64: "VCVT.ZZ.FXS32.F64", 9709 arm_VCVT_EQ_FXU16_F32: "VCVT.EQ.FXU16.F32", 9710 arm_VCVT_NE_FXU16_F32: "VCVT.NE.FXU16.F32", 9711 arm_VCVT_CS_FXU16_F32: "VCVT.CS.FXU16.F32", 9712 arm_VCVT_CC_FXU16_F32: "VCVT.CC.FXU16.F32", 9713 arm_VCVT_MI_FXU16_F32: "VCVT.MI.FXU16.F32", 9714 arm_VCVT_PL_FXU16_F32: "VCVT.PL.FXU16.F32", 9715 arm_VCVT_VS_FXU16_F32: "VCVT.VS.FXU16.F32", 9716 arm_VCVT_VC_FXU16_F32: "VCVT.VC.FXU16.F32", 9717 arm_VCVT_HI_FXU16_F32: "VCVT.HI.FXU16.F32", 9718 arm_VCVT_LS_FXU16_F32: "VCVT.LS.FXU16.F32", 9719 arm_VCVT_GE_FXU16_F32: "VCVT.GE.FXU16.F32", 9720 arm_VCVT_LT_FXU16_F32: "VCVT.LT.FXU16.F32", 9721 arm_VCVT_GT_FXU16_F32: "VCVT.GT.FXU16.F32", 9722 arm_VCVT_LE_FXU16_F32: "VCVT.LE.FXU16.F32", 9723 arm_VCVT_FXU16_F32: "VCVT.FXU16.F32", 9724 arm_VCVT_ZZ_FXU16_F32: "VCVT.ZZ.FXU16.F32", 9725 arm_VCVT_EQ_FXU16_F64: "VCVT.EQ.FXU16.F64", 9726 arm_VCVT_NE_FXU16_F64: "VCVT.NE.FXU16.F64", 9727 arm_VCVT_CS_FXU16_F64: "VCVT.CS.FXU16.F64", 9728 arm_VCVT_CC_FXU16_F64: "VCVT.CC.FXU16.F64", 9729 arm_VCVT_MI_FXU16_F64: "VCVT.MI.FXU16.F64", 9730 arm_VCVT_PL_FXU16_F64: "VCVT.PL.FXU16.F64", 9731 arm_VCVT_VS_FXU16_F64: "VCVT.VS.FXU16.F64", 9732 arm_VCVT_VC_FXU16_F64: "VCVT.VC.FXU16.F64", 9733 arm_VCVT_HI_FXU16_F64: "VCVT.HI.FXU16.F64", 9734 arm_VCVT_LS_FXU16_F64: "VCVT.LS.FXU16.F64", 9735 arm_VCVT_GE_FXU16_F64: "VCVT.GE.FXU16.F64", 9736 arm_VCVT_LT_FXU16_F64: "VCVT.LT.FXU16.F64", 9737 arm_VCVT_GT_FXU16_F64: "VCVT.GT.FXU16.F64", 9738 arm_VCVT_LE_FXU16_F64: "VCVT.LE.FXU16.F64", 9739 arm_VCVT_FXU16_F64: "VCVT.FXU16.F64", 9740 arm_VCVT_ZZ_FXU16_F64: "VCVT.ZZ.FXU16.F64", 9741 arm_VCVT_EQ_FXU32_F32: "VCVT.EQ.FXU32.F32", 9742 arm_VCVT_NE_FXU32_F32: "VCVT.NE.FXU32.F32", 9743 arm_VCVT_CS_FXU32_F32: "VCVT.CS.FXU32.F32", 9744 arm_VCVT_CC_FXU32_F32: "VCVT.CC.FXU32.F32", 9745 arm_VCVT_MI_FXU32_F32: "VCVT.MI.FXU32.F32", 9746 arm_VCVT_PL_FXU32_F32: "VCVT.PL.FXU32.F32", 9747 arm_VCVT_VS_FXU32_F32: "VCVT.VS.FXU32.F32", 9748 arm_VCVT_VC_FXU32_F32: "VCVT.VC.FXU32.F32", 9749 arm_VCVT_HI_FXU32_F32: "VCVT.HI.FXU32.F32", 9750 arm_VCVT_LS_FXU32_F32: "VCVT.LS.FXU32.F32", 9751 arm_VCVT_GE_FXU32_F32: "VCVT.GE.FXU32.F32", 9752 arm_VCVT_LT_FXU32_F32: "VCVT.LT.FXU32.F32", 9753 arm_VCVT_GT_FXU32_F32: "VCVT.GT.FXU32.F32", 9754 arm_VCVT_LE_FXU32_F32: "VCVT.LE.FXU32.F32", 9755 arm_VCVT_FXU32_F32: "VCVT.FXU32.F32", 9756 arm_VCVT_ZZ_FXU32_F32: "VCVT.ZZ.FXU32.F32", 9757 arm_VCVT_EQ_FXU32_F64: "VCVT.EQ.FXU32.F64", 9758 arm_VCVT_NE_FXU32_F64: "VCVT.NE.FXU32.F64", 9759 arm_VCVT_CS_FXU32_F64: "VCVT.CS.FXU32.F64", 9760 arm_VCVT_CC_FXU32_F64: "VCVT.CC.FXU32.F64", 9761 arm_VCVT_MI_FXU32_F64: "VCVT.MI.FXU32.F64", 9762 arm_VCVT_PL_FXU32_F64: "VCVT.PL.FXU32.F64", 9763 arm_VCVT_VS_FXU32_F64: "VCVT.VS.FXU32.F64", 9764 arm_VCVT_VC_FXU32_F64: "VCVT.VC.FXU32.F64", 9765 arm_VCVT_HI_FXU32_F64: "VCVT.HI.FXU32.F64", 9766 arm_VCVT_LS_FXU32_F64: "VCVT.LS.FXU32.F64", 9767 arm_VCVT_GE_FXU32_F64: "VCVT.GE.FXU32.F64", 9768 arm_VCVT_LT_FXU32_F64: "VCVT.LT.FXU32.F64", 9769 arm_VCVT_GT_FXU32_F64: "VCVT.GT.FXU32.F64", 9770 arm_VCVT_LE_FXU32_F64: "VCVT.LE.FXU32.F64", 9771 arm_VCVT_FXU32_F64: "VCVT.FXU32.F64", 9772 arm_VCVT_ZZ_FXU32_F64: "VCVT.ZZ.FXU32.F64", 9773 arm_VCVTB_EQ_F32_F16: "VCVTB.EQ.F32.F16", 9774 arm_VCVTB_NE_F32_F16: "VCVTB.NE.F32.F16", 9775 arm_VCVTB_CS_F32_F16: "VCVTB.CS.F32.F16", 9776 arm_VCVTB_CC_F32_F16: "VCVTB.CC.F32.F16", 9777 arm_VCVTB_MI_F32_F16: "VCVTB.MI.F32.F16", 9778 arm_VCVTB_PL_F32_F16: "VCVTB.PL.F32.F16", 9779 arm_VCVTB_VS_F32_F16: "VCVTB.VS.F32.F16", 9780 arm_VCVTB_VC_F32_F16: "VCVTB.VC.F32.F16", 9781 arm_VCVTB_HI_F32_F16: "VCVTB.HI.F32.F16", 9782 arm_VCVTB_LS_F32_F16: "VCVTB.LS.F32.F16", 9783 arm_VCVTB_GE_F32_F16: "VCVTB.GE.F32.F16", 9784 arm_VCVTB_LT_F32_F16: "VCVTB.LT.F32.F16", 9785 arm_VCVTB_GT_F32_F16: "VCVTB.GT.F32.F16", 9786 arm_VCVTB_LE_F32_F16: "VCVTB.LE.F32.F16", 9787 arm_VCVTB_F32_F16: "VCVTB.F32.F16", 9788 arm_VCVTB_ZZ_F32_F16: "VCVTB.ZZ.F32.F16", 9789 arm_VCVTB_EQ_F16_F32: "VCVTB.EQ.F16.F32", 9790 arm_VCVTB_NE_F16_F32: "VCVTB.NE.F16.F32", 9791 arm_VCVTB_CS_F16_F32: "VCVTB.CS.F16.F32", 9792 arm_VCVTB_CC_F16_F32: "VCVTB.CC.F16.F32", 9793 arm_VCVTB_MI_F16_F32: "VCVTB.MI.F16.F32", 9794 arm_VCVTB_PL_F16_F32: "VCVTB.PL.F16.F32", 9795 arm_VCVTB_VS_F16_F32: "VCVTB.VS.F16.F32", 9796 arm_VCVTB_VC_F16_F32: "VCVTB.VC.F16.F32", 9797 arm_VCVTB_HI_F16_F32: "VCVTB.HI.F16.F32", 9798 arm_VCVTB_LS_F16_F32: "VCVTB.LS.F16.F32", 9799 arm_VCVTB_GE_F16_F32: "VCVTB.GE.F16.F32", 9800 arm_VCVTB_LT_F16_F32: "VCVTB.LT.F16.F32", 9801 arm_VCVTB_GT_F16_F32: "VCVTB.GT.F16.F32", 9802 arm_VCVTB_LE_F16_F32: "VCVTB.LE.F16.F32", 9803 arm_VCVTB_F16_F32: "VCVTB.F16.F32", 9804 arm_VCVTB_ZZ_F16_F32: "VCVTB.ZZ.F16.F32", 9805 arm_VCVTT_EQ_F32_F16: "VCVTT.EQ.F32.F16", 9806 arm_VCVTT_NE_F32_F16: "VCVTT.NE.F32.F16", 9807 arm_VCVTT_CS_F32_F16: "VCVTT.CS.F32.F16", 9808 arm_VCVTT_CC_F32_F16: "VCVTT.CC.F32.F16", 9809 arm_VCVTT_MI_F32_F16: "VCVTT.MI.F32.F16", 9810 arm_VCVTT_PL_F32_F16: "VCVTT.PL.F32.F16", 9811 arm_VCVTT_VS_F32_F16: "VCVTT.VS.F32.F16", 9812 arm_VCVTT_VC_F32_F16: "VCVTT.VC.F32.F16", 9813 arm_VCVTT_HI_F32_F16: "VCVTT.HI.F32.F16", 9814 arm_VCVTT_LS_F32_F16: "VCVTT.LS.F32.F16", 9815 arm_VCVTT_GE_F32_F16: "VCVTT.GE.F32.F16", 9816 arm_VCVTT_LT_F32_F16: "VCVTT.LT.F32.F16", 9817 arm_VCVTT_GT_F32_F16: "VCVTT.GT.F32.F16", 9818 arm_VCVTT_LE_F32_F16: "VCVTT.LE.F32.F16", 9819 arm_VCVTT_F32_F16: "VCVTT.F32.F16", 9820 arm_VCVTT_ZZ_F32_F16: "VCVTT.ZZ.F32.F16", 9821 arm_VCVTT_EQ_F16_F32: "VCVTT.EQ.F16.F32", 9822 arm_VCVTT_NE_F16_F32: "VCVTT.NE.F16.F32", 9823 arm_VCVTT_CS_F16_F32: "VCVTT.CS.F16.F32", 9824 arm_VCVTT_CC_F16_F32: "VCVTT.CC.F16.F32", 9825 arm_VCVTT_MI_F16_F32: "VCVTT.MI.F16.F32", 9826 arm_VCVTT_PL_F16_F32: "VCVTT.PL.F16.F32", 9827 arm_VCVTT_VS_F16_F32: "VCVTT.VS.F16.F32", 9828 arm_VCVTT_VC_F16_F32: "VCVTT.VC.F16.F32", 9829 arm_VCVTT_HI_F16_F32: "VCVTT.HI.F16.F32", 9830 arm_VCVTT_LS_F16_F32: "VCVTT.LS.F16.F32", 9831 arm_VCVTT_GE_F16_F32: "VCVTT.GE.F16.F32", 9832 arm_VCVTT_LT_F16_F32: "VCVTT.LT.F16.F32", 9833 arm_VCVTT_GT_F16_F32: "VCVTT.GT.F16.F32", 9834 arm_VCVTT_LE_F16_F32: "VCVTT.LE.F16.F32", 9835 arm_VCVTT_F16_F32: "VCVTT.F16.F32", 9836 arm_VCVTT_ZZ_F16_F32: "VCVTT.ZZ.F16.F32", 9837 arm_VCVTR_EQ_U32_F32: "VCVTR.EQ.U32.F32", 9838 arm_VCVTR_NE_U32_F32: "VCVTR.NE.U32.F32", 9839 arm_VCVTR_CS_U32_F32: "VCVTR.CS.U32.F32", 9840 arm_VCVTR_CC_U32_F32: "VCVTR.CC.U32.F32", 9841 arm_VCVTR_MI_U32_F32: "VCVTR.MI.U32.F32", 9842 arm_VCVTR_PL_U32_F32: "VCVTR.PL.U32.F32", 9843 arm_VCVTR_VS_U32_F32: "VCVTR.VS.U32.F32", 9844 arm_VCVTR_VC_U32_F32: "VCVTR.VC.U32.F32", 9845 arm_VCVTR_HI_U32_F32: "VCVTR.HI.U32.F32", 9846 arm_VCVTR_LS_U32_F32: "VCVTR.LS.U32.F32", 9847 arm_VCVTR_GE_U32_F32: "VCVTR.GE.U32.F32", 9848 arm_VCVTR_LT_U32_F32: "VCVTR.LT.U32.F32", 9849 arm_VCVTR_GT_U32_F32: "VCVTR.GT.U32.F32", 9850 arm_VCVTR_LE_U32_F32: "VCVTR.LE.U32.F32", 9851 arm_VCVTR_U32_F32: "VCVTR.U32.F32", 9852 arm_VCVTR_ZZ_U32_F32: "VCVTR.ZZ.U32.F32", 9853 arm_VCVTR_EQ_U32_F64: "VCVTR.EQ.U32.F64", 9854 arm_VCVTR_NE_U32_F64: "VCVTR.NE.U32.F64", 9855 arm_VCVTR_CS_U32_F64: "VCVTR.CS.U32.F64", 9856 arm_VCVTR_CC_U32_F64: "VCVTR.CC.U32.F64", 9857 arm_VCVTR_MI_U32_F64: "VCVTR.MI.U32.F64", 9858 arm_VCVTR_PL_U32_F64: "VCVTR.PL.U32.F64", 9859 arm_VCVTR_VS_U32_F64: "VCVTR.VS.U32.F64", 9860 arm_VCVTR_VC_U32_F64: "VCVTR.VC.U32.F64", 9861 arm_VCVTR_HI_U32_F64: "VCVTR.HI.U32.F64", 9862 arm_VCVTR_LS_U32_F64: "VCVTR.LS.U32.F64", 9863 arm_VCVTR_GE_U32_F64: "VCVTR.GE.U32.F64", 9864 arm_VCVTR_LT_U32_F64: "VCVTR.LT.U32.F64", 9865 arm_VCVTR_GT_U32_F64: "VCVTR.GT.U32.F64", 9866 arm_VCVTR_LE_U32_F64: "VCVTR.LE.U32.F64", 9867 arm_VCVTR_U32_F64: "VCVTR.U32.F64", 9868 arm_VCVTR_ZZ_U32_F64: "VCVTR.ZZ.U32.F64", 9869 arm_VCVTR_EQ_S32_F32: "VCVTR.EQ.S32.F32", 9870 arm_VCVTR_NE_S32_F32: "VCVTR.NE.S32.F32", 9871 arm_VCVTR_CS_S32_F32: "VCVTR.CS.S32.F32", 9872 arm_VCVTR_CC_S32_F32: "VCVTR.CC.S32.F32", 9873 arm_VCVTR_MI_S32_F32: "VCVTR.MI.S32.F32", 9874 arm_VCVTR_PL_S32_F32: "VCVTR.PL.S32.F32", 9875 arm_VCVTR_VS_S32_F32: "VCVTR.VS.S32.F32", 9876 arm_VCVTR_VC_S32_F32: "VCVTR.VC.S32.F32", 9877 arm_VCVTR_HI_S32_F32: "VCVTR.HI.S32.F32", 9878 arm_VCVTR_LS_S32_F32: "VCVTR.LS.S32.F32", 9879 arm_VCVTR_GE_S32_F32: "VCVTR.GE.S32.F32", 9880 arm_VCVTR_LT_S32_F32: "VCVTR.LT.S32.F32", 9881 arm_VCVTR_GT_S32_F32: "VCVTR.GT.S32.F32", 9882 arm_VCVTR_LE_S32_F32: "VCVTR.LE.S32.F32", 9883 arm_VCVTR_S32_F32: "VCVTR.S32.F32", 9884 arm_VCVTR_ZZ_S32_F32: "VCVTR.ZZ.S32.F32", 9885 arm_VCVTR_EQ_S32_F64: "VCVTR.EQ.S32.F64", 9886 arm_VCVTR_NE_S32_F64: "VCVTR.NE.S32.F64", 9887 arm_VCVTR_CS_S32_F64: "VCVTR.CS.S32.F64", 9888 arm_VCVTR_CC_S32_F64: "VCVTR.CC.S32.F64", 9889 arm_VCVTR_MI_S32_F64: "VCVTR.MI.S32.F64", 9890 arm_VCVTR_PL_S32_F64: "VCVTR.PL.S32.F64", 9891 arm_VCVTR_VS_S32_F64: "VCVTR.VS.S32.F64", 9892 arm_VCVTR_VC_S32_F64: "VCVTR.VC.S32.F64", 9893 arm_VCVTR_HI_S32_F64: "VCVTR.HI.S32.F64", 9894 arm_VCVTR_LS_S32_F64: "VCVTR.LS.S32.F64", 9895 arm_VCVTR_GE_S32_F64: "VCVTR.GE.S32.F64", 9896 arm_VCVTR_LT_S32_F64: "VCVTR.LT.S32.F64", 9897 arm_VCVTR_GT_S32_F64: "VCVTR.GT.S32.F64", 9898 arm_VCVTR_LE_S32_F64: "VCVTR.LE.S32.F64", 9899 arm_VCVTR_S32_F64: "VCVTR.S32.F64", 9900 arm_VCVTR_ZZ_S32_F64: "VCVTR.ZZ.S32.F64", 9901 arm_VCVT_EQ_U32_F32: "VCVT.EQ.U32.F32", 9902 arm_VCVT_NE_U32_F32: "VCVT.NE.U32.F32", 9903 arm_VCVT_CS_U32_F32: "VCVT.CS.U32.F32", 9904 arm_VCVT_CC_U32_F32: "VCVT.CC.U32.F32", 9905 arm_VCVT_MI_U32_F32: "VCVT.MI.U32.F32", 9906 arm_VCVT_PL_U32_F32: "VCVT.PL.U32.F32", 9907 arm_VCVT_VS_U32_F32: "VCVT.VS.U32.F32", 9908 arm_VCVT_VC_U32_F32: "VCVT.VC.U32.F32", 9909 arm_VCVT_HI_U32_F32: "VCVT.HI.U32.F32", 9910 arm_VCVT_LS_U32_F32: "VCVT.LS.U32.F32", 9911 arm_VCVT_GE_U32_F32: "VCVT.GE.U32.F32", 9912 arm_VCVT_LT_U32_F32: "VCVT.LT.U32.F32", 9913 arm_VCVT_GT_U32_F32: "VCVT.GT.U32.F32", 9914 arm_VCVT_LE_U32_F32: "VCVT.LE.U32.F32", 9915 arm_VCVT_U32_F32: "VCVT.U32.F32", 9916 arm_VCVT_ZZ_U32_F32: "VCVT.ZZ.U32.F32", 9917 arm_VCVT_EQ_U32_F64: "VCVT.EQ.U32.F64", 9918 arm_VCVT_NE_U32_F64: "VCVT.NE.U32.F64", 9919 arm_VCVT_CS_U32_F64: "VCVT.CS.U32.F64", 9920 arm_VCVT_CC_U32_F64: "VCVT.CC.U32.F64", 9921 arm_VCVT_MI_U32_F64: "VCVT.MI.U32.F64", 9922 arm_VCVT_PL_U32_F64: "VCVT.PL.U32.F64", 9923 arm_VCVT_VS_U32_F64: "VCVT.VS.U32.F64", 9924 arm_VCVT_VC_U32_F64: "VCVT.VC.U32.F64", 9925 arm_VCVT_HI_U32_F64: "VCVT.HI.U32.F64", 9926 arm_VCVT_LS_U32_F64: "VCVT.LS.U32.F64", 9927 arm_VCVT_GE_U32_F64: "VCVT.GE.U32.F64", 9928 arm_VCVT_LT_U32_F64: "VCVT.LT.U32.F64", 9929 arm_VCVT_GT_U32_F64: "VCVT.GT.U32.F64", 9930 arm_VCVT_LE_U32_F64: "VCVT.LE.U32.F64", 9931 arm_VCVT_U32_F64: "VCVT.U32.F64", 9932 arm_VCVT_ZZ_U32_F64: "VCVT.ZZ.U32.F64", 9933 arm_VCVT_EQ_S32_F32: "VCVT.EQ.S32.F32", 9934 arm_VCVT_NE_S32_F32: "VCVT.NE.S32.F32", 9935 arm_VCVT_CS_S32_F32: "VCVT.CS.S32.F32", 9936 arm_VCVT_CC_S32_F32: "VCVT.CC.S32.F32", 9937 arm_VCVT_MI_S32_F32: "VCVT.MI.S32.F32", 9938 arm_VCVT_PL_S32_F32: "VCVT.PL.S32.F32", 9939 arm_VCVT_VS_S32_F32: "VCVT.VS.S32.F32", 9940 arm_VCVT_VC_S32_F32: "VCVT.VC.S32.F32", 9941 arm_VCVT_HI_S32_F32: "VCVT.HI.S32.F32", 9942 arm_VCVT_LS_S32_F32: "VCVT.LS.S32.F32", 9943 arm_VCVT_GE_S32_F32: "VCVT.GE.S32.F32", 9944 arm_VCVT_LT_S32_F32: "VCVT.LT.S32.F32", 9945 arm_VCVT_GT_S32_F32: "VCVT.GT.S32.F32", 9946 arm_VCVT_LE_S32_F32: "VCVT.LE.S32.F32", 9947 arm_VCVT_S32_F32: "VCVT.S32.F32", 9948 arm_VCVT_ZZ_S32_F32: "VCVT.ZZ.S32.F32", 9949 arm_VCVT_EQ_S32_F64: "VCVT.EQ.S32.F64", 9950 arm_VCVT_NE_S32_F64: "VCVT.NE.S32.F64", 9951 arm_VCVT_CS_S32_F64: "VCVT.CS.S32.F64", 9952 arm_VCVT_CC_S32_F64: "VCVT.CC.S32.F64", 9953 arm_VCVT_MI_S32_F64: "VCVT.MI.S32.F64", 9954 arm_VCVT_PL_S32_F64: "VCVT.PL.S32.F64", 9955 arm_VCVT_VS_S32_F64: "VCVT.VS.S32.F64", 9956 arm_VCVT_VC_S32_F64: "VCVT.VC.S32.F64", 9957 arm_VCVT_HI_S32_F64: "VCVT.HI.S32.F64", 9958 arm_VCVT_LS_S32_F64: "VCVT.LS.S32.F64", 9959 arm_VCVT_GE_S32_F64: "VCVT.GE.S32.F64", 9960 arm_VCVT_LT_S32_F64: "VCVT.LT.S32.F64", 9961 arm_VCVT_GT_S32_F64: "VCVT.GT.S32.F64", 9962 arm_VCVT_LE_S32_F64: "VCVT.LE.S32.F64", 9963 arm_VCVT_S32_F64: "VCVT.S32.F64", 9964 arm_VCVT_ZZ_S32_F64: "VCVT.ZZ.S32.F64", 9965 arm_VDIV_EQ_F32: "VDIV.EQ.F32", 9966 arm_VDIV_NE_F32: "VDIV.NE.F32", 9967 arm_VDIV_CS_F32: "VDIV.CS.F32", 9968 arm_VDIV_CC_F32: "VDIV.CC.F32", 9969 arm_VDIV_MI_F32: "VDIV.MI.F32", 9970 arm_VDIV_PL_F32: "VDIV.PL.F32", 9971 arm_VDIV_VS_F32: "VDIV.VS.F32", 9972 arm_VDIV_VC_F32: "VDIV.VC.F32", 9973 arm_VDIV_HI_F32: "VDIV.HI.F32", 9974 arm_VDIV_LS_F32: "VDIV.LS.F32", 9975 arm_VDIV_GE_F32: "VDIV.GE.F32", 9976 arm_VDIV_LT_F32: "VDIV.LT.F32", 9977 arm_VDIV_GT_F32: "VDIV.GT.F32", 9978 arm_VDIV_LE_F32: "VDIV.LE.F32", 9979 arm_VDIV_F32: "VDIV.F32", 9980 arm_VDIV_ZZ_F32: "VDIV.ZZ.F32", 9981 arm_VDIV_EQ_F64: "VDIV.EQ.F64", 9982 arm_VDIV_NE_F64: "VDIV.NE.F64", 9983 arm_VDIV_CS_F64: "VDIV.CS.F64", 9984 arm_VDIV_CC_F64: "VDIV.CC.F64", 9985 arm_VDIV_MI_F64: "VDIV.MI.F64", 9986 arm_VDIV_PL_F64: "VDIV.PL.F64", 9987 arm_VDIV_VS_F64: "VDIV.VS.F64", 9988 arm_VDIV_VC_F64: "VDIV.VC.F64", 9989 arm_VDIV_HI_F64: "VDIV.HI.F64", 9990 arm_VDIV_LS_F64: "VDIV.LS.F64", 9991 arm_VDIV_GE_F64: "VDIV.GE.F64", 9992 arm_VDIV_LT_F64: "VDIV.LT.F64", 9993 arm_VDIV_GT_F64: "VDIV.GT.F64", 9994 arm_VDIV_LE_F64: "VDIV.LE.F64", 9995 arm_VDIV_F64: "VDIV.F64", 9996 arm_VDIV_ZZ_F64: "VDIV.ZZ.F64", 9997 arm_VLDR_EQ: "VLDR.EQ", 9998 arm_VLDR_NE: "VLDR.NE", 9999 arm_VLDR_CS: "VLDR.CS", 10000 arm_VLDR_CC: "VLDR.CC", 10001 arm_VLDR_MI: "VLDR.MI", 10002 arm_VLDR_PL: "VLDR.PL", 10003 arm_VLDR_VS: "VLDR.VS", 10004 arm_VLDR_VC: "VLDR.VC", 10005 arm_VLDR_HI: "VLDR.HI", 10006 arm_VLDR_LS: "VLDR.LS", 10007 arm_VLDR_GE: "VLDR.GE", 10008 arm_VLDR_LT: "VLDR.LT", 10009 arm_VLDR_GT: "VLDR.GT", 10010 arm_VLDR_LE: "VLDR.LE", 10011 arm_VLDR: "VLDR", 10012 arm_VLDR_ZZ: "VLDR.ZZ", 10013 arm_VMLA_EQ_F32: "VMLA.EQ.F32", 10014 arm_VMLA_NE_F32: "VMLA.NE.F32", 10015 arm_VMLA_CS_F32: "VMLA.CS.F32", 10016 arm_VMLA_CC_F32: "VMLA.CC.F32", 10017 arm_VMLA_MI_F32: "VMLA.MI.F32", 10018 arm_VMLA_PL_F32: "VMLA.PL.F32", 10019 arm_VMLA_VS_F32: "VMLA.VS.F32", 10020 arm_VMLA_VC_F32: "VMLA.VC.F32", 10021 arm_VMLA_HI_F32: "VMLA.HI.F32", 10022 arm_VMLA_LS_F32: "VMLA.LS.F32", 10023 arm_VMLA_GE_F32: "VMLA.GE.F32", 10024 arm_VMLA_LT_F32: "VMLA.LT.F32", 10025 arm_VMLA_GT_F32: "VMLA.GT.F32", 10026 arm_VMLA_LE_F32: "VMLA.LE.F32", 10027 arm_VMLA_F32: "VMLA.F32", 10028 arm_VMLA_ZZ_F32: "VMLA.ZZ.F32", 10029 arm_VMLA_EQ_F64: "VMLA.EQ.F64", 10030 arm_VMLA_NE_F64: "VMLA.NE.F64", 10031 arm_VMLA_CS_F64: "VMLA.CS.F64", 10032 arm_VMLA_CC_F64: "VMLA.CC.F64", 10033 arm_VMLA_MI_F64: "VMLA.MI.F64", 10034 arm_VMLA_PL_F64: "VMLA.PL.F64", 10035 arm_VMLA_VS_F64: "VMLA.VS.F64", 10036 arm_VMLA_VC_F64: "VMLA.VC.F64", 10037 arm_VMLA_HI_F64: "VMLA.HI.F64", 10038 arm_VMLA_LS_F64: "VMLA.LS.F64", 10039 arm_VMLA_GE_F64: "VMLA.GE.F64", 10040 arm_VMLA_LT_F64: "VMLA.LT.F64", 10041 arm_VMLA_GT_F64: "VMLA.GT.F64", 10042 arm_VMLA_LE_F64: "VMLA.LE.F64", 10043 arm_VMLA_F64: "VMLA.F64", 10044 arm_VMLA_ZZ_F64: "VMLA.ZZ.F64", 10045 arm_VMLS_EQ_F32: "VMLS.EQ.F32", 10046 arm_VMLS_NE_F32: "VMLS.NE.F32", 10047 arm_VMLS_CS_F32: "VMLS.CS.F32", 10048 arm_VMLS_CC_F32: "VMLS.CC.F32", 10049 arm_VMLS_MI_F32: "VMLS.MI.F32", 10050 arm_VMLS_PL_F32: "VMLS.PL.F32", 10051 arm_VMLS_VS_F32: "VMLS.VS.F32", 10052 arm_VMLS_VC_F32: "VMLS.VC.F32", 10053 arm_VMLS_HI_F32: "VMLS.HI.F32", 10054 arm_VMLS_LS_F32: "VMLS.LS.F32", 10055 arm_VMLS_GE_F32: "VMLS.GE.F32", 10056 arm_VMLS_LT_F32: "VMLS.LT.F32", 10057 arm_VMLS_GT_F32: "VMLS.GT.F32", 10058 arm_VMLS_LE_F32: "VMLS.LE.F32", 10059 arm_VMLS_F32: "VMLS.F32", 10060 arm_VMLS_ZZ_F32: "VMLS.ZZ.F32", 10061 arm_VMLS_EQ_F64: "VMLS.EQ.F64", 10062 arm_VMLS_NE_F64: "VMLS.NE.F64", 10063 arm_VMLS_CS_F64: "VMLS.CS.F64", 10064 arm_VMLS_CC_F64: "VMLS.CC.F64", 10065 arm_VMLS_MI_F64: "VMLS.MI.F64", 10066 arm_VMLS_PL_F64: "VMLS.PL.F64", 10067 arm_VMLS_VS_F64: "VMLS.VS.F64", 10068 arm_VMLS_VC_F64: "VMLS.VC.F64", 10069 arm_VMLS_HI_F64: "VMLS.HI.F64", 10070 arm_VMLS_LS_F64: "VMLS.LS.F64", 10071 arm_VMLS_GE_F64: "VMLS.GE.F64", 10072 arm_VMLS_LT_F64: "VMLS.LT.F64", 10073 arm_VMLS_GT_F64: "VMLS.GT.F64", 10074 arm_VMLS_LE_F64: "VMLS.LE.F64", 10075 arm_VMLS_F64: "VMLS.F64", 10076 arm_VMLS_ZZ_F64: "VMLS.ZZ.F64", 10077 arm_VMOV_EQ: "VMOV.EQ", 10078 arm_VMOV_NE: "VMOV.NE", 10079 arm_VMOV_CS: "VMOV.CS", 10080 arm_VMOV_CC: "VMOV.CC", 10081 arm_VMOV_MI: "VMOV.MI", 10082 arm_VMOV_PL: "VMOV.PL", 10083 arm_VMOV_VS: "VMOV.VS", 10084 arm_VMOV_VC: "VMOV.VC", 10085 arm_VMOV_HI: "VMOV.HI", 10086 arm_VMOV_LS: "VMOV.LS", 10087 arm_VMOV_GE: "VMOV.GE", 10088 arm_VMOV_LT: "VMOV.LT", 10089 arm_VMOV_GT: "VMOV.GT", 10090 arm_VMOV_LE: "VMOV.LE", 10091 arm_VMOV: "VMOV", 10092 arm_VMOV_ZZ: "VMOV.ZZ", 10093 arm_VMOV_EQ_32: "VMOV.EQ.32", 10094 arm_VMOV_NE_32: "VMOV.NE.32", 10095 arm_VMOV_CS_32: "VMOV.CS.32", 10096 arm_VMOV_CC_32: "VMOV.CC.32", 10097 arm_VMOV_MI_32: "VMOV.MI.32", 10098 arm_VMOV_PL_32: "VMOV.PL.32", 10099 arm_VMOV_VS_32: "VMOV.VS.32", 10100 arm_VMOV_VC_32: "VMOV.VC.32", 10101 arm_VMOV_HI_32: "VMOV.HI.32", 10102 arm_VMOV_LS_32: "VMOV.LS.32", 10103 arm_VMOV_GE_32: "VMOV.GE.32", 10104 arm_VMOV_LT_32: "VMOV.LT.32", 10105 arm_VMOV_GT_32: "VMOV.GT.32", 10106 arm_VMOV_LE_32: "VMOV.LE.32", 10107 arm_VMOV_32: "VMOV.32", 10108 arm_VMOV_ZZ_32: "VMOV.ZZ.32", 10109 arm_VMOV_EQ_F32: "VMOV.EQ.F32", 10110 arm_VMOV_NE_F32: "VMOV.NE.F32", 10111 arm_VMOV_CS_F32: "VMOV.CS.F32", 10112 arm_VMOV_CC_F32: "VMOV.CC.F32", 10113 arm_VMOV_MI_F32: "VMOV.MI.F32", 10114 arm_VMOV_PL_F32: "VMOV.PL.F32", 10115 arm_VMOV_VS_F32: "VMOV.VS.F32", 10116 arm_VMOV_VC_F32: "VMOV.VC.F32", 10117 arm_VMOV_HI_F32: "VMOV.HI.F32", 10118 arm_VMOV_LS_F32: "VMOV.LS.F32", 10119 arm_VMOV_GE_F32: "VMOV.GE.F32", 10120 arm_VMOV_LT_F32: "VMOV.LT.F32", 10121 arm_VMOV_GT_F32: "VMOV.GT.F32", 10122 arm_VMOV_LE_F32: "VMOV.LE.F32", 10123 arm_VMOV_F32: "VMOV.F32", 10124 arm_VMOV_ZZ_F32: "VMOV.ZZ.F32", 10125 arm_VMOV_EQ_F64: "VMOV.EQ.F64", 10126 arm_VMOV_NE_F64: "VMOV.NE.F64", 10127 arm_VMOV_CS_F64: "VMOV.CS.F64", 10128 arm_VMOV_CC_F64: "VMOV.CC.F64", 10129 arm_VMOV_MI_F64: "VMOV.MI.F64", 10130 arm_VMOV_PL_F64: "VMOV.PL.F64", 10131 arm_VMOV_VS_F64: "VMOV.VS.F64", 10132 arm_VMOV_VC_F64: "VMOV.VC.F64", 10133 arm_VMOV_HI_F64: "VMOV.HI.F64", 10134 arm_VMOV_LS_F64: "VMOV.LS.F64", 10135 arm_VMOV_GE_F64: "VMOV.GE.F64", 10136 arm_VMOV_LT_F64: "VMOV.LT.F64", 10137 arm_VMOV_GT_F64: "VMOV.GT.F64", 10138 arm_VMOV_LE_F64: "VMOV.LE.F64", 10139 arm_VMOV_F64: "VMOV.F64", 10140 arm_VMOV_ZZ_F64: "VMOV.ZZ.F64", 10141 arm_VMRS_EQ: "VMRS.EQ", 10142 arm_VMRS_NE: "VMRS.NE", 10143 arm_VMRS_CS: "VMRS.CS", 10144 arm_VMRS_CC: "VMRS.CC", 10145 arm_VMRS_MI: "VMRS.MI", 10146 arm_VMRS_PL: "VMRS.PL", 10147 arm_VMRS_VS: "VMRS.VS", 10148 arm_VMRS_VC: "VMRS.VC", 10149 arm_VMRS_HI: "VMRS.HI", 10150 arm_VMRS_LS: "VMRS.LS", 10151 arm_VMRS_GE: "VMRS.GE", 10152 arm_VMRS_LT: "VMRS.LT", 10153 arm_VMRS_GT: "VMRS.GT", 10154 arm_VMRS_LE: "VMRS.LE", 10155 arm_VMRS: "VMRS", 10156 arm_VMRS_ZZ: "VMRS.ZZ", 10157 arm_VMSR_EQ: "VMSR.EQ", 10158 arm_VMSR_NE: "VMSR.NE", 10159 arm_VMSR_CS: "VMSR.CS", 10160 arm_VMSR_CC: "VMSR.CC", 10161 arm_VMSR_MI: "VMSR.MI", 10162 arm_VMSR_PL: "VMSR.PL", 10163 arm_VMSR_VS: "VMSR.VS", 10164 arm_VMSR_VC: "VMSR.VC", 10165 arm_VMSR_HI: "VMSR.HI", 10166 arm_VMSR_LS: "VMSR.LS", 10167 arm_VMSR_GE: "VMSR.GE", 10168 arm_VMSR_LT: "VMSR.LT", 10169 arm_VMSR_GT: "VMSR.GT", 10170 arm_VMSR_LE: "VMSR.LE", 10171 arm_VMSR: "VMSR", 10172 arm_VMSR_ZZ: "VMSR.ZZ", 10173 arm_VMUL_EQ_F32: "VMUL.EQ.F32", 10174 arm_VMUL_NE_F32: "VMUL.NE.F32", 10175 arm_VMUL_CS_F32: "VMUL.CS.F32", 10176 arm_VMUL_CC_F32: "VMUL.CC.F32", 10177 arm_VMUL_MI_F32: "VMUL.MI.F32", 10178 arm_VMUL_PL_F32: "VMUL.PL.F32", 10179 arm_VMUL_VS_F32: "VMUL.VS.F32", 10180 arm_VMUL_VC_F32: "VMUL.VC.F32", 10181 arm_VMUL_HI_F32: "VMUL.HI.F32", 10182 arm_VMUL_LS_F32: "VMUL.LS.F32", 10183 arm_VMUL_GE_F32: "VMUL.GE.F32", 10184 arm_VMUL_LT_F32: "VMUL.LT.F32", 10185 arm_VMUL_GT_F32: "VMUL.GT.F32", 10186 arm_VMUL_LE_F32: "VMUL.LE.F32", 10187 arm_VMUL_F32: "VMUL.F32", 10188 arm_VMUL_ZZ_F32: "VMUL.ZZ.F32", 10189 arm_VMUL_EQ_F64: "VMUL.EQ.F64", 10190 arm_VMUL_NE_F64: "VMUL.NE.F64", 10191 arm_VMUL_CS_F64: "VMUL.CS.F64", 10192 arm_VMUL_CC_F64: "VMUL.CC.F64", 10193 arm_VMUL_MI_F64: "VMUL.MI.F64", 10194 arm_VMUL_PL_F64: "VMUL.PL.F64", 10195 arm_VMUL_VS_F64: "VMUL.VS.F64", 10196 arm_VMUL_VC_F64: "VMUL.VC.F64", 10197 arm_VMUL_HI_F64: "VMUL.HI.F64", 10198 arm_VMUL_LS_F64: "VMUL.LS.F64", 10199 arm_VMUL_GE_F64: "VMUL.GE.F64", 10200 arm_VMUL_LT_F64: "VMUL.LT.F64", 10201 arm_VMUL_GT_F64: "VMUL.GT.F64", 10202 arm_VMUL_LE_F64: "VMUL.LE.F64", 10203 arm_VMUL_F64: "VMUL.F64", 10204 arm_VMUL_ZZ_F64: "VMUL.ZZ.F64", 10205 arm_VNEG_EQ_F32: "VNEG.EQ.F32", 10206 arm_VNEG_NE_F32: "VNEG.NE.F32", 10207 arm_VNEG_CS_F32: "VNEG.CS.F32", 10208 arm_VNEG_CC_F32: "VNEG.CC.F32", 10209 arm_VNEG_MI_F32: "VNEG.MI.F32", 10210 arm_VNEG_PL_F32: "VNEG.PL.F32", 10211 arm_VNEG_VS_F32: "VNEG.VS.F32", 10212 arm_VNEG_VC_F32: "VNEG.VC.F32", 10213 arm_VNEG_HI_F32: "VNEG.HI.F32", 10214 arm_VNEG_LS_F32: "VNEG.LS.F32", 10215 arm_VNEG_GE_F32: "VNEG.GE.F32", 10216 arm_VNEG_LT_F32: "VNEG.LT.F32", 10217 arm_VNEG_GT_F32: "VNEG.GT.F32", 10218 arm_VNEG_LE_F32: "VNEG.LE.F32", 10219 arm_VNEG_F32: "VNEG.F32", 10220 arm_VNEG_ZZ_F32: "VNEG.ZZ.F32", 10221 arm_VNEG_EQ_F64: "VNEG.EQ.F64", 10222 arm_VNEG_NE_F64: "VNEG.NE.F64", 10223 arm_VNEG_CS_F64: "VNEG.CS.F64", 10224 arm_VNEG_CC_F64: "VNEG.CC.F64", 10225 arm_VNEG_MI_F64: "VNEG.MI.F64", 10226 arm_VNEG_PL_F64: "VNEG.PL.F64", 10227 arm_VNEG_VS_F64: "VNEG.VS.F64", 10228 arm_VNEG_VC_F64: "VNEG.VC.F64", 10229 arm_VNEG_HI_F64: "VNEG.HI.F64", 10230 arm_VNEG_LS_F64: "VNEG.LS.F64", 10231 arm_VNEG_GE_F64: "VNEG.GE.F64", 10232 arm_VNEG_LT_F64: "VNEG.LT.F64", 10233 arm_VNEG_GT_F64: "VNEG.GT.F64", 10234 arm_VNEG_LE_F64: "VNEG.LE.F64", 10235 arm_VNEG_F64: "VNEG.F64", 10236 arm_VNEG_ZZ_F64: "VNEG.ZZ.F64", 10237 arm_VNMLS_EQ_F32: "VNMLS.EQ.F32", 10238 arm_VNMLS_NE_F32: "VNMLS.NE.F32", 10239 arm_VNMLS_CS_F32: "VNMLS.CS.F32", 10240 arm_VNMLS_CC_F32: "VNMLS.CC.F32", 10241 arm_VNMLS_MI_F32: "VNMLS.MI.F32", 10242 arm_VNMLS_PL_F32: "VNMLS.PL.F32", 10243 arm_VNMLS_VS_F32: "VNMLS.VS.F32", 10244 arm_VNMLS_VC_F32: "VNMLS.VC.F32", 10245 arm_VNMLS_HI_F32: "VNMLS.HI.F32", 10246 arm_VNMLS_LS_F32: "VNMLS.LS.F32", 10247 arm_VNMLS_GE_F32: "VNMLS.GE.F32", 10248 arm_VNMLS_LT_F32: "VNMLS.LT.F32", 10249 arm_VNMLS_GT_F32: "VNMLS.GT.F32", 10250 arm_VNMLS_LE_F32: "VNMLS.LE.F32", 10251 arm_VNMLS_F32: "VNMLS.F32", 10252 arm_VNMLS_ZZ_F32: "VNMLS.ZZ.F32", 10253 arm_VNMLS_EQ_F64: "VNMLS.EQ.F64", 10254 arm_VNMLS_NE_F64: "VNMLS.NE.F64", 10255 arm_VNMLS_CS_F64: "VNMLS.CS.F64", 10256 arm_VNMLS_CC_F64: "VNMLS.CC.F64", 10257 arm_VNMLS_MI_F64: "VNMLS.MI.F64", 10258 arm_VNMLS_PL_F64: "VNMLS.PL.F64", 10259 arm_VNMLS_VS_F64: "VNMLS.VS.F64", 10260 arm_VNMLS_VC_F64: "VNMLS.VC.F64", 10261 arm_VNMLS_HI_F64: "VNMLS.HI.F64", 10262 arm_VNMLS_LS_F64: "VNMLS.LS.F64", 10263 arm_VNMLS_GE_F64: "VNMLS.GE.F64", 10264 arm_VNMLS_LT_F64: "VNMLS.LT.F64", 10265 arm_VNMLS_GT_F64: "VNMLS.GT.F64", 10266 arm_VNMLS_LE_F64: "VNMLS.LE.F64", 10267 arm_VNMLS_F64: "VNMLS.F64", 10268 arm_VNMLS_ZZ_F64: "VNMLS.ZZ.F64", 10269 arm_VNMLA_EQ_F32: "VNMLA.EQ.F32", 10270 arm_VNMLA_NE_F32: "VNMLA.NE.F32", 10271 arm_VNMLA_CS_F32: "VNMLA.CS.F32", 10272 arm_VNMLA_CC_F32: "VNMLA.CC.F32", 10273 arm_VNMLA_MI_F32: "VNMLA.MI.F32", 10274 arm_VNMLA_PL_F32: "VNMLA.PL.F32", 10275 arm_VNMLA_VS_F32: "VNMLA.VS.F32", 10276 arm_VNMLA_VC_F32: "VNMLA.VC.F32", 10277 arm_VNMLA_HI_F32: "VNMLA.HI.F32", 10278 arm_VNMLA_LS_F32: "VNMLA.LS.F32", 10279 arm_VNMLA_GE_F32: "VNMLA.GE.F32", 10280 arm_VNMLA_LT_F32: "VNMLA.LT.F32", 10281 arm_VNMLA_GT_F32: "VNMLA.GT.F32", 10282 arm_VNMLA_LE_F32: "VNMLA.LE.F32", 10283 arm_VNMLA_F32: "VNMLA.F32", 10284 arm_VNMLA_ZZ_F32: "VNMLA.ZZ.F32", 10285 arm_VNMLA_EQ_F64: "VNMLA.EQ.F64", 10286 arm_VNMLA_NE_F64: "VNMLA.NE.F64", 10287 arm_VNMLA_CS_F64: "VNMLA.CS.F64", 10288 arm_VNMLA_CC_F64: "VNMLA.CC.F64", 10289 arm_VNMLA_MI_F64: "VNMLA.MI.F64", 10290 arm_VNMLA_PL_F64: "VNMLA.PL.F64", 10291 arm_VNMLA_VS_F64: "VNMLA.VS.F64", 10292 arm_VNMLA_VC_F64: "VNMLA.VC.F64", 10293 arm_VNMLA_HI_F64: "VNMLA.HI.F64", 10294 arm_VNMLA_LS_F64: "VNMLA.LS.F64", 10295 arm_VNMLA_GE_F64: "VNMLA.GE.F64", 10296 arm_VNMLA_LT_F64: "VNMLA.LT.F64", 10297 arm_VNMLA_GT_F64: "VNMLA.GT.F64", 10298 arm_VNMLA_LE_F64: "VNMLA.LE.F64", 10299 arm_VNMLA_F64: "VNMLA.F64", 10300 arm_VNMLA_ZZ_F64: "VNMLA.ZZ.F64", 10301 arm_VNMUL_EQ_F32: "VNMUL.EQ.F32", 10302 arm_VNMUL_NE_F32: "VNMUL.NE.F32", 10303 arm_VNMUL_CS_F32: "VNMUL.CS.F32", 10304 arm_VNMUL_CC_F32: "VNMUL.CC.F32", 10305 arm_VNMUL_MI_F32: "VNMUL.MI.F32", 10306 arm_VNMUL_PL_F32: "VNMUL.PL.F32", 10307 arm_VNMUL_VS_F32: "VNMUL.VS.F32", 10308 arm_VNMUL_VC_F32: "VNMUL.VC.F32", 10309 arm_VNMUL_HI_F32: "VNMUL.HI.F32", 10310 arm_VNMUL_LS_F32: "VNMUL.LS.F32", 10311 arm_VNMUL_GE_F32: "VNMUL.GE.F32", 10312 arm_VNMUL_LT_F32: "VNMUL.LT.F32", 10313 arm_VNMUL_GT_F32: "VNMUL.GT.F32", 10314 arm_VNMUL_LE_F32: "VNMUL.LE.F32", 10315 arm_VNMUL_F32: "VNMUL.F32", 10316 arm_VNMUL_ZZ_F32: "VNMUL.ZZ.F32", 10317 arm_VNMUL_EQ_F64: "VNMUL.EQ.F64", 10318 arm_VNMUL_NE_F64: "VNMUL.NE.F64", 10319 arm_VNMUL_CS_F64: "VNMUL.CS.F64", 10320 arm_VNMUL_CC_F64: "VNMUL.CC.F64", 10321 arm_VNMUL_MI_F64: "VNMUL.MI.F64", 10322 arm_VNMUL_PL_F64: "VNMUL.PL.F64", 10323 arm_VNMUL_VS_F64: "VNMUL.VS.F64", 10324 arm_VNMUL_VC_F64: "VNMUL.VC.F64", 10325 arm_VNMUL_HI_F64: "VNMUL.HI.F64", 10326 arm_VNMUL_LS_F64: "VNMUL.LS.F64", 10327 arm_VNMUL_GE_F64: "VNMUL.GE.F64", 10328 arm_VNMUL_LT_F64: "VNMUL.LT.F64", 10329 arm_VNMUL_GT_F64: "VNMUL.GT.F64", 10330 arm_VNMUL_LE_F64: "VNMUL.LE.F64", 10331 arm_VNMUL_F64: "VNMUL.F64", 10332 arm_VNMUL_ZZ_F64: "VNMUL.ZZ.F64", 10333 arm_VSQRT_EQ_F32: "VSQRT.EQ.F32", 10334 arm_VSQRT_NE_F32: "VSQRT.NE.F32", 10335 arm_VSQRT_CS_F32: "VSQRT.CS.F32", 10336 arm_VSQRT_CC_F32: "VSQRT.CC.F32", 10337 arm_VSQRT_MI_F32: "VSQRT.MI.F32", 10338 arm_VSQRT_PL_F32: "VSQRT.PL.F32", 10339 arm_VSQRT_VS_F32: "VSQRT.VS.F32", 10340 arm_VSQRT_VC_F32: "VSQRT.VC.F32", 10341 arm_VSQRT_HI_F32: "VSQRT.HI.F32", 10342 arm_VSQRT_LS_F32: "VSQRT.LS.F32", 10343 arm_VSQRT_GE_F32: "VSQRT.GE.F32", 10344 arm_VSQRT_LT_F32: "VSQRT.LT.F32", 10345 arm_VSQRT_GT_F32: "VSQRT.GT.F32", 10346 arm_VSQRT_LE_F32: "VSQRT.LE.F32", 10347 arm_VSQRT_F32: "VSQRT.F32", 10348 arm_VSQRT_ZZ_F32: "VSQRT.ZZ.F32", 10349 arm_VSQRT_EQ_F64: "VSQRT.EQ.F64", 10350 arm_VSQRT_NE_F64: "VSQRT.NE.F64", 10351 arm_VSQRT_CS_F64: "VSQRT.CS.F64", 10352 arm_VSQRT_CC_F64: "VSQRT.CC.F64", 10353 arm_VSQRT_MI_F64: "VSQRT.MI.F64", 10354 arm_VSQRT_PL_F64: "VSQRT.PL.F64", 10355 arm_VSQRT_VS_F64: "VSQRT.VS.F64", 10356 arm_VSQRT_VC_F64: "VSQRT.VC.F64", 10357 arm_VSQRT_HI_F64: "VSQRT.HI.F64", 10358 arm_VSQRT_LS_F64: "VSQRT.LS.F64", 10359 arm_VSQRT_GE_F64: "VSQRT.GE.F64", 10360 arm_VSQRT_LT_F64: "VSQRT.LT.F64", 10361 arm_VSQRT_GT_F64: "VSQRT.GT.F64", 10362 arm_VSQRT_LE_F64: "VSQRT.LE.F64", 10363 arm_VSQRT_F64: "VSQRT.F64", 10364 arm_VSQRT_ZZ_F64: "VSQRT.ZZ.F64", 10365 arm_VSTR_EQ: "VSTR.EQ", 10366 arm_VSTR_NE: "VSTR.NE", 10367 arm_VSTR_CS: "VSTR.CS", 10368 arm_VSTR_CC: "VSTR.CC", 10369 arm_VSTR_MI: "VSTR.MI", 10370 arm_VSTR_PL: "VSTR.PL", 10371 arm_VSTR_VS: "VSTR.VS", 10372 arm_VSTR_VC: "VSTR.VC", 10373 arm_VSTR_HI: "VSTR.HI", 10374 arm_VSTR_LS: "VSTR.LS", 10375 arm_VSTR_GE: "VSTR.GE", 10376 arm_VSTR_LT: "VSTR.LT", 10377 arm_VSTR_GT: "VSTR.GT", 10378 arm_VSTR_LE: "VSTR.LE", 10379 arm_VSTR: "VSTR", 10380 arm_VSTR_ZZ: "VSTR.ZZ", 10381 arm_VSUB_EQ_F32: "VSUB.EQ.F32", 10382 arm_VSUB_NE_F32: "VSUB.NE.F32", 10383 arm_VSUB_CS_F32: "VSUB.CS.F32", 10384 arm_VSUB_CC_F32: "VSUB.CC.F32", 10385 arm_VSUB_MI_F32: "VSUB.MI.F32", 10386 arm_VSUB_PL_F32: "VSUB.PL.F32", 10387 arm_VSUB_VS_F32: "VSUB.VS.F32", 10388 arm_VSUB_VC_F32: "VSUB.VC.F32", 10389 arm_VSUB_HI_F32: "VSUB.HI.F32", 10390 arm_VSUB_LS_F32: "VSUB.LS.F32", 10391 arm_VSUB_GE_F32: "VSUB.GE.F32", 10392 arm_VSUB_LT_F32: "VSUB.LT.F32", 10393 arm_VSUB_GT_F32: "VSUB.GT.F32", 10394 arm_VSUB_LE_F32: "VSUB.LE.F32", 10395 arm_VSUB_F32: "VSUB.F32", 10396 arm_VSUB_ZZ_F32: "VSUB.ZZ.F32", 10397 arm_VSUB_EQ_F64: "VSUB.EQ.F64", 10398 arm_VSUB_NE_F64: "VSUB.NE.F64", 10399 arm_VSUB_CS_F64: "VSUB.CS.F64", 10400 arm_VSUB_CC_F64: "VSUB.CC.F64", 10401 arm_VSUB_MI_F64: "VSUB.MI.F64", 10402 arm_VSUB_PL_F64: "VSUB.PL.F64", 10403 arm_VSUB_VS_F64: "VSUB.VS.F64", 10404 arm_VSUB_VC_F64: "VSUB.VC.F64", 10405 arm_VSUB_HI_F64: "VSUB.HI.F64", 10406 arm_VSUB_LS_F64: "VSUB.LS.F64", 10407 arm_VSUB_GE_F64: "VSUB.GE.F64", 10408 arm_VSUB_LT_F64: "VSUB.LT.F64", 10409 arm_VSUB_GT_F64: "VSUB.GT.F64", 10410 arm_VSUB_LE_F64: "VSUB.LE.F64", 10411 arm_VSUB_F64: "VSUB.F64", 10412 arm_VSUB_ZZ_F64: "VSUB.ZZ.F64", 10413 arm_WFE_EQ: "WFE.EQ", 10414 arm_WFE_NE: "WFE.NE", 10415 arm_WFE_CS: "WFE.CS", 10416 arm_WFE_CC: "WFE.CC", 10417 arm_WFE_MI: "WFE.MI", 10418 arm_WFE_PL: "WFE.PL", 10419 arm_WFE_VS: "WFE.VS", 10420 arm_WFE_VC: "WFE.VC", 10421 arm_WFE_HI: "WFE.HI", 10422 arm_WFE_LS: "WFE.LS", 10423 arm_WFE_GE: "WFE.GE", 10424 arm_WFE_LT: "WFE.LT", 10425 arm_WFE_GT: "WFE.GT", 10426 arm_WFE_LE: "WFE.LE", 10427 arm_WFE: "WFE", 10428 arm_WFE_ZZ: "WFE.ZZ", 10429 arm_WFI_EQ: "WFI.EQ", 10430 arm_WFI_NE: "WFI.NE", 10431 arm_WFI_CS: "WFI.CS", 10432 arm_WFI_CC: "WFI.CC", 10433 arm_WFI_MI: "WFI.MI", 10434 arm_WFI_PL: "WFI.PL", 10435 arm_WFI_VS: "WFI.VS", 10436 arm_WFI_VC: "WFI.VC", 10437 arm_WFI_HI: "WFI.HI", 10438 arm_WFI_LS: "WFI.LS", 10439 arm_WFI_GE: "WFI.GE", 10440 arm_WFI_LT: "WFI.LT", 10441 arm_WFI_GT: "WFI.GT", 10442 arm_WFI_LE: "WFI.LE", 10443 arm_WFI: "WFI", 10444 arm_WFI_ZZ: "WFI.ZZ", 10445 arm_YIELD_EQ: "YIELD.EQ", 10446 arm_YIELD_NE: "YIELD.NE", 10447 arm_YIELD_CS: "YIELD.CS", 10448 arm_YIELD_CC: "YIELD.CC", 10449 arm_YIELD_MI: "YIELD.MI", 10450 arm_YIELD_PL: "YIELD.PL", 10451 arm_YIELD_VS: "YIELD.VS", 10452 arm_YIELD_VC: "YIELD.VC", 10453 arm_YIELD_HI: "YIELD.HI", 10454 arm_YIELD_LS: "YIELD.LS", 10455 arm_YIELD_GE: "YIELD.GE", 10456 arm_YIELD_LT: "YIELD.LT", 10457 arm_YIELD_GT: "YIELD.GT", 10458 arm_YIELD_LE: "YIELD.LE", 10459 arm_YIELD: "YIELD", 10460 arm_YIELD_ZZ: "YIELD.ZZ", 10461 } 10462 10463 var arm_instFormats = [...]arm_instFormat{ 10464 {0x0fe00000, 0x02a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // ADC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|1|S|Rn:4|Rd:4|imm12:12 10465 {0x0fe00090, 0x00a00010, 4, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10466 {0x0fe00010, 0x00a00000, 2, arm_ADC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10467 {0x0fe00000, 0x02800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // ADD{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|0|0|S|Rn:4|Rd:4|imm12:12 10468 {0x0fe00090, 0x00800010, 4, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10469 {0x0fe00010, 0x00800000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10470 {0x0fef0000, 0x028d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_SP, arm_arg_const}}, // ADD{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|1|0|0|S|1|1|0|1|Rd:4|imm12:12 10471 {0x0fef0010, 0x008d0000, 2, arm_ADD_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // ADD{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|1|0|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 10472 {0x0fe00000, 0x02000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // AND{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|0|S|Rn:4|Rd:4|imm12:12 10473 {0x0fe00090, 0x00000010, 4, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10474 {0x0fe00010, 0x00000000, 2, arm_AND_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10475 {0x0fef0070, 0x01a00040, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // ASR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|0|0|Rm:4 10476 {0x0fef00f0, 0x01a00050, 4, arm_ASR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_8}}, // ASR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|0|1|Rn:4 10477 {0x0f000000, 0x0a000000, 4, arm_B_EQ, 0x1c04, arm_instArgs{arm_arg_label24}}, // B<c> <label24> cond:4|1|0|1|0|imm24:24 10478 {0x0fe0007f, 0x07c0001f, 4, arm_BFC_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_imm5, arm_arg_lsb_width}}, // BFC<c> <Rd>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|1|1|1|1 10479 {0x0fe00070, 0x07c00010, 2, arm_BFI_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5, arm_arg_lsb_width}}, // BFI<c> <Rd>,<Rn>,#<lsb>,#<width> cond:4|0|1|1|1|1|1|0|msb:5|Rd:4|lsb:5|0|0|1|Rn:4 10480 {0x0fe00000, 0x03c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // BIC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|1|0|S|Rn:4|Rd:4|imm12:12 10481 {0x0fe00090, 0x01c00010, 4, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10482 {0x0fe00010, 0x01c00000, 2, arm_BIC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10483 {0x0ff000f0, 0x01200070, 4, arm_BKPT_EQ, 0x1c04, arm_instArgs{arm_arg_imm_12at8_4at0}}, // BKPT<c> #<imm12+4> cond:4|0|0|0|1|0|0|1|0|imm12:12|0|1|1|1|imm4:4 10484 {0x0f000000, 0x0b000000, 4, arm_BL_EQ, 0x1c04, arm_instArgs{arm_arg_label24}}, // BL<c> <label24> cond:4|1|0|1|1|imm24:24 10485 {0xfe000000, 0xfa000000, 4, arm_BLX, 0x0, arm_instArgs{arm_arg_label24H}}, // BLX <label24H> 1|1|1|1|1|0|1|H|imm24:24 10486 {0x0ffffff0, 0x012fff30, 4, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10487 {0x0ff000f0, 0x012fff30, 3, arm_BLX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BLX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10488 {0x0ffffff0, 0x012fff10, 4, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10489 {0x0ff000f0, 0x012fff10, 3, arm_BX_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BX<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10490 {0x0ffffff0, 0x012fff20, 4, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 10491 {0x0ff000f0, 0x012fff20, 3, arm_BXJ_EQ, 0x1c04, arm_instArgs{arm_arg_R_0}}, // BXJ<c> <Rm> cond:4|0|0|0|1|0|0|1|0|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|0|0|1|0|Rm:4 10492 {0xffffffff, 0xf57ff01f, 4, arm_CLREX, 0x0, arm_instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) 10493 {0xfff000f0, 0xf57ff01f, 3, arm_CLREX, 0x0, arm_instArgs{}}, // CLREX 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|1|(1)|(1)|(1)|(1) 10494 {0x0fff0ff0, 0x016f0f10, 4, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10495 {0x0ff000f0, 0x016f0f10, 3, arm_CLZ_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // CLZ<c> <Rd>,<Rm> cond:4|0|0|0|1|0|1|1|0|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10496 {0x0ff0f000, 0x03700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10497 {0x0ff00000, 0x03700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // CMN<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10498 {0x0ff0f090, 0x01700010, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10499 {0x0ff00090, 0x01700010, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // CMN<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10500 {0x0ff0f010, 0x01700000, 4, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10501 {0x0ff00010, 0x01700000, 3, arm_CMN_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // CMN<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10502 {0x0ff0f000, 0x03500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10503 {0x0ff00000, 0x03500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // CMP<c> <Rn>,#<const> cond:4|0|0|1|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10504 {0x0ff0f090, 0x01500010, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10505 {0x0ff00090, 0x01500010, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // CMP<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10506 {0x0ff0f010, 0x01500000, 4, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10507 {0x0ff00010, 0x01500000, 3, arm_CMP_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // CMP<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|1|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10508 {0x0ffffff0, 0x0320f0f0, 4, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 10509 {0x0fff00f0, 0x0320f0f0, 3, arm_DBG_EQ, 0x1c04, arm_instArgs{arm_arg_option}}, // DBG<c> #<option> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|1|1|1|1|option:4 10510 {0xfffffff0, 0xf57ff050, 4, arm_DMB, 0x0, arm_instArgs{arm_arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4 10511 {0xfff000f0, 0xf57ff050, 3, arm_DMB, 0x0, arm_instArgs{arm_arg_option}}, // DMB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|1|option:4 10512 {0xfffffff0, 0xf57ff040, 4, arm_DSB, 0x0, arm_instArgs{arm_arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4 10513 {0xfff000f0, 0xf57ff040, 3, arm_DSB, 0x0, arm_instArgs{arm_arg_option}}, // DSB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|0|0|option:4 10514 {0x0fe00000, 0x02200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // EOR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|0|1|S|Rn:4|Rd:4|imm12:12 10515 {0x0fe00090, 0x00200010, 4, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10516 {0x0fe00010, 0x00200000, 2, arm_EOR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|0|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10517 {0xfffffff0, 0xf57ff060, 4, arm_ISB, 0x0, arm_instArgs{arm_arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4 10518 {0xfff000f0, 0xf57ff060, 3, arm_ISB, 0x0, arm_instArgs{arm_arg_option}}, // ISB #<option> 1|1|1|1|0|1|0|1|0|1|1|1|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|1|1|0|option:4 10519 {0x0fd00000, 0x08900000, 2, arm_LDM_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // LDM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|1|Rn:4|register_list:16 10520 {0x0fd00000, 0x08100000, 4, arm_LDMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // LDMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|1|Rn:4|register_list:16 10521 {0x0fd00000, 0x09100000, 4, arm_LDMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // LDMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|1|Rn:4|register_list:16 10522 {0x0fd00000, 0x09900000, 4, arm_LDMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // LDMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|1|Rn:4|register_list:16 10523 {0x0f7f0000, 0x051f0000, 4, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 10524 {0x0e5f0000, 0x051f0000, 3, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_label_pm_12}}, // LDR<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|0|(0)|1|1|1|1|1|Rt:4|imm12:12 10525 {0x0e500010, 0x06100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10526 {0x0e500000, 0x04100000, 2, arm_LDR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_W}}, // LDR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|1|Rn:4|Rt:4|imm12:12 10527 {0x0f7f0000, 0x055f0000, 4, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 10528 {0x0e5f0000, 0x055f0000, 3, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_label_pm_12}}, // LDRB<c> <Rt>,<label+/-12> cond:4|0|1|0|(1)|U|1|(0)|1|1|1|1|1|Rt:4|imm12:12 10529 {0x0e500010, 0x06500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_W}}, // LDRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10530 {0x0e500000, 0x04500000, 2, arm_LDRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_W}}, // LDRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|1|Rn:4|Rt:4|imm12:12 10531 {0x0f700000, 0x04700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|1|Rn:4|Rt:4|imm12:12 10532 {0x0f700010, 0x06700000, 4, arm_LDRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10533 {0x0e500ff0, 0x000000d0, 4, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 10534 {0x0e5000f0, 0x000000d0, 3, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|0|1|Rm:4 10535 {0x0e5000f0, 0x004000d0, 2, arm_LDRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // LDRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 10536 {0x0ff00fff, 0x01900f9f, 4, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10537 {0x0ff000f0, 0x01900f9f, 3, arm_LDREX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREX<c> <Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10538 {0x0ff00fff, 0x01d00f9f, 4, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10539 {0x0ff000f0, 0x01d00f9f, 3, arm_LDREXB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREXB<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|0|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10540 {0x0ff00fff, 0x01b00f9f, 4, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10541 {0x0ff000f0, 0x01b00f9f, 3, arm_LDREXD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R}}, // LDREXD<c> <Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10542 {0x0ff00fff, 0x01f00f9f, 4, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10543 {0x0ff000f0, 0x01f00f9f, 3, arm_LDREXH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R}}, // LDREXH<c> <Rt>, [<Rn>] cond:4|0|0|0|1|1|1|1|1|Rn:4|Rt:4|(1)|(1)|(1)|(1)|1|0|0|1|(1)|(1)|(1)|(1) 10544 {0x0e500ff0, 0x001000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_W}}, // LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 10545 {0x0e5000f0, 0x005000b0, 2, arm_LDRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_W}}, // LDRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 10546 {0x0f7000f0, 0x007000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 10547 {0x0f700ff0, 0x003000b0, 4, arm_LDRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 10548 {0x0e500ff0, 0x001000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_W}}, // LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 10549 {0x0e5000f0, 0x005000d0, 2, arm_LDRSB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSB<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 10550 {0x0f7000f0, 0x007000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSBT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|0|1|imm4L:4 10551 {0x0f700ff0, 0x003000d0, 4, arm_LDRSBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSBT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|0|1|Rm:4 10552 {0x0e500ff0, 0x001000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_W}}, // LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 10553 {0x0e5000f0, 0x005000f0, 2, arm_LDRSH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_W}}, // LDRSH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 10554 {0x0f7000f0, 0x007000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_postindex}}, // LDRSHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 10555 {0x0f700ff0, 0x003000f0, 4, arm_LDRSHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_postindex}}, // LDRSHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|1|Rn:4|Rt:4|0|0|0|0|1|1|1|1|Rm:4 10556 {0x0f700000, 0x04300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_postindex}}, // LDRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|1|Rn:4|Rt:4|imm12:12 10557 {0x0f700010, 0x06300000, 4, arm_LDRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // LDRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|1|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10558 {0x0fef0070, 0x01a00000, 2, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5_nz}}, // LSL{S}<c> <Rd>,<Rm>,#<imm5_nz> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|0|0|Rm:4 10559 {0x0fef00f0, 0x01a00010, 4, arm_LSL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|0|1|Rn:4 10560 {0x0fef0070, 0x01a00020, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5_32}}, // LSR{S}<c> <Rd>,<Rm>,#<imm5_32> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|0|1|0|Rm:4 10561 {0x0fef00f0, 0x01a00030, 4, arm_LSR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_8}}, // LSR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|0|1|1|Rn:4 10562 {0x0fe000f0, 0x00200090, 4, arm_MLA_EQ, 0x14011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|0|1|S|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 10563 {0x0ff000f0, 0x00600090, 4, arm_MLS_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // MLS<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|0|0|1|1|0|Rd:4|Ra:4|Rm:4|1|0|0|1|Rn:4 10564 {0x0ff00000, 0x03400000, 4, arm_MOVT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_imm_4at16_12at0}}, // MOVT<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|1|0|0|imm4:4|Rd:4|imm12:12 10565 {0x0ff00000, 0x03000000, 4, arm_MOVW_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_imm_4at16_12at0}}, // MOVW<c> <Rd>,#<imm12+4> cond:4|0|0|1|1|0|0|0|0|imm4:4|Rd:4|imm12:12 10566 {0x0fef0000, 0x03a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_const}}, // MOV{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|0|1|S|0|0|0|0|Rd:4|imm12:12 10567 {0x0fef0ff0, 0x01a00000, 2, arm_MOV_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // MOV{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|0|0|0|Rm:4 10568 {0x0fff0fff, 0x010f0000, 4, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) 10569 {0x0ff000f0, 0x010f0000, 3, arm_MRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_APSR}}, // MRS<c> <Rd>,APSR cond:4|0|0|0|1|0|0|0|0|(1)|(1)|(1)|(1)|Rd:4|(0)|(0)|(0)|(0)|0|0|0|0|(0)|(0)|(0)|(0) 10570 {0x0fe0f0f0, 0x00000090, 4, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 10571 {0x0fe000f0, 0x00000090, 3, arm_MUL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // MUL{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|0|0|0|0|S|Rd:4|(0)|(0)|(0)|(0)|Rm:4|1|0|0|1|Rn:4 10572 {0x0fef0000, 0x03e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 10573 {0x0fe00000, 0x03e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_const}}, // MVN{S}<c> <Rd>,#<const> cond:4|0|0|1|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm12:12 10574 {0x0fef0090, 0x01e00010, 4, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 10575 {0x0fe00090, 0x01e00010, 3, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_shift_R}}, // MVN{S}<c> <Rd>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|Rs:4|0|type:2|1|Rm:4 10576 {0x0fef0010, 0x01e00000, 2, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 10577 {0x0fe00010, 0x01e00000, 1, arm_MVN_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_shift_imm}}, // MVN{S}<c> <Rd>,<Rm>{,<shift>} cond:4|0|0|0|1|1|1|1|S|(0)|(0)|(0)|(0)|Rd:4|imm5:5|type:2|0|Rm:4 10578 {0x0fffffff, 0x0320f000, 4, arm_NOP_EQ, 0x1c04, arm_instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 10579 {0x0fff00ff, 0x0320f000, 3, arm_NOP_EQ, 0x1c04, arm_instArgs{}}, // NOP<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|0 10580 {0x0fe00000, 0x03800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // ORR{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|1|1|0|0|S|Rn:4|Rd:4|imm12:12 10581 {0x0fe00090, 0x01800010, 4, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10582 {0x0fe00010, 0x01800000, 2, arm_ORR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|1|0|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10583 {0x0ff00030, 0x06800010, 4, arm_PKHBT_EQ, 0x6011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // PKH<BT,TB><c> <Rd>,<Rn>,<Rm>{,LSL #<imm5>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|imm5:5|tb|0|1|Rm:4 10584 {0xff7ff000, 0xf55ff000, 4, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 10585 {0xff3f0000, 0xf55ff000, 3, arm_PLD, 0x0, arm_instArgs{arm_arg_label_pm_12}}, // PLD <label+/-12> 1|1|1|1|0|1|0|1|U|(1)|0|1|1|1|1|1|(1)|(1)|(1)|(1)|imm12:12 10586 {0xff30f000, 0xf510f000, 2, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 10587 {0xff300000, 0xf510f000, 1, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_R_pm_imm12_offset}}, // PLD{W} [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 10588 {0xff30f010, 0xf710f000, 4, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 10589 {0xff300010, 0xf710f000, 3, arm_PLD_W, 0x1601, arm_instArgs{arm_arg_mem_R_pm_R_shift_imm_offset}}, // PLD{W} [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|1|U|R|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 10590 {0xff70f000, 0xf450f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 10591 {0xff700000, 0xf450f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_imm12_offset}}, // PLI [<Rn>,#+/-<imm12>] 1|1|1|1|0|1|0|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm12:12 10592 {0xff70f010, 0xf650f000, 4, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 10593 {0xff700010, 0xf650f000, 3, arm_PLI, 0x0, arm_instArgs{arm_arg_mem_R_pm_R_shift_imm_offset}}, // PLI [<Rn>,+/-<Rm>{, <shift>}] 1|1|1|1|0|1|1|0|U|1|0|1|Rn:4|(1)|(1)|(1)|(1)|imm5:5|type:2|0|Rm:4 10594 {0x0fff0000, 0x08bd0000, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_registers2}}, // POP<c> <registers2> cond:4|1|0|0|0|1|0|1|1|1|1|0|1|register_list:16 10595 {0x0fff0fff, 0x049d0004, 4, arm_POP_EQ, 0x1c04, arm_instArgs{arm_arg_registers1}}, // POP<c> <registers1> cond:4|0|1|0|0|1|0|0|1|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 10596 {0x0fff0000, 0x092d0000, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_registers2}}, // PUSH<c> <registers2> cond:4|1|0|0|1|0|0|1|0|1|1|0|1|register_list:16 10597 {0x0fff0fff, 0x052d0004, 4, arm_PUSH_EQ, 0x1c04, arm_instArgs{arm_arg_registers1}}, // PUSH<c> <registers1> cond:4|0|1|0|1|0|0|1|0|1|1|0|1|Rt:4|0|0|0|0|0|0|0|0|0|1|0|0 10598 {0x0ff00ff0, 0x06200f10, 4, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10599 {0x0ff000f0, 0x06200f10, 3, arm_QADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10600 {0x0ff00ff0, 0x06200f90, 4, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10601 {0x0ff000f0, 0x06200f90, 3, arm_QADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10602 {0x0ff00ff0, 0x01000050, 4, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 10603 {0x0ff000f0, 0x01000050, 3, arm_QADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 10604 {0x0ff00ff0, 0x06200f30, 4, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10605 {0x0ff000f0, 0x06200f30, 3, arm_QASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10606 {0x0ff00ff0, 0x01400050, 4, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 10607 {0x0ff000f0, 0x01400050, 3, arm_QDADD_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QDADD<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|0|0|Rn:4|Rd:4|(0)|(0)|(0)|(0)|0|1|0|1|Rm:4 10608 {0x0ff00ff0, 0x01600050, 4, arm_QDSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QDSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|1|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 10609 {0x0ff00ff0, 0x06200f50, 4, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10610 {0x0ff000f0, 0x06200f50, 3, arm_QSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10611 {0x0ff00ff0, 0x06200f70, 4, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10612 {0x0ff000f0, 0x06200f70, 3, arm_QSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10613 {0x0ff00ff0, 0x06200ff0, 4, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10614 {0x0ff000f0, 0x06200ff0, 3, arm_QSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // QSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10615 {0x0ff00ff0, 0x01200050, 4, arm_QSUB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_16}}, // QSUB<c> <Rd>,<Rm>,<Rn> cond:4|0|0|0|1|0|0|1|0|Rn:4|Rd:4|0|0|0|0|0|1|0|1|Rm:4 10616 {0x0fff0ff0, 0x06ff0f30, 4, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10617 {0x0ff000f0, 0x06ff0f30, 3, arm_RBIT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // RBIT<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10618 {0x0fff0ff0, 0x06bf0fb0, 4, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10619 {0x0ff000f0, 0x06bf0fb0, 3, arm_REV16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REV16<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10620 {0x0fff0ff0, 0x06bf0f30, 4, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10621 {0x0ff000f0, 0x06bf0f30, 3, arm_REV_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REV<c> <Rd>,<Rm> cond:4|0|1|1|0|1|0|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10622 {0x0fff0ff0, 0x06ff0fb0, 4, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10623 {0x0ff000f0, 0x06ff0fb0, 3, arm_REVSH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // REVSH<c> <Rd>,<Rm> cond:4|0|1|1|0|1|1|1|1|(1)|(1)|(1)|(1)|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10624 {0x0fef0070, 0x01a00060, 2, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5}}, // ROR{S}<c> <Rd>,<Rm>,#<imm5> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|imm5:5|1|1|0|Rm:4 10625 {0x0fef00f0, 0x01a00070, 4, arm_ROR_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_R_8}}, // ROR{S}<c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|Rm:4|0|1|1|1|Rn:4 10626 {0x0fef0ff0, 0x01a00060, 4, arm_RRX_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0}}, // RRX{S}<c> <Rd>,<Rm> cond:4|0|0|0|1|1|0|1|S|0|0|0|0|Rd:4|0|0|0|0|0|1|1|0|Rm:4 10627 {0x0fe00000, 0x02600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // RSB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|1|S|Rn:4|Rd:4|imm12:12 10628 {0x0fe00090, 0x00600010, 4, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10629 {0x0fe00010, 0x00600000, 2, arm_RSB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10630 {0x0fe00000, 0x02e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // RSC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|1|S|Rn:4|Rd:4|imm12:12 10631 {0x0fe00090, 0x00e00010, 4, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10632 {0x0fe00010, 0x00e00000, 2, arm_RSC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|1|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10633 {0x0ff00ff0, 0x06100f10, 4, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10634 {0x0ff000f0, 0x06100f10, 3, arm_SADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10635 {0x0ff00ff0, 0x06100f90, 4, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10636 {0x0ff000f0, 0x06100f90, 3, arm_SADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10637 {0x0ff00ff0, 0x06100f30, 4, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10638 {0x0ff000f0, 0x06100f30, 3, arm_SASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10639 {0x0fe00000, 0x02c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // SBC{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|1|1|0|S|Rn:4|Rd:4|imm12:12 10640 {0x0fe00090, 0x00c00010, 4, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10641 {0x0fe00010, 0x00c00000, 2, arm_SBC_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10642 {0x0fe00070, 0x07a00050, 4, arm_SBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 10643 {0x0ff00ff0, 0x06800fb0, 4, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10644 {0x0ff000f0, 0x06800fb0, 3, arm_SEL_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4 10645 {0xfffffdff, 0xf1010000, 4, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0) 10646 {0xfffffc00, 0xf1010000, 3, arm_SETEND, 0x0, arm_instArgs{arm_arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0) 10647 {0x0fffffff, 0x0320f004, 4, arm_SEV_EQ, 0x1c04, arm_instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 10648 {0x0fff00ff, 0x0320f004, 3, arm_SEV_EQ, 0x1c04, arm_instArgs{}}, // SEV<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0 10649 {0x0ff00ff0, 0x06300f10, 4, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10650 {0x0ff000f0, 0x06300f10, 3, arm_SHADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10651 {0x0ff00ff0, 0x06300f90, 4, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10652 {0x0ff000f0, 0x06300f90, 3, arm_SHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10653 {0x0ff00ff0, 0x06300f30, 4, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10654 {0x0ff000f0, 0x06300f30, 3, arm_SHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10655 {0x0ff00ff0, 0x06300f50, 4, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10656 {0x0ff000f0, 0x06300f50, 3, arm_SHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10657 {0x0ff00ff0, 0x06300f70, 4, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10658 {0x0ff000f0, 0x06300f70, 3, arm_SHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10659 {0x0ff00ff0, 0x06300ff0, 4, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10660 {0x0ff000f0, 0x06300ff0, 3, arm_SHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10661 {0x0ff00090, 0x01000080, 4, arm_SMLABB_EQ, 0x50106011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|0|0|Rd:4|Ra:4|Rm:4|1|M|N|0|Rn:4 10662 {0x0ff000d0, 0x07000010, 2, arm_SMLAD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|0|M|1|Rn:4 10663 {0x0ff00090, 0x01400080, 4, arm_SMLALBB_EQ, 0x50106011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL<x><y><c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|M|N|0|Rn:4 10664 {0x0ff000d0, 0x07400010, 4, arm_SMLALD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLALD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|0|M|1|Rn:4 10665 {0x0fe000f0, 0x00e00090, 4, arm_SMLAL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 10666 {0x0ff000b0, 0x01200080, 4, arm_SMLAWB_EQ, 0x6011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLAW<y><c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|0|0|1|0|0|1|0|Rd:4|Ra:4|Rm:4|1|M|0|0|Rn:4 10667 {0x0ff000d0, 0x07000050, 2, arm_SMLSD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMLSD{X}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|0|0|0|Rd:4|Ra:4|Rm:4|0|1|M|1|Rn:4 10668 {0x0ff000d0, 0x07400050, 4, arm_SMLSLD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMLSLD{X}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|0|RdHi:4|RdLo:4|Rm:4|0|1|M|1|Rn:4 10669 {0x0ff000d0, 0x07500010, 2, arm_SMMLA_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLA{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|0|0|R|1|Rn:4 10670 {0x0ff000d0, 0x075000d0, 4, arm_SMMLS_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // SMMLS{R}<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|0|1|0|1|Rd:4|Ra:4|Rm:4|1|1|R|1|Rn:4 10671 {0x0ff0f0d0, 0x0750f010, 4, arm_SMMUL_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMMUL{R}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|1|0|1|Rd:4|1|1|1|1|Rm:4|0|0|R|1|Rn:4 10672 {0x0ff0f0d0, 0x0700f010, 4, arm_SMUAD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUAD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|M|1|Rn:4 10673 {0x0ff0f090, 0x01600080, 4, arm_SMULBB_EQ, 0x50106011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUL<x><y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|1|1|0|Rd:4|0|0|0|0|Rm:4|1|M|N|0|Rn:4 10674 {0x0fe000f0, 0x00c00090, 4, arm_SMULL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|1|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 10675 {0x0ff0f0b0, 0x012000a0, 4, arm_SMULWB_EQ, 0x6011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMULW<y><c> <Rd>,<Rn>,<Rm> cond:4|0|0|0|1|0|0|1|0|Rd:4|0|0|0|0|Rm:4|1|M|1|0|Rn:4 10676 {0x0ff0f0d0, 0x0700f050, 4, arm_SMUSD_EQ, 0x5011c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // SMUSD{X}<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|0|Rd:4|1|1|1|1|Rm:4|0|1|M|1|Rn:4 10677 {0x0ff00ff0, 0x06a00f30, 4, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 10678 {0x0ff000f0, 0x06a00f30, 3, arm_SSAT16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm4m1, arm_arg_R_0}}, // SSAT16<c> <Rd>,#<sat_imm4m1>,<Rn> cond:4|0|1|1|0|1|0|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 10679 {0x0fe00030, 0x06a00010, 4, arm_SSAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm5m1, arm_arg_R_shift_imm}}, // SSAT<c> <Rd>,#<sat_imm5m1>,<Rn>{,<shift>} cond:4|0|1|1|0|1|0|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 10680 {0x0ff00ff0, 0x06100f50, 4, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10681 {0x0ff000f0, 0x06100f50, 3, arm_SSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10682 {0x0ff00ff0, 0x06100f70, 4, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10683 {0x0ff000f0, 0x06100f70, 3, arm_SSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10684 {0x0ff00ff0, 0x06100ff0, 4, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10685 {0x0ff000f0, 0x06100ff0, 3, arm_SSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // SSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|0|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10686 {0x0fd00000, 0x08800000, 4, arm_STM_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // STM<c> <Rn>{!},<registers> cond:4|1|0|0|0|1|0|W|0|Rn:4|register_list:16 10687 {0x0fd00000, 0x08000000, 4, arm_STMDA_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // STMDA<c> <Rn>{!},<registers> cond:4|1|0|0|0|0|0|W|0|Rn:4|register_list:16 10688 {0x0fd00000, 0x09000000, 2, arm_STMDB_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // STMDB<c> <Rn>{!},<registers> cond:4|1|0|0|1|0|0|W|0|Rn:4|register_list:16 10689 {0x0fd00000, 0x09800000, 4, arm_STMIB_EQ, 0x1c04, arm_instArgs{arm_arg_R_16_WB, arm_arg_registers}}, // STMIB<c> <Rn>{!},<registers> cond:4|1|0|0|1|1|0|W|0|Rn:4|register_list:16 10690 {0x0e500018, 0x06000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_W}}, // STR<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|0|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10691 {0x0e500000, 0x04000000, 2, arm_STR_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_W}}, // STR<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|0|W|0|Rn:4|Rt:4|imm12:12 10692 {0x0e500010, 0x06400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_W}}, // STRB<c> <Rt>,[<Rn>,+/-<Rm>{, <shift>}]{!} cond:4|0|1|1|P|U|1|W|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10693 {0x0e500000, 0x04400000, 2, arm_STRB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_W}}, // STRB<c> <Rt>,[<Rn>{,#+/-<imm12>}]{!} cond:4|0|1|0|P|U|1|W|0|Rn:4|Rt:4|imm12:12 10694 {0x0f700000, 0x04600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_postindex}}, // STRBT<c> <Rt>,[<Rn>],#+/-<imm12> cond:4|0|1|0|0|U|1|1|0|Rn:4|Rt:4|imm12:12 10695 {0x0f700010, 0x06600000, 4, arm_STRBT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRBT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|1|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10696 {0x0e500ff0, 0x000000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 10697 {0x0e5000f0, 0x000000f0, 3, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_R_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|(0)|(0)|(0)|(0)|1|1|1|1|Rm:4 10698 {0x0e5000f0, 0x004000f0, 4, arm_STRD_EQ, 0x1c04, arm_instArgs{arm_arg_R1_12, arm_arg_R2_12, arm_arg_mem_R_pm_imm8_W}}, // STRD<c> <Rt1>,<Rt2>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|1|1|1|imm4L:4 10699 {0x0ff00ff0, 0x01800f90, 4, arm_STREX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREX<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|0|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 10700 {0x0ff00ff0, 0x01c00f90, 4, arm_STREXB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXB<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|0|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 10701 {0x0ff00ff0, 0x01a00f90, 4, arm_STREXD_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R1_0, arm_arg_R2_0, arm_arg_mem_R}}, // STREXD<c> <Rd>,<Rt1>,<Rt2>,[<Rn>] cond:4|0|0|0|1|1|0|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 10702 {0x0ff00ff0, 0x01e00f90, 4, arm_STREXH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_mem_R}}, // STREXH<c> <Rd>,<Rt>,[<Rn>] cond:4|0|0|0|1|1|1|1|0|Rn:4|Rd:4|1|1|1|1|1|0|0|1|Rt:4 10703 {0x0e500ff0, 0x000000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_W}}, // STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!} cond:4|0|0|0|P|U|0|W|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 10704 {0x0e5000f0, 0x004000b0, 2, arm_STRH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_W}}, // STRH<c> <Rt>,[<Rn>{,#+/-<imm8>}]{!} cond:4|0|0|0|P|U|1|W|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 10705 {0x0f7000f0, 0x006000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm8_postindex}}, // STRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|0|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4 10706 {0x0f700ff0, 0x002000b0, 4, arm_STRHT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_postindex}}, // STRHT<c> <Rt>, [<Rn>], +/-<Rm> cond:4|0|0|0|0|U|0|1|0|Rn:4|Rt:4|0|0|0|0|1|0|1|1|Rm:4 10707 {0x0f700000, 0x04200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_imm12_postindex}}, // STRT<c> <Rt>, [<Rn>] {,#+/-<imm12>} cond:4|0|1|0|0|U|0|1|0|Rn:4|Rt:4|imm12:12 10708 {0x0f700010, 0x06200000, 4, arm_STRT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_mem_R_pm_R_shift_imm_postindex}}, // STRT<c> <Rt>,[<Rn>],+/-<Rm>{, <shift>} cond:4|0|1|1|0|U|0|1|0|Rn:4|Rt:4|imm5:5|type:2|0|Rm:4 10709 {0x0fe00000, 0x02400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_const}}, // SUB{S}<c> <Rd>,<Rn>,#<const> cond:4|0|0|1|0|0|1|0|S|Rn:4|Rd:4|imm12:12 10710 {0x0fe00090, 0x00400010, 4, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_R}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4 10711 {0x0fe00010, 0x00400000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4 10712 {0x0fef0000, 0x024d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_SP, arm_arg_const}}, // SUB{S}<c> <Rd>,SP,#<const> cond:4|0|0|1|0|0|1|0|S|1|1|0|1|Rd:4|imm12:12 10713 {0x0fef0010, 0x004d0000, 2, arm_SUB_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_SP, arm_arg_R_shift_imm}}, // SUB{S}<c> <Rd>,SP,<Rm>{,<shift>} cond:4|0|0|0|0|0|1|0|S|1|1|0|1|Rd:4|imm5:5|type:2|0|Rm:4 10714 {0x0f000000, 0x0f000000, 4, arm_SVC_EQ, 0x1c04, arm_instArgs{arm_arg_imm24}}, // SVC<c> #<imm24> cond:4|1|1|1|1|imm24:24 10715 {0x0fb00ff0, 0x01000090, 4, arm_SWP_EQ, 0x16011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_mem_R}}, // SWP{B}<c> <Rt>,<Rm>,[<Rn>] cond:4|0|0|0|1|0|B|0|0|Rn:4|Rt:4|0|0|0|0|1|0|0|1|Rm:4 10716 {0x0ff003f0, 0x06800070, 2, arm_SXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10717 {0x0ff003f0, 0x06a00070, 2, arm_SXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10718 {0x0ff003f0, 0x06b00070, 2, arm_SXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10719 {0x0fff03f0, 0x068f0070, 4, arm_SXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // SXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10720 {0x0fff03f0, 0x06af0070, 4, arm_SXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // SXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10721 {0x0fff03f0, 0x06bf0070, 4, arm_SXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // SXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|0|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10722 {0x0ff0f000, 0x03300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10723 {0x0ff00000, 0x03300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // TEQ<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10724 {0x0ff0f090, 0x01300010, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10725 {0x0ff00090, 0x01300010, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // TEQ<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10726 {0x0ff0f010, 0x01300000, 4, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10727 {0x0ff00010, 0x01300000, 3, arm_TEQ_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // TEQ<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|1|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10728 {0x0ff0f000, 0x03100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10729 {0x0ff00000, 0x03100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_const}}, // TST<c> <Rn>,#<const> cond:4|0|0|1|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm12:12 10730 {0x0ff0f090, 0x01100010, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10731 {0x0ff00090, 0x01100010, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_R}}, // TST<c> <Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|Rs:4|0|type:2|1|Rm:4 10732 {0x0ff0f010, 0x01100000, 4, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10733 {0x0ff00010, 0x01100000, 3, arm_TST_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_shift_imm}}, // TST<c> <Rn>,<Rm>{,<shift>} cond:4|0|0|0|1|0|0|0|1|Rn:4|(0)|(0)|(0)|(0)|imm5:5|type:2|0|Rm:4 10734 {0x0ff00ff0, 0x06500f10, 4, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10735 {0x0ff000f0, 0x06500f10, 3, arm_UADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10736 {0x0ff00ff0, 0x06500f90, 4, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10737 {0x0ff000f0, 0x06500f90, 3, arm_UADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10738 {0x0ff00ff0, 0x06500f30, 4, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10739 {0x0ff000f0, 0x06500f30, 3, arm_UASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10740 {0x0fe00070, 0x07e00050, 4, arm_UBFX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_0, arm_arg_imm5, arm_arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4 10741 {0x0ff00ff0, 0x06700f10, 4, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10742 {0x0ff000f0, 0x06700f10, 3, arm_UHADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10743 {0x0ff00ff0, 0x06700f90, 4, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10744 {0x0ff000f0, 0x06700f90, 3, arm_UHADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10745 {0x0ff00ff0, 0x06700f30, 4, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10746 {0x0ff000f0, 0x06700f30, 3, arm_UHASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10747 {0x0ff00ff0, 0x06700f50, 4, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10748 {0x0ff000f0, 0x06700f50, 3, arm_UHSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10749 {0x0ff00ff0, 0x06700f70, 4, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10750 {0x0ff000f0, 0x06700f70, 3, arm_UHSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10751 {0x0ff00ff0, 0x06700ff0, 4, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10752 {0x0ff000f0, 0x06700ff0, 3, arm_UHSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UHSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10753 {0x0ff000f0, 0x00400090, 4, arm_UMAAL_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|0|1|0|0|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 10754 {0x0fe000f0, 0x00a00090, 4, arm_UMLAL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|1|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 10755 {0x0fe000f0, 0x00800090, 4, arm_UMULL_EQ, 0x14011c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm> cond:4|0|0|0|0|1|0|0|S|RdHi:4|RdLo:4|Rm:4|1|0|0|1|Rn:4 10756 {0x0ff00ff0, 0x06600f10, 4, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10757 {0x0ff000f0, 0x06600f10, 3, arm_UQADD16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4 10758 {0x0ff00ff0, 0x06600f90, 4, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10759 {0x0ff000f0, 0x06600f90, 3, arm_UQADD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4 10760 {0x0ff00ff0, 0x06600f30, 4, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10761 {0x0ff000f0, 0x06600f30, 3, arm_UQASX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4 10762 {0x0ff00ff0, 0x06600f50, 4, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10763 {0x0ff000f0, 0x06600f50, 3, arm_UQSAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10764 {0x0ff00ff0, 0x06600f70, 4, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10765 {0x0ff000f0, 0x06600f70, 3, arm_UQSUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10766 {0x0ff00ff0, 0x06600ff0, 4, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10767 {0x0ff000f0, 0x06600ff0, 3, arm_UQSUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // UQSUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10768 {0x0ff0f0f0, 0x0780f010, 4, arm_USAD8_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8}}, // USAD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|1|0|0|0|Rd:4|1|1|1|1|Rm:4|0|0|0|1|Rn:4 10769 {0x0ff000f0, 0x07800010, 2, arm_USADA8_EQ, 0x1c04, arm_instArgs{arm_arg_R_16, arm_arg_R_0, arm_arg_R_8, arm_arg_R_12}}, // USADA8<c> <Rd>,<Rn>,<Rm>,<Ra> cond:4|0|1|1|1|1|0|0|0|Rd:4|Ra:4|Rm:4|0|0|0|1|Rn:4 10770 {0x0ff00ff0, 0x06e00f30, 4, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 10771 {0x0ff000f0, 0x06e00f30, 3, arm_USAT16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm4, arm_arg_R_0}}, // USAT16<c> <Rd>,#<sat_imm4>,<Rn> cond:4|0|1|1|0|1|1|1|0|sat_imm:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rn:4 10772 {0x0fe00030, 0x06e00010, 4, arm_USAT_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_satimm5, arm_arg_R_shift_imm}}, // USAT<c> <Rd>,#<sat_imm5>,<Rn>{,<shift>} cond:4|0|1|1|0|1|1|1|sat_imm:5|Rd:4|imm5:5|sh|0|1|Rn:4 10773 {0x0ff00ff0, 0x06500f50, 4, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10774 {0x0ff000f0, 0x06500f50, 3, arm_USAX_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USAX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|0|1|Rm:4 10775 {0x0ff00ff0, 0x06500f70, 4, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10776 {0x0ff000f0, 0x06500f70, 3, arm_USUB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|1|1|1|Rm:4 10777 {0x0ff00ff0, 0x06500ff0, 4, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10778 {0x0ff000f0, 0x06500ff0, 3, arm_USUB8_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_0}}, // USUB8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|1|1|1|Rm:4 10779 {0x0ff003f0, 0x06c00070, 2, arm_UXTAB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10780 {0x0ff003f0, 0x06e00070, 2, arm_UXTAB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10781 {0x0ff003f0, 0x06f00070, 2, arm_UXTAH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_16, arm_arg_R_rotate}}, // UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|Rn:4|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10782 {0x0fff03f0, 0x06cf0070, 4, arm_UXTB16_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // UXTB16<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|0|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10783 {0x0fff03f0, 0x06ef0070, 4, arm_UXTB_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // UXTB<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|0|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10784 {0x0fff03f0, 0x06ff0070, 4, arm_UXTH_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_R_rotate}}, // UXTH<c> <Rd>,<Rm>{,<rotation>} cond:4|0|1|1|0|1|1|1|1|1|1|1|1|Rd:4|rotate:2|0|0|0|1|1|1|Rm:4 10785 {0x0fb00e10, 0x0e000a00, 4, arm_VMLA_EQ_F32, 0x60108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // V<MLA,MLS><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4 10786 {0x0fbf0ed0, 0x0eb00ac0, 4, arm_VABS_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VABS<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 10787 {0x0fb00e50, 0x0e300a00, 4, arm_VADD_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VADD<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 10788 {0x0fbf0e7f, 0x0eb50a40, 4, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0) 10789 {0x0fbf0e70, 0x0eb50a40, 3, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_fp_0}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, #0.0 cond:4|1|1|1|0|1|D|1|1|0|1|0|1|Vd:4|1|0|1|sz|E|1|0|0|(0)|(0)|(0)|(0) 10790 {0x0fbf0e50, 0x0eb40a40, 4, arm_VCMP_EQ_F32, 0x70108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VCMP{E}<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|0|0|Vd:4|1|0|1|sz|E|1|M|0|Vm:4 10791 {0x0fbe0e50, 0x0eba0a40, 4, arm_VCVT_EQ_F32_FXS16, 0x801100107011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sd_Dd, arm_arg_fbits}}, // VCVT<c>.F<32,64>.FX<S,U><16,32> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|0|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4 10792 {0x0fbe0e50, 0x0ebe0a40, 4, arm_VCVT_EQ_FXS16_F32, 0x1001070108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sd_Dd, arm_arg_fbits}}, // VCVT<c>.FX<S,U><16,32>.F<32,64> <Sd,Dd>, <Sd,Dd>, #<fbits> cond:4|1|1|1|0|1|D|1|1|1|1|1|U|Vd:4|1|0|1|sz|sx|1|i|0|imm4:4 10793 {0x0fbf0ed0, 0x0eb70ac0, 4, arm_VCVT_EQ_F64_F32, 0x8011c04, arm_instArgs{arm_arg_Dd_Sd, arm_arg_Sm_Dm}}, // VCVT<c>.<F64.F32,F32.F64> <Dd,Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|1|1|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 10794 {0x0fbe0f50, 0x0eb20a40, 4, arm_VCVTB_EQ_F32_F16, 0x70110011c04, arm_instArgs{arm_arg_Sd, arm_arg_Sm}}, // VCVT<B,T><c>.<F32.F16,F16.F32> <Sd>, <Sm> cond:4|1|1|1|0|1|D|1|1|0|0|1|op|Vd:4|1|0|1|0|T|1|M|0|Vm:4 10795 {0x0fbf0e50, 0x0eb80a40, 4, arm_VCVT_EQ_F32_U32, 0x80107011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm}}, // VCVT<c>.F<32,64>.<U,S>32 <Sd,Dd>, <Sm> cond:4|1|1|1|0|1|D|1|1|1|0|0|0|Vd:4|1|0|1|sz|op|1|M|0|Vm:4 10796 {0x0fbe0e50, 0x0ebc0a40, 4, arm_VCVTR_EQ_U32_F32, 0x701100108011c04, arm_instArgs{arm_arg_Sd, arm_arg_Sm_Dm}}, // VCVT<R,><c>.<U,S>32.F<32,64> <Sd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|1|1|0|signed|Vd:4|1|0|1|sz|op|1|M|0|Vm:4 10797 {0x0fb00e50, 0x0e800a00, 4, arm_VDIV_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VDIV<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|1|D|0|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 10798 {0x0f300e00, 0x0d100a00, 4, arm_VLDR_EQ, 0x1c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_mem_R_pm_imm8at0_offset}}, // VLDR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|1|Rn:4|Vd:4|1|0|1|sz|imm8:8 10799 {0x0ff00f7f, 0x0e000a10, 4, arm_VMOV_EQ, 0x1c04, arm_instArgs{arm_arg_Sn, arm_arg_R_12}}, // VMOV<c> <Sn>, <Rt> cond:4|1|1|1|0|0|0|0|0|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 10800 {0x0ff00f7f, 0x0e100a10, 4, arm_VMOV_EQ, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_Sn}}, // VMOV<c> <Rt>, <Sn> cond:4|1|1|1|0|0|0|0|1|Vn:4|Rt:4|1|0|1|0|N|0|0|1|0|0|0|0 10801 {0x0fd00f7f, 0x0e100b10, 4, arm_VMOV_EQ_32, 0x1c04, arm_instArgs{arm_arg_R_12, arm_arg_Dn_half}}, // VMOV<c>.32 <Rt>, <Dn[x]> cond:4|1|1|1|0|0|0|opc1|1|Vn:4|Rt:4|1|0|1|1|N|0|0|1|0|0|0|0 10802 {0x0fd00f7f, 0x0e000b10, 4, arm_VMOV_EQ_32, 0x1c04, arm_instArgs{arm_arg_Dn_half, arm_arg_R_12}}, // VMOV<c>.32 <Dd[x]>, <Rt> cond:4|1|1|1|0|0|0|opc1|0|Vd:4|Rt:4|1|0|1|1|D|0|0|1|0|0|0|0 10803 {0x0fb00ef0, 0x0eb00a00, 4, arm_VMOV_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_imm_vfp}}, // VMOV<c>.F<32,64> <Sd,Dd>, #<imm_vfp> cond:4|1|1|1|0|1|D|1|1|imm4H:4|Vd:4|1|0|1|sz|0|0|0|0|imm4L:4 10804 {0x0fbf0ed0, 0x0eb00a40, 4, arm_VMOV_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VMOV<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|0|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 10805 {0x0fff0fff, 0x0ef10a10, 4, arm_VMRS_EQ, 0x1c04, arm_instArgs{arm_arg_R_12_nzcv, arm_arg_FPSCR}}, // VMRS<c> <Rt_nzcv>, FPSCR cond:4|1|1|1|0|1|1|1|1|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 10806 {0x0fff0fff, 0x0ee10a10, 4, arm_VMSR_EQ, 0x1c04, arm_instArgs{arm_arg_FPSCR, arm_arg_R_12}}, // VMSR<c> FPSCR, <Rt> cond:4|1|1|1|0|1|1|1|0|0|0|0|1|Rt:4|1|0|1|0|0|0|0|1|0|0|0|0 10807 {0x0fb00e50, 0x0e200a00, 4, arm_VMUL_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|0|M|0|Vm:4 10808 {0x0fbf0ed0, 0x0eb10a40, 4, arm_VNEG_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VNEG<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|0|1|M|0|Vm:4 10809 {0x0fb00e10, 0x0e100a00, 4, arm_VNMLS_EQ_F32, 0x60108011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VN<MLS,MLA><c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|0|1|Vn:4|Vd:4|1|0|1|sz|N|op|M|0|Vm:4 10810 {0x0fb00e50, 0x0e200a40, 4, arm_VNMUL_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VNMUL<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|0|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 10811 {0x0fbf0ed0, 0x0eb10ac0, 4, arm_VSQRT_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sm_Dm}}, // VSQRT<c>.F<32,64> <Sd,Dd>, <Sm,Dm> cond:4|1|1|1|0|1|D|1|1|0|0|0|1|Vd:4|1|0|1|sz|1|1|M|0|Vm:4 10812 {0x0f300e00, 0x0d000a00, 4, arm_VSTR_EQ, 0x1c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_mem_R_pm_imm8at0_offset}}, // VSTR<c> <Sd,Dd>, [<Rn>{,#+/-<imm8>}] cond:4|1|1|0|1|U|D|0|0|Rn:4|Vd:4|1|0|1|sz|imm8:8 10813 {0x0fb00e50, 0x0e300a40, 4, arm_VSUB_EQ_F32, 0x8011c04, arm_instArgs{arm_arg_Sd_Dd, arm_arg_Sn_Dn, arm_arg_Sm_Dm}}, // VSUB<c>.F<32,64> <Sd,Dd>, <Sn,Dn>, <Sm,Dm> cond:4|1|1|1|0|0|D|1|1|Vn:4|Vd:4|1|0|1|sz|N|1|M|0|Vm:4 10814 {0x0fffffff, 0x0320f002, 4, arm_WFE_EQ, 0x1c04, arm_instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 10815 {0x0fff00ff, 0x0320f002, 3, arm_WFE_EQ, 0x1c04, arm_instArgs{}}, // WFE<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|0 10816 {0x0fffffff, 0x0320f003, 4, arm_WFI_EQ, 0x1c04, arm_instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 10817 {0x0fff00ff, 0x0320f003, 3, arm_WFI_EQ, 0x1c04, arm_instArgs{}}, // WFI<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|1|1 10818 {0x0fffffff, 0x0320f001, 4, arm_YIELD_EQ, 0x1c04, arm_instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 10819 {0x0fff00ff, 0x0320f001, 3, arm_YIELD_EQ, 0x1c04, arm_instArgs{}}, // YIELD<c> cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|0|0|1 10820 {0xffffffff, 0xf7fabcfd, 4, arm_UNDEF, 0x0, arm_instArgs{}}, // UNDEF 1|1|1|1|0|1|1|1|1|1|1|1|1|0|1|0|1|0|1|1|1|1|0|0|1|1|1|1|1|1|0|1 10821 }