github.com/aergoio/aergo@v1.3.1/libtool/src/gmp-6.1.2/mpn/powerpc64/README (about)

     1  Copyright 1999-2001, 2003-2005 Free Software Foundation, Inc.
     2  
     3  This file is part of the GNU MP Library.
     4  
     5  The GNU MP Library is free software; you can redistribute it and/or modify
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     8    * the GNU Lesser General Public License as published by the Free
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    12  or
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    14    * the GNU General Public License as published by the Free Software
    15      Foundation; either version 2 of the License, or (at your option) any
    16      later version.
    17  
    18  or both in parallel, as here.
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    22  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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    24  
    25  You should have received copies of the GNU General Public License and the
    26  GNU Lesser General Public License along with the GNU MP Library.  If not,
    27  see https://www.gnu.org/licenses/.
    28  
    29  
    30  
    31                      POWERPC-64 MPN SUBROUTINES
    32  
    33  
    34  This directory contains mpn functions for 64-bit PowerPC chips.
    35  
    36  
    37  CODE ORGANIZATION
    38  
    39  	mpn/powerpc64          mode-neutral code
    40  	mpn/powerpc64/mode32   code for mode32
    41  	mpn/powerpc64/mode64   code for mode64
    42  
    43  
    44  The mode32 and mode64 sub-directories contain code which is for use in the
    45  respective chip mode, 32 or 64.  The top-level directory is code that's
    46  unaffected by the mode.
    47  
    48  The "adde" instruction is the main difference between mode32 and mode64.  It
    49  operates on either on a 32-bit or 64-bit quantity according to the chip mode.
    50  Other instructions have an operand size in their opcode and hence don't vary.
    51  
    52  
    53  
    54  POWER3/PPC630 pipeline information:
    55  
    56  Decoding is 4-way + branch and issue is 8-way with some out-of-order
    57  capability.
    58  
    59  Functional units:
    60  LS1  - ld/st unit 1
    61  LS2  - ld/st unit 2
    62  FXU1 - integer unit 1, handles any simple integer instruction
    63  FXU2 - integer unit 2, handles any simple integer instruction
    64  FXU3 - integer unit 3, handles integer multiply and divide
    65  FPU1 - floating-point unit 1
    66  FPU2 - floating-point unit 2
    67  
    68  Memory:		  Any two memory operations can issue, but memory subsystem
    69  		  can sustain just one store per cycle.  No need for data
    70  		  prefetch; the hardware has very sophisticated prefetch logic.
    71  Simple integer:	  2 operations (such as add, rl*)
    72  Integer multiply: 1 operation every 9th cycle worst case; exact timing depends
    73  		  on 2nd operand's most significant bit position (10 bits per
    74  		  cycle).  Multiply unit is not pipelined, only one multiply
    75  		  operation in progress is allowed.
    76  Integer divide:	  ?
    77  Floating-point:	  Any plain 2 arithmetic instructions (such as fmul, fadd, and
    78  		  fmadd), latency 4 cycles.
    79  Floating-point divide:
    80  		  ?
    81  Floating-point square root:
    82  		  ?
    83  
    84  POWER3/PPC630 best possible times for the main loops:
    85  shift:	      1.5 cycles limited by integer unit contention.
    86  	      With 63 special loops, one for each shift count, we could
    87  	      reduce the needed integer instructions to 2, which would
    88  	      reduce the best possible time to 1 cycle.
    89  add/sub:      1.5 cycles, limited by ld/st unit contention.
    90  mul:	      18 cycles (average) unless floating-point operations are used,
    91  	      but that would only help for multiplies of perhaps 10 and more
    92  	      limbs.
    93  addmul/submul:Same situation as for mul.
    94  
    95  
    96  POWER4/PPC970 and POWER5 pipeline information:
    97  
    98  This is a very odd pipeline, it is basically a VLIW masquerading as a plain
    99  architecture.  Its issue rules are not made public, and since it is so weird,
   100  it is very hard to figure out any useful information from experimentation.
   101  An example:
   102  
   103    A well-aligned loop with nop's take 3, 4, 6, 7, ... cycles.
   104      3 cycles for  0,  1,  2,  3,  4,  5,  6,  7 nop's
   105      4 cycles for  8,  9, 10, 11, 12, 13, 14, 15 nop's
   106      6 cycles for 16, 17, 18, 19, 20, 21, 22, 23 nop's
   107      7 cycles for 24, 25, 26, 27 nop's
   108      8 cycles for 28, 29, 30, 31 nop's
   109      ... continues regularly
   110  
   111  
   112  Functional units:
   113  LS1  - ld/st unit 1
   114  LS2  - ld/st unit 2
   115  FXU1 - integer unit 1, handles any integer instruction
   116  FXU2 - integer unit 2, handles any integer instruction
   117  FPU1 - floating-point unit 1
   118  FPU2 - floating-point unit 2
   119  
   120  While this is one integer unit less than POWER3/PPC630, the remaining units
   121  are more powerful; here they handle multiply and divide.
   122  
   123  Memory:		  2 ld/st.  Stores go to the L2 cache, which can sustain just
   124  		  one store per cycle.
   125  		  L1 load latency: to gregs 3-4 cycles, to fregs 5-6 cycles.
   126  		  Operations that modify the address register might be split
   127  		  to use also an integer issue slot.
   128  Simple integer:	  2 operations every cycle, latency 2.
   129  Integer multiply: 2 operations every 6th cycle, latency 7 cycles.
   130  Integer divide:	  ?
   131  Floating-point:	  Any plain 2 arithmetic instructions (such as fmul, fadd, and
   132  		  fmadd), latency 6 cycles.
   133  Floating-point divide:
   134  		  ?
   135  Floating-point square root:
   136  		  ?
   137  
   138  
   139  IDEAS
   140  
   141  *mul_1: Handling one limb using mulld/mulhdu and two limbs using floating-
   142  point operations should give performance of about 20 cycles for 3 limbs, or 7
   143  cycles/limb.
   144  
   145  We should probably split the single-limb operand in 32-bit chunks, and the
   146  multi-limb operand in 16-bit chunks, allowing us to accumulate well in fp
   147  registers.
   148  
   149  Problem is to get 32-bit or 16-bit words to the fp registers.  Only 64-bit fp
   150  memops copies bits without fiddling with them.  We might therefore need to
   151  load to integer registers with zero extension, store as 64 bits into temp
   152  space, and then load to fp regs.  Alternatively, load directly to fp space
   153  and add well-chosen constants to get cancellation.  (Other part after given by
   154  subsequent subtraction.)
   155  
   156  Possible code mix for load-via-intregs variant:
   157  
   158  lwz,std,lfd
   159  fmadd,fmadd,fmul,fmul
   160  fctidz,stfd,ld,fctidz,stfd,ld
   161  add,adde
   162  lwz,std,lfd
   163  fmadd,fmadd,fmul,fmul
   164  fctidz,stfd,ld,fctidz,stfd,ld
   165  add,adde
   166  srd,sld,add,adde,add,adde