github.com/aergoio/aergo@v1.3.1/libtool/src/gmp-6.1.2/mpn/x86/p6/README (about)

     1  Copyright 2000, 2001 Free Software Foundation, Inc.
     2  
     3  This file is part of the GNU MP Library.
     4  
     5  The GNU MP Library is free software; you can redistribute it and/or modify
     6  it under the terms of either:
     7  
     8    * the GNU Lesser General Public License as published by the Free
     9      Software Foundation; either version 3 of the License, or (at your
    10      option) any later version.
    11  
    12  or
    13  
    14    * the GNU General Public License as published by the Free Software
    15      Foundation; either version 2 of the License, or (at your option) any
    16      later version.
    17  
    18  or both in parallel, as here.
    19  
    20  The GNU MP Library is distributed in the hope that it will be useful, but
    21  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    22  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    23  for more details.
    24  
    25  You should have received copies of the GNU General Public License and the
    26  GNU Lesser General Public License along with the GNU MP Library.  If not,
    27  see https://www.gnu.org/licenses/.
    28  
    29  
    30  
    31  
    32  
    33                        INTEL P6 MPN SUBROUTINES
    34  
    35  
    36  
    37  This directory contains code optimized for Intel P6 class CPUs, meaning
    38  PentiumPro, Pentium II and Pentium III.  The mmx and p3mmx subdirectories
    39  have routines using MMX instructions.
    40  
    41  
    42  
    43  STATUS
    44  
    45  Times for the loops, with all code and data in L1 cache, are as follows.
    46  Some of these might be able to be improved.
    47  
    48                                 cycles/limb
    49  
    50  	mpn_add_n/sub_n           3.7
    51  
    52  	mpn_copyi                 0.75
    53  	mpn_copyd                 1.75 (or 0.75 if no overlap)
    54  
    55  	mpn_divrem_1             39.0
    56  	mpn_mod_1                21.5
    57  	mpn_divexact_by3          8.5
    58  
    59  	mpn_mul_1                 5.5
    60  	mpn_addmul/submul_1       6.35
    61  
    62  	mpn_l/rshift              2.5
    63  
    64  	mpn_mul_basecase          8.2 cycles/crossproduct (approx)
    65  	mpn_sqr_basecase          4.0 cycles/crossproduct (approx)
    66  				  or 7.75 cycles/triangleproduct (approx)
    67  
    68  Pentium II and III have MMX and get the following improvements.
    69  
    70  	mpn_divrem_1             25.0 integer part, 17.5 fractional part
    71  
    72  	mpn_l/rshift              1.75
    73  
    74  
    75  
    76  
    77  NOTES
    78  
    79  Write-allocate L1 data cache means prefetching of destinations is unnecessary.
    80  
    81  Mispredicted branches have a penalty of between 9 and 15 cycles, and even up
    82  to 26 cycles depending how far speculative execution has gone.  The 9 cycle
    83  minimum penalty comes from the issue pipeline being 9 stages.
    84  
    85  A copy with rep movs seems to copy 16 bytes at a time, since speeds for 4,
    86  5, 6 or 7 limb operations are all the same.  The 0.75 cycles/limb would be 3
    87  cycles per 16 byte block.
    88  
    89  
    90  
    91  
    92  CODING
    93  
    94  Instructions in general code have been shown grouped if they can execute
    95  together, which means up to three instructions with no successive
    96  dependencies, and with only the first being a multiple micro-op.
    97  
    98  P6 has out-of-order execution, so the groupings are really only showing
    99  dependent paths where some shuffling might allow some latencies to be
   100  hidden.
   101  
   102  
   103  
   104  
   105  REFERENCES
   106  
   107  "Intel Architecture Optimization Reference Manual", 1999, revision 001 dated
   108  02/99, order number 245127 (order number 730795-001 is in the document too).
   109  Available on-line:
   110  
   111  	http://download.intel.com/design/PentiumII/manuals/245127.htm
   112  
   113  "Intel Architecture Optimization Manual", 1997, order number 242816.  This
   114  is an older document mostly about P5 and not as good as the above.
   115  Available on-line:
   116  
   117  	http://download.intel.com/design/PentiumII/manuals/242816.htm
   118  
   119  
   120  
   121  ----------------
   122  Local variables:
   123  mode: text
   124  fill-column: 76
   125  End: