github.com/aloncn/graphics-go@v0.0.1/src/cmd/compile/internal/ppc64/prog.go (about) 1 // Copyright 2014 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package ppc64 6 7 import ( 8 "cmd/compile/internal/gc" 9 "cmd/internal/obj" 10 "cmd/internal/obj/ppc64" 11 ) 12 13 const ( 14 LeftRdwr uint32 = gc.LeftRead | gc.LeftWrite 15 RightRdwr uint32 = gc.RightRead | gc.RightWrite 16 ) 17 18 // This table gives the basic information about instruction 19 // generated by the compiler and processed in the optimizer. 20 // See opt.h for bit definitions. 21 // 22 // Instructions not generated need not be listed. 23 // As an exception to that rule, we typically write down all the 24 // size variants of an operation even if we just use a subset. 25 // 26 // The table is formatted for 8-space tabs. 27 var progtable = [ppc64.ALAST]obj.ProgInfo{ 28 obj.ATYPE: {Flags: gc.Pseudo | gc.Skip}, 29 obj.ATEXT: {Flags: gc.Pseudo}, 30 obj.AFUNCDATA: {Flags: gc.Pseudo}, 31 obj.APCDATA: {Flags: gc.Pseudo}, 32 obj.AUNDEF: {Flags: gc.Break}, 33 obj.AUSEFIELD: {Flags: gc.OK}, 34 obj.ACHECKNIL: {Flags: gc.LeftRead}, 35 obj.AVARDEF: {Flags: gc.Pseudo | gc.RightWrite}, 36 obj.AVARKILL: {Flags: gc.Pseudo | gc.RightWrite}, 37 obj.AVARLIVE: {Flags: gc.Pseudo | gc.LeftRead}, 38 39 // NOP is an internal no-op that also stands 40 // for USED and SET annotations, not the Power opcode. 41 obj.ANOP: {Flags: gc.LeftRead | gc.RightWrite}, 42 43 // Integer 44 ppc64.AADD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 45 ppc64.ASUB: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 46 ppc64.ANEG: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 47 ppc64.AAND: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 48 ppc64.AOR: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 49 ppc64.AXOR: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 50 ppc64.AMULLD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 51 ppc64.AMULLW: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 52 ppc64.AMULHD: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 53 ppc64.AMULHDU: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite}, 54 ppc64.ADIVD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 55 ppc64.ADIVDU: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 56 ppc64.ASLD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 57 ppc64.ASRD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 58 ppc64.ASRAD: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite}, 59 ppc64.ACMP: {Flags: gc.SizeQ | gc.LeftRead | gc.RightRead}, 60 ppc64.ACMPU: {Flags: gc.SizeQ | gc.LeftRead | gc.RightRead}, 61 ppc64.ATD: {Flags: gc.SizeQ | gc.RightRead}, 62 63 // Floating point. 64 ppc64.AFADD: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite}, 65 ppc64.AFADDS: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 66 ppc64.AFSUB: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite}, 67 ppc64.AFSUBS: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 68 ppc64.AFMUL: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite}, 69 ppc64.AFMULS: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 70 ppc64.AFDIV: {Flags: gc.SizeD | gc.LeftRead | gc.RegRead | gc.RightWrite}, 71 ppc64.AFDIVS: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 72 ppc64.AFCTIDZ: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 73 ppc64.AFCFID: {Flags: gc.SizeF | gc.LeftRead | gc.RegRead | gc.RightWrite}, 74 ppc64.AFCMPU: {Flags: gc.SizeD | gc.LeftRead | gc.RightRead}, 75 ppc64.AFRSP: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv}, 76 77 // Moves 78 ppc64.AMOVB: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 79 ppc64.AMOVBU: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc}, 80 ppc64.AMOVBZ: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 81 ppc64.AMOVH: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 82 ppc64.AMOVHU: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc}, 83 ppc64.AMOVHZ: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 84 ppc64.AMOVW: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 85 86 // there is no AMOVWU. 87 ppc64.AMOVWZU: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc}, 88 ppc64.AMOVWZ: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 89 ppc64.AMOVD: {Flags: gc.SizeQ | gc.LeftRead | gc.RightWrite | gc.Move}, 90 ppc64.AMOVDU: {Flags: gc.SizeQ | gc.LeftRead | gc.RightWrite | gc.Move | gc.PostInc}, 91 ppc64.AFMOVS: {Flags: gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv}, 92 ppc64.AFMOVD: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Move}, 93 94 // Jumps 95 ppc64.ABR: {Flags: gc.Jump | gc.Break}, 96 ppc64.ABL: {Flags: gc.Call}, 97 ppc64.ABEQ: {Flags: gc.Cjmp}, 98 ppc64.ABNE: {Flags: gc.Cjmp}, 99 ppc64.ABGE: {Flags: gc.Cjmp}, 100 ppc64.ABLT: {Flags: gc.Cjmp}, 101 ppc64.ABGT: {Flags: gc.Cjmp}, 102 ppc64.ABLE: {Flags: gc.Cjmp}, 103 obj.ARET: {Flags: gc.Break}, 104 obj.ADUFFZERO: {Flags: gc.Call}, 105 obj.ADUFFCOPY: {Flags: gc.Call}, 106 } 107 108 var initproginfo_initialized int 109 110 func initproginfo() { 111 var addvariant = []int{V_CC, V_V, V_CC | V_V} 112 113 if initproginfo_initialized != 0 { 114 return 115 } 116 initproginfo_initialized = 1 117 118 // Perform one-time expansion of instructions in progtable to 119 // their CC, V, and VCC variants 120 var as2 int 121 var i int 122 var variant int 123 for as := int(0); as < len(progtable); as++ { 124 if progtable[as].Flags == 0 { 125 continue 126 } 127 variant = as2variant(as) 128 for i = 0; i < len(addvariant); i++ { 129 as2 = variant2as(as, variant|addvariant[i]) 130 if as2 != 0 && progtable[as2].Flags == 0 { 131 progtable[as2] = progtable[as] 132 } 133 } 134 } 135 } 136 137 func proginfo(p *obj.Prog) { 138 initproginfo() 139 140 info := &p.Info 141 *info = progtable[p.As] 142 if info.Flags == 0 { 143 gc.Fatalf("proginfo: unknown instruction %v", p) 144 } 145 146 if (info.Flags&gc.RegRead != 0) && p.Reg == 0 { 147 info.Flags &^= gc.RegRead 148 info.Flags |= gc.RightRead /*CanRegRead |*/ 149 } 150 151 if (p.From.Type == obj.TYPE_MEM || p.From.Type == obj.TYPE_ADDR) && p.From.Reg != 0 { 152 info.Regindex |= RtoB(int(p.From.Reg)) 153 if info.Flags&gc.PostInc != 0 { 154 info.Regset |= RtoB(int(p.From.Reg)) 155 } 156 } 157 158 if (p.To.Type == obj.TYPE_MEM || p.To.Type == obj.TYPE_ADDR) && p.To.Reg != 0 { 159 info.Regindex |= RtoB(int(p.To.Reg)) 160 if info.Flags&gc.PostInc != 0 { 161 info.Regset |= RtoB(int(p.To.Reg)) 162 } 163 } 164 165 if p.From.Type == obj.TYPE_ADDR && p.From.Sym != nil && (info.Flags&gc.LeftRead != 0) { 166 info.Flags &^= gc.LeftRead 167 info.Flags |= gc.LeftAddr 168 } 169 170 if p.As == obj.ADUFFZERO { 171 info.Reguse |= 1<<0 | RtoB(ppc64.REG_R3) 172 info.Regset |= RtoB(ppc64.REG_R3) 173 } 174 175 if p.As == obj.ADUFFCOPY { 176 // TODO(austin) Revisit when duffcopy is implemented 177 info.Reguse |= RtoB(ppc64.REG_R3) | RtoB(ppc64.REG_R4) | RtoB(ppc64.REG_R5) 178 179 info.Regset |= RtoB(ppc64.REG_R3) | RtoB(ppc64.REG_R4) 180 } 181 } 182 183 // Instruction variants table. Initially this contains entries only 184 // for the "base" form of each instruction. On the first call to 185 // as2variant or variant2as, we'll add the variants to the table. 186 var varianttable = [ppc64.ALAST][4]int{ 187 ppc64.AADD: {ppc64.AADD, ppc64.AADDCC, ppc64.AADDV, ppc64.AADDVCC}, 188 ppc64.AADDC: {ppc64.AADDC, ppc64.AADDCCC, ppc64.AADDCV, ppc64.AADDCVCC}, 189 ppc64.AADDE: {ppc64.AADDE, ppc64.AADDECC, ppc64.AADDEV, ppc64.AADDEVCC}, 190 ppc64.AADDME: {ppc64.AADDME, ppc64.AADDMECC, ppc64.AADDMEV, ppc64.AADDMEVCC}, 191 ppc64.AADDZE: {ppc64.AADDZE, ppc64.AADDZECC, ppc64.AADDZEV, ppc64.AADDZEVCC}, 192 ppc64.AAND: {ppc64.AAND, ppc64.AANDCC, 0, 0}, 193 ppc64.AANDN: {ppc64.AANDN, ppc64.AANDNCC, 0, 0}, 194 ppc64.ACNTLZD: {ppc64.ACNTLZD, ppc64.ACNTLZDCC, 0, 0}, 195 ppc64.ACNTLZW: {ppc64.ACNTLZW, ppc64.ACNTLZWCC, 0, 0}, 196 ppc64.ADIVD: {ppc64.ADIVD, ppc64.ADIVDCC, ppc64.ADIVDV, ppc64.ADIVDVCC}, 197 ppc64.ADIVDU: {ppc64.ADIVDU, ppc64.ADIVDUCC, ppc64.ADIVDUV, ppc64.ADIVDUVCC}, 198 ppc64.ADIVW: {ppc64.ADIVW, ppc64.ADIVWCC, ppc64.ADIVWV, ppc64.ADIVWVCC}, 199 ppc64.ADIVWU: {ppc64.ADIVWU, ppc64.ADIVWUCC, ppc64.ADIVWUV, ppc64.ADIVWUVCC}, 200 ppc64.AEQV: {ppc64.AEQV, ppc64.AEQVCC, 0, 0}, 201 ppc64.AEXTSB: {ppc64.AEXTSB, ppc64.AEXTSBCC, 0, 0}, 202 ppc64.AEXTSH: {ppc64.AEXTSH, ppc64.AEXTSHCC, 0, 0}, 203 ppc64.AEXTSW: {ppc64.AEXTSW, ppc64.AEXTSWCC, 0, 0}, 204 ppc64.AFABS: {ppc64.AFABS, ppc64.AFABSCC, 0, 0}, 205 ppc64.AFADD: {ppc64.AFADD, ppc64.AFADDCC, 0, 0}, 206 ppc64.AFADDS: {ppc64.AFADDS, ppc64.AFADDSCC, 0, 0}, 207 ppc64.AFCFID: {ppc64.AFCFID, ppc64.AFCFIDCC, 0, 0}, 208 ppc64.AFCTID: {ppc64.AFCTID, ppc64.AFCTIDCC, 0, 0}, 209 ppc64.AFCTIDZ: {ppc64.AFCTIDZ, ppc64.AFCTIDZCC, 0, 0}, 210 ppc64.AFCTIW: {ppc64.AFCTIW, ppc64.AFCTIWCC, 0, 0}, 211 ppc64.AFCTIWZ: {ppc64.AFCTIWZ, ppc64.AFCTIWZCC, 0, 0}, 212 ppc64.AFDIV: {ppc64.AFDIV, ppc64.AFDIVCC, 0, 0}, 213 ppc64.AFDIVS: {ppc64.AFDIVS, ppc64.AFDIVSCC, 0, 0}, 214 ppc64.AFMADD: {ppc64.AFMADD, ppc64.AFMADDCC, 0, 0}, 215 ppc64.AFMADDS: {ppc64.AFMADDS, ppc64.AFMADDSCC, 0, 0}, 216 ppc64.AFMOVD: {ppc64.AFMOVD, ppc64.AFMOVDCC, 0, 0}, 217 ppc64.AFMSUB: {ppc64.AFMSUB, ppc64.AFMSUBCC, 0, 0}, 218 ppc64.AFMSUBS: {ppc64.AFMSUBS, ppc64.AFMSUBSCC, 0, 0}, 219 ppc64.AFMUL: {ppc64.AFMUL, ppc64.AFMULCC, 0, 0}, 220 ppc64.AFMULS: {ppc64.AFMULS, ppc64.AFMULSCC, 0, 0}, 221 ppc64.AFNABS: {ppc64.AFNABS, ppc64.AFNABSCC, 0, 0}, 222 ppc64.AFNEG: {ppc64.AFNEG, ppc64.AFNEGCC, 0, 0}, 223 ppc64.AFNMADD: {ppc64.AFNMADD, ppc64.AFNMADDCC, 0, 0}, 224 ppc64.AFNMADDS: {ppc64.AFNMADDS, ppc64.AFNMADDSCC, 0, 0}, 225 ppc64.AFNMSUB: {ppc64.AFNMSUB, ppc64.AFNMSUBCC, 0, 0}, 226 ppc64.AFNMSUBS: {ppc64.AFNMSUBS, ppc64.AFNMSUBSCC, 0, 0}, 227 ppc64.AFRES: {ppc64.AFRES, ppc64.AFRESCC, 0, 0}, 228 ppc64.AFRSP: {ppc64.AFRSP, ppc64.AFRSPCC, 0, 0}, 229 ppc64.AFRSQRTE: {ppc64.AFRSQRTE, ppc64.AFRSQRTECC, 0, 0}, 230 ppc64.AFSEL: {ppc64.AFSEL, ppc64.AFSELCC, 0, 0}, 231 ppc64.AFSQRT: {ppc64.AFSQRT, ppc64.AFSQRTCC, 0, 0}, 232 ppc64.AFSQRTS: {ppc64.AFSQRTS, ppc64.AFSQRTSCC, 0, 0}, 233 ppc64.AFSUB: {ppc64.AFSUB, ppc64.AFSUBCC, 0, 0}, 234 ppc64.AFSUBS: {ppc64.AFSUBS, ppc64.AFSUBSCC, 0, 0}, 235 ppc64.AMTFSB0: {ppc64.AMTFSB0, ppc64.AMTFSB0CC, 0, 0}, 236 ppc64.AMTFSB1: {ppc64.AMTFSB1, ppc64.AMTFSB1CC, 0, 0}, 237 ppc64.AMULHD: {ppc64.AMULHD, ppc64.AMULHDCC, 0, 0}, 238 ppc64.AMULHDU: {ppc64.AMULHDU, ppc64.AMULHDUCC, 0, 0}, 239 ppc64.AMULHW: {ppc64.AMULHW, ppc64.AMULHWCC, 0, 0}, 240 ppc64.AMULHWU: {ppc64.AMULHWU, ppc64.AMULHWUCC, 0, 0}, 241 ppc64.AMULLD: {ppc64.AMULLD, ppc64.AMULLDCC, ppc64.AMULLDV, ppc64.AMULLDVCC}, 242 ppc64.AMULLW: {ppc64.AMULLW, ppc64.AMULLWCC, ppc64.AMULLWV, ppc64.AMULLWVCC}, 243 ppc64.ANAND: {ppc64.ANAND, ppc64.ANANDCC, 0, 0}, 244 ppc64.ANEG: {ppc64.ANEG, ppc64.ANEGCC, ppc64.ANEGV, ppc64.ANEGVCC}, 245 ppc64.ANOR: {ppc64.ANOR, ppc64.ANORCC, 0, 0}, 246 ppc64.AOR: {ppc64.AOR, ppc64.AORCC, 0, 0}, 247 ppc64.AORN: {ppc64.AORN, ppc64.AORNCC, 0, 0}, 248 ppc64.AREM: {ppc64.AREM, ppc64.AREMCC, ppc64.AREMV, ppc64.AREMVCC}, 249 ppc64.AREMD: {ppc64.AREMD, ppc64.AREMDCC, ppc64.AREMDV, ppc64.AREMDVCC}, 250 ppc64.AREMDU: {ppc64.AREMDU, ppc64.AREMDUCC, ppc64.AREMDUV, ppc64.AREMDUVCC}, 251 ppc64.AREMU: {ppc64.AREMU, ppc64.AREMUCC, ppc64.AREMUV, ppc64.AREMUVCC}, 252 ppc64.ARLDC: {ppc64.ARLDC, ppc64.ARLDCCC, 0, 0}, 253 ppc64.ARLDCL: {ppc64.ARLDCL, ppc64.ARLDCLCC, 0, 0}, 254 ppc64.ARLDCR: {ppc64.ARLDCR, ppc64.ARLDCRCC, 0, 0}, 255 ppc64.ARLDMI: {ppc64.ARLDMI, ppc64.ARLDMICC, 0, 0}, 256 ppc64.ARLWMI: {ppc64.ARLWMI, ppc64.ARLWMICC, 0, 0}, 257 ppc64.ARLWNM: {ppc64.ARLWNM, ppc64.ARLWNMCC, 0, 0}, 258 ppc64.ASLD: {ppc64.ASLD, ppc64.ASLDCC, 0, 0}, 259 ppc64.ASLW: {ppc64.ASLW, ppc64.ASLWCC, 0, 0}, 260 ppc64.ASRAD: {ppc64.ASRAD, ppc64.ASRADCC, 0, 0}, 261 ppc64.ASRAW: {ppc64.ASRAW, ppc64.ASRAWCC, 0, 0}, 262 ppc64.ASRD: {ppc64.ASRD, ppc64.ASRDCC, 0, 0}, 263 ppc64.ASRW: {ppc64.ASRW, ppc64.ASRWCC, 0, 0}, 264 ppc64.ASUB: {ppc64.ASUB, ppc64.ASUBCC, ppc64.ASUBV, ppc64.ASUBVCC}, 265 ppc64.ASUBC: {ppc64.ASUBC, ppc64.ASUBCCC, ppc64.ASUBCV, ppc64.ASUBCVCC}, 266 ppc64.ASUBE: {ppc64.ASUBE, ppc64.ASUBECC, ppc64.ASUBEV, ppc64.ASUBEVCC}, 267 ppc64.ASUBME: {ppc64.ASUBME, ppc64.ASUBMECC, ppc64.ASUBMEV, ppc64.ASUBMEVCC}, 268 ppc64.ASUBZE: {ppc64.ASUBZE, ppc64.ASUBZECC, ppc64.ASUBZEV, ppc64.ASUBZEVCC}, 269 ppc64.AXOR: {ppc64.AXOR, ppc64.AXORCC, 0, 0}, 270 } 271 272 var initvariants_initialized int 273 274 func initvariants() { 275 if initvariants_initialized != 0 { 276 return 277 } 278 initvariants_initialized = 1 279 280 var j int 281 for i := int(0); i < len(varianttable); i++ { 282 if varianttable[i][0] == 0 { 283 // Instruction has no variants 284 varianttable[i][0] = i 285 286 continue 287 } 288 289 // Copy base form to other variants 290 if varianttable[i][0] == i { 291 for j = 0; j < len(varianttable[i]); j++ { 292 varianttable[varianttable[i][j]] = varianttable[i] 293 } 294 } 295 } 296 } 297 298 // as2variant returns the variant (V_*) flags of instruction as. 299 func as2variant(as int) int { 300 initvariants() 301 for i := int(0); i < len(varianttable[as]); i++ { 302 if varianttable[as][i] == as { 303 return i 304 } 305 } 306 gc.Fatalf("as2variant: instruction %v is not a variant of itself", obj.Aconv(as)) 307 return 0 308 } 309 310 // variant2as returns the instruction as with the given variant (V_*) flags. 311 // If no such variant exists, this returns 0. 312 func variant2as(as int, flags int) int { 313 initvariants() 314 return varianttable[as][flags] 315 }