github.com/aykevl/tinygo@v0.5.0/src/device/stm32/stm32f103xx-bitfields.go (about)

     1  // Hand created file. DO NOT DELETE.
     2  // STM32F103XX bitfield definitions that are not auto-generated by gen-device-svd.py
     3  
     4  // +build stm32,stm32f103xx
     5  
     6  package stm32
     7  
     8  const (
     9  	// Flash Access Control Register flag values.
    10  	FLASH_ACR_LATENCY_0 = 0x00000001
    11  	FLASH_ACR_LATENCY_1 = 0x00000002
    12  	FLASH_ACR_LATENCY_2 = 0x00000004
    13  
    14  	// Reset and Clock Control Control Register flag values.
    15  
    16  	// System Clock source
    17  	RCC_CFGR_SW_HSI = 0
    18  	RCC_CFGR_SW_HSE = 1
    19  	RCC_CFGR_SW_PLL = 2
    20  
    21  	// Flags for when System Clock source is set.
    22  	RCC_CFGR_SWS_HSI = 0x00000000
    23  	RCC_CFGR_SWS_HSE = 0x00000004
    24  	RCC_CFGR_SWS_PLL = 0x00000008
    25  
    26  	// Sets PCLK1
    27  	RCC_CFGR_PPRE1_DIV_NONE = 0x00000000
    28  	RCC_CFGR_PPRE1_DIV_2    = 0x00000400
    29  	RCC_CFGR_PPRE1_DIV_4    = 0x00000500
    30  	RCC_CFGR_PPRE1_DIV_8    = 0x00000600
    31  	RCC_CFGR_PPRE1_DIV_16   = 0x00000700
    32  
    33  	// Sets PCLK2
    34  	RCC_CFGR_PPRE2_DIV_NONE = 0x00000000
    35  	RCC_CFGR_PPRE2_DIV_2    = 0x00002000
    36  	RCC_CFGR_PPRE2_DIV_4    = 0x00002800
    37  	RCC_CFGR_PPRE2_DIV_8    = 0x00003000
    38  	RCC_CFGR_PPRE2_DIV_16   = 0x00003800
    39  
    40  	// Sets PLL multiplier
    41  	RCC_CFGR_PLLMUL_2  = 0x00000000
    42  	RCC_CFGR_PLLMUL_3  = 0x00040000
    43  	RCC_CFGR_PLLMUL_4  = 0x00080000
    44  	RCC_CFGR_PLLMUL_5  = 0x000C0000
    45  	RCC_CFGR_PLLMUL_6  = 0x00100000
    46  	RCC_CFGR_PLLMUL_7  = 0x00140000
    47  	RCC_CFGR_PLLMUL_8  = 0x00180000
    48  	RCC_CFGR_PLLMUL_9  = 0x001C0000
    49  	RCC_CFGR_PLLMUL_10 = 0x00200000
    50  	RCC_CFGR_PLLMUL_11 = 0x00240000
    51  	RCC_CFGR_PLLMUL_12 = 0x00280000
    52  	RCC_CFGR_PLLMUL_13 = 0x002C0000
    53  	RCC_CFGR_PLLMUL_14 = 0x00300000
    54  	RCC_CFGR_PLLMUL_15 = 0x00340000
    55  	RCC_CFGR_PLLMUL_16 = 0x00380000
    56  
    57  	// RTC clock source
    58  	RCC_RTCCLKSource_LSE        = 0x00000100
    59  	RCC_RTCCLKSource_LSI        = 0x00000200
    60  	RCC_RTCCLKSource_HSE_Div128 = 0x00000300
    61  
    62  	// SPI settings
    63  	SPI_FirstBit_MSB = 0x0000
    64  	SPI_FirstBit_LSB = 0x0080
    65  
    66  	SPI_BaudRatePrescaler_2   = 0x0000
    67  	SPI_BaudRatePrescaler_4   = 0x0008
    68  	SPI_BaudRatePrescaler_8   = 0x0010
    69  	SPI_BaudRatePrescaler_16  = 0x0018
    70  	SPI_BaudRatePrescaler_32  = 0x0020
    71  	SPI_BaudRatePrescaler_64  = 0x0028
    72  	SPI_BaudRatePrescaler_128 = 0x0030
    73  	SPI_BaudRatePrescaler_256 = 0x0038
    74  
    75  	SPI_Direction_2Lines_FullDuplex = 0x0000
    76  	SPI_Direction_2Lines_RxOnly     = 0x0400
    77  	SPI_Direction_1Line_Rx          = 0x8000
    78  	SPI_Direction_1Line_Tx          = 0xC000
    79  
    80  	SPI_Mode_Master = 0x0104
    81  	SPI_Mode_Slave  = 0x0000
    82  
    83  	SPI_NSS_Soft = 0x0200
    84  	SPI_NSS_Hard = 0x0000
    85  
    86  	SPI_NSSInternalSoft_Set   = 0x0100
    87  	SPI_NSSInternalSoft_Reset = 0xFEFF
    88  )