github.com/bananabytelabs/wazero@v0.0.0-20240105073314-54b22a776da8/internal/asm/arm64/assembler.go (about)

     1  package arm64
     2  
     3  import (
     4  	"github.com/bananabytelabs/wazero/internal/asm"
     5  )
     6  
     7  // Assembler is the interface for arm64 specific assembler.
     8  type Assembler interface {
     9  	asm.AssemblerBase
    10  
    11  	// CompileMemoryWithRegisterOffsetToRegister adds an instruction where source operand is the memory address
    12  	// specified as `srcBaseReg + srcOffsetReg` and dst is the register `dstReg`.
    13  	CompileMemoryWithRegisterOffsetToRegister(instruction asm.Instruction, srcBaseReg, srcOffsetReg, dstReg asm.Register)
    14  
    15  	// CompileRegisterToMemoryWithRegisterOffset adds an instruction where source operand is the register `srcReg`,
    16  	// and the destination is the memory address specified as `dstBaseReg + dstOffsetReg`
    17  	CompileRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg, dstOffsetReg asm.Register)
    18  
    19  	// CompileTwoRegistersToRegister adds an instruction where source operands consists of two registers `src1` and `src2`,
    20  	// and the destination is the register `dst`.
    21  	CompileTwoRegistersToRegister(instruction asm.Instruction, src1, src2, dst asm.Register)
    22  
    23  	// CompileThreeRegistersToRegister adds an instruction where source operands consist of three registers
    24  	// `src1`, `src2` and `src3`, and destination operands consist of `dst` register.
    25  	CompileThreeRegistersToRegister(instruction asm.Instruction, src1, src2, src3, dst asm.Register)
    26  
    27  	// CompileTwoRegistersToNone adds an instruction where source operands consist of two registers `src1` and `src2`,
    28  	// and destination operand is unspecified.
    29  	CompileTwoRegistersToNone(instruction asm.Instruction, src1, src2 asm.Register)
    30  
    31  	// CompileRegisterAndConstToNone adds an instruction where source operands consist of one register `src` and
    32  	// constant `srcConst`, and destination operand is unspecified.
    33  	CompileRegisterAndConstToNone(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue)
    34  
    35  	// CompileRegisterAndConstToRegister adds an instruction where source operands consist of one register `src` and
    36  	// constant `srcConst`, and destination operand is a register `dst`.
    37  	CompileRegisterAndConstToRegister(instruction asm.Instruction, src asm.Register, srcConst asm.ConstantValue, dst asm.Register)
    38  
    39  	// CompileLeftShiftedRegisterToRegister adds an instruction where source operand is the "left shifted register"
    40  	// represented as `srcReg << shiftNum` and the destination is the register `dstReg`.
    41  	CompileLeftShiftedRegisterToRegister(
    42  		instruction asm.Instruction,
    43  		shiftedSourceReg asm.Register,
    44  		shiftNum asm.ConstantValue,
    45  		srcReg, dstReg asm.Register,
    46  	)
    47  
    48  	// CompileConditionalRegisterSet adds an instruction to set 1 on dstReg if the condition satisfies,
    49  	// otherwise set 0.
    50  	CompileConditionalRegisterSet(cond asm.ConditionalRegisterState, dstReg asm.Register)
    51  
    52  	// CompileMemoryToVectorRegister adds an instruction where source operands is the memory address specified by
    53  	// `srcBaseReg+srcOffset` and the destination is `dstReg` vector register.
    54  	CompileMemoryToVectorRegister(instruction asm.Instruction, srcBaseReg asm.Register, srcOffset asm.ConstantValue,
    55  		dstReg asm.Register, arrangement VectorArrangement)
    56  
    57  	// CompileMemoryWithRegisterOffsetToVectorRegister is the same as CompileMemoryToVectorRegister except that the
    58  	// offset is specified by the `srcOffsetRegister` register.
    59  	CompileMemoryWithRegisterOffsetToVectorRegister(instruction asm.Instruction, srcBaseReg,
    60  		srcOffsetRegister asm.Register, dstReg asm.Register, arrangement VectorArrangement)
    61  
    62  	// CompileVectorRegisterToMemory adds an instruction where source operand is `srcReg` vector register and the
    63  	// destination is the memory address specified by `dstBaseReg+dstOffset`.
    64  	CompileVectorRegisterToMemory(instruction asm.Instruction, srcReg, dstBaseReg asm.Register,
    65  		dstOffset asm.ConstantValue, arrangement VectorArrangement)
    66  
    67  	// CompileVectorRegisterToMemoryWithRegisterOffset is the same as CompileVectorRegisterToMemory except that the
    68  	// offset is specified by the `dstOffsetRegister` register.
    69  	CompileVectorRegisterToMemoryWithRegisterOffset(instruction asm.Instruction, srcReg, dstBaseReg,
    70  		dstOffsetRegister asm.Register, arrangement VectorArrangement)
    71  
    72  	// CompileRegisterToVectorRegister adds an instruction where source operand is `srcReg` general purpose register and
    73  	// the destination is the `dstReg` vector register. The destination vector's arrangement and index of element can be
    74  	// given by `arrangement` and `index`, but not all the instructions will use them.
    75  	CompileRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
    76  		arrangement VectorArrangement, index VectorIndex)
    77  
    78  	// CompileVectorRegisterToRegister adds an instruction where destination operand is `dstReg` general purpose register
    79  	// and the source is the `srcReg` vector register. The source vector's arrangement and index of element can be
    80  	// given by `arrangement` and `index`, but not all the instructions will use them.
    81  	CompileVectorRegisterToRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
    82  		arrangement VectorArrangement, index VectorIndex)
    83  
    84  	// CompileVectorRegisterToVectorRegister adds an instruction where both source and destination operands are vector
    85  	// registers. The vector's arrangement can be specified `arrangement`, and the source and destination element's
    86  	// index are given by `srcIndex` and `dstIndex` respectively, but not all the instructions will use them.
    87  	CompileVectorRegisterToVectorRegister(instruction asm.Instruction, srcReg, dstReg asm.Register,
    88  		arrangement VectorArrangement, srcIndex, dstIndex VectorIndex)
    89  
    90  	// CompileVectorRegisterToVectorRegisterWithConst is the same as CompileVectorRegisterToVectorRegister but the
    91  	// additional constant can be provided.
    92  	// For example, the const can be used to specify the shift amount for USHLL instruction.
    93  	CompileVectorRegisterToVectorRegisterWithConst(instruction asm.Instruction, srcReg, dstReg asm.Register,
    94  		arrangement VectorArrangement, c asm.ConstantValue)
    95  
    96  	// CompileStaticConstToRegister adds an instruction where the source operand is StaticConstant located in
    97  	// the memory and the destination is the dstReg.
    98  	CompileStaticConstToRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register)
    99  
   100  	// CompileStaticConstToVectorRegister adds an instruction where the source operand is StaticConstant located in
   101  	// the memory and the destination is the dstReg.
   102  	CompileStaticConstToVectorRegister(instruction asm.Instruction, c *asm.StaticConst, dstReg asm.Register,
   103  		arrangement VectorArrangement)
   104  
   105  	// CompileTwoVectorRegistersToVectorRegister adds an instruction where source are two vectors and destination is one
   106  	// vector. The vector's arrangement can be specified `arrangement`.
   107  	CompileTwoVectorRegistersToVectorRegister(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register,
   108  		arrangement VectorArrangement)
   109  
   110  	// CompileTwoVectorRegistersToVectorRegisterWithConst is the same as CompileTwoVectorRegistersToVectorRegister except
   111  	// that this also accept additional constant.
   112  	// For example EXIT instruction needs the extraction target immediate as const.
   113  	CompileTwoVectorRegistersToVectorRegisterWithConst(instruction asm.Instruction, srcReg, srcReg2, dstReg asm.Register,
   114  		arrangement VectorArrangement, c asm.ConstantValue)
   115  }