github.com/bananabytelabs/wazero@v0.0.0-20240105073314-54b22a776da8/internal/asm/arm64/consts.go (about) 1 package arm64 2 3 import ( 4 "fmt" 5 6 "github.com/bananabytelabs/wazero/internal/asm" 7 ) 8 9 // Arm64-specific register states. 10 // 11 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 12 // See https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/condition-codes-1-condition-flags-and-codes 13 const ( 14 // CondEQ is the eq (equal) condition code 15 CondEQ = asm.ConditionalRegisterStateUnset + 1 + iota 16 // CondNE is the ne (not equal) condition code 17 CondNE 18 // CondHS is the hs (unsigned higher or same) condition code 19 CondHS 20 // CondLO is the lo (unsigned lower) condition code 21 CondLO 22 // CondMI is the mi (negative) condition code 23 CondMI 24 // CondPL is the pl (positive or zero) condition code 25 CondPL 26 // CondVS is the vs (signed overflow) condition code 27 CondVS 28 // CondVC is the vc (no signed overflow) condition code 29 CondVC 30 // CondHI is the hi (unsigned higher) condition code 31 CondHI 32 // CondLS is the ls (unsigned lower or same) condition code 33 CondLS 34 // CondGE is the ge (signed greater than or equal) condition code 35 CondGE 36 // CondLT is the lt (signed less than) condition code 37 CondLT 38 // CondGT is the gt (signed greater than) condition code 39 CondGT 40 // CondLE is the le (signed less than or equal) condition code 41 CondLE 42 // CondAL is the al (always executed) condition code 43 CondAL 44 // CondNV has the same meaning as CondAL 45 CondNV 46 ) 47 48 // Arm64-specific registers. 49 // 50 // Note: Naming conventions intentionally match the Go assembler: https://go.dev/doc/asm 51 // See https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Predeclared-core-register-names-in-AArch64-state 52 const ( 53 // Integer registers. 54 55 // RegR0 is the R0 register 56 RegR0 asm.Register = asm.NilRegister + 1 + iota 57 // RegR1 is the R1 register 58 RegR1 59 // RegR2 is the R2 register 60 RegR2 61 // RegR3 is the R3 register 62 RegR3 63 // RegR4 is the R4 register 64 RegR4 65 // RegR5 is the R5 register 66 RegR5 67 // RegR6 is the R6 register 68 RegR6 69 // RegR7 is the R7 register 70 RegR7 71 // RegR8 is the R8 register 72 RegR8 73 // RegR9 is the R9 register 74 RegR9 75 // RegR10 is the R10 register 76 RegR10 77 // RegR11 is the R11 register 78 RegR11 79 // RegR12 is the R12 register 80 RegR12 81 // RegR13 is the R13 register 82 RegR13 83 // RegR14 is the R14 register 84 RegR14 85 // RegR15 is the R15 register 86 RegR15 87 // RegR16 is the R16 register 88 RegR16 89 // RegR17 is the R17 register 90 RegR17 91 // RegR18 is the R18 register 92 RegR18 93 // RegR19 is the R19 register 94 RegR19 95 // RegR20 is the R20 register 96 RegR20 97 // RegR21 is the R21 register 98 RegR21 99 // RegR22 is the R22 register 100 RegR22 101 // RegR23 is the R23 register 102 RegR23 103 // RegR24 is the R24 register 104 RegR24 105 // RegR25 is the R25 register 106 RegR25 107 // RegR26 is the R26 register 108 RegR26 109 // RegR27 is the R27 register 110 RegR27 111 // RegR28 is the R28 register 112 RegR28 113 // RegR29 is the R29 register 114 RegR29 115 // RegR30 is the R30 register 116 RegR30 117 // RegRZR is the RZR register (read-only, always returning zero) 118 RegRZR 119 // RegSP is the SP register 120 RegSP 121 122 // Scalar floating point registers. 123 124 // RegV0 is the V0 register 125 RegV0 126 // RegV1 is the V1 register 127 RegV1 128 // RegV2 is the V2 register 129 RegV2 130 // RegV3 is the V3 register 131 RegV3 132 // RegV4 is the V4 register 133 RegV4 134 // RegV5 is the V5 register 135 RegV5 136 // RegV6 is the V6 register 137 RegV6 138 // RegV7 is the V7 register 139 RegV7 140 // RegV8 is the V8 register 141 RegV8 142 // RegV9 is the V9 register 143 RegV9 144 // RegV10 is the V10 register 145 RegV10 146 // RegV11 is the V11 register 147 RegV11 148 // RegV12 is the V12 register 149 RegV12 150 // RegV13 is the V13 register 151 RegV13 152 // RegV14 is the V14 register 153 RegV14 154 // RegV15 is the V15 register 155 RegV15 156 // RegV16 is the V16 register 157 RegV16 158 // RegV17 is the V17 register 159 RegV17 160 // RegV18 is the V18 register 161 RegV18 162 // RegV19 is the V19 register 163 RegV19 164 // RegV20 is the V20 register 165 RegV20 166 // RegV21 is the V21 register 167 RegV21 168 // RegV22 is the V22 register 169 RegV22 170 // RegV23 is the V23 register 171 RegV23 172 // RegV24 is the V24 register 173 RegV24 174 // RegV25 is the V25 register 175 RegV25 176 // RegV26 is the V26 register 177 RegV26 178 // RegV27 is the V27 register 179 RegV27 180 // RegV28 is the V28 register 181 RegV28 182 // RegV29 is the V29 register 183 RegV29 184 // RegV30 is the V30 register 185 RegV30 186 // RegV31 is the V31 register 187 RegV31 188 189 // Floating point status register. 190 191 // RegFPSR is the FPSR register 192 RegFPSR 193 194 // Assign each conditional register state to the unique register ID. 195 // This is to reduce the size of nodeImpl struct without having dedicated field 196 // for conditional register state which would not be used by most nodes. 197 // This is taking advantage of the fact that conditional operations are always 198 // on a single register and condition code, and never two registers. 199 200 // RegCondEQ encodes CondEQ into a field that would otherwise store a register 201 RegCondEQ 202 // RegCondNE encodes CondNE into a field that would otherwise store a register 203 RegCondNE 204 // RegCondHS encodes CondHS into a field that would otherwise store a register 205 RegCondHS 206 // RegCondLO encodes CondLO into a field that would otherwise store a register 207 RegCondLO 208 // RegCondMI encodes CondMI into a field that would otherwise store a register 209 RegCondMI 210 // RegCondPL encodes CondPL into a field that would otherwise store a register 211 RegCondPL 212 // RegCondVS encodes CondVS into a field that would otherwise store a register 213 RegCondVS 214 // RegCondVC encodes CondVC into a field that would otherwise store a register 215 RegCondVC 216 // RegCondHI encodes CondHI into a field that would otherwise store a register 217 RegCondHI 218 // RegCondLS encodes CondLS into a field that would otherwise store a register 219 RegCondLS 220 // RegCondGE encodes CondGE into a field that would otherwise store a register 221 RegCondGE 222 // RegCondLT encodes CondLT into a field that would otherwise store a register 223 RegCondLT 224 // RegCondGT encodes CondGT into a field that would otherwise store a register 225 RegCondGT 226 // RegCondLE encodes CondLE into a field that would otherwise store a register 227 RegCondLE 228 // RegCondAL encodes CondAL into a field that would otherwise store a register 229 RegCondAL 230 // RegCondNV encodes CondNV into a field that would otherwise store a register 231 RegCondNV 232 ) 233 234 // conditionalRegisterStateToRegister cast a conditional register to its unique register ID. 235 // See the comment on RegCondEQ above. 236 func conditionalRegisterStateToRegister(c asm.ConditionalRegisterState) asm.Register { 237 switch c { 238 case CondEQ: 239 return RegCondEQ 240 case CondNE: 241 return RegCondNE 242 case CondHS: 243 return RegCondHS 244 case CondLO: 245 return RegCondLO 246 case CondMI: 247 return RegCondMI 248 case CondPL: 249 return RegCondPL 250 case CondVS: 251 return RegCondVS 252 case CondVC: 253 return RegCondVC 254 case CondHI: 255 return RegCondHI 256 case CondLS: 257 return RegCondLS 258 case CondGE: 259 return RegCondGE 260 case CondLT: 261 return RegCondLT 262 case CondGT: 263 return RegCondGT 264 case CondLE: 265 return RegCondLE 266 case CondAL: 267 return RegCondAL 268 case CondNV: 269 return RegCondNV 270 } 271 return asm.NilRegister 272 } 273 274 // RegisterName returns the name of a given register 275 func RegisterName(r asm.Register) string { 276 switch r { 277 case asm.NilRegister: 278 return "nil" 279 case RegR0: 280 return "R0" 281 case RegR1: 282 return "R1" 283 case RegR2: 284 return "R2" 285 case RegR3: 286 return "R3" 287 case RegR4: 288 return "R4" 289 case RegR5: 290 return "R5" 291 case RegR6: 292 return "R6" 293 case RegR7: 294 return "R7" 295 case RegR8: 296 return "R8" 297 case RegR9: 298 return "R9" 299 case RegR10: 300 return "R10" 301 case RegR11: 302 return "R11" 303 case RegR12: 304 return "R12" 305 case RegR13: 306 return "R13" 307 case RegR14: 308 return "R14" 309 case RegR15: 310 return "R15" 311 case RegR16: 312 return "R16" 313 case RegR17: 314 return "R17" 315 case RegR18: 316 return "R18" 317 case RegR19: 318 return "R19" 319 case RegR20: 320 return "R20" 321 case RegR21: 322 return "R21" 323 case RegR22: 324 return "R22" 325 case RegR23: 326 return "R23" 327 case RegR24: 328 return "R24" 329 case RegR25: 330 return "R25" 331 case RegR26: 332 return "R26" 333 case RegR27: 334 return "R27" 335 case RegR28: 336 return "R28" 337 case RegR29: 338 return "R29" 339 case RegR30: 340 return "R30" 341 case RegRZR: 342 return "RZR" 343 case RegSP: 344 return "SP" 345 case RegV0: 346 return "V0" 347 case RegV1: 348 return "V1" 349 case RegV2: 350 return "V2" 351 case RegV3: 352 return "V3" 353 case RegV4: 354 return "V4" 355 case RegV5: 356 return "V5" 357 case RegV6: 358 return "V6" 359 case RegV7: 360 return "V7" 361 case RegV8: 362 return "V8" 363 case RegV9: 364 return "V9" 365 case RegV10: 366 return "V10" 367 case RegV11: 368 return "V11" 369 case RegV12: 370 return "V12" 371 case RegV13: 372 return "V13" 373 case RegV14: 374 return "V14" 375 case RegV15: 376 return "V15" 377 case RegV16: 378 return "V16" 379 case RegV17: 380 return "V17" 381 case RegV18: 382 return "V18" 383 case RegV19: 384 return "V19" 385 case RegV20: 386 return "V20" 387 case RegV21: 388 return "V21" 389 case RegV22: 390 return "V22" 391 case RegV23: 392 return "V23" 393 case RegV24: 394 return "V24" 395 case RegV25: 396 return "V25" 397 case RegV26: 398 return "V26" 399 case RegV27: 400 return "V27" 401 case RegV28: 402 return "V28" 403 case RegV29: 404 return "V29" 405 case RegV30: 406 return "V30" 407 case RegV31: 408 return "V31" 409 case RegFPSR: 410 return "FPSR" 411 case RegCondEQ: 412 return "COND_EQ" 413 case RegCondNE: 414 return "COND_NE" 415 case RegCondHS: 416 return "COND_HS" 417 case RegCondLO: 418 return "COND_LO" 419 case RegCondMI: 420 return "COND_MI" 421 case RegCondPL: 422 return "COND_PL" 423 case RegCondVS: 424 return "COND_VS" 425 case RegCondVC: 426 return "COND_VC" 427 case RegCondHI: 428 return "COND_HI" 429 case RegCondLS: 430 return "COND_LS" 431 case RegCondGE: 432 return "COND_GE" 433 case RegCondLT: 434 return "COND_LT" 435 case RegCondGT: 436 return "COND_GT" 437 case RegCondLE: 438 return "COND_LE" 439 case RegCondAL: 440 return "COND_AL" 441 case RegCondNV: 442 return "COND_NV" 443 } 444 return "UNKNOWN" 445 } 446 447 // Arm64-specific instructions. 448 // 449 // Note: This only defines arm64 instructions used by wazero's compiler. 450 // Note: Naming conventions partially match the Go assembler: https://go.dev/doc/asm 451 const ( 452 // NOP is the NOP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NOP 453 NOP asm.Instruction = iota 454 // RET is the RET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RET 455 RET 456 // ADD is the ADD instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 457 ADD 458 // ADDS is the ADDS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADDS--shifted-register- 459 ADDS 460 // ADDW is the ADD instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADD--shifted-register- 461 ADDW 462 // ADR is the ADR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ADR 463 ADR 464 // AND is the AND instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--shifted-register- 465 AND 466 // ANDIMM32 is the AND(immediate) instruction in 32-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 467 ANDIMM32 468 // ANDIMM64 is the AND(immediate) instruction in 64-bit mode https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/AND--immediate---Bitwise-AND--immediate--?lang=en 469 ANDIMM64 470 // ANDW is the AND instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/AND--register- 471 ANDW 472 // ASR is the ASR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 473 ASR 474 // ASRW is the ASR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ASR--register- 475 ASRW 476 // B is the B instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B 477 B 478 479 // Below are B.cond instructions. 480 // * https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/B-cond 481 // * https://developer.arm.com/documentation/dui0802/a/A32-and-T32-Instructions/Condition-codes 482 483 // BCONDEQ is the B.cond instruction with CondEQ. 484 BCONDEQ 485 // BCONDGE is the B.cond instruction with CondGE. 486 BCONDGE 487 // BCONDGT is the B.cond instruction with CondGT. 488 BCONDGT 489 // BCONDHI is the B.cond instruction with CondHI. 490 BCONDHI 491 // BCONDHS is the B.cond instruction with CondHS. 492 BCONDHS 493 // BCONDLE is the B.cond instruction with CondLE. 494 BCONDLE 495 // BCONDLO is the B.cond instruction with CondLO. 496 BCONDLO 497 // BCONDLS is the B.cond instruction with CondLS. 498 BCONDLS 499 // BCONDLT is the B.cond instruction with CondLT. 500 BCONDLT 501 // BCONDMI is the B.cond instruction with CondMI. 502 BCONDMI 503 // BCONDPL is the B.cond instruction with CondPL. 504 BCONDPL 505 // BCONDNE is the B.cond instruction with CondNE. 506 BCONDNE 507 // BCONDVS is the B.cond instruction with CondVS. 508 BCONDVS 509 // BCONDVC is the B.cond instruction with CondVC. 510 BCONDVC 511 512 // CLZ is the CLZ instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 513 CLZ 514 // CLZW is the CLZ instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CLZ 515 CLZW 516 // CMP is the CMP instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 517 CMP 518 // CMPW is the CMP instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CMP--shifted-register- 519 CMPW 520 // CSET is the CSET instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/CSET 521 CSET 522 // EOR is the EOR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 523 EOR 524 // EORW is the EOR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/EOR--shifted-register- 525 EORW 526 // FABSD is the FABS instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 527 FABSD 528 // FABSS is the FABS instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FABS--scalar- 529 FABSS 530 // FADDD is the FADD instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 531 FADDD 532 // FADDS is the FADD instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FADD--scalar- 533 FADDS 534 // FCMPD is the FCMP instruction, for double-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 535 FCMPD 536 // FCMPS is the FCMP instruction, for single-precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCMP 537 FCMPS 538 // FCVTDS is the FCVT instruction, for single to double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 539 FCVTDS 540 // FCVTSD is the FCVT instruction, for double to single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVT 541 FCVTSD 542 // FCVTZSD is the FCVTZS instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 543 FCVTZSD 544 // FCVTZSDW is the FCVTZS instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 545 FCVTZSDW 546 // FCVTZSS is the FCVTZS instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 547 FCVTZSS 548 // FCVTZSSW is the FCVTZS instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZS--scalar--integer- 549 FCVTZSSW 550 // FCVTZUD is the FCVTZU instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 551 FCVTZUD 552 // FCVTZUDW is the FCVTZU instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 553 FCVTZUDW 554 // FCVTZUS is the FCVTZU instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 555 FCVTZUS 556 // FCVTZUSW is the FCVTZU instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FCVTZU--scalar--integer- 557 FCVTZUSW 558 // FDIVD is the FDIV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 559 FDIVD 560 // FDIVS is the FDIV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FDIV--scalar- 561 FDIVS 562 // FMAXD is the FMAX instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 563 FMAXD 564 // FMAXS is the FMAX instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMAX--scalar- 565 FMAXS 566 // FMIND is the FMIN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 567 FMIND 568 // FMINS is the FMIN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMIN--scalar- 569 FMINS 570 // FMOVD is the FMOV instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 571 FMOVD 572 // FMOVS is the FMOV instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMOV--register- 573 FMOVS 574 // FMULD is the FMUL instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 575 FMULD 576 // FMULS is the FMUL instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FMUL--scalar- 577 FMULS 578 // FNEGD is the FNEG instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 579 FNEGD 580 // FNEGS is the FNEG instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FNEG--scalar- 581 FNEGS 582 // FRINTMD is the FRINTM instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 583 FRINTMD 584 // FRINTMS is the FRINTM instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTM--scalar- 585 FRINTMS 586 // FRINTND is the FRINTN instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 587 FRINTND 588 // FRINTNS is the FRINTN instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTN--scalar- 589 FRINTNS 590 // FRINTPD is the FRINTP instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 591 FRINTPD 592 // FRINTPS is the FRINTP instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTP--scalar- 593 FRINTPS 594 // FRINTZD is the FRINTZ instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 595 FRINTZD 596 // FRINTZS is the FRINTZ instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FRINTZ--scalar- 597 FRINTZS 598 // FSQRTD is the FSQRT instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 599 FSQRTD 600 // FSQRTS is the FSQRT instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSQRT--scalar- 601 FSQRTS 602 // FSUBD is the FSUB instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 603 FSUBD 604 // FSUBS is the FSUB instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/FSUB--scalar- 605 FSUBS 606 // LSL is the LSL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 607 LSL 608 // LSLW is the LSL instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSL--register- 609 LSLW 610 // LSR is the LSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 611 LSR 612 // LSRW is the LSR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/LSR--register- 613 LSRW 614 // FLDRD is the LDR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 615 FLDRD 616 // FLDRS is the LDR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LDR--register--SIMD-FP---Load-SIMD-FP-Register--register-offset--?lang=en 617 FLDRS 618 // LDRD is the LDR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 619 LDRD 620 // LDRW is the LDR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en 621 LDRW 622 // LDRSBD is the LDRSB instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 623 LDRSBD 624 // LDRSBW is the LDRSB instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSB--register- 625 LDRSBW 626 // LDRB is the LDRB instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--register- 627 LDRB 628 // LDRSHD is the LDRSHW instruction in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 629 LDRSHD 630 // LDRSHW is the LDRSHW instruction in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSH--register- 631 LDRSHW 632 // LDRH is the LDRH instruction. https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--register- 633 LDRH 634 // LDRSW is the LDRSW instruction https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRSW--register- 635 LDRSW 636 // FSTRD is the STR (SIMD&FP) instruction for double precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 637 FSTRD 638 // FSTRS is the STR (SIMD&FP) instruction for single precisions. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset--?lang=en 639 FSTRS 640 // STRD is the STR instruction in 64-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 641 STRD 642 // STRW is the STR instruction in 32-bit mode. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STR--register---Store-Register--register--?lang=en 643 STRW 644 // STRH is the STRH instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRH--register---Store-Register-Halfword--register--?lang=en 645 STRH 646 // STRB is the STRB instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/STRB--register---Store-Register-Byte--register--?lang=en 647 STRB 648 // MOVD moves a double word from register to register, or const to register. 649 MOVD 650 // MOVW moves a word from register to register, or const to register. 651 MOVW 652 // MRS is the MRS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MRS 653 MRS 654 // MSR is the MSR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSR--register- 655 MSR 656 // MSUB is the MSUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 657 MSUB 658 // MSUBW is the MSUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MSUB 659 MSUBW 660 // MUL is the MUL instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 661 MUL 662 // MULW is the MUL instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/MUL 663 MULW 664 // NEG is the NEG instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 665 NEG 666 // NEGW is the NEG instruction, in 32-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/NEG 667 NEGW 668 // ORR is the ORR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 669 ORR 670 // ORRW is the ORR instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ORR--shifted-register- 671 ORRW 672 // RBIT is the RBIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 673 RBIT 674 // RBITW is the RBIT instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/RBIT 675 RBITW 676 // ROR is the ROR instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 677 ROR 678 // RORW is the RORW instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/ROR--register- 679 RORW 680 // SCVTFD is the SCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 681 SCVTFD 682 // SCVTFS is the SCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 683 SCVTFS 684 // SCVTFWD is the SCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 685 SCVTFWD 686 // SCVTFWS is the SCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/SCVTF--scalar--integer- 687 SCVTFWS 688 // SDIV is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 689 SDIV 690 // SDIVW is the SDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SDIV 691 SDIVW 692 // SUB is the SUB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 693 SUB 694 // SUBS is the SUBS instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUBS--shifted-register- 695 SUBS 696 // SUBW is the SUB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SUB--shifted-register- 697 SUBW 698 // SXTB is the SXTB instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 699 SXTB 700 // SXTBW is the SXTB instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTB 701 SXTBW 702 // SXTH is the SXTH instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 703 SXTH 704 // SXTHW is the SXTH instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTH 705 SXTHW 706 // SXTW is the SXTW instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/SXTW 707 SXTW 708 // UCVTFD is the UCVTF instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 709 UCVTFD 710 // UCVTFS is the UCVTF instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 711 UCVTFS 712 // UCVTFWD is the UCVTF instruction, for double precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 713 UCVTFWD 714 // UCVTFWS is the UCVTF instruction, for single precision in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-Floating-point-Instructions/UCVTF--scalar--integer- 715 UCVTFWS 716 // UDIV is the UDIV instruction. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 717 UDIV 718 // UDIVW is the UDIV instruction, in 64-bit mode. https://developer.arm.com/documentation/dui0802/a/A64-General-Instructions/UDIV 719 UDIVW 720 // VBIT is the BIT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/BIT--vector- 721 VBIT 722 // VCNT is the CNT instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/CNT--vector- 723 VCNT 724 // VMOV has different semantics depending on the types of operands: 725 // - LDR(SIMD&FP) if the src is memory and dst is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/LDR--immediate--SIMD-FP---Load-SIMD-FP-Register--immediate-offset-- 726 // - LDR(literal, SIMD&FP) if the src is static const and dst is a vector: https://developer.arm.com/documentation/dui0801/h/A64-Floating-point-Instructions/LDR--literal--SIMD-and-FP- 727 // - STR(SIMD&FP) if the dst is memory and src is a vector: https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/STR--immediate--SIMD-FP---Store-SIMD-FP-register--immediate-offset-- 728 VMOV 729 // UMOV is the UMOV instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMOV--Unsigned-Move-vector-element-to-general-purpose-register-?lang=en 730 UMOV 731 // INSGEN is the INS(general) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--general---Insert-vector-element-from-general-purpose-register-?lang=en 732 INSGEN 733 // INSELEM is the INS(element) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/INS--element---Insert-vector-element-from-another-vector-element-?lang=en 734 INSELEM 735 // UADDLV is the UADDLV(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/UADDLV--vector- 736 UADDLV 737 // VADD is the ADD(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/ADD--vector- 738 VADD 739 // VFADDS is the FADD(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 740 VFADDS 741 // VFADDD is the FADD(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FADD--vector- 742 VFADDD 743 // VSUB is the SUB(vector) instruction. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/SUB--vector- 744 VSUB 745 // VFSUBS is the FSUB(vector) instruction, for single precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 746 VFSUBS 747 // VFSUBD is the FSUB(vector) instruction, for double precision. https://developer.arm.com/documentation/dui0802/a/A64-Advanced-SIMD-Vector-Instructions/FSUB--vector- 748 VFSUBD 749 // SSHL is the SSHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 750 SSHL 751 // SSHLL is the SSHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 752 SSHLL 753 // USHL is the USHL(vector,register) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHL--Signed-Shift-Left--register--?lang=en 754 USHL 755 // USHLL is the USHLL(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 756 USHLL 757 // LD1R is the LD1R instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/LD1R--Load-one-single-element-structure-and-Replicate-to-all-lanes--of-one-register-- 758 LD1R 759 // SMOV32 is the 32-bit variant of SMOV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/SMOV--vector- 760 SMOV32 761 // DUPGEN is the DUP(general) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--general---Duplicate-general-purpose-register-to-vector- 762 DUPGEN 763 // DUPELEM is the DUP(element) instruction. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/DUP--element---Duplicate-vector-element-to-vector-or-scalar- 764 DUPELEM 765 // UMAXP is the UMAXP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/UMAXP--vector- 766 UMAXP 767 // UMINV is the UMINV(vector) instruction. https://developer.arm.com/documentation/100069/0610/A64-SIMD-Vector-Instructions/UMINV--vector- 768 UMINV 769 // CMEQ is the CMEQ(vector, register) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/CMEQ--vector--register- 770 CMEQ 771 // CMEQZERO is the CMEP(zero) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMEQ--zero---Compare-bitwise-Equal-to-zero--vector--?lang=en 772 CMEQZERO 773 // ADDP is the ADDP(scalar) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ADDP--scalar---Add-Pair-of-elements--scalar--?lang=en 774 ADDP 775 // VADDP is the ADDP(vector) instruction. https://developer.arm.com/documentation/dui0801/g/A64-SIMD-Vector-Instructions/ADDP--vector- 776 // Note: prefixed by V to distinguish from the non-vector variant of ADDP(scalar). 777 VADDP 778 // TBL1 is the TBL instruction whose source is one vector. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 779 TBL1 780 // TBL2 is the TBL instruction whose source is two vectors. https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/TBL--Table-vector-Lookup- 781 TBL2 782 // NOT is the NOT(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/NOT--Bitwise-NOT--vector--?lang=en 783 NOT 784 // VAND is the AND(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- 785 // Note: prefixed by V to distinguish from the non-vector variant of AND. 786 VAND 787 // VORR is the ORR(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ORR--vector--register---Bitwise-inclusive-OR--vector--register-- 788 // Note: prefixed by V to distinguish from the non-vector variant of ORR. 789 VORR 790 // BSL https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BSL--Bitwise-Select- 791 BSL 792 // BIC is the BIC(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/BIC--vector--register---Bitwise-bit-Clear--vector--register-- 793 BIC 794 // VFNEG is the FNEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/FNEG--vector---Floating-point-Negate--vector-- 795 // Note: prefixed by V to distinguish from the non-vector variant of FNEG. 796 VFNEG 797 // ADDV is the ADDV instruction https://developer.arm.com/documentation/ddi0596/2020-12/SIMD-FP-Instructions/ADDV--Add-across-Vector- 798 ADDV 799 // ZIP1 is the ZIP1 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ZIP1--Zip-vectors--primary--?lang=en 800 ZIP1 801 // SSHR is the SSHR(immediate,vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SSHR--Signed-Shift-Right--immediate--?lang=en 802 SSHR 803 // EXT is the EXT instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/EXT--Extract-vector-from-pair-of-vectors-?lang=en 804 EXT 805 // CMGT is the CMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGT--register---Compare-signed-Greater-than--vector--?lang=en 806 CMGT 807 // CMHI is the CMHI(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHI--register---Compare-unsigned-Higher--vector--?lang=en 808 CMHI 809 // CMGE is the CMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMGE--register---Compare-signed-Greater-than-or-Equal--vector--?lang=en 810 CMGE 811 // CMHS is the CMHS(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/CMHS--register---Compare-unsigned-Higher-or-Same--vector--?lang=en 812 CMHS 813 // FCMEQ is the FCMEQ(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMEQ--register---Floating-point-Compare-Equal--vector--?lang=en 814 FCMEQ 815 // FCMGT is the FCMGT(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGT--register---Floating-point-Compare-Greater-than--vector--?lang=en 816 FCMGT 817 // FCMGE is the FCMGE(register) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCMGE--register---Floating-point-Compare-Greater-than-or-Equal--vector--?lang=en 818 FCMGE 819 // VFMUL is the FMUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMUL--vector---Floating-point-Multiply--vector--?lang=en 820 // Note: prefixed by V to distinguish from the non-vector variant. 821 VFMUL 822 // VFDIV is the FDIV(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FDIV--vector---Floating-point-Divide--vector--?lang=en 823 // Note: prefixed by V to distinguish from the non-vector variant. 824 VFDIV 825 // VFSQRT is the FSQRT(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FSQRT--vector---Floating-point-Square-Root--vector--?lang=en 826 // Note: prefixed by V to distinguish from the non-vector variant. 827 VFSQRT 828 // VFMIN is the FMIN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMIN--vector---Floating-point-minimum--vector--?lang=en 829 // Note: prefixed by V to distinguish from the non-vector variant. 830 VFMIN 831 // VFMAX is the FMAX(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FMAX--vector---Floating-point-Maximum--vector--?lang=en 832 // Note: prefixed by V to distinguish from the non-vector variant. 833 VFMAX 834 // VFABS is the FABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FABS--vector---Floating-point-Absolute-value--vector--?lang=en 835 // Note: prefixed by V to distinguish from the non-vector variant. 836 VFABS 837 // VFRINTP is the FRINTP(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTP--vector---Floating-point-Round-to-Integral--toward-Plus-infinity--vector--?lang=en 838 // Note: prefixed by V to distinguish from the non-vector variant. 839 VFRINTP 840 // VFRINTM is the FRINTM(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTM--vector---Floating-point-Round-to-Integral--toward-Minus-infinity--vector--?lang=en 841 // Note: prefixed by V to distinguish from the non-vector variant. 842 VFRINTM 843 // VFRINTZ is the FRINTZ(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTZ--vector---Floating-point-Round-to-Integral--toward-Zero--vector--?lang=en 844 // Note: prefixed by V to distinguish from the non-vector variant. 845 VFRINTZ 846 // VFRINTN is the FRINTN(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FRINTN--vector---Floating-point-Round-to-Integral--to-nearest-with-ties-to-even--vector--?lang=en 847 // Note: prefixed by V to distinguish from the non-vector variant. 848 VFRINTN 849 // VMUL is the MUL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/MUL--vector---Multiply--vector--?lang=en 850 // Note: prefixed by V to distinguish from the non-vector variant. 851 VMUL 852 // VNEG is the NEG(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/NEG--vector---Negate--vector--?lang=en 853 // Note: prefixed by V to distinguish from the non-vector variant. 854 VNEG 855 // VABS is the ABS(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/ABS--Absolute-value--vector--?lang=en 856 // Note: prefixed by V to distinguish from the non-vector variant. 857 VABS 858 // VSQADD is the SQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQADD--Signed-saturating-Add-?lang=en 859 // Note: prefixed by V to distinguish from the non-vector variant. 860 VSQADD 861 // VUQADD is the UQADD(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQADD--Unsigned-saturating-Add-?lang=en 862 // Note: prefixed by V to distinguish from the non-vector variant. 863 VUQADD 864 // VSQSUB is the SQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQSUB--Signed-saturating-Subtract-?lang=en 865 // Note: prefixed by V to distinguish from the non-vector variant. 866 VSQSUB 867 // VUQSUB is the UQSUB(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQSUB--Unsigned-saturating-Subtract-?lang=en 868 // Note: prefixed by V to distinguish from the non-vector variant. 869 VUQSUB 870 // SMIN is the SMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMIN--Signed-Minimum--vector--?lang=en 871 SMIN 872 // SMAX is the SMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMAX--Signed-Maximum--vector--?lang=en 873 SMAX 874 // UMIN is the UMIN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMIN--Unsigned-Minimum--vector--?lang=en 875 UMIN 876 // UMAX is the UMAX instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMAX--Unsigned-Maximum--vector--?lang=en 877 UMAX 878 // URHADD is the URHADD instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/URHADD--Unsigned-Rounding-Halving-Add-?lang=en 879 URHADD 880 // REV64 is the REV64 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/REV64--Reverse-elements-in-64-bit-doublewords--vector--?lang=en 881 REV64 882 // XTN is the XTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/XTN--XTN2--Extract-Narrow-?lang=en 883 XTN 884 // VUMLAL is the UMLAL(vector) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UMLAL--UMLAL2--vector---Unsigned-Multiply-Add-Long--vector--?lang=en 885 // Note: prefixed by V to distinguish from the non-vector variant. 886 VUMLAL 887 // SHLL is the SHLL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SHLL--SHLL2--Shift-Left-Long--by-element-size--?lang=en 888 SHLL 889 // SADDLP is the SADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SADDLP--Signed-Add-Long-Pairwise-?lang=en 890 SADDLP 891 // UADDLP is the UADDLP instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UADDLP--Unsigned-Add-Long-Pairwise-?lang=en 892 UADDLP 893 // SSHLL2 is the SSHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 894 SSHLL2 895 // USHLL2 is the USHLL2(vector,immediate) instruction. https://developer.arm.com/documentation/dui0801/h/A64-SIMD-Vector-Instructions/SSHLL--SSHLL2--vector- 896 USHLL2 897 // SQRDMULH is the SQRDMULH(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQRDMULH--vector---Signed-saturating-Rounding-Doubling-Multiply-returning-High-half-?lang=en 898 SQRDMULH 899 // SMULL is the SMULL(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 900 SMULL 901 // SMULL2 is the SMULL2(vector) instruction. https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SMULL--SMULL2--vector---Signed-Multiply-Long--vector--?lang=en 902 SMULL2 903 // UMULL is the UMULL instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 904 UMULL 905 // UMULL2 is the UMULL2 instruction. https://developer.arm.com/documentation/ddi0596/2021-12/Index-by-Encoding/Data-Processing----Scalar-Floating-Point-and-Advanced-SIMD?lang=en 906 UMULL2 907 // VFCVTZS is the FCVTZS(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZS--vector--integer---Floating-point-Convert-to-Signed-integer--rounding-toward-Zero--vector--?lang=en 908 // Note: prefixed by V to distinguish from the non-vector variant. 909 VFCVTZS 910 // VFCVTZU is the FCVTZU(vector,integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTZU--vector--integer---Floating-point-Convert-to-Unsigned-integer--rounding-toward-Zero--vector--?lang=en 911 // Note: prefixed by V to distinguish from the non-vector variant. 912 VFCVTZU 913 // SQXTN is the SQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 914 SQXTN 915 // UQXTN is the UQXTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UQXTN--UQXTN2--Unsigned-saturating-extract-Narrow-?lang=en 916 UQXTN 917 // SQXTN2 is the SQXTN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTN--SQXTN2--Signed-saturating-extract-Narrow-?lang=en 918 SQXTN2 919 // SQXTUN is the SQXTUN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 920 SQXTUN 921 // SQXTUN2 is the SQXTUN2 instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SQXTUN--SQXTUN2--Signed-saturating-extract-Unsigned-Narrow-?lang=en 922 SQXTUN2 923 // VSCVTF is the SCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/SCVTF--vector--integer---Signed-integer-Convert-to-Floating-point--vector--?lang=en 924 // Note: prefixed by V to distinguish from the non-vector variant. 925 VSCVTF 926 // VUCVTF is the UCVTF(vector, integer) instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/UCVTF--vector--integer---Unsigned-integer-Convert-to-Floating-point--vector--?lang=en 927 // Note: prefixed by V to distinguish from the non-vector variant. 928 VUCVTF 929 // FCVTL is the FCVTL instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTL--FCVTL2--Floating-point-Convert-to-higher-precision-Long--vector--?lang=en 930 FCVTL 931 // FCVTN is the FCVTN instruction https://developer.arm.com/documentation/ddi0596/2021-12/SIMD-FP-Instructions/FCVTN--FCVTN2--Floating-point-Convert-to-lower-precision-Narrow--vector--?lang=en 932 FCVTN 933 934 // UDF is the UDF instruction https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/UDF--Permanently-Undefined-?lang=en 935 UDF 936 937 // instructionEnd is always placed at the bottom of this iota definition to be used in the test. 938 instructionEnd 939 ) 940 941 // VectorArrangement is the arrangement of data within a vector register. 942 type VectorArrangement byte 943 944 const ( 945 // VectorArrangementNone is an arrangement indicating no data is stored. 946 VectorArrangementNone VectorArrangement = iota 947 // VectorArrangement8B is an arrangement of 8 bytes (64-bit vector) 948 VectorArrangement8B 949 // VectorArrangement16B is an arrangement of 16 bytes (128-bit vector) 950 VectorArrangement16B 951 // VectorArrangement4H is an arrangement of 4 half precisions (64-bit vector) 952 VectorArrangement4H 953 // VectorArrangement8H is an arrangement of 8 half precisions (128-bit vector) 954 VectorArrangement8H 955 // VectorArrangement2S is an arrangement of 2 single precisions (64-bit vector) 956 VectorArrangement2S 957 // VectorArrangement4S is an arrangement of 4 single precisions (128-bit vector) 958 VectorArrangement4S 959 // VectorArrangement1D is an arrangement of 1 double precision (64-bit vector) 960 VectorArrangement1D 961 // VectorArrangement2D is an arrangement of 2 double precisions (128-bit vector) 962 VectorArrangement2D 963 964 // Assign each vector size specifier to a vector arrangement ID. 965 // Instructions can only have an arrangement or a size specifier, but not both, so it 966 // simplifies the internal representation of vector instructions by being able to 967 // store either into the same field. 968 969 // VectorArrangementB is a size specifier of byte 970 VectorArrangementB 971 // VectorArrangementH is a size specifier of word (16-bit) 972 VectorArrangementH 973 // VectorArrangementS is a size specifier of double word (32-bit) 974 VectorArrangementS 975 // VectorArrangementD is a size specifier of quad word (64-bit) 976 VectorArrangementD 977 // VectorArrangementQ is a size specifier of the entire vector (128-bit) 978 VectorArrangementQ 979 ) 980 981 func (v VectorArrangement) String() (ret string) { 982 switch v { 983 case VectorArrangement8B: 984 ret = "8B" 985 case VectorArrangement16B: 986 ret = "16B" 987 case VectorArrangement4H: 988 ret = "4H" 989 case VectorArrangement8H: 990 ret = "8H" 991 case VectorArrangement2S: 992 ret = "2S" 993 case VectorArrangement4S: 994 ret = "4S" 995 case VectorArrangement1D: 996 ret = "1D" 997 case VectorArrangement2D: 998 ret = "2D" 999 case VectorArrangementB: 1000 ret = "B" 1001 case VectorArrangementH: 1002 ret = "H" 1003 case VectorArrangementS: 1004 ret = "S" 1005 case VectorArrangementD: 1006 ret = "D" 1007 case VectorArrangementQ: 1008 ret = "Q" 1009 case VectorArrangementNone: 1010 ret = "none" 1011 default: 1012 panic(v) 1013 } 1014 return 1015 } 1016 1017 // VectorIndex is the index of an element of a vector register 1018 type VectorIndex byte 1019 1020 // VectorIndexNone indicates no vector index specified. 1021 const VectorIndexNone = ^VectorIndex(0) 1022 1023 // InstructionName returns the name of the given instruction 1024 func InstructionName(i asm.Instruction) string { 1025 switch i { 1026 case NOP: 1027 return "NOP" 1028 case RET: 1029 return "RET" 1030 case ADD: 1031 return "ADD" 1032 case ADDS: 1033 return "ADDS" 1034 case ADDW: 1035 return "ADDW" 1036 case ADR: 1037 return "ADR" 1038 case AND: 1039 return "AND" 1040 case ANDIMM32: 1041 return "ANDIMM32" 1042 case ANDIMM64: 1043 return "ANDIMM64" 1044 case ANDW: 1045 return "ANDW" 1046 case ASR: 1047 return "ASR" 1048 case ASRW: 1049 return "ASRW" 1050 case B: 1051 return "B" 1052 case BCONDEQ: 1053 return "BCONDEQ" 1054 case BCONDGE: 1055 return "BCONDGE" 1056 case BCONDGT: 1057 return "BCONDGT" 1058 case BCONDHI: 1059 return "BCONDHI" 1060 case BCONDHS: 1061 return "BCONDHS" 1062 case BCONDLE: 1063 return "BCONDLE" 1064 case BCONDLO: 1065 return "BCONDLO" 1066 case BCONDLS: 1067 return "BCONDLS" 1068 case BCONDLT: 1069 return "BCONDLT" 1070 case BCONDMI: 1071 return "BCONDMI" 1072 case BCONDPL: 1073 return "BCONDPL" 1074 case BCONDNE: 1075 return "BCONDNE" 1076 case BCONDVS: 1077 return "BCONDVS" 1078 case BCONDVC: 1079 return "BCONDVC" 1080 case CLZ: 1081 return "CLZ" 1082 case CLZW: 1083 return "CLZW" 1084 case CMP: 1085 return "CMP" 1086 case CMPW: 1087 return "CMPW" 1088 case CSET: 1089 return "CSET" 1090 case EOR: 1091 return "EOR" 1092 case EORW: 1093 return "EORW" 1094 case FABSD: 1095 return "FABSD" 1096 case FABSS: 1097 return "FABSS" 1098 case FADDD: 1099 return "FADDD" 1100 case FADDS: 1101 return "FADDS" 1102 case FCMPD: 1103 return "FCMPD" 1104 case FCMPS: 1105 return "FCMPS" 1106 case FCVTDS: 1107 return "FCVTDS" 1108 case FCVTSD: 1109 return "FCVTSD" 1110 case FCVTZSD: 1111 return "FCVTZSD" 1112 case FCVTZSDW: 1113 return "FCVTZSDW" 1114 case FCVTZSS: 1115 return "FCVTZSS" 1116 case FCVTZSSW: 1117 return "FCVTZSSW" 1118 case FCVTZUD: 1119 return "FCVTZUD" 1120 case FCVTZUDW: 1121 return "FCVTZUDW" 1122 case FCVTZUS: 1123 return "FCVTZUS" 1124 case FCVTZUSW: 1125 return "FCVTZUSW" 1126 case FDIVD: 1127 return "FDIVD" 1128 case FDIVS: 1129 return "FDIVS" 1130 case FMAXD: 1131 return "FMAXD" 1132 case FMAXS: 1133 return "FMAXS" 1134 case FMIND: 1135 return "FMIND" 1136 case FMINS: 1137 return "FMINS" 1138 case FMOVD: 1139 return "FMOVD" 1140 case FMOVS: 1141 return "FMOVS" 1142 case FMULD: 1143 return "FMULD" 1144 case FMULS: 1145 return "FMULS" 1146 case FNEGD: 1147 return "FNEGD" 1148 case FNEGS: 1149 return "FNEGS" 1150 case FRINTMD: 1151 return "FRINTMD" 1152 case FRINTMS: 1153 return "FRINTMS" 1154 case FRINTND: 1155 return "FRINTND" 1156 case FRINTNS: 1157 return "FRINTNS" 1158 case FRINTPD: 1159 return "FRINTPD" 1160 case FRINTPS: 1161 return "FRINTPS" 1162 case FRINTZD: 1163 return "FRINTZD" 1164 case FRINTZS: 1165 return "FRINTZS" 1166 case FSQRTD: 1167 return "FSQRTD" 1168 case FSQRTS: 1169 return "FSQRTS" 1170 case FSUBD: 1171 return "FSUBD" 1172 case FSUBS: 1173 return "FSUBS" 1174 case LSL: 1175 return "LSL" 1176 case LSLW: 1177 return "LSLW" 1178 case LSR: 1179 return "LSR" 1180 case LSRW: 1181 return "LSRW" 1182 case LDRSBD: 1183 return "LDRSBD" 1184 case LDRSBW: 1185 return "LDRSBW" 1186 case LDRB: 1187 return "LDRB" 1188 case MOVD: 1189 return "MOVD" 1190 case LDRSHD: 1191 return "LDRSHD" 1192 case LDRSHW: 1193 return "LDRSHW" 1194 case LDRH: 1195 return "LDRH" 1196 case LDRSW: 1197 return "LDRSW" 1198 case STRD: 1199 return "STRD" 1200 case STRW: 1201 return "STRW" 1202 case STRH: 1203 return "STRH" 1204 case STRB: 1205 return "STRB" 1206 case MOVW: 1207 return "MOVW" 1208 case MRS: 1209 return "MRS" 1210 case MSR: 1211 return "MSR" 1212 case MSUB: 1213 return "MSUB" 1214 case MSUBW: 1215 return "MSUBW" 1216 case MUL: 1217 return "MUL" 1218 case MULW: 1219 return "MULW" 1220 case NEG: 1221 return "NEG" 1222 case NEGW: 1223 return "NEGW" 1224 case ORR: 1225 return "ORR" 1226 case ORRW: 1227 return "ORRW" 1228 case RBIT: 1229 return "RBIT" 1230 case RBITW: 1231 return "RBITW" 1232 case ROR: 1233 return "ROR" 1234 case RORW: 1235 return "RORW" 1236 case SCVTFD: 1237 return "SCVTFD" 1238 case SCVTFS: 1239 return "SCVTFS" 1240 case SCVTFWD: 1241 return "SCVTFWD" 1242 case SCVTFWS: 1243 return "SCVTFWS" 1244 case SDIV: 1245 return "SDIV" 1246 case SDIVW: 1247 return "SDIVW" 1248 case SUB: 1249 return "SUB" 1250 case SUBS: 1251 return "SUBS" 1252 case SUBW: 1253 return "SUBW" 1254 case SXTB: 1255 return "SXTB" 1256 case SXTBW: 1257 return "SXTBW" 1258 case SXTH: 1259 return "SXTH" 1260 case SXTHW: 1261 return "SXTHW" 1262 case SXTW: 1263 return "SXTW" 1264 case UCVTFD: 1265 return "UCVTFD" 1266 case UCVTFS: 1267 return "UCVTFS" 1268 case UCVTFWD: 1269 return "UCVTFWD" 1270 case UCVTFWS: 1271 return "UCVTFWS" 1272 case UDIV: 1273 return "UDIV" 1274 case UDIVW: 1275 return "UDIVW" 1276 case VBIT: 1277 return "VBIT" 1278 case VCNT: 1279 return "VCNT" 1280 case UADDLV: 1281 return "UADDLV" 1282 case VMOV: 1283 return "VMOV" 1284 case INSELEM: 1285 return "INSELEM" 1286 case UMOV: 1287 return "UMOV" 1288 case INSGEN: 1289 return "INSGEN" 1290 case VADD: 1291 return "VADD" 1292 case VFADDS: 1293 return "VFADDS" 1294 case VFADDD: 1295 return "VFADDD" 1296 case VSUB: 1297 return "VSUB" 1298 case VFSUBS: 1299 return "VFSUBS" 1300 case VFSUBD: 1301 return "VFSUBD" 1302 case SSHL: 1303 return "SSHL" 1304 case USHL: 1305 return "USHL" 1306 case SSHLL: 1307 return "SSHLL" 1308 case USHLL: 1309 return "USHLL" 1310 case LD1R: 1311 return "LD1R" 1312 case SMOV32: 1313 return "SMOV32" 1314 case DUPGEN: 1315 return "DUPGEN" 1316 case DUPELEM: 1317 return "DUPELEM" 1318 case UMAXP: 1319 return "UMAXP" 1320 case UMINV: 1321 return "UMINV" 1322 case CMEQ: 1323 return "CMEQ" 1324 case ADDP: 1325 return "ADDP" 1326 case VADDP: 1327 return "VADDP" 1328 case TBL1: 1329 return "TBL1" 1330 case TBL2: 1331 return "TBL2" 1332 case NOT: 1333 return "NOT" 1334 case VAND: 1335 return "VAND" 1336 case VORR: 1337 return "VORR" 1338 case BSL: 1339 return "BSL" 1340 case BIC: 1341 return "BIC" 1342 case VFNEG: 1343 return "VFNEG" 1344 case ADDV: 1345 return "ADDV" 1346 case CMEQZERO: 1347 return "CMEQZERO" 1348 case ZIP1: 1349 return "ZIP1" 1350 case SSHR: 1351 return "SSHR" 1352 case EXT: 1353 return "EXT" 1354 case CMGT: 1355 return "CMGT" 1356 case CMHI: 1357 return "CMHI" 1358 case CMGE: 1359 return "CMGE" 1360 case CMHS: 1361 return "CMHS" 1362 case FCMEQ: 1363 return "FCMEQ" 1364 case FCMGT: 1365 return "FCMGT" 1366 case FCMGE: 1367 return "FCMGE" 1368 case VFMUL: 1369 return "VFMUL" 1370 case VFDIV: 1371 return "VFDIV" 1372 case VFSQRT: 1373 return "VFSQRT" 1374 case VFMIN: 1375 return "VFMIN" 1376 case VFMAX: 1377 return "VFMAX" 1378 case VFABS: 1379 return "VFABS" 1380 case VFRINTP: 1381 return "VFRINTP" 1382 case VFRINTM: 1383 return "VFRINTM" 1384 case VFRINTZ: 1385 return "VFRINTZ" 1386 case VFRINTN: 1387 return "VFRINTN" 1388 case VMUL: 1389 return "VMUL" 1390 case VNEG: 1391 return "VNEG" 1392 case VABS: 1393 return "VABS" 1394 case VSQADD: 1395 return "VSQADD" 1396 case VUQADD: 1397 return "VUQADD" 1398 case SMIN: 1399 return "SMIN" 1400 case SMAX: 1401 return "SMAX" 1402 case UMIN: 1403 return "UMIN" 1404 case UMAX: 1405 return "UMAX" 1406 case URHADD: 1407 return "URHADD" 1408 case VSQSUB: 1409 return "VSQSUB" 1410 case VUQSUB: 1411 return "VUQSUB" 1412 case REV64: 1413 return "REV64" 1414 case XTN: 1415 return "XTN" 1416 case VUMLAL: 1417 return "VUMLAL" 1418 case SHLL: 1419 return "SHLL" 1420 case SSHLL2: 1421 return "SSHLL2" 1422 case USHLL2: 1423 return "USHLL2" 1424 case SQRDMULH: 1425 return "SQRDMULH" 1426 case SADDLP: 1427 return "SADDLP" 1428 case UADDLP: 1429 return "UADDLP" 1430 case SMULL: 1431 return "SMULL" 1432 case SMULL2: 1433 return "SMULL2" 1434 case UMULL: 1435 return "UMULL" 1436 case UMULL2: 1437 return "UMULL2" 1438 case VFCVTZS: 1439 return "VFCVTZS" 1440 case VFCVTZU: 1441 return "VFCVTZU" 1442 case SQXTN: 1443 return "SQXTN" 1444 case UQXTN: 1445 return "UQXTN" 1446 case SQXTN2: 1447 return "SQXTN2" 1448 case SQXTUN: 1449 return "SQXTUN" 1450 case SQXTUN2: 1451 return "SQXTUN2" 1452 case VSCVTF: 1453 return "VSCVTF" 1454 case VUCVTF: 1455 return "VUCVTF" 1456 case FCVTL: 1457 return "FCVTL" 1458 case FCVTN: 1459 return "FCVTN" 1460 case FSTRD: 1461 return "FSTRD" 1462 case FSTRS: 1463 return "FSTRS" 1464 case LDRD: 1465 return "LDRD" 1466 case LDRW: 1467 return "LDRW" 1468 case FLDRD: 1469 return "FLDRD" 1470 case FLDRS: 1471 return "FLDRS" 1472 case UDF: 1473 return "UDF" 1474 } 1475 panic(fmt.Errorf("unknown instruction %d", i)) 1476 }