github.com/bananabytelabs/wazero@v0.0.0-20240105073314-54b22a776da8/internal/asm/arm64/impl_5_test.go (about) 1 package arm64 2 3 import ( 4 "testing" 5 6 "github.com/bananabytelabs/wazero/internal/asm" 7 "github.com/bananabytelabs/wazero/internal/testing/require" 8 ) 9 10 func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) { 11 t.Run("error", func(t *testing.T) { 12 tests := []struct { 13 n *nodeImpl 14 expErr string 15 }{ 16 { 17 n: &nodeImpl{instruction: ADR, types: operandTypesRegisterToMemory}, 18 expErr: "ADR is unsupported for RegisterToMemory type", 19 }, 20 } 21 22 code := asm.CodeSegment{} 23 defer func() { require.NoError(t, code.Unmap()) }() 24 25 for _, tt := range tests { 26 tc := tt 27 a := NewAssembler(asm.NilRegister) 28 buf := code.NextCodeSection() 29 err := a.encodeRegisterToMemory(buf, tc.n) 30 require.EqualError(t, err, tc.expErr) 31 } 32 }) 33 34 tests := []struct { 35 name string 36 n *nodeImpl 37 exp []byte 38 }{ 39 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xf8}}, 40 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xf9}}, 41 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xf8}}, 42 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xf8}}, 43 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xf8}}, 44 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xf8}}, 45 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xf8}}, 46 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, 47 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xf8}}, 48 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xf9}}, 49 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, 50 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xf8}}, 51 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, 52 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xf8}}, 53 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xf9}}, 54 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, 55 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xf8}}, 56 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xf9}}, 57 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xf9}}, 58 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xf9}}, 59 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, 60 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, 61 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, 62 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 63 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 64 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 65 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 66 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 67 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 68 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 69 {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, 70 {name: "STRD/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xf8}}, 71 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xf8}}, 72 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xf9}}, 73 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xf8}}, 74 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xf8}}, 75 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xf8}}, 76 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xf8}}, 77 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xf8}}, 78 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, 79 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xf8}}, 80 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xf9}}, 81 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, 82 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xf8}}, 83 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, 84 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xf8}}, 85 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xf9}}, 86 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, 87 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xf8}}, 88 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xf9}}, 89 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xf9}}, 90 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xf9}}, 91 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, 92 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, 93 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, 94 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 95 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 96 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 97 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 98 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 99 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 100 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 101 {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, 102 {name: "STRD/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xf8}}, 103 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xf8}}, 104 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xf9}}, 105 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xf8}}, 106 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xf8}}, 107 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xf8}}, 108 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xf8}}, 109 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xf8}}, 110 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, 111 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xf8}}, 112 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xf9}}, 113 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, 114 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xf8}}, 115 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, 116 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xf8}}, 117 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xf9}}, 118 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, 119 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xf8}}, 120 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xf9}}, 121 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xf9}}, 122 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xf9}}, 123 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, 124 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, 125 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, 126 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 127 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 128 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 129 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 130 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 131 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 132 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 133 {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, 134 {name: "STRD/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xf8}}, 135 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xf8}}, 136 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xf9}}, 137 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xf8}}, 138 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xf8}}, 139 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xf8}}, 140 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xf8}}, 141 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xf8}}, 142 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, 143 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xf8}}, 144 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xf9}}, 145 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, 146 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xf8}}, 147 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, 148 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xf8}}, 149 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xf9}}, 150 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, 151 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xf8}}, 152 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xf9}}, 153 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xf9}}, 154 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xf9}}, 155 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, 156 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, 157 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, 158 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 159 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 160 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 161 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 162 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 163 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 164 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 165 {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, 166 {name: "STRD/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xf8}}, 167 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xb8}}, 168 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xb9}}, 169 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xb8}}, 170 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xb8}}, 171 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xb8}}, 172 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xb9}}, 173 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xb8}}, 174 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, 175 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xb8}}, 176 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xb9}}, 177 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, 178 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xb8}}, 179 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, 180 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xb8}}, 181 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xb9}}, 182 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, 183 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xb8}}, 184 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xb9}}, 185 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xb9}}, 186 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, 187 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, 188 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, 189 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, 190 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 191 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 192 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 193 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 194 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 195 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 196 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 197 {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, 198 {name: "STRW/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xb8}}, 199 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xb8}}, 200 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xb9}}, 201 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xb8}}, 202 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xb8}}, 203 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xb8}}, 204 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xb9}}, 205 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xb8}}, 206 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, 207 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xb8}}, 208 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xb9}}, 209 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, 210 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xb8}}, 211 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, 212 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xb8}}, 213 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xb9}}, 214 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, 215 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xb8}}, 216 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xb9}}, 217 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xb9}}, 218 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, 219 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, 220 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, 221 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, 222 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 223 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 224 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 225 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 226 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 227 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 228 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 229 {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, 230 {name: "STRW/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xb8}}, 231 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xb8}}, 232 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xb9}}, 233 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xb8}}, 234 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xb8}}, 235 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xb8}}, 236 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xb9}}, 237 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xb8}}, 238 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, 239 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xb8}}, 240 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xb9}}, 241 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, 242 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xb8}}, 243 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, 244 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xb8}}, 245 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xb9}}, 246 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, 247 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xb8}}, 248 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xb9}}, 249 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xb9}}, 250 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, 251 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, 252 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, 253 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, 254 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 255 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 256 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 257 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 258 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 259 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 260 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 261 {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, 262 {name: "STRW/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xb8}}, 263 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xb8}}, 264 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xb9}}, 265 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xb8}}, 266 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xb8}}, 267 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xb8}}, 268 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xb9}}, 269 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xb8}}, 270 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, 271 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xb8}}, 272 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xb9}}, 273 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, 274 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xb8}}, 275 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, 276 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xb8}}, 277 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xb9}}, 278 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, 279 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xb8}}, 280 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xb9}}, 281 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xb9}}, 282 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, 283 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, 284 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, 285 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, 286 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 287 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 288 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 289 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 290 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 291 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 292 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 293 {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, 294 {name: "STRW/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xb8}}, 295 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x78}}, 296 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x79}}, 297 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0x78}}, 298 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x4, 0x0, 0x79}}, 299 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x78}}, 300 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x8, 0x0, 0x79}}, 301 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x78}}, 302 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, 303 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x78}}, 304 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x20, 0x0, 0x79}}, 305 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, 306 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0x78}}, 307 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, 308 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x78}}, 309 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0xa0, 0x0, 0x79}}, 310 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, 311 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0x78}}, 312 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x20, 0x79}}, 313 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, 314 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, 315 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, 316 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, 317 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, 318 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 319 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 320 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 321 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 322 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 323 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 324 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 325 {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, 326 {name: "STRH/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x78}}, 327 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x78}}, 328 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x79}}, 329 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0x78}}, 330 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x7, 0x0, 0x79}}, 331 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x78}}, 332 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0xb, 0x0, 0x79}}, 333 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x78}}, 334 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, 335 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x78}}, 336 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x23, 0x0, 0x79}}, 337 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, 338 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0x78}}, 339 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, 340 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x78}}, 341 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0xa3, 0x0, 0x79}}, 342 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, 343 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0x78}}, 344 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x20, 0x79}}, 345 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, 346 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, 347 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, 348 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, 349 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, 350 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 351 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 352 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 353 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 354 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 355 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 356 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 357 {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, 358 {name: "STRH/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x78}}, 359 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x78}}, 360 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x79}}, 361 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0x78}}, 362 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x4, 0x0, 0x79}}, 363 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x78}}, 364 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x8, 0x0, 0x79}}, 365 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x78}}, 366 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, 367 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x78}}, 368 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x20, 0x0, 0x79}}, 369 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, 370 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0x78}}, 371 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, 372 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x78}}, 373 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0xa0, 0x0, 0x79}}, 374 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, 375 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0x78}}, 376 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x20, 0x79}}, 377 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, 378 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, 379 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, 380 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, 381 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, 382 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 383 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 384 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 385 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 386 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 387 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 388 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 389 {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, 390 {name: "STRH/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x78}}, 391 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x78}}, 392 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x79}}, 393 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0x78}}, 394 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x7, 0x0, 0x79}}, 395 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x78}}, 396 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0xb, 0x0, 0x79}}, 397 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x78}}, 398 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, 399 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x78}}, 400 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x23, 0x0, 0x79}}, 401 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, 402 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0x78}}, 403 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, 404 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x78}}, 405 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0xa3, 0x0, 0x79}}, 406 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, 407 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0x78}}, 408 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x20, 0x79}}, 409 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, 410 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, 411 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, 412 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, 413 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, 414 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 415 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 416 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 417 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 418 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 419 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 420 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 421 {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, 422 {name: "STRH/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x78}}, 423 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x38}}, 424 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x39}}, 425 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x4, 0x0, 0x39}}, 426 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x8, 0x0, 0x39}}, 427 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x38}}, 428 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x10, 0x0, 0x39}}, 429 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x38}}, 430 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, 431 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x38}}, 432 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x40, 0x0, 0x39}}, 433 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, 434 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x44, 0x0, 0x39}}, 435 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, 436 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x38}}, 437 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x40, 0x1, 0x39}}, 438 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, 439 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xfc, 0x3, 0x39}}, 440 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, 441 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, 442 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, 443 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, 444 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, 445 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, 446 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 447 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 448 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 449 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 450 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 451 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 452 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 453 {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, 454 {name: "STRB/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x38}}, 455 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x38}}, 456 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x39}}, 457 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x7, 0x0, 0x39}}, 458 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0xb, 0x0, 0x39}}, 459 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x38}}, 460 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x13, 0x0, 0x39}}, 461 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x38}}, 462 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, 463 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x38}}, 464 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x43, 0x0, 0x39}}, 465 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, 466 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x47, 0x0, 0x39}}, 467 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, 468 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x38}}, 469 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x43, 0x1, 0x39}}, 470 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, 471 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xff, 0x3, 0x39}}, 472 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, 473 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, 474 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, 475 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, 476 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, 477 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, 478 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 479 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 480 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 481 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 482 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 483 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 484 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 485 {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, 486 {name: "STRB/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x38}}, 487 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x38}}, 488 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x39}}, 489 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x4, 0x0, 0x39}}, 490 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x8, 0x0, 0x39}}, 491 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x38}}, 492 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x10, 0x0, 0x39}}, 493 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x38}}, 494 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, 495 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x38}}, 496 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x40, 0x0, 0x39}}, 497 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, 498 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x44, 0x0, 0x39}}, 499 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, 500 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x38}}, 501 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x40, 0x1, 0x39}}, 502 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, 503 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xfc, 0x3, 0x39}}, 504 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, 505 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, 506 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, 507 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, 508 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, 509 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, 510 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 511 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 512 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 513 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 514 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 515 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 516 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 517 {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, 518 {name: "STRB/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x38}}, 519 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x38}}, 520 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x39}}, 521 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x39}}, 522 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0x39}}, 523 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x38}}, 524 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0x39}}, 525 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x38}}, 526 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, 527 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x38}}, 528 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0x39}}, 529 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, 530 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0x39}}, 531 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, 532 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x38}}, 533 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x43, 0x1, 0x39}}, 534 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, 535 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xff, 0x3, 0x39}}, 536 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, 537 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, 538 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, 539 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, 540 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, 541 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, 542 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 543 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 544 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 545 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 546 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 547 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 548 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 549 {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, 550 {name: "STRB/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x38}}, 551 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xfc}}, 552 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xfd}}, 553 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xfc}}, 554 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xfc}}, 555 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xfc}}, 556 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xfc}}, 557 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xfc}}, 558 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, 559 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xfc}}, 560 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xfd}}, 561 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, 562 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xfc}}, 563 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, 564 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xfc}}, 565 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xfd}}, 566 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, 567 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xfc}}, 568 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xfd}}, 569 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xfd}}, 570 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xfd}}, 571 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, 572 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, 573 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, 574 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 575 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 576 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 577 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 578 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 579 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 580 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 581 {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, 582 {name: "FSTRD/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xfc}}, 583 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xfc}}, 584 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xfd}}, 585 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xfc}}, 586 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xfc}}, 587 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xfc}}, 588 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xfc}}, 589 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xfc}}, 590 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, 591 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xfc}}, 592 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xfd}}, 593 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, 594 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xfc}}, 595 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, 596 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xfc}}, 597 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xfd}}, 598 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, 599 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xfc}}, 600 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xfd}}, 601 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xfd}}, 602 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xfd}}, 603 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, 604 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, 605 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, 606 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 607 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 608 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 609 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 610 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 611 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 612 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 613 {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, 614 {name: "FSTRD/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xfc}}, 615 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xfc}}, 616 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xfd}}, 617 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xfc}}, 618 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xfc}}, 619 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xfc}}, 620 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xfc}}, 621 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xfc}}, 622 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, 623 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xfc}}, 624 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xfd}}, 625 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, 626 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xfc}}, 627 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, 628 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xfc}}, 629 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xfd}}, 630 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, 631 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xfc}}, 632 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xfd}}, 633 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xfd}}, 634 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xfd}}, 635 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, 636 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, 637 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, 638 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 639 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 640 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 641 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 642 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 643 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 644 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 645 {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, 646 {name: "FSTRD/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xfc}}, 647 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xfc}}, 648 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xfd}}, 649 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xfc}}, 650 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xfc}}, 651 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xfc}}, 652 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xfc}}, 653 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xfc}}, 654 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, 655 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xfc}}, 656 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xfd}}, 657 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, 658 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xfc}}, 659 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, 660 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xfc}}, 661 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xfd}}, 662 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, 663 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xfc}}, 664 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xfd}}, 665 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xfd}}, 666 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xfd}}, 667 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, 668 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, 669 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, 670 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 671 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 672 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 673 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 674 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 675 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 676 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 677 {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, 678 {name: "FSTRD/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xfc}}, 679 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xbc}}, 680 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xbd}}, 681 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xbc}}, 682 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xbc}}, 683 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xbc}}, 684 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xbd}}, 685 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xbc}}, 686 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, 687 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xbc}}, 688 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xbd}}, 689 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, 690 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xbc}}, 691 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, 692 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xbc}}, 693 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xbd}}, 694 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, 695 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xbc}}, 696 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xbd}}, 697 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xbd}}, 698 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, 699 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, 700 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, 701 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, 702 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 703 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 704 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 705 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 706 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 707 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 708 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 709 {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, 710 {name: "FSTRS/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xbc}}, 711 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xbc}}, 712 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xbd}}, 713 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xbc}}, 714 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xbc}}, 715 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xbc}}, 716 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xbd}}, 717 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xbc}}, 718 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, 719 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xbc}}, 720 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xbd}}, 721 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, 722 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xbc}}, 723 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, 724 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xbc}}, 725 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xbd}}, 726 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, 727 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xbc}}, 728 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xbd}}, 729 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xbd}}, 730 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, 731 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, 732 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, 733 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, 734 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 735 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 736 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 737 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 738 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 739 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 740 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 741 {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, 742 {name: "FSTRS/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xbc}}, 743 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xbc}}, 744 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xbd}}, 745 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xbc}}, 746 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xbc}}, 747 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xbc}}, 748 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xbd}}, 749 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xbc}}, 750 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, 751 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xbc}}, 752 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xbd}}, 753 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, 754 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xbc}}, 755 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, 756 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xbc}}, 757 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xbd}}, 758 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, 759 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xbc}}, 760 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xbd}}, 761 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xbd}}, 762 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, 763 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, 764 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, 765 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, 766 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 767 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 768 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 769 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 770 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 771 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 772 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 773 {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, 774 {name: "FSTRS/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xbc}}, 775 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xbc}}, 776 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xbd}}, 777 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xbc}}, 778 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xbc}}, 779 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xbc}}, 780 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xbd}}, 781 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xbc}}, 782 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, 783 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xbc}}, 784 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xbd}}, 785 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, 786 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xbc}}, 787 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, 788 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xbc}}, 789 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xbd}}, 790 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, 791 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xbc}}, 792 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xbd}}, 793 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xbd}}, 794 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, 795 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, 796 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, 797 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, 798 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 799 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 800 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 801 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 802 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 803 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 804 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 805 {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, 806 {name: "FSTRS/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xbc}}, 807 } 808 809 for _, tc := range tests { 810 t.Run(tc.name, func(t *testing.T) { 811 code := asm.CodeSegment{} 812 defer func() { require.NoError(t, code.Unmap()) }() 813 814 a := NewAssembler(RegR27) 815 tc.n.types = operandTypesRegisterToMemory 816 817 buf := code.NextCodeSection() 818 err := a.encodeRegisterToMemory(buf, tc.n) 819 require.NoError(t, err) 820 821 err = a.Assemble(buf) 822 require.NoError(t, err) 823 824 actual := buf.Bytes() 825 require.Equal(t, tc.exp, actual) 826 }) 827 } 828 }