github.com/bananabytelabs/wazero@v0.0.0-20240105073314-54b22a776da8/internal/engine/wazevo/backend/isa/arm64/instr_encoding_test.go (about) 1 package arm64 2 3 import ( 4 "encoding/binary" 5 "encoding/hex" 6 "fmt" 7 "math" 8 "testing" 9 10 "github.com/bananabytelabs/wazero/internal/engine/wazevo/backend/regalloc" 11 "github.com/bananabytelabs/wazero/internal/engine/wazevo/ssa" 12 "github.com/bananabytelabs/wazero/internal/testing/require" 13 ) 14 15 func Test_dummy(t *testing.T) { 16 require.Equal(t, dummyInstruction, encodeUnconditionalBranch(false, 0)) 17 } 18 19 func TestInstruction_encode(t *testing.T) { 20 dummyLabel := label(1) 21 for _, tc := range []struct { 22 setup func(*instruction) 23 want string 24 }{ 25 {want: "3f441bd5", setup: func(i *instruction) { i.asMovToFPSR(xzrVReg) }}, 26 {want: "21441bd5", setup: func(i *instruction) { i.asMovToFPSR(x1VReg) }}, 27 {want: "21443bd5", setup: func(i *instruction) { i.asMovFromFPSR(x1VReg) }}, 28 {want: "2f08417a", setup: func(i *instruction) { i.asCCmpImm(operandNR(x1VReg), 1, eq, 0b1111, false) }}, 29 {want: "201841fa", setup: func(i *instruction) { i.asCCmpImm(operandNR(x1VReg), 1, ne, 0, true) }}, 30 {want: "410c010e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) }}, 31 {want: "410c014e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) }}, 32 {want: "410c020e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) }}, 33 {want: "410c024e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) }}, 34 {want: "410c040e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) }}, 35 {want: "410c044e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) }}, 36 {want: "410c084e", setup: func(i *instruction) { i.asVecDup(operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) }}, 37 {want: "4104034e", setup: func(i *instruction) { i.asVecDupElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementB, 1) }}, 38 {want: "4104064e", setup: func(i *instruction) { i.asVecDupElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementH, 1) }}, 39 {want: "41040c4e", setup: func(i *instruction) { i.asVecDupElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementS, 1) }}, 40 {want: "4104184e", setup: func(i *instruction) { i.asVecDupElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementD, 1) }}, 41 {want: "4138032e", setup: func(i *instruction) { 42 i.asVecExtract(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B, 7) 43 }}, 44 {want: "4138036e", setup: func(i *instruction) { 45 i.asVecExtract(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B, 7) 46 }}, 47 {want: "410c036e", setup: func(i *instruction) { i.asVecMovElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementB, 1, 1) }}, 48 {want: "4114066e", setup: func(i *instruction) { i.asVecMovElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementH, 1, 1) }}, 49 {want: "41240c6e", setup: func(i *instruction) { i.asVecMovElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementS, 1, 1) }}, 50 {want: "4144186e", setup: func(i *instruction) { i.asVecMovElement(operandNR(v1VReg), operandNR(v2VReg), vecArrangementD, 1, 1) }}, 51 {want: "4104090f", setup: func(i *instruction) { 52 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement8B) 53 }}, 54 {want: "4104094f", setup: func(i *instruction) { 55 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement16B) 56 }}, 57 {want: "4104190f", setup: func(i *instruction) { 58 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement4H) 59 }}, 60 {want: "4104194f", setup: func(i *instruction) { 61 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement8H) 62 }}, 63 {want: "4104390f", setup: func(i *instruction) { 64 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement2S) 65 }}, 66 {want: "4104394f", setup: func(i *instruction) { 67 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement4S) 68 }}, 69 {want: "4104794f", setup: func(i *instruction) { 70 i.asVecShiftImm(vecOpSshr, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(7), vecArrangement2D) 71 }}, 72 73 {want: "41a40d0f", setup: func(i *instruction) { 74 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement8B) 75 }}, 76 {want: "41a40d4f", setup: func(i *instruction) { // sshll2 77 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement16B) 78 }}, 79 {want: "41a41d0f", setup: func(i *instruction) { 80 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement4H) 81 }}, 82 {want: "41a41d4f", setup: func(i *instruction) { // sshll2 83 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement8H) 84 }}, 85 {want: "41a43d0f", setup: func(i *instruction) { 86 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement2S) 87 }}, 88 {want: "41a43d4f", setup: func(i *instruction) { // sshll2 89 i.asVecShiftImm(vecOpSshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement4S) 90 }}, 91 {want: "41a40d2f", setup: func(i *instruction) { 92 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement8B) 93 }}, 94 {want: "41a40d6f", setup: func(i *instruction) { // ushll2 95 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement16B) 96 }}, 97 {want: "41a41d2f", setup: func(i *instruction) { 98 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement4H) 99 }}, 100 {want: "41a41d6f", setup: func(i *instruction) { // ushll2 101 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement8H) 102 }}, 103 {want: "41a43d2f", setup: func(i *instruction) { 104 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement2S) 105 }}, 106 {want: "41a43d6f", setup: func(i *instruction) { // ushll2 107 i.asVecShiftImm(vecOpUshll, operandNR(v1VReg), operandNR(v2VReg), operandShiftImm(3), vecArrangement4S) 108 }}, 109 {want: "4100030e", setup: func(i *instruction) { 110 i.asVecTbl(1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 111 }}, 112 {want: "4100034e", setup: func(i *instruction) { 113 i.asVecTbl(1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 114 }}, 115 {want: "4120040e", setup: func(i *instruction) { 116 i.asVecTbl(2, operandNR(v1VReg), operandNR(v2VReg), operandNR(v4VReg), vecArrangement8B) 117 }}, 118 {want: "4120044e", setup: func(i *instruction) { 119 i.asVecTbl(2, operandNR(v1VReg), operandNR(v2VReg), operandNR(v4VReg), vecArrangement16B) 120 }}, 121 {want: "4138030e", setup: func(i *instruction) { 122 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 123 }}, 124 {want: "4138034e", setup: func(i *instruction) { 125 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 126 }}, 127 {want: "4138430e", setup: func(i *instruction) { 128 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 129 }}, 130 {want: "4138434e", setup: func(i *instruction) { 131 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 132 }}, 133 {want: "4138830e", setup: func(i *instruction) { 134 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 135 }}, 136 {want: "4138834e", setup: func(i *instruction) { 137 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 138 }}, 139 {want: "4138c34e", setup: func(i *instruction) { 140 i.asVecPermute(vecOpZip1, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 141 }}, 142 {want: "411ca32e", setup: func(i *instruction) { 143 i.asVecRRRRewrite(vecOpBit, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 144 }}, 145 {want: "411ca36e", setup: func(i *instruction) { 146 i.asVecRRRRewrite(vecOpBit, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 147 }}, 148 {want: "411c236e", setup: func(i *instruction) { 149 i.asVecRRR(vecOpEOR, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 150 }}, 151 {want: "411c232e", setup: func(i *instruction) { 152 i.asVecRRR(vecOpEOR, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 153 }}, 154 {want: "4184234e", setup: func(i *instruction) { 155 i.asVecRRR(vecOpAdd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 156 }}, 157 {want: "4184a34e", setup: func(i *instruction) { 158 i.asVecRRR(vecOpAdd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 159 }}, 160 {want: "4184e34e", setup: func(i *instruction) { 161 i.asVecRRR(vecOpAdd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 162 }}, 163 {want: "410c230e", setup: func(i *instruction) { 164 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 165 }}, 166 {want: "410c234e", setup: func(i *instruction) { 167 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 168 }}, 169 {want: "410c630e", setup: func(i *instruction) { 170 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 171 }}, 172 {want: "410c634e", setup: func(i *instruction) { 173 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 174 }}, 175 {want: "410ca30e", setup: func(i *instruction) { 176 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 177 }}, 178 {want: "410ca34e", setup: func(i *instruction) { 179 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 180 }}, 181 {want: "410ce34e", setup: func(i *instruction) { 182 i.asVecRRR(vecOpSqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 183 }}, 184 {want: "410c232e", setup: func(i *instruction) { 185 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 186 }}, 187 {want: "410c236e", setup: func(i *instruction) { 188 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 189 }}, 190 {want: "410c632e", setup: func(i *instruction) { 191 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 192 }}, 193 {want: "410c636e", setup: func(i *instruction) { 194 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 195 }}, 196 {want: "410ca32e", setup: func(i *instruction) { 197 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 198 }}, 199 {want: "410ca36e", setup: func(i *instruction) { 200 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 201 }}, 202 {want: "410ce36e", setup: func(i *instruction) { 203 i.asVecRRR(vecOpUqadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 204 }}, 205 {want: "412c230e", setup: func(i *instruction) { 206 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 207 }}, 208 {want: "412c234e", setup: func(i *instruction) { 209 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 210 }}, 211 {want: "412c630e", setup: func(i *instruction) { 212 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 213 }}, 214 {want: "412c634e", setup: func(i *instruction) { 215 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 216 }}, 217 {want: "412ca30e", setup: func(i *instruction) { 218 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 219 }}, 220 {want: "412ca34e", setup: func(i *instruction) { 221 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 222 }}, 223 {want: "412ce34e", setup: func(i *instruction) { 224 i.asVecRRR(vecOpSqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 225 }}, 226 {want: "412c232e", setup: func(i *instruction) { 227 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 228 }}, 229 {want: "412c236e", setup: func(i *instruction) { 230 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 231 }}, 232 {want: "412c632e", setup: func(i *instruction) { 233 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 234 }}, 235 {want: "412c636e", setup: func(i *instruction) { 236 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 237 }}, 238 {want: "412ca32e", setup: func(i *instruction) { 239 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 240 }}, 241 {want: "412ca36e", setup: func(i *instruction) { 242 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 243 }}, 244 {want: "412ce36e", setup: func(i *instruction) { 245 i.asVecRRR(vecOpUqsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 246 }}, 247 {want: "4184232e", setup: func(i *instruction) { 248 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 249 }}, 250 {want: "4184236e", setup: func(i *instruction) { 251 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 252 }}, 253 {want: "4184632e", setup: func(i *instruction) { 254 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 255 }}, 256 {want: "4184636e", setup: func(i *instruction) { 257 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 258 }}, 259 {want: "4184a32e", setup: func(i *instruction) { 260 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 261 }}, 262 {want: "4184a36e", setup: func(i *instruction) { 263 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 264 }}, 265 {want: "4184e36e", setup: func(i *instruction) { 266 i.asVecRRR(vecOpSub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 267 }}, 268 {want: "41bc230e", setup: func(i *instruction) { 269 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 270 }}, 271 {want: "41bc234e", setup: func(i *instruction) { 272 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 273 }}, 274 {want: "41bc630e", setup: func(i *instruction) { 275 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 276 }}, 277 {want: "41bc634e", setup: func(i *instruction) { 278 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 279 }}, 280 {want: "41bca30e", setup: func(i *instruction) { 281 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 282 }}, 283 {want: "41bca34e", setup: func(i *instruction) { 284 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 285 }}, 286 {want: "41bce34e", setup: func(i *instruction) { 287 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 288 }}, 289 {want: "41bc230e", setup: func(i *instruction) { 290 i.asVecRRR(vecOpAddp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 291 }}, 292 {want: "41b8314e", setup: func(i *instruction) { 293 i.asVecLanes(vecOpAddv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 294 }}, 295 {want: "41b8710e", setup: func(i *instruction) { 296 i.asVecLanes(vecOpAddv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 297 }}, 298 {want: "41b8714e", setup: func(i *instruction) { 299 i.asVecLanes(vecOpAddv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 300 }}, 301 {want: "41b8b14e", setup: func(i *instruction) { 302 i.asVecLanes(vecOpAddv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 303 }}, 304 {want: "416c230e", setup: func(i *instruction) { 305 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 306 }}, 307 {want: "416c234e", setup: func(i *instruction) { 308 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 309 }}, 310 {want: "416c630e", setup: func(i *instruction) { 311 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 312 }}, 313 {want: "416c634e", setup: func(i *instruction) { 314 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 315 }}, 316 {want: "416ca30e", setup: func(i *instruction) { 317 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 318 }}, 319 {want: "416ca34e", setup: func(i *instruction) { 320 i.asVecRRR(vecOpSmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 321 }}, 322 {want: "416c232e", setup: func(i *instruction) { 323 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 324 }}, 325 {want: "416c236e", setup: func(i *instruction) { 326 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 327 }}, 328 {want: "416c632e", setup: func(i *instruction) { 329 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 330 }}, 331 {want: "416c636e", setup: func(i *instruction) { 332 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 333 }}, 334 {want: "416ca32e", setup: func(i *instruction) { 335 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 336 }}, 337 {want: "416ca36e", setup: func(i *instruction) { 338 i.asVecRRR(vecOpUmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 339 }}, 340 {want: "4164230e", setup: func(i *instruction) { 341 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 342 }}, 343 {want: "4164234e", setup: func(i *instruction) { 344 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 345 }}, 346 {want: "4164630e", setup: func(i *instruction) { 347 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 348 }}, 349 {want: "4164634e", setup: func(i *instruction) { 350 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 351 }}, 352 {want: "4164a30e", setup: func(i *instruction) { 353 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 354 }}, 355 {want: "4164a34e", setup: func(i *instruction) { 356 i.asVecRRR(vecOpSmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 357 }}, 358 {want: "4164232e", setup: func(i *instruction) { 359 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 360 }}, 361 {want: "4164236e", setup: func(i *instruction) { 362 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 363 }}, 364 {want: "4164632e", setup: func(i *instruction) { 365 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 366 }}, 367 {want: "4164636e", setup: func(i *instruction) { 368 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 369 }}, 370 {want: "4164a32e", setup: func(i *instruction) { 371 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 372 }}, 373 {want: "4164a36e", setup: func(i *instruction) { 374 i.asVecRRR(vecOpUmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 375 }}, 376 {want: "41a4232e", setup: func(i *instruction) { 377 i.asVecRRR(vecOpUmaxp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 378 }}, 379 {want: "41a4236e", setup: func(i *instruction) { 380 i.asVecRRR(vecOpUmaxp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 381 }}, 382 {want: "41a4632e", setup: func(i *instruction) { 383 i.asVecRRR(vecOpUmaxp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 384 }}, 385 {want: "41a4636e", setup: func(i *instruction) { 386 i.asVecRRR(vecOpUmaxp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 387 }}, 388 {want: "41a4a32e", setup: func(i *instruction) { 389 i.asVecRRR(vecOpUmaxp, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 390 }}, 391 {want: "41a8312e", setup: func(i *instruction) { 392 i.asVecLanes(vecOpUminv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 393 }}, 394 {want: "41a8316e", setup: func(i *instruction) { 395 i.asVecLanes(vecOpUminv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 396 }}, 397 {want: "41a8712e", setup: func(i *instruction) { 398 i.asVecLanes(vecOpUminv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 399 }}, 400 {want: "41a8716e", setup: func(i *instruction) { 401 i.asVecLanes(vecOpUminv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 402 }}, 403 {want: "41a8b16e", setup: func(i *instruction) { 404 i.asVecLanes(vecOpUminv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 405 }}, 406 {want: "4114232e", setup: func(i *instruction) { 407 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 408 }}, 409 {want: "4114236e", setup: func(i *instruction) { 410 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 411 }}, 412 {want: "4114632e", setup: func(i *instruction) { 413 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 414 }}, 415 {want: "4114636e", setup: func(i *instruction) { 416 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 417 }}, 418 {want: "4114a32e", setup: func(i *instruction) { 419 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 420 }}, 421 {want: "4114a36e", setup: func(i *instruction) { 422 i.asVecRRR(vecOpUrhadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 423 }}, 424 {want: "419c230e", setup: func(i *instruction) { 425 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 426 }}, 427 {want: "419c234e", setup: func(i *instruction) { 428 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 429 }}, 430 {want: "419c630e", setup: func(i *instruction) { 431 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 432 }}, 433 {want: "419c634e", setup: func(i *instruction) { 434 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 435 }}, 436 {want: "419ca30e", setup: func(i *instruction) { 437 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 438 }}, 439 {want: "419ca34e", setup: func(i *instruction) { 440 i.asVecRRR(vecOpMul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 441 }}, 442 {want: "4198200e", setup: func(i *instruction) { 443 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 444 }}, 445 {want: "4198204e", setup: func(i *instruction) { 446 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 447 }}, 448 {want: "4198600e", setup: func(i *instruction) { 449 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 450 }}, 451 {want: "4198604e", setup: func(i *instruction) { 452 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 453 }}, 454 {want: "4198a00e", setup: func(i *instruction) { 455 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 456 }}, 457 {want: "4198a04e", setup: func(i *instruction) { 458 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 459 }}, 460 {want: "4198e04e", setup: func(i *instruction) { 461 i.asVecMisc(vecOpCmeq0, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 462 }}, 463 {want: "418c232e", setup: func(i *instruction) { 464 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 465 }}, 466 {want: "418c236e", setup: func(i *instruction) { 467 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 468 }}, 469 {want: "418c632e", setup: func(i *instruction) { 470 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 471 }}, 472 {want: "418c636e", setup: func(i *instruction) { 473 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 474 }}, 475 {want: "418ca32e", setup: func(i *instruction) { 476 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 477 }}, 478 {want: "418ca36e", setup: func(i *instruction) { 479 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 480 }}, 481 {want: "418ce36e", setup: func(i *instruction) { 482 i.asVecRRR(vecOpCmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 483 }}, 484 {want: "4134230e", setup: func(i *instruction) { 485 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 486 }}, 487 {want: "4134234e", setup: func(i *instruction) { 488 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 489 }}, 490 {want: "4134630e", setup: func(i *instruction) { 491 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 492 }}, 493 {want: "4134634e", setup: func(i *instruction) { 494 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 495 }}, 496 {want: "4134a30e", setup: func(i *instruction) { 497 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 498 }}, 499 {want: "4134a34e", setup: func(i *instruction) { 500 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 501 }}, 502 {want: "4134e34e", setup: func(i *instruction) { 503 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 504 }}, 505 {want: "4134232e", setup: func(i *instruction) { 506 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 507 }}, 508 {want: "4134236e", setup: func(i *instruction) { 509 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 510 }}, 511 {want: "4134632e", setup: func(i *instruction) { 512 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 513 }}, 514 {want: "4134636e", setup: func(i *instruction) { 515 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 516 }}, 517 {want: "4134a32e", setup: func(i *instruction) { 518 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 519 }}, 520 {want: "4134a36e", setup: func(i *instruction) { 521 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 522 }}, 523 {want: "4134e36e", setup: func(i *instruction) { 524 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 525 }}, 526 {want: "413c230e", setup: func(i *instruction) { 527 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 528 }}, 529 {want: "413c234e", setup: func(i *instruction) { 530 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 531 }}, 532 {want: "413c630e", setup: func(i *instruction) { 533 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 534 }}, 535 {want: "413c634e", setup: func(i *instruction) { 536 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 537 }}, 538 {want: "413ca30e", setup: func(i *instruction) { 539 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 540 }}, 541 {want: "413ca34e", setup: func(i *instruction) { 542 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 543 }}, 544 {want: "413ce34e", setup: func(i *instruction) { 545 i.asVecRRR(vecOpCmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 546 }}, 547 {want: "4134230e", setup: func(i *instruction) { 548 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 549 }}, 550 {want: "4134234e", setup: func(i *instruction) { 551 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 552 }}, 553 {want: "4134630e", setup: func(i *instruction) { 554 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 555 }}, 556 {want: "4134634e", setup: func(i *instruction) { 557 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 558 }}, 559 {want: "4134a30e", setup: func(i *instruction) { 560 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 561 }}, 562 {want: "4134a34e", setup: func(i *instruction) { 563 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 564 }}, 565 {want: "4134e34e", setup: func(i *instruction) { 566 i.asVecRRR(vecOpCmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 567 }}, 568 {want: "4134232e", setup: func(i *instruction) { 569 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 570 }}, 571 {want: "4134236e", setup: func(i *instruction) { 572 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 573 }}, 574 {want: "4134632e", setup: func(i *instruction) { 575 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 576 }}, 577 {want: "4134636e", setup: func(i *instruction) { 578 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 579 }}, 580 {want: "4134a32e", setup: func(i *instruction) { 581 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 582 }}, 583 {want: "4134a36e", setup: func(i *instruction) { 584 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 585 }}, 586 {want: "4134e36e", setup: func(i *instruction) { 587 i.asVecRRR(vecOpCmhi, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 588 }}, 589 {want: "413c232e", setup: func(i *instruction) { 590 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 591 }}, 592 {want: "413c236e", setup: func(i *instruction) { 593 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 594 }}, 595 {want: "413c632e", setup: func(i *instruction) { 596 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 597 }}, 598 {want: "413c636e", setup: func(i *instruction) { 599 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 600 }}, 601 {want: "413ca32e", setup: func(i *instruction) { 602 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 603 }}, 604 {want: "413ca36e", setup: func(i *instruction) { 605 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 606 }}, 607 {want: "413ce36e", setup: func(i *instruction) { 608 i.asVecRRR(vecOpCmhs, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 609 }}, 610 {want: "41f4230e", setup: func(i *instruction) { 611 i.asVecRRR(vecOpFmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 612 }}, 613 {want: "41f4234e", setup: func(i *instruction) { 614 i.asVecRRR(vecOpFmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 615 }}, 616 {want: "41f4634e", setup: func(i *instruction) { 617 i.asVecRRR(vecOpFmax, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 618 }}, 619 {want: "41f4a30e", setup: func(i *instruction) { 620 i.asVecRRR(vecOpFmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 621 }}, 622 {want: "41f4a34e", setup: func(i *instruction) { 623 i.asVecRRR(vecOpFmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 624 }}, 625 {want: "41f4e34e", setup: func(i *instruction) { 626 i.asVecRRR(vecOpFmin, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 627 }}, 628 {want: "41d4230e", setup: func(i *instruction) { 629 i.asVecRRR(vecOpFadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 630 }}, 631 {want: "41d4234e", setup: func(i *instruction) { 632 i.asVecRRR(vecOpFadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 633 }}, 634 {want: "41d4634e", setup: func(i *instruction) { 635 i.asVecRRR(vecOpFadd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 636 }}, 637 {want: "41d4a30e", setup: func(i *instruction) { 638 i.asVecRRR(vecOpFsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 639 }}, 640 {want: "41d4a34e", setup: func(i *instruction) { 641 i.asVecRRR(vecOpFsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 642 }}, 643 {want: "41d4e34e", setup: func(i *instruction) { 644 i.asVecRRR(vecOpFsub, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 645 }}, 646 {want: "41dc232e", setup: func(i *instruction) { 647 i.asVecRRR(vecOpFmul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 648 }}, 649 {want: "41dc236e", setup: func(i *instruction) { 650 i.asVecRRR(vecOpFmul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 651 }}, 652 {want: "41dc636e", setup: func(i *instruction) { 653 i.asVecRRR(vecOpFmul, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 654 }}, 655 {want: "41b4636e", setup: func(i *instruction) { 656 i.asVecRRR(vecOpSqrdmulh, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 657 }}, 658 {want: "41b4632e", setup: func(i *instruction) { 659 i.asVecRRR(vecOpSqrdmulh, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 660 }}, 661 {want: "41b4a32e", setup: func(i *instruction) { 662 i.asVecRRR(vecOpSqrdmulh, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 663 }}, 664 {want: "41b4a36e", setup: func(i *instruction) { 665 i.asVecRRR(vecOpSqrdmulh, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 666 }}, 667 {want: "41fc232e", setup: func(i *instruction) { 668 i.asVecRRR(vecOpFdiv, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 669 }}, 670 {want: "41fc236e", setup: func(i *instruction) { 671 i.asVecRRR(vecOpFdiv, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 672 }}, 673 {want: "41fc636e", setup: func(i *instruction) { 674 i.asVecRRR(vecOpFdiv, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 675 }}, 676 {want: "41e4230e", setup: func(i *instruction) { 677 i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 678 }}, 679 {want: "41e4234e", setup: func(i *instruction) { 680 i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 681 }}, 682 {want: "41e4634e", setup: func(i *instruction) { 683 i.asVecRRR(vecOpFcmeq, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 684 }}, 685 {want: "41e4a32e", setup: func(i *instruction) { 686 i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 687 }}, 688 {want: "41e4a36e", setup: func(i *instruction) { 689 i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 690 }}, 691 {want: "41e4e36e", setup: func(i *instruction) { 692 i.asVecRRR(vecOpFcmgt, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 693 }}, 694 {want: "41e4232e", setup: func(i *instruction) { 695 i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 696 }}, 697 {want: "41e4236e", setup: func(i *instruction) { 698 i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4S) 699 }}, 700 {want: "41e4636e", setup: func(i *instruction) { 701 i.asVecRRR(vecOpFcmge, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 702 }}, 703 {want: "4198210e", setup: func(i *instruction) { 704 i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 705 }}, 706 {want: "4198214e", setup: func(i *instruction) { 707 i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 708 }}, 709 {want: "4198614e", setup: func(i *instruction) { 710 i.asVecMisc(vecOpFrintm, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 711 }}, 712 {want: "4188210e", setup: func(i *instruction) { 713 i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 714 }}, 715 {want: "4188214e", setup: func(i *instruction) { 716 i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 717 }}, 718 {want: "4188614e", setup: func(i *instruction) { 719 i.asVecMisc(vecOpFrintn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 720 }}, 721 {want: "4188a10e", setup: func(i *instruction) { 722 i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 723 }}, 724 {want: "4188a14e", setup: func(i *instruction) { 725 i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 726 }}, 727 {want: "4188e14e", setup: func(i *instruction) { 728 i.asVecMisc(vecOpFrintp, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 729 }}, 730 {want: "4198a10e", setup: func(i *instruction) { 731 i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 732 }}, 733 {want: "4198a14e", setup: func(i *instruction) { 734 i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 735 }}, 736 {want: "4198e14e", setup: func(i *instruction) { 737 i.asVecMisc(vecOpFrintz, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 738 }}, 739 {want: "4178610e", setup: func(i *instruction) { 740 i.asVecMisc(vecOpFcvtl, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 741 }}, 742 {want: "4178210e", setup: func(i *instruction) { 743 i.asVecMisc(vecOpFcvtl, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 744 }}, 745 {want: "4168610e", setup: func(i *instruction) { 746 i.asVecMisc(vecOpFcvtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 747 }}, 748 {want: "4168210e", setup: func(i *instruction) { 749 i.asVecMisc(vecOpFcvtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 750 }}, 751 {want: "41b8a10e", setup: func(i *instruction) { 752 i.asVecMisc(vecOpFcvtzs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 753 }}, 754 {want: "41b8a14e", setup: func(i *instruction) { 755 i.asVecMisc(vecOpFcvtzs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 756 }}, 757 {want: "41b8e14e", setup: func(i *instruction) { 758 i.asVecMisc(vecOpFcvtzs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 759 }}, 760 {want: "41b8a12e", setup: func(i *instruction) { 761 i.asVecMisc(vecOpFcvtzu, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 762 }}, 763 {want: "41b8a16e", setup: func(i *instruction) { 764 i.asVecMisc(vecOpFcvtzu, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 765 }}, 766 {want: "41b8e16e", setup: func(i *instruction) { 767 i.asVecMisc(vecOpFcvtzu, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 768 }}, 769 {want: "41d8210e", setup: func(i *instruction) { 770 i.asVecMisc(vecOpScvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 771 }}, 772 {want: "41d8214e", setup: func(i *instruction) { 773 i.asVecMisc(vecOpScvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 774 }}, 775 {want: "41d8614e", setup: func(i *instruction) { 776 i.asVecMisc(vecOpScvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 777 }}, 778 {want: "41d8212e", setup: func(i *instruction) { 779 i.asVecMisc(vecOpUcvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 780 }}, 781 {want: "41d8216e", setup: func(i *instruction) { 782 i.asVecMisc(vecOpUcvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 783 }}, 784 {want: "41d8616e", setup: func(i *instruction) { 785 i.asVecMisc(vecOpUcvtf, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 786 }}, 787 {want: "4148210e", setup: func(i *instruction) { 788 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 789 }}, 790 {want: "4148214e", setup: func(i *instruction) { // sqxtn2 791 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 792 }}, 793 {want: "4148610e", setup: func(i *instruction) { 794 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 795 }}, 796 {want: "4148614e", setup: func(i *instruction) { // sqxtn2 797 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 798 }}, 799 {want: "4148a10e", setup: func(i *instruction) { 800 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 801 }}, 802 {want: "4148a14e", setup: func(i *instruction) { // sqxtun2 803 i.asVecMisc(vecOpSqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 804 }}, 805 {want: "4128212e", setup: func(i *instruction) { 806 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 807 }}, 808 {want: "4128216e", setup: func(i *instruction) { // uqxtun2 809 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 810 }}, 811 {want: "4128612e", setup: func(i *instruction) { 812 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 813 }}, 814 {want: "4128616e", setup: func(i *instruction) { // sqxtun2 815 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 816 }}, 817 {want: "4128a12e", setup: func(i *instruction) { 818 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 819 }}, 820 {want: "4128a16e", setup: func(i *instruction) { // sqxtun2 821 i.asVecMisc(vecOpSqxtun, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 822 }}, 823 {want: "4148212e", setup: func(i *instruction) { 824 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 825 }}, 826 {want: "4148216e", setup: func(i *instruction) { // uqxtn2 827 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 828 }}, 829 {want: "4148612e", setup: func(i *instruction) { 830 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 831 }}, 832 {want: "4148616e", setup: func(i *instruction) { // sqxtn2 833 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 834 }}, 835 {want: "4148a12e", setup: func(i *instruction) { 836 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 837 }}, 838 {want: "4148a16e", setup: func(i *instruction) { // sqxtn2 839 i.asVecMisc(vecOpUqxtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 840 }}, 841 {want: "41b8200e", setup: func(i *instruction) { 842 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 843 }}, 844 {want: "41b8204e", setup: func(i *instruction) { 845 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 846 }}, 847 {want: "41b8600e", setup: func(i *instruction) { 848 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 849 }}, 850 {want: "41b8604e", setup: func(i *instruction) { 851 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 852 }}, 853 {want: "41b8a00e", setup: func(i *instruction) { 854 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 855 }}, 856 {want: "41b8a04e", setup: func(i *instruction) { 857 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 858 }}, 859 {want: "41b8e04e", setup: func(i *instruction) { 860 i.asVecMisc(vecOpAbs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 861 }}, 862 {want: "41f8a00e", setup: func(i *instruction) { 863 i.asVecMisc(vecOpFabs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 864 }}, 865 {want: "41f8a04e", setup: func(i *instruction) { 866 i.asVecMisc(vecOpFabs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 867 }}, 868 {want: "41f8e04e", setup: func(i *instruction) { 869 i.asVecMisc(vecOpFabs, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 870 }}, 871 {want: "41b8202e", setup: func(i *instruction) { 872 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 873 }}, 874 {want: "41b8206e", setup: func(i *instruction) { 875 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 876 }}, 877 {want: "41b8602e", setup: func(i *instruction) { 878 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 879 }}, 880 {want: "41b8606e", setup: func(i *instruction) { 881 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 882 }}, 883 {want: "41b8a02e", setup: func(i *instruction) { 884 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 885 }}, 886 {want: "41b8a06e", setup: func(i *instruction) { 887 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 888 }}, 889 {want: "41b8e06e", setup: func(i *instruction) { 890 i.asVecMisc(vecOpNeg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 891 }}, 892 {want: "4128a10e", setup: func(i *instruction) { 893 i.asVecMisc(vecOpXtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 894 }}, 895 {want: "4128a10e", setup: func(i *instruction) { 896 i.asVecMisc(vecOpXtn, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 897 }}, 898 {want: "41f8a02e", setup: func(i *instruction) { 899 i.asVecMisc(vecOpFneg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 900 }}, 901 {want: "41f8a06e", setup: func(i *instruction) { 902 i.asVecMisc(vecOpFneg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 903 }}, 904 {want: "41f8e06e", setup: func(i *instruction) { 905 i.asVecMisc(vecOpFneg, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 906 }}, 907 {want: "41f8a12e", setup: func(i *instruction) { 908 i.asVecMisc(vecOpFsqrt, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2S) 909 }}, 910 {want: "41f8a16e", setup: func(i *instruction) { 911 i.asVecMisc(vecOpFsqrt, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 912 }}, 913 {want: "41f8e16e", setup: func(i *instruction) { 914 i.asVecMisc(vecOpFsqrt, operandNR(v1VReg), operandNR(v2VReg), vecArrangement2D) 915 }}, 916 {want: "4100839a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), eq, true) }}, 917 {want: "4110839a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), ne, true) }}, 918 {want: "4100831a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), eq, false) }}, 919 {want: "4110831a", setup: func(i *instruction) { i.asCSel(operandNR(x1VReg), operandNR(x2VReg), operandNR(x3VReg), ne, false) }}, 920 {want: "41cc631e", setup: func(i *instruction) { i.asFpuCSel(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), gt, true) }}, 921 {want: "41bc631e", setup: func(i *instruction) { i.asFpuCSel(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), lt, true) }}, 922 {want: "41cc231e", setup: func(i *instruction) { i.asFpuCSel(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), gt, false) }}, 923 {want: "41bc231e", setup: func(i *instruction) { i.asFpuCSel(operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), lt, false) }}, 924 {want: "411c014e", setup: func(i *instruction) { i.asMovToVec(operandNR(v1VReg), operandNR(x2VReg), vecArrangementB, 0) }}, 925 {want: "411c024e", setup: func(i *instruction) { i.asMovToVec(operandNR(v1VReg), operandNR(x2VReg), vecArrangementH, 0) }}, 926 {want: "411c044e", setup: func(i *instruction) { i.asMovToVec(operandNR(v1VReg), operandNR(x2VReg), vecArrangementS, 0) }}, 927 {want: "411c084e", setup: func(i *instruction) { i.asMovToVec(operandNR(v1VReg), operandNR(x2VReg), vecArrangementD, 0) }}, 928 {want: "413c010e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementB, 0, false) }}, 929 {want: "413c020e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementH, 0, false) }}, 930 {want: "413c040e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementS, 0, false) }}, 931 {want: "413c084e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementD, 0, false) }}, 932 {want: "412c030e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementB, 1, true) }}, 933 {want: "412c060e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementH, 1, true) }}, 934 {want: "412c0c4e", setup: func(i *instruction) { i.asMovFromVec(operandNR(x1VReg), operandNR(v2VReg), vecArrangementS, 1, true) }}, 935 {want: "410c084e", setup: func(i *instruction) { i.asVecDup(operandNR(x1VReg), operandNR(v2VReg), vecArrangement2D) }}, 936 {want: "4140036e", setup: func(i *instruction) { // 4140036e 937 i.asVecExtract(operandNR(x1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B, 8) 938 }}, 939 {want: "4138034e", setup: func(i *instruction) { 940 i.asVecPermute(vecOpZip1, operandNR(x1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 941 }}, 942 {want: "4104214f", setup: func(i *instruction) { 943 i.asVecShiftImm(vecOpSshr, operandNR(x1VReg), operandNR(x2VReg), operandShiftImm(31), vecArrangement4S) 944 }}, 945 {want: "5b28030b", setup: func(i *instruction) { 946 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), false) 947 }}, 948 {want: "5b28038b", setup: func(i *instruction) { 949 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), true) 950 }}, 951 {want: "5b28032b", setup: func(i *instruction) { 952 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), false) 953 }}, 954 {want: "5b2803ab", setup: func(i *instruction) { 955 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), true) 956 }}, 957 {want: "5b28430b", setup: func(i *instruction) { 958 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), false) 959 }}, 960 {want: "5b28438b", setup: func(i *instruction) { 961 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), true) 962 }}, 963 {want: "5b28432b", setup: func(i *instruction) { 964 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), false) 965 }}, 966 {want: "5b2843ab", setup: func(i *instruction) { 967 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), true) 968 }}, 969 {want: "5b28830b", setup: func(i *instruction) { 970 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), false) 971 }}, 972 {want: "5b28838b", setup: func(i *instruction) { 973 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), true) 974 }}, 975 {want: "5b28832b", setup: func(i *instruction) { 976 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), false) 977 }}, 978 {want: "5b2883ab", setup: func(i *instruction) { 979 i.asALU(aluOpAddS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), true) 980 }}, 981 {want: "5b28034b", setup: func(i *instruction) { 982 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), false) 983 }}, 984 {want: "5b2803cb", setup: func(i *instruction) { 985 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), true) 986 }}, 987 {want: "5b28036b", setup: func(i *instruction) { 988 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), false) 989 }}, 990 {want: "5b2803eb", setup: func(i *instruction) { 991 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSL), true) 992 }}, 993 {want: "5b28434b", setup: func(i *instruction) { 994 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), false) 995 }}, 996 {want: "5b2843cb", setup: func(i *instruction) { 997 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), true) 998 }}, 999 {want: "5b28436b", setup: func(i *instruction) { 1000 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), false) 1001 }}, 1002 {want: "5b2843eb", setup: func(i *instruction) { 1003 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpLSR), true) 1004 }}, 1005 {want: "5b28834b", setup: func(i *instruction) { 1006 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), false) 1007 }}, 1008 {want: "5b2883cb", setup: func(i *instruction) { 1009 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), true) 1010 }}, 1011 {want: "5b28836b", setup: func(i *instruction) { 1012 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), false) 1013 }}, 1014 {want: "5b2883eb", setup: func(i *instruction) { 1015 i.asALU(aluOpSubS, operandNR(tmpRegVReg), operandNR(x2VReg), operandSR(x3VReg, 10, shiftOpASR), true) 1016 }}, 1017 {want: "60033fd6", setup: func(i *instruction) { 1018 i.asCallIndirect(tmpRegVReg, nil) 1019 }}, 1020 {want: "fb633bcb", setup: func(i *instruction) { 1021 i.asALU(aluOpSub, operandNR(tmpRegVReg), operandNR(spVReg), operandNR(tmpRegVReg), true) 1022 }}, 1023 {want: "fb633b8b", setup: func(i *instruction) { 1024 i.asALU(aluOpAdd, operandNR(tmpRegVReg), operandNR(spVReg), operandNR(tmpRegVReg), true) 1025 }}, 1026 {want: "2000020a", setup: func(i *instruction) { 1027 i.asALU(aluOpAnd, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), false) 1028 }}, 1029 {want: "2000028a", setup: func(i *instruction) { 1030 i.asALU(aluOpAnd, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), true) 1031 }}, 1032 {want: "2010028a", setup: func(i *instruction) { 1033 i.asALU(aluOpAnd, operandNR(x0VReg), operandNR(x1VReg), operandSR(x2VReg, 4, shiftOpLSL), true) 1034 }}, 1035 {want: "2030428a", setup: func(i *instruction) { 1036 i.asALU(aluOpAnd, operandNR(x0VReg), operandNR(x1VReg), operandSR(x2VReg, 12, shiftOpLSR), true) 1037 }}, 1038 {want: "2000022a", setup: func(i *instruction) { 1039 i.asALU(aluOpOrr, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), false) 1040 }}, 1041 {want: "200002aa", setup: func(i *instruction) { 1042 i.asALU(aluOpOrr, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), true) 1043 }}, 1044 {want: "201002aa", setup: func(i *instruction) { 1045 i.asALU(aluOpOrr, operandNR(x0VReg), operandNR(x1VReg), operandSR(x2VReg, 4, shiftOpLSL), true) 1046 }}, 1047 {want: "201082aa", setup: func(i *instruction) { 1048 i.asALU(aluOpOrr, operandNR(x0VReg), operandNR(x1VReg), operandSR(x2VReg, 4, shiftOpASR), true) 1049 }}, 1050 {want: "2000024a", setup: func(i *instruction) { 1051 i.asALU(aluOpEor, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), false) 1052 }}, 1053 {want: "200002ca", setup: func(i *instruction) { 1054 i.asALU(aluOpEor, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), true) 1055 }}, 1056 {want: "201002ca", setup: func(i *instruction) { 1057 i.asALU(aluOpEor, operandNR(x0VReg), operandNR(x1VReg), operandSR(x2VReg, 4, shiftOpLSL), true) 1058 }}, 1059 {want: "202cc21a", setup: func(i *instruction) { 1060 i.asALU(aluOpRotR, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), false) 1061 }}, 1062 {want: "202cc29a", setup: func(i *instruction) { 1063 i.asALU(aluOpRotR, operandNR(x0VReg), operandNR(x1VReg), operandNR(x2VReg), true) 1064 }}, 1065 {want: "30000010", setup: func(i *instruction) { i.asAdr(v16VReg, 4) }}, 1066 {want: "50050030", setup: func(i *instruction) { i.asAdr(v16VReg, 169) }}, 1067 {want: "101e302e", setup: func(i *instruction) { i.asLoadFpuConst32(v16VReg, uint64(math.Float32bits(0))) }}, 1068 {want: "5000001c020000140000803f", setup: func(i *instruction) { 1069 i.asLoadFpuConst32(v16VReg, uint64(math.Float32bits(1.0))) 1070 }}, 1071 {want: "101e302e", setup: func(i *instruction) { i.asLoadFpuConst64(v16VReg, uint64(math.Float32bits(0))) }}, 1072 {want: "5000005c03000014000000000000f03f", setup: func(i *instruction) { 1073 i.asLoadFpuConst64(v16VReg, math.Float64bits(1.0)) 1074 }}, 1075 {want: "101e306e", setup: func(i *instruction) { i.asLoadFpuConst128(v16VReg, 0, 0) }}, 1076 {want: "5000009c05000014ffffffffffffffffaaaaaaaaaaaaaaaa", setup: func(i *instruction) { i.asLoadFpuConst128(v16VReg, 0xffffffff_ffffffff, 0xaaaaaaaa_aaaaaaaa) }}, 1077 {want: "8220061b", setup: func(i *instruction) { 1078 i.asALURRRR(aluOpMAdd, operandNR(x2VReg), operandNR(x4VReg), operandNR(x6VReg), operandNR(x8VReg), false) 1079 }}, 1080 {want: "8220069b", setup: func(i *instruction) { 1081 i.asALURRRR(aluOpMAdd, operandNR(x2VReg), operandNR(x4VReg), operandNR(x6VReg), operandNR(x8VReg), true) 1082 }}, 1083 {want: "82a0061b", setup: func(i *instruction) { 1084 i.asALURRRR(aluOpMSub, operandNR(x2VReg), operandNR(x4VReg), operandNR(x6VReg), operandNR(x8VReg), false) 1085 }}, 1086 {want: "82a0069b", setup: func(i *instruction) { 1087 i.asALURRRR(aluOpMSub, operandNR(x2VReg), operandNR(x4VReg), operandNR(x6VReg), operandNR(x8VReg), true) 1088 }}, 1089 {want: "00213f1e", setup: func(i *instruction) { i.asFpuCmp(operandNR(v8VReg), operandNR(v31VReg), false) }}, 1090 {want: "00217f1e", setup: func(i *instruction) { i.asFpuCmp(operandNR(v8VReg), operandNR(v31VReg), true) }}, 1091 {want: "b21c0053", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 8, 32, false) }}, 1092 {want: "b23c0053", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 16, 32, false) }}, 1093 {want: "b21c0053", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 8, 64, false) }}, 1094 {want: "b23c0053", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 16, 64, false) }}, 1095 {want: "f203052a", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 32, 64, false) }}, 1096 {want: "b21c0013", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 8, 32, true) }}, 1097 {want: "b23c0013", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 16, 32, true) }}, 1098 {want: "b21c4093", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 8, 64, true) }}, 1099 {want: "b23c4093", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 16, 64, true) }}, 1100 {want: "b27c4093", setup: func(i *instruction) { i.asExtend(x18VReg, x5VReg, 32, 64, true) }}, 1101 {want: "f2079f9a", setup: func(i *instruction) { i.asCSet(x18VReg, false, ne) }}, 1102 {want: "f2179f9a", setup: func(i *instruction) { i.asCSet(x18VReg, false, eq) }}, 1103 {want: "e0039fda", setup: func(i *instruction) { i.asCSet(x0VReg, true, ne) }}, 1104 {want: "f2139fda", setup: func(i *instruction) { i.asCSet(x18VReg, true, eq) }}, 1105 {want: "32008012", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 0, false) }}, 1106 {want: "52559512", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 0, false) }}, 1107 {want: "f2ff9f12", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 0, false) }}, 1108 {want: "3200a012", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 1, false) }}, 1109 {want: "5255b512", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 1, false) }}, 1110 {want: "f2ffbf12", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 1, false) }}, 1111 {want: "32008092", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 0, true) }}, 1112 {want: "52559592", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 0, true) }}, 1113 {want: "f2ff9f92", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 0, true) }}, 1114 {want: "3200a092", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 1, true) }}, 1115 {want: "5255b592", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 1, true) }}, 1116 {want: "f2ffbf92", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 1, true) }}, 1117 {want: "3200c092", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 2, true) }}, 1118 {want: "5255d592", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 2, true) }}, 1119 {want: "f2ffdf92", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 2, true) }}, 1120 {want: "3200e092", setup: func(i *instruction) { i.asMOVN(x18VReg, 1, 3, true) }}, 1121 {want: "5255f592", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xaaaa, 3, true) }}, 1122 {want: "f2ffff92", setup: func(i *instruction) { i.asMOVN(x18VReg, 0xffff, 3, true) }}, 1123 {want: "5255b572", setup: func(i *instruction) { i.asMOVK(x18VReg, 0xaaaa, 1, false) }}, 1124 {want: "5255f5f2", setup: func(i *instruction) { i.asMOVK(x18VReg, 0xaaaa, 3, true) }}, 1125 {want: "5255b552", setup: func(i *instruction) { i.asMOVZ(x18VReg, 0xaaaa, 1, false) }}, 1126 {want: "5255f5d2", setup: func(i *instruction) { i.asMOVZ(x18VReg, 0xaaaa, 3, true) }}, 1127 {want: "4f020012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1, false) }}, 1128 {want: "4f0a0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7, false) }}, 1129 {want: "4f0e0012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xf, false) }}, 1130 {want: "4f120012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1f, false) }}, 1131 {want: "4f160012", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3f, false) }}, 1132 {want: "4f021112", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x8000, false) }}, 1133 {want: "4f721f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3ffffffe, false) }}, 1134 {want: "4f7a1f12", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffffffe, false) }}, 1135 {want: "4f024092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1, true) }}, 1136 {want: "4f0a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7, true) }}, 1137 {want: "4f0e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xf, true) }}, 1138 {want: "4f124092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x1f, true) }}, 1139 {want: "4f164092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x3f, true) }}, 1140 {want: "4f4e4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffff, true) }}, 1141 {want: "4f7e7092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xffffffff0000, true) }}, 1142 {want: "4f7a4092", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7fffffff, true) }}, 1143 {want: "4f767f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0x7ffffffe, true) }}, 1144 {want: "4fba7f92", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpAnd, x15VReg, x18VReg, 0xfffffffffffe, true) }}, 1145 {want: "4f020032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1, false) }}, 1146 {want: "4f0a0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7, false) }}, 1147 {want: "4f0e0032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xf, false) }}, 1148 {want: "4f120032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1f, false) }}, 1149 {want: "4f160032", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3f, false) }}, 1150 {want: "4f021132", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x8000, false) }}, 1151 {want: "4f721f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3ffffffe, false) }}, 1152 {want: "4f7a1f32", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffffffe, false) }}, 1153 {want: "4f0240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1, true) }}, 1154 {want: "4f0a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7, true) }}, 1155 {want: "4f0e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xf, true) }}, 1156 {want: "4f1240b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x1f, true) }}, 1157 {want: "4f1640b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x3f, true) }}, 1158 {want: "4f4e40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffff, true) }}, 1159 {want: "4f7e70b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xffffffff0000, true) }}, 1160 {want: "4f7a40b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7fffffff, true) }}, 1161 {want: "4f767fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0x7ffffffe, true) }}, 1162 {want: "4fba7fb2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x15VReg, x18VReg, 0xfffffffffffe, true) }}, 1163 {want: "4f020052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1, false) }}, 1164 {want: "4f0a0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7, false) }}, 1165 {want: "4f0e0052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xf, false) }}, 1166 {want: "4f120052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1f, false) }}, 1167 {want: "4f160052", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3f, false) }}, 1168 {want: "4f021152", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x8000, false) }}, 1169 {want: "4f721f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3ffffffe, false) }}, 1170 {want: "4f7a1f52", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffffffe, false) }}, 1171 {want: "4f0240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1, true) }}, 1172 {want: "4f0a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7, true) }}, 1173 {want: "4f0e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xf, true) }}, 1174 {want: "4f1240d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x1f, true) }}, 1175 {want: "4f1640d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x3f, true) }}, 1176 {want: "4f4e40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffff, true) }}, 1177 {want: "4f7e70d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xffffffff0000, true) }}, 1178 {want: "4f7a40d2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7fffffff, true) }}, 1179 {want: "4f767fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0x7ffffffe, true) }}, 1180 {want: "4fba7fd2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpEor, x15VReg, x18VReg, 0xfffffffffffe, true) }}, 1181 {want: "f20300b2", setup: func(i *instruction) { i.asALUBitmaskImm(aluOpOrr, x18VReg, xzrVReg, 0x100000001, true) }}, 1182 {want: "f21fbf0e", setup: func(i *instruction) { i.asFpuMov64(v18VReg, v31VReg) }}, 1183 {want: "f21fbf4e", setup: func(i *instruction) { i.asFpuMov128(v18VReg, v31VReg) }}, 1184 {want: "40a034ab", setup: func(i *instruction) { 1185 i.asALU(aluOpAddS, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTH, 64), false) 1186 }}, 1187 {want: "4080348b", setup: func(i *instruction) { 1188 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTB, 64), false) 1189 }}, 1190 {want: "40a0348b", setup: func(i *instruction) { 1191 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTH, 64), false) 1192 }}, 1193 {want: "40c0348b", setup: func(i *instruction) { 1194 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTW, 64), false) 1195 }}, 1196 {want: "4080340b", setup: func(i *instruction) { 1197 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTB, 32), false) 1198 }}, 1199 {want: "40a0340b", setup: func(i *instruction) { 1200 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTH, 32), false) 1201 }}, 1202 {want: "40c0340b", setup: func(i *instruction) { 1203 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpSXTW, 32), false) 1204 }}, 1205 {want: "400034eb", setup: func(i *instruction) { 1206 i.asALU(aluOpSubS, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTB, 64), false) 1207 }}, 1208 {want: "400034cb", setup: func(i *instruction) { 1209 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTB, 64), false) 1210 }}, 1211 {want: "402034cb", setup: func(i *instruction) { 1212 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTH, 64), false) 1213 }}, 1214 {want: "404034cb", setup: func(i *instruction) { 1215 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTW, 64), false) 1216 }}, 1217 {want: "4000344b", setup: func(i *instruction) { 1218 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTB, 32), false) 1219 }}, 1220 {want: "4020344b", setup: func(i *instruction) { 1221 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTH, 32), false) 1222 }}, 1223 {want: "4040344b", setup: func(i *instruction) { 1224 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandER(x20VReg, extendOpUXTW, 32), false) 1225 }}, 1226 {want: "4000140b", setup: func(i *instruction) { 1227 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1228 }}, 1229 {want: "4000148b", setup: func(i *instruction) { 1230 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1231 }}, 1232 {want: "40001f8b", setup: func(i *instruction) { 1233 i.asALU(aluOpAdd, operandNR(x0VReg), operandNR(x2VReg), operandNR(xzrVReg), true) 1234 }}, 1235 {want: "4000142b", setup: func(i *instruction) { 1236 i.asALU(aluOpAddS, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1237 }}, 1238 {want: "400014ab", setup: func(i *instruction) { 1239 i.asALU(aluOpAddS, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1240 }}, 1241 {want: "4000144b", setup: func(i *instruction) { 1242 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1243 }}, 1244 {want: "400014cb", setup: func(i *instruction) { 1245 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1246 }}, 1247 {want: "40001fcb", setup: func(i *instruction) { 1248 i.asALU(aluOpSub, operandNR(x0VReg), operandNR(x2VReg), operandNR(xzrVReg), true) 1249 }}, 1250 {want: "400014eb", setup: func(i *instruction) { 1251 i.asALU(aluOpSubS, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1252 }}, 1253 {want: "40001feb", setup: func(i *instruction) { 1254 i.asALU(aluOpSubS, operandNR(x0VReg), operandNR(x2VReg), operandNR(xzrVReg), true) 1255 }}, 1256 {want: "c0035fd6", setup: func(i *instruction) { i.asRet(nil) }}, 1257 {want: "e303042a", setup: func(i *instruction) { i.asMove32(x3VReg, x4VReg) }}, 1258 {want: "fe03002a", setup: func(i *instruction) { i.asMove32(x30VReg, x0VReg) }}, 1259 {want: "e30304aa", setup: func(i *instruction) { i.asMove64(x3VReg, x4VReg) }}, 1260 {want: "fe0300aa", setup: func(i *instruction) { i.asMove64(x30VReg, x0VReg) }}, 1261 {want: "9f000091", setup: func(i *instruction) { i.asMove64(spVReg, x4VReg) }}, 1262 {want: "e0030091", setup: func(i *instruction) { i.asMove64(x0VReg, spVReg) }}, 1263 {want: "e17bc1a8", setup: func(i *instruction) { 1264 i.asLoadPair64(x1VReg, x30VReg, addressModePreOrPostIndex(spVReg, 16, false)) 1265 }}, 1266 {want: "e17bc1a9", setup: func(i *instruction) { 1267 i.asLoadPair64(x1VReg, x30VReg, addressModePreOrPostIndex(spVReg, 16, true)) 1268 }}, 1269 {want: "e17b81a8", setup: func(i *instruction) { 1270 i.asStorePair64(x1VReg, x30VReg, addressModePreOrPostIndex(spVReg, 16, false)) 1271 }}, 1272 {want: "e17b81a9", setup: func(i *instruction) { 1273 i.asStorePair64(x1VReg, x30VReg, addressModePreOrPostIndex(spVReg, 16, true)) 1274 }}, 1275 {want: "e17f81a9", setup: func(i *instruction) { 1276 i.asStorePair64(x1VReg, xzrVReg, addressModePreOrPostIndex(spVReg, 16, true)) 1277 }}, 1278 {want: "ff7f81a9", setup: func(i *instruction) { 1279 i.asStorePair64(xzrVReg, xzrVReg, addressModePreOrPostIndex(spVReg, 16, true)) 1280 }}, 1281 {want: "20000014", setup: func(i *instruction) { 1282 i.asBr(dummyLabel) 1283 i.brOffsetResolve(0x80) 1284 }}, 1285 {want: "01040034", setup: func(i *instruction) { 1286 i.asCondBr(registerAsRegZeroCond(x1VReg), dummyLabel, false) 1287 i.condBrOffsetResolve(0x80) 1288 }}, 1289 {want: "010400b4", setup: func(i *instruction) { 1290 i.asCondBr(registerAsRegZeroCond(x1VReg), dummyLabel, true) 1291 i.condBrOffsetResolve(0x80) 1292 }}, 1293 {want: "01040035", setup: func(i *instruction) { 1294 i.asCondBr(registerAsRegNotZeroCond(x1VReg), dummyLabel, false) 1295 i.condBrOffsetResolve(0x80) 1296 }}, 1297 {want: "010400b5", setup: func(i *instruction) { 1298 i.asCondBr(registerAsRegNotZeroCond(x1VReg), dummyLabel, true) 1299 i.condBrOffsetResolve(0x80) 1300 }}, 1301 {want: "8328321e", setup: func(i *instruction) { 1302 i.asFpuRRR(fpuBinOpAdd, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1303 }}, 1304 {want: "8328721e", setup: func(i *instruction) { 1305 i.asFpuRRR(fpuBinOpAdd, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1306 }}, 1307 {want: "8338321e", setup: func(i *instruction) { 1308 i.asFpuRRR(fpuBinOpSub, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1309 }}, 1310 {want: "8338721e", setup: func(i *instruction) { 1311 i.asFpuRRR(fpuBinOpSub, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1312 }}, 1313 {want: "8308321e", setup: func(i *instruction) { 1314 i.asFpuRRR(fpuBinOpMul, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1315 }}, 1316 {want: "8308721e", setup: func(i *instruction) { 1317 i.asFpuRRR(fpuBinOpMul, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1318 }}, 1319 {want: "8318321e", setup: func(i *instruction) { 1320 i.asFpuRRR(fpuBinOpDiv, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1321 }}, 1322 {want: "8318721e", setup: func(i *instruction) { 1323 i.asFpuRRR(fpuBinOpDiv, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1324 }}, 1325 {want: "8348321e", setup: func(i *instruction) { 1326 i.asFpuRRR(fpuBinOpMax, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1327 }}, 1328 {want: "8348721e", setup: func(i *instruction) { 1329 i.asFpuRRR(fpuBinOpMax, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1330 }}, 1331 {want: "8358321e", setup: func(i *instruction) { 1332 i.asFpuRRR(fpuBinOpMin, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), false) 1333 }}, 1334 {want: "8358721e", setup: func(i *instruction) { 1335 i.asFpuRRR(fpuBinOpMin, operandNR(v3VReg), operandNR(v4VReg), operandNR(v18VReg), true) 1336 }}, 1337 {want: "49fd7f11", setup: func(i *instruction) { 1338 i.asALU(aluOpAdd, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), false) 1339 }}, 1340 {want: "e9ff7f91", setup: func(i *instruction) { 1341 i.asALU(aluOpAdd, operandNR(x9VReg), operandNR(spVReg), operandImm12(0b111111111111, 0b1), true) 1342 }}, 1343 {want: "49fd3f11", setup: func(i *instruction) { 1344 i.asALU(aluOpAdd, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), false) 1345 }}, 1346 {want: "5ffd3f91", setup: func(i *instruction) { 1347 i.asALU(aluOpAdd, operandNR(spVReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), true) 1348 }}, 1349 {want: "49fd7f31", setup: func(i *instruction) { 1350 i.asALU(aluOpAddS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), false) 1351 }}, 1352 {want: "49fd7fb1", setup: func(i *instruction) { 1353 i.asALU(aluOpAddS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), true) 1354 }}, 1355 {want: "49fd3f31", setup: func(i *instruction) { 1356 i.asALU(aluOpAddS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), false) 1357 }}, 1358 {want: "49fd3fb1", setup: func(i *instruction) { 1359 i.asALU(aluOpAddS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), true) 1360 }}, 1361 {want: "49fd7f51", setup: func(i *instruction) { 1362 i.asALU(aluOpSub, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), false) 1363 }}, 1364 {want: "e9ff7fd1", setup: func(i *instruction) { 1365 i.asALU(aluOpSub, operandNR(x9VReg), operandNR(spVReg), operandImm12(0b111111111111, 0b1), true) 1366 }}, 1367 {want: "49fd3f51", setup: func(i *instruction) { 1368 i.asALU(aluOpSub, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), false) 1369 }}, 1370 {want: "5ffd3fd1", setup: func(i *instruction) { 1371 i.asALU(aluOpSub, operandNR(spVReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), true) 1372 }}, 1373 {want: "49fd7f71", setup: func(i *instruction) { 1374 i.asALU(aluOpSubS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), false) 1375 }}, 1376 {want: "49fd7ff1", setup: func(i *instruction) { 1377 i.asALU(aluOpSubS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b1), true) 1378 }}, 1379 {want: "49fd3f71", setup: func(i *instruction) { 1380 i.asALU(aluOpSubS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), false) 1381 }}, 1382 {want: "49fd3ff1", setup: func(i *instruction) { 1383 i.asALU(aluOpSubS, operandNR(x9VReg), operandNR(x10VReg), operandImm12(0b111111111111, 0b0), true) 1384 }}, 1385 {want: "4020d41a", setup: func(i *instruction) { 1386 i.asALU(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1387 }}, 1388 {want: "4020d49a", setup: func(i *instruction) { 1389 i.asALU(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1390 }}, 1391 {want: "4024d41a", setup: func(i *instruction) { 1392 i.asALU(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1393 }}, 1394 {want: "4024d49a", setup: func(i *instruction) { 1395 i.asALU(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1396 }}, 1397 {want: "4028d41a", setup: func(i *instruction) { 1398 i.asALU(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1399 }}, 1400 {want: "4028d49a", setup: func(i *instruction) { 1401 i.asALU(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1402 }}, 1403 {want: "400cd49a", setup: func(i *instruction) { 1404 i.asALU(aluOpSDiv, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1405 }}, 1406 {want: "400cd41a", setup: func(i *instruction) { 1407 i.asALU(aluOpSDiv, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1408 }}, 1409 {want: "4008d49a", setup: func(i *instruction) { 1410 i.asALU(aluOpUDiv, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), true) 1411 }}, 1412 {want: "4008d41a", setup: func(i *instruction) { 1413 i.asALU(aluOpUDiv, operandNR(x0VReg), operandNR(x2VReg), operandNR(x20VReg), false) 1414 }}, 1415 {want: "407c0013", setup: func(i *instruction) { 1416 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(0), false) 1417 }}, 1418 {want: "40fc4093", setup: func(i *instruction) { 1419 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(0), true) 1420 }}, 1421 {want: "407c0113", setup: func(i *instruction) { 1422 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), false) 1423 }}, 1424 {want: "407c1f13", setup: func(i *instruction) { 1425 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), false) 1426 }}, 1427 {want: "40fc4193", setup: func(i *instruction) { 1428 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), true) 1429 }}, 1430 {want: "40fc5f93", setup: func(i *instruction) { 1431 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), true) 1432 }}, 1433 {want: "40fc7f93", setup: func(i *instruction) { 1434 i.asALUShift(aluOpAsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(63), true) 1435 }}, 1436 {want: "407c0153", setup: func(i *instruction) { 1437 i.asALUShift(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), false) 1438 }}, 1439 {want: "407c1f53", setup: func(i *instruction) { 1440 i.asALUShift(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), false) 1441 }}, 1442 {want: "40fc41d3", setup: func(i *instruction) { 1443 i.asALUShift(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), true) 1444 }}, 1445 {want: "40fc5fd3", setup: func(i *instruction) { 1446 i.asALUShift(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), true) 1447 }}, 1448 {want: "40fc7fd3", setup: func(i *instruction) { 1449 i.asALUShift(aluOpLsr, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(63), true) 1450 }}, 1451 {want: "407c0053", setup: func(i *instruction) { 1452 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(0), false) 1453 }}, 1454 {want: "40fc40d3", setup: func(i *instruction) { 1455 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(0), true) 1456 }}, 1457 {want: "40781f53", setup: func(i *instruction) { 1458 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), false) 1459 }}, 1460 {want: "40000153", setup: func(i *instruction) { 1461 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), false) 1462 }}, 1463 {want: "40f87fd3", setup: func(i *instruction) { 1464 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(1), true) 1465 }}, 1466 {want: "408061d3", setup: func(i *instruction) { 1467 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(31), true) 1468 }}, 1469 {want: "400041d3", setup: func(i *instruction) { 1470 i.asALUShift(aluOpLsl, operandNR(x0VReg), operandNR(x2VReg), operandShiftImm(63), true) 1471 }}, 1472 {want: "4000c05a", setup: func(i *instruction) { i.asBitRR(bitOpRbit, x0VReg, x2VReg, false) }}, 1473 {want: "4000c0da", setup: func(i *instruction) { i.asBitRR(bitOpRbit, x0VReg, x2VReg, true) }}, 1474 {want: "4010c05a", setup: func(i *instruction) { i.asBitRR(bitOpClz, x0VReg, x2VReg, false) }}, 1475 {want: "4010c0da", setup: func(i *instruction) { i.asBitRR(bitOpClz, x0VReg, x2VReg, true) }}, 1476 {want: "4138302e", setup: func(i *instruction) { 1477 i.asVecLanes(vecOpUaddlv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 1478 }}, 1479 {want: "4138306e", setup: func(i *instruction) { 1480 i.asVecLanes(vecOpUaddlv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 1481 }}, 1482 {want: "4138702e", setup: func(i *instruction) { 1483 i.asVecLanes(vecOpUaddlv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4H) 1484 }}, 1485 {want: "4138706e", setup: func(i *instruction) { 1486 i.asVecLanes(vecOpUaddlv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8H) 1487 }}, 1488 {want: "4138b06e", setup: func(i *instruction) { 1489 i.asVecLanes(vecOpUaddlv, operandNR(v1VReg), operandNR(v2VReg), vecArrangement4S) 1490 }}, 1491 {want: "411c630e", setup: func(i *instruction) { 1492 i.asVecRRR(vecOpBic, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1493 }}, 1494 {want: "411c634e", setup: func(i *instruction) { 1495 i.asVecRRR(vecOpBic, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1496 }}, 1497 {want: "411c632e", setup: func(i *instruction) { 1498 i.asVecRRRRewrite(vecOpBsl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1499 }}, 1500 {want: "411c636e", setup: func(i *instruction) { 1501 i.asVecRRRRewrite(vecOpBsl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1502 }}, 1503 {want: "4158202e", setup: func(i *instruction) { 1504 i.asVecMisc(vecOpNot, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) 1505 }}, 1506 {want: "4158206e", setup: func(i *instruction) { 1507 i.asVecMisc(vecOpNot, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) 1508 }}, 1509 {want: "411c230e", setup: func(i *instruction) { 1510 i.asVecRRR(vecOpAnd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1511 }}, 1512 {want: "411c234e", setup: func(i *instruction) { 1513 i.asVecRRR(vecOpAnd, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1514 }}, 1515 {want: "411ca30e", setup: func(i *instruction) { 1516 i.asVecRRR(vecOpOrr, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1517 }}, 1518 {want: "411ca34e", setup: func(i *instruction) { 1519 i.asVecRRR(vecOpOrr, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1520 }}, 1521 {want: "4144230e", setup: func(i *instruction) { 1522 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1523 }}, 1524 {want: "4144234e", setup: func(i *instruction) { 1525 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1526 }}, 1527 {want: "4144630e", setup: func(i *instruction) { 1528 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 1529 }}, 1530 {want: "4144634e", setup: func(i *instruction) { 1531 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 1532 }}, 1533 {want: "4144a30e", setup: func(i *instruction) { 1534 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 1535 }}, 1536 {want: "4144e34e", setup: func(i *instruction) { 1537 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 1538 }}, 1539 {want: "4144a30e", setup: func(i *instruction) { 1540 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 1541 }}, 1542 {want: "4144232e", setup: func(i *instruction) { 1543 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8B) 1544 }}, 1545 {want: "4144236e", setup: func(i *instruction) { 1546 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement16B) 1547 }}, 1548 {want: "4144632e", setup: func(i *instruction) { 1549 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement4H) 1550 }}, 1551 {want: "4144636e", setup: func(i *instruction) { 1552 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement8H) 1553 }}, 1554 {want: "4144a32e", setup: func(i *instruction) { 1555 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 1556 }}, 1557 {want: "4144e36e", setup: func(i *instruction) { 1558 i.asVecRRR(vecOpUshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2D) 1559 }}, 1560 {want: "4144a30e", setup: func(i *instruction) { 1561 i.asVecRRR(vecOpSshl, operandNR(v1VReg), operandNR(v2VReg), operandNR(v3VReg), vecArrangement2S) 1562 }}, 1563 {want: "4158200e", setup: func(i *instruction) { i.asVecMisc(vecOpCnt, operandNR(v1VReg), operandNR(v2VReg), vecArrangement8B) }}, 1564 {want: "4158204e", setup: func(i *instruction) { i.asVecMisc(vecOpCnt, operandNR(v1VReg), operandNR(v2VReg), vecArrangement16B) }}, 1565 {want: "41c0221e", setup: func(i *instruction) { 1566 i.asFpuRR(fpuUniOpCvt32To64, operandNR(v1VReg), operandNR(v2VReg), true) 1567 }}, 1568 {want: "4140621e", setup: func(i *instruction) { 1569 i.asFpuRR(fpuUniOpCvt64To32, operandNR(v1VReg), operandNR(v2VReg), true) 1570 }}, 1571 {want: "4140211e", setup: func(i *instruction) { 1572 i.asFpuRR(fpuUniOpNeg, operandNR(v1VReg), operandNR(v2VReg), false) 1573 }}, 1574 1575 {want: "41c0211e", setup: func(i *instruction) { 1576 i.asFpuRR(fpuUniOpSqrt, operandNR(v1VReg), operandNR(v2VReg), false) 1577 }}, 1578 {want: "41c0611e", setup: func(i *instruction) { 1579 i.asFpuRR(fpuUniOpSqrt, operandNR(v1VReg), operandNR(v2VReg), true) 1580 }}, 1581 {want: "41c0241e", setup: func(i *instruction) { 1582 i.asFpuRR(fpuUniOpRoundPlus, operandNR(v1VReg), operandNR(v2VReg), false) 1583 }}, 1584 {want: "41c0641e", setup: func(i *instruction) { 1585 i.asFpuRR(fpuUniOpRoundPlus, operandNR(v1VReg), operandNR(v2VReg), true) 1586 }}, 1587 {want: "4140251e", setup: func(i *instruction) { 1588 i.asFpuRR(fpuUniOpRoundMinus, operandNR(v1VReg), operandNR(v2VReg), false) 1589 }}, 1590 {want: "4140651e", setup: func(i *instruction) { 1591 i.asFpuRR(fpuUniOpRoundMinus, operandNR(v1VReg), operandNR(v2VReg), true) 1592 }}, 1593 {want: "41c0251e", setup: func(i *instruction) { 1594 i.asFpuRR(fpuUniOpRoundZero, operandNR(v1VReg), operandNR(v2VReg), false) 1595 }}, 1596 {want: "41c0651e", setup: func(i *instruction) { 1597 i.asFpuRR(fpuUniOpRoundZero, operandNR(v1VReg), operandNR(v2VReg), true) 1598 }}, 1599 {want: "4140241e", setup: func(i *instruction) { 1600 i.asFpuRR(fpuUniOpRoundNearest, operandNR(v1VReg), operandNR(v2VReg), false) 1601 }}, 1602 {want: "4140641e", setup: func(i *instruction) { 1603 i.asFpuRR(fpuUniOpRoundNearest, operandNR(v1VReg), operandNR(v2VReg), true) 1604 }}, 1605 {want: "4140611e", setup: func(i *instruction) { i.asFpuRR(fpuUniOpNeg, operandNR(v1VReg), operandNR(v2VReg), true) }}, 1606 {want: "41c0404d", setup: func(i *instruction) { i.asVecLoad1R(operandNR(v1VReg), operandNR(x2VReg), vecArrangement16B) }}, 1607 {want: "41c4404d", setup: func(i *instruction) { i.asVecLoad1R(operandNR(v1VReg), operandNR(x2VReg), vecArrangement8H) }}, 1608 {want: "41c8404d", setup: func(i *instruction) { i.asVecLoad1R(operandNR(v1VReg), operandNR(x2VReg), vecArrangement4S) }}, 1609 {want: "41cc404d", setup: func(i *instruction) { i.asVecLoad1R(operandNR(v1VReg), operandNR(x2VReg), vecArrangement2D) }}, 1610 {want: "4201231e4201631e4201239e4201639e4201221e4201621e4201229e4201629e", setup: func(i *instruction) { 1611 i.asNop0() 1612 cur := i 1613 trueFalse := []bool{false, true} 1614 for _, rnSigned := range trueFalse { 1615 for _, src64bit := range trueFalse { 1616 for _, dst64bit := range trueFalse { 1617 i := &instruction{prev: cur} 1618 cur.next = i 1619 i.asIntToFpu(operandNR(v2VReg), operandNR(x10VReg), rnSigned, src64bit, dst64bit) 1620 cur = i 1621 } 1622 } 1623 } 1624 }}, 1625 {want: "4201391e4201399e4201791e4201799e4201381e4201389e4201781e4201789e", setup: func(i *instruction) { 1626 i.asNop0() 1627 cur := i 1628 trueFalse := []bool{false, true} 1629 for _, rnSigned := range trueFalse { 1630 for _, src64bit := range trueFalse { 1631 for _, dst64bit := range trueFalse { 1632 i := &instruction{prev: cur} 1633 cur.next = i 1634 i.asFpuToInt(operandNR(v2VReg), operandNR(x10VReg), rnSigned, src64bit, dst64bit) 1635 cur = i 1636 } 1637 } 1638 } 1639 }}, 1640 } { 1641 tc := tc 1642 t.Run(tc.want, func(t *testing.T) { 1643 i := &instruction{} 1644 tc.setup(i) 1645 1646 mc := &mockCompiler{} 1647 m := &machine{compiler: mc} 1648 m.encode(i) 1649 // Note: for quick iteration we can use golang.org/x/arch package to verify the encoding. 1650 // but wazero doesn't add even a test dependency to it, so commented out. 1651 // inst, err := arm64asm.Decode(m.buf) 1652 // require.NoError(t, err, hex.EncodeToString(m.buf)) 1653 // fmt.Println(inst.String()) 1654 require.Equal(t, tc.want, hex.EncodeToString(mc.buf)) 1655 1656 var actualSize int 1657 for cur := i; cur != nil; cur = cur.next { 1658 actualSize += int(cur.size()) 1659 } 1660 require.Equal(t, len(tc.want)/2, actualSize) 1661 }) 1662 } 1663 } 1664 1665 func TestInstruction_encode_call(t *testing.T) { 1666 m := &mockCompiler{buf: make([]byte, 128)} 1667 i := &instruction{} 1668 i.asCall(ssa.FuncRef(555), nil) 1669 i.encode(m) 1670 buf := m.buf[128:] 1671 require.Equal(t, "00000094", hex.EncodeToString(buf)) 1672 require.Equal(t, 1, len(m.relocs)) 1673 require.Equal(t, ssa.FuncRef(555), m.relocs[0].FuncRef) 1674 require.Equal(t, int64(128), m.relocs[0].Offset) 1675 } 1676 1677 func TestInstruction_encode_br_condflag(t *testing.T) { 1678 for _, tc := range []struct { 1679 c condFlag 1680 want string 1681 }{ 1682 {c: eq, want: "80070054"}, 1683 {c: ne, want: "81070054"}, 1684 {c: hs, want: "82070054"}, 1685 {c: lo, want: "83070054"}, 1686 {c: mi, want: "84070054"}, 1687 {c: pl, want: "85070054"}, 1688 {c: vs, want: "86070054"}, 1689 {c: vc, want: "87070054"}, 1690 {c: hi, want: "88070054"}, 1691 {c: ls, want: "89070054"}, 1692 {c: ge, want: "8a070054"}, 1693 {c: lt, want: "8b070054"}, 1694 {c: gt, want: "8c070054"}, 1695 {c: le, want: "8d070054"}, 1696 {c: al, want: "8e070054"}, 1697 {c: nv, want: "8f070054"}, 1698 } { 1699 i := &instruction{} 1700 i.asCondBr(tc.c.asCond(), label(1), false) 1701 i.condBrOffsetResolve(0xf0) 1702 m := &mockCompiler{} 1703 i.encode(m) 1704 // Note: for quick iteration we can use golang.org/x/arch package to verify the encoding. 1705 // but wazero doesn't add even a test dependency to it, so commented out. 1706 // inst, err := arm64asm.Decode(m.buf) 1707 // require.NoError(t, err) 1708 // fmt.Println(inst.String()) 1709 require.Equal(t, tc.want, hex.EncodeToString(m.buf)) 1710 } 1711 } 1712 1713 func TestInstruction_encoding_store_encoding(t *testing.T) { 1714 amodeRegScaledExtended1 := addressMode{kind: addressModeKindRegScaledExtended, rn: x30VReg, rm: x1VReg, extOp: extendOpUXTW} 1715 amodeRegScaledExtended2 := addressMode{kind: addressModeKindRegScaledExtended, rn: spVReg, rm: x1VReg, extOp: extendOpSXTW} 1716 amodeRegScaled1 := addressMode{kind: addressModeKindRegScaled, rn: x30VReg, rm: x1VReg} 1717 amodeRegScaled2 := addressMode{kind: addressModeKindRegScaled, rn: spVReg, rm: x1VReg} 1718 amodeRegExtended1 := addressMode{kind: addressModeKindRegExtended, rn: x30VReg, rm: x1VReg, extOp: extendOpUXTW} 1719 amodeRegExtended2 := addressMode{kind: addressModeKindRegExtended, rn: spVReg, rm: x1VReg, extOp: extendOpSXTW} 1720 amodeRegReg1 := addressMode{kind: addressModeKindRegReg, rn: x30VReg, rm: x1VReg} 1721 amodeRegReg2 := addressMode{kind: addressModeKindRegReg, rn: spVReg, rm: x1VReg} 1722 amodeRegSignedImm9_1 := addressMode{kind: addressModeKindRegSignedImm9, rn: x30VReg, imm: 10} 1723 amodeRegSignedImm9_2 := addressMode{kind: addressModeKindRegSignedImm9, rn: spVReg, imm: 0b111111111} 1724 amodePostIndex1 := addressMode{kind: addressModeKindPostIndex, rn: x30VReg, imm: 10} 1725 amodePostIndex2 := addressMode{kind: addressModeKindPostIndex, rn: spVReg, imm: 0b100000000} 1726 amodePreIndex1 := addressMode{kind: addressModeKindPreIndex, rn: x30VReg, imm: 10} 1727 amodePreIndex2 := addressMode{kind: addressModeKindPreIndex, rn: spVReg, imm: 0b100000000} 1728 amodeUnsignedImm12_1 := addressMode{kind: addressModeKindRegUnsignedImm12, rn: x30VReg} 1729 amodeUnsignedImm12_2 := addressMode{kind: addressModeKindRegUnsignedImm12, rn: spVReg} 1730 setImm := func(amode addressMode, imm int64) addressMode { 1731 amode.imm = imm 1732 return amode 1733 } 1734 for _, tc := range []struct { 1735 k instructionKind 1736 amode addressMode 1737 rn regalloc.VReg 1738 want string 1739 }{ 1740 // addressModeKindRegScaledExtended. 1741 {k: store8, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b2138"}, 1742 {k: store8, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db2138"}, 1743 {k: store16, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b2178"}, 1744 {k: store16, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db2178"}, 1745 {k: store32, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b21b8"}, 1746 {k: store32, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db21b8"}, 1747 {k: store64, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b21f8"}, 1748 {k: store64, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db21f8"}, 1749 {k: fpuStore32, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55b21bc"}, 1750 {k: fpuStore32, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5db21bc"}, 1751 {k: fpuStore64, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55b21fc"}, 1752 {k: fpuStore64, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5db21fc"}, 1753 {k: fpuStore128, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55ba13c"}, 1754 {k: fpuStore128, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5dba13c"}, 1755 {k: uLoad8, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b6138"}, 1756 {k: uLoad8, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db6138"}, 1757 {k: uLoad16, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b6178"}, 1758 {k: uLoad16, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db6178"}, 1759 {k: uLoad32, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b61b8"}, 1760 {k: uLoad32, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db61b8"}, 1761 {k: uLoad64, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55b61f8"}, 1762 {k: uLoad64, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5db61f8"}, 1763 {k: sLoad8, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55ba138"}, 1764 {k: sLoad8, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5dba138"}, 1765 {k: sLoad16, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55ba178"}, 1766 {k: sLoad16, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5dba178"}, 1767 {k: sLoad32, amode: amodeRegScaledExtended1, rn: x5VReg, want: "c55ba1b8"}, 1768 {k: sLoad32, amode: amodeRegScaledExtended2, rn: x5VReg, want: "e5dba1b8"}, 1769 {k: fpuLoad32, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55b61bc"}, 1770 {k: fpuLoad32, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5db61bc"}, 1771 {k: fpuLoad64, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55b61fc"}, 1772 {k: fpuLoad64, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5db61fc"}, 1773 {k: fpuLoad128, amode: amodeRegScaledExtended1, rn: v5VReg, want: "c55be13c"}, 1774 {k: fpuLoad128, amode: amodeRegScaledExtended2, rn: v5VReg, want: "e5dbe13c"}, 1775 // addressModeKindRegScaled. 1776 {k: store8, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb2138"}, 1777 {k: store8, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb2138"}, 1778 {k: store16, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb2178"}, 1779 {k: store16, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb2178"}, 1780 {k: store32, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb21b8"}, 1781 {k: store32, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb21b8"}, 1782 {k: store64, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb21f8"}, 1783 {k: store64, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb21f8"}, 1784 {k: fpuStore32, amode: amodeRegScaled1, rn: v5VReg, want: "c5fb21bc"}, 1785 {k: fpuStore32, amode: amodeRegScaled2, rn: v5VReg, want: "e5fb21bc"}, 1786 {k: fpuStore64, amode: amodeRegScaled1, rn: v5VReg, want: "c5fb21fc"}, 1787 {k: fpuStore64, amode: amodeRegScaled2, rn: v5VReg, want: "e5fb21fc"}, 1788 {k: fpuStore128, amode: amodeRegScaled1, rn: v5VReg, want: "c5fba13c"}, 1789 {k: fpuStore128, amode: amodeRegScaled2, rn: v5VReg, want: "e5fba13c"}, 1790 {k: uLoad8, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb6138"}, 1791 {k: uLoad8, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb6138"}, 1792 {k: uLoad16, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb6178"}, 1793 {k: uLoad16, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb6178"}, 1794 {k: uLoad32, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb61b8"}, 1795 {k: uLoad32, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb61b8"}, 1796 {k: uLoad64, amode: amodeRegScaled1, rn: x5VReg, want: "c5fb61f8"}, 1797 {k: uLoad64, amode: amodeRegScaled2, rn: x5VReg, want: "e5fb61f8"}, 1798 {k: sLoad8, amode: amodeRegScaled1, rn: x5VReg, want: "c5fba138"}, 1799 {k: sLoad8, amode: amodeRegScaled2, rn: x5VReg, want: "e5fba138"}, 1800 {k: sLoad16, amode: amodeRegScaled1, rn: x5VReg, want: "c5fba178"}, 1801 {k: sLoad16, amode: amodeRegScaled2, rn: x5VReg, want: "e5fba178"}, 1802 {k: sLoad32, amode: amodeRegScaled1, rn: x5VReg, want: "c5fba1b8"}, 1803 {k: sLoad32, amode: amodeRegScaled2, rn: x5VReg, want: "e5fba1b8"}, 1804 {k: fpuLoad32, amode: amodeRegScaled1, rn: v5VReg, want: "c5fb61bc"}, 1805 {k: fpuLoad32, amode: amodeRegScaled2, rn: v5VReg, want: "e5fb61bc"}, 1806 {k: fpuLoad64, amode: amodeRegScaled1, rn: v5VReg, want: "c5fb61fc"}, 1807 {k: fpuLoad64, amode: amodeRegScaled2, rn: v5VReg, want: "e5fb61fc"}, 1808 {k: fpuLoad128, amode: amodeRegScaled1, rn: v5VReg, want: "c5fbe13c"}, 1809 {k: fpuLoad128, amode: amodeRegScaled2, rn: v5VReg, want: "e5fbe13c"}, 1810 // addressModeKindRegExtended. 1811 {k: store8, amode: amodeRegExtended1, rn: x5VReg, want: "c54b2138"}, 1812 {k: store8, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb2138"}, 1813 {k: store16, amode: amodeRegExtended1, rn: x5VReg, want: "c54b2178"}, 1814 {k: store16, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb2178"}, 1815 {k: store32, amode: amodeRegExtended1, rn: x5VReg, want: "c54b21b8"}, 1816 {k: store32, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb21b8"}, 1817 {k: store64, amode: amodeRegExtended1, rn: x5VReg, want: "c54b21f8"}, 1818 {k: store64, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb21f8"}, 1819 {k: fpuStore32, amode: amodeRegExtended1, rn: v5VReg, want: "c54b21bc"}, 1820 {k: fpuStore32, amode: amodeRegExtended2, rn: v5VReg, want: "e5cb21bc"}, 1821 {k: fpuStore64, amode: amodeRegExtended1, rn: v5VReg, want: "c54b21fc"}, 1822 {k: fpuStore64, amode: amodeRegExtended2, rn: v5VReg, want: "e5cb21fc"}, 1823 {k: fpuStore128, amode: amodeRegExtended1, rn: v5VReg, want: "c54ba13c"}, 1824 {k: fpuStore128, amode: amodeRegExtended2, rn: v5VReg, want: "e5cba13c"}, 1825 {k: uLoad8, amode: amodeRegExtended1, rn: x5VReg, want: "c54b6138"}, 1826 {k: uLoad8, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb6138"}, 1827 {k: uLoad16, amode: amodeRegExtended1, rn: x5VReg, want: "c54b6178"}, 1828 {k: uLoad16, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb6178"}, 1829 {k: uLoad32, amode: amodeRegExtended1, rn: x5VReg, want: "c54b61b8"}, 1830 {k: uLoad32, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb61b8"}, 1831 {k: uLoad64, amode: amodeRegExtended1, rn: x5VReg, want: "c54b61f8"}, 1832 {k: uLoad64, amode: amodeRegExtended2, rn: x5VReg, want: "e5cb61f8"}, 1833 {k: sLoad8, amode: amodeRegExtended1, rn: x5VReg, want: "c54ba138"}, 1834 {k: sLoad8, amode: amodeRegExtended2, rn: x5VReg, want: "e5cba138"}, 1835 {k: sLoad16, amode: amodeRegExtended1, rn: x5VReg, want: "c54ba178"}, 1836 {k: sLoad16, amode: amodeRegExtended2, rn: x5VReg, want: "e5cba178"}, 1837 {k: sLoad32, amode: amodeRegExtended1, rn: x5VReg, want: "c54ba1b8"}, 1838 {k: sLoad32, amode: amodeRegExtended2, rn: x5VReg, want: "e5cba1b8"}, 1839 {k: fpuLoad32, amode: amodeRegExtended1, rn: v5VReg, want: "c54b61bc"}, 1840 {k: fpuLoad32, amode: amodeRegExtended2, rn: v5VReg, want: "e5cb61bc"}, 1841 {k: fpuLoad64, amode: amodeRegExtended1, rn: v5VReg, want: "c54b61fc"}, 1842 {k: fpuLoad64, amode: amodeRegExtended2, rn: v5VReg, want: "e5cb61fc"}, 1843 {k: fpuLoad128, amode: amodeRegExtended1, rn: v5VReg, want: "c54be13c"}, 1844 {k: fpuLoad128, amode: amodeRegExtended2, rn: v5VReg, want: "e5cbe13c"}, 1845 // addressModeKindRegReg. 1846 {k: store8, amode: amodeRegReg1, rn: x5VReg, want: "c5eb2138"}, 1847 {k: store8, amode: amodeRegReg2, rn: x5VReg, want: "e5eb2138"}, 1848 {k: store16, amode: amodeRegReg1, rn: x5VReg, want: "c5eb2178"}, 1849 {k: store16, amode: amodeRegReg2, rn: x5VReg, want: "e5eb2178"}, 1850 {k: store32, amode: amodeRegReg1, rn: x5VReg, want: "c5eb21b8"}, 1851 {k: store32, amode: amodeRegReg2, rn: x5VReg, want: "e5eb21b8"}, 1852 {k: store64, amode: amodeRegReg1, rn: x5VReg, want: "c5eb21f8"}, 1853 {k: store64, amode: amodeRegReg2, rn: x5VReg, want: "e5eb21f8"}, 1854 {k: fpuStore32, amode: amodeRegReg1, rn: v5VReg, want: "c5eb21bc"}, 1855 {k: fpuStore32, amode: amodeRegReg2, rn: v5VReg, want: "e5eb21bc"}, 1856 {k: fpuStore64, amode: amodeRegReg1, rn: v5VReg, want: "c5eb21fc"}, 1857 {k: fpuStore64, amode: amodeRegReg2, rn: v5VReg, want: "e5eb21fc"}, 1858 {k: fpuStore128, amode: amodeRegReg1, rn: v5VReg, want: "c5eba13c"}, 1859 {k: fpuStore128, amode: amodeRegReg2, rn: v5VReg, want: "e5eba13c"}, 1860 {k: uLoad8, amode: amodeRegReg1, rn: x5VReg, want: "c5eb6138"}, 1861 {k: uLoad8, amode: amodeRegReg2, rn: x5VReg, want: "e5eb6138"}, 1862 {k: uLoad16, amode: amodeRegReg1, rn: x5VReg, want: "c5eb6178"}, 1863 {k: uLoad16, amode: amodeRegReg2, rn: x5VReg, want: "e5eb6178"}, 1864 {k: uLoad32, amode: amodeRegReg1, rn: x5VReg, want: "c5eb61b8"}, 1865 {k: uLoad32, amode: amodeRegReg2, rn: x5VReg, want: "e5eb61b8"}, 1866 {k: uLoad64, amode: amodeRegReg1, rn: x5VReg, want: "c5eb61f8"}, 1867 {k: uLoad64, amode: amodeRegReg2, rn: x5VReg, want: "e5eb61f8"}, 1868 {k: sLoad8, amode: amodeRegReg1, rn: x5VReg, want: "c5eba138"}, 1869 {k: sLoad8, amode: amodeRegReg2, rn: x5VReg, want: "e5eba138"}, 1870 {k: sLoad16, amode: amodeRegReg1, rn: x5VReg, want: "c5eba178"}, 1871 {k: sLoad16, amode: amodeRegReg2, rn: x5VReg, want: "e5eba178"}, 1872 {k: sLoad32, amode: amodeRegReg1, rn: x5VReg, want: "c5eba1b8"}, 1873 {k: sLoad32, amode: amodeRegReg2, rn: x5VReg, want: "e5eba1b8"}, 1874 {k: fpuLoad32, amode: amodeRegReg1, rn: v5VReg, want: "c5eb61bc"}, 1875 {k: fpuLoad32, amode: amodeRegReg2, rn: v5VReg, want: "e5eb61bc"}, 1876 {k: fpuLoad64, amode: amodeRegReg1, rn: v5VReg, want: "c5eb61fc"}, 1877 {k: fpuLoad64, amode: amodeRegReg2, rn: v5VReg, want: "e5eb61fc"}, 1878 {k: fpuLoad128, amode: amodeRegReg1, rn: v5VReg, want: "c5ebe13c"}, 1879 {k: fpuLoad128, amode: amodeRegReg2, rn: v5VReg, want: "e5ebe13c"}, 1880 // addressModeKindRegSignedImm9. 1881 {k: store8, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a30038"}, 1882 {k: store8, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f31f38"}, 1883 {k: store16, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a30078"}, 1884 {k: store16, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f31f78"}, 1885 {k: store32, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a300b8"}, 1886 {k: store32, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f31fb8"}, 1887 {k: store64, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a300f8"}, 1888 {k: store64, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f31ff8"}, 1889 {k: fpuStore32, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a300bc"}, 1890 {k: fpuStore32, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f31fbc"}, 1891 {k: fpuStore64, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a300fc"}, 1892 {k: fpuStore64, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f31ffc"}, 1893 {k: fpuStore128, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a3803c"}, 1894 {k: fpuStore128, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f39f3c"}, 1895 {k: uLoad8, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a34038"}, 1896 {k: uLoad8, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f35f38"}, 1897 {k: uLoad16, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a34078"}, 1898 {k: uLoad16, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f35f78"}, 1899 {k: uLoad32, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a340b8"}, 1900 {k: uLoad32, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f35fb8"}, 1901 {k: uLoad64, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a340f8"}, 1902 {k: uLoad64, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f35ff8"}, 1903 {k: sLoad8, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a38038"}, 1904 {k: sLoad8, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f39f38"}, 1905 {k: sLoad16, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a38078"}, 1906 {k: sLoad16, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f39f78"}, 1907 {k: sLoad32, amode: amodeRegSignedImm9_1, rn: x5VReg, want: "c5a380b8"}, 1908 {k: sLoad32, amode: amodeRegSignedImm9_2, rn: x5VReg, want: "e5f39fb8"}, 1909 {k: fpuLoad32, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a340bc"}, 1910 {k: fpuLoad32, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f35fbc"}, 1911 {k: fpuLoad64, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a340fc"}, 1912 {k: fpuLoad64, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f35ffc"}, 1913 {k: fpuLoad128, amode: amodeRegSignedImm9_1, rn: v5VReg, want: "c5a3c03c"}, 1914 {k: fpuLoad128, amode: amodeRegSignedImm9_2, rn: v5VReg, want: "e5f3df3c"}, 1915 // addressModeKindPostIndex. 1916 {k: store8, amode: amodePostIndex1, rn: x5VReg, want: "c5a70038"}, 1917 {k: store8, amode: amodePostIndex2, rn: x5VReg, want: "e5071038"}, 1918 {k: store16, amode: amodePostIndex1, rn: x5VReg, want: "c5a70078"}, 1919 {k: store16, amode: amodePostIndex2, rn: x5VReg, want: "e5071078"}, 1920 {k: store32, amode: amodePostIndex1, rn: x5VReg, want: "c5a700b8"}, 1921 {k: store32, amode: amodePostIndex2, rn: x5VReg, want: "e50710b8"}, 1922 {k: store64, amode: amodePostIndex1, rn: x5VReg, want: "c5a700f8"}, 1923 {k: store64, amode: amodePostIndex2, rn: x5VReg, want: "e50710f8"}, 1924 {k: fpuStore32, amode: amodePostIndex1, rn: v5VReg, want: "c5a700bc"}, 1925 {k: fpuStore32, amode: amodePostIndex2, rn: v5VReg, want: "e50710bc"}, 1926 {k: fpuStore64, amode: amodePostIndex1, rn: v5VReg, want: "c5a700fc"}, 1927 {k: fpuStore64, amode: amodePostIndex2, rn: v5VReg, want: "e50710fc"}, 1928 {k: fpuStore128, amode: amodePostIndex1, rn: v5VReg, want: "c5a7803c"}, 1929 {k: fpuStore128, amode: amodePostIndex2, rn: v5VReg, want: "e507903c"}, 1930 {k: uLoad8, amode: amodePostIndex1, rn: x5VReg, want: "c5a74038"}, 1931 {k: uLoad8, amode: amodePostIndex2, rn: x5VReg, want: "e5075038"}, 1932 {k: uLoad16, amode: amodePostIndex1, rn: x5VReg, want: "c5a74078"}, 1933 {k: uLoad16, amode: amodePostIndex2, rn: x5VReg, want: "e5075078"}, 1934 {k: uLoad32, amode: amodePostIndex1, rn: x5VReg, want: "c5a740b8"}, 1935 {k: uLoad32, amode: amodePostIndex2, rn: x5VReg, want: "e50750b8"}, 1936 {k: uLoad64, amode: amodePostIndex1, rn: x5VReg, want: "c5a740f8"}, 1937 {k: uLoad64, amode: amodePostIndex2, rn: x5VReg, want: "e50750f8"}, 1938 {k: sLoad8, amode: amodePostIndex1, rn: x5VReg, want: "c5a78038"}, 1939 {k: sLoad8, amode: amodePostIndex2, rn: x5VReg, want: "e5079038"}, 1940 {k: sLoad16, amode: amodePostIndex1, rn: x5VReg, want: "c5a78078"}, 1941 {k: sLoad16, amode: amodePostIndex2, rn: x5VReg, want: "e5079078"}, 1942 {k: sLoad32, amode: amodePostIndex1, rn: x5VReg, want: "c5a780b8"}, 1943 {k: sLoad32, amode: amodePostIndex2, rn: x5VReg, want: "e50790b8"}, 1944 {k: fpuLoad32, amode: amodePostIndex1, rn: v5VReg, want: "c5a740bc"}, 1945 {k: fpuLoad32, amode: amodePostIndex2, rn: v5VReg, want: "e50750bc"}, 1946 {k: fpuLoad64, amode: amodePostIndex1, rn: v5VReg, want: "c5a740fc"}, 1947 {k: fpuLoad64, amode: amodePostIndex2, rn: v5VReg, want: "e50750fc"}, 1948 {k: fpuLoad128, amode: amodePostIndex1, rn: v5VReg, want: "c5a7c03c"}, 1949 {k: fpuLoad128, amode: amodePostIndex2, rn: v5VReg, want: "e507d03c"}, 1950 // addressModeKindPreIndex. 1951 {k: store8, amode: amodePreIndex1, rn: x5VReg, want: "c5af0038"}, 1952 {k: store8, amode: amodePreIndex2, rn: x5VReg, want: "e50f1038"}, 1953 {k: store16, amode: amodePreIndex1, rn: x5VReg, want: "c5af0078"}, 1954 {k: store16, amode: amodePreIndex2, rn: x5VReg, want: "e50f1078"}, 1955 {k: store32, amode: amodePreIndex1, rn: x5VReg, want: "c5af00b8"}, 1956 {k: store32, amode: amodePreIndex2, rn: x5VReg, want: "e50f10b8"}, 1957 {k: store64, amode: amodePreIndex1, rn: x5VReg, want: "c5af00f8"}, 1958 {k: store64, amode: amodePreIndex2, rn: x5VReg, want: "e50f10f8"}, 1959 {k: store64, amode: amodePreIndex2, rn: xzrVReg, want: "ff0f10f8"}, 1960 {k: fpuStore32, amode: amodePreIndex1, rn: v5VReg, want: "c5af00bc"}, 1961 {k: fpuStore32, amode: amodePreIndex2, rn: v5VReg, want: "e50f10bc"}, 1962 {k: fpuStore64, amode: amodePreIndex1, rn: v5VReg, want: "c5af00fc"}, 1963 {k: fpuStore64, amode: amodePreIndex2, rn: v5VReg, want: "e50f10fc"}, 1964 {k: fpuStore128, amode: amodePreIndex1, rn: v5VReg, want: "c5af803c"}, 1965 {k: fpuStore128, amode: amodePreIndex2, rn: v5VReg, want: "e50f903c"}, 1966 {k: uLoad8, amode: amodePreIndex1, rn: x5VReg, want: "c5af4038"}, 1967 {k: uLoad8, amode: amodePreIndex2, rn: x5VReg, want: "e50f5038"}, 1968 {k: uLoad16, amode: amodePreIndex1, rn: x5VReg, want: "c5af4078"}, 1969 {k: uLoad16, amode: amodePreIndex2, rn: x5VReg, want: "e50f5078"}, 1970 {k: uLoad32, amode: amodePreIndex1, rn: x5VReg, want: "c5af40b8"}, 1971 {k: uLoad32, amode: amodePreIndex2, rn: x5VReg, want: "e50f50b8"}, 1972 {k: uLoad64, amode: amodePreIndex1, rn: x5VReg, want: "c5af40f8"}, 1973 {k: uLoad64, amode: amodePreIndex2, rn: x5VReg, want: "e50f50f8"}, 1974 {k: sLoad8, amode: amodePreIndex1, rn: x5VReg, want: "c5af8038"}, 1975 {k: sLoad8, amode: amodePreIndex2, rn: x5VReg, want: "e50f9038"}, 1976 {k: sLoad16, amode: amodePreIndex1, rn: x5VReg, want: "c5af8078"}, 1977 {k: sLoad16, amode: amodePreIndex2, rn: x5VReg, want: "e50f9078"}, 1978 {k: sLoad32, amode: amodePreIndex1, rn: x5VReg, want: "c5af80b8"}, 1979 {k: sLoad32, amode: amodePreIndex2, rn: x5VReg, want: "e50f90b8"}, 1980 {k: fpuLoad32, amode: amodePreIndex1, rn: v5VReg, want: "c5af40bc"}, 1981 {k: fpuLoad32, amode: amodePreIndex2, rn: v5VReg, want: "e50f50bc"}, 1982 {k: fpuLoad64, amode: amodePreIndex1, rn: v5VReg, want: "c5af40fc"}, 1983 {k: fpuLoad64, amode: amodePreIndex2, rn: v5VReg, want: "e50f50fc"}, 1984 {k: fpuLoad128, amode: amodePreIndex1, rn: v5VReg, want: "c5afc03c"}, 1985 {k: fpuLoad128, amode: amodePreIndex2, rn: v5VReg, want: "e50fd03c"}, 1986 // addressModeKindRegUnsignedImm12. 1987 {k: store8, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c52b0039"}, 1988 {k: store8, amode: setImm(amodeUnsignedImm12_2, 4095), rn: x5VReg, want: "e5ff3f39"}, 1989 {k: store16, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c5170079"}, 1990 {k: store16, amode: setImm(amodeUnsignedImm12_2, 4095*2), rn: x5VReg, want: "e5ff3f79"}, 1991 {k: store32, amode: setImm(amodeUnsignedImm12_1, 16), rn: x5VReg, want: "c51300b9"}, 1992 {k: store32, amode: setImm(amodeUnsignedImm12_2, 4095*4), rn: x5VReg, want: "e5ff3fb9"}, 1993 {k: store64, amode: setImm(amodeUnsignedImm12_1, 16), rn: x5VReg, want: "c50b00f9"}, 1994 {k: store64, amode: setImm(amodeUnsignedImm12_2, 4095*8), rn: x5VReg, want: "e5ff3ff9"}, 1995 {k: fpuStore32, amode: setImm(amodeUnsignedImm12_1, 256), rn: v5VReg, want: "c50301bd"}, 1996 {k: fpuStore32, amode: setImm(amodeUnsignedImm12_2, 4095*4), rn: v5VReg, want: "e5ff3fbd"}, 1997 {k: fpuStore64, amode: setImm(amodeUnsignedImm12_1, 512), rn: v5VReg, want: "c50301fd"}, 1998 {k: fpuStore64, amode: setImm(amodeUnsignedImm12_2, 4095*8), rn: v5VReg, want: "e5ff3ffd"}, 1999 {k: fpuStore128, amode: setImm(amodeUnsignedImm12_1, 16), rn: v5VReg, want: "c507803d"}, 2000 {k: fpuStore128, amode: setImm(amodeUnsignedImm12_2, 4095*16), rn: v5VReg, want: "e5ffbf3d"}, 2001 {k: uLoad8, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c52b4039"}, 2002 {k: uLoad8, amode: setImm(amodeUnsignedImm12_2, 4095), rn: x5VReg, want: "e5ff7f39"}, 2003 {k: uLoad16, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c5174079"}, 2004 {k: uLoad16, amode: setImm(amodeUnsignedImm12_2, 4095*2), rn: x5VReg, want: "e5ff7f79"}, 2005 {k: uLoad32, amode: setImm(amodeUnsignedImm12_1, 16), rn: x5VReg, want: "c51340b9"}, 2006 {k: uLoad32, amode: setImm(amodeUnsignedImm12_2, 4095*4), rn: x5VReg, want: "e5ff7fb9"}, 2007 {k: uLoad64, amode: setImm(amodeUnsignedImm12_1, 16), rn: x5VReg, want: "c50b40f9"}, 2008 {k: uLoad64, amode: setImm(amodeUnsignedImm12_2, 4095*8), rn: x5VReg, want: "e5ff7ff9"}, 2009 {k: sLoad8, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c52b8039"}, 2010 {k: sLoad8, amode: setImm(amodeUnsignedImm12_2, 4095), rn: x5VReg, want: "e5ffbf39"}, 2011 {k: sLoad16, amode: setImm(amodeUnsignedImm12_1, 10), rn: x5VReg, want: "c5178079"}, 2012 {k: sLoad16, amode: setImm(amodeUnsignedImm12_2, 4095*2), rn: x5VReg, want: "e5ffbf79"}, 2013 {k: sLoad32, amode: setImm(amodeUnsignedImm12_1, 16), rn: x5VReg, want: "c51380b9"}, 2014 {k: sLoad32, amode: setImm(amodeUnsignedImm12_2, 4095*4), rn: x5VReg, want: "e5ffbfb9"}, 2015 {k: fpuLoad32, amode: setImm(amodeUnsignedImm12_1, 256), rn: v5VReg, want: "c50341bd"}, 2016 {k: fpuLoad32, amode: setImm(amodeUnsignedImm12_2, 4095*4), rn: v5VReg, want: "e5ff7fbd"}, 2017 {k: fpuLoad64, amode: setImm(amodeUnsignedImm12_1, 512), rn: v5VReg, want: "c50341fd"}, 2018 {k: fpuLoad64, amode: setImm(amodeUnsignedImm12_2, 4095*8), rn: v5VReg, want: "e5ff7ffd"}, 2019 {k: fpuLoad128, amode: setImm(amodeUnsignedImm12_1, 16), rn: v5VReg, want: "c507c03d"}, 2020 {k: fpuLoad128, amode: setImm(amodeUnsignedImm12_2, 4095*16), rn: v5VReg, want: "e5ffff3d"}, 2021 } { 2022 t.Run(tc.want, func(t *testing.T) { 2023 var i *instruction 2024 switch tc.k { 2025 case store8, store16, store32, store64, fpuStore32, fpuStore64, fpuStore128: 2026 i = &instruction{kind: tc.k, amode: tc.amode, rn: operandNR(tc.rn)} 2027 case uLoad8, uLoad16, uLoad32, uLoad64, sLoad8, sLoad16, sLoad32, fpuLoad32, fpuLoad64, fpuLoad128: 2028 i = &instruction{kind: tc.k, amode: tc.amode, rd: operandNR(tc.rn)} 2029 default: 2030 t.Fatalf("unknown kind: %v", tc.k) 2031 } 2032 m := &mockCompiler{} 2033 i.encode(m) 2034 // Note: for quick iteration we can use golang.org/x/arch package to verify the encoding. 2035 // but wazero doesn't add even a test dependency to it, so commented out. 2036 // inst, err := arm64asm.Decode(m.buf) 2037 // require.NoError(t, err) 2038 // fmt.Println(inst.String()) 2039 require.Equal(t, tc.want, hex.EncodeToString(m.buf)) 2040 }) 2041 } 2042 } 2043 2044 func Test_encodeExitSequence(t *testing.T) { 2045 t.Run("no overlap", func(t *testing.T) { 2046 m := &mockCompiler{} 2047 encodeExitSequence(m, x22VReg) 2048 // ldr x29, [x22, #0x10] 2049 // ldr x30, [x22, #0x20] 2050 // ldr x27, [x22, #0x18] 2051 // mov sp, x27 2052 // ret 2053 // b #0x14 ;; dummy 2054 require.Equal(t, "dd0a40f9de1240f9db0e40f97f030091c0035fd600000014", hex.EncodeToString(m.buf)) 2055 require.Equal(t, len(m.buf), exitSequenceSize) 2056 }) 2057 t.Run("fp", func(t *testing.T) { 2058 m := &mockCompiler{} 2059 encodeExitSequence(m, fpVReg) 2060 // mov x27, x29 2061 // ldr x29, [x27, #0x10] 2062 // ldr x30, [x27, #0x20] 2063 // ldr x27, [x27, #0x18] 2064 // mov sp, x27 2065 // ret 2066 require.Equal(t, "fb031daa7d0b40f97e1340f97b0f40f97f030091c0035fd6", hex.EncodeToString(m.buf)) 2067 require.Equal(t, len(m.buf), exitSequenceSize) 2068 }) 2069 t.Run("lr", func(t *testing.T) { 2070 m := &mockCompiler{} 2071 encodeExitSequence(m, lrVReg) 2072 // mov x27, x30 2073 // ldr x29, [x27, #0x10] 2074 // ldr x30, [x27, #0x20] 2075 // ldr x27, [x27, #0x18] 2076 // mov sp, x27 2077 // ret 2078 require.Equal(t, "fb031eaa7d0b40f97e1340f97b0f40f97f030091c0035fd6", hex.EncodeToString(m.buf)) 2079 require.Equal(t, len(m.buf), exitSequenceSize) 2080 }) 2081 } 2082 2083 func Test_encodeBrTableSequence(t *testing.T) { 2084 m := &mockCompiler{} 2085 i := &instruction{kind: brTableSequence, targets: []uint32{1, 2, 3, 4, 5}} 2086 encodeBrTableSequence(m, x22VReg, i.targets) 2087 encoded := m.Buf() 2088 require.Equal(t, i.size(), int64(len(encoded))) 2089 require.Equal(t, "9b000010765bb6b87b03168b60031fd6", hex.EncodeToString(encoded[:brTableSequenceOffsetTableBegin])) 2090 require.Equal(t, "0100000002000000030000000400000005000000", hex.EncodeToString(encoded[brTableSequenceOffsetTableBegin:])) 2091 } 2092 2093 func Test_encodeUnconditionalBranch(t *testing.T) { 2094 buf := make([]byte, 4) 2095 2096 actual := encodeUnconditionalBranch(true, 4) 2097 binary.LittleEndian.PutUint32(buf, actual) 2098 require.Equal(t, "0x01000094", fmt.Sprintf("%#x", buf)) 2099 2100 actual = encodeUnconditionalBranch(false, 4*1024) 2101 binary.LittleEndian.PutUint32(buf, actual) 2102 require.Equal(t, "0x00040014", fmt.Sprintf("%#x", buf)) 2103 }