github.com/bir3/gocompiler@v0.3.205/src/cmd/compile/internal/ssa/_gen/LOONG64.rules (about) 1 // Copyright 2022 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 (Add(Ptr|64|32|16|8) ...) => (ADDV ...) 6 (Add(32|64)F ...) => (ADD(F|D) ...) 7 8 (Sub(Ptr|64|32|16|8) ...) => (SUBV ...) 9 (Sub(32|64)F ...) => (SUB(F|D) ...) 10 11 (Mul(64|32|16|8) x y) => (Select1 (MULVU x y)) 12 (Mul(32|64)F ...) => (MUL(F|D) ...) 13 (Mul64uhilo ...) => (MULVU ...) 14 (Select0 (Mul64uover x y)) => (Select1 <typ.UInt64> (MULVU x y)) 15 (Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (Select0 <typ.UInt64> (MULVU x y)) (MOVVconst <typ.UInt64> [0])) 16 17 (Hmul64 x y) => (Select0 (MULV x y)) 18 (Hmul64u x y) => (Select0 (MULVU x y)) 19 (Hmul32 x y) => (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32]) 20 (Hmul32u x y) => (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32]) 21 22 (Div64 x y) => (Select1 (DIVV x y)) 23 (Div64u x y) => (Select1 (DIVVU x y)) 24 (Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 25 (Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 26 (Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 27 (Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 28 (Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 29 (Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 30 (Div(32|64)F ...) => (DIV(F|D) ...) 31 32 (Mod64 x y) => (Select0 (DIVV x y)) 33 (Mod64u x y) => (Select0 (DIVVU x y)) 34 (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 35 (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 36 (Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 37 (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 38 (Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 39 (Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 40 41 (Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c) 42 (Select1 <t> (Add64carry x y c)) => 43 (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c))) 44 45 (Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c) 46 (Select1 <t> (Sub64borrow x y c)) => 47 (OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s)) 48 49 // (x + y) / 2 with x>=y => (x - y) / 2 + y 50 (Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y) 51 52 (And(64|32|16|8) ...) => (AND ...) 53 (Or(64|32|16|8) ...) => (OR ...) 54 (Xor(64|32|16|8) ...) => (XOR ...) 55 56 // shifts 57 // hardware instruction uses only the low 6 bits of the shift 58 // we compare to 64 to ensure Go semantics for large shifts 59 (Lsh64x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 60 (Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 61 (Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 62 (Lsh64x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 63 64 (Lsh32x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 65 (Lsh32x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 66 (Lsh32x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 67 (Lsh32x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 68 69 (Lsh16x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 70 (Lsh16x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 71 (Lsh16x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 72 (Lsh16x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 73 74 (Lsh8x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 75 (Lsh8x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 76 (Lsh8x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 77 (Lsh8x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 78 79 (Rsh64Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y)) 80 (Rsh64Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y))) 81 (Rsh64Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y))) 82 (Rsh64Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y))) 83 84 (Rsh32Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y)) 85 (Rsh32Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y))) 86 (Rsh32Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y))) 87 (Rsh32Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y))) 88 89 (Rsh16Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y)) 90 (Rsh16Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y))) 91 (Rsh16Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y))) 92 (Rsh16Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y))) 93 94 (Rsh8Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y)) 95 (Rsh8Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y))) 96 (Rsh8Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y))) 97 (Rsh8Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y))) 98 99 (Rsh64x64 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 100 (Rsh64x32 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 101 (Rsh64x16 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 102 (Rsh64x8 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 103 104 (Rsh32x64 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 105 (Rsh32x32 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 106 (Rsh32x16 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 107 (Rsh32x8 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 108 109 (Rsh16x64 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 110 (Rsh16x32 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 111 (Rsh16x16 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 112 (Rsh16x8 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 113 114 (Rsh8x64 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 115 (Rsh8x32 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 116 (Rsh8x16 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 117 (Rsh8x8 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 118 119 // rotates 120 (RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7]))) 121 (RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15]))) 122 (RotateLeft32 x y) => (ROTR x (NEGV <y.Type> y)) 123 (RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y)) 124 125 // unary ops 126 (Neg(64|32|16|8) ...) => (NEGV ...) 127 (Neg(32|64)F ...) => (NEG(F|D) ...) 128 129 (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x) 130 131 (Sqrt ...) => (SQRTD ...) 132 (Sqrt32 ...) => (SQRTF ...) 133 134 // boolean ops -- booleans are represented with 0=false, 1=true 135 (AndB ...) => (AND ...) 136 (OrB ...) => (OR ...) 137 (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y)) 138 (NeqB ...) => (XOR ...) 139 (Not x) => (XORconst [1] x) 140 141 // constants 142 (Const(64|32|16|8) [val]) => (MOVVconst [int64(val)]) 143 (Const(32|64)F [val]) => (MOV(F|D)const [float64(val)]) 144 (ConstNil) => (MOVVconst [0]) 145 (ConstBool [t]) => (MOVVconst [int64(b2i(t))]) 146 147 (Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63]) 148 149 // truncations 150 // Because we ignore high parts of registers, truncates are just copies. 151 (Trunc16to8 ...) => (Copy ...) 152 (Trunc32to8 ...) => (Copy ...) 153 (Trunc32to16 ...) => (Copy ...) 154 (Trunc64to8 ...) => (Copy ...) 155 (Trunc64to16 ...) => (Copy ...) 156 (Trunc64to32 ...) => (Copy ...) 157 158 // Zero-/Sign-extensions 159 (ZeroExt8to16 ...) => (MOVBUreg ...) 160 (ZeroExt8to32 ...) => (MOVBUreg ...) 161 (ZeroExt16to32 ...) => (MOVHUreg ...) 162 (ZeroExt8to64 ...) => (MOVBUreg ...) 163 (ZeroExt16to64 ...) => (MOVHUreg ...) 164 (ZeroExt32to64 ...) => (MOVWUreg ...) 165 166 (SignExt8to16 ...) => (MOVBreg ...) 167 (SignExt8to32 ...) => (MOVBreg ...) 168 (SignExt16to32 ...) => (MOVHreg ...) 169 (SignExt8to64 ...) => (MOVBreg ...) 170 (SignExt16to64 ...) => (MOVHreg ...) 171 (SignExt32to64 ...) => (MOVWreg ...) 172 173 // float <=> int conversion 174 (Cvt32to32F ...) => (MOVWF ...) 175 (Cvt32to64F ...) => (MOVWD ...) 176 (Cvt64to32F ...) => (MOVVF ...) 177 (Cvt64to64F ...) => (MOVVD ...) 178 (Cvt32Fto32 ...) => (TRUNCFW ...) 179 (Cvt64Fto32 ...) => (TRUNCDW ...) 180 (Cvt32Fto64 ...) => (TRUNCFV ...) 181 (Cvt64Fto64 ...) => (TRUNCDV ...) 182 (Cvt32Fto64F ...) => (MOVFD ...) 183 (Cvt64Fto32F ...) => (MOVDF ...) 184 185 (CvtBoolToUint8 ...) => (Copy ...) 186 187 (Round(32|64)F ...) => (Copy ...) 188 189 // comparisons 190 (Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) 191 (Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) 192 (Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) 193 (Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y)) 194 (EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y)) 195 (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y)) 196 197 (Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0])) 198 (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0])) 199 (Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0])) 200 (Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0])) 201 (NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0])) 202 (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y)) 203 204 (Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x)) 205 (Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x)) 206 (Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x)) 207 (Less64 x y) => (SGT y x) 208 (Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN 209 210 (Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x)) 211 (Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x)) 212 (Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x)) 213 (Less64U x y) => (SGTU y x) 214 215 (Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y))) 216 (Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y))) 217 (Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y))) 218 (Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y)) 219 (Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN 220 221 (Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y))) 222 (Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y))) 223 (Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y))) 224 (Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y)) 225 226 (OffPtr [off] ptr:(SP)) => (MOVVaddr [int32(off)] ptr) 227 (OffPtr [off] ptr) => (ADDVconst [off] ptr) 228 229 (Addr {sym} base) => (MOVVaddr {sym} base) 230 (LocalAddr {sym} base _) => (MOVVaddr {sym} base) 231 232 // loads 233 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem) 234 (Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem) 235 (Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem) 236 (Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem) 237 (Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem) 238 (Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem) 239 (Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem) 240 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem) 241 (Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem) 242 (Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem) 243 244 // stores 245 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem) 246 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem) 247 (Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem) 248 (Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVVstore ptr val mem) 249 (Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem) 250 (Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem) 251 252 // zeroing 253 (Zero [0] _ mem) => mem 254 (Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem) 255 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 => 256 (MOVHstore ptr (MOVVconst [0]) mem) 257 (Zero [2] ptr mem) => 258 (MOVBstore [1] ptr (MOVVconst [0]) 259 (MOVBstore [0] ptr (MOVVconst [0]) mem)) 260 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 => 261 (MOVWstore ptr (MOVVconst [0]) mem) 262 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 => 263 (MOVHstore [2] ptr (MOVVconst [0]) 264 (MOVHstore [0] ptr (MOVVconst [0]) mem)) 265 (Zero [4] ptr mem) => 266 (MOVBstore [3] ptr (MOVVconst [0]) 267 (MOVBstore [2] ptr (MOVVconst [0]) 268 (MOVBstore [1] ptr (MOVVconst [0]) 269 (MOVBstore [0] ptr (MOVVconst [0]) mem)))) 270 (Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 => 271 (MOVVstore ptr (MOVVconst [0]) mem) 272 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 => 273 (MOVWstore [4] ptr (MOVVconst [0]) 274 (MOVWstore [0] ptr (MOVVconst [0]) mem)) 275 (Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 => 276 (MOVHstore [6] ptr (MOVVconst [0]) 277 (MOVHstore [4] ptr (MOVVconst [0]) 278 (MOVHstore [2] ptr (MOVVconst [0]) 279 (MOVHstore [0] ptr (MOVVconst [0]) mem)))) 280 281 (Zero [3] ptr mem) => 282 (MOVBstore [2] ptr (MOVVconst [0]) 283 (MOVBstore [1] ptr (MOVVconst [0]) 284 (MOVBstore [0] ptr (MOVVconst [0]) mem))) 285 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 => 286 (MOVHstore [4] ptr (MOVVconst [0]) 287 (MOVHstore [2] ptr (MOVVconst [0]) 288 (MOVHstore [0] ptr (MOVVconst [0]) mem))) 289 (Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 => 290 (MOVWstore [8] ptr (MOVVconst [0]) 291 (MOVWstore [4] ptr (MOVVconst [0]) 292 (MOVWstore [0] ptr (MOVVconst [0]) mem))) 293 (Zero [16] {t} ptr mem) && t.Alignment()%8 == 0 => 294 (MOVVstore [8] ptr (MOVVconst [0]) 295 (MOVVstore [0] ptr (MOVVconst [0]) mem)) 296 (Zero [24] {t} ptr mem) && t.Alignment()%8 == 0 => 297 (MOVVstore [16] ptr (MOVVconst [0]) 298 (MOVVstore [8] ptr (MOVVconst [0]) 299 (MOVVstore [0] ptr (MOVVconst [0]) mem))) 300 301 // medium zeroing uses a duff device 302 // 8, and 128 are magic constants, see runtime/mkduff.go 303 (Zero [s] {t} ptr mem) 304 && s%8 == 0 && s > 24 && s <= 8*128 305 && t.Alignment()%8 == 0 && !config.noDuffDevice => 306 (DUFFZERO [8 * (128 - s/8)] ptr mem) 307 308 // large or unaligned zeroing uses a loop 309 (Zero [s] {t} ptr mem) 310 && (s > 8*128 || config.noDuffDevice) || t.Alignment()%8 != 0 => 311 (LoweredZero [t.Alignment()] 312 ptr 313 (ADDVconst <ptr.Type> ptr [s-moveSize(t.Alignment(), config)]) 314 mem) 315 316 // moves 317 (Move [0] _ _ mem) => mem 318 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem) 319 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 => 320 (MOVHstore dst (MOVHload src mem) mem) 321 (Move [2] dst src mem) => 322 (MOVBstore [1] dst (MOVBload [1] src mem) 323 (MOVBstore dst (MOVBload src mem) mem)) 324 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 => 325 (MOVWstore dst (MOVWload src mem) mem) 326 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 => 327 (MOVHstore [2] dst (MOVHload [2] src mem) 328 (MOVHstore dst (MOVHload src mem) mem)) 329 (Move [4] dst src mem) => 330 (MOVBstore [3] dst (MOVBload [3] src mem) 331 (MOVBstore [2] dst (MOVBload [2] src mem) 332 (MOVBstore [1] dst (MOVBload [1] src mem) 333 (MOVBstore dst (MOVBload src mem) mem)))) 334 (Move [8] {t} dst src mem) && t.Alignment()%8 == 0 => 335 (MOVVstore dst (MOVVload src mem) mem) 336 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 => 337 (MOVWstore [4] dst (MOVWload [4] src mem) 338 (MOVWstore dst (MOVWload src mem) mem)) 339 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 => 340 (MOVHstore [6] dst (MOVHload [6] src mem) 341 (MOVHstore [4] dst (MOVHload [4] src mem) 342 (MOVHstore [2] dst (MOVHload [2] src mem) 343 (MOVHstore dst (MOVHload src mem) mem)))) 344 345 (Move [3] dst src mem) => 346 (MOVBstore [2] dst (MOVBload [2] src mem) 347 (MOVBstore [1] dst (MOVBload [1] src mem) 348 (MOVBstore dst (MOVBload src mem) mem))) 349 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 => 350 (MOVHstore [4] dst (MOVHload [4] src mem) 351 (MOVHstore [2] dst (MOVHload [2] src mem) 352 (MOVHstore dst (MOVHload src mem) mem))) 353 (Move [12] {t} dst src mem) && t.Alignment()%4 == 0 => 354 (MOVWstore [8] dst (MOVWload [8] src mem) 355 (MOVWstore [4] dst (MOVWload [4] src mem) 356 (MOVWstore dst (MOVWload src mem) mem))) 357 (Move [16] {t} dst src mem) && t.Alignment()%8 == 0 => 358 (MOVVstore [8] dst (MOVVload [8] src mem) 359 (MOVVstore dst (MOVVload src mem) mem)) 360 (Move [24] {t} dst src mem) && t.Alignment()%8 == 0 => 361 (MOVVstore [16] dst (MOVVload [16] src mem) 362 (MOVVstore [8] dst (MOVVload [8] src mem) 363 (MOVVstore dst (MOVVload src mem) mem))) 364 365 // medium move uses a duff device 366 (Move [s] {t} dst src mem) 367 && s%8 == 0 && s >= 24 && s <= 8*128 && t.Alignment()%8 == 0 368 && !config.noDuffDevice && logLargeCopy(v, s) => 369 (DUFFCOPY [16 * (128 - s/8)] dst src mem) 370 // 16 and 128 are magic constants. 16 is the number of bytes to encode: 371 // MOVV (R1), R23 372 // ADDV $8, R1 373 // MOVV R23, (R2) 374 // ADDV $8, R2 375 // and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy. 376 377 // large or unaligned move uses a loop 378 (Move [s] {t} dst src mem) 379 && s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0 => 380 (LoweredMove [t.Alignment()] 381 dst 382 src 383 (ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)]) 384 mem) 385 386 // calls 387 (StaticCall ...) => (CALLstatic ...) 388 (ClosureCall ...) => (CALLclosure ...) 389 (InterCall ...) => (CALLinter ...) 390 (TailCall ...) => (CALLtail ...) 391 392 // atomic intrinsics 393 (AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...) 394 (AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...) 395 396 (AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...) 397 (AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...) 398 399 (AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...) 400 401 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...) 402 403 (AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem) 404 (AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...) 405 406 // checks 407 (NilCheck ...) => (LoweredNilCheck ...) 408 (IsNonNil ptr) => (SGTU ptr (MOVVconst [0])) 409 (IsInBounds idx len) => (SGTU len idx) 410 (IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len)) 411 412 // pseudo-ops 413 (GetClosurePtr ...) => (LoweredGetClosurePtr ...) 414 (GetCallerSP ...) => (LoweredGetCallerSP ...) 415 (GetCallerPC ...) => (LoweredGetCallerPC ...) 416 417 (If cond yes no) => (NE cond yes no) 418 419 // Write barrier. 420 (WB ...) => (LoweredWB ...) 421 422 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem) 423 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem) 424 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem) 425 426 (CondSelect <t> x y cond) => (OR (MASKEQZ <t> x cond) (MASKNEZ <t> y cond)) 427 428 // Optimizations 429 430 // Absorb boolean tests into block 431 (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no) 432 (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no) 433 (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no) 434 (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no) 435 (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no) 436 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no) 437 (NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no) 438 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no) 439 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no) 440 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no) 441 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no) 442 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no) 443 (NE (SGTUconst [1] x) yes no) => (EQ x yes no) 444 (EQ (SGTUconst [1] x) yes no) => (NE x yes no) 445 (NE (SGTU x (MOVVconst [0])) yes no) => (NE x yes no) 446 (EQ (SGTU x (MOVVconst [0])) yes no) => (EQ x yes no) 447 (NE (SGTconst [0] x) yes no) => (LTZ x yes no) 448 (EQ (SGTconst [0] x) yes no) => (GEZ x yes no) 449 (NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no) 450 (EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no) 451 452 // fold offset into address 453 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr) 454 455 // fold address into load/store 456 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBload [off1+int32(off2)] {sym} ptr mem) 457 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBUload [off1+int32(off2)] {sym} ptr mem) 458 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHload [off1+int32(off2)] {sym} ptr mem) 459 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHUload [off1+int32(off2)] {sym} ptr mem) 460 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWload [off1+int32(off2)] {sym} ptr mem) 461 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWUload [off1+int32(off2)] {sym} ptr mem) 462 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVload [off1+int32(off2)] {sym} ptr mem) 463 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVFload [off1+int32(off2)] {sym} ptr mem) 464 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVDload [off1+int32(off2)] {sym} ptr mem) 465 466 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVBstore [off1+int32(off2)] {sym} ptr val mem) 467 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVHstore [off1+int32(off2)] {sym} ptr val mem) 468 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVWstore [off1+int32(off2)] {sym} ptr val mem) 469 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVVstore [off1+int32(off2)] {sym} ptr val mem) 470 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVFstore [off1+int32(off2)] {sym} ptr val mem) 471 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVDstore [off1+int32(off2)] {sym} ptr val mem) 472 (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) 473 (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) 474 (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) 475 (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVstorezero [off1+int32(off2)] {sym} ptr mem) 476 477 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 478 (MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 479 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 480 (MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 481 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 482 (MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 483 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 484 (MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 485 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 486 (MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 487 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 488 (MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 489 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 490 (MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 491 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 492 (MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 493 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 494 (MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 495 496 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 497 (MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 498 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 499 (MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 500 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 501 (MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 502 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 503 (MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 504 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 505 (MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 506 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 507 (MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem) 508 (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 509 (MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 510 (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 511 (MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 512 (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 513 (MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 514 (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) => 515 (MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem) 516 517 (LoweredAtomicStore(32|64) ptr (MOVVconst [0]) mem) => (LoweredAtomicStorezero(32|64) ptr mem) 518 (LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst32 [int32(c)] ptr mem) 519 (LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst64 [c] ptr mem) 520 521 // don't extend after proper load 522 (MOVBreg x:(MOVBload _ _)) => (MOVVreg x) 523 (MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x) 524 (MOVHreg x:(MOVBload _ _)) => (MOVVreg x) 525 (MOVHreg x:(MOVBUload _ _)) => (MOVVreg x) 526 (MOVHreg x:(MOVHload _ _)) => (MOVVreg x) 527 (MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x) 528 (MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x) 529 (MOVWreg x:(MOVBload _ _)) => (MOVVreg x) 530 (MOVWreg x:(MOVBUload _ _)) => (MOVVreg x) 531 (MOVWreg x:(MOVHload _ _)) => (MOVVreg x) 532 (MOVWreg x:(MOVHUload _ _)) => (MOVVreg x) 533 (MOVWreg x:(MOVWload _ _)) => (MOVVreg x) 534 (MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x) 535 (MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x) 536 (MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x) 537 538 // fold double extensions 539 (MOVBreg x:(MOVBreg _)) => (MOVVreg x) 540 (MOVBUreg x:(MOVBUreg _)) => (MOVVreg x) 541 (MOVHreg x:(MOVBreg _)) => (MOVVreg x) 542 (MOVHreg x:(MOVBUreg _)) => (MOVVreg x) 543 (MOVHreg x:(MOVHreg _)) => (MOVVreg x) 544 (MOVHUreg x:(MOVBUreg _)) => (MOVVreg x) 545 (MOVHUreg x:(MOVHUreg _)) => (MOVVreg x) 546 (MOVWreg x:(MOVBreg _)) => (MOVVreg x) 547 (MOVWreg x:(MOVBUreg _)) => (MOVVreg x) 548 (MOVWreg x:(MOVHreg _)) => (MOVVreg x) 549 (MOVWreg x:(MOVWreg _)) => (MOVVreg x) 550 (MOVWUreg x:(MOVBUreg _)) => (MOVVreg x) 551 (MOVWUreg x:(MOVHUreg _)) => (MOVVreg x) 552 (MOVWUreg x:(MOVWUreg _)) => (MOVVreg x) 553 554 // don't extend before store 555 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 556 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 557 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 558 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 559 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 560 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 561 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 562 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 563 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 564 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 565 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem) 566 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem) 567 568 // if a register move has only 1 use, just use the same register without emitting instruction 569 // MOVVnop doesn't emit instruction, only for ensuring the type. 570 (MOVVreg x) && x.Uses == 1 => (MOVVnop x) 571 572 // fold constant into arithmetic ops 573 (ADDV x (MOVVconst [c])) && is32Bit(c) => (ADDVconst [c] x) 574 (SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x) 575 (AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x) 576 (OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x) 577 (XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x) 578 (NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x) 579 580 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) 581 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0]) 582 (SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63]) 583 (SLLV x (MOVVconst [c])) => (SLLVconst x [c]) 584 (SRLV x (MOVVconst [c])) => (SRLVconst x [c]) 585 (SRAV x (MOVVconst [c])) => (SRAVconst x [c]) 586 (ROTR x (MOVVconst [c])) => (ROTRconst x [c&31]) 587 (ROTRV x (MOVVconst [c])) => (ROTRVconst x [c&63]) 588 589 (SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x) 590 (SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x) 591 592 // mul by constant 593 (Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x) 594 (Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0]) 595 (Select1 (MULVU x (MOVVconst [1]))) => x 596 (Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SLLVconst [log64(c)] x) 597 598 // div by constant 599 (Select1 (DIVVU x (MOVVconst [1]))) => x 600 (Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SRLVconst [log64(c)] x) 601 (Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod 602 (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (ANDconst [c-1] x) // mod 603 604 // generic simplifications 605 (ADDV x (NEGV y)) => (SUBV x y) 606 (SUBV x x) => (MOVVconst [0]) 607 (SUBV (MOVVconst [0]) x) => (NEGV x) 608 (AND x x) => x 609 (OR x x) => x 610 (XOR x x) => (MOVVconst [0]) 611 612 // remove redundant *const ops 613 (ADDVconst [0] x) => x 614 (SUBVconst [0] x) => x 615 (ANDconst [0] _) => (MOVVconst [0]) 616 (ANDconst [-1] x) => x 617 (ORconst [0] x) => x 618 (ORconst [-1] _) => (MOVVconst [-1]) 619 (XORconst [0] x) => x 620 (XORconst [-1] x) => (NORconst [0] x) 621 (MASKEQZ (MOVVconst [0]) cond) => (MOVVconst [0]) 622 (MASKNEZ (MOVVconst [0]) cond) => (MOVVconst [0]) 623 624 // generic constant folding 625 (ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d]) 626 (ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) => (ADDVconst [c+d] x) 627 (ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) => (ADDVconst [c-d] x) 628 (SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c]) 629 (SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) => (ADDVconst [-c-d] x) 630 (SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) => (ADDVconst [-c+d] x) 631 (SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)]) 632 (SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))]) 633 (SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)]) 634 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c*d]) 635 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c/d]) 636 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)/uint64(d))]) 637 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c%d]) // mod 638 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod 639 (ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d]) 640 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) 641 (ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d]) 642 (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x) 643 (XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d]) 644 (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x) 645 (NORconst [c] (MOVVconst [d])) => (MOVVconst [^(c|d)]) 646 (NEGV (MOVVconst [c])) => (MOVVconst [-c]) 647 (MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))]) 648 (MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))]) 649 (MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))]) 650 (MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))]) 651 (MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))]) 652 (MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))]) 653 (MOVVreg (MOVVconst [c])) => (MOVVconst [c]) 654 655 // constant comparisons 656 (SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1]) 657 (SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0]) 658 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1]) 659 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0]) 660 661 // other known comparisons 662 (SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1]) 663 (SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0]) 664 (SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1]) 665 (SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0]) 666 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1]) 667 (SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1]) 668 (SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0]) 669 (SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1]) 670 (SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0]) 671 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1]) 672 (SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0]) 673 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1]) 674 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1]) 675 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1]) 676 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1]) 677 678 // absorb constants into branches 679 (EQ (MOVVconst [0]) yes no) => (First yes no) 680 (EQ (MOVVconst [c]) yes no) && c != 0 => (First no yes) 681 (NE (MOVVconst [0]) yes no) => (First no yes) 682 (NE (MOVVconst [c]) yes no) && c != 0 => (First yes no) 683 (LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no) 684 (LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes) 685 (LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no) 686 (LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes) 687 (GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no) 688 (GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes) 689 (GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no) 690 (GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes) 691 692 // SGT/SGTU with known outcomes. 693 (SGT x x) => (MOVVconst [0]) 694 (SGTU x x) => (MOVVconst [0])