github.com/bir3/gocompiler@v0.3.205/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from _gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "github.com/bir3/gocompiler/src/cmd/internal/obj" 7 "github.com/bir3/gocompiler/src/cmd/internal/obj/arm" 8 "github.com/bir3/gocompiler/src/cmd/internal/obj/arm64" 9 "github.com/bir3/gocompiler/src/cmd/internal/obj/loong64" 10 "github.com/bir3/gocompiler/src/cmd/internal/obj/mips" 11 "github.com/bir3/gocompiler/src/cmd/internal/obj/ppc64" 12 "github.com/bir3/gocompiler/src/cmd/internal/obj/riscv" 13 "github.com/bir3/gocompiler/src/cmd/internal/obj/s390x" 14 "github.com/bir3/gocompiler/src/cmd/internal/obj/wasm" 15 "github.com/bir3/gocompiler/src/cmd/internal/obj/x86" 16 ) 17 18 const ( 19 BlockInvalid BlockKind = iota 20 21 Block386EQ 22 Block386NE 23 Block386LT 24 Block386LE 25 Block386GT 26 Block386GE 27 Block386OS 28 Block386OC 29 Block386ULT 30 Block386ULE 31 Block386UGT 32 Block386UGE 33 Block386EQF 34 Block386NEF 35 Block386ORD 36 Block386NAN 37 38 BlockAMD64EQ 39 BlockAMD64NE 40 BlockAMD64LT 41 BlockAMD64LE 42 BlockAMD64GT 43 BlockAMD64GE 44 BlockAMD64OS 45 BlockAMD64OC 46 BlockAMD64ULT 47 BlockAMD64ULE 48 BlockAMD64UGT 49 BlockAMD64UGE 50 BlockAMD64EQF 51 BlockAMD64NEF 52 BlockAMD64ORD 53 BlockAMD64NAN 54 BlockAMD64JUMPTABLE 55 56 BlockARMEQ 57 BlockARMNE 58 BlockARMLT 59 BlockARMLE 60 BlockARMGT 61 BlockARMGE 62 BlockARMULT 63 BlockARMULE 64 BlockARMUGT 65 BlockARMUGE 66 BlockARMLTnoov 67 BlockARMLEnoov 68 BlockARMGTnoov 69 BlockARMGEnoov 70 71 BlockARM64EQ 72 BlockARM64NE 73 BlockARM64LT 74 BlockARM64LE 75 BlockARM64GT 76 BlockARM64GE 77 BlockARM64ULT 78 BlockARM64ULE 79 BlockARM64UGT 80 BlockARM64UGE 81 BlockARM64Z 82 BlockARM64NZ 83 BlockARM64ZW 84 BlockARM64NZW 85 BlockARM64TBZ 86 BlockARM64TBNZ 87 BlockARM64FLT 88 BlockARM64FLE 89 BlockARM64FGT 90 BlockARM64FGE 91 BlockARM64LTnoov 92 BlockARM64LEnoov 93 BlockARM64GTnoov 94 BlockARM64GEnoov 95 BlockARM64JUMPTABLE 96 97 BlockLOONG64EQ 98 BlockLOONG64NE 99 BlockLOONG64LTZ 100 BlockLOONG64LEZ 101 BlockLOONG64GTZ 102 BlockLOONG64GEZ 103 BlockLOONG64FPT 104 BlockLOONG64FPF 105 106 BlockMIPSEQ 107 BlockMIPSNE 108 BlockMIPSLTZ 109 BlockMIPSLEZ 110 BlockMIPSGTZ 111 BlockMIPSGEZ 112 BlockMIPSFPT 113 BlockMIPSFPF 114 115 BlockMIPS64EQ 116 BlockMIPS64NE 117 BlockMIPS64LTZ 118 BlockMIPS64LEZ 119 BlockMIPS64GTZ 120 BlockMIPS64GEZ 121 BlockMIPS64FPT 122 BlockMIPS64FPF 123 124 BlockPPC64EQ 125 BlockPPC64NE 126 BlockPPC64LT 127 BlockPPC64LE 128 BlockPPC64GT 129 BlockPPC64GE 130 BlockPPC64FLT 131 BlockPPC64FLE 132 BlockPPC64FGT 133 BlockPPC64FGE 134 135 BlockRISCV64BEQ 136 BlockRISCV64BNE 137 BlockRISCV64BLT 138 BlockRISCV64BGE 139 BlockRISCV64BLTU 140 BlockRISCV64BGEU 141 BlockRISCV64BEQZ 142 BlockRISCV64BNEZ 143 BlockRISCV64BLEZ 144 BlockRISCV64BGEZ 145 BlockRISCV64BLTZ 146 BlockRISCV64BGTZ 147 148 BlockS390XBRC 149 BlockS390XCRJ 150 BlockS390XCGRJ 151 BlockS390XCLRJ 152 BlockS390XCLGRJ 153 BlockS390XCIJ 154 BlockS390XCGIJ 155 BlockS390XCLIJ 156 BlockS390XCLGIJ 157 158 BlockPlain 159 BlockIf 160 BlockDefer 161 BlockRet 162 BlockRetJmp 163 BlockExit 164 BlockJumpTable 165 BlockFirst 166 ) 167 168 var blockString = [...]string{ 169 BlockInvalid: "BlockInvalid", 170 171 Block386EQ: "EQ", 172 Block386NE: "NE", 173 Block386LT: "LT", 174 Block386LE: "LE", 175 Block386GT: "GT", 176 Block386GE: "GE", 177 Block386OS: "OS", 178 Block386OC: "OC", 179 Block386ULT: "ULT", 180 Block386ULE: "ULE", 181 Block386UGT: "UGT", 182 Block386UGE: "UGE", 183 Block386EQF: "EQF", 184 Block386NEF: "NEF", 185 Block386ORD: "ORD", 186 Block386NAN: "NAN", 187 188 BlockAMD64EQ: "EQ", 189 BlockAMD64NE: "NE", 190 BlockAMD64LT: "LT", 191 BlockAMD64LE: "LE", 192 BlockAMD64GT: "GT", 193 BlockAMD64GE: "GE", 194 BlockAMD64OS: "OS", 195 BlockAMD64OC: "OC", 196 BlockAMD64ULT: "ULT", 197 BlockAMD64ULE: "ULE", 198 BlockAMD64UGT: "UGT", 199 BlockAMD64UGE: "UGE", 200 BlockAMD64EQF: "EQF", 201 BlockAMD64NEF: "NEF", 202 BlockAMD64ORD: "ORD", 203 BlockAMD64NAN: "NAN", 204 BlockAMD64JUMPTABLE: "JUMPTABLE", 205 206 BlockARMEQ: "EQ", 207 BlockARMNE: "NE", 208 BlockARMLT: "LT", 209 BlockARMLE: "LE", 210 BlockARMGT: "GT", 211 BlockARMGE: "GE", 212 BlockARMULT: "ULT", 213 BlockARMULE: "ULE", 214 BlockARMUGT: "UGT", 215 BlockARMUGE: "UGE", 216 BlockARMLTnoov: "LTnoov", 217 BlockARMLEnoov: "LEnoov", 218 BlockARMGTnoov: "GTnoov", 219 BlockARMGEnoov: "GEnoov", 220 221 BlockARM64EQ: "EQ", 222 BlockARM64NE: "NE", 223 BlockARM64LT: "LT", 224 BlockARM64LE: "LE", 225 BlockARM64GT: "GT", 226 BlockARM64GE: "GE", 227 BlockARM64ULT: "ULT", 228 BlockARM64ULE: "ULE", 229 BlockARM64UGT: "UGT", 230 BlockARM64UGE: "UGE", 231 BlockARM64Z: "Z", 232 BlockARM64NZ: "NZ", 233 BlockARM64ZW: "ZW", 234 BlockARM64NZW: "NZW", 235 BlockARM64TBZ: "TBZ", 236 BlockARM64TBNZ: "TBNZ", 237 BlockARM64FLT: "FLT", 238 BlockARM64FLE: "FLE", 239 BlockARM64FGT: "FGT", 240 BlockARM64FGE: "FGE", 241 BlockARM64LTnoov: "LTnoov", 242 BlockARM64LEnoov: "LEnoov", 243 BlockARM64GTnoov: "GTnoov", 244 BlockARM64GEnoov: "GEnoov", 245 BlockARM64JUMPTABLE: "JUMPTABLE", 246 247 BlockLOONG64EQ: "EQ", 248 BlockLOONG64NE: "NE", 249 BlockLOONG64LTZ: "LTZ", 250 BlockLOONG64LEZ: "LEZ", 251 BlockLOONG64GTZ: "GTZ", 252 BlockLOONG64GEZ: "GEZ", 253 BlockLOONG64FPT: "FPT", 254 BlockLOONG64FPF: "FPF", 255 256 BlockMIPSEQ: "EQ", 257 BlockMIPSNE: "NE", 258 BlockMIPSLTZ: "LTZ", 259 BlockMIPSLEZ: "LEZ", 260 BlockMIPSGTZ: "GTZ", 261 BlockMIPSGEZ: "GEZ", 262 BlockMIPSFPT: "FPT", 263 BlockMIPSFPF: "FPF", 264 265 BlockMIPS64EQ: "EQ", 266 BlockMIPS64NE: "NE", 267 BlockMIPS64LTZ: "LTZ", 268 BlockMIPS64LEZ: "LEZ", 269 BlockMIPS64GTZ: "GTZ", 270 BlockMIPS64GEZ: "GEZ", 271 BlockMIPS64FPT: "FPT", 272 BlockMIPS64FPF: "FPF", 273 274 BlockPPC64EQ: "EQ", 275 BlockPPC64NE: "NE", 276 BlockPPC64LT: "LT", 277 BlockPPC64LE: "LE", 278 BlockPPC64GT: "GT", 279 BlockPPC64GE: "GE", 280 BlockPPC64FLT: "FLT", 281 BlockPPC64FLE: "FLE", 282 BlockPPC64FGT: "FGT", 283 BlockPPC64FGE: "FGE", 284 285 BlockRISCV64BEQ: "BEQ", 286 BlockRISCV64BNE: "BNE", 287 BlockRISCV64BLT: "BLT", 288 BlockRISCV64BGE: "BGE", 289 BlockRISCV64BLTU: "BLTU", 290 BlockRISCV64BGEU: "BGEU", 291 BlockRISCV64BEQZ: "BEQZ", 292 BlockRISCV64BNEZ: "BNEZ", 293 BlockRISCV64BLEZ: "BLEZ", 294 BlockRISCV64BGEZ: "BGEZ", 295 BlockRISCV64BLTZ: "BLTZ", 296 BlockRISCV64BGTZ: "BGTZ", 297 298 BlockS390XBRC: "BRC", 299 BlockS390XCRJ: "CRJ", 300 BlockS390XCGRJ: "CGRJ", 301 BlockS390XCLRJ: "CLRJ", 302 BlockS390XCLGRJ: "CLGRJ", 303 BlockS390XCIJ: "CIJ", 304 BlockS390XCGIJ: "CGIJ", 305 BlockS390XCLIJ: "CLIJ", 306 BlockS390XCLGIJ: "CLGIJ", 307 308 BlockPlain: "Plain", 309 BlockIf: "If", 310 BlockDefer: "Defer", 311 BlockRet: "Ret", 312 BlockRetJmp: "RetJmp", 313 BlockExit: "Exit", 314 BlockJumpTable: "JumpTable", 315 BlockFirst: "First", 316 } 317 318 func (k BlockKind) String() string { return blockString[k] } 319 func (k BlockKind) AuxIntType() string { 320 switch k { 321 case BlockARM64TBZ: 322 return "int64" 323 case BlockARM64TBNZ: 324 return "int64" 325 case BlockS390XCIJ: 326 return "int8" 327 case BlockS390XCGIJ: 328 return "int8" 329 case BlockS390XCLIJ: 330 return "uint8" 331 case BlockS390XCLGIJ: 332 return "uint8" 333 } 334 return "" 335 } 336 337 const ( 338 OpInvalid Op = iota 339 340 Op386ADDSS 341 Op386ADDSD 342 Op386SUBSS 343 Op386SUBSD 344 Op386MULSS 345 Op386MULSD 346 Op386DIVSS 347 Op386DIVSD 348 Op386MOVSSload 349 Op386MOVSDload 350 Op386MOVSSconst 351 Op386MOVSDconst 352 Op386MOVSSloadidx1 353 Op386MOVSSloadidx4 354 Op386MOVSDloadidx1 355 Op386MOVSDloadidx8 356 Op386MOVSSstore 357 Op386MOVSDstore 358 Op386MOVSSstoreidx1 359 Op386MOVSSstoreidx4 360 Op386MOVSDstoreidx1 361 Op386MOVSDstoreidx8 362 Op386ADDSSload 363 Op386ADDSDload 364 Op386SUBSSload 365 Op386SUBSDload 366 Op386MULSSload 367 Op386MULSDload 368 Op386DIVSSload 369 Op386DIVSDload 370 Op386ADDL 371 Op386ADDLconst 372 Op386ADDLcarry 373 Op386ADDLconstcarry 374 Op386ADCL 375 Op386ADCLconst 376 Op386SUBL 377 Op386SUBLconst 378 Op386SUBLcarry 379 Op386SUBLconstcarry 380 Op386SBBL 381 Op386SBBLconst 382 Op386MULL 383 Op386MULLconst 384 Op386MULLU 385 Op386HMULL 386 Op386HMULLU 387 Op386MULLQU 388 Op386AVGLU 389 Op386DIVL 390 Op386DIVW 391 Op386DIVLU 392 Op386DIVWU 393 Op386MODL 394 Op386MODW 395 Op386MODLU 396 Op386MODWU 397 Op386ANDL 398 Op386ANDLconst 399 Op386ORL 400 Op386ORLconst 401 Op386XORL 402 Op386XORLconst 403 Op386CMPL 404 Op386CMPW 405 Op386CMPB 406 Op386CMPLconst 407 Op386CMPWconst 408 Op386CMPBconst 409 Op386CMPLload 410 Op386CMPWload 411 Op386CMPBload 412 Op386CMPLconstload 413 Op386CMPWconstload 414 Op386CMPBconstload 415 Op386UCOMISS 416 Op386UCOMISD 417 Op386TESTL 418 Op386TESTW 419 Op386TESTB 420 Op386TESTLconst 421 Op386TESTWconst 422 Op386TESTBconst 423 Op386SHLL 424 Op386SHLLconst 425 Op386SHRL 426 Op386SHRW 427 Op386SHRB 428 Op386SHRLconst 429 Op386SHRWconst 430 Op386SHRBconst 431 Op386SARL 432 Op386SARW 433 Op386SARB 434 Op386SARLconst 435 Op386SARWconst 436 Op386SARBconst 437 Op386ROLL 438 Op386ROLW 439 Op386ROLB 440 Op386ROLLconst 441 Op386ROLWconst 442 Op386ROLBconst 443 Op386ADDLload 444 Op386SUBLload 445 Op386MULLload 446 Op386ANDLload 447 Op386ORLload 448 Op386XORLload 449 Op386ADDLloadidx4 450 Op386SUBLloadidx4 451 Op386MULLloadidx4 452 Op386ANDLloadidx4 453 Op386ORLloadidx4 454 Op386XORLloadidx4 455 Op386NEGL 456 Op386NOTL 457 Op386BSFL 458 Op386BSFW 459 Op386BSRL 460 Op386BSRW 461 Op386BSWAPL 462 Op386SQRTSD 463 Op386SQRTSS 464 Op386SBBLcarrymask 465 Op386SETEQ 466 Op386SETNE 467 Op386SETL 468 Op386SETLE 469 Op386SETG 470 Op386SETGE 471 Op386SETB 472 Op386SETBE 473 Op386SETA 474 Op386SETAE 475 Op386SETO 476 Op386SETEQF 477 Op386SETNEF 478 Op386SETORD 479 Op386SETNAN 480 Op386SETGF 481 Op386SETGEF 482 Op386MOVBLSX 483 Op386MOVBLZX 484 Op386MOVWLSX 485 Op386MOVWLZX 486 Op386MOVLconst 487 Op386CVTTSD2SL 488 Op386CVTTSS2SL 489 Op386CVTSL2SS 490 Op386CVTSL2SD 491 Op386CVTSD2SS 492 Op386CVTSS2SD 493 Op386PXOR 494 Op386LEAL 495 Op386LEAL1 496 Op386LEAL2 497 Op386LEAL4 498 Op386LEAL8 499 Op386MOVBload 500 Op386MOVBLSXload 501 Op386MOVWload 502 Op386MOVWLSXload 503 Op386MOVLload 504 Op386MOVBstore 505 Op386MOVWstore 506 Op386MOVLstore 507 Op386ADDLmodify 508 Op386SUBLmodify 509 Op386ANDLmodify 510 Op386ORLmodify 511 Op386XORLmodify 512 Op386ADDLmodifyidx4 513 Op386SUBLmodifyidx4 514 Op386ANDLmodifyidx4 515 Op386ORLmodifyidx4 516 Op386XORLmodifyidx4 517 Op386ADDLconstmodify 518 Op386ANDLconstmodify 519 Op386ORLconstmodify 520 Op386XORLconstmodify 521 Op386ADDLconstmodifyidx4 522 Op386ANDLconstmodifyidx4 523 Op386ORLconstmodifyidx4 524 Op386XORLconstmodifyidx4 525 Op386MOVBloadidx1 526 Op386MOVWloadidx1 527 Op386MOVWloadidx2 528 Op386MOVLloadidx1 529 Op386MOVLloadidx4 530 Op386MOVBstoreidx1 531 Op386MOVWstoreidx1 532 Op386MOVWstoreidx2 533 Op386MOVLstoreidx1 534 Op386MOVLstoreidx4 535 Op386MOVBstoreconst 536 Op386MOVWstoreconst 537 Op386MOVLstoreconst 538 Op386MOVBstoreconstidx1 539 Op386MOVWstoreconstidx1 540 Op386MOVWstoreconstidx2 541 Op386MOVLstoreconstidx1 542 Op386MOVLstoreconstidx4 543 Op386DUFFZERO 544 Op386REPSTOSL 545 Op386CALLstatic 546 Op386CALLtail 547 Op386CALLclosure 548 Op386CALLinter 549 Op386DUFFCOPY 550 Op386REPMOVSL 551 Op386InvertFlags 552 Op386LoweredGetG 553 Op386LoweredGetClosurePtr 554 Op386LoweredGetCallerPC 555 Op386LoweredGetCallerSP 556 Op386LoweredNilCheck 557 Op386LoweredWB 558 Op386LoweredPanicBoundsA 559 Op386LoweredPanicBoundsB 560 Op386LoweredPanicBoundsC 561 Op386LoweredPanicExtendA 562 Op386LoweredPanicExtendB 563 Op386LoweredPanicExtendC 564 Op386FlagEQ 565 Op386FlagLT_ULT 566 Op386FlagLT_UGT 567 Op386FlagGT_UGT 568 Op386FlagGT_ULT 569 Op386MOVSSconst1 570 Op386MOVSDconst1 571 Op386MOVSSconst2 572 Op386MOVSDconst2 573 574 OpAMD64ADDSS 575 OpAMD64ADDSD 576 OpAMD64SUBSS 577 OpAMD64SUBSD 578 OpAMD64MULSS 579 OpAMD64MULSD 580 OpAMD64DIVSS 581 OpAMD64DIVSD 582 OpAMD64MOVSSload 583 OpAMD64MOVSDload 584 OpAMD64MOVSSconst 585 OpAMD64MOVSDconst 586 OpAMD64MOVSSloadidx1 587 OpAMD64MOVSSloadidx4 588 OpAMD64MOVSDloadidx1 589 OpAMD64MOVSDloadidx8 590 OpAMD64MOVSSstore 591 OpAMD64MOVSDstore 592 OpAMD64MOVSSstoreidx1 593 OpAMD64MOVSSstoreidx4 594 OpAMD64MOVSDstoreidx1 595 OpAMD64MOVSDstoreidx8 596 OpAMD64ADDSSload 597 OpAMD64ADDSDload 598 OpAMD64SUBSSload 599 OpAMD64SUBSDload 600 OpAMD64MULSSload 601 OpAMD64MULSDload 602 OpAMD64DIVSSload 603 OpAMD64DIVSDload 604 OpAMD64ADDSSloadidx1 605 OpAMD64ADDSSloadidx4 606 OpAMD64ADDSDloadidx1 607 OpAMD64ADDSDloadidx8 608 OpAMD64SUBSSloadidx1 609 OpAMD64SUBSSloadidx4 610 OpAMD64SUBSDloadidx1 611 OpAMD64SUBSDloadidx8 612 OpAMD64MULSSloadidx1 613 OpAMD64MULSSloadidx4 614 OpAMD64MULSDloadidx1 615 OpAMD64MULSDloadidx8 616 OpAMD64DIVSSloadidx1 617 OpAMD64DIVSSloadidx4 618 OpAMD64DIVSDloadidx1 619 OpAMD64DIVSDloadidx8 620 OpAMD64ADDQ 621 OpAMD64ADDL 622 OpAMD64ADDQconst 623 OpAMD64ADDLconst 624 OpAMD64ADDQconstmodify 625 OpAMD64ADDLconstmodify 626 OpAMD64SUBQ 627 OpAMD64SUBL 628 OpAMD64SUBQconst 629 OpAMD64SUBLconst 630 OpAMD64MULQ 631 OpAMD64MULL 632 OpAMD64MULQconst 633 OpAMD64MULLconst 634 OpAMD64MULLU 635 OpAMD64MULQU 636 OpAMD64HMULQ 637 OpAMD64HMULL 638 OpAMD64HMULQU 639 OpAMD64HMULLU 640 OpAMD64AVGQU 641 OpAMD64DIVQ 642 OpAMD64DIVL 643 OpAMD64DIVW 644 OpAMD64DIVQU 645 OpAMD64DIVLU 646 OpAMD64DIVWU 647 OpAMD64NEGLflags 648 OpAMD64ADDQcarry 649 OpAMD64ADCQ 650 OpAMD64ADDQconstcarry 651 OpAMD64ADCQconst 652 OpAMD64SUBQborrow 653 OpAMD64SBBQ 654 OpAMD64SUBQconstborrow 655 OpAMD64SBBQconst 656 OpAMD64MULQU2 657 OpAMD64DIVQU2 658 OpAMD64ANDQ 659 OpAMD64ANDL 660 OpAMD64ANDQconst 661 OpAMD64ANDLconst 662 OpAMD64ANDQconstmodify 663 OpAMD64ANDLconstmodify 664 OpAMD64ORQ 665 OpAMD64ORL 666 OpAMD64ORQconst 667 OpAMD64ORLconst 668 OpAMD64ORQconstmodify 669 OpAMD64ORLconstmodify 670 OpAMD64XORQ 671 OpAMD64XORL 672 OpAMD64XORQconst 673 OpAMD64XORLconst 674 OpAMD64XORQconstmodify 675 OpAMD64XORLconstmodify 676 OpAMD64CMPQ 677 OpAMD64CMPL 678 OpAMD64CMPW 679 OpAMD64CMPB 680 OpAMD64CMPQconst 681 OpAMD64CMPLconst 682 OpAMD64CMPWconst 683 OpAMD64CMPBconst 684 OpAMD64CMPQload 685 OpAMD64CMPLload 686 OpAMD64CMPWload 687 OpAMD64CMPBload 688 OpAMD64CMPQconstload 689 OpAMD64CMPLconstload 690 OpAMD64CMPWconstload 691 OpAMD64CMPBconstload 692 OpAMD64CMPQloadidx8 693 OpAMD64CMPQloadidx1 694 OpAMD64CMPLloadidx4 695 OpAMD64CMPLloadidx1 696 OpAMD64CMPWloadidx2 697 OpAMD64CMPWloadidx1 698 OpAMD64CMPBloadidx1 699 OpAMD64CMPQconstloadidx8 700 OpAMD64CMPQconstloadidx1 701 OpAMD64CMPLconstloadidx4 702 OpAMD64CMPLconstloadidx1 703 OpAMD64CMPWconstloadidx2 704 OpAMD64CMPWconstloadidx1 705 OpAMD64CMPBconstloadidx1 706 OpAMD64UCOMISS 707 OpAMD64UCOMISD 708 OpAMD64BTL 709 OpAMD64BTQ 710 OpAMD64BTCL 711 OpAMD64BTCQ 712 OpAMD64BTRL 713 OpAMD64BTRQ 714 OpAMD64BTSL 715 OpAMD64BTSQ 716 OpAMD64BTLconst 717 OpAMD64BTQconst 718 OpAMD64BTCLconst 719 OpAMD64BTCQconst 720 OpAMD64BTRLconst 721 OpAMD64BTRQconst 722 OpAMD64BTSLconst 723 OpAMD64BTSQconst 724 OpAMD64TESTQ 725 OpAMD64TESTL 726 OpAMD64TESTW 727 OpAMD64TESTB 728 OpAMD64TESTQconst 729 OpAMD64TESTLconst 730 OpAMD64TESTWconst 731 OpAMD64TESTBconst 732 OpAMD64SHLQ 733 OpAMD64SHLL 734 OpAMD64SHLQconst 735 OpAMD64SHLLconst 736 OpAMD64SHRQ 737 OpAMD64SHRL 738 OpAMD64SHRW 739 OpAMD64SHRB 740 OpAMD64SHRQconst 741 OpAMD64SHRLconst 742 OpAMD64SHRWconst 743 OpAMD64SHRBconst 744 OpAMD64SARQ 745 OpAMD64SARL 746 OpAMD64SARW 747 OpAMD64SARB 748 OpAMD64SARQconst 749 OpAMD64SARLconst 750 OpAMD64SARWconst 751 OpAMD64SARBconst 752 OpAMD64SHRDQ 753 OpAMD64SHLDQ 754 OpAMD64ROLQ 755 OpAMD64ROLL 756 OpAMD64ROLW 757 OpAMD64ROLB 758 OpAMD64RORQ 759 OpAMD64RORL 760 OpAMD64RORW 761 OpAMD64RORB 762 OpAMD64ROLQconst 763 OpAMD64ROLLconst 764 OpAMD64ROLWconst 765 OpAMD64ROLBconst 766 OpAMD64ADDLload 767 OpAMD64ADDQload 768 OpAMD64SUBQload 769 OpAMD64SUBLload 770 OpAMD64ANDLload 771 OpAMD64ANDQload 772 OpAMD64ORQload 773 OpAMD64ORLload 774 OpAMD64XORQload 775 OpAMD64XORLload 776 OpAMD64ADDLloadidx1 777 OpAMD64ADDLloadidx4 778 OpAMD64ADDLloadidx8 779 OpAMD64ADDQloadidx1 780 OpAMD64ADDQloadidx8 781 OpAMD64SUBLloadidx1 782 OpAMD64SUBLloadidx4 783 OpAMD64SUBLloadidx8 784 OpAMD64SUBQloadidx1 785 OpAMD64SUBQloadidx8 786 OpAMD64ANDLloadidx1 787 OpAMD64ANDLloadidx4 788 OpAMD64ANDLloadidx8 789 OpAMD64ANDQloadidx1 790 OpAMD64ANDQloadidx8 791 OpAMD64ORLloadidx1 792 OpAMD64ORLloadidx4 793 OpAMD64ORLloadidx8 794 OpAMD64ORQloadidx1 795 OpAMD64ORQloadidx8 796 OpAMD64XORLloadidx1 797 OpAMD64XORLloadidx4 798 OpAMD64XORLloadidx8 799 OpAMD64XORQloadidx1 800 OpAMD64XORQloadidx8 801 OpAMD64ADDQmodify 802 OpAMD64SUBQmodify 803 OpAMD64ANDQmodify 804 OpAMD64ORQmodify 805 OpAMD64XORQmodify 806 OpAMD64ADDLmodify 807 OpAMD64SUBLmodify 808 OpAMD64ANDLmodify 809 OpAMD64ORLmodify 810 OpAMD64XORLmodify 811 OpAMD64ADDQmodifyidx1 812 OpAMD64ADDQmodifyidx8 813 OpAMD64SUBQmodifyidx1 814 OpAMD64SUBQmodifyidx8 815 OpAMD64ANDQmodifyidx1 816 OpAMD64ANDQmodifyidx8 817 OpAMD64ORQmodifyidx1 818 OpAMD64ORQmodifyidx8 819 OpAMD64XORQmodifyidx1 820 OpAMD64XORQmodifyidx8 821 OpAMD64ADDLmodifyidx1 822 OpAMD64ADDLmodifyidx4 823 OpAMD64ADDLmodifyidx8 824 OpAMD64SUBLmodifyidx1 825 OpAMD64SUBLmodifyidx4 826 OpAMD64SUBLmodifyidx8 827 OpAMD64ANDLmodifyidx1 828 OpAMD64ANDLmodifyidx4 829 OpAMD64ANDLmodifyidx8 830 OpAMD64ORLmodifyidx1 831 OpAMD64ORLmodifyidx4 832 OpAMD64ORLmodifyidx8 833 OpAMD64XORLmodifyidx1 834 OpAMD64XORLmodifyidx4 835 OpAMD64XORLmodifyidx8 836 OpAMD64ADDQconstmodifyidx1 837 OpAMD64ADDQconstmodifyidx8 838 OpAMD64ANDQconstmodifyidx1 839 OpAMD64ANDQconstmodifyidx8 840 OpAMD64ORQconstmodifyidx1 841 OpAMD64ORQconstmodifyidx8 842 OpAMD64XORQconstmodifyidx1 843 OpAMD64XORQconstmodifyidx8 844 OpAMD64ADDLconstmodifyidx1 845 OpAMD64ADDLconstmodifyidx4 846 OpAMD64ADDLconstmodifyidx8 847 OpAMD64ANDLconstmodifyidx1 848 OpAMD64ANDLconstmodifyidx4 849 OpAMD64ANDLconstmodifyidx8 850 OpAMD64ORLconstmodifyidx1 851 OpAMD64ORLconstmodifyidx4 852 OpAMD64ORLconstmodifyidx8 853 OpAMD64XORLconstmodifyidx1 854 OpAMD64XORLconstmodifyidx4 855 OpAMD64XORLconstmodifyidx8 856 OpAMD64NEGQ 857 OpAMD64NEGL 858 OpAMD64NOTQ 859 OpAMD64NOTL 860 OpAMD64BSFQ 861 OpAMD64BSFL 862 OpAMD64BSRQ 863 OpAMD64BSRL 864 OpAMD64CMOVQEQ 865 OpAMD64CMOVQNE 866 OpAMD64CMOVQLT 867 OpAMD64CMOVQGT 868 OpAMD64CMOVQLE 869 OpAMD64CMOVQGE 870 OpAMD64CMOVQLS 871 OpAMD64CMOVQHI 872 OpAMD64CMOVQCC 873 OpAMD64CMOVQCS 874 OpAMD64CMOVLEQ 875 OpAMD64CMOVLNE 876 OpAMD64CMOVLLT 877 OpAMD64CMOVLGT 878 OpAMD64CMOVLLE 879 OpAMD64CMOVLGE 880 OpAMD64CMOVLLS 881 OpAMD64CMOVLHI 882 OpAMD64CMOVLCC 883 OpAMD64CMOVLCS 884 OpAMD64CMOVWEQ 885 OpAMD64CMOVWNE 886 OpAMD64CMOVWLT 887 OpAMD64CMOVWGT 888 OpAMD64CMOVWLE 889 OpAMD64CMOVWGE 890 OpAMD64CMOVWLS 891 OpAMD64CMOVWHI 892 OpAMD64CMOVWCC 893 OpAMD64CMOVWCS 894 OpAMD64CMOVQEQF 895 OpAMD64CMOVQNEF 896 OpAMD64CMOVQGTF 897 OpAMD64CMOVQGEF 898 OpAMD64CMOVLEQF 899 OpAMD64CMOVLNEF 900 OpAMD64CMOVLGTF 901 OpAMD64CMOVLGEF 902 OpAMD64CMOVWEQF 903 OpAMD64CMOVWNEF 904 OpAMD64CMOVWGTF 905 OpAMD64CMOVWGEF 906 OpAMD64BSWAPQ 907 OpAMD64BSWAPL 908 OpAMD64POPCNTQ 909 OpAMD64POPCNTL 910 OpAMD64SQRTSD 911 OpAMD64SQRTSS 912 OpAMD64ROUNDSD 913 OpAMD64VFMADD231SD 914 OpAMD64SBBQcarrymask 915 OpAMD64SBBLcarrymask 916 OpAMD64SETEQ 917 OpAMD64SETNE 918 OpAMD64SETL 919 OpAMD64SETLE 920 OpAMD64SETG 921 OpAMD64SETGE 922 OpAMD64SETB 923 OpAMD64SETBE 924 OpAMD64SETA 925 OpAMD64SETAE 926 OpAMD64SETO 927 OpAMD64SETEQstore 928 OpAMD64SETNEstore 929 OpAMD64SETLstore 930 OpAMD64SETLEstore 931 OpAMD64SETGstore 932 OpAMD64SETGEstore 933 OpAMD64SETBstore 934 OpAMD64SETBEstore 935 OpAMD64SETAstore 936 OpAMD64SETAEstore 937 OpAMD64SETEQF 938 OpAMD64SETNEF 939 OpAMD64SETORD 940 OpAMD64SETNAN 941 OpAMD64SETGF 942 OpAMD64SETGEF 943 OpAMD64MOVBQSX 944 OpAMD64MOVBQZX 945 OpAMD64MOVWQSX 946 OpAMD64MOVWQZX 947 OpAMD64MOVLQSX 948 OpAMD64MOVLQZX 949 OpAMD64MOVLconst 950 OpAMD64MOVQconst 951 OpAMD64CVTTSD2SL 952 OpAMD64CVTTSD2SQ 953 OpAMD64CVTTSS2SL 954 OpAMD64CVTTSS2SQ 955 OpAMD64CVTSL2SS 956 OpAMD64CVTSL2SD 957 OpAMD64CVTSQ2SS 958 OpAMD64CVTSQ2SD 959 OpAMD64CVTSD2SS 960 OpAMD64CVTSS2SD 961 OpAMD64MOVQi2f 962 OpAMD64MOVQf2i 963 OpAMD64MOVLi2f 964 OpAMD64MOVLf2i 965 OpAMD64PXOR 966 OpAMD64LEAQ 967 OpAMD64LEAL 968 OpAMD64LEAW 969 OpAMD64LEAQ1 970 OpAMD64LEAL1 971 OpAMD64LEAW1 972 OpAMD64LEAQ2 973 OpAMD64LEAL2 974 OpAMD64LEAW2 975 OpAMD64LEAQ4 976 OpAMD64LEAL4 977 OpAMD64LEAW4 978 OpAMD64LEAQ8 979 OpAMD64LEAL8 980 OpAMD64LEAW8 981 OpAMD64MOVBload 982 OpAMD64MOVBQSXload 983 OpAMD64MOVWload 984 OpAMD64MOVWQSXload 985 OpAMD64MOVLload 986 OpAMD64MOVLQSXload 987 OpAMD64MOVQload 988 OpAMD64MOVBstore 989 OpAMD64MOVWstore 990 OpAMD64MOVLstore 991 OpAMD64MOVQstore 992 OpAMD64MOVOload 993 OpAMD64MOVOstore 994 OpAMD64MOVBloadidx1 995 OpAMD64MOVWloadidx1 996 OpAMD64MOVWloadidx2 997 OpAMD64MOVLloadidx1 998 OpAMD64MOVLloadidx4 999 OpAMD64MOVLloadidx8 1000 OpAMD64MOVQloadidx1 1001 OpAMD64MOVQloadidx8 1002 OpAMD64MOVBstoreidx1 1003 OpAMD64MOVWstoreidx1 1004 OpAMD64MOVWstoreidx2 1005 OpAMD64MOVLstoreidx1 1006 OpAMD64MOVLstoreidx4 1007 OpAMD64MOVLstoreidx8 1008 OpAMD64MOVQstoreidx1 1009 OpAMD64MOVQstoreidx8 1010 OpAMD64MOVBstoreconst 1011 OpAMD64MOVWstoreconst 1012 OpAMD64MOVLstoreconst 1013 OpAMD64MOVQstoreconst 1014 OpAMD64MOVOstoreconst 1015 OpAMD64MOVBstoreconstidx1 1016 OpAMD64MOVWstoreconstidx1 1017 OpAMD64MOVWstoreconstidx2 1018 OpAMD64MOVLstoreconstidx1 1019 OpAMD64MOVLstoreconstidx4 1020 OpAMD64MOVQstoreconstidx1 1021 OpAMD64MOVQstoreconstidx8 1022 OpAMD64DUFFZERO 1023 OpAMD64REPSTOSQ 1024 OpAMD64CALLstatic 1025 OpAMD64CALLtail 1026 OpAMD64CALLclosure 1027 OpAMD64CALLinter 1028 OpAMD64DUFFCOPY 1029 OpAMD64REPMOVSQ 1030 OpAMD64InvertFlags 1031 OpAMD64LoweredGetG 1032 OpAMD64LoweredGetClosurePtr 1033 OpAMD64LoweredGetCallerPC 1034 OpAMD64LoweredGetCallerSP 1035 OpAMD64LoweredNilCheck 1036 OpAMD64LoweredWB 1037 OpAMD64LoweredHasCPUFeature 1038 OpAMD64LoweredPanicBoundsA 1039 OpAMD64LoweredPanicBoundsB 1040 OpAMD64LoweredPanicBoundsC 1041 OpAMD64FlagEQ 1042 OpAMD64FlagLT_ULT 1043 OpAMD64FlagLT_UGT 1044 OpAMD64FlagGT_UGT 1045 OpAMD64FlagGT_ULT 1046 OpAMD64MOVBatomicload 1047 OpAMD64MOVLatomicload 1048 OpAMD64MOVQatomicload 1049 OpAMD64XCHGB 1050 OpAMD64XCHGL 1051 OpAMD64XCHGQ 1052 OpAMD64XADDLlock 1053 OpAMD64XADDQlock 1054 OpAMD64AddTupleFirst32 1055 OpAMD64AddTupleFirst64 1056 OpAMD64CMPXCHGLlock 1057 OpAMD64CMPXCHGQlock 1058 OpAMD64ANDBlock 1059 OpAMD64ANDLlock 1060 OpAMD64ORBlock 1061 OpAMD64ORLlock 1062 OpAMD64PrefetchT0 1063 OpAMD64PrefetchNTA 1064 OpAMD64ANDNQ 1065 OpAMD64ANDNL 1066 OpAMD64BLSIQ 1067 OpAMD64BLSIL 1068 OpAMD64BLSMSKQ 1069 OpAMD64BLSMSKL 1070 OpAMD64BLSRQ 1071 OpAMD64BLSRL 1072 OpAMD64TZCNTQ 1073 OpAMD64TZCNTL 1074 OpAMD64LZCNTQ 1075 OpAMD64LZCNTL 1076 OpAMD64MOVBEWstore 1077 OpAMD64MOVBELload 1078 OpAMD64MOVBELstore 1079 OpAMD64MOVBEQload 1080 OpAMD64MOVBEQstore 1081 OpAMD64MOVBELloadidx1 1082 OpAMD64MOVBELloadidx4 1083 OpAMD64MOVBELloadidx8 1084 OpAMD64MOVBEQloadidx1 1085 OpAMD64MOVBEQloadidx8 1086 OpAMD64MOVBEWstoreidx1 1087 OpAMD64MOVBEWstoreidx2 1088 OpAMD64MOVBELstoreidx1 1089 OpAMD64MOVBELstoreidx4 1090 OpAMD64MOVBELstoreidx8 1091 OpAMD64MOVBEQstoreidx1 1092 OpAMD64MOVBEQstoreidx8 1093 OpAMD64SARXQ 1094 OpAMD64SARXL 1095 OpAMD64SHLXQ 1096 OpAMD64SHLXL 1097 OpAMD64SHRXQ 1098 OpAMD64SHRXL 1099 OpAMD64SARXLload 1100 OpAMD64SARXQload 1101 OpAMD64SHLXLload 1102 OpAMD64SHLXQload 1103 OpAMD64SHRXLload 1104 OpAMD64SHRXQload 1105 OpAMD64SARXLloadidx1 1106 OpAMD64SARXLloadidx4 1107 OpAMD64SARXLloadidx8 1108 OpAMD64SARXQloadidx1 1109 OpAMD64SARXQloadidx8 1110 OpAMD64SHLXLloadidx1 1111 OpAMD64SHLXLloadidx4 1112 OpAMD64SHLXLloadidx8 1113 OpAMD64SHLXQloadidx1 1114 OpAMD64SHLXQloadidx8 1115 OpAMD64SHRXLloadidx1 1116 OpAMD64SHRXLloadidx4 1117 OpAMD64SHRXLloadidx8 1118 OpAMD64SHRXQloadidx1 1119 OpAMD64SHRXQloadidx8 1120 1121 OpARMADD 1122 OpARMADDconst 1123 OpARMSUB 1124 OpARMSUBconst 1125 OpARMRSB 1126 OpARMRSBconst 1127 OpARMMUL 1128 OpARMHMUL 1129 OpARMHMULU 1130 OpARMCALLudiv 1131 OpARMADDS 1132 OpARMADDSconst 1133 OpARMADC 1134 OpARMADCconst 1135 OpARMSUBS 1136 OpARMSUBSconst 1137 OpARMRSBSconst 1138 OpARMSBC 1139 OpARMSBCconst 1140 OpARMRSCconst 1141 OpARMMULLU 1142 OpARMMULA 1143 OpARMMULS 1144 OpARMADDF 1145 OpARMADDD 1146 OpARMSUBF 1147 OpARMSUBD 1148 OpARMMULF 1149 OpARMMULD 1150 OpARMNMULF 1151 OpARMNMULD 1152 OpARMDIVF 1153 OpARMDIVD 1154 OpARMMULAF 1155 OpARMMULAD 1156 OpARMMULSF 1157 OpARMMULSD 1158 OpARMFMULAD 1159 OpARMAND 1160 OpARMANDconst 1161 OpARMOR 1162 OpARMORconst 1163 OpARMXOR 1164 OpARMXORconst 1165 OpARMBIC 1166 OpARMBICconst 1167 OpARMBFX 1168 OpARMBFXU 1169 OpARMMVN 1170 OpARMNEGF 1171 OpARMNEGD 1172 OpARMSQRTD 1173 OpARMSQRTF 1174 OpARMABSD 1175 OpARMCLZ 1176 OpARMREV 1177 OpARMREV16 1178 OpARMRBIT 1179 OpARMSLL 1180 OpARMSLLconst 1181 OpARMSRL 1182 OpARMSRLconst 1183 OpARMSRA 1184 OpARMSRAconst 1185 OpARMSRR 1186 OpARMSRRconst 1187 OpARMADDshiftLL 1188 OpARMADDshiftRL 1189 OpARMADDshiftRA 1190 OpARMSUBshiftLL 1191 OpARMSUBshiftRL 1192 OpARMSUBshiftRA 1193 OpARMRSBshiftLL 1194 OpARMRSBshiftRL 1195 OpARMRSBshiftRA 1196 OpARMANDshiftLL 1197 OpARMANDshiftRL 1198 OpARMANDshiftRA 1199 OpARMORshiftLL 1200 OpARMORshiftRL 1201 OpARMORshiftRA 1202 OpARMXORshiftLL 1203 OpARMXORshiftRL 1204 OpARMXORshiftRA 1205 OpARMXORshiftRR 1206 OpARMBICshiftLL 1207 OpARMBICshiftRL 1208 OpARMBICshiftRA 1209 OpARMMVNshiftLL 1210 OpARMMVNshiftRL 1211 OpARMMVNshiftRA 1212 OpARMADCshiftLL 1213 OpARMADCshiftRL 1214 OpARMADCshiftRA 1215 OpARMSBCshiftLL 1216 OpARMSBCshiftRL 1217 OpARMSBCshiftRA 1218 OpARMRSCshiftLL 1219 OpARMRSCshiftRL 1220 OpARMRSCshiftRA 1221 OpARMADDSshiftLL 1222 OpARMADDSshiftRL 1223 OpARMADDSshiftRA 1224 OpARMSUBSshiftLL 1225 OpARMSUBSshiftRL 1226 OpARMSUBSshiftRA 1227 OpARMRSBSshiftLL 1228 OpARMRSBSshiftRL 1229 OpARMRSBSshiftRA 1230 OpARMADDshiftLLreg 1231 OpARMADDshiftRLreg 1232 OpARMADDshiftRAreg 1233 OpARMSUBshiftLLreg 1234 OpARMSUBshiftRLreg 1235 OpARMSUBshiftRAreg 1236 OpARMRSBshiftLLreg 1237 OpARMRSBshiftRLreg 1238 OpARMRSBshiftRAreg 1239 OpARMANDshiftLLreg 1240 OpARMANDshiftRLreg 1241 OpARMANDshiftRAreg 1242 OpARMORshiftLLreg 1243 OpARMORshiftRLreg 1244 OpARMORshiftRAreg 1245 OpARMXORshiftLLreg 1246 OpARMXORshiftRLreg 1247 OpARMXORshiftRAreg 1248 OpARMBICshiftLLreg 1249 OpARMBICshiftRLreg 1250 OpARMBICshiftRAreg 1251 OpARMMVNshiftLLreg 1252 OpARMMVNshiftRLreg 1253 OpARMMVNshiftRAreg 1254 OpARMADCshiftLLreg 1255 OpARMADCshiftRLreg 1256 OpARMADCshiftRAreg 1257 OpARMSBCshiftLLreg 1258 OpARMSBCshiftRLreg 1259 OpARMSBCshiftRAreg 1260 OpARMRSCshiftLLreg 1261 OpARMRSCshiftRLreg 1262 OpARMRSCshiftRAreg 1263 OpARMADDSshiftLLreg 1264 OpARMADDSshiftRLreg 1265 OpARMADDSshiftRAreg 1266 OpARMSUBSshiftLLreg 1267 OpARMSUBSshiftRLreg 1268 OpARMSUBSshiftRAreg 1269 OpARMRSBSshiftLLreg 1270 OpARMRSBSshiftRLreg 1271 OpARMRSBSshiftRAreg 1272 OpARMCMP 1273 OpARMCMPconst 1274 OpARMCMN 1275 OpARMCMNconst 1276 OpARMTST 1277 OpARMTSTconst 1278 OpARMTEQ 1279 OpARMTEQconst 1280 OpARMCMPF 1281 OpARMCMPD 1282 OpARMCMPshiftLL 1283 OpARMCMPshiftRL 1284 OpARMCMPshiftRA 1285 OpARMCMNshiftLL 1286 OpARMCMNshiftRL 1287 OpARMCMNshiftRA 1288 OpARMTSTshiftLL 1289 OpARMTSTshiftRL 1290 OpARMTSTshiftRA 1291 OpARMTEQshiftLL 1292 OpARMTEQshiftRL 1293 OpARMTEQshiftRA 1294 OpARMCMPshiftLLreg 1295 OpARMCMPshiftRLreg 1296 OpARMCMPshiftRAreg 1297 OpARMCMNshiftLLreg 1298 OpARMCMNshiftRLreg 1299 OpARMCMNshiftRAreg 1300 OpARMTSTshiftLLreg 1301 OpARMTSTshiftRLreg 1302 OpARMTSTshiftRAreg 1303 OpARMTEQshiftLLreg 1304 OpARMTEQshiftRLreg 1305 OpARMTEQshiftRAreg 1306 OpARMCMPF0 1307 OpARMCMPD0 1308 OpARMMOVWconst 1309 OpARMMOVFconst 1310 OpARMMOVDconst 1311 OpARMMOVWaddr 1312 OpARMMOVBload 1313 OpARMMOVBUload 1314 OpARMMOVHload 1315 OpARMMOVHUload 1316 OpARMMOVWload 1317 OpARMMOVFload 1318 OpARMMOVDload 1319 OpARMMOVBstore 1320 OpARMMOVHstore 1321 OpARMMOVWstore 1322 OpARMMOVFstore 1323 OpARMMOVDstore 1324 OpARMMOVWloadidx 1325 OpARMMOVWloadshiftLL 1326 OpARMMOVWloadshiftRL 1327 OpARMMOVWloadshiftRA 1328 OpARMMOVBUloadidx 1329 OpARMMOVBloadidx 1330 OpARMMOVHUloadidx 1331 OpARMMOVHloadidx 1332 OpARMMOVWstoreidx 1333 OpARMMOVWstoreshiftLL 1334 OpARMMOVWstoreshiftRL 1335 OpARMMOVWstoreshiftRA 1336 OpARMMOVBstoreidx 1337 OpARMMOVHstoreidx 1338 OpARMMOVBreg 1339 OpARMMOVBUreg 1340 OpARMMOVHreg 1341 OpARMMOVHUreg 1342 OpARMMOVWreg 1343 OpARMMOVWnop 1344 OpARMMOVWF 1345 OpARMMOVWD 1346 OpARMMOVWUF 1347 OpARMMOVWUD 1348 OpARMMOVFW 1349 OpARMMOVDW 1350 OpARMMOVFWU 1351 OpARMMOVDWU 1352 OpARMMOVFD 1353 OpARMMOVDF 1354 OpARMCMOVWHSconst 1355 OpARMCMOVWLSconst 1356 OpARMSRAcond 1357 OpARMCALLstatic 1358 OpARMCALLtail 1359 OpARMCALLclosure 1360 OpARMCALLinter 1361 OpARMLoweredNilCheck 1362 OpARMEqual 1363 OpARMNotEqual 1364 OpARMLessThan 1365 OpARMLessEqual 1366 OpARMGreaterThan 1367 OpARMGreaterEqual 1368 OpARMLessThanU 1369 OpARMLessEqualU 1370 OpARMGreaterThanU 1371 OpARMGreaterEqualU 1372 OpARMDUFFZERO 1373 OpARMDUFFCOPY 1374 OpARMLoweredZero 1375 OpARMLoweredMove 1376 OpARMLoweredGetClosurePtr 1377 OpARMLoweredGetCallerSP 1378 OpARMLoweredGetCallerPC 1379 OpARMLoweredPanicBoundsA 1380 OpARMLoweredPanicBoundsB 1381 OpARMLoweredPanicBoundsC 1382 OpARMLoweredPanicExtendA 1383 OpARMLoweredPanicExtendB 1384 OpARMLoweredPanicExtendC 1385 OpARMFlagConstant 1386 OpARMInvertFlags 1387 OpARMLoweredWB 1388 1389 OpARM64ADCSflags 1390 OpARM64ADCzerocarry 1391 OpARM64ADD 1392 OpARM64ADDconst 1393 OpARM64ADDSconstflags 1394 OpARM64ADDSflags 1395 OpARM64SUB 1396 OpARM64SUBconst 1397 OpARM64SBCSflags 1398 OpARM64SUBSflags 1399 OpARM64MUL 1400 OpARM64MULW 1401 OpARM64MNEG 1402 OpARM64MNEGW 1403 OpARM64MULH 1404 OpARM64UMULH 1405 OpARM64MULL 1406 OpARM64UMULL 1407 OpARM64DIV 1408 OpARM64UDIV 1409 OpARM64DIVW 1410 OpARM64UDIVW 1411 OpARM64MOD 1412 OpARM64UMOD 1413 OpARM64MODW 1414 OpARM64UMODW 1415 OpARM64FADDS 1416 OpARM64FADDD 1417 OpARM64FSUBS 1418 OpARM64FSUBD 1419 OpARM64FMULS 1420 OpARM64FMULD 1421 OpARM64FNMULS 1422 OpARM64FNMULD 1423 OpARM64FDIVS 1424 OpARM64FDIVD 1425 OpARM64AND 1426 OpARM64ANDconst 1427 OpARM64OR 1428 OpARM64ORconst 1429 OpARM64XOR 1430 OpARM64XORconst 1431 OpARM64BIC 1432 OpARM64EON 1433 OpARM64ORN 1434 OpARM64MVN 1435 OpARM64NEG 1436 OpARM64NEGSflags 1437 OpARM64NGCzerocarry 1438 OpARM64FABSD 1439 OpARM64FNEGS 1440 OpARM64FNEGD 1441 OpARM64FSQRTD 1442 OpARM64FSQRTS 1443 OpARM64REV 1444 OpARM64REVW 1445 OpARM64REV16 1446 OpARM64REV16W 1447 OpARM64RBIT 1448 OpARM64RBITW 1449 OpARM64CLZ 1450 OpARM64CLZW 1451 OpARM64VCNT 1452 OpARM64VUADDLV 1453 OpARM64LoweredRound32F 1454 OpARM64LoweredRound64F 1455 OpARM64FMADDS 1456 OpARM64FMADDD 1457 OpARM64FNMADDS 1458 OpARM64FNMADDD 1459 OpARM64FMSUBS 1460 OpARM64FMSUBD 1461 OpARM64FNMSUBS 1462 OpARM64FNMSUBD 1463 OpARM64MADD 1464 OpARM64MADDW 1465 OpARM64MSUB 1466 OpARM64MSUBW 1467 OpARM64SLL 1468 OpARM64SLLconst 1469 OpARM64SRL 1470 OpARM64SRLconst 1471 OpARM64SRA 1472 OpARM64SRAconst 1473 OpARM64ROR 1474 OpARM64RORW 1475 OpARM64RORconst 1476 OpARM64RORWconst 1477 OpARM64EXTRconst 1478 OpARM64EXTRWconst 1479 OpARM64CMP 1480 OpARM64CMPconst 1481 OpARM64CMPW 1482 OpARM64CMPWconst 1483 OpARM64CMN 1484 OpARM64CMNconst 1485 OpARM64CMNW 1486 OpARM64CMNWconst 1487 OpARM64TST 1488 OpARM64TSTconst 1489 OpARM64TSTW 1490 OpARM64TSTWconst 1491 OpARM64FCMPS 1492 OpARM64FCMPD 1493 OpARM64FCMPS0 1494 OpARM64FCMPD0 1495 OpARM64MVNshiftLL 1496 OpARM64MVNshiftRL 1497 OpARM64MVNshiftRA 1498 OpARM64MVNshiftRO 1499 OpARM64NEGshiftLL 1500 OpARM64NEGshiftRL 1501 OpARM64NEGshiftRA 1502 OpARM64ADDshiftLL 1503 OpARM64ADDshiftRL 1504 OpARM64ADDshiftRA 1505 OpARM64SUBshiftLL 1506 OpARM64SUBshiftRL 1507 OpARM64SUBshiftRA 1508 OpARM64ANDshiftLL 1509 OpARM64ANDshiftRL 1510 OpARM64ANDshiftRA 1511 OpARM64ANDshiftRO 1512 OpARM64ORshiftLL 1513 OpARM64ORshiftRL 1514 OpARM64ORshiftRA 1515 OpARM64ORshiftRO 1516 OpARM64XORshiftLL 1517 OpARM64XORshiftRL 1518 OpARM64XORshiftRA 1519 OpARM64XORshiftRO 1520 OpARM64BICshiftLL 1521 OpARM64BICshiftRL 1522 OpARM64BICshiftRA 1523 OpARM64BICshiftRO 1524 OpARM64EONshiftLL 1525 OpARM64EONshiftRL 1526 OpARM64EONshiftRA 1527 OpARM64EONshiftRO 1528 OpARM64ORNshiftLL 1529 OpARM64ORNshiftRL 1530 OpARM64ORNshiftRA 1531 OpARM64ORNshiftRO 1532 OpARM64CMPshiftLL 1533 OpARM64CMPshiftRL 1534 OpARM64CMPshiftRA 1535 OpARM64CMNshiftLL 1536 OpARM64CMNshiftRL 1537 OpARM64CMNshiftRA 1538 OpARM64TSTshiftLL 1539 OpARM64TSTshiftRL 1540 OpARM64TSTshiftRA 1541 OpARM64TSTshiftRO 1542 OpARM64BFI 1543 OpARM64BFXIL 1544 OpARM64SBFIZ 1545 OpARM64SBFX 1546 OpARM64UBFIZ 1547 OpARM64UBFX 1548 OpARM64MOVDconst 1549 OpARM64FMOVSconst 1550 OpARM64FMOVDconst 1551 OpARM64MOVDaddr 1552 OpARM64MOVBload 1553 OpARM64MOVBUload 1554 OpARM64MOVHload 1555 OpARM64MOVHUload 1556 OpARM64MOVWload 1557 OpARM64MOVWUload 1558 OpARM64MOVDload 1559 OpARM64LDP 1560 OpARM64FMOVSload 1561 OpARM64FMOVDload 1562 OpARM64MOVDloadidx 1563 OpARM64MOVWloadidx 1564 OpARM64MOVWUloadidx 1565 OpARM64MOVHloadidx 1566 OpARM64MOVHUloadidx 1567 OpARM64MOVBloadidx 1568 OpARM64MOVBUloadidx 1569 OpARM64FMOVSloadidx 1570 OpARM64FMOVDloadidx 1571 OpARM64MOVHloadidx2 1572 OpARM64MOVHUloadidx2 1573 OpARM64MOVWloadidx4 1574 OpARM64MOVWUloadidx4 1575 OpARM64MOVDloadidx8 1576 OpARM64FMOVSloadidx4 1577 OpARM64FMOVDloadidx8 1578 OpARM64MOVBstore 1579 OpARM64MOVHstore 1580 OpARM64MOVWstore 1581 OpARM64MOVDstore 1582 OpARM64STP 1583 OpARM64FMOVSstore 1584 OpARM64FMOVDstore 1585 OpARM64MOVBstoreidx 1586 OpARM64MOVHstoreidx 1587 OpARM64MOVWstoreidx 1588 OpARM64MOVDstoreidx 1589 OpARM64FMOVSstoreidx 1590 OpARM64FMOVDstoreidx 1591 OpARM64MOVHstoreidx2 1592 OpARM64MOVWstoreidx4 1593 OpARM64MOVDstoreidx8 1594 OpARM64FMOVSstoreidx4 1595 OpARM64FMOVDstoreidx8 1596 OpARM64MOVBstorezero 1597 OpARM64MOVHstorezero 1598 OpARM64MOVWstorezero 1599 OpARM64MOVDstorezero 1600 OpARM64MOVQstorezero 1601 OpARM64MOVBstorezeroidx 1602 OpARM64MOVHstorezeroidx 1603 OpARM64MOVWstorezeroidx 1604 OpARM64MOVDstorezeroidx 1605 OpARM64MOVHstorezeroidx2 1606 OpARM64MOVWstorezeroidx4 1607 OpARM64MOVDstorezeroidx8 1608 OpARM64FMOVDgpfp 1609 OpARM64FMOVDfpgp 1610 OpARM64FMOVSgpfp 1611 OpARM64FMOVSfpgp 1612 OpARM64MOVBreg 1613 OpARM64MOVBUreg 1614 OpARM64MOVHreg 1615 OpARM64MOVHUreg 1616 OpARM64MOVWreg 1617 OpARM64MOVWUreg 1618 OpARM64MOVDreg 1619 OpARM64MOVDnop 1620 OpARM64SCVTFWS 1621 OpARM64SCVTFWD 1622 OpARM64UCVTFWS 1623 OpARM64UCVTFWD 1624 OpARM64SCVTFS 1625 OpARM64SCVTFD 1626 OpARM64UCVTFS 1627 OpARM64UCVTFD 1628 OpARM64FCVTZSSW 1629 OpARM64FCVTZSDW 1630 OpARM64FCVTZUSW 1631 OpARM64FCVTZUDW 1632 OpARM64FCVTZSS 1633 OpARM64FCVTZSD 1634 OpARM64FCVTZUS 1635 OpARM64FCVTZUD 1636 OpARM64FCVTSD 1637 OpARM64FCVTDS 1638 OpARM64FRINTAD 1639 OpARM64FRINTMD 1640 OpARM64FRINTND 1641 OpARM64FRINTPD 1642 OpARM64FRINTZD 1643 OpARM64CSEL 1644 OpARM64CSEL0 1645 OpARM64CSINC 1646 OpARM64CSINV 1647 OpARM64CSNEG 1648 OpARM64CSETM 1649 OpARM64CALLstatic 1650 OpARM64CALLtail 1651 OpARM64CALLclosure 1652 OpARM64CALLinter 1653 OpARM64LoweredNilCheck 1654 OpARM64Equal 1655 OpARM64NotEqual 1656 OpARM64LessThan 1657 OpARM64LessEqual 1658 OpARM64GreaterThan 1659 OpARM64GreaterEqual 1660 OpARM64LessThanU 1661 OpARM64LessEqualU 1662 OpARM64GreaterThanU 1663 OpARM64GreaterEqualU 1664 OpARM64LessThanF 1665 OpARM64LessEqualF 1666 OpARM64GreaterThanF 1667 OpARM64GreaterEqualF 1668 OpARM64NotLessThanF 1669 OpARM64NotLessEqualF 1670 OpARM64NotGreaterThanF 1671 OpARM64NotGreaterEqualF 1672 OpARM64DUFFZERO 1673 OpARM64LoweredZero 1674 OpARM64DUFFCOPY 1675 OpARM64LoweredMove 1676 OpARM64LoweredGetClosurePtr 1677 OpARM64LoweredGetCallerSP 1678 OpARM64LoweredGetCallerPC 1679 OpARM64FlagConstant 1680 OpARM64InvertFlags 1681 OpARM64LDAR 1682 OpARM64LDARB 1683 OpARM64LDARW 1684 OpARM64STLRB 1685 OpARM64STLR 1686 OpARM64STLRW 1687 OpARM64LoweredAtomicExchange64 1688 OpARM64LoweredAtomicExchange32 1689 OpARM64LoweredAtomicExchange64Variant 1690 OpARM64LoweredAtomicExchange32Variant 1691 OpARM64LoweredAtomicAdd64 1692 OpARM64LoweredAtomicAdd32 1693 OpARM64LoweredAtomicAdd64Variant 1694 OpARM64LoweredAtomicAdd32Variant 1695 OpARM64LoweredAtomicCas64 1696 OpARM64LoweredAtomicCas32 1697 OpARM64LoweredAtomicCas64Variant 1698 OpARM64LoweredAtomicCas32Variant 1699 OpARM64LoweredAtomicAnd8 1700 OpARM64LoweredAtomicAnd32 1701 OpARM64LoweredAtomicOr8 1702 OpARM64LoweredAtomicOr32 1703 OpARM64LoweredAtomicAnd8Variant 1704 OpARM64LoweredAtomicAnd32Variant 1705 OpARM64LoweredAtomicOr8Variant 1706 OpARM64LoweredAtomicOr32Variant 1707 OpARM64LoweredWB 1708 OpARM64LoweredPanicBoundsA 1709 OpARM64LoweredPanicBoundsB 1710 OpARM64LoweredPanicBoundsC 1711 OpARM64PRFM 1712 OpARM64DMB 1713 1714 OpLOONG64ADDV 1715 OpLOONG64ADDVconst 1716 OpLOONG64SUBV 1717 OpLOONG64SUBVconst 1718 OpLOONG64MULV 1719 OpLOONG64MULVU 1720 OpLOONG64DIVV 1721 OpLOONG64DIVVU 1722 OpLOONG64ADDF 1723 OpLOONG64ADDD 1724 OpLOONG64SUBF 1725 OpLOONG64SUBD 1726 OpLOONG64MULF 1727 OpLOONG64MULD 1728 OpLOONG64DIVF 1729 OpLOONG64DIVD 1730 OpLOONG64AND 1731 OpLOONG64ANDconst 1732 OpLOONG64OR 1733 OpLOONG64ORconst 1734 OpLOONG64XOR 1735 OpLOONG64XORconst 1736 OpLOONG64NOR 1737 OpLOONG64NORconst 1738 OpLOONG64NEGV 1739 OpLOONG64NEGF 1740 OpLOONG64NEGD 1741 OpLOONG64SQRTD 1742 OpLOONG64SQRTF 1743 OpLOONG64MASKEQZ 1744 OpLOONG64MASKNEZ 1745 OpLOONG64SLLV 1746 OpLOONG64SLLVconst 1747 OpLOONG64SRLV 1748 OpLOONG64SRLVconst 1749 OpLOONG64SRAV 1750 OpLOONG64SRAVconst 1751 OpLOONG64ROTR 1752 OpLOONG64ROTRV 1753 OpLOONG64ROTRconst 1754 OpLOONG64ROTRVconst 1755 OpLOONG64SGT 1756 OpLOONG64SGTconst 1757 OpLOONG64SGTU 1758 OpLOONG64SGTUconst 1759 OpLOONG64CMPEQF 1760 OpLOONG64CMPEQD 1761 OpLOONG64CMPGEF 1762 OpLOONG64CMPGED 1763 OpLOONG64CMPGTF 1764 OpLOONG64CMPGTD 1765 OpLOONG64MOVVconst 1766 OpLOONG64MOVFconst 1767 OpLOONG64MOVDconst 1768 OpLOONG64MOVVaddr 1769 OpLOONG64MOVBload 1770 OpLOONG64MOVBUload 1771 OpLOONG64MOVHload 1772 OpLOONG64MOVHUload 1773 OpLOONG64MOVWload 1774 OpLOONG64MOVWUload 1775 OpLOONG64MOVVload 1776 OpLOONG64MOVFload 1777 OpLOONG64MOVDload 1778 OpLOONG64MOVBstore 1779 OpLOONG64MOVHstore 1780 OpLOONG64MOVWstore 1781 OpLOONG64MOVVstore 1782 OpLOONG64MOVFstore 1783 OpLOONG64MOVDstore 1784 OpLOONG64MOVBstorezero 1785 OpLOONG64MOVHstorezero 1786 OpLOONG64MOVWstorezero 1787 OpLOONG64MOVVstorezero 1788 OpLOONG64MOVBreg 1789 OpLOONG64MOVBUreg 1790 OpLOONG64MOVHreg 1791 OpLOONG64MOVHUreg 1792 OpLOONG64MOVWreg 1793 OpLOONG64MOVWUreg 1794 OpLOONG64MOVVreg 1795 OpLOONG64MOVVnop 1796 OpLOONG64MOVWF 1797 OpLOONG64MOVWD 1798 OpLOONG64MOVVF 1799 OpLOONG64MOVVD 1800 OpLOONG64TRUNCFW 1801 OpLOONG64TRUNCDW 1802 OpLOONG64TRUNCFV 1803 OpLOONG64TRUNCDV 1804 OpLOONG64MOVFD 1805 OpLOONG64MOVDF 1806 OpLOONG64CALLstatic 1807 OpLOONG64CALLtail 1808 OpLOONG64CALLclosure 1809 OpLOONG64CALLinter 1810 OpLOONG64DUFFZERO 1811 OpLOONG64DUFFCOPY 1812 OpLOONG64LoweredZero 1813 OpLOONG64LoweredMove 1814 OpLOONG64LoweredAtomicLoad8 1815 OpLOONG64LoweredAtomicLoad32 1816 OpLOONG64LoweredAtomicLoad64 1817 OpLOONG64LoweredAtomicStore8 1818 OpLOONG64LoweredAtomicStore32 1819 OpLOONG64LoweredAtomicStore64 1820 OpLOONG64LoweredAtomicStorezero32 1821 OpLOONG64LoweredAtomicStorezero64 1822 OpLOONG64LoweredAtomicExchange32 1823 OpLOONG64LoweredAtomicExchange64 1824 OpLOONG64LoweredAtomicAdd32 1825 OpLOONG64LoweredAtomicAdd64 1826 OpLOONG64LoweredAtomicAddconst32 1827 OpLOONG64LoweredAtomicAddconst64 1828 OpLOONG64LoweredAtomicCas32 1829 OpLOONG64LoweredAtomicCas64 1830 OpLOONG64LoweredNilCheck 1831 OpLOONG64FPFlagTrue 1832 OpLOONG64FPFlagFalse 1833 OpLOONG64LoweredGetClosurePtr 1834 OpLOONG64LoweredGetCallerSP 1835 OpLOONG64LoweredGetCallerPC 1836 OpLOONG64LoweredWB 1837 OpLOONG64LoweredPanicBoundsA 1838 OpLOONG64LoweredPanicBoundsB 1839 OpLOONG64LoweredPanicBoundsC 1840 1841 OpMIPSADD 1842 OpMIPSADDconst 1843 OpMIPSSUB 1844 OpMIPSSUBconst 1845 OpMIPSMUL 1846 OpMIPSMULT 1847 OpMIPSMULTU 1848 OpMIPSDIV 1849 OpMIPSDIVU 1850 OpMIPSADDF 1851 OpMIPSADDD 1852 OpMIPSSUBF 1853 OpMIPSSUBD 1854 OpMIPSMULF 1855 OpMIPSMULD 1856 OpMIPSDIVF 1857 OpMIPSDIVD 1858 OpMIPSAND 1859 OpMIPSANDconst 1860 OpMIPSOR 1861 OpMIPSORconst 1862 OpMIPSXOR 1863 OpMIPSXORconst 1864 OpMIPSNOR 1865 OpMIPSNORconst 1866 OpMIPSNEG 1867 OpMIPSNEGF 1868 OpMIPSNEGD 1869 OpMIPSSQRTD 1870 OpMIPSSQRTF 1871 OpMIPSSLL 1872 OpMIPSSLLconst 1873 OpMIPSSRL 1874 OpMIPSSRLconst 1875 OpMIPSSRA 1876 OpMIPSSRAconst 1877 OpMIPSCLZ 1878 OpMIPSSGT 1879 OpMIPSSGTconst 1880 OpMIPSSGTzero 1881 OpMIPSSGTU 1882 OpMIPSSGTUconst 1883 OpMIPSSGTUzero 1884 OpMIPSCMPEQF 1885 OpMIPSCMPEQD 1886 OpMIPSCMPGEF 1887 OpMIPSCMPGED 1888 OpMIPSCMPGTF 1889 OpMIPSCMPGTD 1890 OpMIPSMOVWconst 1891 OpMIPSMOVFconst 1892 OpMIPSMOVDconst 1893 OpMIPSMOVWaddr 1894 OpMIPSMOVBload 1895 OpMIPSMOVBUload 1896 OpMIPSMOVHload 1897 OpMIPSMOVHUload 1898 OpMIPSMOVWload 1899 OpMIPSMOVFload 1900 OpMIPSMOVDload 1901 OpMIPSMOVBstore 1902 OpMIPSMOVHstore 1903 OpMIPSMOVWstore 1904 OpMIPSMOVFstore 1905 OpMIPSMOVDstore 1906 OpMIPSMOVBstorezero 1907 OpMIPSMOVHstorezero 1908 OpMIPSMOVWstorezero 1909 OpMIPSMOVBreg 1910 OpMIPSMOVBUreg 1911 OpMIPSMOVHreg 1912 OpMIPSMOVHUreg 1913 OpMIPSMOVWreg 1914 OpMIPSMOVWnop 1915 OpMIPSCMOVZ 1916 OpMIPSCMOVZzero 1917 OpMIPSMOVWF 1918 OpMIPSMOVWD 1919 OpMIPSTRUNCFW 1920 OpMIPSTRUNCDW 1921 OpMIPSMOVFD 1922 OpMIPSMOVDF 1923 OpMIPSCALLstatic 1924 OpMIPSCALLtail 1925 OpMIPSCALLclosure 1926 OpMIPSCALLinter 1927 OpMIPSLoweredAtomicLoad8 1928 OpMIPSLoweredAtomicLoad32 1929 OpMIPSLoweredAtomicStore8 1930 OpMIPSLoweredAtomicStore32 1931 OpMIPSLoweredAtomicStorezero 1932 OpMIPSLoweredAtomicExchange 1933 OpMIPSLoweredAtomicAdd 1934 OpMIPSLoweredAtomicAddconst 1935 OpMIPSLoweredAtomicCas 1936 OpMIPSLoweredAtomicAnd 1937 OpMIPSLoweredAtomicOr 1938 OpMIPSLoweredZero 1939 OpMIPSLoweredMove 1940 OpMIPSLoweredNilCheck 1941 OpMIPSFPFlagTrue 1942 OpMIPSFPFlagFalse 1943 OpMIPSLoweredGetClosurePtr 1944 OpMIPSLoweredGetCallerSP 1945 OpMIPSLoweredGetCallerPC 1946 OpMIPSLoweredWB 1947 OpMIPSLoweredPanicBoundsA 1948 OpMIPSLoweredPanicBoundsB 1949 OpMIPSLoweredPanicBoundsC 1950 OpMIPSLoweredPanicExtendA 1951 OpMIPSLoweredPanicExtendB 1952 OpMIPSLoweredPanicExtendC 1953 1954 OpMIPS64ADDV 1955 OpMIPS64ADDVconst 1956 OpMIPS64SUBV 1957 OpMIPS64SUBVconst 1958 OpMIPS64MULV 1959 OpMIPS64MULVU 1960 OpMIPS64DIVV 1961 OpMIPS64DIVVU 1962 OpMIPS64ADDF 1963 OpMIPS64ADDD 1964 OpMIPS64SUBF 1965 OpMIPS64SUBD 1966 OpMIPS64MULF 1967 OpMIPS64MULD 1968 OpMIPS64DIVF 1969 OpMIPS64DIVD 1970 OpMIPS64AND 1971 OpMIPS64ANDconst 1972 OpMIPS64OR 1973 OpMIPS64ORconst 1974 OpMIPS64XOR 1975 OpMIPS64XORconst 1976 OpMIPS64NOR 1977 OpMIPS64NORconst 1978 OpMIPS64NEGV 1979 OpMIPS64NEGF 1980 OpMIPS64NEGD 1981 OpMIPS64SQRTD 1982 OpMIPS64SQRTF 1983 OpMIPS64SLLV 1984 OpMIPS64SLLVconst 1985 OpMIPS64SRLV 1986 OpMIPS64SRLVconst 1987 OpMIPS64SRAV 1988 OpMIPS64SRAVconst 1989 OpMIPS64SGT 1990 OpMIPS64SGTconst 1991 OpMIPS64SGTU 1992 OpMIPS64SGTUconst 1993 OpMIPS64CMPEQF 1994 OpMIPS64CMPEQD 1995 OpMIPS64CMPGEF 1996 OpMIPS64CMPGED 1997 OpMIPS64CMPGTF 1998 OpMIPS64CMPGTD 1999 OpMIPS64MOVVconst 2000 OpMIPS64MOVFconst 2001 OpMIPS64MOVDconst 2002 OpMIPS64MOVVaddr 2003 OpMIPS64MOVBload 2004 OpMIPS64MOVBUload 2005 OpMIPS64MOVHload 2006 OpMIPS64MOVHUload 2007 OpMIPS64MOVWload 2008 OpMIPS64MOVWUload 2009 OpMIPS64MOVVload 2010 OpMIPS64MOVFload 2011 OpMIPS64MOVDload 2012 OpMIPS64MOVBstore 2013 OpMIPS64MOVHstore 2014 OpMIPS64MOVWstore 2015 OpMIPS64MOVVstore 2016 OpMIPS64MOVFstore 2017 OpMIPS64MOVDstore 2018 OpMIPS64MOVBstorezero 2019 OpMIPS64MOVHstorezero 2020 OpMIPS64MOVWstorezero 2021 OpMIPS64MOVVstorezero 2022 OpMIPS64MOVBreg 2023 OpMIPS64MOVBUreg 2024 OpMIPS64MOVHreg 2025 OpMIPS64MOVHUreg 2026 OpMIPS64MOVWreg 2027 OpMIPS64MOVWUreg 2028 OpMIPS64MOVVreg 2029 OpMIPS64MOVVnop 2030 OpMIPS64MOVWF 2031 OpMIPS64MOVWD 2032 OpMIPS64MOVVF 2033 OpMIPS64MOVVD 2034 OpMIPS64TRUNCFW 2035 OpMIPS64TRUNCDW 2036 OpMIPS64TRUNCFV 2037 OpMIPS64TRUNCDV 2038 OpMIPS64MOVFD 2039 OpMIPS64MOVDF 2040 OpMIPS64CALLstatic 2041 OpMIPS64CALLtail 2042 OpMIPS64CALLclosure 2043 OpMIPS64CALLinter 2044 OpMIPS64DUFFZERO 2045 OpMIPS64DUFFCOPY 2046 OpMIPS64LoweredZero 2047 OpMIPS64LoweredMove 2048 OpMIPS64LoweredAtomicLoad8 2049 OpMIPS64LoweredAtomicLoad32 2050 OpMIPS64LoweredAtomicLoad64 2051 OpMIPS64LoweredAtomicStore8 2052 OpMIPS64LoweredAtomicStore32 2053 OpMIPS64LoweredAtomicStore64 2054 OpMIPS64LoweredAtomicStorezero32 2055 OpMIPS64LoweredAtomicStorezero64 2056 OpMIPS64LoweredAtomicExchange32 2057 OpMIPS64LoweredAtomicExchange64 2058 OpMIPS64LoweredAtomicAdd32 2059 OpMIPS64LoweredAtomicAdd64 2060 OpMIPS64LoweredAtomicAddconst32 2061 OpMIPS64LoweredAtomicAddconst64 2062 OpMIPS64LoweredAtomicCas32 2063 OpMIPS64LoweredAtomicCas64 2064 OpMIPS64LoweredNilCheck 2065 OpMIPS64FPFlagTrue 2066 OpMIPS64FPFlagFalse 2067 OpMIPS64LoweredGetClosurePtr 2068 OpMIPS64LoweredGetCallerSP 2069 OpMIPS64LoweredGetCallerPC 2070 OpMIPS64LoweredWB 2071 OpMIPS64LoweredPanicBoundsA 2072 OpMIPS64LoweredPanicBoundsB 2073 OpMIPS64LoweredPanicBoundsC 2074 2075 OpPPC64ADD 2076 OpPPC64ADDconst 2077 OpPPC64FADD 2078 OpPPC64FADDS 2079 OpPPC64SUB 2080 OpPPC64SUBFCconst 2081 OpPPC64FSUB 2082 OpPPC64FSUBS 2083 OpPPC64MULLD 2084 OpPPC64MULLW 2085 OpPPC64MULLDconst 2086 OpPPC64MULLWconst 2087 OpPPC64MADDLD 2088 OpPPC64MULHD 2089 OpPPC64MULHW 2090 OpPPC64MULHDU 2091 OpPPC64MULHWU 2092 OpPPC64FMUL 2093 OpPPC64FMULS 2094 OpPPC64FMADD 2095 OpPPC64FMADDS 2096 OpPPC64FMSUB 2097 OpPPC64FMSUBS 2098 OpPPC64SRAD 2099 OpPPC64SRAW 2100 OpPPC64SRD 2101 OpPPC64SRW 2102 OpPPC64SLD 2103 OpPPC64SLW 2104 OpPPC64ROTL 2105 OpPPC64ROTLW 2106 OpPPC64RLDICL 2107 OpPPC64CLRLSLWI 2108 OpPPC64CLRLSLDI 2109 OpPPC64ADDC 2110 OpPPC64SUBC 2111 OpPPC64ADDCconst 2112 OpPPC64SUBCconst 2113 OpPPC64ADDE 2114 OpPPC64SUBE 2115 OpPPC64ADDZEzero 2116 OpPPC64SUBZEzero 2117 OpPPC64SRADconst 2118 OpPPC64SRAWconst 2119 OpPPC64SRDconst 2120 OpPPC64SRWconst 2121 OpPPC64SLDconst 2122 OpPPC64SLWconst 2123 OpPPC64ROTLconst 2124 OpPPC64ROTLWconst 2125 OpPPC64EXTSWSLconst 2126 OpPPC64RLWINM 2127 OpPPC64RLWNM 2128 OpPPC64RLWMI 2129 OpPPC64CNTLZD 2130 OpPPC64CNTLZW 2131 OpPPC64CNTTZD 2132 OpPPC64CNTTZW 2133 OpPPC64POPCNTD 2134 OpPPC64POPCNTW 2135 OpPPC64POPCNTB 2136 OpPPC64FDIV 2137 OpPPC64FDIVS 2138 OpPPC64DIVD 2139 OpPPC64DIVW 2140 OpPPC64DIVDU 2141 OpPPC64DIVWU 2142 OpPPC64MODUD 2143 OpPPC64MODSD 2144 OpPPC64MODUW 2145 OpPPC64MODSW 2146 OpPPC64FCTIDZ 2147 OpPPC64FCTIWZ 2148 OpPPC64FCFID 2149 OpPPC64FCFIDS 2150 OpPPC64FRSP 2151 OpPPC64MFVSRD 2152 OpPPC64MTVSRD 2153 OpPPC64AND 2154 OpPPC64ANDN 2155 OpPPC64ANDCC 2156 OpPPC64OR 2157 OpPPC64ORN 2158 OpPPC64ORCC 2159 OpPPC64NOR 2160 OpPPC64XOR 2161 OpPPC64XORCC 2162 OpPPC64EQV 2163 OpPPC64NEG 2164 OpPPC64FNEG 2165 OpPPC64FSQRT 2166 OpPPC64FSQRTS 2167 OpPPC64FFLOOR 2168 OpPPC64FCEIL 2169 OpPPC64FTRUNC 2170 OpPPC64FROUND 2171 OpPPC64FABS 2172 OpPPC64FNABS 2173 OpPPC64FCPSGN 2174 OpPPC64ORconst 2175 OpPPC64XORconst 2176 OpPPC64ANDCCconst 2177 OpPPC64MOVBreg 2178 OpPPC64MOVBZreg 2179 OpPPC64MOVHreg 2180 OpPPC64MOVHZreg 2181 OpPPC64MOVWreg 2182 OpPPC64MOVWZreg 2183 OpPPC64MOVBZload 2184 OpPPC64MOVHload 2185 OpPPC64MOVHZload 2186 OpPPC64MOVWload 2187 OpPPC64MOVWZload 2188 OpPPC64MOVDload 2189 OpPPC64MOVDBRload 2190 OpPPC64MOVWBRload 2191 OpPPC64MOVHBRload 2192 OpPPC64MOVBZloadidx 2193 OpPPC64MOVHloadidx 2194 OpPPC64MOVHZloadidx 2195 OpPPC64MOVWloadidx 2196 OpPPC64MOVWZloadidx 2197 OpPPC64MOVDloadidx 2198 OpPPC64MOVHBRloadidx 2199 OpPPC64MOVWBRloadidx 2200 OpPPC64MOVDBRloadidx 2201 OpPPC64FMOVDloadidx 2202 OpPPC64FMOVSloadidx 2203 OpPPC64DCBT 2204 OpPPC64MOVDBRstore 2205 OpPPC64MOVWBRstore 2206 OpPPC64MOVHBRstore 2207 OpPPC64FMOVDload 2208 OpPPC64FMOVSload 2209 OpPPC64MOVBstore 2210 OpPPC64MOVHstore 2211 OpPPC64MOVWstore 2212 OpPPC64MOVDstore 2213 OpPPC64FMOVDstore 2214 OpPPC64FMOVSstore 2215 OpPPC64MOVBstoreidx 2216 OpPPC64MOVHstoreidx 2217 OpPPC64MOVWstoreidx 2218 OpPPC64MOVDstoreidx 2219 OpPPC64FMOVDstoreidx 2220 OpPPC64FMOVSstoreidx 2221 OpPPC64MOVHBRstoreidx 2222 OpPPC64MOVWBRstoreidx 2223 OpPPC64MOVDBRstoreidx 2224 OpPPC64MOVBstorezero 2225 OpPPC64MOVHstorezero 2226 OpPPC64MOVWstorezero 2227 OpPPC64MOVDstorezero 2228 OpPPC64MOVDaddr 2229 OpPPC64MOVDconst 2230 OpPPC64FMOVDconst 2231 OpPPC64FMOVSconst 2232 OpPPC64FCMPU 2233 OpPPC64CMP 2234 OpPPC64CMPU 2235 OpPPC64CMPW 2236 OpPPC64CMPWU 2237 OpPPC64CMPconst 2238 OpPPC64CMPUconst 2239 OpPPC64CMPWconst 2240 OpPPC64CMPWUconst 2241 OpPPC64ISEL 2242 OpPPC64ISELB 2243 OpPPC64ISELZ 2244 OpPPC64Equal 2245 OpPPC64NotEqual 2246 OpPPC64LessThan 2247 OpPPC64FLessThan 2248 OpPPC64LessEqual 2249 OpPPC64FLessEqual 2250 OpPPC64GreaterThan 2251 OpPPC64FGreaterThan 2252 OpPPC64GreaterEqual 2253 OpPPC64FGreaterEqual 2254 OpPPC64LoweredGetClosurePtr 2255 OpPPC64LoweredGetCallerSP 2256 OpPPC64LoweredGetCallerPC 2257 OpPPC64LoweredNilCheck 2258 OpPPC64LoweredRound32F 2259 OpPPC64LoweredRound64F 2260 OpPPC64CALLstatic 2261 OpPPC64CALLtail 2262 OpPPC64CALLclosure 2263 OpPPC64CALLinter 2264 OpPPC64LoweredZero 2265 OpPPC64LoweredZeroShort 2266 OpPPC64LoweredQuadZeroShort 2267 OpPPC64LoweredQuadZero 2268 OpPPC64LoweredMove 2269 OpPPC64LoweredMoveShort 2270 OpPPC64LoweredQuadMove 2271 OpPPC64LoweredQuadMoveShort 2272 OpPPC64LoweredAtomicStore8 2273 OpPPC64LoweredAtomicStore32 2274 OpPPC64LoweredAtomicStore64 2275 OpPPC64LoweredAtomicLoad8 2276 OpPPC64LoweredAtomicLoad32 2277 OpPPC64LoweredAtomicLoad64 2278 OpPPC64LoweredAtomicLoadPtr 2279 OpPPC64LoweredAtomicAdd32 2280 OpPPC64LoweredAtomicAdd64 2281 OpPPC64LoweredAtomicExchange32 2282 OpPPC64LoweredAtomicExchange64 2283 OpPPC64LoweredAtomicCas64 2284 OpPPC64LoweredAtomicCas32 2285 OpPPC64LoweredAtomicAnd8 2286 OpPPC64LoweredAtomicAnd32 2287 OpPPC64LoweredAtomicOr8 2288 OpPPC64LoweredAtomicOr32 2289 OpPPC64LoweredWB 2290 OpPPC64LoweredPubBarrier 2291 OpPPC64LoweredPanicBoundsA 2292 OpPPC64LoweredPanicBoundsB 2293 OpPPC64LoweredPanicBoundsC 2294 OpPPC64InvertFlags 2295 OpPPC64FlagEQ 2296 OpPPC64FlagLT 2297 OpPPC64FlagGT 2298 2299 OpRISCV64ADD 2300 OpRISCV64ADDI 2301 OpRISCV64ADDIW 2302 OpRISCV64NEG 2303 OpRISCV64NEGW 2304 OpRISCV64SUB 2305 OpRISCV64SUBW 2306 OpRISCV64MUL 2307 OpRISCV64MULW 2308 OpRISCV64MULH 2309 OpRISCV64MULHU 2310 OpRISCV64LoweredMuluhilo 2311 OpRISCV64LoweredMuluover 2312 OpRISCV64DIV 2313 OpRISCV64DIVU 2314 OpRISCV64DIVW 2315 OpRISCV64DIVUW 2316 OpRISCV64REM 2317 OpRISCV64REMU 2318 OpRISCV64REMW 2319 OpRISCV64REMUW 2320 OpRISCV64MOVaddr 2321 OpRISCV64MOVDconst 2322 OpRISCV64MOVBload 2323 OpRISCV64MOVHload 2324 OpRISCV64MOVWload 2325 OpRISCV64MOVDload 2326 OpRISCV64MOVBUload 2327 OpRISCV64MOVHUload 2328 OpRISCV64MOVWUload 2329 OpRISCV64MOVBstore 2330 OpRISCV64MOVHstore 2331 OpRISCV64MOVWstore 2332 OpRISCV64MOVDstore 2333 OpRISCV64MOVBstorezero 2334 OpRISCV64MOVHstorezero 2335 OpRISCV64MOVWstorezero 2336 OpRISCV64MOVDstorezero 2337 OpRISCV64MOVBreg 2338 OpRISCV64MOVHreg 2339 OpRISCV64MOVWreg 2340 OpRISCV64MOVDreg 2341 OpRISCV64MOVBUreg 2342 OpRISCV64MOVHUreg 2343 OpRISCV64MOVWUreg 2344 OpRISCV64MOVDnop 2345 OpRISCV64SLL 2346 OpRISCV64SRA 2347 OpRISCV64SRL 2348 OpRISCV64SLLI 2349 OpRISCV64SRAI 2350 OpRISCV64SRLI 2351 OpRISCV64XOR 2352 OpRISCV64XORI 2353 OpRISCV64OR 2354 OpRISCV64ORI 2355 OpRISCV64AND 2356 OpRISCV64ANDI 2357 OpRISCV64NOT 2358 OpRISCV64SEQZ 2359 OpRISCV64SNEZ 2360 OpRISCV64SLT 2361 OpRISCV64SLTI 2362 OpRISCV64SLTU 2363 OpRISCV64SLTIU 2364 OpRISCV64MOVconvert 2365 OpRISCV64CALLstatic 2366 OpRISCV64CALLtail 2367 OpRISCV64CALLclosure 2368 OpRISCV64CALLinter 2369 OpRISCV64DUFFZERO 2370 OpRISCV64DUFFCOPY 2371 OpRISCV64LoweredZero 2372 OpRISCV64LoweredMove 2373 OpRISCV64LoweredAtomicLoad8 2374 OpRISCV64LoweredAtomicLoad32 2375 OpRISCV64LoweredAtomicLoad64 2376 OpRISCV64LoweredAtomicStore8 2377 OpRISCV64LoweredAtomicStore32 2378 OpRISCV64LoweredAtomicStore64 2379 OpRISCV64LoweredAtomicExchange32 2380 OpRISCV64LoweredAtomicExchange64 2381 OpRISCV64LoweredAtomicAdd32 2382 OpRISCV64LoweredAtomicAdd64 2383 OpRISCV64LoweredAtomicCas32 2384 OpRISCV64LoweredAtomicCas64 2385 OpRISCV64LoweredAtomicAnd32 2386 OpRISCV64LoweredAtomicOr32 2387 OpRISCV64LoweredNilCheck 2388 OpRISCV64LoweredGetClosurePtr 2389 OpRISCV64LoweredGetCallerSP 2390 OpRISCV64LoweredGetCallerPC 2391 OpRISCV64LoweredWB 2392 OpRISCV64LoweredPanicBoundsA 2393 OpRISCV64LoweredPanicBoundsB 2394 OpRISCV64LoweredPanicBoundsC 2395 OpRISCV64FADDS 2396 OpRISCV64FSUBS 2397 OpRISCV64FMULS 2398 OpRISCV64FDIVS 2399 OpRISCV64FSQRTS 2400 OpRISCV64FNEGS 2401 OpRISCV64FMVSX 2402 OpRISCV64FCVTSW 2403 OpRISCV64FCVTSL 2404 OpRISCV64FCVTWS 2405 OpRISCV64FCVTLS 2406 OpRISCV64FMOVWload 2407 OpRISCV64FMOVWstore 2408 OpRISCV64FEQS 2409 OpRISCV64FNES 2410 OpRISCV64FLTS 2411 OpRISCV64FLES 2412 OpRISCV64FADDD 2413 OpRISCV64FSUBD 2414 OpRISCV64FMULD 2415 OpRISCV64FDIVD 2416 OpRISCV64FMADDD 2417 OpRISCV64FMSUBD 2418 OpRISCV64FNMADDD 2419 OpRISCV64FNMSUBD 2420 OpRISCV64FSQRTD 2421 OpRISCV64FNEGD 2422 OpRISCV64FABSD 2423 OpRISCV64FSGNJD 2424 OpRISCV64FMVDX 2425 OpRISCV64FCVTDW 2426 OpRISCV64FCVTDL 2427 OpRISCV64FCVTWD 2428 OpRISCV64FCVTLD 2429 OpRISCV64FCVTDS 2430 OpRISCV64FCVTSD 2431 OpRISCV64FMOVDload 2432 OpRISCV64FMOVDstore 2433 OpRISCV64FEQD 2434 OpRISCV64FNED 2435 OpRISCV64FLTD 2436 OpRISCV64FLED 2437 2438 OpS390XFADDS 2439 OpS390XFADD 2440 OpS390XFSUBS 2441 OpS390XFSUB 2442 OpS390XFMULS 2443 OpS390XFMUL 2444 OpS390XFDIVS 2445 OpS390XFDIV 2446 OpS390XFNEGS 2447 OpS390XFNEG 2448 OpS390XFMADDS 2449 OpS390XFMADD 2450 OpS390XFMSUBS 2451 OpS390XFMSUB 2452 OpS390XLPDFR 2453 OpS390XLNDFR 2454 OpS390XCPSDR 2455 OpS390XFIDBR 2456 OpS390XFMOVSload 2457 OpS390XFMOVDload 2458 OpS390XFMOVSconst 2459 OpS390XFMOVDconst 2460 OpS390XFMOVSloadidx 2461 OpS390XFMOVDloadidx 2462 OpS390XFMOVSstore 2463 OpS390XFMOVDstore 2464 OpS390XFMOVSstoreidx 2465 OpS390XFMOVDstoreidx 2466 OpS390XADD 2467 OpS390XADDW 2468 OpS390XADDconst 2469 OpS390XADDWconst 2470 OpS390XADDload 2471 OpS390XADDWload 2472 OpS390XSUB 2473 OpS390XSUBW 2474 OpS390XSUBconst 2475 OpS390XSUBWconst 2476 OpS390XSUBload 2477 OpS390XSUBWload 2478 OpS390XMULLD 2479 OpS390XMULLW 2480 OpS390XMULLDconst 2481 OpS390XMULLWconst 2482 OpS390XMULLDload 2483 OpS390XMULLWload 2484 OpS390XMULHD 2485 OpS390XMULHDU 2486 OpS390XDIVD 2487 OpS390XDIVW 2488 OpS390XDIVDU 2489 OpS390XDIVWU 2490 OpS390XMODD 2491 OpS390XMODW 2492 OpS390XMODDU 2493 OpS390XMODWU 2494 OpS390XAND 2495 OpS390XANDW 2496 OpS390XANDconst 2497 OpS390XANDWconst 2498 OpS390XANDload 2499 OpS390XANDWload 2500 OpS390XOR 2501 OpS390XORW 2502 OpS390XORconst 2503 OpS390XORWconst 2504 OpS390XORload 2505 OpS390XORWload 2506 OpS390XXOR 2507 OpS390XXORW 2508 OpS390XXORconst 2509 OpS390XXORWconst 2510 OpS390XXORload 2511 OpS390XXORWload 2512 OpS390XADDC 2513 OpS390XADDCconst 2514 OpS390XADDE 2515 OpS390XSUBC 2516 OpS390XSUBE 2517 OpS390XCMP 2518 OpS390XCMPW 2519 OpS390XCMPU 2520 OpS390XCMPWU 2521 OpS390XCMPconst 2522 OpS390XCMPWconst 2523 OpS390XCMPUconst 2524 OpS390XCMPWUconst 2525 OpS390XFCMPS 2526 OpS390XFCMP 2527 OpS390XLTDBR 2528 OpS390XLTEBR 2529 OpS390XSLD 2530 OpS390XSLW 2531 OpS390XSLDconst 2532 OpS390XSLWconst 2533 OpS390XSRD 2534 OpS390XSRW 2535 OpS390XSRDconst 2536 OpS390XSRWconst 2537 OpS390XSRAD 2538 OpS390XSRAW 2539 OpS390XSRADconst 2540 OpS390XSRAWconst 2541 OpS390XRLLG 2542 OpS390XRLL 2543 OpS390XRLLconst 2544 OpS390XRXSBG 2545 OpS390XRISBGZ 2546 OpS390XNEG 2547 OpS390XNEGW 2548 OpS390XNOT 2549 OpS390XNOTW 2550 OpS390XFSQRT 2551 OpS390XFSQRTS 2552 OpS390XLOCGR 2553 OpS390XMOVBreg 2554 OpS390XMOVBZreg 2555 OpS390XMOVHreg 2556 OpS390XMOVHZreg 2557 OpS390XMOVWreg 2558 OpS390XMOVWZreg 2559 OpS390XMOVDconst 2560 OpS390XLDGR 2561 OpS390XLGDR 2562 OpS390XCFDBRA 2563 OpS390XCGDBRA 2564 OpS390XCFEBRA 2565 OpS390XCGEBRA 2566 OpS390XCEFBRA 2567 OpS390XCDFBRA 2568 OpS390XCEGBRA 2569 OpS390XCDGBRA 2570 OpS390XCLFEBR 2571 OpS390XCLFDBR 2572 OpS390XCLGEBR 2573 OpS390XCLGDBR 2574 OpS390XCELFBR 2575 OpS390XCDLFBR 2576 OpS390XCELGBR 2577 OpS390XCDLGBR 2578 OpS390XLEDBR 2579 OpS390XLDEBR 2580 OpS390XMOVDaddr 2581 OpS390XMOVDaddridx 2582 OpS390XMOVBZload 2583 OpS390XMOVBload 2584 OpS390XMOVHZload 2585 OpS390XMOVHload 2586 OpS390XMOVWZload 2587 OpS390XMOVWload 2588 OpS390XMOVDload 2589 OpS390XMOVWBR 2590 OpS390XMOVDBR 2591 OpS390XMOVHBRload 2592 OpS390XMOVWBRload 2593 OpS390XMOVDBRload 2594 OpS390XMOVBstore 2595 OpS390XMOVHstore 2596 OpS390XMOVWstore 2597 OpS390XMOVDstore 2598 OpS390XMOVHBRstore 2599 OpS390XMOVWBRstore 2600 OpS390XMOVDBRstore 2601 OpS390XMVC 2602 OpS390XMOVBZloadidx 2603 OpS390XMOVBloadidx 2604 OpS390XMOVHZloadidx 2605 OpS390XMOVHloadidx 2606 OpS390XMOVWZloadidx 2607 OpS390XMOVWloadidx 2608 OpS390XMOVDloadidx 2609 OpS390XMOVHBRloadidx 2610 OpS390XMOVWBRloadidx 2611 OpS390XMOVDBRloadidx 2612 OpS390XMOVBstoreidx 2613 OpS390XMOVHstoreidx 2614 OpS390XMOVWstoreidx 2615 OpS390XMOVDstoreidx 2616 OpS390XMOVHBRstoreidx 2617 OpS390XMOVWBRstoreidx 2618 OpS390XMOVDBRstoreidx 2619 OpS390XMOVBstoreconst 2620 OpS390XMOVHstoreconst 2621 OpS390XMOVWstoreconst 2622 OpS390XMOVDstoreconst 2623 OpS390XCLEAR 2624 OpS390XCALLstatic 2625 OpS390XCALLtail 2626 OpS390XCALLclosure 2627 OpS390XCALLinter 2628 OpS390XInvertFlags 2629 OpS390XLoweredGetG 2630 OpS390XLoweredGetClosurePtr 2631 OpS390XLoweredGetCallerSP 2632 OpS390XLoweredGetCallerPC 2633 OpS390XLoweredNilCheck 2634 OpS390XLoweredRound32F 2635 OpS390XLoweredRound64F 2636 OpS390XLoweredWB 2637 OpS390XLoweredPanicBoundsA 2638 OpS390XLoweredPanicBoundsB 2639 OpS390XLoweredPanicBoundsC 2640 OpS390XFlagEQ 2641 OpS390XFlagLT 2642 OpS390XFlagGT 2643 OpS390XFlagOV 2644 OpS390XSYNC 2645 OpS390XMOVBZatomicload 2646 OpS390XMOVWZatomicload 2647 OpS390XMOVDatomicload 2648 OpS390XMOVBatomicstore 2649 OpS390XMOVWatomicstore 2650 OpS390XMOVDatomicstore 2651 OpS390XLAA 2652 OpS390XLAAG 2653 OpS390XAddTupleFirst32 2654 OpS390XAddTupleFirst64 2655 OpS390XLAN 2656 OpS390XLANfloor 2657 OpS390XLAO 2658 OpS390XLAOfloor 2659 OpS390XLoweredAtomicCas32 2660 OpS390XLoweredAtomicCas64 2661 OpS390XLoweredAtomicExchange32 2662 OpS390XLoweredAtomicExchange64 2663 OpS390XFLOGR 2664 OpS390XPOPCNT 2665 OpS390XMLGR 2666 OpS390XSumBytes2 2667 OpS390XSumBytes4 2668 OpS390XSumBytes8 2669 OpS390XSTMG2 2670 OpS390XSTMG3 2671 OpS390XSTMG4 2672 OpS390XSTM2 2673 OpS390XSTM3 2674 OpS390XSTM4 2675 OpS390XLoweredMove 2676 OpS390XLoweredZero 2677 2678 OpWasmLoweredStaticCall 2679 OpWasmLoweredTailCall 2680 OpWasmLoweredClosureCall 2681 OpWasmLoweredInterCall 2682 OpWasmLoweredAddr 2683 OpWasmLoweredMove 2684 OpWasmLoweredZero 2685 OpWasmLoweredGetClosurePtr 2686 OpWasmLoweredGetCallerPC 2687 OpWasmLoweredGetCallerSP 2688 OpWasmLoweredNilCheck 2689 OpWasmLoweredWB 2690 OpWasmLoweredConvert 2691 OpWasmSelect 2692 OpWasmI64Load8U 2693 OpWasmI64Load8S 2694 OpWasmI64Load16U 2695 OpWasmI64Load16S 2696 OpWasmI64Load32U 2697 OpWasmI64Load32S 2698 OpWasmI64Load 2699 OpWasmI64Store8 2700 OpWasmI64Store16 2701 OpWasmI64Store32 2702 OpWasmI64Store 2703 OpWasmF32Load 2704 OpWasmF64Load 2705 OpWasmF32Store 2706 OpWasmF64Store 2707 OpWasmI64Const 2708 OpWasmF32Const 2709 OpWasmF64Const 2710 OpWasmI64Eqz 2711 OpWasmI64Eq 2712 OpWasmI64Ne 2713 OpWasmI64LtS 2714 OpWasmI64LtU 2715 OpWasmI64GtS 2716 OpWasmI64GtU 2717 OpWasmI64LeS 2718 OpWasmI64LeU 2719 OpWasmI64GeS 2720 OpWasmI64GeU 2721 OpWasmF32Eq 2722 OpWasmF32Ne 2723 OpWasmF32Lt 2724 OpWasmF32Gt 2725 OpWasmF32Le 2726 OpWasmF32Ge 2727 OpWasmF64Eq 2728 OpWasmF64Ne 2729 OpWasmF64Lt 2730 OpWasmF64Gt 2731 OpWasmF64Le 2732 OpWasmF64Ge 2733 OpWasmI64Add 2734 OpWasmI64AddConst 2735 OpWasmI64Sub 2736 OpWasmI64Mul 2737 OpWasmI64DivS 2738 OpWasmI64DivU 2739 OpWasmI64RemS 2740 OpWasmI64RemU 2741 OpWasmI64And 2742 OpWasmI64Or 2743 OpWasmI64Xor 2744 OpWasmI64Shl 2745 OpWasmI64ShrS 2746 OpWasmI64ShrU 2747 OpWasmF32Neg 2748 OpWasmF32Add 2749 OpWasmF32Sub 2750 OpWasmF32Mul 2751 OpWasmF32Div 2752 OpWasmF64Neg 2753 OpWasmF64Add 2754 OpWasmF64Sub 2755 OpWasmF64Mul 2756 OpWasmF64Div 2757 OpWasmI64TruncSatF64S 2758 OpWasmI64TruncSatF64U 2759 OpWasmI64TruncSatF32S 2760 OpWasmI64TruncSatF32U 2761 OpWasmF32ConvertI64S 2762 OpWasmF32ConvertI64U 2763 OpWasmF64ConvertI64S 2764 OpWasmF64ConvertI64U 2765 OpWasmF32DemoteF64 2766 OpWasmF64PromoteF32 2767 OpWasmI64Extend8S 2768 OpWasmI64Extend16S 2769 OpWasmI64Extend32S 2770 OpWasmF32Sqrt 2771 OpWasmF32Trunc 2772 OpWasmF32Ceil 2773 OpWasmF32Floor 2774 OpWasmF32Nearest 2775 OpWasmF32Abs 2776 OpWasmF32Copysign 2777 OpWasmF64Sqrt 2778 OpWasmF64Trunc 2779 OpWasmF64Ceil 2780 OpWasmF64Floor 2781 OpWasmF64Nearest 2782 OpWasmF64Abs 2783 OpWasmF64Copysign 2784 OpWasmI64Ctz 2785 OpWasmI64Clz 2786 OpWasmI32Rotl 2787 OpWasmI64Rotl 2788 OpWasmI64Popcnt 2789 2790 OpAdd8 2791 OpAdd16 2792 OpAdd32 2793 OpAdd64 2794 OpAddPtr 2795 OpAdd32F 2796 OpAdd64F 2797 OpSub8 2798 OpSub16 2799 OpSub32 2800 OpSub64 2801 OpSubPtr 2802 OpSub32F 2803 OpSub64F 2804 OpMul8 2805 OpMul16 2806 OpMul32 2807 OpMul64 2808 OpMul32F 2809 OpMul64F 2810 OpDiv32F 2811 OpDiv64F 2812 OpHmul32 2813 OpHmul32u 2814 OpHmul64 2815 OpHmul64u 2816 OpMul32uhilo 2817 OpMul64uhilo 2818 OpMul32uover 2819 OpMul64uover 2820 OpAvg32u 2821 OpAvg64u 2822 OpDiv8 2823 OpDiv8u 2824 OpDiv16 2825 OpDiv16u 2826 OpDiv32 2827 OpDiv32u 2828 OpDiv64 2829 OpDiv64u 2830 OpDiv128u 2831 OpMod8 2832 OpMod8u 2833 OpMod16 2834 OpMod16u 2835 OpMod32 2836 OpMod32u 2837 OpMod64 2838 OpMod64u 2839 OpAnd8 2840 OpAnd16 2841 OpAnd32 2842 OpAnd64 2843 OpOr8 2844 OpOr16 2845 OpOr32 2846 OpOr64 2847 OpXor8 2848 OpXor16 2849 OpXor32 2850 OpXor64 2851 OpLsh8x8 2852 OpLsh8x16 2853 OpLsh8x32 2854 OpLsh8x64 2855 OpLsh16x8 2856 OpLsh16x16 2857 OpLsh16x32 2858 OpLsh16x64 2859 OpLsh32x8 2860 OpLsh32x16 2861 OpLsh32x32 2862 OpLsh32x64 2863 OpLsh64x8 2864 OpLsh64x16 2865 OpLsh64x32 2866 OpLsh64x64 2867 OpRsh8x8 2868 OpRsh8x16 2869 OpRsh8x32 2870 OpRsh8x64 2871 OpRsh16x8 2872 OpRsh16x16 2873 OpRsh16x32 2874 OpRsh16x64 2875 OpRsh32x8 2876 OpRsh32x16 2877 OpRsh32x32 2878 OpRsh32x64 2879 OpRsh64x8 2880 OpRsh64x16 2881 OpRsh64x32 2882 OpRsh64x64 2883 OpRsh8Ux8 2884 OpRsh8Ux16 2885 OpRsh8Ux32 2886 OpRsh8Ux64 2887 OpRsh16Ux8 2888 OpRsh16Ux16 2889 OpRsh16Ux32 2890 OpRsh16Ux64 2891 OpRsh32Ux8 2892 OpRsh32Ux16 2893 OpRsh32Ux32 2894 OpRsh32Ux64 2895 OpRsh64Ux8 2896 OpRsh64Ux16 2897 OpRsh64Ux32 2898 OpRsh64Ux64 2899 OpEq8 2900 OpEq16 2901 OpEq32 2902 OpEq64 2903 OpEqPtr 2904 OpEqInter 2905 OpEqSlice 2906 OpEq32F 2907 OpEq64F 2908 OpNeq8 2909 OpNeq16 2910 OpNeq32 2911 OpNeq64 2912 OpNeqPtr 2913 OpNeqInter 2914 OpNeqSlice 2915 OpNeq32F 2916 OpNeq64F 2917 OpLess8 2918 OpLess8U 2919 OpLess16 2920 OpLess16U 2921 OpLess32 2922 OpLess32U 2923 OpLess64 2924 OpLess64U 2925 OpLess32F 2926 OpLess64F 2927 OpLeq8 2928 OpLeq8U 2929 OpLeq16 2930 OpLeq16U 2931 OpLeq32 2932 OpLeq32U 2933 OpLeq64 2934 OpLeq64U 2935 OpLeq32F 2936 OpLeq64F 2937 OpCondSelect 2938 OpAndB 2939 OpOrB 2940 OpEqB 2941 OpNeqB 2942 OpNot 2943 OpNeg8 2944 OpNeg16 2945 OpNeg32 2946 OpNeg64 2947 OpNeg32F 2948 OpNeg64F 2949 OpCom8 2950 OpCom16 2951 OpCom32 2952 OpCom64 2953 OpCtz8 2954 OpCtz16 2955 OpCtz32 2956 OpCtz64 2957 OpCtz8NonZero 2958 OpCtz16NonZero 2959 OpCtz32NonZero 2960 OpCtz64NonZero 2961 OpBitLen8 2962 OpBitLen16 2963 OpBitLen32 2964 OpBitLen64 2965 OpBswap32 2966 OpBswap64 2967 OpBitRev8 2968 OpBitRev16 2969 OpBitRev32 2970 OpBitRev64 2971 OpPopCount8 2972 OpPopCount16 2973 OpPopCount32 2974 OpPopCount64 2975 OpRotateLeft64 2976 OpRotateLeft32 2977 OpRotateLeft16 2978 OpRotateLeft8 2979 OpSqrt 2980 OpSqrt32 2981 OpFloor 2982 OpCeil 2983 OpTrunc 2984 OpRound 2985 OpRoundToEven 2986 OpAbs 2987 OpCopysign 2988 OpFMA 2989 OpPhi 2990 OpCopy 2991 OpConvert 2992 OpConstBool 2993 OpConstString 2994 OpConstNil 2995 OpConst8 2996 OpConst16 2997 OpConst32 2998 OpConst64 2999 OpConst32F 3000 OpConst64F 3001 OpConstInterface 3002 OpConstSlice 3003 OpInitMem 3004 OpArg 3005 OpArgIntReg 3006 OpArgFloatReg 3007 OpAddr 3008 OpLocalAddr 3009 OpSP 3010 OpSB 3011 OpLoad 3012 OpDereference 3013 OpStore 3014 OpMove 3015 OpZero 3016 OpStoreWB 3017 OpMoveWB 3018 OpZeroWB 3019 OpWB 3020 OpHasCPUFeature 3021 OpPanicBounds 3022 OpPanicExtend 3023 OpClosureCall 3024 OpStaticCall 3025 OpInterCall 3026 OpTailCall 3027 OpClosureLECall 3028 OpStaticLECall 3029 OpInterLECall 3030 OpTailLECall 3031 OpSignExt8to16 3032 OpSignExt8to32 3033 OpSignExt8to64 3034 OpSignExt16to32 3035 OpSignExt16to64 3036 OpSignExt32to64 3037 OpZeroExt8to16 3038 OpZeroExt8to32 3039 OpZeroExt8to64 3040 OpZeroExt16to32 3041 OpZeroExt16to64 3042 OpZeroExt32to64 3043 OpTrunc16to8 3044 OpTrunc32to8 3045 OpTrunc32to16 3046 OpTrunc64to8 3047 OpTrunc64to16 3048 OpTrunc64to32 3049 OpCvt32to32F 3050 OpCvt32to64F 3051 OpCvt64to32F 3052 OpCvt64to64F 3053 OpCvt32Fto32 3054 OpCvt32Fto64 3055 OpCvt64Fto32 3056 OpCvt64Fto64 3057 OpCvt32Fto64F 3058 OpCvt64Fto32F 3059 OpCvtBoolToUint8 3060 OpRound32F 3061 OpRound64F 3062 OpIsNonNil 3063 OpIsInBounds 3064 OpIsSliceInBounds 3065 OpNilCheck 3066 OpGetG 3067 OpGetClosurePtr 3068 OpGetCallerPC 3069 OpGetCallerSP 3070 OpPtrIndex 3071 OpOffPtr 3072 OpSliceMake 3073 OpSlicePtr 3074 OpSliceLen 3075 OpSliceCap 3076 OpSlicePtrUnchecked 3077 OpComplexMake 3078 OpComplexReal 3079 OpComplexImag 3080 OpStringMake 3081 OpStringPtr 3082 OpStringLen 3083 OpIMake 3084 OpITab 3085 OpIData 3086 OpStructMake0 3087 OpStructMake1 3088 OpStructMake2 3089 OpStructMake3 3090 OpStructMake4 3091 OpStructSelect 3092 OpArrayMake0 3093 OpArrayMake1 3094 OpArraySelect 3095 OpStoreReg 3096 OpLoadReg 3097 OpFwdRef 3098 OpUnknown 3099 OpVarDef 3100 OpVarLive 3101 OpKeepAlive 3102 OpInlMark 3103 OpInt64Make 3104 OpInt64Hi 3105 OpInt64Lo 3106 OpAdd32carry 3107 OpAdd32withcarry 3108 OpSub32carry 3109 OpSub32withcarry 3110 OpAdd64carry 3111 OpSub64borrow 3112 OpSignmask 3113 OpZeromask 3114 OpSlicemask 3115 OpSpectreIndex 3116 OpSpectreSliceIndex 3117 OpCvt32Uto32F 3118 OpCvt32Uto64F 3119 OpCvt32Fto32U 3120 OpCvt64Fto32U 3121 OpCvt64Uto32F 3122 OpCvt64Uto64F 3123 OpCvt32Fto64U 3124 OpCvt64Fto64U 3125 OpSelect0 3126 OpSelect1 3127 OpSelectN 3128 OpSelectNAddr 3129 OpMakeResult 3130 OpAtomicLoad8 3131 OpAtomicLoad32 3132 OpAtomicLoad64 3133 OpAtomicLoadPtr 3134 OpAtomicLoadAcq32 3135 OpAtomicLoadAcq64 3136 OpAtomicStore8 3137 OpAtomicStore32 3138 OpAtomicStore64 3139 OpAtomicStorePtrNoWB 3140 OpAtomicStoreRel32 3141 OpAtomicStoreRel64 3142 OpAtomicExchange32 3143 OpAtomicExchange64 3144 OpAtomicAdd32 3145 OpAtomicAdd64 3146 OpAtomicCompareAndSwap32 3147 OpAtomicCompareAndSwap64 3148 OpAtomicCompareAndSwapRel32 3149 OpAtomicAnd8 3150 OpAtomicAnd32 3151 OpAtomicOr8 3152 OpAtomicOr32 3153 OpAtomicAdd32Variant 3154 OpAtomicAdd64Variant 3155 OpAtomicExchange32Variant 3156 OpAtomicExchange64Variant 3157 OpAtomicCompareAndSwap32Variant 3158 OpAtomicCompareAndSwap64Variant 3159 OpAtomicAnd8Variant 3160 OpAtomicAnd32Variant 3161 OpAtomicOr8Variant 3162 OpAtomicOr32Variant 3163 OpPubBarrier 3164 OpClobber 3165 OpClobberReg 3166 OpPrefetchCache 3167 OpPrefetchCacheStreamed 3168 ) 3169 3170 var opcodeTable = [...]opInfo{ 3171 {name: "OpInvalid"}, 3172 3173 { 3174 name: "ADDSS", 3175 argLen: 2, 3176 commutative: true, 3177 resultInArg0: true, 3178 asm: x86.AADDSS, 3179 reg: regInfo{ 3180 inputs: []inputInfo{ 3181 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3182 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3183 }, 3184 outputs: []outputInfo{ 3185 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3186 }, 3187 }, 3188 }, 3189 { 3190 name: "ADDSD", 3191 argLen: 2, 3192 commutative: true, 3193 resultInArg0: true, 3194 asm: x86.AADDSD, 3195 reg: regInfo{ 3196 inputs: []inputInfo{ 3197 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3198 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3199 }, 3200 outputs: []outputInfo{ 3201 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3202 }, 3203 }, 3204 }, 3205 { 3206 name: "SUBSS", 3207 argLen: 2, 3208 resultInArg0: true, 3209 asm: x86.ASUBSS, 3210 reg: regInfo{ 3211 inputs: []inputInfo{ 3212 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3213 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3214 }, 3215 outputs: []outputInfo{ 3216 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3217 }, 3218 }, 3219 }, 3220 { 3221 name: "SUBSD", 3222 argLen: 2, 3223 resultInArg0: true, 3224 asm: x86.ASUBSD, 3225 reg: regInfo{ 3226 inputs: []inputInfo{ 3227 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3228 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3229 }, 3230 outputs: []outputInfo{ 3231 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3232 }, 3233 }, 3234 }, 3235 { 3236 name: "MULSS", 3237 argLen: 2, 3238 commutative: true, 3239 resultInArg0: true, 3240 asm: x86.AMULSS, 3241 reg: regInfo{ 3242 inputs: []inputInfo{ 3243 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3244 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3245 }, 3246 outputs: []outputInfo{ 3247 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3248 }, 3249 }, 3250 }, 3251 { 3252 name: "MULSD", 3253 argLen: 2, 3254 commutative: true, 3255 resultInArg0: true, 3256 asm: x86.AMULSD, 3257 reg: regInfo{ 3258 inputs: []inputInfo{ 3259 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3260 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3261 }, 3262 outputs: []outputInfo{ 3263 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3264 }, 3265 }, 3266 }, 3267 { 3268 name: "DIVSS", 3269 argLen: 2, 3270 resultInArg0: true, 3271 asm: x86.ADIVSS, 3272 reg: regInfo{ 3273 inputs: []inputInfo{ 3274 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3275 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3276 }, 3277 outputs: []outputInfo{ 3278 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3279 }, 3280 }, 3281 }, 3282 { 3283 name: "DIVSD", 3284 argLen: 2, 3285 resultInArg0: true, 3286 asm: x86.ADIVSD, 3287 reg: regInfo{ 3288 inputs: []inputInfo{ 3289 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3290 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3291 }, 3292 outputs: []outputInfo{ 3293 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3294 }, 3295 }, 3296 }, 3297 { 3298 name: "MOVSSload", 3299 auxType: auxSymOff, 3300 argLen: 2, 3301 faultOnNilArg0: true, 3302 symEffect: SymRead, 3303 asm: x86.AMOVSS, 3304 reg: regInfo{ 3305 inputs: []inputInfo{ 3306 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3307 }, 3308 outputs: []outputInfo{ 3309 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3310 }, 3311 }, 3312 }, 3313 { 3314 name: "MOVSDload", 3315 auxType: auxSymOff, 3316 argLen: 2, 3317 faultOnNilArg0: true, 3318 symEffect: SymRead, 3319 asm: x86.AMOVSD, 3320 reg: regInfo{ 3321 inputs: []inputInfo{ 3322 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3323 }, 3324 outputs: []outputInfo{ 3325 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3326 }, 3327 }, 3328 }, 3329 { 3330 name: "MOVSSconst", 3331 auxType: auxFloat32, 3332 argLen: 0, 3333 rematerializeable: true, 3334 asm: x86.AMOVSS, 3335 reg: regInfo{ 3336 outputs: []outputInfo{ 3337 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3338 }, 3339 }, 3340 }, 3341 { 3342 name: "MOVSDconst", 3343 auxType: auxFloat64, 3344 argLen: 0, 3345 rematerializeable: true, 3346 asm: x86.AMOVSD, 3347 reg: regInfo{ 3348 outputs: []outputInfo{ 3349 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3350 }, 3351 }, 3352 }, 3353 { 3354 name: "MOVSSloadidx1", 3355 auxType: auxSymOff, 3356 argLen: 3, 3357 symEffect: SymRead, 3358 asm: x86.AMOVSS, 3359 reg: regInfo{ 3360 inputs: []inputInfo{ 3361 {1, 255}, // AX CX DX BX SP BP SI DI 3362 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3363 }, 3364 outputs: []outputInfo{ 3365 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3366 }, 3367 }, 3368 }, 3369 { 3370 name: "MOVSSloadidx4", 3371 auxType: auxSymOff, 3372 argLen: 3, 3373 symEffect: SymRead, 3374 asm: x86.AMOVSS, 3375 reg: regInfo{ 3376 inputs: []inputInfo{ 3377 {1, 255}, // AX CX DX BX SP BP SI DI 3378 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3379 }, 3380 outputs: []outputInfo{ 3381 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3382 }, 3383 }, 3384 }, 3385 { 3386 name: "MOVSDloadidx1", 3387 auxType: auxSymOff, 3388 argLen: 3, 3389 symEffect: SymRead, 3390 asm: x86.AMOVSD, 3391 reg: regInfo{ 3392 inputs: []inputInfo{ 3393 {1, 255}, // AX CX DX BX SP BP SI DI 3394 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3395 }, 3396 outputs: []outputInfo{ 3397 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3398 }, 3399 }, 3400 }, 3401 { 3402 name: "MOVSDloadidx8", 3403 auxType: auxSymOff, 3404 argLen: 3, 3405 symEffect: SymRead, 3406 asm: x86.AMOVSD, 3407 reg: regInfo{ 3408 inputs: []inputInfo{ 3409 {1, 255}, // AX CX DX BX SP BP SI DI 3410 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3411 }, 3412 outputs: []outputInfo{ 3413 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3414 }, 3415 }, 3416 }, 3417 { 3418 name: "MOVSSstore", 3419 auxType: auxSymOff, 3420 argLen: 3, 3421 faultOnNilArg0: true, 3422 symEffect: SymWrite, 3423 asm: x86.AMOVSS, 3424 reg: regInfo{ 3425 inputs: []inputInfo{ 3426 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3427 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3428 }, 3429 }, 3430 }, 3431 { 3432 name: "MOVSDstore", 3433 auxType: auxSymOff, 3434 argLen: 3, 3435 faultOnNilArg0: true, 3436 symEffect: SymWrite, 3437 asm: x86.AMOVSD, 3438 reg: regInfo{ 3439 inputs: []inputInfo{ 3440 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3441 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3442 }, 3443 }, 3444 }, 3445 { 3446 name: "MOVSSstoreidx1", 3447 auxType: auxSymOff, 3448 argLen: 4, 3449 symEffect: SymWrite, 3450 asm: x86.AMOVSS, 3451 reg: regInfo{ 3452 inputs: []inputInfo{ 3453 {1, 255}, // AX CX DX BX SP BP SI DI 3454 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3455 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3456 }, 3457 }, 3458 }, 3459 { 3460 name: "MOVSSstoreidx4", 3461 auxType: auxSymOff, 3462 argLen: 4, 3463 symEffect: SymWrite, 3464 asm: x86.AMOVSS, 3465 reg: regInfo{ 3466 inputs: []inputInfo{ 3467 {1, 255}, // AX CX DX BX SP BP SI DI 3468 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3469 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3470 }, 3471 }, 3472 }, 3473 { 3474 name: "MOVSDstoreidx1", 3475 auxType: auxSymOff, 3476 argLen: 4, 3477 symEffect: SymWrite, 3478 asm: x86.AMOVSD, 3479 reg: regInfo{ 3480 inputs: []inputInfo{ 3481 {1, 255}, // AX CX DX BX SP BP SI DI 3482 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3483 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3484 }, 3485 }, 3486 }, 3487 { 3488 name: "MOVSDstoreidx8", 3489 auxType: auxSymOff, 3490 argLen: 4, 3491 symEffect: SymWrite, 3492 asm: x86.AMOVSD, 3493 reg: regInfo{ 3494 inputs: []inputInfo{ 3495 {1, 255}, // AX CX DX BX SP BP SI DI 3496 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3497 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3498 }, 3499 }, 3500 }, 3501 { 3502 name: "ADDSSload", 3503 auxType: auxSymOff, 3504 argLen: 3, 3505 resultInArg0: true, 3506 faultOnNilArg1: true, 3507 symEffect: SymRead, 3508 asm: x86.AADDSS, 3509 reg: regInfo{ 3510 inputs: []inputInfo{ 3511 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3512 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3513 }, 3514 outputs: []outputInfo{ 3515 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "ADDSDload", 3521 auxType: auxSymOff, 3522 argLen: 3, 3523 resultInArg0: true, 3524 faultOnNilArg1: true, 3525 symEffect: SymRead, 3526 asm: x86.AADDSD, 3527 reg: regInfo{ 3528 inputs: []inputInfo{ 3529 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3530 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3531 }, 3532 outputs: []outputInfo{ 3533 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3534 }, 3535 }, 3536 }, 3537 { 3538 name: "SUBSSload", 3539 auxType: auxSymOff, 3540 argLen: 3, 3541 resultInArg0: true, 3542 faultOnNilArg1: true, 3543 symEffect: SymRead, 3544 asm: x86.ASUBSS, 3545 reg: regInfo{ 3546 inputs: []inputInfo{ 3547 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3548 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3549 }, 3550 outputs: []outputInfo{ 3551 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3552 }, 3553 }, 3554 }, 3555 { 3556 name: "SUBSDload", 3557 auxType: auxSymOff, 3558 argLen: 3, 3559 resultInArg0: true, 3560 faultOnNilArg1: true, 3561 symEffect: SymRead, 3562 asm: x86.ASUBSD, 3563 reg: regInfo{ 3564 inputs: []inputInfo{ 3565 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3566 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3567 }, 3568 outputs: []outputInfo{ 3569 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3570 }, 3571 }, 3572 }, 3573 { 3574 name: "MULSSload", 3575 auxType: auxSymOff, 3576 argLen: 3, 3577 resultInArg0: true, 3578 faultOnNilArg1: true, 3579 symEffect: SymRead, 3580 asm: x86.AMULSS, 3581 reg: regInfo{ 3582 inputs: []inputInfo{ 3583 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3584 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3585 }, 3586 outputs: []outputInfo{ 3587 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3588 }, 3589 }, 3590 }, 3591 { 3592 name: "MULSDload", 3593 auxType: auxSymOff, 3594 argLen: 3, 3595 resultInArg0: true, 3596 faultOnNilArg1: true, 3597 symEffect: SymRead, 3598 asm: x86.AMULSD, 3599 reg: regInfo{ 3600 inputs: []inputInfo{ 3601 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3602 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3603 }, 3604 outputs: []outputInfo{ 3605 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3606 }, 3607 }, 3608 }, 3609 { 3610 name: "DIVSSload", 3611 auxType: auxSymOff, 3612 argLen: 3, 3613 resultInArg0: true, 3614 faultOnNilArg1: true, 3615 symEffect: SymRead, 3616 asm: x86.ADIVSS, 3617 reg: regInfo{ 3618 inputs: []inputInfo{ 3619 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3620 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3621 }, 3622 outputs: []outputInfo{ 3623 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3624 }, 3625 }, 3626 }, 3627 { 3628 name: "DIVSDload", 3629 auxType: auxSymOff, 3630 argLen: 3, 3631 resultInArg0: true, 3632 faultOnNilArg1: true, 3633 symEffect: SymRead, 3634 asm: x86.ADIVSD, 3635 reg: regInfo{ 3636 inputs: []inputInfo{ 3637 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3638 {1, 65791}, // AX CX DX BX SP BP SI DI SB 3639 }, 3640 outputs: []outputInfo{ 3641 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3642 }, 3643 }, 3644 }, 3645 { 3646 name: "ADDL", 3647 argLen: 2, 3648 commutative: true, 3649 clobberFlags: true, 3650 asm: x86.AADDL, 3651 reg: regInfo{ 3652 inputs: []inputInfo{ 3653 {1, 239}, // AX CX DX BX BP SI DI 3654 {0, 255}, // AX CX DX BX SP BP SI DI 3655 }, 3656 outputs: []outputInfo{ 3657 {0, 239}, // AX CX DX BX BP SI DI 3658 }, 3659 }, 3660 }, 3661 { 3662 name: "ADDLconst", 3663 auxType: auxInt32, 3664 argLen: 1, 3665 clobberFlags: true, 3666 asm: x86.AADDL, 3667 reg: regInfo{ 3668 inputs: []inputInfo{ 3669 {0, 255}, // AX CX DX BX SP BP SI DI 3670 }, 3671 outputs: []outputInfo{ 3672 {0, 239}, // AX CX DX BX BP SI DI 3673 }, 3674 }, 3675 }, 3676 { 3677 name: "ADDLcarry", 3678 argLen: 2, 3679 commutative: true, 3680 resultInArg0: true, 3681 asm: x86.AADDL, 3682 reg: regInfo{ 3683 inputs: []inputInfo{ 3684 {0, 239}, // AX CX DX BX BP SI DI 3685 {1, 239}, // AX CX DX BX BP SI DI 3686 }, 3687 outputs: []outputInfo{ 3688 {1, 0}, 3689 {0, 239}, // AX CX DX BX BP SI DI 3690 }, 3691 }, 3692 }, 3693 { 3694 name: "ADDLconstcarry", 3695 auxType: auxInt32, 3696 argLen: 1, 3697 resultInArg0: true, 3698 asm: x86.AADDL, 3699 reg: regInfo{ 3700 inputs: []inputInfo{ 3701 {0, 239}, // AX CX DX BX BP SI DI 3702 }, 3703 outputs: []outputInfo{ 3704 {1, 0}, 3705 {0, 239}, // AX CX DX BX BP SI DI 3706 }, 3707 }, 3708 }, 3709 { 3710 name: "ADCL", 3711 argLen: 3, 3712 commutative: true, 3713 resultInArg0: true, 3714 clobberFlags: true, 3715 asm: x86.AADCL, 3716 reg: regInfo{ 3717 inputs: []inputInfo{ 3718 {0, 239}, // AX CX DX BX BP SI DI 3719 {1, 239}, // AX CX DX BX BP SI DI 3720 }, 3721 outputs: []outputInfo{ 3722 {0, 239}, // AX CX DX BX BP SI DI 3723 }, 3724 }, 3725 }, 3726 { 3727 name: "ADCLconst", 3728 auxType: auxInt32, 3729 argLen: 2, 3730 resultInArg0: true, 3731 clobberFlags: true, 3732 asm: x86.AADCL, 3733 reg: regInfo{ 3734 inputs: []inputInfo{ 3735 {0, 239}, // AX CX DX BX BP SI DI 3736 }, 3737 outputs: []outputInfo{ 3738 {0, 239}, // AX CX DX BX BP SI DI 3739 }, 3740 }, 3741 }, 3742 { 3743 name: "SUBL", 3744 argLen: 2, 3745 resultInArg0: true, 3746 clobberFlags: true, 3747 asm: x86.ASUBL, 3748 reg: regInfo{ 3749 inputs: []inputInfo{ 3750 {0, 239}, // AX CX DX BX BP SI DI 3751 {1, 239}, // AX CX DX BX BP SI DI 3752 }, 3753 outputs: []outputInfo{ 3754 {0, 239}, // AX CX DX BX BP SI DI 3755 }, 3756 }, 3757 }, 3758 { 3759 name: "SUBLconst", 3760 auxType: auxInt32, 3761 argLen: 1, 3762 resultInArg0: true, 3763 clobberFlags: true, 3764 asm: x86.ASUBL, 3765 reg: regInfo{ 3766 inputs: []inputInfo{ 3767 {0, 239}, // AX CX DX BX BP SI DI 3768 }, 3769 outputs: []outputInfo{ 3770 {0, 239}, // AX CX DX BX BP SI DI 3771 }, 3772 }, 3773 }, 3774 { 3775 name: "SUBLcarry", 3776 argLen: 2, 3777 resultInArg0: true, 3778 asm: x86.ASUBL, 3779 reg: regInfo{ 3780 inputs: []inputInfo{ 3781 {0, 239}, // AX CX DX BX BP SI DI 3782 {1, 239}, // AX CX DX BX BP SI DI 3783 }, 3784 outputs: []outputInfo{ 3785 {1, 0}, 3786 {0, 239}, // AX CX DX BX BP SI DI 3787 }, 3788 }, 3789 }, 3790 { 3791 name: "SUBLconstcarry", 3792 auxType: auxInt32, 3793 argLen: 1, 3794 resultInArg0: true, 3795 asm: x86.ASUBL, 3796 reg: regInfo{ 3797 inputs: []inputInfo{ 3798 {0, 239}, // AX CX DX BX BP SI DI 3799 }, 3800 outputs: []outputInfo{ 3801 {1, 0}, 3802 {0, 239}, // AX CX DX BX BP SI DI 3803 }, 3804 }, 3805 }, 3806 { 3807 name: "SBBL", 3808 argLen: 3, 3809 resultInArg0: true, 3810 clobberFlags: true, 3811 asm: x86.ASBBL, 3812 reg: regInfo{ 3813 inputs: []inputInfo{ 3814 {0, 239}, // AX CX DX BX BP SI DI 3815 {1, 239}, // AX CX DX BX BP SI DI 3816 }, 3817 outputs: []outputInfo{ 3818 {0, 239}, // AX CX DX BX BP SI DI 3819 }, 3820 }, 3821 }, 3822 { 3823 name: "SBBLconst", 3824 auxType: auxInt32, 3825 argLen: 2, 3826 resultInArg0: true, 3827 clobberFlags: true, 3828 asm: x86.ASBBL, 3829 reg: regInfo{ 3830 inputs: []inputInfo{ 3831 {0, 239}, // AX CX DX BX BP SI DI 3832 }, 3833 outputs: []outputInfo{ 3834 {0, 239}, // AX CX DX BX BP SI DI 3835 }, 3836 }, 3837 }, 3838 { 3839 name: "MULL", 3840 argLen: 2, 3841 commutative: true, 3842 resultInArg0: true, 3843 clobberFlags: true, 3844 asm: x86.AIMULL, 3845 reg: regInfo{ 3846 inputs: []inputInfo{ 3847 {0, 239}, // AX CX DX BX BP SI DI 3848 {1, 239}, // AX CX DX BX BP SI DI 3849 }, 3850 outputs: []outputInfo{ 3851 {0, 239}, // AX CX DX BX BP SI DI 3852 }, 3853 }, 3854 }, 3855 { 3856 name: "MULLconst", 3857 auxType: auxInt32, 3858 argLen: 1, 3859 clobberFlags: true, 3860 asm: x86.AIMUL3L, 3861 reg: regInfo{ 3862 inputs: []inputInfo{ 3863 {0, 239}, // AX CX DX BX BP SI DI 3864 }, 3865 outputs: []outputInfo{ 3866 {0, 239}, // AX CX DX BX BP SI DI 3867 }, 3868 }, 3869 }, 3870 { 3871 name: "MULLU", 3872 argLen: 2, 3873 commutative: true, 3874 clobberFlags: true, 3875 asm: x86.AMULL, 3876 reg: regInfo{ 3877 inputs: []inputInfo{ 3878 {0, 1}, // AX 3879 {1, 255}, // AX CX DX BX SP BP SI DI 3880 }, 3881 clobbers: 4, // DX 3882 outputs: []outputInfo{ 3883 {1, 0}, 3884 {0, 1}, // AX 3885 }, 3886 }, 3887 }, 3888 { 3889 name: "HMULL", 3890 argLen: 2, 3891 commutative: true, 3892 clobberFlags: true, 3893 asm: x86.AIMULL, 3894 reg: regInfo{ 3895 inputs: []inputInfo{ 3896 {0, 1}, // AX 3897 {1, 255}, // AX CX DX BX SP BP SI DI 3898 }, 3899 clobbers: 1, // AX 3900 outputs: []outputInfo{ 3901 {0, 4}, // DX 3902 }, 3903 }, 3904 }, 3905 { 3906 name: "HMULLU", 3907 argLen: 2, 3908 commutative: true, 3909 clobberFlags: true, 3910 asm: x86.AMULL, 3911 reg: regInfo{ 3912 inputs: []inputInfo{ 3913 {0, 1}, // AX 3914 {1, 255}, // AX CX DX BX SP BP SI DI 3915 }, 3916 clobbers: 1, // AX 3917 outputs: []outputInfo{ 3918 {0, 4}, // DX 3919 }, 3920 }, 3921 }, 3922 { 3923 name: "MULLQU", 3924 argLen: 2, 3925 commutative: true, 3926 clobberFlags: true, 3927 asm: x86.AMULL, 3928 reg: regInfo{ 3929 inputs: []inputInfo{ 3930 {0, 1}, // AX 3931 {1, 255}, // AX CX DX BX SP BP SI DI 3932 }, 3933 outputs: []outputInfo{ 3934 {0, 4}, // DX 3935 {1, 1}, // AX 3936 }, 3937 }, 3938 }, 3939 { 3940 name: "AVGLU", 3941 argLen: 2, 3942 commutative: true, 3943 resultInArg0: true, 3944 clobberFlags: true, 3945 reg: regInfo{ 3946 inputs: []inputInfo{ 3947 {0, 239}, // AX CX DX BX BP SI DI 3948 {1, 239}, // AX CX DX BX BP SI DI 3949 }, 3950 outputs: []outputInfo{ 3951 {0, 239}, // AX CX DX BX BP SI DI 3952 }, 3953 }, 3954 }, 3955 { 3956 name: "DIVL", 3957 auxType: auxBool, 3958 argLen: 2, 3959 clobberFlags: true, 3960 asm: x86.AIDIVL, 3961 reg: regInfo{ 3962 inputs: []inputInfo{ 3963 {0, 1}, // AX 3964 {1, 251}, // AX CX BX SP BP SI DI 3965 }, 3966 clobbers: 4, // DX 3967 outputs: []outputInfo{ 3968 {0, 1}, // AX 3969 }, 3970 }, 3971 }, 3972 { 3973 name: "DIVW", 3974 auxType: auxBool, 3975 argLen: 2, 3976 clobberFlags: true, 3977 asm: x86.AIDIVW, 3978 reg: regInfo{ 3979 inputs: []inputInfo{ 3980 {0, 1}, // AX 3981 {1, 251}, // AX CX BX SP BP SI DI 3982 }, 3983 clobbers: 4, // DX 3984 outputs: []outputInfo{ 3985 {0, 1}, // AX 3986 }, 3987 }, 3988 }, 3989 { 3990 name: "DIVLU", 3991 argLen: 2, 3992 clobberFlags: true, 3993 asm: x86.ADIVL, 3994 reg: regInfo{ 3995 inputs: []inputInfo{ 3996 {0, 1}, // AX 3997 {1, 251}, // AX CX BX SP BP SI DI 3998 }, 3999 clobbers: 4, // DX 4000 outputs: []outputInfo{ 4001 {0, 1}, // AX 4002 }, 4003 }, 4004 }, 4005 { 4006 name: "DIVWU", 4007 argLen: 2, 4008 clobberFlags: true, 4009 asm: x86.ADIVW, 4010 reg: regInfo{ 4011 inputs: []inputInfo{ 4012 {0, 1}, // AX 4013 {1, 251}, // AX CX BX SP BP SI DI 4014 }, 4015 clobbers: 4, // DX 4016 outputs: []outputInfo{ 4017 {0, 1}, // AX 4018 }, 4019 }, 4020 }, 4021 { 4022 name: "MODL", 4023 auxType: auxBool, 4024 argLen: 2, 4025 clobberFlags: true, 4026 asm: x86.AIDIVL, 4027 reg: regInfo{ 4028 inputs: []inputInfo{ 4029 {0, 1}, // AX 4030 {1, 251}, // AX CX BX SP BP SI DI 4031 }, 4032 clobbers: 1, // AX 4033 outputs: []outputInfo{ 4034 {0, 4}, // DX 4035 }, 4036 }, 4037 }, 4038 { 4039 name: "MODW", 4040 auxType: auxBool, 4041 argLen: 2, 4042 clobberFlags: true, 4043 asm: x86.AIDIVW, 4044 reg: regInfo{ 4045 inputs: []inputInfo{ 4046 {0, 1}, // AX 4047 {1, 251}, // AX CX BX SP BP SI DI 4048 }, 4049 clobbers: 1, // AX 4050 outputs: []outputInfo{ 4051 {0, 4}, // DX 4052 }, 4053 }, 4054 }, 4055 { 4056 name: "MODLU", 4057 argLen: 2, 4058 clobberFlags: true, 4059 asm: x86.ADIVL, 4060 reg: regInfo{ 4061 inputs: []inputInfo{ 4062 {0, 1}, // AX 4063 {1, 251}, // AX CX BX SP BP SI DI 4064 }, 4065 clobbers: 1, // AX 4066 outputs: []outputInfo{ 4067 {0, 4}, // DX 4068 }, 4069 }, 4070 }, 4071 { 4072 name: "MODWU", 4073 argLen: 2, 4074 clobberFlags: true, 4075 asm: x86.ADIVW, 4076 reg: regInfo{ 4077 inputs: []inputInfo{ 4078 {0, 1}, // AX 4079 {1, 251}, // AX CX BX SP BP SI DI 4080 }, 4081 clobbers: 1, // AX 4082 outputs: []outputInfo{ 4083 {0, 4}, // DX 4084 }, 4085 }, 4086 }, 4087 { 4088 name: "ANDL", 4089 argLen: 2, 4090 commutative: true, 4091 resultInArg0: true, 4092 clobberFlags: true, 4093 asm: x86.AANDL, 4094 reg: regInfo{ 4095 inputs: []inputInfo{ 4096 {0, 239}, // AX CX DX BX BP SI DI 4097 {1, 239}, // AX CX DX BX BP SI DI 4098 }, 4099 outputs: []outputInfo{ 4100 {0, 239}, // AX CX DX BX BP SI DI 4101 }, 4102 }, 4103 }, 4104 { 4105 name: "ANDLconst", 4106 auxType: auxInt32, 4107 argLen: 1, 4108 resultInArg0: true, 4109 clobberFlags: true, 4110 asm: x86.AANDL, 4111 reg: regInfo{ 4112 inputs: []inputInfo{ 4113 {0, 239}, // AX CX DX BX BP SI DI 4114 }, 4115 outputs: []outputInfo{ 4116 {0, 239}, // AX CX DX BX BP SI DI 4117 }, 4118 }, 4119 }, 4120 { 4121 name: "ORL", 4122 argLen: 2, 4123 commutative: true, 4124 resultInArg0: true, 4125 clobberFlags: true, 4126 asm: x86.AORL, 4127 reg: regInfo{ 4128 inputs: []inputInfo{ 4129 {0, 239}, // AX CX DX BX BP SI DI 4130 {1, 239}, // AX CX DX BX BP SI DI 4131 }, 4132 outputs: []outputInfo{ 4133 {0, 239}, // AX CX DX BX BP SI DI 4134 }, 4135 }, 4136 }, 4137 { 4138 name: "ORLconst", 4139 auxType: auxInt32, 4140 argLen: 1, 4141 resultInArg0: true, 4142 clobberFlags: true, 4143 asm: x86.AORL, 4144 reg: regInfo{ 4145 inputs: []inputInfo{ 4146 {0, 239}, // AX CX DX BX BP SI DI 4147 }, 4148 outputs: []outputInfo{ 4149 {0, 239}, // AX CX DX BX BP SI DI 4150 }, 4151 }, 4152 }, 4153 { 4154 name: "XORL", 4155 argLen: 2, 4156 commutative: true, 4157 resultInArg0: true, 4158 clobberFlags: true, 4159 asm: x86.AXORL, 4160 reg: regInfo{ 4161 inputs: []inputInfo{ 4162 {0, 239}, // AX CX DX BX BP SI DI 4163 {1, 239}, // AX CX DX BX BP SI DI 4164 }, 4165 outputs: []outputInfo{ 4166 {0, 239}, // AX CX DX BX BP SI DI 4167 }, 4168 }, 4169 }, 4170 { 4171 name: "XORLconst", 4172 auxType: auxInt32, 4173 argLen: 1, 4174 resultInArg0: true, 4175 clobberFlags: true, 4176 asm: x86.AXORL, 4177 reg: regInfo{ 4178 inputs: []inputInfo{ 4179 {0, 239}, // AX CX DX BX BP SI DI 4180 }, 4181 outputs: []outputInfo{ 4182 {0, 239}, // AX CX DX BX BP SI DI 4183 }, 4184 }, 4185 }, 4186 { 4187 name: "CMPL", 4188 argLen: 2, 4189 asm: x86.ACMPL, 4190 reg: regInfo{ 4191 inputs: []inputInfo{ 4192 {0, 255}, // AX CX DX BX SP BP SI DI 4193 {1, 255}, // AX CX DX BX SP BP SI DI 4194 }, 4195 }, 4196 }, 4197 { 4198 name: "CMPW", 4199 argLen: 2, 4200 asm: x86.ACMPW, 4201 reg: regInfo{ 4202 inputs: []inputInfo{ 4203 {0, 255}, // AX CX DX BX SP BP SI DI 4204 {1, 255}, // AX CX DX BX SP BP SI DI 4205 }, 4206 }, 4207 }, 4208 { 4209 name: "CMPB", 4210 argLen: 2, 4211 asm: x86.ACMPB, 4212 reg: regInfo{ 4213 inputs: []inputInfo{ 4214 {0, 255}, // AX CX DX BX SP BP SI DI 4215 {1, 255}, // AX CX DX BX SP BP SI DI 4216 }, 4217 }, 4218 }, 4219 { 4220 name: "CMPLconst", 4221 auxType: auxInt32, 4222 argLen: 1, 4223 asm: x86.ACMPL, 4224 reg: regInfo{ 4225 inputs: []inputInfo{ 4226 {0, 255}, // AX CX DX BX SP BP SI DI 4227 }, 4228 }, 4229 }, 4230 { 4231 name: "CMPWconst", 4232 auxType: auxInt16, 4233 argLen: 1, 4234 asm: x86.ACMPW, 4235 reg: regInfo{ 4236 inputs: []inputInfo{ 4237 {0, 255}, // AX CX DX BX SP BP SI DI 4238 }, 4239 }, 4240 }, 4241 { 4242 name: "CMPBconst", 4243 auxType: auxInt8, 4244 argLen: 1, 4245 asm: x86.ACMPB, 4246 reg: regInfo{ 4247 inputs: []inputInfo{ 4248 {0, 255}, // AX CX DX BX SP BP SI DI 4249 }, 4250 }, 4251 }, 4252 { 4253 name: "CMPLload", 4254 auxType: auxSymOff, 4255 argLen: 3, 4256 faultOnNilArg0: true, 4257 symEffect: SymRead, 4258 asm: x86.ACMPL, 4259 reg: regInfo{ 4260 inputs: []inputInfo{ 4261 {1, 255}, // AX CX DX BX SP BP SI DI 4262 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4263 }, 4264 }, 4265 }, 4266 { 4267 name: "CMPWload", 4268 auxType: auxSymOff, 4269 argLen: 3, 4270 faultOnNilArg0: true, 4271 symEffect: SymRead, 4272 asm: x86.ACMPW, 4273 reg: regInfo{ 4274 inputs: []inputInfo{ 4275 {1, 255}, // AX CX DX BX SP BP SI DI 4276 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4277 }, 4278 }, 4279 }, 4280 { 4281 name: "CMPBload", 4282 auxType: auxSymOff, 4283 argLen: 3, 4284 faultOnNilArg0: true, 4285 symEffect: SymRead, 4286 asm: x86.ACMPB, 4287 reg: regInfo{ 4288 inputs: []inputInfo{ 4289 {1, 255}, // AX CX DX BX SP BP SI DI 4290 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4291 }, 4292 }, 4293 }, 4294 { 4295 name: "CMPLconstload", 4296 auxType: auxSymValAndOff, 4297 argLen: 2, 4298 faultOnNilArg0: true, 4299 symEffect: SymRead, 4300 asm: x86.ACMPL, 4301 reg: regInfo{ 4302 inputs: []inputInfo{ 4303 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4304 }, 4305 }, 4306 }, 4307 { 4308 name: "CMPWconstload", 4309 auxType: auxSymValAndOff, 4310 argLen: 2, 4311 faultOnNilArg0: true, 4312 symEffect: SymRead, 4313 asm: x86.ACMPW, 4314 reg: regInfo{ 4315 inputs: []inputInfo{ 4316 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4317 }, 4318 }, 4319 }, 4320 { 4321 name: "CMPBconstload", 4322 auxType: auxSymValAndOff, 4323 argLen: 2, 4324 faultOnNilArg0: true, 4325 symEffect: SymRead, 4326 asm: x86.ACMPB, 4327 reg: regInfo{ 4328 inputs: []inputInfo{ 4329 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4330 }, 4331 }, 4332 }, 4333 { 4334 name: "UCOMISS", 4335 argLen: 2, 4336 asm: x86.AUCOMISS, 4337 reg: regInfo{ 4338 inputs: []inputInfo{ 4339 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4340 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4341 }, 4342 }, 4343 }, 4344 { 4345 name: "UCOMISD", 4346 argLen: 2, 4347 asm: x86.AUCOMISD, 4348 reg: regInfo{ 4349 inputs: []inputInfo{ 4350 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4351 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4352 }, 4353 }, 4354 }, 4355 { 4356 name: "TESTL", 4357 argLen: 2, 4358 commutative: true, 4359 asm: x86.ATESTL, 4360 reg: regInfo{ 4361 inputs: []inputInfo{ 4362 {0, 255}, // AX CX DX BX SP BP SI DI 4363 {1, 255}, // AX CX DX BX SP BP SI DI 4364 }, 4365 }, 4366 }, 4367 { 4368 name: "TESTW", 4369 argLen: 2, 4370 commutative: true, 4371 asm: x86.ATESTW, 4372 reg: regInfo{ 4373 inputs: []inputInfo{ 4374 {0, 255}, // AX CX DX BX SP BP SI DI 4375 {1, 255}, // AX CX DX BX SP BP SI DI 4376 }, 4377 }, 4378 }, 4379 { 4380 name: "TESTB", 4381 argLen: 2, 4382 commutative: true, 4383 asm: x86.ATESTB, 4384 reg: regInfo{ 4385 inputs: []inputInfo{ 4386 {0, 255}, // AX CX DX BX SP BP SI DI 4387 {1, 255}, // AX CX DX BX SP BP SI DI 4388 }, 4389 }, 4390 }, 4391 { 4392 name: "TESTLconst", 4393 auxType: auxInt32, 4394 argLen: 1, 4395 asm: x86.ATESTL, 4396 reg: regInfo{ 4397 inputs: []inputInfo{ 4398 {0, 255}, // AX CX DX BX SP BP SI DI 4399 }, 4400 }, 4401 }, 4402 { 4403 name: "TESTWconst", 4404 auxType: auxInt16, 4405 argLen: 1, 4406 asm: x86.ATESTW, 4407 reg: regInfo{ 4408 inputs: []inputInfo{ 4409 {0, 255}, // AX CX DX BX SP BP SI DI 4410 }, 4411 }, 4412 }, 4413 { 4414 name: "TESTBconst", 4415 auxType: auxInt8, 4416 argLen: 1, 4417 asm: x86.ATESTB, 4418 reg: regInfo{ 4419 inputs: []inputInfo{ 4420 {0, 255}, // AX CX DX BX SP BP SI DI 4421 }, 4422 }, 4423 }, 4424 { 4425 name: "SHLL", 4426 argLen: 2, 4427 resultInArg0: true, 4428 clobberFlags: true, 4429 asm: x86.ASHLL, 4430 reg: regInfo{ 4431 inputs: []inputInfo{ 4432 {1, 2}, // CX 4433 {0, 239}, // AX CX DX BX BP SI DI 4434 }, 4435 outputs: []outputInfo{ 4436 {0, 239}, // AX CX DX BX BP SI DI 4437 }, 4438 }, 4439 }, 4440 { 4441 name: "SHLLconst", 4442 auxType: auxInt32, 4443 argLen: 1, 4444 resultInArg0: true, 4445 clobberFlags: true, 4446 asm: x86.ASHLL, 4447 reg: regInfo{ 4448 inputs: []inputInfo{ 4449 {0, 239}, // AX CX DX BX BP SI DI 4450 }, 4451 outputs: []outputInfo{ 4452 {0, 239}, // AX CX DX BX BP SI DI 4453 }, 4454 }, 4455 }, 4456 { 4457 name: "SHRL", 4458 argLen: 2, 4459 resultInArg0: true, 4460 clobberFlags: true, 4461 asm: x86.ASHRL, 4462 reg: regInfo{ 4463 inputs: []inputInfo{ 4464 {1, 2}, // CX 4465 {0, 239}, // AX CX DX BX BP SI DI 4466 }, 4467 outputs: []outputInfo{ 4468 {0, 239}, // AX CX DX BX BP SI DI 4469 }, 4470 }, 4471 }, 4472 { 4473 name: "SHRW", 4474 argLen: 2, 4475 resultInArg0: true, 4476 clobberFlags: true, 4477 asm: x86.ASHRW, 4478 reg: regInfo{ 4479 inputs: []inputInfo{ 4480 {1, 2}, // CX 4481 {0, 239}, // AX CX DX BX BP SI DI 4482 }, 4483 outputs: []outputInfo{ 4484 {0, 239}, // AX CX DX BX BP SI DI 4485 }, 4486 }, 4487 }, 4488 { 4489 name: "SHRB", 4490 argLen: 2, 4491 resultInArg0: true, 4492 clobberFlags: true, 4493 asm: x86.ASHRB, 4494 reg: regInfo{ 4495 inputs: []inputInfo{ 4496 {1, 2}, // CX 4497 {0, 239}, // AX CX DX BX BP SI DI 4498 }, 4499 outputs: []outputInfo{ 4500 {0, 239}, // AX CX DX BX BP SI DI 4501 }, 4502 }, 4503 }, 4504 { 4505 name: "SHRLconst", 4506 auxType: auxInt32, 4507 argLen: 1, 4508 resultInArg0: true, 4509 clobberFlags: true, 4510 asm: x86.ASHRL, 4511 reg: regInfo{ 4512 inputs: []inputInfo{ 4513 {0, 239}, // AX CX DX BX BP SI DI 4514 }, 4515 outputs: []outputInfo{ 4516 {0, 239}, // AX CX DX BX BP SI DI 4517 }, 4518 }, 4519 }, 4520 { 4521 name: "SHRWconst", 4522 auxType: auxInt16, 4523 argLen: 1, 4524 resultInArg0: true, 4525 clobberFlags: true, 4526 asm: x86.ASHRW, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {0, 239}, // AX CX DX BX BP SI DI 4530 }, 4531 outputs: []outputInfo{ 4532 {0, 239}, // AX CX DX BX BP SI DI 4533 }, 4534 }, 4535 }, 4536 { 4537 name: "SHRBconst", 4538 auxType: auxInt8, 4539 argLen: 1, 4540 resultInArg0: true, 4541 clobberFlags: true, 4542 asm: x86.ASHRB, 4543 reg: regInfo{ 4544 inputs: []inputInfo{ 4545 {0, 239}, // AX CX DX BX BP SI DI 4546 }, 4547 outputs: []outputInfo{ 4548 {0, 239}, // AX CX DX BX BP SI DI 4549 }, 4550 }, 4551 }, 4552 { 4553 name: "SARL", 4554 argLen: 2, 4555 resultInArg0: true, 4556 clobberFlags: true, 4557 asm: x86.ASARL, 4558 reg: regInfo{ 4559 inputs: []inputInfo{ 4560 {1, 2}, // CX 4561 {0, 239}, // AX CX DX BX BP SI DI 4562 }, 4563 outputs: []outputInfo{ 4564 {0, 239}, // AX CX DX BX BP SI DI 4565 }, 4566 }, 4567 }, 4568 { 4569 name: "SARW", 4570 argLen: 2, 4571 resultInArg0: true, 4572 clobberFlags: true, 4573 asm: x86.ASARW, 4574 reg: regInfo{ 4575 inputs: []inputInfo{ 4576 {1, 2}, // CX 4577 {0, 239}, // AX CX DX BX BP SI DI 4578 }, 4579 outputs: []outputInfo{ 4580 {0, 239}, // AX CX DX BX BP SI DI 4581 }, 4582 }, 4583 }, 4584 { 4585 name: "SARB", 4586 argLen: 2, 4587 resultInArg0: true, 4588 clobberFlags: true, 4589 asm: x86.ASARB, 4590 reg: regInfo{ 4591 inputs: []inputInfo{ 4592 {1, 2}, // CX 4593 {0, 239}, // AX CX DX BX BP SI DI 4594 }, 4595 outputs: []outputInfo{ 4596 {0, 239}, // AX CX DX BX BP SI DI 4597 }, 4598 }, 4599 }, 4600 { 4601 name: "SARLconst", 4602 auxType: auxInt32, 4603 argLen: 1, 4604 resultInArg0: true, 4605 clobberFlags: true, 4606 asm: x86.ASARL, 4607 reg: regInfo{ 4608 inputs: []inputInfo{ 4609 {0, 239}, // AX CX DX BX BP SI DI 4610 }, 4611 outputs: []outputInfo{ 4612 {0, 239}, // AX CX DX BX BP SI DI 4613 }, 4614 }, 4615 }, 4616 { 4617 name: "SARWconst", 4618 auxType: auxInt16, 4619 argLen: 1, 4620 resultInArg0: true, 4621 clobberFlags: true, 4622 asm: x86.ASARW, 4623 reg: regInfo{ 4624 inputs: []inputInfo{ 4625 {0, 239}, // AX CX DX BX BP SI DI 4626 }, 4627 outputs: []outputInfo{ 4628 {0, 239}, // AX CX DX BX BP SI DI 4629 }, 4630 }, 4631 }, 4632 { 4633 name: "SARBconst", 4634 auxType: auxInt8, 4635 argLen: 1, 4636 resultInArg0: true, 4637 clobberFlags: true, 4638 asm: x86.ASARB, 4639 reg: regInfo{ 4640 inputs: []inputInfo{ 4641 {0, 239}, // AX CX DX BX BP SI DI 4642 }, 4643 outputs: []outputInfo{ 4644 {0, 239}, // AX CX DX BX BP SI DI 4645 }, 4646 }, 4647 }, 4648 { 4649 name: "ROLL", 4650 argLen: 2, 4651 resultInArg0: true, 4652 clobberFlags: true, 4653 asm: x86.AROLL, 4654 reg: regInfo{ 4655 inputs: []inputInfo{ 4656 {1, 2}, // CX 4657 {0, 239}, // AX CX DX BX BP SI DI 4658 }, 4659 outputs: []outputInfo{ 4660 {0, 239}, // AX CX DX BX BP SI DI 4661 }, 4662 }, 4663 }, 4664 { 4665 name: "ROLW", 4666 argLen: 2, 4667 resultInArg0: true, 4668 clobberFlags: true, 4669 asm: x86.AROLW, 4670 reg: regInfo{ 4671 inputs: []inputInfo{ 4672 {1, 2}, // CX 4673 {0, 239}, // AX CX DX BX BP SI DI 4674 }, 4675 outputs: []outputInfo{ 4676 {0, 239}, // AX CX DX BX BP SI DI 4677 }, 4678 }, 4679 }, 4680 { 4681 name: "ROLB", 4682 argLen: 2, 4683 resultInArg0: true, 4684 clobberFlags: true, 4685 asm: x86.AROLB, 4686 reg: regInfo{ 4687 inputs: []inputInfo{ 4688 {1, 2}, // CX 4689 {0, 239}, // AX CX DX BX BP SI DI 4690 }, 4691 outputs: []outputInfo{ 4692 {0, 239}, // AX CX DX BX BP SI DI 4693 }, 4694 }, 4695 }, 4696 { 4697 name: "ROLLconst", 4698 auxType: auxInt32, 4699 argLen: 1, 4700 resultInArg0: true, 4701 clobberFlags: true, 4702 asm: x86.AROLL, 4703 reg: regInfo{ 4704 inputs: []inputInfo{ 4705 {0, 239}, // AX CX DX BX BP SI DI 4706 }, 4707 outputs: []outputInfo{ 4708 {0, 239}, // AX CX DX BX BP SI DI 4709 }, 4710 }, 4711 }, 4712 { 4713 name: "ROLWconst", 4714 auxType: auxInt16, 4715 argLen: 1, 4716 resultInArg0: true, 4717 clobberFlags: true, 4718 asm: x86.AROLW, 4719 reg: regInfo{ 4720 inputs: []inputInfo{ 4721 {0, 239}, // AX CX DX BX BP SI DI 4722 }, 4723 outputs: []outputInfo{ 4724 {0, 239}, // AX CX DX BX BP SI DI 4725 }, 4726 }, 4727 }, 4728 { 4729 name: "ROLBconst", 4730 auxType: auxInt8, 4731 argLen: 1, 4732 resultInArg0: true, 4733 clobberFlags: true, 4734 asm: x86.AROLB, 4735 reg: regInfo{ 4736 inputs: []inputInfo{ 4737 {0, 239}, // AX CX DX BX BP SI DI 4738 }, 4739 outputs: []outputInfo{ 4740 {0, 239}, // AX CX DX BX BP SI DI 4741 }, 4742 }, 4743 }, 4744 { 4745 name: "ADDLload", 4746 auxType: auxSymOff, 4747 argLen: 3, 4748 resultInArg0: true, 4749 clobberFlags: true, 4750 faultOnNilArg1: true, 4751 symEffect: SymRead, 4752 asm: x86.AADDL, 4753 reg: regInfo{ 4754 inputs: []inputInfo{ 4755 {0, 239}, // AX CX DX BX BP SI DI 4756 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4757 }, 4758 outputs: []outputInfo{ 4759 {0, 239}, // AX CX DX BX BP SI DI 4760 }, 4761 }, 4762 }, 4763 { 4764 name: "SUBLload", 4765 auxType: auxSymOff, 4766 argLen: 3, 4767 resultInArg0: true, 4768 clobberFlags: true, 4769 faultOnNilArg1: true, 4770 symEffect: SymRead, 4771 asm: x86.ASUBL, 4772 reg: regInfo{ 4773 inputs: []inputInfo{ 4774 {0, 239}, // AX CX DX BX BP SI DI 4775 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4776 }, 4777 outputs: []outputInfo{ 4778 {0, 239}, // AX CX DX BX BP SI DI 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "MULLload", 4784 auxType: auxSymOff, 4785 argLen: 3, 4786 resultInArg0: true, 4787 clobberFlags: true, 4788 faultOnNilArg1: true, 4789 symEffect: SymRead, 4790 asm: x86.AIMULL, 4791 reg: regInfo{ 4792 inputs: []inputInfo{ 4793 {0, 239}, // AX CX DX BX BP SI DI 4794 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4795 }, 4796 outputs: []outputInfo{ 4797 {0, 239}, // AX CX DX BX BP SI DI 4798 }, 4799 }, 4800 }, 4801 { 4802 name: "ANDLload", 4803 auxType: auxSymOff, 4804 argLen: 3, 4805 resultInArg0: true, 4806 clobberFlags: true, 4807 faultOnNilArg1: true, 4808 symEffect: SymRead, 4809 asm: x86.AANDL, 4810 reg: regInfo{ 4811 inputs: []inputInfo{ 4812 {0, 239}, // AX CX DX BX BP SI DI 4813 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4814 }, 4815 outputs: []outputInfo{ 4816 {0, 239}, // AX CX DX BX BP SI DI 4817 }, 4818 }, 4819 }, 4820 { 4821 name: "ORLload", 4822 auxType: auxSymOff, 4823 argLen: 3, 4824 resultInArg0: true, 4825 clobberFlags: true, 4826 faultOnNilArg1: true, 4827 symEffect: SymRead, 4828 asm: x86.AORL, 4829 reg: regInfo{ 4830 inputs: []inputInfo{ 4831 {0, 239}, // AX CX DX BX BP SI DI 4832 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4833 }, 4834 outputs: []outputInfo{ 4835 {0, 239}, // AX CX DX BX BP SI DI 4836 }, 4837 }, 4838 }, 4839 { 4840 name: "XORLload", 4841 auxType: auxSymOff, 4842 argLen: 3, 4843 resultInArg0: true, 4844 clobberFlags: true, 4845 faultOnNilArg1: true, 4846 symEffect: SymRead, 4847 asm: x86.AXORL, 4848 reg: regInfo{ 4849 inputs: []inputInfo{ 4850 {0, 239}, // AX CX DX BX BP SI DI 4851 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4852 }, 4853 outputs: []outputInfo{ 4854 {0, 239}, // AX CX DX BX BP SI DI 4855 }, 4856 }, 4857 }, 4858 { 4859 name: "ADDLloadidx4", 4860 auxType: auxSymOff, 4861 argLen: 4, 4862 resultInArg0: true, 4863 clobberFlags: true, 4864 symEffect: SymRead, 4865 asm: x86.AADDL, 4866 reg: regInfo{ 4867 inputs: []inputInfo{ 4868 {0, 239}, // AX CX DX BX BP SI DI 4869 {2, 255}, // AX CX DX BX SP BP SI DI 4870 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4871 }, 4872 outputs: []outputInfo{ 4873 {0, 239}, // AX CX DX BX BP SI DI 4874 }, 4875 }, 4876 }, 4877 { 4878 name: "SUBLloadidx4", 4879 auxType: auxSymOff, 4880 argLen: 4, 4881 resultInArg0: true, 4882 clobberFlags: true, 4883 symEffect: SymRead, 4884 asm: x86.ASUBL, 4885 reg: regInfo{ 4886 inputs: []inputInfo{ 4887 {0, 239}, // AX CX DX BX BP SI DI 4888 {2, 255}, // AX CX DX BX SP BP SI DI 4889 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4890 }, 4891 outputs: []outputInfo{ 4892 {0, 239}, // AX CX DX BX BP SI DI 4893 }, 4894 }, 4895 }, 4896 { 4897 name: "MULLloadidx4", 4898 auxType: auxSymOff, 4899 argLen: 4, 4900 resultInArg0: true, 4901 clobberFlags: true, 4902 symEffect: SymRead, 4903 asm: x86.AIMULL, 4904 reg: regInfo{ 4905 inputs: []inputInfo{ 4906 {0, 239}, // AX CX DX BX BP SI DI 4907 {2, 255}, // AX CX DX BX SP BP SI DI 4908 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4909 }, 4910 outputs: []outputInfo{ 4911 {0, 239}, // AX CX DX BX BP SI DI 4912 }, 4913 }, 4914 }, 4915 { 4916 name: "ANDLloadidx4", 4917 auxType: auxSymOff, 4918 argLen: 4, 4919 resultInArg0: true, 4920 clobberFlags: true, 4921 symEffect: SymRead, 4922 asm: x86.AANDL, 4923 reg: regInfo{ 4924 inputs: []inputInfo{ 4925 {0, 239}, // AX CX DX BX BP SI DI 4926 {2, 255}, // AX CX DX BX SP BP SI DI 4927 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4928 }, 4929 outputs: []outputInfo{ 4930 {0, 239}, // AX CX DX BX BP SI DI 4931 }, 4932 }, 4933 }, 4934 { 4935 name: "ORLloadidx4", 4936 auxType: auxSymOff, 4937 argLen: 4, 4938 resultInArg0: true, 4939 clobberFlags: true, 4940 symEffect: SymRead, 4941 asm: x86.AORL, 4942 reg: regInfo{ 4943 inputs: []inputInfo{ 4944 {0, 239}, // AX CX DX BX BP SI DI 4945 {2, 255}, // AX CX DX BX SP BP SI DI 4946 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4947 }, 4948 outputs: []outputInfo{ 4949 {0, 239}, // AX CX DX BX BP SI DI 4950 }, 4951 }, 4952 }, 4953 { 4954 name: "XORLloadidx4", 4955 auxType: auxSymOff, 4956 argLen: 4, 4957 resultInArg0: true, 4958 clobberFlags: true, 4959 symEffect: SymRead, 4960 asm: x86.AXORL, 4961 reg: regInfo{ 4962 inputs: []inputInfo{ 4963 {0, 239}, // AX CX DX BX BP SI DI 4964 {2, 255}, // AX CX DX BX SP BP SI DI 4965 {1, 65791}, // AX CX DX BX SP BP SI DI SB 4966 }, 4967 outputs: []outputInfo{ 4968 {0, 239}, // AX CX DX BX BP SI DI 4969 }, 4970 }, 4971 }, 4972 { 4973 name: "NEGL", 4974 argLen: 1, 4975 resultInArg0: true, 4976 clobberFlags: true, 4977 asm: x86.ANEGL, 4978 reg: regInfo{ 4979 inputs: []inputInfo{ 4980 {0, 239}, // AX CX DX BX BP SI DI 4981 }, 4982 outputs: []outputInfo{ 4983 {0, 239}, // AX CX DX BX BP SI DI 4984 }, 4985 }, 4986 }, 4987 { 4988 name: "NOTL", 4989 argLen: 1, 4990 resultInArg0: true, 4991 asm: x86.ANOTL, 4992 reg: regInfo{ 4993 inputs: []inputInfo{ 4994 {0, 239}, // AX CX DX BX BP SI DI 4995 }, 4996 outputs: []outputInfo{ 4997 {0, 239}, // AX CX DX BX BP SI DI 4998 }, 4999 }, 5000 }, 5001 { 5002 name: "BSFL", 5003 argLen: 1, 5004 clobberFlags: true, 5005 asm: x86.ABSFL, 5006 reg: regInfo{ 5007 inputs: []inputInfo{ 5008 {0, 239}, // AX CX DX BX BP SI DI 5009 }, 5010 outputs: []outputInfo{ 5011 {0, 239}, // AX CX DX BX BP SI DI 5012 }, 5013 }, 5014 }, 5015 { 5016 name: "BSFW", 5017 argLen: 1, 5018 clobberFlags: true, 5019 asm: x86.ABSFW, 5020 reg: regInfo{ 5021 inputs: []inputInfo{ 5022 {0, 239}, // AX CX DX BX BP SI DI 5023 }, 5024 outputs: []outputInfo{ 5025 {0, 239}, // AX CX DX BX BP SI DI 5026 }, 5027 }, 5028 }, 5029 { 5030 name: "BSRL", 5031 argLen: 1, 5032 clobberFlags: true, 5033 asm: x86.ABSRL, 5034 reg: regInfo{ 5035 inputs: []inputInfo{ 5036 {0, 239}, // AX CX DX BX BP SI DI 5037 }, 5038 outputs: []outputInfo{ 5039 {0, 239}, // AX CX DX BX BP SI DI 5040 }, 5041 }, 5042 }, 5043 { 5044 name: "BSRW", 5045 argLen: 1, 5046 clobberFlags: true, 5047 asm: x86.ABSRW, 5048 reg: regInfo{ 5049 inputs: []inputInfo{ 5050 {0, 239}, // AX CX DX BX BP SI DI 5051 }, 5052 outputs: []outputInfo{ 5053 {0, 239}, // AX CX DX BX BP SI DI 5054 }, 5055 }, 5056 }, 5057 { 5058 name: "BSWAPL", 5059 argLen: 1, 5060 resultInArg0: true, 5061 asm: x86.ABSWAPL, 5062 reg: regInfo{ 5063 inputs: []inputInfo{ 5064 {0, 239}, // AX CX DX BX BP SI DI 5065 }, 5066 outputs: []outputInfo{ 5067 {0, 239}, // AX CX DX BX BP SI DI 5068 }, 5069 }, 5070 }, 5071 { 5072 name: "SQRTSD", 5073 argLen: 1, 5074 asm: x86.ASQRTSD, 5075 reg: regInfo{ 5076 inputs: []inputInfo{ 5077 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5078 }, 5079 outputs: []outputInfo{ 5080 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5081 }, 5082 }, 5083 }, 5084 { 5085 name: "SQRTSS", 5086 argLen: 1, 5087 asm: x86.ASQRTSS, 5088 reg: regInfo{ 5089 inputs: []inputInfo{ 5090 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5091 }, 5092 outputs: []outputInfo{ 5093 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5094 }, 5095 }, 5096 }, 5097 { 5098 name: "SBBLcarrymask", 5099 argLen: 1, 5100 asm: x86.ASBBL, 5101 reg: regInfo{ 5102 outputs: []outputInfo{ 5103 {0, 239}, // AX CX DX BX BP SI DI 5104 }, 5105 }, 5106 }, 5107 { 5108 name: "SETEQ", 5109 argLen: 1, 5110 asm: x86.ASETEQ, 5111 reg: regInfo{ 5112 outputs: []outputInfo{ 5113 {0, 239}, // AX CX DX BX BP SI DI 5114 }, 5115 }, 5116 }, 5117 { 5118 name: "SETNE", 5119 argLen: 1, 5120 asm: x86.ASETNE, 5121 reg: regInfo{ 5122 outputs: []outputInfo{ 5123 {0, 239}, // AX CX DX BX BP SI DI 5124 }, 5125 }, 5126 }, 5127 { 5128 name: "SETL", 5129 argLen: 1, 5130 asm: x86.ASETLT, 5131 reg: regInfo{ 5132 outputs: []outputInfo{ 5133 {0, 239}, // AX CX DX BX BP SI DI 5134 }, 5135 }, 5136 }, 5137 { 5138 name: "SETLE", 5139 argLen: 1, 5140 asm: x86.ASETLE, 5141 reg: regInfo{ 5142 outputs: []outputInfo{ 5143 {0, 239}, // AX CX DX BX BP SI DI 5144 }, 5145 }, 5146 }, 5147 { 5148 name: "SETG", 5149 argLen: 1, 5150 asm: x86.ASETGT, 5151 reg: regInfo{ 5152 outputs: []outputInfo{ 5153 {0, 239}, // AX CX DX BX BP SI DI 5154 }, 5155 }, 5156 }, 5157 { 5158 name: "SETGE", 5159 argLen: 1, 5160 asm: x86.ASETGE, 5161 reg: regInfo{ 5162 outputs: []outputInfo{ 5163 {0, 239}, // AX CX DX BX BP SI DI 5164 }, 5165 }, 5166 }, 5167 { 5168 name: "SETB", 5169 argLen: 1, 5170 asm: x86.ASETCS, 5171 reg: regInfo{ 5172 outputs: []outputInfo{ 5173 {0, 239}, // AX CX DX BX BP SI DI 5174 }, 5175 }, 5176 }, 5177 { 5178 name: "SETBE", 5179 argLen: 1, 5180 asm: x86.ASETLS, 5181 reg: regInfo{ 5182 outputs: []outputInfo{ 5183 {0, 239}, // AX CX DX BX BP SI DI 5184 }, 5185 }, 5186 }, 5187 { 5188 name: "SETA", 5189 argLen: 1, 5190 asm: x86.ASETHI, 5191 reg: regInfo{ 5192 outputs: []outputInfo{ 5193 {0, 239}, // AX CX DX BX BP SI DI 5194 }, 5195 }, 5196 }, 5197 { 5198 name: "SETAE", 5199 argLen: 1, 5200 asm: x86.ASETCC, 5201 reg: regInfo{ 5202 outputs: []outputInfo{ 5203 {0, 239}, // AX CX DX BX BP SI DI 5204 }, 5205 }, 5206 }, 5207 { 5208 name: "SETO", 5209 argLen: 1, 5210 asm: x86.ASETOS, 5211 reg: regInfo{ 5212 outputs: []outputInfo{ 5213 {0, 239}, // AX CX DX BX BP SI DI 5214 }, 5215 }, 5216 }, 5217 { 5218 name: "SETEQF", 5219 argLen: 1, 5220 clobberFlags: true, 5221 asm: x86.ASETEQ, 5222 reg: regInfo{ 5223 clobbers: 1, // AX 5224 outputs: []outputInfo{ 5225 {0, 238}, // CX DX BX BP SI DI 5226 }, 5227 }, 5228 }, 5229 { 5230 name: "SETNEF", 5231 argLen: 1, 5232 clobberFlags: true, 5233 asm: x86.ASETNE, 5234 reg: regInfo{ 5235 clobbers: 1, // AX 5236 outputs: []outputInfo{ 5237 {0, 238}, // CX DX BX BP SI DI 5238 }, 5239 }, 5240 }, 5241 { 5242 name: "SETORD", 5243 argLen: 1, 5244 asm: x86.ASETPC, 5245 reg: regInfo{ 5246 outputs: []outputInfo{ 5247 {0, 239}, // AX CX DX BX BP SI DI 5248 }, 5249 }, 5250 }, 5251 { 5252 name: "SETNAN", 5253 argLen: 1, 5254 asm: x86.ASETPS, 5255 reg: regInfo{ 5256 outputs: []outputInfo{ 5257 {0, 239}, // AX CX DX BX BP SI DI 5258 }, 5259 }, 5260 }, 5261 { 5262 name: "SETGF", 5263 argLen: 1, 5264 asm: x86.ASETHI, 5265 reg: regInfo{ 5266 outputs: []outputInfo{ 5267 {0, 239}, // AX CX DX BX BP SI DI 5268 }, 5269 }, 5270 }, 5271 { 5272 name: "SETGEF", 5273 argLen: 1, 5274 asm: x86.ASETCC, 5275 reg: regInfo{ 5276 outputs: []outputInfo{ 5277 {0, 239}, // AX CX DX BX BP SI DI 5278 }, 5279 }, 5280 }, 5281 { 5282 name: "MOVBLSX", 5283 argLen: 1, 5284 asm: x86.AMOVBLSX, 5285 reg: regInfo{ 5286 inputs: []inputInfo{ 5287 {0, 239}, // AX CX DX BX BP SI DI 5288 }, 5289 outputs: []outputInfo{ 5290 {0, 239}, // AX CX DX BX BP SI DI 5291 }, 5292 }, 5293 }, 5294 { 5295 name: "MOVBLZX", 5296 argLen: 1, 5297 asm: x86.AMOVBLZX, 5298 reg: regInfo{ 5299 inputs: []inputInfo{ 5300 {0, 239}, // AX CX DX BX BP SI DI 5301 }, 5302 outputs: []outputInfo{ 5303 {0, 239}, // AX CX DX BX BP SI DI 5304 }, 5305 }, 5306 }, 5307 { 5308 name: "MOVWLSX", 5309 argLen: 1, 5310 asm: x86.AMOVWLSX, 5311 reg: regInfo{ 5312 inputs: []inputInfo{ 5313 {0, 239}, // AX CX DX BX BP SI DI 5314 }, 5315 outputs: []outputInfo{ 5316 {0, 239}, // AX CX DX BX BP SI DI 5317 }, 5318 }, 5319 }, 5320 { 5321 name: "MOVWLZX", 5322 argLen: 1, 5323 asm: x86.AMOVWLZX, 5324 reg: regInfo{ 5325 inputs: []inputInfo{ 5326 {0, 239}, // AX CX DX BX BP SI DI 5327 }, 5328 outputs: []outputInfo{ 5329 {0, 239}, // AX CX DX BX BP SI DI 5330 }, 5331 }, 5332 }, 5333 { 5334 name: "MOVLconst", 5335 auxType: auxInt32, 5336 argLen: 0, 5337 rematerializeable: true, 5338 asm: x86.AMOVL, 5339 reg: regInfo{ 5340 outputs: []outputInfo{ 5341 {0, 239}, // AX CX DX BX BP SI DI 5342 }, 5343 }, 5344 }, 5345 { 5346 name: "CVTTSD2SL", 5347 argLen: 1, 5348 asm: x86.ACVTTSD2SL, 5349 reg: regInfo{ 5350 inputs: []inputInfo{ 5351 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5352 }, 5353 outputs: []outputInfo{ 5354 {0, 239}, // AX CX DX BX BP SI DI 5355 }, 5356 }, 5357 }, 5358 { 5359 name: "CVTTSS2SL", 5360 argLen: 1, 5361 asm: x86.ACVTTSS2SL, 5362 reg: regInfo{ 5363 inputs: []inputInfo{ 5364 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5365 }, 5366 outputs: []outputInfo{ 5367 {0, 239}, // AX CX DX BX BP SI DI 5368 }, 5369 }, 5370 }, 5371 { 5372 name: "CVTSL2SS", 5373 argLen: 1, 5374 asm: x86.ACVTSL2SS, 5375 reg: regInfo{ 5376 inputs: []inputInfo{ 5377 {0, 239}, // AX CX DX BX BP SI DI 5378 }, 5379 outputs: []outputInfo{ 5380 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5381 }, 5382 }, 5383 }, 5384 { 5385 name: "CVTSL2SD", 5386 argLen: 1, 5387 asm: x86.ACVTSL2SD, 5388 reg: regInfo{ 5389 inputs: []inputInfo{ 5390 {0, 239}, // AX CX DX BX BP SI DI 5391 }, 5392 outputs: []outputInfo{ 5393 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5394 }, 5395 }, 5396 }, 5397 { 5398 name: "CVTSD2SS", 5399 argLen: 1, 5400 asm: x86.ACVTSD2SS, 5401 reg: regInfo{ 5402 inputs: []inputInfo{ 5403 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5404 }, 5405 outputs: []outputInfo{ 5406 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5407 }, 5408 }, 5409 }, 5410 { 5411 name: "CVTSS2SD", 5412 argLen: 1, 5413 asm: x86.ACVTSS2SD, 5414 reg: regInfo{ 5415 inputs: []inputInfo{ 5416 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5417 }, 5418 outputs: []outputInfo{ 5419 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5420 }, 5421 }, 5422 }, 5423 { 5424 name: "PXOR", 5425 argLen: 2, 5426 commutative: true, 5427 resultInArg0: true, 5428 asm: x86.APXOR, 5429 reg: regInfo{ 5430 inputs: []inputInfo{ 5431 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5432 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5433 }, 5434 outputs: []outputInfo{ 5435 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 5436 }, 5437 }, 5438 }, 5439 { 5440 name: "LEAL", 5441 auxType: auxSymOff, 5442 argLen: 1, 5443 rematerializeable: true, 5444 symEffect: SymAddr, 5445 reg: regInfo{ 5446 inputs: []inputInfo{ 5447 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5448 }, 5449 outputs: []outputInfo{ 5450 {0, 239}, // AX CX DX BX BP SI DI 5451 }, 5452 }, 5453 }, 5454 { 5455 name: "LEAL1", 5456 auxType: auxSymOff, 5457 argLen: 2, 5458 commutative: true, 5459 symEffect: SymAddr, 5460 reg: regInfo{ 5461 inputs: []inputInfo{ 5462 {1, 255}, // AX CX DX BX SP BP SI DI 5463 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5464 }, 5465 outputs: []outputInfo{ 5466 {0, 239}, // AX CX DX BX BP SI DI 5467 }, 5468 }, 5469 }, 5470 { 5471 name: "LEAL2", 5472 auxType: auxSymOff, 5473 argLen: 2, 5474 symEffect: SymAddr, 5475 reg: regInfo{ 5476 inputs: []inputInfo{ 5477 {1, 255}, // AX CX DX BX SP BP SI DI 5478 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5479 }, 5480 outputs: []outputInfo{ 5481 {0, 239}, // AX CX DX BX BP SI DI 5482 }, 5483 }, 5484 }, 5485 { 5486 name: "LEAL4", 5487 auxType: auxSymOff, 5488 argLen: 2, 5489 symEffect: SymAddr, 5490 reg: regInfo{ 5491 inputs: []inputInfo{ 5492 {1, 255}, // AX CX DX BX SP BP SI DI 5493 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5494 }, 5495 outputs: []outputInfo{ 5496 {0, 239}, // AX CX DX BX BP SI DI 5497 }, 5498 }, 5499 }, 5500 { 5501 name: "LEAL8", 5502 auxType: auxSymOff, 5503 argLen: 2, 5504 symEffect: SymAddr, 5505 reg: regInfo{ 5506 inputs: []inputInfo{ 5507 {1, 255}, // AX CX DX BX SP BP SI DI 5508 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5509 }, 5510 outputs: []outputInfo{ 5511 {0, 239}, // AX CX DX BX BP SI DI 5512 }, 5513 }, 5514 }, 5515 { 5516 name: "MOVBload", 5517 auxType: auxSymOff, 5518 argLen: 2, 5519 faultOnNilArg0: true, 5520 symEffect: SymRead, 5521 asm: x86.AMOVBLZX, 5522 reg: regInfo{ 5523 inputs: []inputInfo{ 5524 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5525 }, 5526 outputs: []outputInfo{ 5527 {0, 239}, // AX CX DX BX BP SI DI 5528 }, 5529 }, 5530 }, 5531 { 5532 name: "MOVBLSXload", 5533 auxType: auxSymOff, 5534 argLen: 2, 5535 faultOnNilArg0: true, 5536 symEffect: SymRead, 5537 asm: x86.AMOVBLSX, 5538 reg: regInfo{ 5539 inputs: []inputInfo{ 5540 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5541 }, 5542 outputs: []outputInfo{ 5543 {0, 239}, // AX CX DX BX BP SI DI 5544 }, 5545 }, 5546 }, 5547 { 5548 name: "MOVWload", 5549 auxType: auxSymOff, 5550 argLen: 2, 5551 faultOnNilArg0: true, 5552 symEffect: SymRead, 5553 asm: x86.AMOVWLZX, 5554 reg: regInfo{ 5555 inputs: []inputInfo{ 5556 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5557 }, 5558 outputs: []outputInfo{ 5559 {0, 239}, // AX CX DX BX BP SI DI 5560 }, 5561 }, 5562 }, 5563 { 5564 name: "MOVWLSXload", 5565 auxType: auxSymOff, 5566 argLen: 2, 5567 faultOnNilArg0: true, 5568 symEffect: SymRead, 5569 asm: x86.AMOVWLSX, 5570 reg: regInfo{ 5571 inputs: []inputInfo{ 5572 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5573 }, 5574 outputs: []outputInfo{ 5575 {0, 239}, // AX CX DX BX BP SI DI 5576 }, 5577 }, 5578 }, 5579 { 5580 name: "MOVLload", 5581 auxType: auxSymOff, 5582 argLen: 2, 5583 faultOnNilArg0: true, 5584 symEffect: SymRead, 5585 asm: x86.AMOVL, 5586 reg: regInfo{ 5587 inputs: []inputInfo{ 5588 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5589 }, 5590 outputs: []outputInfo{ 5591 {0, 239}, // AX CX DX BX BP SI DI 5592 }, 5593 }, 5594 }, 5595 { 5596 name: "MOVBstore", 5597 auxType: auxSymOff, 5598 argLen: 3, 5599 faultOnNilArg0: true, 5600 symEffect: SymWrite, 5601 asm: x86.AMOVB, 5602 reg: regInfo{ 5603 inputs: []inputInfo{ 5604 {1, 255}, // AX CX DX BX SP BP SI DI 5605 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5606 }, 5607 }, 5608 }, 5609 { 5610 name: "MOVWstore", 5611 auxType: auxSymOff, 5612 argLen: 3, 5613 faultOnNilArg0: true, 5614 symEffect: SymWrite, 5615 asm: x86.AMOVW, 5616 reg: regInfo{ 5617 inputs: []inputInfo{ 5618 {1, 255}, // AX CX DX BX SP BP SI DI 5619 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5620 }, 5621 }, 5622 }, 5623 { 5624 name: "MOVLstore", 5625 auxType: auxSymOff, 5626 argLen: 3, 5627 faultOnNilArg0: true, 5628 symEffect: SymWrite, 5629 asm: x86.AMOVL, 5630 reg: regInfo{ 5631 inputs: []inputInfo{ 5632 {1, 255}, // AX CX DX BX SP BP SI DI 5633 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5634 }, 5635 }, 5636 }, 5637 { 5638 name: "ADDLmodify", 5639 auxType: auxSymOff, 5640 argLen: 3, 5641 clobberFlags: true, 5642 faultOnNilArg0: true, 5643 symEffect: SymRead | SymWrite, 5644 asm: x86.AADDL, 5645 reg: regInfo{ 5646 inputs: []inputInfo{ 5647 {1, 255}, // AX CX DX BX SP BP SI DI 5648 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5649 }, 5650 }, 5651 }, 5652 { 5653 name: "SUBLmodify", 5654 auxType: auxSymOff, 5655 argLen: 3, 5656 clobberFlags: true, 5657 faultOnNilArg0: true, 5658 symEffect: SymRead | SymWrite, 5659 asm: x86.ASUBL, 5660 reg: regInfo{ 5661 inputs: []inputInfo{ 5662 {1, 255}, // AX CX DX BX SP BP SI DI 5663 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5664 }, 5665 }, 5666 }, 5667 { 5668 name: "ANDLmodify", 5669 auxType: auxSymOff, 5670 argLen: 3, 5671 clobberFlags: true, 5672 faultOnNilArg0: true, 5673 symEffect: SymRead | SymWrite, 5674 asm: x86.AANDL, 5675 reg: regInfo{ 5676 inputs: []inputInfo{ 5677 {1, 255}, // AX CX DX BX SP BP SI DI 5678 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5679 }, 5680 }, 5681 }, 5682 { 5683 name: "ORLmodify", 5684 auxType: auxSymOff, 5685 argLen: 3, 5686 clobberFlags: true, 5687 faultOnNilArg0: true, 5688 symEffect: SymRead | SymWrite, 5689 asm: x86.AORL, 5690 reg: regInfo{ 5691 inputs: []inputInfo{ 5692 {1, 255}, // AX CX DX BX SP BP SI DI 5693 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5694 }, 5695 }, 5696 }, 5697 { 5698 name: "XORLmodify", 5699 auxType: auxSymOff, 5700 argLen: 3, 5701 clobberFlags: true, 5702 faultOnNilArg0: true, 5703 symEffect: SymRead | SymWrite, 5704 asm: x86.AXORL, 5705 reg: regInfo{ 5706 inputs: []inputInfo{ 5707 {1, 255}, // AX CX DX BX SP BP SI DI 5708 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5709 }, 5710 }, 5711 }, 5712 { 5713 name: "ADDLmodifyidx4", 5714 auxType: auxSymOff, 5715 argLen: 4, 5716 clobberFlags: true, 5717 symEffect: SymRead | SymWrite, 5718 asm: x86.AADDL, 5719 reg: regInfo{ 5720 inputs: []inputInfo{ 5721 {1, 255}, // AX CX DX BX SP BP SI DI 5722 {2, 255}, // AX CX DX BX SP BP SI DI 5723 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5724 }, 5725 }, 5726 }, 5727 { 5728 name: "SUBLmodifyidx4", 5729 auxType: auxSymOff, 5730 argLen: 4, 5731 clobberFlags: true, 5732 symEffect: SymRead | SymWrite, 5733 asm: x86.ASUBL, 5734 reg: regInfo{ 5735 inputs: []inputInfo{ 5736 {1, 255}, // AX CX DX BX SP BP SI DI 5737 {2, 255}, // AX CX DX BX SP BP SI DI 5738 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5739 }, 5740 }, 5741 }, 5742 { 5743 name: "ANDLmodifyidx4", 5744 auxType: auxSymOff, 5745 argLen: 4, 5746 clobberFlags: true, 5747 symEffect: SymRead | SymWrite, 5748 asm: x86.AANDL, 5749 reg: regInfo{ 5750 inputs: []inputInfo{ 5751 {1, 255}, // AX CX DX BX SP BP SI DI 5752 {2, 255}, // AX CX DX BX SP BP SI DI 5753 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5754 }, 5755 }, 5756 }, 5757 { 5758 name: "ORLmodifyidx4", 5759 auxType: auxSymOff, 5760 argLen: 4, 5761 clobberFlags: true, 5762 symEffect: SymRead | SymWrite, 5763 asm: x86.AORL, 5764 reg: regInfo{ 5765 inputs: []inputInfo{ 5766 {1, 255}, // AX CX DX BX SP BP SI DI 5767 {2, 255}, // AX CX DX BX SP BP SI DI 5768 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5769 }, 5770 }, 5771 }, 5772 { 5773 name: "XORLmodifyidx4", 5774 auxType: auxSymOff, 5775 argLen: 4, 5776 clobberFlags: true, 5777 symEffect: SymRead | SymWrite, 5778 asm: x86.AXORL, 5779 reg: regInfo{ 5780 inputs: []inputInfo{ 5781 {1, 255}, // AX CX DX BX SP BP SI DI 5782 {2, 255}, // AX CX DX BX SP BP SI DI 5783 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5784 }, 5785 }, 5786 }, 5787 { 5788 name: "ADDLconstmodify", 5789 auxType: auxSymValAndOff, 5790 argLen: 2, 5791 clobberFlags: true, 5792 faultOnNilArg0: true, 5793 symEffect: SymRead | SymWrite, 5794 asm: x86.AADDL, 5795 reg: regInfo{ 5796 inputs: []inputInfo{ 5797 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5798 }, 5799 }, 5800 }, 5801 { 5802 name: "ANDLconstmodify", 5803 auxType: auxSymValAndOff, 5804 argLen: 2, 5805 clobberFlags: true, 5806 faultOnNilArg0: true, 5807 symEffect: SymRead | SymWrite, 5808 asm: x86.AANDL, 5809 reg: regInfo{ 5810 inputs: []inputInfo{ 5811 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5812 }, 5813 }, 5814 }, 5815 { 5816 name: "ORLconstmodify", 5817 auxType: auxSymValAndOff, 5818 argLen: 2, 5819 clobberFlags: true, 5820 faultOnNilArg0: true, 5821 symEffect: SymRead | SymWrite, 5822 asm: x86.AORL, 5823 reg: regInfo{ 5824 inputs: []inputInfo{ 5825 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5826 }, 5827 }, 5828 }, 5829 { 5830 name: "XORLconstmodify", 5831 auxType: auxSymValAndOff, 5832 argLen: 2, 5833 clobberFlags: true, 5834 faultOnNilArg0: true, 5835 symEffect: SymRead | SymWrite, 5836 asm: x86.AXORL, 5837 reg: regInfo{ 5838 inputs: []inputInfo{ 5839 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5840 }, 5841 }, 5842 }, 5843 { 5844 name: "ADDLconstmodifyidx4", 5845 auxType: auxSymValAndOff, 5846 argLen: 3, 5847 clobberFlags: true, 5848 symEffect: SymRead | SymWrite, 5849 asm: x86.AADDL, 5850 reg: regInfo{ 5851 inputs: []inputInfo{ 5852 {1, 255}, // AX CX DX BX SP BP SI DI 5853 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5854 }, 5855 }, 5856 }, 5857 { 5858 name: "ANDLconstmodifyidx4", 5859 auxType: auxSymValAndOff, 5860 argLen: 3, 5861 clobberFlags: true, 5862 symEffect: SymRead | SymWrite, 5863 asm: x86.AANDL, 5864 reg: regInfo{ 5865 inputs: []inputInfo{ 5866 {1, 255}, // AX CX DX BX SP BP SI DI 5867 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5868 }, 5869 }, 5870 }, 5871 { 5872 name: "ORLconstmodifyidx4", 5873 auxType: auxSymValAndOff, 5874 argLen: 3, 5875 clobberFlags: true, 5876 symEffect: SymRead | SymWrite, 5877 asm: x86.AORL, 5878 reg: regInfo{ 5879 inputs: []inputInfo{ 5880 {1, 255}, // AX CX DX BX SP BP SI DI 5881 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5882 }, 5883 }, 5884 }, 5885 { 5886 name: "XORLconstmodifyidx4", 5887 auxType: auxSymValAndOff, 5888 argLen: 3, 5889 clobberFlags: true, 5890 symEffect: SymRead | SymWrite, 5891 asm: x86.AXORL, 5892 reg: regInfo{ 5893 inputs: []inputInfo{ 5894 {1, 255}, // AX CX DX BX SP BP SI DI 5895 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5896 }, 5897 }, 5898 }, 5899 { 5900 name: "MOVBloadidx1", 5901 auxType: auxSymOff, 5902 argLen: 3, 5903 commutative: true, 5904 symEffect: SymRead, 5905 asm: x86.AMOVBLZX, 5906 reg: regInfo{ 5907 inputs: []inputInfo{ 5908 {1, 255}, // AX CX DX BX SP BP SI DI 5909 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5910 }, 5911 outputs: []outputInfo{ 5912 {0, 239}, // AX CX DX BX BP SI DI 5913 }, 5914 }, 5915 }, 5916 { 5917 name: "MOVWloadidx1", 5918 auxType: auxSymOff, 5919 argLen: 3, 5920 commutative: true, 5921 symEffect: SymRead, 5922 asm: x86.AMOVWLZX, 5923 reg: regInfo{ 5924 inputs: []inputInfo{ 5925 {1, 255}, // AX CX DX BX SP BP SI DI 5926 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5927 }, 5928 outputs: []outputInfo{ 5929 {0, 239}, // AX CX DX BX BP SI DI 5930 }, 5931 }, 5932 }, 5933 { 5934 name: "MOVWloadidx2", 5935 auxType: auxSymOff, 5936 argLen: 3, 5937 symEffect: SymRead, 5938 asm: x86.AMOVWLZX, 5939 reg: regInfo{ 5940 inputs: []inputInfo{ 5941 {1, 255}, // AX CX DX BX SP BP SI DI 5942 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5943 }, 5944 outputs: []outputInfo{ 5945 {0, 239}, // AX CX DX BX BP SI DI 5946 }, 5947 }, 5948 }, 5949 { 5950 name: "MOVLloadidx1", 5951 auxType: auxSymOff, 5952 argLen: 3, 5953 commutative: true, 5954 symEffect: SymRead, 5955 asm: x86.AMOVL, 5956 reg: regInfo{ 5957 inputs: []inputInfo{ 5958 {1, 255}, // AX CX DX BX SP BP SI DI 5959 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5960 }, 5961 outputs: []outputInfo{ 5962 {0, 239}, // AX CX DX BX BP SI DI 5963 }, 5964 }, 5965 }, 5966 { 5967 name: "MOVLloadidx4", 5968 auxType: auxSymOff, 5969 argLen: 3, 5970 symEffect: SymRead, 5971 asm: x86.AMOVL, 5972 reg: regInfo{ 5973 inputs: []inputInfo{ 5974 {1, 255}, // AX CX DX BX SP BP SI DI 5975 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5976 }, 5977 outputs: []outputInfo{ 5978 {0, 239}, // AX CX DX BX BP SI DI 5979 }, 5980 }, 5981 }, 5982 { 5983 name: "MOVBstoreidx1", 5984 auxType: auxSymOff, 5985 argLen: 4, 5986 commutative: true, 5987 symEffect: SymWrite, 5988 asm: x86.AMOVB, 5989 reg: regInfo{ 5990 inputs: []inputInfo{ 5991 {1, 255}, // AX CX DX BX SP BP SI DI 5992 {2, 255}, // AX CX DX BX SP BP SI DI 5993 {0, 65791}, // AX CX DX BX SP BP SI DI SB 5994 }, 5995 }, 5996 }, 5997 { 5998 name: "MOVWstoreidx1", 5999 auxType: auxSymOff, 6000 argLen: 4, 6001 commutative: true, 6002 symEffect: SymWrite, 6003 asm: x86.AMOVW, 6004 reg: regInfo{ 6005 inputs: []inputInfo{ 6006 {1, 255}, // AX CX DX BX SP BP SI DI 6007 {2, 255}, // AX CX DX BX SP BP SI DI 6008 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6009 }, 6010 }, 6011 }, 6012 { 6013 name: "MOVWstoreidx2", 6014 auxType: auxSymOff, 6015 argLen: 4, 6016 symEffect: SymWrite, 6017 asm: x86.AMOVW, 6018 reg: regInfo{ 6019 inputs: []inputInfo{ 6020 {1, 255}, // AX CX DX BX SP BP SI DI 6021 {2, 255}, // AX CX DX BX SP BP SI DI 6022 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6023 }, 6024 }, 6025 }, 6026 { 6027 name: "MOVLstoreidx1", 6028 auxType: auxSymOff, 6029 argLen: 4, 6030 commutative: true, 6031 symEffect: SymWrite, 6032 asm: x86.AMOVL, 6033 reg: regInfo{ 6034 inputs: []inputInfo{ 6035 {1, 255}, // AX CX DX BX SP BP SI DI 6036 {2, 255}, // AX CX DX BX SP BP SI DI 6037 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6038 }, 6039 }, 6040 }, 6041 { 6042 name: "MOVLstoreidx4", 6043 auxType: auxSymOff, 6044 argLen: 4, 6045 symEffect: SymWrite, 6046 asm: x86.AMOVL, 6047 reg: regInfo{ 6048 inputs: []inputInfo{ 6049 {1, 255}, // AX CX DX BX SP BP SI DI 6050 {2, 255}, // AX CX DX BX SP BP SI DI 6051 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6052 }, 6053 }, 6054 }, 6055 { 6056 name: "MOVBstoreconst", 6057 auxType: auxSymValAndOff, 6058 argLen: 2, 6059 faultOnNilArg0: true, 6060 symEffect: SymWrite, 6061 asm: x86.AMOVB, 6062 reg: regInfo{ 6063 inputs: []inputInfo{ 6064 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6065 }, 6066 }, 6067 }, 6068 { 6069 name: "MOVWstoreconst", 6070 auxType: auxSymValAndOff, 6071 argLen: 2, 6072 faultOnNilArg0: true, 6073 symEffect: SymWrite, 6074 asm: x86.AMOVW, 6075 reg: regInfo{ 6076 inputs: []inputInfo{ 6077 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6078 }, 6079 }, 6080 }, 6081 { 6082 name: "MOVLstoreconst", 6083 auxType: auxSymValAndOff, 6084 argLen: 2, 6085 faultOnNilArg0: true, 6086 symEffect: SymWrite, 6087 asm: x86.AMOVL, 6088 reg: regInfo{ 6089 inputs: []inputInfo{ 6090 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6091 }, 6092 }, 6093 }, 6094 { 6095 name: "MOVBstoreconstidx1", 6096 auxType: auxSymValAndOff, 6097 argLen: 3, 6098 symEffect: SymWrite, 6099 asm: x86.AMOVB, 6100 reg: regInfo{ 6101 inputs: []inputInfo{ 6102 {1, 255}, // AX CX DX BX SP BP SI DI 6103 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6104 }, 6105 }, 6106 }, 6107 { 6108 name: "MOVWstoreconstidx1", 6109 auxType: auxSymValAndOff, 6110 argLen: 3, 6111 symEffect: SymWrite, 6112 asm: x86.AMOVW, 6113 reg: regInfo{ 6114 inputs: []inputInfo{ 6115 {1, 255}, // AX CX DX BX SP BP SI DI 6116 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6117 }, 6118 }, 6119 }, 6120 { 6121 name: "MOVWstoreconstidx2", 6122 auxType: auxSymValAndOff, 6123 argLen: 3, 6124 symEffect: SymWrite, 6125 asm: x86.AMOVW, 6126 reg: regInfo{ 6127 inputs: []inputInfo{ 6128 {1, 255}, // AX CX DX BX SP BP SI DI 6129 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6130 }, 6131 }, 6132 }, 6133 { 6134 name: "MOVLstoreconstidx1", 6135 auxType: auxSymValAndOff, 6136 argLen: 3, 6137 symEffect: SymWrite, 6138 asm: x86.AMOVL, 6139 reg: regInfo{ 6140 inputs: []inputInfo{ 6141 {1, 255}, // AX CX DX BX SP BP SI DI 6142 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6143 }, 6144 }, 6145 }, 6146 { 6147 name: "MOVLstoreconstidx4", 6148 auxType: auxSymValAndOff, 6149 argLen: 3, 6150 symEffect: SymWrite, 6151 asm: x86.AMOVL, 6152 reg: regInfo{ 6153 inputs: []inputInfo{ 6154 {1, 255}, // AX CX DX BX SP BP SI DI 6155 {0, 65791}, // AX CX DX BX SP BP SI DI SB 6156 }, 6157 }, 6158 }, 6159 { 6160 name: "DUFFZERO", 6161 auxType: auxInt64, 6162 argLen: 3, 6163 faultOnNilArg0: true, 6164 reg: regInfo{ 6165 inputs: []inputInfo{ 6166 {0, 128}, // DI 6167 {1, 1}, // AX 6168 }, 6169 clobbers: 130, // CX DI 6170 }, 6171 }, 6172 { 6173 name: "REPSTOSL", 6174 argLen: 4, 6175 faultOnNilArg0: true, 6176 reg: regInfo{ 6177 inputs: []inputInfo{ 6178 {0, 128}, // DI 6179 {1, 2}, // CX 6180 {2, 1}, // AX 6181 }, 6182 clobbers: 130, // CX DI 6183 }, 6184 }, 6185 { 6186 name: "CALLstatic", 6187 auxType: auxCallOff, 6188 argLen: 1, 6189 clobberFlags: true, 6190 call: true, 6191 reg: regInfo{ 6192 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 6193 }, 6194 }, 6195 { 6196 name: "CALLtail", 6197 auxType: auxCallOff, 6198 argLen: 1, 6199 clobberFlags: true, 6200 call: true, 6201 tailCall: true, 6202 reg: regInfo{ 6203 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 6204 }, 6205 }, 6206 { 6207 name: "CALLclosure", 6208 auxType: auxCallOff, 6209 argLen: 3, 6210 clobberFlags: true, 6211 call: true, 6212 reg: regInfo{ 6213 inputs: []inputInfo{ 6214 {1, 4}, // DX 6215 {0, 255}, // AX CX DX BX SP BP SI DI 6216 }, 6217 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 6218 }, 6219 }, 6220 { 6221 name: "CALLinter", 6222 auxType: auxCallOff, 6223 argLen: 2, 6224 clobberFlags: true, 6225 call: true, 6226 reg: regInfo{ 6227 inputs: []inputInfo{ 6228 {0, 239}, // AX CX DX BX BP SI DI 6229 }, 6230 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 6231 }, 6232 }, 6233 { 6234 name: "DUFFCOPY", 6235 auxType: auxInt64, 6236 argLen: 3, 6237 clobberFlags: true, 6238 faultOnNilArg0: true, 6239 faultOnNilArg1: true, 6240 reg: regInfo{ 6241 inputs: []inputInfo{ 6242 {0, 128}, // DI 6243 {1, 64}, // SI 6244 }, 6245 clobbers: 194, // CX SI DI 6246 }, 6247 }, 6248 { 6249 name: "REPMOVSL", 6250 argLen: 4, 6251 faultOnNilArg0: true, 6252 faultOnNilArg1: true, 6253 reg: regInfo{ 6254 inputs: []inputInfo{ 6255 {0, 128}, // DI 6256 {1, 64}, // SI 6257 {2, 2}, // CX 6258 }, 6259 clobbers: 194, // CX SI DI 6260 }, 6261 }, 6262 { 6263 name: "InvertFlags", 6264 argLen: 1, 6265 reg: regInfo{}, 6266 }, 6267 { 6268 name: "LoweredGetG", 6269 argLen: 1, 6270 reg: regInfo{ 6271 outputs: []outputInfo{ 6272 {0, 239}, // AX CX DX BX BP SI DI 6273 }, 6274 }, 6275 }, 6276 { 6277 name: "LoweredGetClosurePtr", 6278 argLen: 0, 6279 zeroWidth: true, 6280 reg: regInfo{ 6281 outputs: []outputInfo{ 6282 {0, 4}, // DX 6283 }, 6284 }, 6285 }, 6286 { 6287 name: "LoweredGetCallerPC", 6288 argLen: 0, 6289 rematerializeable: true, 6290 reg: regInfo{ 6291 outputs: []outputInfo{ 6292 {0, 239}, // AX CX DX BX BP SI DI 6293 }, 6294 }, 6295 }, 6296 { 6297 name: "LoweredGetCallerSP", 6298 argLen: 0, 6299 rematerializeable: true, 6300 reg: regInfo{ 6301 outputs: []outputInfo{ 6302 {0, 239}, // AX CX DX BX BP SI DI 6303 }, 6304 }, 6305 }, 6306 { 6307 name: "LoweredNilCheck", 6308 argLen: 2, 6309 clobberFlags: true, 6310 nilCheck: true, 6311 faultOnNilArg0: true, 6312 reg: regInfo{ 6313 inputs: []inputInfo{ 6314 {0, 255}, // AX CX DX BX SP BP SI DI 6315 }, 6316 }, 6317 }, 6318 { 6319 name: "LoweredWB", 6320 auxType: auxSym, 6321 argLen: 3, 6322 clobberFlags: true, 6323 symEffect: SymNone, 6324 reg: regInfo{ 6325 inputs: []inputInfo{ 6326 {0, 128}, // DI 6327 {1, 1}, // AX 6328 }, 6329 clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 6330 }, 6331 }, 6332 { 6333 name: "LoweredPanicBoundsA", 6334 auxType: auxInt64, 6335 argLen: 3, 6336 call: true, 6337 reg: regInfo{ 6338 inputs: []inputInfo{ 6339 {0, 4}, // DX 6340 {1, 8}, // BX 6341 }, 6342 }, 6343 }, 6344 { 6345 name: "LoweredPanicBoundsB", 6346 auxType: auxInt64, 6347 argLen: 3, 6348 call: true, 6349 reg: regInfo{ 6350 inputs: []inputInfo{ 6351 {0, 2}, // CX 6352 {1, 4}, // DX 6353 }, 6354 }, 6355 }, 6356 { 6357 name: "LoweredPanicBoundsC", 6358 auxType: auxInt64, 6359 argLen: 3, 6360 call: true, 6361 reg: regInfo{ 6362 inputs: []inputInfo{ 6363 {0, 1}, // AX 6364 {1, 2}, // CX 6365 }, 6366 }, 6367 }, 6368 { 6369 name: "LoweredPanicExtendA", 6370 auxType: auxInt64, 6371 argLen: 4, 6372 call: true, 6373 reg: regInfo{ 6374 inputs: []inputInfo{ 6375 {0, 64}, // SI 6376 {1, 4}, // DX 6377 {2, 8}, // BX 6378 }, 6379 }, 6380 }, 6381 { 6382 name: "LoweredPanicExtendB", 6383 auxType: auxInt64, 6384 argLen: 4, 6385 call: true, 6386 reg: regInfo{ 6387 inputs: []inputInfo{ 6388 {0, 64}, // SI 6389 {1, 2}, // CX 6390 {2, 4}, // DX 6391 }, 6392 }, 6393 }, 6394 { 6395 name: "LoweredPanicExtendC", 6396 auxType: auxInt64, 6397 argLen: 4, 6398 call: true, 6399 reg: regInfo{ 6400 inputs: []inputInfo{ 6401 {0, 64}, // SI 6402 {1, 1}, // AX 6403 {2, 2}, // CX 6404 }, 6405 }, 6406 }, 6407 { 6408 name: "FlagEQ", 6409 argLen: 0, 6410 reg: regInfo{}, 6411 }, 6412 { 6413 name: "FlagLT_ULT", 6414 argLen: 0, 6415 reg: regInfo{}, 6416 }, 6417 { 6418 name: "FlagLT_UGT", 6419 argLen: 0, 6420 reg: regInfo{}, 6421 }, 6422 { 6423 name: "FlagGT_UGT", 6424 argLen: 0, 6425 reg: regInfo{}, 6426 }, 6427 { 6428 name: "FlagGT_ULT", 6429 argLen: 0, 6430 reg: regInfo{}, 6431 }, 6432 { 6433 name: "MOVSSconst1", 6434 auxType: auxFloat32, 6435 argLen: 0, 6436 reg: regInfo{ 6437 outputs: []outputInfo{ 6438 {0, 239}, // AX CX DX BX BP SI DI 6439 }, 6440 }, 6441 }, 6442 { 6443 name: "MOVSDconst1", 6444 auxType: auxFloat64, 6445 argLen: 0, 6446 reg: regInfo{ 6447 outputs: []outputInfo{ 6448 {0, 239}, // AX CX DX BX BP SI DI 6449 }, 6450 }, 6451 }, 6452 { 6453 name: "MOVSSconst2", 6454 argLen: 1, 6455 asm: x86.AMOVSS, 6456 reg: regInfo{ 6457 inputs: []inputInfo{ 6458 {0, 239}, // AX CX DX BX BP SI DI 6459 }, 6460 outputs: []outputInfo{ 6461 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 6462 }, 6463 }, 6464 }, 6465 { 6466 name: "MOVSDconst2", 6467 argLen: 1, 6468 asm: x86.AMOVSD, 6469 reg: regInfo{ 6470 inputs: []inputInfo{ 6471 {0, 239}, // AX CX DX BX BP SI DI 6472 }, 6473 outputs: []outputInfo{ 6474 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 6475 }, 6476 }, 6477 }, 6478 6479 { 6480 name: "ADDSS", 6481 argLen: 2, 6482 commutative: true, 6483 resultInArg0: true, 6484 asm: x86.AADDSS, 6485 reg: regInfo{ 6486 inputs: []inputInfo{ 6487 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6488 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6489 }, 6490 outputs: []outputInfo{ 6491 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6492 }, 6493 }, 6494 }, 6495 { 6496 name: "ADDSD", 6497 argLen: 2, 6498 commutative: true, 6499 resultInArg0: true, 6500 asm: x86.AADDSD, 6501 reg: regInfo{ 6502 inputs: []inputInfo{ 6503 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6504 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6505 }, 6506 outputs: []outputInfo{ 6507 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6508 }, 6509 }, 6510 }, 6511 { 6512 name: "SUBSS", 6513 argLen: 2, 6514 resultInArg0: true, 6515 asm: x86.ASUBSS, 6516 reg: regInfo{ 6517 inputs: []inputInfo{ 6518 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6519 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6520 }, 6521 outputs: []outputInfo{ 6522 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6523 }, 6524 }, 6525 }, 6526 { 6527 name: "SUBSD", 6528 argLen: 2, 6529 resultInArg0: true, 6530 asm: x86.ASUBSD, 6531 reg: regInfo{ 6532 inputs: []inputInfo{ 6533 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6534 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6535 }, 6536 outputs: []outputInfo{ 6537 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6538 }, 6539 }, 6540 }, 6541 { 6542 name: "MULSS", 6543 argLen: 2, 6544 commutative: true, 6545 resultInArg0: true, 6546 asm: x86.AMULSS, 6547 reg: regInfo{ 6548 inputs: []inputInfo{ 6549 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6550 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6551 }, 6552 outputs: []outputInfo{ 6553 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6554 }, 6555 }, 6556 }, 6557 { 6558 name: "MULSD", 6559 argLen: 2, 6560 commutative: true, 6561 resultInArg0: true, 6562 asm: x86.AMULSD, 6563 reg: regInfo{ 6564 inputs: []inputInfo{ 6565 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6566 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6567 }, 6568 outputs: []outputInfo{ 6569 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6570 }, 6571 }, 6572 }, 6573 { 6574 name: "DIVSS", 6575 argLen: 2, 6576 resultInArg0: true, 6577 asm: x86.ADIVSS, 6578 reg: regInfo{ 6579 inputs: []inputInfo{ 6580 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6581 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6582 }, 6583 outputs: []outputInfo{ 6584 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6585 }, 6586 }, 6587 }, 6588 { 6589 name: "DIVSD", 6590 argLen: 2, 6591 resultInArg0: true, 6592 asm: x86.ADIVSD, 6593 reg: regInfo{ 6594 inputs: []inputInfo{ 6595 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6596 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6597 }, 6598 outputs: []outputInfo{ 6599 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6600 }, 6601 }, 6602 }, 6603 { 6604 name: "MOVSSload", 6605 auxType: auxSymOff, 6606 argLen: 2, 6607 faultOnNilArg0: true, 6608 symEffect: SymRead, 6609 asm: x86.AMOVSS, 6610 reg: regInfo{ 6611 inputs: []inputInfo{ 6612 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6613 }, 6614 outputs: []outputInfo{ 6615 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6616 }, 6617 }, 6618 }, 6619 { 6620 name: "MOVSDload", 6621 auxType: auxSymOff, 6622 argLen: 2, 6623 faultOnNilArg0: true, 6624 symEffect: SymRead, 6625 asm: x86.AMOVSD, 6626 reg: regInfo{ 6627 inputs: []inputInfo{ 6628 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6629 }, 6630 outputs: []outputInfo{ 6631 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6632 }, 6633 }, 6634 }, 6635 { 6636 name: "MOVSSconst", 6637 auxType: auxFloat32, 6638 argLen: 0, 6639 rematerializeable: true, 6640 asm: x86.AMOVSS, 6641 reg: regInfo{ 6642 outputs: []outputInfo{ 6643 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6644 }, 6645 }, 6646 }, 6647 { 6648 name: "MOVSDconst", 6649 auxType: auxFloat64, 6650 argLen: 0, 6651 rematerializeable: true, 6652 asm: x86.AMOVSD, 6653 reg: regInfo{ 6654 outputs: []outputInfo{ 6655 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6656 }, 6657 }, 6658 }, 6659 { 6660 name: "MOVSSloadidx1", 6661 auxType: auxSymOff, 6662 argLen: 3, 6663 symEffect: SymRead, 6664 asm: x86.AMOVSS, 6665 scale: 1, 6666 reg: regInfo{ 6667 inputs: []inputInfo{ 6668 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6669 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6670 }, 6671 outputs: []outputInfo{ 6672 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6673 }, 6674 }, 6675 }, 6676 { 6677 name: "MOVSSloadidx4", 6678 auxType: auxSymOff, 6679 argLen: 3, 6680 symEffect: SymRead, 6681 asm: x86.AMOVSS, 6682 scale: 4, 6683 reg: regInfo{ 6684 inputs: []inputInfo{ 6685 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6686 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6687 }, 6688 outputs: []outputInfo{ 6689 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6690 }, 6691 }, 6692 }, 6693 { 6694 name: "MOVSDloadidx1", 6695 auxType: auxSymOff, 6696 argLen: 3, 6697 symEffect: SymRead, 6698 asm: x86.AMOVSD, 6699 scale: 1, 6700 reg: regInfo{ 6701 inputs: []inputInfo{ 6702 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6703 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6704 }, 6705 outputs: []outputInfo{ 6706 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6707 }, 6708 }, 6709 }, 6710 { 6711 name: "MOVSDloadidx8", 6712 auxType: auxSymOff, 6713 argLen: 3, 6714 symEffect: SymRead, 6715 asm: x86.AMOVSD, 6716 scale: 8, 6717 reg: regInfo{ 6718 inputs: []inputInfo{ 6719 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6720 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6721 }, 6722 outputs: []outputInfo{ 6723 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6724 }, 6725 }, 6726 }, 6727 { 6728 name: "MOVSSstore", 6729 auxType: auxSymOff, 6730 argLen: 3, 6731 faultOnNilArg0: true, 6732 symEffect: SymWrite, 6733 asm: x86.AMOVSS, 6734 reg: regInfo{ 6735 inputs: []inputInfo{ 6736 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6737 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6738 }, 6739 }, 6740 }, 6741 { 6742 name: "MOVSDstore", 6743 auxType: auxSymOff, 6744 argLen: 3, 6745 faultOnNilArg0: true, 6746 symEffect: SymWrite, 6747 asm: x86.AMOVSD, 6748 reg: regInfo{ 6749 inputs: []inputInfo{ 6750 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6751 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6752 }, 6753 }, 6754 }, 6755 { 6756 name: "MOVSSstoreidx1", 6757 auxType: auxSymOff, 6758 argLen: 4, 6759 symEffect: SymWrite, 6760 asm: x86.AMOVSS, 6761 scale: 1, 6762 reg: regInfo{ 6763 inputs: []inputInfo{ 6764 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6765 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6766 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6767 }, 6768 }, 6769 }, 6770 { 6771 name: "MOVSSstoreidx4", 6772 auxType: auxSymOff, 6773 argLen: 4, 6774 symEffect: SymWrite, 6775 asm: x86.AMOVSS, 6776 scale: 4, 6777 reg: regInfo{ 6778 inputs: []inputInfo{ 6779 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6780 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6781 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6782 }, 6783 }, 6784 }, 6785 { 6786 name: "MOVSDstoreidx1", 6787 auxType: auxSymOff, 6788 argLen: 4, 6789 symEffect: SymWrite, 6790 asm: x86.AMOVSD, 6791 scale: 1, 6792 reg: regInfo{ 6793 inputs: []inputInfo{ 6794 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6795 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6796 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6797 }, 6798 }, 6799 }, 6800 { 6801 name: "MOVSDstoreidx8", 6802 auxType: auxSymOff, 6803 argLen: 4, 6804 symEffect: SymWrite, 6805 asm: x86.AMOVSD, 6806 scale: 8, 6807 reg: regInfo{ 6808 inputs: []inputInfo{ 6809 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 6810 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6811 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6812 }, 6813 }, 6814 }, 6815 { 6816 name: "ADDSSload", 6817 auxType: auxSymOff, 6818 argLen: 3, 6819 resultInArg0: true, 6820 faultOnNilArg1: true, 6821 symEffect: SymRead, 6822 asm: x86.AADDSS, 6823 reg: regInfo{ 6824 inputs: []inputInfo{ 6825 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6826 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6827 }, 6828 outputs: []outputInfo{ 6829 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6830 }, 6831 }, 6832 }, 6833 { 6834 name: "ADDSDload", 6835 auxType: auxSymOff, 6836 argLen: 3, 6837 resultInArg0: true, 6838 faultOnNilArg1: true, 6839 symEffect: SymRead, 6840 asm: x86.AADDSD, 6841 reg: regInfo{ 6842 inputs: []inputInfo{ 6843 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6844 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6845 }, 6846 outputs: []outputInfo{ 6847 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6848 }, 6849 }, 6850 }, 6851 { 6852 name: "SUBSSload", 6853 auxType: auxSymOff, 6854 argLen: 3, 6855 resultInArg0: true, 6856 faultOnNilArg1: true, 6857 symEffect: SymRead, 6858 asm: x86.ASUBSS, 6859 reg: regInfo{ 6860 inputs: []inputInfo{ 6861 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6862 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6863 }, 6864 outputs: []outputInfo{ 6865 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6866 }, 6867 }, 6868 }, 6869 { 6870 name: "SUBSDload", 6871 auxType: auxSymOff, 6872 argLen: 3, 6873 resultInArg0: true, 6874 faultOnNilArg1: true, 6875 symEffect: SymRead, 6876 asm: x86.ASUBSD, 6877 reg: regInfo{ 6878 inputs: []inputInfo{ 6879 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6880 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6881 }, 6882 outputs: []outputInfo{ 6883 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6884 }, 6885 }, 6886 }, 6887 { 6888 name: "MULSSload", 6889 auxType: auxSymOff, 6890 argLen: 3, 6891 resultInArg0: true, 6892 faultOnNilArg1: true, 6893 symEffect: SymRead, 6894 asm: x86.AMULSS, 6895 reg: regInfo{ 6896 inputs: []inputInfo{ 6897 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6898 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6899 }, 6900 outputs: []outputInfo{ 6901 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6902 }, 6903 }, 6904 }, 6905 { 6906 name: "MULSDload", 6907 auxType: auxSymOff, 6908 argLen: 3, 6909 resultInArg0: true, 6910 faultOnNilArg1: true, 6911 symEffect: SymRead, 6912 asm: x86.AMULSD, 6913 reg: regInfo{ 6914 inputs: []inputInfo{ 6915 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6916 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6917 }, 6918 outputs: []outputInfo{ 6919 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6920 }, 6921 }, 6922 }, 6923 { 6924 name: "DIVSSload", 6925 auxType: auxSymOff, 6926 argLen: 3, 6927 resultInArg0: true, 6928 faultOnNilArg1: true, 6929 symEffect: SymRead, 6930 asm: x86.ADIVSS, 6931 reg: regInfo{ 6932 inputs: []inputInfo{ 6933 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6934 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6935 }, 6936 outputs: []outputInfo{ 6937 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6938 }, 6939 }, 6940 }, 6941 { 6942 name: "DIVSDload", 6943 auxType: auxSymOff, 6944 argLen: 3, 6945 resultInArg0: true, 6946 faultOnNilArg1: true, 6947 symEffect: SymRead, 6948 asm: x86.ADIVSD, 6949 reg: regInfo{ 6950 inputs: []inputInfo{ 6951 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6952 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6953 }, 6954 outputs: []outputInfo{ 6955 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6956 }, 6957 }, 6958 }, 6959 { 6960 name: "ADDSSloadidx1", 6961 auxType: auxSymOff, 6962 argLen: 4, 6963 resultInArg0: true, 6964 symEffect: SymRead, 6965 asm: x86.AADDSS, 6966 scale: 1, 6967 reg: regInfo{ 6968 inputs: []inputInfo{ 6969 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6970 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6971 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6972 }, 6973 outputs: []outputInfo{ 6974 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6975 }, 6976 }, 6977 }, 6978 { 6979 name: "ADDSSloadidx4", 6980 auxType: auxSymOff, 6981 argLen: 4, 6982 resultInArg0: true, 6983 symEffect: SymRead, 6984 asm: x86.AADDSS, 6985 scale: 4, 6986 reg: regInfo{ 6987 inputs: []inputInfo{ 6988 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6989 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 6990 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 6991 }, 6992 outputs: []outputInfo{ 6993 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 6994 }, 6995 }, 6996 }, 6997 { 6998 name: "ADDSDloadidx1", 6999 auxType: auxSymOff, 7000 argLen: 4, 7001 resultInArg0: true, 7002 symEffect: SymRead, 7003 asm: x86.AADDSD, 7004 scale: 1, 7005 reg: regInfo{ 7006 inputs: []inputInfo{ 7007 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7008 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7009 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7010 }, 7011 outputs: []outputInfo{ 7012 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7013 }, 7014 }, 7015 }, 7016 { 7017 name: "ADDSDloadidx8", 7018 auxType: auxSymOff, 7019 argLen: 4, 7020 resultInArg0: true, 7021 symEffect: SymRead, 7022 asm: x86.AADDSD, 7023 scale: 8, 7024 reg: regInfo{ 7025 inputs: []inputInfo{ 7026 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7027 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7028 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7029 }, 7030 outputs: []outputInfo{ 7031 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7032 }, 7033 }, 7034 }, 7035 { 7036 name: "SUBSSloadidx1", 7037 auxType: auxSymOff, 7038 argLen: 4, 7039 resultInArg0: true, 7040 symEffect: SymRead, 7041 asm: x86.ASUBSS, 7042 scale: 1, 7043 reg: regInfo{ 7044 inputs: []inputInfo{ 7045 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7046 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7047 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7048 }, 7049 outputs: []outputInfo{ 7050 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7051 }, 7052 }, 7053 }, 7054 { 7055 name: "SUBSSloadidx4", 7056 auxType: auxSymOff, 7057 argLen: 4, 7058 resultInArg0: true, 7059 symEffect: SymRead, 7060 asm: x86.ASUBSS, 7061 scale: 4, 7062 reg: regInfo{ 7063 inputs: []inputInfo{ 7064 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7065 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7066 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7067 }, 7068 outputs: []outputInfo{ 7069 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7070 }, 7071 }, 7072 }, 7073 { 7074 name: "SUBSDloadidx1", 7075 auxType: auxSymOff, 7076 argLen: 4, 7077 resultInArg0: true, 7078 symEffect: SymRead, 7079 asm: x86.ASUBSD, 7080 scale: 1, 7081 reg: regInfo{ 7082 inputs: []inputInfo{ 7083 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7084 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7085 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7086 }, 7087 outputs: []outputInfo{ 7088 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7089 }, 7090 }, 7091 }, 7092 { 7093 name: "SUBSDloadidx8", 7094 auxType: auxSymOff, 7095 argLen: 4, 7096 resultInArg0: true, 7097 symEffect: SymRead, 7098 asm: x86.ASUBSD, 7099 scale: 8, 7100 reg: regInfo{ 7101 inputs: []inputInfo{ 7102 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7103 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7104 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7105 }, 7106 outputs: []outputInfo{ 7107 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7108 }, 7109 }, 7110 }, 7111 { 7112 name: "MULSSloadidx1", 7113 auxType: auxSymOff, 7114 argLen: 4, 7115 resultInArg0: true, 7116 symEffect: SymRead, 7117 asm: x86.AMULSS, 7118 scale: 1, 7119 reg: regInfo{ 7120 inputs: []inputInfo{ 7121 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7122 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7123 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7124 }, 7125 outputs: []outputInfo{ 7126 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7127 }, 7128 }, 7129 }, 7130 { 7131 name: "MULSSloadidx4", 7132 auxType: auxSymOff, 7133 argLen: 4, 7134 resultInArg0: true, 7135 symEffect: SymRead, 7136 asm: x86.AMULSS, 7137 scale: 4, 7138 reg: regInfo{ 7139 inputs: []inputInfo{ 7140 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7141 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7142 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7143 }, 7144 outputs: []outputInfo{ 7145 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7146 }, 7147 }, 7148 }, 7149 { 7150 name: "MULSDloadidx1", 7151 auxType: auxSymOff, 7152 argLen: 4, 7153 resultInArg0: true, 7154 symEffect: SymRead, 7155 asm: x86.AMULSD, 7156 scale: 1, 7157 reg: regInfo{ 7158 inputs: []inputInfo{ 7159 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7160 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7161 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7162 }, 7163 outputs: []outputInfo{ 7164 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7165 }, 7166 }, 7167 }, 7168 { 7169 name: "MULSDloadidx8", 7170 auxType: auxSymOff, 7171 argLen: 4, 7172 resultInArg0: true, 7173 symEffect: SymRead, 7174 asm: x86.AMULSD, 7175 scale: 8, 7176 reg: regInfo{ 7177 inputs: []inputInfo{ 7178 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7179 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7180 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7181 }, 7182 outputs: []outputInfo{ 7183 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7184 }, 7185 }, 7186 }, 7187 { 7188 name: "DIVSSloadidx1", 7189 auxType: auxSymOff, 7190 argLen: 4, 7191 resultInArg0: true, 7192 symEffect: SymRead, 7193 asm: x86.ADIVSS, 7194 scale: 1, 7195 reg: regInfo{ 7196 inputs: []inputInfo{ 7197 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7198 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7199 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7200 }, 7201 outputs: []outputInfo{ 7202 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7203 }, 7204 }, 7205 }, 7206 { 7207 name: "DIVSSloadidx4", 7208 auxType: auxSymOff, 7209 argLen: 4, 7210 resultInArg0: true, 7211 symEffect: SymRead, 7212 asm: x86.ADIVSS, 7213 scale: 4, 7214 reg: regInfo{ 7215 inputs: []inputInfo{ 7216 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7217 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7218 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7219 }, 7220 outputs: []outputInfo{ 7221 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7222 }, 7223 }, 7224 }, 7225 { 7226 name: "DIVSDloadidx1", 7227 auxType: auxSymOff, 7228 argLen: 4, 7229 resultInArg0: true, 7230 symEffect: SymRead, 7231 asm: x86.ADIVSD, 7232 scale: 1, 7233 reg: regInfo{ 7234 inputs: []inputInfo{ 7235 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7236 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7237 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7238 }, 7239 outputs: []outputInfo{ 7240 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7241 }, 7242 }, 7243 }, 7244 { 7245 name: "DIVSDloadidx8", 7246 auxType: auxSymOff, 7247 argLen: 4, 7248 resultInArg0: true, 7249 symEffect: SymRead, 7250 asm: x86.ADIVSD, 7251 scale: 8, 7252 reg: regInfo{ 7253 inputs: []inputInfo{ 7254 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7255 {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 7256 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7257 }, 7258 outputs: []outputInfo{ 7259 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 7260 }, 7261 }, 7262 }, 7263 { 7264 name: "ADDQ", 7265 argLen: 2, 7266 commutative: true, 7267 clobberFlags: true, 7268 asm: x86.AADDQ, 7269 reg: regInfo{ 7270 inputs: []inputInfo{ 7271 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7272 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7273 }, 7274 outputs: []outputInfo{ 7275 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7276 }, 7277 }, 7278 }, 7279 { 7280 name: "ADDL", 7281 argLen: 2, 7282 commutative: true, 7283 clobberFlags: true, 7284 asm: x86.AADDL, 7285 reg: regInfo{ 7286 inputs: []inputInfo{ 7287 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7288 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7289 }, 7290 outputs: []outputInfo{ 7291 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7292 }, 7293 }, 7294 }, 7295 { 7296 name: "ADDQconst", 7297 auxType: auxInt32, 7298 argLen: 1, 7299 clobberFlags: true, 7300 asm: x86.AADDQ, 7301 reg: regInfo{ 7302 inputs: []inputInfo{ 7303 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7304 }, 7305 outputs: []outputInfo{ 7306 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7307 }, 7308 }, 7309 }, 7310 { 7311 name: "ADDLconst", 7312 auxType: auxInt32, 7313 argLen: 1, 7314 clobberFlags: true, 7315 asm: x86.AADDL, 7316 reg: regInfo{ 7317 inputs: []inputInfo{ 7318 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7319 }, 7320 outputs: []outputInfo{ 7321 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7322 }, 7323 }, 7324 }, 7325 { 7326 name: "ADDQconstmodify", 7327 auxType: auxSymValAndOff, 7328 argLen: 2, 7329 clobberFlags: true, 7330 faultOnNilArg0: true, 7331 symEffect: SymRead | SymWrite, 7332 asm: x86.AADDQ, 7333 reg: regInfo{ 7334 inputs: []inputInfo{ 7335 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7336 }, 7337 }, 7338 }, 7339 { 7340 name: "ADDLconstmodify", 7341 auxType: auxSymValAndOff, 7342 argLen: 2, 7343 clobberFlags: true, 7344 faultOnNilArg0: true, 7345 symEffect: SymRead | SymWrite, 7346 asm: x86.AADDL, 7347 reg: regInfo{ 7348 inputs: []inputInfo{ 7349 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7350 }, 7351 }, 7352 }, 7353 { 7354 name: "SUBQ", 7355 argLen: 2, 7356 resultInArg0: true, 7357 clobberFlags: true, 7358 asm: x86.ASUBQ, 7359 reg: regInfo{ 7360 inputs: []inputInfo{ 7361 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7362 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7363 }, 7364 outputs: []outputInfo{ 7365 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7366 }, 7367 }, 7368 }, 7369 { 7370 name: "SUBL", 7371 argLen: 2, 7372 resultInArg0: true, 7373 clobberFlags: true, 7374 asm: x86.ASUBL, 7375 reg: regInfo{ 7376 inputs: []inputInfo{ 7377 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7378 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7379 }, 7380 outputs: []outputInfo{ 7381 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7382 }, 7383 }, 7384 }, 7385 { 7386 name: "SUBQconst", 7387 auxType: auxInt32, 7388 argLen: 1, 7389 resultInArg0: true, 7390 clobberFlags: true, 7391 asm: x86.ASUBQ, 7392 reg: regInfo{ 7393 inputs: []inputInfo{ 7394 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7395 }, 7396 outputs: []outputInfo{ 7397 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7398 }, 7399 }, 7400 }, 7401 { 7402 name: "SUBLconst", 7403 auxType: auxInt32, 7404 argLen: 1, 7405 resultInArg0: true, 7406 clobberFlags: true, 7407 asm: x86.ASUBL, 7408 reg: regInfo{ 7409 inputs: []inputInfo{ 7410 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7411 }, 7412 outputs: []outputInfo{ 7413 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7414 }, 7415 }, 7416 }, 7417 { 7418 name: "MULQ", 7419 argLen: 2, 7420 commutative: true, 7421 resultInArg0: true, 7422 clobberFlags: true, 7423 asm: x86.AIMULQ, 7424 reg: regInfo{ 7425 inputs: []inputInfo{ 7426 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7427 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7428 }, 7429 outputs: []outputInfo{ 7430 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7431 }, 7432 }, 7433 }, 7434 { 7435 name: "MULL", 7436 argLen: 2, 7437 commutative: true, 7438 resultInArg0: true, 7439 clobberFlags: true, 7440 asm: x86.AIMULL, 7441 reg: regInfo{ 7442 inputs: []inputInfo{ 7443 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7444 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7445 }, 7446 outputs: []outputInfo{ 7447 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7448 }, 7449 }, 7450 }, 7451 { 7452 name: "MULQconst", 7453 auxType: auxInt32, 7454 argLen: 1, 7455 clobberFlags: true, 7456 asm: x86.AIMUL3Q, 7457 reg: regInfo{ 7458 inputs: []inputInfo{ 7459 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7460 }, 7461 outputs: []outputInfo{ 7462 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7463 }, 7464 }, 7465 }, 7466 { 7467 name: "MULLconst", 7468 auxType: auxInt32, 7469 argLen: 1, 7470 clobberFlags: true, 7471 asm: x86.AIMUL3L, 7472 reg: regInfo{ 7473 inputs: []inputInfo{ 7474 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7475 }, 7476 outputs: []outputInfo{ 7477 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7478 }, 7479 }, 7480 }, 7481 { 7482 name: "MULLU", 7483 argLen: 2, 7484 commutative: true, 7485 clobberFlags: true, 7486 asm: x86.AMULL, 7487 reg: regInfo{ 7488 inputs: []inputInfo{ 7489 {0, 1}, // AX 7490 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7491 }, 7492 clobbers: 4, // DX 7493 outputs: []outputInfo{ 7494 {1, 0}, 7495 {0, 1}, // AX 7496 }, 7497 }, 7498 }, 7499 { 7500 name: "MULQU", 7501 argLen: 2, 7502 commutative: true, 7503 clobberFlags: true, 7504 asm: x86.AMULQ, 7505 reg: regInfo{ 7506 inputs: []inputInfo{ 7507 {0, 1}, // AX 7508 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7509 }, 7510 clobbers: 4, // DX 7511 outputs: []outputInfo{ 7512 {1, 0}, 7513 {0, 1}, // AX 7514 }, 7515 }, 7516 }, 7517 { 7518 name: "HMULQ", 7519 argLen: 2, 7520 clobberFlags: true, 7521 asm: x86.AIMULQ, 7522 reg: regInfo{ 7523 inputs: []inputInfo{ 7524 {0, 1}, // AX 7525 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7526 }, 7527 clobbers: 1, // AX 7528 outputs: []outputInfo{ 7529 {0, 4}, // DX 7530 }, 7531 }, 7532 }, 7533 { 7534 name: "HMULL", 7535 argLen: 2, 7536 clobberFlags: true, 7537 asm: x86.AIMULL, 7538 reg: regInfo{ 7539 inputs: []inputInfo{ 7540 {0, 1}, // AX 7541 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7542 }, 7543 clobbers: 1, // AX 7544 outputs: []outputInfo{ 7545 {0, 4}, // DX 7546 }, 7547 }, 7548 }, 7549 { 7550 name: "HMULQU", 7551 argLen: 2, 7552 clobberFlags: true, 7553 asm: x86.AMULQ, 7554 reg: regInfo{ 7555 inputs: []inputInfo{ 7556 {0, 1}, // AX 7557 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7558 }, 7559 clobbers: 1, // AX 7560 outputs: []outputInfo{ 7561 {0, 4}, // DX 7562 }, 7563 }, 7564 }, 7565 { 7566 name: "HMULLU", 7567 argLen: 2, 7568 clobberFlags: true, 7569 asm: x86.AMULL, 7570 reg: regInfo{ 7571 inputs: []inputInfo{ 7572 {0, 1}, // AX 7573 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7574 }, 7575 clobbers: 1, // AX 7576 outputs: []outputInfo{ 7577 {0, 4}, // DX 7578 }, 7579 }, 7580 }, 7581 { 7582 name: "AVGQU", 7583 argLen: 2, 7584 commutative: true, 7585 resultInArg0: true, 7586 clobberFlags: true, 7587 reg: regInfo{ 7588 inputs: []inputInfo{ 7589 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7590 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7591 }, 7592 outputs: []outputInfo{ 7593 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7594 }, 7595 }, 7596 }, 7597 { 7598 name: "DIVQ", 7599 auxType: auxBool, 7600 argLen: 2, 7601 clobberFlags: true, 7602 asm: x86.AIDIVQ, 7603 reg: regInfo{ 7604 inputs: []inputInfo{ 7605 {0, 1}, // AX 7606 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7607 }, 7608 outputs: []outputInfo{ 7609 {0, 1}, // AX 7610 {1, 4}, // DX 7611 }, 7612 }, 7613 }, 7614 { 7615 name: "DIVL", 7616 auxType: auxBool, 7617 argLen: 2, 7618 clobberFlags: true, 7619 asm: x86.AIDIVL, 7620 reg: regInfo{ 7621 inputs: []inputInfo{ 7622 {0, 1}, // AX 7623 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7624 }, 7625 outputs: []outputInfo{ 7626 {0, 1}, // AX 7627 {1, 4}, // DX 7628 }, 7629 }, 7630 }, 7631 { 7632 name: "DIVW", 7633 auxType: auxBool, 7634 argLen: 2, 7635 clobberFlags: true, 7636 asm: x86.AIDIVW, 7637 reg: regInfo{ 7638 inputs: []inputInfo{ 7639 {0, 1}, // AX 7640 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7641 }, 7642 outputs: []outputInfo{ 7643 {0, 1}, // AX 7644 {1, 4}, // DX 7645 }, 7646 }, 7647 }, 7648 { 7649 name: "DIVQU", 7650 argLen: 2, 7651 clobberFlags: true, 7652 asm: x86.ADIVQ, 7653 reg: regInfo{ 7654 inputs: []inputInfo{ 7655 {0, 1}, // AX 7656 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7657 }, 7658 outputs: []outputInfo{ 7659 {0, 1}, // AX 7660 {1, 4}, // DX 7661 }, 7662 }, 7663 }, 7664 { 7665 name: "DIVLU", 7666 argLen: 2, 7667 clobberFlags: true, 7668 asm: x86.ADIVL, 7669 reg: regInfo{ 7670 inputs: []inputInfo{ 7671 {0, 1}, // AX 7672 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7673 }, 7674 outputs: []outputInfo{ 7675 {0, 1}, // AX 7676 {1, 4}, // DX 7677 }, 7678 }, 7679 }, 7680 { 7681 name: "DIVWU", 7682 argLen: 2, 7683 clobberFlags: true, 7684 asm: x86.ADIVW, 7685 reg: regInfo{ 7686 inputs: []inputInfo{ 7687 {0, 1}, // AX 7688 {1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7689 }, 7690 outputs: []outputInfo{ 7691 {0, 1}, // AX 7692 {1, 4}, // DX 7693 }, 7694 }, 7695 }, 7696 { 7697 name: "NEGLflags", 7698 argLen: 1, 7699 resultInArg0: true, 7700 asm: x86.ANEGL, 7701 reg: regInfo{ 7702 inputs: []inputInfo{ 7703 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7704 }, 7705 outputs: []outputInfo{ 7706 {1, 0}, 7707 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7708 }, 7709 }, 7710 }, 7711 { 7712 name: "ADDQcarry", 7713 argLen: 2, 7714 commutative: true, 7715 resultInArg0: true, 7716 asm: x86.AADDQ, 7717 reg: regInfo{ 7718 inputs: []inputInfo{ 7719 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7720 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7721 }, 7722 outputs: []outputInfo{ 7723 {1, 0}, 7724 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7725 }, 7726 }, 7727 }, 7728 { 7729 name: "ADCQ", 7730 argLen: 3, 7731 commutative: true, 7732 resultInArg0: true, 7733 asm: x86.AADCQ, 7734 reg: regInfo{ 7735 inputs: []inputInfo{ 7736 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7737 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7738 }, 7739 outputs: []outputInfo{ 7740 {1, 0}, 7741 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7742 }, 7743 }, 7744 }, 7745 { 7746 name: "ADDQconstcarry", 7747 auxType: auxInt32, 7748 argLen: 1, 7749 resultInArg0: true, 7750 asm: x86.AADDQ, 7751 reg: regInfo{ 7752 inputs: []inputInfo{ 7753 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7754 }, 7755 outputs: []outputInfo{ 7756 {1, 0}, 7757 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7758 }, 7759 }, 7760 }, 7761 { 7762 name: "ADCQconst", 7763 auxType: auxInt32, 7764 argLen: 2, 7765 resultInArg0: true, 7766 asm: x86.AADCQ, 7767 reg: regInfo{ 7768 inputs: []inputInfo{ 7769 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7770 }, 7771 outputs: []outputInfo{ 7772 {1, 0}, 7773 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7774 }, 7775 }, 7776 }, 7777 { 7778 name: "SUBQborrow", 7779 argLen: 2, 7780 resultInArg0: true, 7781 asm: x86.ASUBQ, 7782 reg: regInfo{ 7783 inputs: []inputInfo{ 7784 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7785 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7786 }, 7787 outputs: []outputInfo{ 7788 {1, 0}, 7789 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7790 }, 7791 }, 7792 }, 7793 { 7794 name: "SBBQ", 7795 argLen: 3, 7796 resultInArg0: true, 7797 asm: x86.ASBBQ, 7798 reg: regInfo{ 7799 inputs: []inputInfo{ 7800 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7801 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7802 }, 7803 outputs: []outputInfo{ 7804 {1, 0}, 7805 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7806 }, 7807 }, 7808 }, 7809 { 7810 name: "SUBQconstborrow", 7811 auxType: auxInt32, 7812 argLen: 1, 7813 resultInArg0: true, 7814 asm: x86.ASUBQ, 7815 reg: regInfo{ 7816 inputs: []inputInfo{ 7817 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7818 }, 7819 outputs: []outputInfo{ 7820 {1, 0}, 7821 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7822 }, 7823 }, 7824 }, 7825 { 7826 name: "SBBQconst", 7827 auxType: auxInt32, 7828 argLen: 2, 7829 resultInArg0: true, 7830 asm: x86.ASBBQ, 7831 reg: regInfo{ 7832 inputs: []inputInfo{ 7833 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7834 }, 7835 outputs: []outputInfo{ 7836 {1, 0}, 7837 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7838 }, 7839 }, 7840 }, 7841 { 7842 name: "MULQU2", 7843 argLen: 2, 7844 commutative: true, 7845 clobberFlags: true, 7846 asm: x86.AMULQ, 7847 reg: regInfo{ 7848 inputs: []inputInfo{ 7849 {0, 1}, // AX 7850 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7851 }, 7852 outputs: []outputInfo{ 7853 {0, 4}, // DX 7854 {1, 1}, // AX 7855 }, 7856 }, 7857 }, 7858 { 7859 name: "DIVQU2", 7860 argLen: 3, 7861 clobberFlags: true, 7862 asm: x86.ADIVQ, 7863 reg: regInfo{ 7864 inputs: []inputInfo{ 7865 {0, 4}, // DX 7866 {1, 1}, // AX 7867 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 7868 }, 7869 outputs: []outputInfo{ 7870 {0, 1}, // AX 7871 {1, 4}, // DX 7872 }, 7873 }, 7874 }, 7875 { 7876 name: "ANDQ", 7877 argLen: 2, 7878 commutative: true, 7879 resultInArg0: true, 7880 clobberFlags: true, 7881 asm: x86.AANDQ, 7882 reg: regInfo{ 7883 inputs: []inputInfo{ 7884 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7885 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7886 }, 7887 outputs: []outputInfo{ 7888 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7889 }, 7890 }, 7891 }, 7892 { 7893 name: "ANDL", 7894 argLen: 2, 7895 commutative: true, 7896 resultInArg0: true, 7897 clobberFlags: true, 7898 asm: x86.AANDL, 7899 reg: regInfo{ 7900 inputs: []inputInfo{ 7901 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7902 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7903 }, 7904 outputs: []outputInfo{ 7905 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7906 }, 7907 }, 7908 }, 7909 { 7910 name: "ANDQconst", 7911 auxType: auxInt32, 7912 argLen: 1, 7913 resultInArg0: true, 7914 clobberFlags: true, 7915 asm: x86.AANDQ, 7916 reg: regInfo{ 7917 inputs: []inputInfo{ 7918 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7919 }, 7920 outputs: []outputInfo{ 7921 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7922 }, 7923 }, 7924 }, 7925 { 7926 name: "ANDLconst", 7927 auxType: auxInt32, 7928 argLen: 1, 7929 resultInArg0: true, 7930 clobberFlags: true, 7931 asm: x86.AANDL, 7932 reg: regInfo{ 7933 inputs: []inputInfo{ 7934 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7935 }, 7936 outputs: []outputInfo{ 7937 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7938 }, 7939 }, 7940 }, 7941 { 7942 name: "ANDQconstmodify", 7943 auxType: auxSymValAndOff, 7944 argLen: 2, 7945 clobberFlags: true, 7946 faultOnNilArg0: true, 7947 symEffect: SymRead | SymWrite, 7948 asm: x86.AANDQ, 7949 reg: regInfo{ 7950 inputs: []inputInfo{ 7951 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7952 }, 7953 }, 7954 }, 7955 { 7956 name: "ANDLconstmodify", 7957 auxType: auxSymValAndOff, 7958 argLen: 2, 7959 clobberFlags: true, 7960 faultOnNilArg0: true, 7961 symEffect: SymRead | SymWrite, 7962 asm: x86.AANDL, 7963 reg: regInfo{ 7964 inputs: []inputInfo{ 7965 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 7966 }, 7967 }, 7968 }, 7969 { 7970 name: "ORQ", 7971 argLen: 2, 7972 commutative: true, 7973 resultInArg0: true, 7974 clobberFlags: true, 7975 asm: x86.AORQ, 7976 reg: regInfo{ 7977 inputs: []inputInfo{ 7978 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7979 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7980 }, 7981 outputs: []outputInfo{ 7982 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7983 }, 7984 }, 7985 }, 7986 { 7987 name: "ORL", 7988 argLen: 2, 7989 commutative: true, 7990 resultInArg0: true, 7991 clobberFlags: true, 7992 asm: x86.AORL, 7993 reg: regInfo{ 7994 inputs: []inputInfo{ 7995 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7996 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 7997 }, 7998 outputs: []outputInfo{ 7999 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8000 }, 8001 }, 8002 }, 8003 { 8004 name: "ORQconst", 8005 auxType: auxInt32, 8006 argLen: 1, 8007 resultInArg0: true, 8008 clobberFlags: true, 8009 asm: x86.AORQ, 8010 reg: regInfo{ 8011 inputs: []inputInfo{ 8012 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8013 }, 8014 outputs: []outputInfo{ 8015 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8016 }, 8017 }, 8018 }, 8019 { 8020 name: "ORLconst", 8021 auxType: auxInt32, 8022 argLen: 1, 8023 resultInArg0: true, 8024 clobberFlags: true, 8025 asm: x86.AORL, 8026 reg: regInfo{ 8027 inputs: []inputInfo{ 8028 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8029 }, 8030 outputs: []outputInfo{ 8031 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8032 }, 8033 }, 8034 }, 8035 { 8036 name: "ORQconstmodify", 8037 auxType: auxSymValAndOff, 8038 argLen: 2, 8039 clobberFlags: true, 8040 faultOnNilArg0: true, 8041 symEffect: SymRead | SymWrite, 8042 asm: x86.AORQ, 8043 reg: regInfo{ 8044 inputs: []inputInfo{ 8045 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8046 }, 8047 }, 8048 }, 8049 { 8050 name: "ORLconstmodify", 8051 auxType: auxSymValAndOff, 8052 argLen: 2, 8053 clobberFlags: true, 8054 faultOnNilArg0: true, 8055 symEffect: SymRead | SymWrite, 8056 asm: x86.AORL, 8057 reg: regInfo{ 8058 inputs: []inputInfo{ 8059 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8060 }, 8061 }, 8062 }, 8063 { 8064 name: "XORQ", 8065 argLen: 2, 8066 commutative: true, 8067 resultInArg0: true, 8068 clobberFlags: true, 8069 asm: x86.AXORQ, 8070 reg: regInfo{ 8071 inputs: []inputInfo{ 8072 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8073 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8074 }, 8075 outputs: []outputInfo{ 8076 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8077 }, 8078 }, 8079 }, 8080 { 8081 name: "XORL", 8082 argLen: 2, 8083 commutative: true, 8084 resultInArg0: true, 8085 clobberFlags: true, 8086 asm: x86.AXORL, 8087 reg: regInfo{ 8088 inputs: []inputInfo{ 8089 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8090 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8091 }, 8092 outputs: []outputInfo{ 8093 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8094 }, 8095 }, 8096 }, 8097 { 8098 name: "XORQconst", 8099 auxType: auxInt32, 8100 argLen: 1, 8101 resultInArg0: true, 8102 clobberFlags: true, 8103 asm: x86.AXORQ, 8104 reg: regInfo{ 8105 inputs: []inputInfo{ 8106 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8107 }, 8108 outputs: []outputInfo{ 8109 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8110 }, 8111 }, 8112 }, 8113 { 8114 name: "XORLconst", 8115 auxType: auxInt32, 8116 argLen: 1, 8117 resultInArg0: true, 8118 clobberFlags: true, 8119 asm: x86.AXORL, 8120 reg: regInfo{ 8121 inputs: []inputInfo{ 8122 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8123 }, 8124 outputs: []outputInfo{ 8125 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8126 }, 8127 }, 8128 }, 8129 { 8130 name: "XORQconstmodify", 8131 auxType: auxSymValAndOff, 8132 argLen: 2, 8133 clobberFlags: true, 8134 faultOnNilArg0: true, 8135 symEffect: SymRead | SymWrite, 8136 asm: x86.AXORQ, 8137 reg: regInfo{ 8138 inputs: []inputInfo{ 8139 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8140 }, 8141 }, 8142 }, 8143 { 8144 name: "XORLconstmodify", 8145 auxType: auxSymValAndOff, 8146 argLen: 2, 8147 clobberFlags: true, 8148 faultOnNilArg0: true, 8149 symEffect: SymRead | SymWrite, 8150 asm: x86.AXORL, 8151 reg: regInfo{ 8152 inputs: []inputInfo{ 8153 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8154 }, 8155 }, 8156 }, 8157 { 8158 name: "CMPQ", 8159 argLen: 2, 8160 asm: x86.ACMPQ, 8161 reg: regInfo{ 8162 inputs: []inputInfo{ 8163 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8164 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8165 }, 8166 }, 8167 }, 8168 { 8169 name: "CMPL", 8170 argLen: 2, 8171 asm: x86.ACMPL, 8172 reg: regInfo{ 8173 inputs: []inputInfo{ 8174 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8175 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8176 }, 8177 }, 8178 }, 8179 { 8180 name: "CMPW", 8181 argLen: 2, 8182 asm: x86.ACMPW, 8183 reg: regInfo{ 8184 inputs: []inputInfo{ 8185 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8186 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8187 }, 8188 }, 8189 }, 8190 { 8191 name: "CMPB", 8192 argLen: 2, 8193 asm: x86.ACMPB, 8194 reg: regInfo{ 8195 inputs: []inputInfo{ 8196 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8197 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8198 }, 8199 }, 8200 }, 8201 { 8202 name: "CMPQconst", 8203 auxType: auxInt32, 8204 argLen: 1, 8205 asm: x86.ACMPQ, 8206 reg: regInfo{ 8207 inputs: []inputInfo{ 8208 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8209 }, 8210 }, 8211 }, 8212 { 8213 name: "CMPLconst", 8214 auxType: auxInt32, 8215 argLen: 1, 8216 asm: x86.ACMPL, 8217 reg: regInfo{ 8218 inputs: []inputInfo{ 8219 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8220 }, 8221 }, 8222 }, 8223 { 8224 name: "CMPWconst", 8225 auxType: auxInt16, 8226 argLen: 1, 8227 asm: x86.ACMPW, 8228 reg: regInfo{ 8229 inputs: []inputInfo{ 8230 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8231 }, 8232 }, 8233 }, 8234 { 8235 name: "CMPBconst", 8236 auxType: auxInt8, 8237 argLen: 1, 8238 asm: x86.ACMPB, 8239 reg: regInfo{ 8240 inputs: []inputInfo{ 8241 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8242 }, 8243 }, 8244 }, 8245 { 8246 name: "CMPQload", 8247 auxType: auxSymOff, 8248 argLen: 3, 8249 faultOnNilArg0: true, 8250 symEffect: SymRead, 8251 asm: x86.ACMPQ, 8252 reg: regInfo{ 8253 inputs: []inputInfo{ 8254 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8255 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8256 }, 8257 }, 8258 }, 8259 { 8260 name: "CMPLload", 8261 auxType: auxSymOff, 8262 argLen: 3, 8263 faultOnNilArg0: true, 8264 symEffect: SymRead, 8265 asm: x86.ACMPL, 8266 reg: regInfo{ 8267 inputs: []inputInfo{ 8268 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8269 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8270 }, 8271 }, 8272 }, 8273 { 8274 name: "CMPWload", 8275 auxType: auxSymOff, 8276 argLen: 3, 8277 faultOnNilArg0: true, 8278 symEffect: SymRead, 8279 asm: x86.ACMPW, 8280 reg: regInfo{ 8281 inputs: []inputInfo{ 8282 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8283 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8284 }, 8285 }, 8286 }, 8287 { 8288 name: "CMPBload", 8289 auxType: auxSymOff, 8290 argLen: 3, 8291 faultOnNilArg0: true, 8292 symEffect: SymRead, 8293 asm: x86.ACMPB, 8294 reg: regInfo{ 8295 inputs: []inputInfo{ 8296 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8297 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8298 }, 8299 }, 8300 }, 8301 { 8302 name: "CMPQconstload", 8303 auxType: auxSymValAndOff, 8304 argLen: 2, 8305 faultOnNilArg0: true, 8306 symEffect: SymRead, 8307 asm: x86.ACMPQ, 8308 reg: regInfo{ 8309 inputs: []inputInfo{ 8310 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8311 }, 8312 }, 8313 }, 8314 { 8315 name: "CMPLconstload", 8316 auxType: auxSymValAndOff, 8317 argLen: 2, 8318 faultOnNilArg0: true, 8319 symEffect: SymRead, 8320 asm: x86.ACMPL, 8321 reg: regInfo{ 8322 inputs: []inputInfo{ 8323 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8324 }, 8325 }, 8326 }, 8327 { 8328 name: "CMPWconstload", 8329 auxType: auxSymValAndOff, 8330 argLen: 2, 8331 faultOnNilArg0: true, 8332 symEffect: SymRead, 8333 asm: x86.ACMPW, 8334 reg: regInfo{ 8335 inputs: []inputInfo{ 8336 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8337 }, 8338 }, 8339 }, 8340 { 8341 name: "CMPBconstload", 8342 auxType: auxSymValAndOff, 8343 argLen: 2, 8344 faultOnNilArg0: true, 8345 symEffect: SymRead, 8346 asm: x86.ACMPB, 8347 reg: regInfo{ 8348 inputs: []inputInfo{ 8349 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8350 }, 8351 }, 8352 }, 8353 { 8354 name: "CMPQloadidx8", 8355 auxType: auxSymOff, 8356 argLen: 4, 8357 symEffect: SymRead, 8358 asm: x86.ACMPQ, 8359 scale: 8, 8360 reg: regInfo{ 8361 inputs: []inputInfo{ 8362 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8363 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8364 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8365 }, 8366 }, 8367 }, 8368 { 8369 name: "CMPQloadidx1", 8370 auxType: auxSymOff, 8371 argLen: 4, 8372 commutative: true, 8373 symEffect: SymRead, 8374 asm: x86.ACMPQ, 8375 scale: 1, 8376 reg: regInfo{ 8377 inputs: []inputInfo{ 8378 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8379 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8380 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8381 }, 8382 }, 8383 }, 8384 { 8385 name: "CMPLloadidx4", 8386 auxType: auxSymOff, 8387 argLen: 4, 8388 symEffect: SymRead, 8389 asm: x86.ACMPL, 8390 scale: 4, 8391 reg: regInfo{ 8392 inputs: []inputInfo{ 8393 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8394 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8395 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8396 }, 8397 }, 8398 }, 8399 { 8400 name: "CMPLloadidx1", 8401 auxType: auxSymOff, 8402 argLen: 4, 8403 commutative: true, 8404 symEffect: SymRead, 8405 asm: x86.ACMPL, 8406 scale: 1, 8407 reg: regInfo{ 8408 inputs: []inputInfo{ 8409 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8410 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8411 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8412 }, 8413 }, 8414 }, 8415 { 8416 name: "CMPWloadidx2", 8417 auxType: auxSymOff, 8418 argLen: 4, 8419 symEffect: SymRead, 8420 asm: x86.ACMPW, 8421 scale: 2, 8422 reg: regInfo{ 8423 inputs: []inputInfo{ 8424 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8425 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8426 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8427 }, 8428 }, 8429 }, 8430 { 8431 name: "CMPWloadidx1", 8432 auxType: auxSymOff, 8433 argLen: 4, 8434 commutative: true, 8435 symEffect: SymRead, 8436 asm: x86.ACMPW, 8437 scale: 1, 8438 reg: regInfo{ 8439 inputs: []inputInfo{ 8440 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8441 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8442 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8443 }, 8444 }, 8445 }, 8446 { 8447 name: "CMPBloadidx1", 8448 auxType: auxSymOff, 8449 argLen: 4, 8450 commutative: true, 8451 symEffect: SymRead, 8452 asm: x86.ACMPB, 8453 scale: 1, 8454 reg: regInfo{ 8455 inputs: []inputInfo{ 8456 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8457 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8458 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8459 }, 8460 }, 8461 }, 8462 { 8463 name: "CMPQconstloadidx8", 8464 auxType: auxSymValAndOff, 8465 argLen: 3, 8466 symEffect: SymRead, 8467 asm: x86.ACMPQ, 8468 scale: 8, 8469 reg: regInfo{ 8470 inputs: []inputInfo{ 8471 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8472 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8473 }, 8474 }, 8475 }, 8476 { 8477 name: "CMPQconstloadidx1", 8478 auxType: auxSymValAndOff, 8479 argLen: 3, 8480 commutative: true, 8481 symEffect: SymRead, 8482 asm: x86.ACMPQ, 8483 scale: 1, 8484 reg: regInfo{ 8485 inputs: []inputInfo{ 8486 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8487 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8488 }, 8489 }, 8490 }, 8491 { 8492 name: "CMPLconstloadidx4", 8493 auxType: auxSymValAndOff, 8494 argLen: 3, 8495 symEffect: SymRead, 8496 asm: x86.ACMPL, 8497 scale: 4, 8498 reg: regInfo{ 8499 inputs: []inputInfo{ 8500 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8501 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8502 }, 8503 }, 8504 }, 8505 { 8506 name: "CMPLconstloadidx1", 8507 auxType: auxSymValAndOff, 8508 argLen: 3, 8509 commutative: true, 8510 symEffect: SymRead, 8511 asm: x86.ACMPL, 8512 scale: 1, 8513 reg: regInfo{ 8514 inputs: []inputInfo{ 8515 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8516 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8517 }, 8518 }, 8519 }, 8520 { 8521 name: "CMPWconstloadidx2", 8522 auxType: auxSymValAndOff, 8523 argLen: 3, 8524 symEffect: SymRead, 8525 asm: x86.ACMPW, 8526 scale: 2, 8527 reg: regInfo{ 8528 inputs: []inputInfo{ 8529 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8530 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8531 }, 8532 }, 8533 }, 8534 { 8535 name: "CMPWconstloadidx1", 8536 auxType: auxSymValAndOff, 8537 argLen: 3, 8538 commutative: true, 8539 symEffect: SymRead, 8540 asm: x86.ACMPW, 8541 scale: 1, 8542 reg: regInfo{ 8543 inputs: []inputInfo{ 8544 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8545 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8546 }, 8547 }, 8548 }, 8549 { 8550 name: "CMPBconstloadidx1", 8551 auxType: auxSymValAndOff, 8552 argLen: 3, 8553 commutative: true, 8554 symEffect: SymRead, 8555 asm: x86.ACMPB, 8556 scale: 1, 8557 reg: regInfo{ 8558 inputs: []inputInfo{ 8559 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8560 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 8561 }, 8562 }, 8563 }, 8564 { 8565 name: "UCOMISS", 8566 argLen: 2, 8567 asm: x86.AUCOMISS, 8568 reg: regInfo{ 8569 inputs: []inputInfo{ 8570 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 8571 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 8572 }, 8573 }, 8574 }, 8575 { 8576 name: "UCOMISD", 8577 argLen: 2, 8578 asm: x86.AUCOMISD, 8579 reg: regInfo{ 8580 inputs: []inputInfo{ 8581 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 8582 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 8583 }, 8584 }, 8585 }, 8586 { 8587 name: "BTL", 8588 argLen: 2, 8589 asm: x86.ABTL, 8590 reg: regInfo{ 8591 inputs: []inputInfo{ 8592 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8593 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8594 }, 8595 }, 8596 }, 8597 { 8598 name: "BTQ", 8599 argLen: 2, 8600 asm: x86.ABTQ, 8601 reg: regInfo{ 8602 inputs: []inputInfo{ 8603 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8604 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8605 }, 8606 }, 8607 }, 8608 { 8609 name: "BTCL", 8610 argLen: 2, 8611 resultInArg0: true, 8612 clobberFlags: true, 8613 asm: x86.ABTCL, 8614 reg: regInfo{ 8615 inputs: []inputInfo{ 8616 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8617 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8618 }, 8619 outputs: []outputInfo{ 8620 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8621 }, 8622 }, 8623 }, 8624 { 8625 name: "BTCQ", 8626 argLen: 2, 8627 resultInArg0: true, 8628 clobberFlags: true, 8629 asm: x86.ABTCQ, 8630 reg: regInfo{ 8631 inputs: []inputInfo{ 8632 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8633 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8634 }, 8635 outputs: []outputInfo{ 8636 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8637 }, 8638 }, 8639 }, 8640 { 8641 name: "BTRL", 8642 argLen: 2, 8643 resultInArg0: true, 8644 clobberFlags: true, 8645 asm: x86.ABTRL, 8646 reg: regInfo{ 8647 inputs: []inputInfo{ 8648 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8649 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8650 }, 8651 outputs: []outputInfo{ 8652 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8653 }, 8654 }, 8655 }, 8656 { 8657 name: "BTRQ", 8658 argLen: 2, 8659 resultInArg0: true, 8660 clobberFlags: true, 8661 asm: x86.ABTRQ, 8662 reg: regInfo{ 8663 inputs: []inputInfo{ 8664 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8665 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8666 }, 8667 outputs: []outputInfo{ 8668 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8669 }, 8670 }, 8671 }, 8672 { 8673 name: "BTSL", 8674 argLen: 2, 8675 resultInArg0: true, 8676 clobberFlags: true, 8677 asm: x86.ABTSL, 8678 reg: regInfo{ 8679 inputs: []inputInfo{ 8680 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8681 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8682 }, 8683 outputs: []outputInfo{ 8684 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8685 }, 8686 }, 8687 }, 8688 { 8689 name: "BTSQ", 8690 argLen: 2, 8691 resultInArg0: true, 8692 clobberFlags: true, 8693 asm: x86.ABTSQ, 8694 reg: regInfo{ 8695 inputs: []inputInfo{ 8696 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8697 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8698 }, 8699 outputs: []outputInfo{ 8700 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8701 }, 8702 }, 8703 }, 8704 { 8705 name: "BTLconst", 8706 auxType: auxInt8, 8707 argLen: 1, 8708 asm: x86.ABTL, 8709 reg: regInfo{ 8710 inputs: []inputInfo{ 8711 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8712 }, 8713 }, 8714 }, 8715 { 8716 name: "BTQconst", 8717 auxType: auxInt8, 8718 argLen: 1, 8719 asm: x86.ABTQ, 8720 reg: regInfo{ 8721 inputs: []inputInfo{ 8722 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8723 }, 8724 }, 8725 }, 8726 { 8727 name: "BTCLconst", 8728 auxType: auxInt8, 8729 argLen: 1, 8730 resultInArg0: true, 8731 clobberFlags: true, 8732 asm: x86.ABTCL, 8733 reg: regInfo{ 8734 inputs: []inputInfo{ 8735 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8736 }, 8737 outputs: []outputInfo{ 8738 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8739 }, 8740 }, 8741 }, 8742 { 8743 name: "BTCQconst", 8744 auxType: auxInt8, 8745 argLen: 1, 8746 resultInArg0: true, 8747 clobberFlags: true, 8748 asm: x86.ABTCQ, 8749 reg: regInfo{ 8750 inputs: []inputInfo{ 8751 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8752 }, 8753 outputs: []outputInfo{ 8754 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8755 }, 8756 }, 8757 }, 8758 { 8759 name: "BTRLconst", 8760 auxType: auxInt8, 8761 argLen: 1, 8762 resultInArg0: true, 8763 clobberFlags: true, 8764 asm: x86.ABTRL, 8765 reg: regInfo{ 8766 inputs: []inputInfo{ 8767 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8768 }, 8769 outputs: []outputInfo{ 8770 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8771 }, 8772 }, 8773 }, 8774 { 8775 name: "BTRQconst", 8776 auxType: auxInt8, 8777 argLen: 1, 8778 resultInArg0: true, 8779 clobberFlags: true, 8780 asm: x86.ABTRQ, 8781 reg: regInfo{ 8782 inputs: []inputInfo{ 8783 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8784 }, 8785 outputs: []outputInfo{ 8786 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8787 }, 8788 }, 8789 }, 8790 { 8791 name: "BTSLconst", 8792 auxType: auxInt8, 8793 argLen: 1, 8794 resultInArg0: true, 8795 clobberFlags: true, 8796 asm: x86.ABTSL, 8797 reg: regInfo{ 8798 inputs: []inputInfo{ 8799 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8800 }, 8801 outputs: []outputInfo{ 8802 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8803 }, 8804 }, 8805 }, 8806 { 8807 name: "BTSQconst", 8808 auxType: auxInt8, 8809 argLen: 1, 8810 resultInArg0: true, 8811 clobberFlags: true, 8812 asm: x86.ABTSQ, 8813 reg: regInfo{ 8814 inputs: []inputInfo{ 8815 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8816 }, 8817 outputs: []outputInfo{ 8818 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8819 }, 8820 }, 8821 }, 8822 { 8823 name: "TESTQ", 8824 argLen: 2, 8825 commutative: true, 8826 asm: x86.ATESTQ, 8827 reg: regInfo{ 8828 inputs: []inputInfo{ 8829 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8830 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8831 }, 8832 }, 8833 }, 8834 { 8835 name: "TESTL", 8836 argLen: 2, 8837 commutative: true, 8838 asm: x86.ATESTL, 8839 reg: regInfo{ 8840 inputs: []inputInfo{ 8841 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8842 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8843 }, 8844 }, 8845 }, 8846 { 8847 name: "TESTW", 8848 argLen: 2, 8849 commutative: true, 8850 asm: x86.ATESTW, 8851 reg: regInfo{ 8852 inputs: []inputInfo{ 8853 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8854 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8855 }, 8856 }, 8857 }, 8858 { 8859 name: "TESTB", 8860 argLen: 2, 8861 commutative: true, 8862 asm: x86.ATESTB, 8863 reg: regInfo{ 8864 inputs: []inputInfo{ 8865 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8866 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8867 }, 8868 }, 8869 }, 8870 { 8871 name: "TESTQconst", 8872 auxType: auxInt32, 8873 argLen: 1, 8874 asm: x86.ATESTQ, 8875 reg: regInfo{ 8876 inputs: []inputInfo{ 8877 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8878 }, 8879 }, 8880 }, 8881 { 8882 name: "TESTLconst", 8883 auxType: auxInt32, 8884 argLen: 1, 8885 asm: x86.ATESTL, 8886 reg: regInfo{ 8887 inputs: []inputInfo{ 8888 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8889 }, 8890 }, 8891 }, 8892 { 8893 name: "TESTWconst", 8894 auxType: auxInt16, 8895 argLen: 1, 8896 asm: x86.ATESTW, 8897 reg: regInfo{ 8898 inputs: []inputInfo{ 8899 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8900 }, 8901 }, 8902 }, 8903 { 8904 name: "TESTBconst", 8905 auxType: auxInt8, 8906 argLen: 1, 8907 asm: x86.ATESTB, 8908 reg: regInfo{ 8909 inputs: []inputInfo{ 8910 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 8911 }, 8912 }, 8913 }, 8914 { 8915 name: "SHLQ", 8916 argLen: 2, 8917 resultInArg0: true, 8918 clobberFlags: true, 8919 asm: x86.ASHLQ, 8920 reg: regInfo{ 8921 inputs: []inputInfo{ 8922 {1, 2}, // CX 8923 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8924 }, 8925 outputs: []outputInfo{ 8926 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8927 }, 8928 }, 8929 }, 8930 { 8931 name: "SHLL", 8932 argLen: 2, 8933 resultInArg0: true, 8934 clobberFlags: true, 8935 asm: x86.ASHLL, 8936 reg: regInfo{ 8937 inputs: []inputInfo{ 8938 {1, 2}, // CX 8939 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8940 }, 8941 outputs: []outputInfo{ 8942 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8943 }, 8944 }, 8945 }, 8946 { 8947 name: "SHLQconst", 8948 auxType: auxInt8, 8949 argLen: 1, 8950 resultInArg0: true, 8951 clobberFlags: true, 8952 asm: x86.ASHLQ, 8953 reg: regInfo{ 8954 inputs: []inputInfo{ 8955 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8956 }, 8957 outputs: []outputInfo{ 8958 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8959 }, 8960 }, 8961 }, 8962 { 8963 name: "SHLLconst", 8964 auxType: auxInt8, 8965 argLen: 1, 8966 resultInArg0: true, 8967 clobberFlags: true, 8968 asm: x86.ASHLL, 8969 reg: regInfo{ 8970 inputs: []inputInfo{ 8971 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8972 }, 8973 outputs: []outputInfo{ 8974 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8975 }, 8976 }, 8977 }, 8978 { 8979 name: "SHRQ", 8980 argLen: 2, 8981 resultInArg0: true, 8982 clobberFlags: true, 8983 asm: x86.ASHRQ, 8984 reg: regInfo{ 8985 inputs: []inputInfo{ 8986 {1, 2}, // CX 8987 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8988 }, 8989 outputs: []outputInfo{ 8990 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 8991 }, 8992 }, 8993 }, 8994 { 8995 name: "SHRL", 8996 argLen: 2, 8997 resultInArg0: true, 8998 clobberFlags: true, 8999 asm: x86.ASHRL, 9000 reg: regInfo{ 9001 inputs: []inputInfo{ 9002 {1, 2}, // CX 9003 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9004 }, 9005 outputs: []outputInfo{ 9006 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9007 }, 9008 }, 9009 }, 9010 { 9011 name: "SHRW", 9012 argLen: 2, 9013 resultInArg0: true, 9014 clobberFlags: true, 9015 asm: x86.ASHRW, 9016 reg: regInfo{ 9017 inputs: []inputInfo{ 9018 {1, 2}, // CX 9019 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9020 }, 9021 outputs: []outputInfo{ 9022 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9023 }, 9024 }, 9025 }, 9026 { 9027 name: "SHRB", 9028 argLen: 2, 9029 resultInArg0: true, 9030 clobberFlags: true, 9031 asm: x86.ASHRB, 9032 reg: regInfo{ 9033 inputs: []inputInfo{ 9034 {1, 2}, // CX 9035 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9036 }, 9037 outputs: []outputInfo{ 9038 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9039 }, 9040 }, 9041 }, 9042 { 9043 name: "SHRQconst", 9044 auxType: auxInt8, 9045 argLen: 1, 9046 resultInArg0: true, 9047 clobberFlags: true, 9048 asm: x86.ASHRQ, 9049 reg: regInfo{ 9050 inputs: []inputInfo{ 9051 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9052 }, 9053 outputs: []outputInfo{ 9054 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9055 }, 9056 }, 9057 }, 9058 { 9059 name: "SHRLconst", 9060 auxType: auxInt8, 9061 argLen: 1, 9062 resultInArg0: true, 9063 clobberFlags: true, 9064 asm: x86.ASHRL, 9065 reg: regInfo{ 9066 inputs: []inputInfo{ 9067 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9068 }, 9069 outputs: []outputInfo{ 9070 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9071 }, 9072 }, 9073 }, 9074 { 9075 name: "SHRWconst", 9076 auxType: auxInt8, 9077 argLen: 1, 9078 resultInArg0: true, 9079 clobberFlags: true, 9080 asm: x86.ASHRW, 9081 reg: regInfo{ 9082 inputs: []inputInfo{ 9083 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9084 }, 9085 outputs: []outputInfo{ 9086 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9087 }, 9088 }, 9089 }, 9090 { 9091 name: "SHRBconst", 9092 auxType: auxInt8, 9093 argLen: 1, 9094 resultInArg0: true, 9095 clobberFlags: true, 9096 asm: x86.ASHRB, 9097 reg: regInfo{ 9098 inputs: []inputInfo{ 9099 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9100 }, 9101 outputs: []outputInfo{ 9102 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9103 }, 9104 }, 9105 }, 9106 { 9107 name: "SARQ", 9108 argLen: 2, 9109 resultInArg0: true, 9110 clobberFlags: true, 9111 asm: x86.ASARQ, 9112 reg: regInfo{ 9113 inputs: []inputInfo{ 9114 {1, 2}, // CX 9115 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9116 }, 9117 outputs: []outputInfo{ 9118 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9119 }, 9120 }, 9121 }, 9122 { 9123 name: "SARL", 9124 argLen: 2, 9125 resultInArg0: true, 9126 clobberFlags: true, 9127 asm: x86.ASARL, 9128 reg: regInfo{ 9129 inputs: []inputInfo{ 9130 {1, 2}, // CX 9131 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9132 }, 9133 outputs: []outputInfo{ 9134 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9135 }, 9136 }, 9137 }, 9138 { 9139 name: "SARW", 9140 argLen: 2, 9141 resultInArg0: true, 9142 clobberFlags: true, 9143 asm: x86.ASARW, 9144 reg: regInfo{ 9145 inputs: []inputInfo{ 9146 {1, 2}, // CX 9147 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9148 }, 9149 outputs: []outputInfo{ 9150 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9151 }, 9152 }, 9153 }, 9154 { 9155 name: "SARB", 9156 argLen: 2, 9157 resultInArg0: true, 9158 clobberFlags: true, 9159 asm: x86.ASARB, 9160 reg: regInfo{ 9161 inputs: []inputInfo{ 9162 {1, 2}, // CX 9163 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9164 }, 9165 outputs: []outputInfo{ 9166 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9167 }, 9168 }, 9169 }, 9170 { 9171 name: "SARQconst", 9172 auxType: auxInt8, 9173 argLen: 1, 9174 resultInArg0: true, 9175 clobberFlags: true, 9176 asm: x86.ASARQ, 9177 reg: regInfo{ 9178 inputs: []inputInfo{ 9179 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9180 }, 9181 outputs: []outputInfo{ 9182 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9183 }, 9184 }, 9185 }, 9186 { 9187 name: "SARLconst", 9188 auxType: auxInt8, 9189 argLen: 1, 9190 resultInArg0: true, 9191 clobberFlags: true, 9192 asm: x86.ASARL, 9193 reg: regInfo{ 9194 inputs: []inputInfo{ 9195 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9196 }, 9197 outputs: []outputInfo{ 9198 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9199 }, 9200 }, 9201 }, 9202 { 9203 name: "SARWconst", 9204 auxType: auxInt8, 9205 argLen: 1, 9206 resultInArg0: true, 9207 clobberFlags: true, 9208 asm: x86.ASARW, 9209 reg: regInfo{ 9210 inputs: []inputInfo{ 9211 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9212 }, 9213 outputs: []outputInfo{ 9214 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9215 }, 9216 }, 9217 }, 9218 { 9219 name: "SARBconst", 9220 auxType: auxInt8, 9221 argLen: 1, 9222 resultInArg0: true, 9223 clobberFlags: true, 9224 asm: x86.ASARB, 9225 reg: regInfo{ 9226 inputs: []inputInfo{ 9227 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9228 }, 9229 outputs: []outputInfo{ 9230 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9231 }, 9232 }, 9233 }, 9234 { 9235 name: "SHRDQ", 9236 argLen: 3, 9237 resultInArg0: true, 9238 clobberFlags: true, 9239 asm: x86.ASHRQ, 9240 reg: regInfo{ 9241 inputs: []inputInfo{ 9242 {2, 2}, // CX 9243 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9244 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9245 }, 9246 outputs: []outputInfo{ 9247 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9248 }, 9249 }, 9250 }, 9251 { 9252 name: "SHLDQ", 9253 argLen: 3, 9254 resultInArg0: true, 9255 clobberFlags: true, 9256 asm: x86.ASHLQ, 9257 reg: regInfo{ 9258 inputs: []inputInfo{ 9259 {2, 2}, // CX 9260 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9261 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9262 }, 9263 outputs: []outputInfo{ 9264 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9265 }, 9266 }, 9267 }, 9268 { 9269 name: "ROLQ", 9270 argLen: 2, 9271 resultInArg0: true, 9272 clobberFlags: true, 9273 asm: x86.AROLQ, 9274 reg: regInfo{ 9275 inputs: []inputInfo{ 9276 {1, 2}, // CX 9277 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9278 }, 9279 outputs: []outputInfo{ 9280 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9281 }, 9282 }, 9283 }, 9284 { 9285 name: "ROLL", 9286 argLen: 2, 9287 resultInArg0: true, 9288 clobberFlags: true, 9289 asm: x86.AROLL, 9290 reg: regInfo{ 9291 inputs: []inputInfo{ 9292 {1, 2}, // CX 9293 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9294 }, 9295 outputs: []outputInfo{ 9296 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9297 }, 9298 }, 9299 }, 9300 { 9301 name: "ROLW", 9302 argLen: 2, 9303 resultInArg0: true, 9304 clobberFlags: true, 9305 asm: x86.AROLW, 9306 reg: regInfo{ 9307 inputs: []inputInfo{ 9308 {1, 2}, // CX 9309 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9310 }, 9311 outputs: []outputInfo{ 9312 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9313 }, 9314 }, 9315 }, 9316 { 9317 name: "ROLB", 9318 argLen: 2, 9319 resultInArg0: true, 9320 clobberFlags: true, 9321 asm: x86.AROLB, 9322 reg: regInfo{ 9323 inputs: []inputInfo{ 9324 {1, 2}, // CX 9325 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9326 }, 9327 outputs: []outputInfo{ 9328 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9329 }, 9330 }, 9331 }, 9332 { 9333 name: "RORQ", 9334 argLen: 2, 9335 resultInArg0: true, 9336 clobberFlags: true, 9337 asm: x86.ARORQ, 9338 reg: regInfo{ 9339 inputs: []inputInfo{ 9340 {1, 2}, // CX 9341 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9342 }, 9343 outputs: []outputInfo{ 9344 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9345 }, 9346 }, 9347 }, 9348 { 9349 name: "RORL", 9350 argLen: 2, 9351 resultInArg0: true, 9352 clobberFlags: true, 9353 asm: x86.ARORL, 9354 reg: regInfo{ 9355 inputs: []inputInfo{ 9356 {1, 2}, // CX 9357 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9358 }, 9359 outputs: []outputInfo{ 9360 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9361 }, 9362 }, 9363 }, 9364 { 9365 name: "RORW", 9366 argLen: 2, 9367 resultInArg0: true, 9368 clobberFlags: true, 9369 asm: x86.ARORW, 9370 reg: regInfo{ 9371 inputs: []inputInfo{ 9372 {1, 2}, // CX 9373 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9374 }, 9375 outputs: []outputInfo{ 9376 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9377 }, 9378 }, 9379 }, 9380 { 9381 name: "RORB", 9382 argLen: 2, 9383 resultInArg0: true, 9384 clobberFlags: true, 9385 asm: x86.ARORB, 9386 reg: regInfo{ 9387 inputs: []inputInfo{ 9388 {1, 2}, // CX 9389 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9390 }, 9391 outputs: []outputInfo{ 9392 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9393 }, 9394 }, 9395 }, 9396 { 9397 name: "ROLQconst", 9398 auxType: auxInt8, 9399 argLen: 1, 9400 resultInArg0: true, 9401 clobberFlags: true, 9402 asm: x86.AROLQ, 9403 reg: regInfo{ 9404 inputs: []inputInfo{ 9405 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9406 }, 9407 outputs: []outputInfo{ 9408 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9409 }, 9410 }, 9411 }, 9412 { 9413 name: "ROLLconst", 9414 auxType: auxInt8, 9415 argLen: 1, 9416 resultInArg0: true, 9417 clobberFlags: true, 9418 asm: x86.AROLL, 9419 reg: regInfo{ 9420 inputs: []inputInfo{ 9421 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9422 }, 9423 outputs: []outputInfo{ 9424 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9425 }, 9426 }, 9427 }, 9428 { 9429 name: "ROLWconst", 9430 auxType: auxInt8, 9431 argLen: 1, 9432 resultInArg0: true, 9433 clobberFlags: true, 9434 asm: x86.AROLW, 9435 reg: regInfo{ 9436 inputs: []inputInfo{ 9437 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9438 }, 9439 outputs: []outputInfo{ 9440 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9441 }, 9442 }, 9443 }, 9444 { 9445 name: "ROLBconst", 9446 auxType: auxInt8, 9447 argLen: 1, 9448 resultInArg0: true, 9449 clobberFlags: true, 9450 asm: x86.AROLB, 9451 reg: regInfo{ 9452 inputs: []inputInfo{ 9453 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9454 }, 9455 outputs: []outputInfo{ 9456 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9457 }, 9458 }, 9459 }, 9460 { 9461 name: "ADDLload", 9462 auxType: auxSymOff, 9463 argLen: 3, 9464 resultInArg0: true, 9465 clobberFlags: true, 9466 faultOnNilArg1: true, 9467 symEffect: SymRead, 9468 asm: x86.AADDL, 9469 reg: regInfo{ 9470 inputs: []inputInfo{ 9471 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9472 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9473 }, 9474 outputs: []outputInfo{ 9475 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9476 }, 9477 }, 9478 }, 9479 { 9480 name: "ADDQload", 9481 auxType: auxSymOff, 9482 argLen: 3, 9483 resultInArg0: true, 9484 clobberFlags: true, 9485 faultOnNilArg1: true, 9486 symEffect: SymRead, 9487 asm: x86.AADDQ, 9488 reg: regInfo{ 9489 inputs: []inputInfo{ 9490 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9491 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9492 }, 9493 outputs: []outputInfo{ 9494 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9495 }, 9496 }, 9497 }, 9498 { 9499 name: "SUBQload", 9500 auxType: auxSymOff, 9501 argLen: 3, 9502 resultInArg0: true, 9503 clobberFlags: true, 9504 faultOnNilArg1: true, 9505 symEffect: SymRead, 9506 asm: x86.ASUBQ, 9507 reg: regInfo{ 9508 inputs: []inputInfo{ 9509 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9510 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9511 }, 9512 outputs: []outputInfo{ 9513 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9514 }, 9515 }, 9516 }, 9517 { 9518 name: "SUBLload", 9519 auxType: auxSymOff, 9520 argLen: 3, 9521 resultInArg0: true, 9522 clobberFlags: true, 9523 faultOnNilArg1: true, 9524 symEffect: SymRead, 9525 asm: x86.ASUBL, 9526 reg: regInfo{ 9527 inputs: []inputInfo{ 9528 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9529 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9530 }, 9531 outputs: []outputInfo{ 9532 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9533 }, 9534 }, 9535 }, 9536 { 9537 name: "ANDLload", 9538 auxType: auxSymOff, 9539 argLen: 3, 9540 resultInArg0: true, 9541 clobberFlags: true, 9542 faultOnNilArg1: true, 9543 symEffect: SymRead, 9544 asm: x86.AANDL, 9545 reg: regInfo{ 9546 inputs: []inputInfo{ 9547 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9548 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9549 }, 9550 outputs: []outputInfo{ 9551 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9552 }, 9553 }, 9554 }, 9555 { 9556 name: "ANDQload", 9557 auxType: auxSymOff, 9558 argLen: 3, 9559 resultInArg0: true, 9560 clobberFlags: true, 9561 faultOnNilArg1: true, 9562 symEffect: SymRead, 9563 asm: x86.AANDQ, 9564 reg: regInfo{ 9565 inputs: []inputInfo{ 9566 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9567 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9568 }, 9569 outputs: []outputInfo{ 9570 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9571 }, 9572 }, 9573 }, 9574 { 9575 name: "ORQload", 9576 auxType: auxSymOff, 9577 argLen: 3, 9578 resultInArg0: true, 9579 clobberFlags: true, 9580 faultOnNilArg1: true, 9581 symEffect: SymRead, 9582 asm: x86.AORQ, 9583 reg: regInfo{ 9584 inputs: []inputInfo{ 9585 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9586 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9587 }, 9588 outputs: []outputInfo{ 9589 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9590 }, 9591 }, 9592 }, 9593 { 9594 name: "ORLload", 9595 auxType: auxSymOff, 9596 argLen: 3, 9597 resultInArg0: true, 9598 clobberFlags: true, 9599 faultOnNilArg1: true, 9600 symEffect: SymRead, 9601 asm: x86.AORL, 9602 reg: regInfo{ 9603 inputs: []inputInfo{ 9604 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9605 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9606 }, 9607 outputs: []outputInfo{ 9608 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9609 }, 9610 }, 9611 }, 9612 { 9613 name: "XORQload", 9614 auxType: auxSymOff, 9615 argLen: 3, 9616 resultInArg0: true, 9617 clobberFlags: true, 9618 faultOnNilArg1: true, 9619 symEffect: SymRead, 9620 asm: x86.AXORQ, 9621 reg: regInfo{ 9622 inputs: []inputInfo{ 9623 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9624 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9625 }, 9626 outputs: []outputInfo{ 9627 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9628 }, 9629 }, 9630 }, 9631 { 9632 name: "XORLload", 9633 auxType: auxSymOff, 9634 argLen: 3, 9635 resultInArg0: true, 9636 clobberFlags: true, 9637 faultOnNilArg1: true, 9638 symEffect: SymRead, 9639 asm: x86.AXORL, 9640 reg: regInfo{ 9641 inputs: []inputInfo{ 9642 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9643 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9644 }, 9645 outputs: []outputInfo{ 9646 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9647 }, 9648 }, 9649 }, 9650 { 9651 name: "ADDLloadidx1", 9652 auxType: auxSymOff, 9653 argLen: 4, 9654 resultInArg0: true, 9655 clobberFlags: true, 9656 symEffect: SymRead, 9657 asm: x86.AADDL, 9658 scale: 1, 9659 reg: regInfo{ 9660 inputs: []inputInfo{ 9661 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9662 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9663 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9664 }, 9665 outputs: []outputInfo{ 9666 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9667 }, 9668 }, 9669 }, 9670 { 9671 name: "ADDLloadidx4", 9672 auxType: auxSymOff, 9673 argLen: 4, 9674 resultInArg0: true, 9675 clobberFlags: true, 9676 symEffect: SymRead, 9677 asm: x86.AADDL, 9678 scale: 4, 9679 reg: regInfo{ 9680 inputs: []inputInfo{ 9681 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9682 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9683 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9684 }, 9685 outputs: []outputInfo{ 9686 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9687 }, 9688 }, 9689 }, 9690 { 9691 name: "ADDLloadidx8", 9692 auxType: auxSymOff, 9693 argLen: 4, 9694 resultInArg0: true, 9695 clobberFlags: true, 9696 symEffect: SymRead, 9697 asm: x86.AADDL, 9698 scale: 8, 9699 reg: regInfo{ 9700 inputs: []inputInfo{ 9701 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9702 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9703 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9704 }, 9705 outputs: []outputInfo{ 9706 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9707 }, 9708 }, 9709 }, 9710 { 9711 name: "ADDQloadidx1", 9712 auxType: auxSymOff, 9713 argLen: 4, 9714 resultInArg0: true, 9715 clobberFlags: true, 9716 symEffect: SymRead, 9717 asm: x86.AADDQ, 9718 scale: 1, 9719 reg: regInfo{ 9720 inputs: []inputInfo{ 9721 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9722 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9723 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9724 }, 9725 outputs: []outputInfo{ 9726 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9727 }, 9728 }, 9729 }, 9730 { 9731 name: "ADDQloadidx8", 9732 auxType: auxSymOff, 9733 argLen: 4, 9734 resultInArg0: true, 9735 clobberFlags: true, 9736 symEffect: SymRead, 9737 asm: x86.AADDQ, 9738 scale: 8, 9739 reg: regInfo{ 9740 inputs: []inputInfo{ 9741 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9742 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9743 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9744 }, 9745 outputs: []outputInfo{ 9746 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9747 }, 9748 }, 9749 }, 9750 { 9751 name: "SUBLloadidx1", 9752 auxType: auxSymOff, 9753 argLen: 4, 9754 resultInArg0: true, 9755 clobberFlags: true, 9756 symEffect: SymRead, 9757 asm: x86.ASUBL, 9758 scale: 1, 9759 reg: regInfo{ 9760 inputs: []inputInfo{ 9761 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9762 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9763 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9764 }, 9765 outputs: []outputInfo{ 9766 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9767 }, 9768 }, 9769 }, 9770 { 9771 name: "SUBLloadidx4", 9772 auxType: auxSymOff, 9773 argLen: 4, 9774 resultInArg0: true, 9775 clobberFlags: true, 9776 symEffect: SymRead, 9777 asm: x86.ASUBL, 9778 scale: 4, 9779 reg: regInfo{ 9780 inputs: []inputInfo{ 9781 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9782 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9783 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9784 }, 9785 outputs: []outputInfo{ 9786 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9787 }, 9788 }, 9789 }, 9790 { 9791 name: "SUBLloadidx8", 9792 auxType: auxSymOff, 9793 argLen: 4, 9794 resultInArg0: true, 9795 clobberFlags: true, 9796 symEffect: SymRead, 9797 asm: x86.ASUBL, 9798 scale: 8, 9799 reg: regInfo{ 9800 inputs: []inputInfo{ 9801 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9802 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9803 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9804 }, 9805 outputs: []outputInfo{ 9806 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9807 }, 9808 }, 9809 }, 9810 { 9811 name: "SUBQloadidx1", 9812 auxType: auxSymOff, 9813 argLen: 4, 9814 resultInArg0: true, 9815 clobberFlags: true, 9816 symEffect: SymRead, 9817 asm: x86.ASUBQ, 9818 scale: 1, 9819 reg: regInfo{ 9820 inputs: []inputInfo{ 9821 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9822 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9823 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9824 }, 9825 outputs: []outputInfo{ 9826 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9827 }, 9828 }, 9829 }, 9830 { 9831 name: "SUBQloadidx8", 9832 auxType: auxSymOff, 9833 argLen: 4, 9834 resultInArg0: true, 9835 clobberFlags: true, 9836 symEffect: SymRead, 9837 asm: x86.ASUBQ, 9838 scale: 8, 9839 reg: regInfo{ 9840 inputs: []inputInfo{ 9841 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9842 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9843 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9844 }, 9845 outputs: []outputInfo{ 9846 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9847 }, 9848 }, 9849 }, 9850 { 9851 name: "ANDLloadidx1", 9852 auxType: auxSymOff, 9853 argLen: 4, 9854 resultInArg0: true, 9855 clobberFlags: true, 9856 symEffect: SymRead, 9857 asm: x86.AANDL, 9858 scale: 1, 9859 reg: regInfo{ 9860 inputs: []inputInfo{ 9861 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9862 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9863 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9864 }, 9865 outputs: []outputInfo{ 9866 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9867 }, 9868 }, 9869 }, 9870 { 9871 name: "ANDLloadidx4", 9872 auxType: auxSymOff, 9873 argLen: 4, 9874 resultInArg0: true, 9875 clobberFlags: true, 9876 symEffect: SymRead, 9877 asm: x86.AANDL, 9878 scale: 4, 9879 reg: regInfo{ 9880 inputs: []inputInfo{ 9881 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9882 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9883 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9884 }, 9885 outputs: []outputInfo{ 9886 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9887 }, 9888 }, 9889 }, 9890 { 9891 name: "ANDLloadidx8", 9892 auxType: auxSymOff, 9893 argLen: 4, 9894 resultInArg0: true, 9895 clobberFlags: true, 9896 symEffect: SymRead, 9897 asm: x86.AANDL, 9898 scale: 8, 9899 reg: regInfo{ 9900 inputs: []inputInfo{ 9901 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9902 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9903 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9904 }, 9905 outputs: []outputInfo{ 9906 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9907 }, 9908 }, 9909 }, 9910 { 9911 name: "ANDQloadidx1", 9912 auxType: auxSymOff, 9913 argLen: 4, 9914 resultInArg0: true, 9915 clobberFlags: true, 9916 symEffect: SymRead, 9917 asm: x86.AANDQ, 9918 scale: 1, 9919 reg: regInfo{ 9920 inputs: []inputInfo{ 9921 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9922 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9923 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9924 }, 9925 outputs: []outputInfo{ 9926 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9927 }, 9928 }, 9929 }, 9930 { 9931 name: "ANDQloadidx8", 9932 auxType: auxSymOff, 9933 argLen: 4, 9934 resultInArg0: true, 9935 clobberFlags: true, 9936 symEffect: SymRead, 9937 asm: x86.AANDQ, 9938 scale: 8, 9939 reg: regInfo{ 9940 inputs: []inputInfo{ 9941 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9942 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9943 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9944 }, 9945 outputs: []outputInfo{ 9946 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9947 }, 9948 }, 9949 }, 9950 { 9951 name: "ORLloadidx1", 9952 auxType: auxSymOff, 9953 argLen: 4, 9954 resultInArg0: true, 9955 clobberFlags: true, 9956 symEffect: SymRead, 9957 asm: x86.AORL, 9958 scale: 1, 9959 reg: regInfo{ 9960 inputs: []inputInfo{ 9961 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9962 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9963 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9964 }, 9965 outputs: []outputInfo{ 9966 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9967 }, 9968 }, 9969 }, 9970 { 9971 name: "ORLloadidx4", 9972 auxType: auxSymOff, 9973 argLen: 4, 9974 resultInArg0: true, 9975 clobberFlags: true, 9976 symEffect: SymRead, 9977 asm: x86.AORL, 9978 scale: 4, 9979 reg: regInfo{ 9980 inputs: []inputInfo{ 9981 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9982 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 9983 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 9984 }, 9985 outputs: []outputInfo{ 9986 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 9987 }, 9988 }, 9989 }, 9990 { 9991 name: "ORLloadidx8", 9992 auxType: auxSymOff, 9993 argLen: 4, 9994 resultInArg0: true, 9995 clobberFlags: true, 9996 symEffect: SymRead, 9997 asm: x86.AORL, 9998 scale: 8, 9999 reg: regInfo{ 10000 inputs: []inputInfo{ 10001 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10002 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10003 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10004 }, 10005 outputs: []outputInfo{ 10006 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10007 }, 10008 }, 10009 }, 10010 { 10011 name: "ORQloadidx1", 10012 auxType: auxSymOff, 10013 argLen: 4, 10014 resultInArg0: true, 10015 clobberFlags: true, 10016 symEffect: SymRead, 10017 asm: x86.AORQ, 10018 scale: 1, 10019 reg: regInfo{ 10020 inputs: []inputInfo{ 10021 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10022 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10023 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10024 }, 10025 outputs: []outputInfo{ 10026 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10027 }, 10028 }, 10029 }, 10030 { 10031 name: "ORQloadidx8", 10032 auxType: auxSymOff, 10033 argLen: 4, 10034 resultInArg0: true, 10035 clobberFlags: true, 10036 symEffect: SymRead, 10037 asm: x86.AORQ, 10038 scale: 8, 10039 reg: regInfo{ 10040 inputs: []inputInfo{ 10041 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10042 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10043 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10044 }, 10045 outputs: []outputInfo{ 10046 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10047 }, 10048 }, 10049 }, 10050 { 10051 name: "XORLloadidx1", 10052 auxType: auxSymOff, 10053 argLen: 4, 10054 resultInArg0: true, 10055 clobberFlags: true, 10056 symEffect: SymRead, 10057 asm: x86.AXORL, 10058 scale: 1, 10059 reg: regInfo{ 10060 inputs: []inputInfo{ 10061 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10062 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10063 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10064 }, 10065 outputs: []outputInfo{ 10066 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10067 }, 10068 }, 10069 }, 10070 { 10071 name: "XORLloadidx4", 10072 auxType: auxSymOff, 10073 argLen: 4, 10074 resultInArg0: true, 10075 clobberFlags: true, 10076 symEffect: SymRead, 10077 asm: x86.AXORL, 10078 scale: 4, 10079 reg: regInfo{ 10080 inputs: []inputInfo{ 10081 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10082 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10083 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10084 }, 10085 outputs: []outputInfo{ 10086 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10087 }, 10088 }, 10089 }, 10090 { 10091 name: "XORLloadidx8", 10092 auxType: auxSymOff, 10093 argLen: 4, 10094 resultInArg0: true, 10095 clobberFlags: true, 10096 symEffect: SymRead, 10097 asm: x86.AXORL, 10098 scale: 8, 10099 reg: regInfo{ 10100 inputs: []inputInfo{ 10101 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10102 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10103 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10104 }, 10105 outputs: []outputInfo{ 10106 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10107 }, 10108 }, 10109 }, 10110 { 10111 name: "XORQloadidx1", 10112 auxType: auxSymOff, 10113 argLen: 4, 10114 resultInArg0: true, 10115 clobberFlags: true, 10116 symEffect: SymRead, 10117 asm: x86.AXORQ, 10118 scale: 1, 10119 reg: regInfo{ 10120 inputs: []inputInfo{ 10121 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10122 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10123 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10124 }, 10125 outputs: []outputInfo{ 10126 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10127 }, 10128 }, 10129 }, 10130 { 10131 name: "XORQloadidx8", 10132 auxType: auxSymOff, 10133 argLen: 4, 10134 resultInArg0: true, 10135 clobberFlags: true, 10136 symEffect: SymRead, 10137 asm: x86.AXORQ, 10138 scale: 8, 10139 reg: regInfo{ 10140 inputs: []inputInfo{ 10141 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10142 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10143 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10144 }, 10145 outputs: []outputInfo{ 10146 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 10147 }, 10148 }, 10149 }, 10150 { 10151 name: "ADDQmodify", 10152 auxType: auxSymOff, 10153 argLen: 3, 10154 clobberFlags: true, 10155 faultOnNilArg0: true, 10156 symEffect: SymRead | SymWrite, 10157 asm: x86.AADDQ, 10158 reg: regInfo{ 10159 inputs: []inputInfo{ 10160 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10161 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10162 }, 10163 }, 10164 }, 10165 { 10166 name: "SUBQmodify", 10167 auxType: auxSymOff, 10168 argLen: 3, 10169 clobberFlags: true, 10170 faultOnNilArg0: true, 10171 symEffect: SymRead | SymWrite, 10172 asm: x86.ASUBQ, 10173 reg: regInfo{ 10174 inputs: []inputInfo{ 10175 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10176 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10177 }, 10178 }, 10179 }, 10180 { 10181 name: "ANDQmodify", 10182 auxType: auxSymOff, 10183 argLen: 3, 10184 clobberFlags: true, 10185 faultOnNilArg0: true, 10186 symEffect: SymRead | SymWrite, 10187 asm: x86.AANDQ, 10188 reg: regInfo{ 10189 inputs: []inputInfo{ 10190 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10191 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10192 }, 10193 }, 10194 }, 10195 { 10196 name: "ORQmodify", 10197 auxType: auxSymOff, 10198 argLen: 3, 10199 clobberFlags: true, 10200 faultOnNilArg0: true, 10201 symEffect: SymRead | SymWrite, 10202 asm: x86.AORQ, 10203 reg: regInfo{ 10204 inputs: []inputInfo{ 10205 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10206 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10207 }, 10208 }, 10209 }, 10210 { 10211 name: "XORQmodify", 10212 auxType: auxSymOff, 10213 argLen: 3, 10214 clobberFlags: true, 10215 faultOnNilArg0: true, 10216 symEffect: SymRead | SymWrite, 10217 asm: x86.AXORQ, 10218 reg: regInfo{ 10219 inputs: []inputInfo{ 10220 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10221 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10222 }, 10223 }, 10224 }, 10225 { 10226 name: "ADDLmodify", 10227 auxType: auxSymOff, 10228 argLen: 3, 10229 clobberFlags: true, 10230 faultOnNilArg0: true, 10231 symEffect: SymRead | SymWrite, 10232 asm: x86.AADDL, 10233 reg: regInfo{ 10234 inputs: []inputInfo{ 10235 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10236 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10237 }, 10238 }, 10239 }, 10240 { 10241 name: "SUBLmodify", 10242 auxType: auxSymOff, 10243 argLen: 3, 10244 clobberFlags: true, 10245 faultOnNilArg0: true, 10246 symEffect: SymRead | SymWrite, 10247 asm: x86.ASUBL, 10248 reg: regInfo{ 10249 inputs: []inputInfo{ 10250 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10251 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10252 }, 10253 }, 10254 }, 10255 { 10256 name: "ANDLmodify", 10257 auxType: auxSymOff, 10258 argLen: 3, 10259 clobberFlags: true, 10260 faultOnNilArg0: true, 10261 symEffect: SymRead | SymWrite, 10262 asm: x86.AANDL, 10263 reg: regInfo{ 10264 inputs: []inputInfo{ 10265 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10266 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10267 }, 10268 }, 10269 }, 10270 { 10271 name: "ORLmodify", 10272 auxType: auxSymOff, 10273 argLen: 3, 10274 clobberFlags: true, 10275 faultOnNilArg0: true, 10276 symEffect: SymRead | SymWrite, 10277 asm: x86.AORL, 10278 reg: regInfo{ 10279 inputs: []inputInfo{ 10280 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10281 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10282 }, 10283 }, 10284 }, 10285 { 10286 name: "XORLmodify", 10287 auxType: auxSymOff, 10288 argLen: 3, 10289 clobberFlags: true, 10290 faultOnNilArg0: true, 10291 symEffect: SymRead | SymWrite, 10292 asm: x86.AXORL, 10293 reg: regInfo{ 10294 inputs: []inputInfo{ 10295 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10296 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10297 }, 10298 }, 10299 }, 10300 { 10301 name: "ADDQmodifyidx1", 10302 auxType: auxSymOff, 10303 argLen: 4, 10304 clobberFlags: true, 10305 symEffect: SymRead | SymWrite, 10306 asm: x86.AADDQ, 10307 scale: 1, 10308 reg: regInfo{ 10309 inputs: []inputInfo{ 10310 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10311 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10312 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10313 }, 10314 }, 10315 }, 10316 { 10317 name: "ADDQmodifyidx8", 10318 auxType: auxSymOff, 10319 argLen: 4, 10320 clobberFlags: true, 10321 symEffect: SymRead | SymWrite, 10322 asm: x86.AADDQ, 10323 scale: 8, 10324 reg: regInfo{ 10325 inputs: []inputInfo{ 10326 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10327 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10328 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10329 }, 10330 }, 10331 }, 10332 { 10333 name: "SUBQmodifyidx1", 10334 auxType: auxSymOff, 10335 argLen: 4, 10336 clobberFlags: true, 10337 symEffect: SymRead | SymWrite, 10338 asm: x86.ASUBQ, 10339 scale: 1, 10340 reg: regInfo{ 10341 inputs: []inputInfo{ 10342 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10343 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10344 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10345 }, 10346 }, 10347 }, 10348 { 10349 name: "SUBQmodifyidx8", 10350 auxType: auxSymOff, 10351 argLen: 4, 10352 clobberFlags: true, 10353 symEffect: SymRead | SymWrite, 10354 asm: x86.ASUBQ, 10355 scale: 8, 10356 reg: regInfo{ 10357 inputs: []inputInfo{ 10358 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10359 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10360 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10361 }, 10362 }, 10363 }, 10364 { 10365 name: "ANDQmodifyidx1", 10366 auxType: auxSymOff, 10367 argLen: 4, 10368 clobberFlags: true, 10369 symEffect: SymRead | SymWrite, 10370 asm: x86.AANDQ, 10371 scale: 1, 10372 reg: regInfo{ 10373 inputs: []inputInfo{ 10374 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10375 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10376 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10377 }, 10378 }, 10379 }, 10380 { 10381 name: "ANDQmodifyidx8", 10382 auxType: auxSymOff, 10383 argLen: 4, 10384 clobberFlags: true, 10385 symEffect: SymRead | SymWrite, 10386 asm: x86.AANDQ, 10387 scale: 8, 10388 reg: regInfo{ 10389 inputs: []inputInfo{ 10390 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10391 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10392 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10393 }, 10394 }, 10395 }, 10396 { 10397 name: "ORQmodifyidx1", 10398 auxType: auxSymOff, 10399 argLen: 4, 10400 clobberFlags: true, 10401 symEffect: SymRead | SymWrite, 10402 asm: x86.AORQ, 10403 scale: 1, 10404 reg: regInfo{ 10405 inputs: []inputInfo{ 10406 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10407 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10408 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10409 }, 10410 }, 10411 }, 10412 { 10413 name: "ORQmodifyidx8", 10414 auxType: auxSymOff, 10415 argLen: 4, 10416 clobberFlags: true, 10417 symEffect: SymRead | SymWrite, 10418 asm: x86.AORQ, 10419 scale: 8, 10420 reg: regInfo{ 10421 inputs: []inputInfo{ 10422 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10423 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10424 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10425 }, 10426 }, 10427 }, 10428 { 10429 name: "XORQmodifyidx1", 10430 auxType: auxSymOff, 10431 argLen: 4, 10432 clobberFlags: true, 10433 symEffect: SymRead | SymWrite, 10434 asm: x86.AXORQ, 10435 scale: 1, 10436 reg: regInfo{ 10437 inputs: []inputInfo{ 10438 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10439 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10440 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10441 }, 10442 }, 10443 }, 10444 { 10445 name: "XORQmodifyidx8", 10446 auxType: auxSymOff, 10447 argLen: 4, 10448 clobberFlags: true, 10449 symEffect: SymRead | SymWrite, 10450 asm: x86.AXORQ, 10451 scale: 8, 10452 reg: regInfo{ 10453 inputs: []inputInfo{ 10454 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10455 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10456 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10457 }, 10458 }, 10459 }, 10460 { 10461 name: "ADDLmodifyidx1", 10462 auxType: auxSymOff, 10463 argLen: 4, 10464 clobberFlags: true, 10465 symEffect: SymRead | SymWrite, 10466 asm: x86.AADDL, 10467 scale: 1, 10468 reg: regInfo{ 10469 inputs: []inputInfo{ 10470 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10471 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10472 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10473 }, 10474 }, 10475 }, 10476 { 10477 name: "ADDLmodifyidx4", 10478 auxType: auxSymOff, 10479 argLen: 4, 10480 clobberFlags: true, 10481 symEffect: SymRead | SymWrite, 10482 asm: x86.AADDL, 10483 scale: 4, 10484 reg: regInfo{ 10485 inputs: []inputInfo{ 10486 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10487 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10488 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10489 }, 10490 }, 10491 }, 10492 { 10493 name: "ADDLmodifyidx8", 10494 auxType: auxSymOff, 10495 argLen: 4, 10496 clobberFlags: true, 10497 symEffect: SymRead | SymWrite, 10498 asm: x86.AADDL, 10499 scale: 8, 10500 reg: regInfo{ 10501 inputs: []inputInfo{ 10502 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10503 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10504 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10505 }, 10506 }, 10507 }, 10508 { 10509 name: "SUBLmodifyidx1", 10510 auxType: auxSymOff, 10511 argLen: 4, 10512 clobberFlags: true, 10513 symEffect: SymRead | SymWrite, 10514 asm: x86.ASUBL, 10515 scale: 1, 10516 reg: regInfo{ 10517 inputs: []inputInfo{ 10518 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10519 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10520 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10521 }, 10522 }, 10523 }, 10524 { 10525 name: "SUBLmodifyidx4", 10526 auxType: auxSymOff, 10527 argLen: 4, 10528 clobberFlags: true, 10529 symEffect: SymRead | SymWrite, 10530 asm: x86.ASUBL, 10531 scale: 4, 10532 reg: regInfo{ 10533 inputs: []inputInfo{ 10534 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10535 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10536 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10537 }, 10538 }, 10539 }, 10540 { 10541 name: "SUBLmodifyidx8", 10542 auxType: auxSymOff, 10543 argLen: 4, 10544 clobberFlags: true, 10545 symEffect: SymRead | SymWrite, 10546 asm: x86.ASUBL, 10547 scale: 8, 10548 reg: regInfo{ 10549 inputs: []inputInfo{ 10550 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10551 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10552 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10553 }, 10554 }, 10555 }, 10556 { 10557 name: "ANDLmodifyidx1", 10558 auxType: auxSymOff, 10559 argLen: 4, 10560 clobberFlags: true, 10561 symEffect: SymRead | SymWrite, 10562 asm: x86.AANDL, 10563 scale: 1, 10564 reg: regInfo{ 10565 inputs: []inputInfo{ 10566 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10567 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10568 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10569 }, 10570 }, 10571 }, 10572 { 10573 name: "ANDLmodifyidx4", 10574 auxType: auxSymOff, 10575 argLen: 4, 10576 clobberFlags: true, 10577 symEffect: SymRead | SymWrite, 10578 asm: x86.AANDL, 10579 scale: 4, 10580 reg: regInfo{ 10581 inputs: []inputInfo{ 10582 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10583 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10584 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10585 }, 10586 }, 10587 }, 10588 { 10589 name: "ANDLmodifyidx8", 10590 auxType: auxSymOff, 10591 argLen: 4, 10592 clobberFlags: true, 10593 symEffect: SymRead | SymWrite, 10594 asm: x86.AANDL, 10595 scale: 8, 10596 reg: regInfo{ 10597 inputs: []inputInfo{ 10598 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10599 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10600 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10601 }, 10602 }, 10603 }, 10604 { 10605 name: "ORLmodifyidx1", 10606 auxType: auxSymOff, 10607 argLen: 4, 10608 clobberFlags: true, 10609 symEffect: SymRead | SymWrite, 10610 asm: x86.AORL, 10611 scale: 1, 10612 reg: regInfo{ 10613 inputs: []inputInfo{ 10614 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10615 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10616 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10617 }, 10618 }, 10619 }, 10620 { 10621 name: "ORLmodifyidx4", 10622 auxType: auxSymOff, 10623 argLen: 4, 10624 clobberFlags: true, 10625 symEffect: SymRead | SymWrite, 10626 asm: x86.AORL, 10627 scale: 4, 10628 reg: regInfo{ 10629 inputs: []inputInfo{ 10630 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10631 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10632 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10633 }, 10634 }, 10635 }, 10636 { 10637 name: "ORLmodifyidx8", 10638 auxType: auxSymOff, 10639 argLen: 4, 10640 clobberFlags: true, 10641 symEffect: SymRead | SymWrite, 10642 asm: x86.AORL, 10643 scale: 8, 10644 reg: regInfo{ 10645 inputs: []inputInfo{ 10646 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10647 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10648 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10649 }, 10650 }, 10651 }, 10652 { 10653 name: "XORLmodifyidx1", 10654 auxType: auxSymOff, 10655 argLen: 4, 10656 clobberFlags: true, 10657 symEffect: SymRead | SymWrite, 10658 asm: x86.AXORL, 10659 scale: 1, 10660 reg: regInfo{ 10661 inputs: []inputInfo{ 10662 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10663 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10664 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10665 }, 10666 }, 10667 }, 10668 { 10669 name: "XORLmodifyidx4", 10670 auxType: auxSymOff, 10671 argLen: 4, 10672 clobberFlags: true, 10673 symEffect: SymRead | SymWrite, 10674 asm: x86.AXORL, 10675 scale: 4, 10676 reg: regInfo{ 10677 inputs: []inputInfo{ 10678 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10679 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10680 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10681 }, 10682 }, 10683 }, 10684 { 10685 name: "XORLmodifyidx8", 10686 auxType: auxSymOff, 10687 argLen: 4, 10688 clobberFlags: true, 10689 symEffect: SymRead | SymWrite, 10690 asm: x86.AXORL, 10691 scale: 8, 10692 reg: regInfo{ 10693 inputs: []inputInfo{ 10694 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10695 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10696 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10697 }, 10698 }, 10699 }, 10700 { 10701 name: "ADDQconstmodifyidx1", 10702 auxType: auxSymValAndOff, 10703 argLen: 3, 10704 clobberFlags: true, 10705 symEffect: SymRead | SymWrite, 10706 asm: x86.AADDQ, 10707 scale: 1, 10708 reg: regInfo{ 10709 inputs: []inputInfo{ 10710 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10711 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10712 }, 10713 }, 10714 }, 10715 { 10716 name: "ADDQconstmodifyidx8", 10717 auxType: auxSymValAndOff, 10718 argLen: 3, 10719 clobberFlags: true, 10720 symEffect: SymRead | SymWrite, 10721 asm: x86.AADDQ, 10722 scale: 8, 10723 reg: regInfo{ 10724 inputs: []inputInfo{ 10725 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10726 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10727 }, 10728 }, 10729 }, 10730 { 10731 name: "ANDQconstmodifyidx1", 10732 auxType: auxSymValAndOff, 10733 argLen: 3, 10734 clobberFlags: true, 10735 symEffect: SymRead | SymWrite, 10736 asm: x86.AANDQ, 10737 scale: 1, 10738 reg: regInfo{ 10739 inputs: []inputInfo{ 10740 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10741 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10742 }, 10743 }, 10744 }, 10745 { 10746 name: "ANDQconstmodifyidx8", 10747 auxType: auxSymValAndOff, 10748 argLen: 3, 10749 clobberFlags: true, 10750 symEffect: SymRead | SymWrite, 10751 asm: x86.AANDQ, 10752 scale: 8, 10753 reg: regInfo{ 10754 inputs: []inputInfo{ 10755 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10756 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10757 }, 10758 }, 10759 }, 10760 { 10761 name: "ORQconstmodifyidx1", 10762 auxType: auxSymValAndOff, 10763 argLen: 3, 10764 clobberFlags: true, 10765 symEffect: SymRead | SymWrite, 10766 asm: x86.AORQ, 10767 scale: 1, 10768 reg: regInfo{ 10769 inputs: []inputInfo{ 10770 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10771 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10772 }, 10773 }, 10774 }, 10775 { 10776 name: "ORQconstmodifyidx8", 10777 auxType: auxSymValAndOff, 10778 argLen: 3, 10779 clobberFlags: true, 10780 symEffect: SymRead | SymWrite, 10781 asm: x86.AORQ, 10782 scale: 8, 10783 reg: regInfo{ 10784 inputs: []inputInfo{ 10785 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10786 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10787 }, 10788 }, 10789 }, 10790 { 10791 name: "XORQconstmodifyidx1", 10792 auxType: auxSymValAndOff, 10793 argLen: 3, 10794 clobberFlags: true, 10795 symEffect: SymRead | SymWrite, 10796 asm: x86.AXORQ, 10797 scale: 1, 10798 reg: regInfo{ 10799 inputs: []inputInfo{ 10800 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10801 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10802 }, 10803 }, 10804 }, 10805 { 10806 name: "XORQconstmodifyidx8", 10807 auxType: auxSymValAndOff, 10808 argLen: 3, 10809 clobberFlags: true, 10810 symEffect: SymRead | SymWrite, 10811 asm: x86.AXORQ, 10812 scale: 8, 10813 reg: regInfo{ 10814 inputs: []inputInfo{ 10815 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10816 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10817 }, 10818 }, 10819 }, 10820 { 10821 name: "ADDLconstmodifyidx1", 10822 auxType: auxSymValAndOff, 10823 argLen: 3, 10824 clobberFlags: true, 10825 symEffect: SymRead | SymWrite, 10826 asm: x86.AADDL, 10827 scale: 1, 10828 reg: regInfo{ 10829 inputs: []inputInfo{ 10830 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10831 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10832 }, 10833 }, 10834 }, 10835 { 10836 name: "ADDLconstmodifyidx4", 10837 auxType: auxSymValAndOff, 10838 argLen: 3, 10839 clobberFlags: true, 10840 symEffect: SymRead | SymWrite, 10841 asm: x86.AADDL, 10842 scale: 4, 10843 reg: regInfo{ 10844 inputs: []inputInfo{ 10845 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10846 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10847 }, 10848 }, 10849 }, 10850 { 10851 name: "ADDLconstmodifyidx8", 10852 auxType: auxSymValAndOff, 10853 argLen: 3, 10854 clobberFlags: true, 10855 symEffect: SymRead | SymWrite, 10856 asm: x86.AADDL, 10857 scale: 8, 10858 reg: regInfo{ 10859 inputs: []inputInfo{ 10860 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10861 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10862 }, 10863 }, 10864 }, 10865 { 10866 name: "ANDLconstmodifyidx1", 10867 auxType: auxSymValAndOff, 10868 argLen: 3, 10869 clobberFlags: true, 10870 symEffect: SymRead | SymWrite, 10871 asm: x86.AANDL, 10872 scale: 1, 10873 reg: regInfo{ 10874 inputs: []inputInfo{ 10875 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10876 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10877 }, 10878 }, 10879 }, 10880 { 10881 name: "ANDLconstmodifyidx4", 10882 auxType: auxSymValAndOff, 10883 argLen: 3, 10884 clobberFlags: true, 10885 symEffect: SymRead | SymWrite, 10886 asm: x86.AANDL, 10887 scale: 4, 10888 reg: regInfo{ 10889 inputs: []inputInfo{ 10890 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10891 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10892 }, 10893 }, 10894 }, 10895 { 10896 name: "ANDLconstmodifyidx8", 10897 auxType: auxSymValAndOff, 10898 argLen: 3, 10899 clobberFlags: true, 10900 symEffect: SymRead | SymWrite, 10901 asm: x86.AANDL, 10902 scale: 8, 10903 reg: regInfo{ 10904 inputs: []inputInfo{ 10905 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10906 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10907 }, 10908 }, 10909 }, 10910 { 10911 name: "ORLconstmodifyidx1", 10912 auxType: auxSymValAndOff, 10913 argLen: 3, 10914 clobberFlags: true, 10915 symEffect: SymRead | SymWrite, 10916 asm: x86.AORL, 10917 scale: 1, 10918 reg: regInfo{ 10919 inputs: []inputInfo{ 10920 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10921 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10922 }, 10923 }, 10924 }, 10925 { 10926 name: "ORLconstmodifyidx4", 10927 auxType: auxSymValAndOff, 10928 argLen: 3, 10929 clobberFlags: true, 10930 symEffect: SymRead | SymWrite, 10931 asm: x86.AORL, 10932 scale: 4, 10933 reg: regInfo{ 10934 inputs: []inputInfo{ 10935 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10936 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10937 }, 10938 }, 10939 }, 10940 { 10941 name: "ORLconstmodifyidx8", 10942 auxType: auxSymValAndOff, 10943 argLen: 3, 10944 clobberFlags: true, 10945 symEffect: SymRead | SymWrite, 10946 asm: x86.AORL, 10947 scale: 8, 10948 reg: regInfo{ 10949 inputs: []inputInfo{ 10950 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10951 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10952 }, 10953 }, 10954 }, 10955 { 10956 name: "XORLconstmodifyidx1", 10957 auxType: auxSymValAndOff, 10958 argLen: 3, 10959 clobberFlags: true, 10960 symEffect: SymRead | SymWrite, 10961 asm: x86.AXORL, 10962 scale: 1, 10963 reg: regInfo{ 10964 inputs: []inputInfo{ 10965 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10966 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10967 }, 10968 }, 10969 }, 10970 { 10971 name: "XORLconstmodifyidx4", 10972 auxType: auxSymValAndOff, 10973 argLen: 3, 10974 clobberFlags: true, 10975 symEffect: SymRead | SymWrite, 10976 asm: x86.AXORL, 10977 scale: 4, 10978 reg: regInfo{ 10979 inputs: []inputInfo{ 10980 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10981 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10982 }, 10983 }, 10984 }, 10985 { 10986 name: "XORLconstmodifyidx8", 10987 auxType: auxSymValAndOff, 10988 argLen: 3, 10989 clobberFlags: true, 10990 symEffect: SymRead | SymWrite, 10991 asm: x86.AXORL, 10992 scale: 8, 10993 reg: regInfo{ 10994 inputs: []inputInfo{ 10995 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 10996 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 10997 }, 10998 }, 10999 }, 11000 { 11001 name: "NEGQ", 11002 argLen: 1, 11003 resultInArg0: true, 11004 clobberFlags: true, 11005 asm: x86.ANEGQ, 11006 reg: regInfo{ 11007 inputs: []inputInfo{ 11008 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11009 }, 11010 outputs: []outputInfo{ 11011 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11012 }, 11013 }, 11014 }, 11015 { 11016 name: "NEGL", 11017 argLen: 1, 11018 resultInArg0: true, 11019 clobberFlags: true, 11020 asm: x86.ANEGL, 11021 reg: regInfo{ 11022 inputs: []inputInfo{ 11023 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11024 }, 11025 outputs: []outputInfo{ 11026 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11027 }, 11028 }, 11029 }, 11030 { 11031 name: "NOTQ", 11032 argLen: 1, 11033 resultInArg0: true, 11034 asm: x86.ANOTQ, 11035 reg: regInfo{ 11036 inputs: []inputInfo{ 11037 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11038 }, 11039 outputs: []outputInfo{ 11040 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11041 }, 11042 }, 11043 }, 11044 { 11045 name: "NOTL", 11046 argLen: 1, 11047 resultInArg0: true, 11048 asm: x86.ANOTL, 11049 reg: regInfo{ 11050 inputs: []inputInfo{ 11051 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11052 }, 11053 outputs: []outputInfo{ 11054 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11055 }, 11056 }, 11057 }, 11058 { 11059 name: "BSFQ", 11060 argLen: 1, 11061 asm: x86.ABSFQ, 11062 reg: regInfo{ 11063 inputs: []inputInfo{ 11064 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11065 }, 11066 outputs: []outputInfo{ 11067 {1, 0}, 11068 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11069 }, 11070 }, 11071 }, 11072 { 11073 name: "BSFL", 11074 argLen: 1, 11075 clobberFlags: true, 11076 asm: x86.ABSFL, 11077 reg: regInfo{ 11078 inputs: []inputInfo{ 11079 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11080 }, 11081 outputs: []outputInfo{ 11082 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11083 }, 11084 }, 11085 }, 11086 { 11087 name: "BSRQ", 11088 argLen: 1, 11089 asm: x86.ABSRQ, 11090 reg: regInfo{ 11091 inputs: []inputInfo{ 11092 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11093 }, 11094 outputs: []outputInfo{ 11095 {1, 0}, 11096 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11097 }, 11098 }, 11099 }, 11100 { 11101 name: "BSRL", 11102 argLen: 1, 11103 clobberFlags: true, 11104 asm: x86.ABSRL, 11105 reg: regInfo{ 11106 inputs: []inputInfo{ 11107 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11108 }, 11109 outputs: []outputInfo{ 11110 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11111 }, 11112 }, 11113 }, 11114 { 11115 name: "CMOVQEQ", 11116 argLen: 3, 11117 resultInArg0: true, 11118 asm: x86.ACMOVQEQ, 11119 reg: regInfo{ 11120 inputs: []inputInfo{ 11121 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11122 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11123 }, 11124 outputs: []outputInfo{ 11125 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11126 }, 11127 }, 11128 }, 11129 { 11130 name: "CMOVQNE", 11131 argLen: 3, 11132 resultInArg0: true, 11133 asm: x86.ACMOVQNE, 11134 reg: regInfo{ 11135 inputs: []inputInfo{ 11136 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11137 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11138 }, 11139 outputs: []outputInfo{ 11140 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11141 }, 11142 }, 11143 }, 11144 { 11145 name: "CMOVQLT", 11146 argLen: 3, 11147 resultInArg0: true, 11148 asm: x86.ACMOVQLT, 11149 reg: regInfo{ 11150 inputs: []inputInfo{ 11151 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11152 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11153 }, 11154 outputs: []outputInfo{ 11155 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11156 }, 11157 }, 11158 }, 11159 { 11160 name: "CMOVQGT", 11161 argLen: 3, 11162 resultInArg0: true, 11163 asm: x86.ACMOVQGT, 11164 reg: regInfo{ 11165 inputs: []inputInfo{ 11166 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11167 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11168 }, 11169 outputs: []outputInfo{ 11170 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11171 }, 11172 }, 11173 }, 11174 { 11175 name: "CMOVQLE", 11176 argLen: 3, 11177 resultInArg0: true, 11178 asm: x86.ACMOVQLE, 11179 reg: regInfo{ 11180 inputs: []inputInfo{ 11181 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11182 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11183 }, 11184 outputs: []outputInfo{ 11185 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11186 }, 11187 }, 11188 }, 11189 { 11190 name: "CMOVQGE", 11191 argLen: 3, 11192 resultInArg0: true, 11193 asm: x86.ACMOVQGE, 11194 reg: regInfo{ 11195 inputs: []inputInfo{ 11196 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11197 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11198 }, 11199 outputs: []outputInfo{ 11200 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11201 }, 11202 }, 11203 }, 11204 { 11205 name: "CMOVQLS", 11206 argLen: 3, 11207 resultInArg0: true, 11208 asm: x86.ACMOVQLS, 11209 reg: regInfo{ 11210 inputs: []inputInfo{ 11211 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11212 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11213 }, 11214 outputs: []outputInfo{ 11215 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11216 }, 11217 }, 11218 }, 11219 { 11220 name: "CMOVQHI", 11221 argLen: 3, 11222 resultInArg0: true, 11223 asm: x86.ACMOVQHI, 11224 reg: regInfo{ 11225 inputs: []inputInfo{ 11226 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11227 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11228 }, 11229 outputs: []outputInfo{ 11230 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11231 }, 11232 }, 11233 }, 11234 { 11235 name: "CMOVQCC", 11236 argLen: 3, 11237 resultInArg0: true, 11238 asm: x86.ACMOVQCC, 11239 reg: regInfo{ 11240 inputs: []inputInfo{ 11241 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11242 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11243 }, 11244 outputs: []outputInfo{ 11245 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11246 }, 11247 }, 11248 }, 11249 { 11250 name: "CMOVQCS", 11251 argLen: 3, 11252 resultInArg0: true, 11253 asm: x86.ACMOVQCS, 11254 reg: regInfo{ 11255 inputs: []inputInfo{ 11256 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11257 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11258 }, 11259 outputs: []outputInfo{ 11260 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11261 }, 11262 }, 11263 }, 11264 { 11265 name: "CMOVLEQ", 11266 argLen: 3, 11267 resultInArg0: true, 11268 asm: x86.ACMOVLEQ, 11269 reg: regInfo{ 11270 inputs: []inputInfo{ 11271 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11272 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11273 }, 11274 outputs: []outputInfo{ 11275 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11276 }, 11277 }, 11278 }, 11279 { 11280 name: "CMOVLNE", 11281 argLen: 3, 11282 resultInArg0: true, 11283 asm: x86.ACMOVLNE, 11284 reg: regInfo{ 11285 inputs: []inputInfo{ 11286 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11287 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11288 }, 11289 outputs: []outputInfo{ 11290 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11291 }, 11292 }, 11293 }, 11294 { 11295 name: "CMOVLLT", 11296 argLen: 3, 11297 resultInArg0: true, 11298 asm: x86.ACMOVLLT, 11299 reg: regInfo{ 11300 inputs: []inputInfo{ 11301 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11302 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11303 }, 11304 outputs: []outputInfo{ 11305 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11306 }, 11307 }, 11308 }, 11309 { 11310 name: "CMOVLGT", 11311 argLen: 3, 11312 resultInArg0: true, 11313 asm: x86.ACMOVLGT, 11314 reg: regInfo{ 11315 inputs: []inputInfo{ 11316 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11317 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11318 }, 11319 outputs: []outputInfo{ 11320 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11321 }, 11322 }, 11323 }, 11324 { 11325 name: "CMOVLLE", 11326 argLen: 3, 11327 resultInArg0: true, 11328 asm: x86.ACMOVLLE, 11329 reg: regInfo{ 11330 inputs: []inputInfo{ 11331 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11332 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11333 }, 11334 outputs: []outputInfo{ 11335 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11336 }, 11337 }, 11338 }, 11339 { 11340 name: "CMOVLGE", 11341 argLen: 3, 11342 resultInArg0: true, 11343 asm: x86.ACMOVLGE, 11344 reg: regInfo{ 11345 inputs: []inputInfo{ 11346 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11347 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11348 }, 11349 outputs: []outputInfo{ 11350 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11351 }, 11352 }, 11353 }, 11354 { 11355 name: "CMOVLLS", 11356 argLen: 3, 11357 resultInArg0: true, 11358 asm: x86.ACMOVLLS, 11359 reg: regInfo{ 11360 inputs: []inputInfo{ 11361 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11362 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11363 }, 11364 outputs: []outputInfo{ 11365 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11366 }, 11367 }, 11368 }, 11369 { 11370 name: "CMOVLHI", 11371 argLen: 3, 11372 resultInArg0: true, 11373 asm: x86.ACMOVLHI, 11374 reg: regInfo{ 11375 inputs: []inputInfo{ 11376 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11377 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11378 }, 11379 outputs: []outputInfo{ 11380 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11381 }, 11382 }, 11383 }, 11384 { 11385 name: "CMOVLCC", 11386 argLen: 3, 11387 resultInArg0: true, 11388 asm: x86.ACMOVLCC, 11389 reg: regInfo{ 11390 inputs: []inputInfo{ 11391 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11392 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11393 }, 11394 outputs: []outputInfo{ 11395 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11396 }, 11397 }, 11398 }, 11399 { 11400 name: "CMOVLCS", 11401 argLen: 3, 11402 resultInArg0: true, 11403 asm: x86.ACMOVLCS, 11404 reg: regInfo{ 11405 inputs: []inputInfo{ 11406 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11407 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11408 }, 11409 outputs: []outputInfo{ 11410 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11411 }, 11412 }, 11413 }, 11414 { 11415 name: "CMOVWEQ", 11416 argLen: 3, 11417 resultInArg0: true, 11418 asm: x86.ACMOVWEQ, 11419 reg: regInfo{ 11420 inputs: []inputInfo{ 11421 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11422 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11423 }, 11424 outputs: []outputInfo{ 11425 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11426 }, 11427 }, 11428 }, 11429 { 11430 name: "CMOVWNE", 11431 argLen: 3, 11432 resultInArg0: true, 11433 asm: x86.ACMOVWNE, 11434 reg: regInfo{ 11435 inputs: []inputInfo{ 11436 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11437 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11438 }, 11439 outputs: []outputInfo{ 11440 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11441 }, 11442 }, 11443 }, 11444 { 11445 name: "CMOVWLT", 11446 argLen: 3, 11447 resultInArg0: true, 11448 asm: x86.ACMOVWLT, 11449 reg: regInfo{ 11450 inputs: []inputInfo{ 11451 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11452 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11453 }, 11454 outputs: []outputInfo{ 11455 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11456 }, 11457 }, 11458 }, 11459 { 11460 name: "CMOVWGT", 11461 argLen: 3, 11462 resultInArg0: true, 11463 asm: x86.ACMOVWGT, 11464 reg: regInfo{ 11465 inputs: []inputInfo{ 11466 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11467 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11468 }, 11469 outputs: []outputInfo{ 11470 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11471 }, 11472 }, 11473 }, 11474 { 11475 name: "CMOVWLE", 11476 argLen: 3, 11477 resultInArg0: true, 11478 asm: x86.ACMOVWLE, 11479 reg: regInfo{ 11480 inputs: []inputInfo{ 11481 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11482 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11483 }, 11484 outputs: []outputInfo{ 11485 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11486 }, 11487 }, 11488 }, 11489 { 11490 name: "CMOVWGE", 11491 argLen: 3, 11492 resultInArg0: true, 11493 asm: x86.ACMOVWGE, 11494 reg: regInfo{ 11495 inputs: []inputInfo{ 11496 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11497 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11498 }, 11499 outputs: []outputInfo{ 11500 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11501 }, 11502 }, 11503 }, 11504 { 11505 name: "CMOVWLS", 11506 argLen: 3, 11507 resultInArg0: true, 11508 asm: x86.ACMOVWLS, 11509 reg: regInfo{ 11510 inputs: []inputInfo{ 11511 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11512 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11513 }, 11514 outputs: []outputInfo{ 11515 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11516 }, 11517 }, 11518 }, 11519 { 11520 name: "CMOVWHI", 11521 argLen: 3, 11522 resultInArg0: true, 11523 asm: x86.ACMOVWHI, 11524 reg: regInfo{ 11525 inputs: []inputInfo{ 11526 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11527 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11528 }, 11529 outputs: []outputInfo{ 11530 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11531 }, 11532 }, 11533 }, 11534 { 11535 name: "CMOVWCC", 11536 argLen: 3, 11537 resultInArg0: true, 11538 asm: x86.ACMOVWCC, 11539 reg: regInfo{ 11540 inputs: []inputInfo{ 11541 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11542 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11543 }, 11544 outputs: []outputInfo{ 11545 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11546 }, 11547 }, 11548 }, 11549 { 11550 name: "CMOVWCS", 11551 argLen: 3, 11552 resultInArg0: true, 11553 asm: x86.ACMOVWCS, 11554 reg: regInfo{ 11555 inputs: []inputInfo{ 11556 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11557 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11558 }, 11559 outputs: []outputInfo{ 11560 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11561 }, 11562 }, 11563 }, 11564 { 11565 name: "CMOVQEQF", 11566 argLen: 3, 11567 resultInArg0: true, 11568 needIntTemp: true, 11569 asm: x86.ACMOVQNE, 11570 reg: regInfo{ 11571 inputs: []inputInfo{ 11572 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11573 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11574 }, 11575 outputs: []outputInfo{ 11576 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11577 }, 11578 }, 11579 }, 11580 { 11581 name: "CMOVQNEF", 11582 argLen: 3, 11583 resultInArg0: true, 11584 asm: x86.ACMOVQNE, 11585 reg: regInfo{ 11586 inputs: []inputInfo{ 11587 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11588 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11589 }, 11590 outputs: []outputInfo{ 11591 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11592 }, 11593 }, 11594 }, 11595 { 11596 name: "CMOVQGTF", 11597 argLen: 3, 11598 resultInArg0: true, 11599 asm: x86.ACMOVQHI, 11600 reg: regInfo{ 11601 inputs: []inputInfo{ 11602 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11603 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11604 }, 11605 outputs: []outputInfo{ 11606 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11607 }, 11608 }, 11609 }, 11610 { 11611 name: "CMOVQGEF", 11612 argLen: 3, 11613 resultInArg0: true, 11614 asm: x86.ACMOVQCC, 11615 reg: regInfo{ 11616 inputs: []inputInfo{ 11617 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11618 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11619 }, 11620 outputs: []outputInfo{ 11621 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11622 }, 11623 }, 11624 }, 11625 { 11626 name: "CMOVLEQF", 11627 argLen: 3, 11628 resultInArg0: true, 11629 needIntTemp: true, 11630 asm: x86.ACMOVLNE, 11631 reg: regInfo{ 11632 inputs: []inputInfo{ 11633 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11634 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11635 }, 11636 outputs: []outputInfo{ 11637 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11638 }, 11639 }, 11640 }, 11641 { 11642 name: "CMOVLNEF", 11643 argLen: 3, 11644 resultInArg0: true, 11645 asm: x86.ACMOVLNE, 11646 reg: regInfo{ 11647 inputs: []inputInfo{ 11648 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11649 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11650 }, 11651 outputs: []outputInfo{ 11652 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11653 }, 11654 }, 11655 }, 11656 { 11657 name: "CMOVLGTF", 11658 argLen: 3, 11659 resultInArg0: true, 11660 asm: x86.ACMOVLHI, 11661 reg: regInfo{ 11662 inputs: []inputInfo{ 11663 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11664 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11665 }, 11666 outputs: []outputInfo{ 11667 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11668 }, 11669 }, 11670 }, 11671 { 11672 name: "CMOVLGEF", 11673 argLen: 3, 11674 resultInArg0: true, 11675 asm: x86.ACMOVLCC, 11676 reg: regInfo{ 11677 inputs: []inputInfo{ 11678 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11679 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11680 }, 11681 outputs: []outputInfo{ 11682 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11683 }, 11684 }, 11685 }, 11686 { 11687 name: "CMOVWEQF", 11688 argLen: 3, 11689 resultInArg0: true, 11690 needIntTemp: true, 11691 asm: x86.ACMOVWNE, 11692 reg: regInfo{ 11693 inputs: []inputInfo{ 11694 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11695 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11696 }, 11697 outputs: []outputInfo{ 11698 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11699 }, 11700 }, 11701 }, 11702 { 11703 name: "CMOVWNEF", 11704 argLen: 3, 11705 resultInArg0: true, 11706 asm: x86.ACMOVWNE, 11707 reg: regInfo{ 11708 inputs: []inputInfo{ 11709 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11710 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11711 }, 11712 outputs: []outputInfo{ 11713 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11714 }, 11715 }, 11716 }, 11717 { 11718 name: "CMOVWGTF", 11719 argLen: 3, 11720 resultInArg0: true, 11721 asm: x86.ACMOVWHI, 11722 reg: regInfo{ 11723 inputs: []inputInfo{ 11724 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11725 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11726 }, 11727 outputs: []outputInfo{ 11728 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11729 }, 11730 }, 11731 }, 11732 { 11733 name: "CMOVWGEF", 11734 argLen: 3, 11735 resultInArg0: true, 11736 asm: x86.ACMOVWCC, 11737 reg: regInfo{ 11738 inputs: []inputInfo{ 11739 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11740 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11741 }, 11742 outputs: []outputInfo{ 11743 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11744 }, 11745 }, 11746 }, 11747 { 11748 name: "BSWAPQ", 11749 argLen: 1, 11750 resultInArg0: true, 11751 asm: x86.ABSWAPQ, 11752 reg: regInfo{ 11753 inputs: []inputInfo{ 11754 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11755 }, 11756 outputs: []outputInfo{ 11757 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11758 }, 11759 }, 11760 }, 11761 { 11762 name: "BSWAPL", 11763 argLen: 1, 11764 resultInArg0: true, 11765 asm: x86.ABSWAPL, 11766 reg: regInfo{ 11767 inputs: []inputInfo{ 11768 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11769 }, 11770 outputs: []outputInfo{ 11771 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11772 }, 11773 }, 11774 }, 11775 { 11776 name: "POPCNTQ", 11777 argLen: 1, 11778 clobberFlags: true, 11779 asm: x86.APOPCNTQ, 11780 reg: regInfo{ 11781 inputs: []inputInfo{ 11782 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11783 }, 11784 outputs: []outputInfo{ 11785 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11786 }, 11787 }, 11788 }, 11789 { 11790 name: "POPCNTL", 11791 argLen: 1, 11792 clobberFlags: true, 11793 asm: x86.APOPCNTL, 11794 reg: regInfo{ 11795 inputs: []inputInfo{ 11796 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11797 }, 11798 outputs: []outputInfo{ 11799 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11800 }, 11801 }, 11802 }, 11803 { 11804 name: "SQRTSD", 11805 argLen: 1, 11806 asm: x86.ASQRTSD, 11807 reg: regInfo{ 11808 inputs: []inputInfo{ 11809 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11810 }, 11811 outputs: []outputInfo{ 11812 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11813 }, 11814 }, 11815 }, 11816 { 11817 name: "SQRTSS", 11818 argLen: 1, 11819 asm: x86.ASQRTSS, 11820 reg: regInfo{ 11821 inputs: []inputInfo{ 11822 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11823 }, 11824 outputs: []outputInfo{ 11825 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11826 }, 11827 }, 11828 }, 11829 { 11830 name: "ROUNDSD", 11831 auxType: auxInt8, 11832 argLen: 1, 11833 asm: x86.AROUNDSD, 11834 reg: regInfo{ 11835 inputs: []inputInfo{ 11836 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11837 }, 11838 outputs: []outputInfo{ 11839 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11840 }, 11841 }, 11842 }, 11843 { 11844 name: "VFMADD231SD", 11845 argLen: 3, 11846 resultInArg0: true, 11847 asm: x86.AVFMADD231SD, 11848 reg: regInfo{ 11849 inputs: []inputInfo{ 11850 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11851 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11852 {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11853 }, 11854 outputs: []outputInfo{ 11855 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 11856 }, 11857 }, 11858 }, 11859 { 11860 name: "SBBQcarrymask", 11861 argLen: 1, 11862 asm: x86.ASBBQ, 11863 reg: regInfo{ 11864 outputs: []outputInfo{ 11865 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11866 }, 11867 }, 11868 }, 11869 { 11870 name: "SBBLcarrymask", 11871 argLen: 1, 11872 asm: x86.ASBBL, 11873 reg: regInfo{ 11874 outputs: []outputInfo{ 11875 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11876 }, 11877 }, 11878 }, 11879 { 11880 name: "SETEQ", 11881 argLen: 1, 11882 asm: x86.ASETEQ, 11883 reg: regInfo{ 11884 outputs: []outputInfo{ 11885 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11886 }, 11887 }, 11888 }, 11889 { 11890 name: "SETNE", 11891 argLen: 1, 11892 asm: x86.ASETNE, 11893 reg: regInfo{ 11894 outputs: []outputInfo{ 11895 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11896 }, 11897 }, 11898 }, 11899 { 11900 name: "SETL", 11901 argLen: 1, 11902 asm: x86.ASETLT, 11903 reg: regInfo{ 11904 outputs: []outputInfo{ 11905 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11906 }, 11907 }, 11908 }, 11909 { 11910 name: "SETLE", 11911 argLen: 1, 11912 asm: x86.ASETLE, 11913 reg: regInfo{ 11914 outputs: []outputInfo{ 11915 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11916 }, 11917 }, 11918 }, 11919 { 11920 name: "SETG", 11921 argLen: 1, 11922 asm: x86.ASETGT, 11923 reg: regInfo{ 11924 outputs: []outputInfo{ 11925 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11926 }, 11927 }, 11928 }, 11929 { 11930 name: "SETGE", 11931 argLen: 1, 11932 asm: x86.ASETGE, 11933 reg: regInfo{ 11934 outputs: []outputInfo{ 11935 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11936 }, 11937 }, 11938 }, 11939 { 11940 name: "SETB", 11941 argLen: 1, 11942 asm: x86.ASETCS, 11943 reg: regInfo{ 11944 outputs: []outputInfo{ 11945 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11946 }, 11947 }, 11948 }, 11949 { 11950 name: "SETBE", 11951 argLen: 1, 11952 asm: x86.ASETLS, 11953 reg: regInfo{ 11954 outputs: []outputInfo{ 11955 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11956 }, 11957 }, 11958 }, 11959 { 11960 name: "SETA", 11961 argLen: 1, 11962 asm: x86.ASETHI, 11963 reg: regInfo{ 11964 outputs: []outputInfo{ 11965 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11966 }, 11967 }, 11968 }, 11969 { 11970 name: "SETAE", 11971 argLen: 1, 11972 asm: x86.ASETCC, 11973 reg: regInfo{ 11974 outputs: []outputInfo{ 11975 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11976 }, 11977 }, 11978 }, 11979 { 11980 name: "SETO", 11981 argLen: 1, 11982 asm: x86.ASETOS, 11983 reg: regInfo{ 11984 outputs: []outputInfo{ 11985 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 11986 }, 11987 }, 11988 }, 11989 { 11990 name: "SETEQstore", 11991 auxType: auxSymOff, 11992 argLen: 3, 11993 faultOnNilArg0: true, 11994 symEffect: SymWrite, 11995 asm: x86.ASETEQ, 11996 reg: regInfo{ 11997 inputs: []inputInfo{ 11998 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 11999 }, 12000 }, 12001 }, 12002 { 12003 name: "SETNEstore", 12004 auxType: auxSymOff, 12005 argLen: 3, 12006 faultOnNilArg0: true, 12007 symEffect: SymWrite, 12008 asm: x86.ASETNE, 12009 reg: regInfo{ 12010 inputs: []inputInfo{ 12011 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12012 }, 12013 }, 12014 }, 12015 { 12016 name: "SETLstore", 12017 auxType: auxSymOff, 12018 argLen: 3, 12019 faultOnNilArg0: true, 12020 symEffect: SymWrite, 12021 asm: x86.ASETLT, 12022 reg: regInfo{ 12023 inputs: []inputInfo{ 12024 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12025 }, 12026 }, 12027 }, 12028 { 12029 name: "SETLEstore", 12030 auxType: auxSymOff, 12031 argLen: 3, 12032 faultOnNilArg0: true, 12033 symEffect: SymWrite, 12034 asm: x86.ASETLE, 12035 reg: regInfo{ 12036 inputs: []inputInfo{ 12037 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12038 }, 12039 }, 12040 }, 12041 { 12042 name: "SETGstore", 12043 auxType: auxSymOff, 12044 argLen: 3, 12045 faultOnNilArg0: true, 12046 symEffect: SymWrite, 12047 asm: x86.ASETGT, 12048 reg: regInfo{ 12049 inputs: []inputInfo{ 12050 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12051 }, 12052 }, 12053 }, 12054 { 12055 name: "SETGEstore", 12056 auxType: auxSymOff, 12057 argLen: 3, 12058 faultOnNilArg0: true, 12059 symEffect: SymWrite, 12060 asm: x86.ASETGE, 12061 reg: regInfo{ 12062 inputs: []inputInfo{ 12063 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12064 }, 12065 }, 12066 }, 12067 { 12068 name: "SETBstore", 12069 auxType: auxSymOff, 12070 argLen: 3, 12071 faultOnNilArg0: true, 12072 symEffect: SymWrite, 12073 asm: x86.ASETCS, 12074 reg: regInfo{ 12075 inputs: []inputInfo{ 12076 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12077 }, 12078 }, 12079 }, 12080 { 12081 name: "SETBEstore", 12082 auxType: auxSymOff, 12083 argLen: 3, 12084 faultOnNilArg0: true, 12085 symEffect: SymWrite, 12086 asm: x86.ASETLS, 12087 reg: regInfo{ 12088 inputs: []inputInfo{ 12089 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12090 }, 12091 }, 12092 }, 12093 { 12094 name: "SETAstore", 12095 auxType: auxSymOff, 12096 argLen: 3, 12097 faultOnNilArg0: true, 12098 symEffect: SymWrite, 12099 asm: x86.ASETHI, 12100 reg: regInfo{ 12101 inputs: []inputInfo{ 12102 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12103 }, 12104 }, 12105 }, 12106 { 12107 name: "SETAEstore", 12108 auxType: auxSymOff, 12109 argLen: 3, 12110 faultOnNilArg0: true, 12111 symEffect: SymWrite, 12112 asm: x86.ASETCC, 12113 reg: regInfo{ 12114 inputs: []inputInfo{ 12115 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12116 }, 12117 }, 12118 }, 12119 { 12120 name: "SETEQF", 12121 argLen: 1, 12122 clobberFlags: true, 12123 needIntTemp: true, 12124 asm: x86.ASETEQ, 12125 reg: regInfo{ 12126 outputs: []outputInfo{ 12127 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12128 }, 12129 }, 12130 }, 12131 { 12132 name: "SETNEF", 12133 argLen: 1, 12134 clobberFlags: true, 12135 needIntTemp: true, 12136 asm: x86.ASETNE, 12137 reg: regInfo{ 12138 outputs: []outputInfo{ 12139 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12140 }, 12141 }, 12142 }, 12143 { 12144 name: "SETORD", 12145 argLen: 1, 12146 asm: x86.ASETPC, 12147 reg: regInfo{ 12148 outputs: []outputInfo{ 12149 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12150 }, 12151 }, 12152 }, 12153 { 12154 name: "SETNAN", 12155 argLen: 1, 12156 asm: x86.ASETPS, 12157 reg: regInfo{ 12158 outputs: []outputInfo{ 12159 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12160 }, 12161 }, 12162 }, 12163 { 12164 name: "SETGF", 12165 argLen: 1, 12166 asm: x86.ASETHI, 12167 reg: regInfo{ 12168 outputs: []outputInfo{ 12169 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12170 }, 12171 }, 12172 }, 12173 { 12174 name: "SETGEF", 12175 argLen: 1, 12176 asm: x86.ASETCC, 12177 reg: regInfo{ 12178 outputs: []outputInfo{ 12179 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12180 }, 12181 }, 12182 }, 12183 { 12184 name: "MOVBQSX", 12185 argLen: 1, 12186 asm: x86.AMOVBQSX, 12187 reg: regInfo{ 12188 inputs: []inputInfo{ 12189 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12190 }, 12191 outputs: []outputInfo{ 12192 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12193 }, 12194 }, 12195 }, 12196 { 12197 name: "MOVBQZX", 12198 argLen: 1, 12199 asm: x86.AMOVBLZX, 12200 reg: regInfo{ 12201 inputs: []inputInfo{ 12202 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12203 }, 12204 outputs: []outputInfo{ 12205 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12206 }, 12207 }, 12208 }, 12209 { 12210 name: "MOVWQSX", 12211 argLen: 1, 12212 asm: x86.AMOVWQSX, 12213 reg: regInfo{ 12214 inputs: []inputInfo{ 12215 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12216 }, 12217 outputs: []outputInfo{ 12218 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12219 }, 12220 }, 12221 }, 12222 { 12223 name: "MOVWQZX", 12224 argLen: 1, 12225 asm: x86.AMOVWLZX, 12226 reg: regInfo{ 12227 inputs: []inputInfo{ 12228 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12229 }, 12230 outputs: []outputInfo{ 12231 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12232 }, 12233 }, 12234 }, 12235 { 12236 name: "MOVLQSX", 12237 argLen: 1, 12238 asm: x86.AMOVLQSX, 12239 reg: regInfo{ 12240 inputs: []inputInfo{ 12241 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12242 }, 12243 outputs: []outputInfo{ 12244 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12245 }, 12246 }, 12247 }, 12248 { 12249 name: "MOVLQZX", 12250 argLen: 1, 12251 asm: x86.AMOVL, 12252 reg: regInfo{ 12253 inputs: []inputInfo{ 12254 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12255 }, 12256 outputs: []outputInfo{ 12257 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12258 }, 12259 }, 12260 }, 12261 { 12262 name: "MOVLconst", 12263 auxType: auxInt32, 12264 argLen: 0, 12265 rematerializeable: true, 12266 asm: x86.AMOVL, 12267 reg: regInfo{ 12268 outputs: []outputInfo{ 12269 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12270 }, 12271 }, 12272 }, 12273 { 12274 name: "MOVQconst", 12275 auxType: auxInt64, 12276 argLen: 0, 12277 rematerializeable: true, 12278 asm: x86.AMOVQ, 12279 reg: regInfo{ 12280 outputs: []outputInfo{ 12281 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12282 }, 12283 }, 12284 }, 12285 { 12286 name: "CVTTSD2SL", 12287 argLen: 1, 12288 asm: x86.ACVTTSD2SL, 12289 reg: regInfo{ 12290 inputs: []inputInfo{ 12291 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12292 }, 12293 outputs: []outputInfo{ 12294 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12295 }, 12296 }, 12297 }, 12298 { 12299 name: "CVTTSD2SQ", 12300 argLen: 1, 12301 asm: x86.ACVTTSD2SQ, 12302 reg: regInfo{ 12303 inputs: []inputInfo{ 12304 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12305 }, 12306 outputs: []outputInfo{ 12307 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12308 }, 12309 }, 12310 }, 12311 { 12312 name: "CVTTSS2SL", 12313 argLen: 1, 12314 asm: x86.ACVTTSS2SL, 12315 reg: regInfo{ 12316 inputs: []inputInfo{ 12317 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12318 }, 12319 outputs: []outputInfo{ 12320 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12321 }, 12322 }, 12323 }, 12324 { 12325 name: "CVTTSS2SQ", 12326 argLen: 1, 12327 asm: x86.ACVTTSS2SQ, 12328 reg: regInfo{ 12329 inputs: []inputInfo{ 12330 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12331 }, 12332 outputs: []outputInfo{ 12333 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12334 }, 12335 }, 12336 }, 12337 { 12338 name: "CVTSL2SS", 12339 argLen: 1, 12340 asm: x86.ACVTSL2SS, 12341 reg: regInfo{ 12342 inputs: []inputInfo{ 12343 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12344 }, 12345 outputs: []outputInfo{ 12346 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12347 }, 12348 }, 12349 }, 12350 { 12351 name: "CVTSL2SD", 12352 argLen: 1, 12353 asm: x86.ACVTSL2SD, 12354 reg: regInfo{ 12355 inputs: []inputInfo{ 12356 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12357 }, 12358 outputs: []outputInfo{ 12359 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12360 }, 12361 }, 12362 }, 12363 { 12364 name: "CVTSQ2SS", 12365 argLen: 1, 12366 asm: x86.ACVTSQ2SS, 12367 reg: regInfo{ 12368 inputs: []inputInfo{ 12369 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12370 }, 12371 outputs: []outputInfo{ 12372 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12373 }, 12374 }, 12375 }, 12376 { 12377 name: "CVTSQ2SD", 12378 argLen: 1, 12379 asm: x86.ACVTSQ2SD, 12380 reg: regInfo{ 12381 inputs: []inputInfo{ 12382 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12383 }, 12384 outputs: []outputInfo{ 12385 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12386 }, 12387 }, 12388 }, 12389 { 12390 name: "CVTSD2SS", 12391 argLen: 1, 12392 asm: x86.ACVTSD2SS, 12393 reg: regInfo{ 12394 inputs: []inputInfo{ 12395 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12396 }, 12397 outputs: []outputInfo{ 12398 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12399 }, 12400 }, 12401 }, 12402 { 12403 name: "CVTSS2SD", 12404 argLen: 1, 12405 asm: x86.ACVTSS2SD, 12406 reg: regInfo{ 12407 inputs: []inputInfo{ 12408 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12409 }, 12410 outputs: []outputInfo{ 12411 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12412 }, 12413 }, 12414 }, 12415 { 12416 name: "MOVQi2f", 12417 argLen: 1, 12418 reg: regInfo{ 12419 inputs: []inputInfo{ 12420 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12421 }, 12422 outputs: []outputInfo{ 12423 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12424 }, 12425 }, 12426 }, 12427 { 12428 name: "MOVQf2i", 12429 argLen: 1, 12430 reg: regInfo{ 12431 inputs: []inputInfo{ 12432 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12433 }, 12434 outputs: []outputInfo{ 12435 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12436 }, 12437 }, 12438 }, 12439 { 12440 name: "MOVLi2f", 12441 argLen: 1, 12442 reg: regInfo{ 12443 inputs: []inputInfo{ 12444 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12445 }, 12446 outputs: []outputInfo{ 12447 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12448 }, 12449 }, 12450 }, 12451 { 12452 name: "MOVLf2i", 12453 argLen: 1, 12454 reg: regInfo{ 12455 inputs: []inputInfo{ 12456 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12457 }, 12458 outputs: []outputInfo{ 12459 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12460 }, 12461 }, 12462 }, 12463 { 12464 name: "PXOR", 12465 argLen: 2, 12466 commutative: true, 12467 resultInArg0: true, 12468 asm: x86.APXOR, 12469 reg: regInfo{ 12470 inputs: []inputInfo{ 12471 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12472 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12473 }, 12474 outputs: []outputInfo{ 12475 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12476 }, 12477 }, 12478 }, 12479 { 12480 name: "LEAQ", 12481 auxType: auxSymOff, 12482 argLen: 1, 12483 rematerializeable: true, 12484 symEffect: SymAddr, 12485 asm: x86.ALEAQ, 12486 reg: regInfo{ 12487 inputs: []inputInfo{ 12488 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12489 }, 12490 outputs: []outputInfo{ 12491 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12492 }, 12493 }, 12494 }, 12495 { 12496 name: "LEAL", 12497 auxType: auxSymOff, 12498 argLen: 1, 12499 rematerializeable: true, 12500 symEffect: SymAddr, 12501 asm: x86.ALEAL, 12502 reg: regInfo{ 12503 inputs: []inputInfo{ 12504 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12505 }, 12506 outputs: []outputInfo{ 12507 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12508 }, 12509 }, 12510 }, 12511 { 12512 name: "LEAW", 12513 auxType: auxSymOff, 12514 argLen: 1, 12515 rematerializeable: true, 12516 symEffect: SymAddr, 12517 asm: x86.ALEAW, 12518 reg: regInfo{ 12519 inputs: []inputInfo{ 12520 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12521 }, 12522 outputs: []outputInfo{ 12523 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12524 }, 12525 }, 12526 }, 12527 { 12528 name: "LEAQ1", 12529 auxType: auxSymOff, 12530 argLen: 2, 12531 commutative: true, 12532 symEffect: SymAddr, 12533 asm: x86.ALEAQ, 12534 scale: 1, 12535 reg: regInfo{ 12536 inputs: []inputInfo{ 12537 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12538 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12539 }, 12540 outputs: []outputInfo{ 12541 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12542 }, 12543 }, 12544 }, 12545 { 12546 name: "LEAL1", 12547 auxType: auxSymOff, 12548 argLen: 2, 12549 commutative: true, 12550 symEffect: SymAddr, 12551 asm: x86.ALEAL, 12552 scale: 1, 12553 reg: regInfo{ 12554 inputs: []inputInfo{ 12555 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12556 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12557 }, 12558 outputs: []outputInfo{ 12559 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12560 }, 12561 }, 12562 }, 12563 { 12564 name: "LEAW1", 12565 auxType: auxSymOff, 12566 argLen: 2, 12567 commutative: true, 12568 symEffect: SymAddr, 12569 asm: x86.ALEAW, 12570 scale: 1, 12571 reg: regInfo{ 12572 inputs: []inputInfo{ 12573 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12574 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12575 }, 12576 outputs: []outputInfo{ 12577 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12578 }, 12579 }, 12580 }, 12581 { 12582 name: "LEAQ2", 12583 auxType: auxSymOff, 12584 argLen: 2, 12585 symEffect: SymAddr, 12586 asm: x86.ALEAQ, 12587 scale: 2, 12588 reg: regInfo{ 12589 inputs: []inputInfo{ 12590 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12591 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12592 }, 12593 outputs: []outputInfo{ 12594 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12595 }, 12596 }, 12597 }, 12598 { 12599 name: "LEAL2", 12600 auxType: auxSymOff, 12601 argLen: 2, 12602 symEffect: SymAddr, 12603 asm: x86.ALEAL, 12604 scale: 2, 12605 reg: regInfo{ 12606 inputs: []inputInfo{ 12607 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12608 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12609 }, 12610 outputs: []outputInfo{ 12611 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12612 }, 12613 }, 12614 }, 12615 { 12616 name: "LEAW2", 12617 auxType: auxSymOff, 12618 argLen: 2, 12619 symEffect: SymAddr, 12620 asm: x86.ALEAW, 12621 scale: 2, 12622 reg: regInfo{ 12623 inputs: []inputInfo{ 12624 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12625 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12626 }, 12627 outputs: []outputInfo{ 12628 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12629 }, 12630 }, 12631 }, 12632 { 12633 name: "LEAQ4", 12634 auxType: auxSymOff, 12635 argLen: 2, 12636 symEffect: SymAddr, 12637 asm: x86.ALEAQ, 12638 scale: 4, 12639 reg: regInfo{ 12640 inputs: []inputInfo{ 12641 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12642 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12643 }, 12644 outputs: []outputInfo{ 12645 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12646 }, 12647 }, 12648 }, 12649 { 12650 name: "LEAL4", 12651 auxType: auxSymOff, 12652 argLen: 2, 12653 symEffect: SymAddr, 12654 asm: x86.ALEAL, 12655 scale: 4, 12656 reg: regInfo{ 12657 inputs: []inputInfo{ 12658 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12659 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12660 }, 12661 outputs: []outputInfo{ 12662 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12663 }, 12664 }, 12665 }, 12666 { 12667 name: "LEAW4", 12668 auxType: auxSymOff, 12669 argLen: 2, 12670 symEffect: SymAddr, 12671 asm: x86.ALEAW, 12672 scale: 4, 12673 reg: regInfo{ 12674 inputs: []inputInfo{ 12675 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12676 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12677 }, 12678 outputs: []outputInfo{ 12679 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12680 }, 12681 }, 12682 }, 12683 { 12684 name: "LEAQ8", 12685 auxType: auxSymOff, 12686 argLen: 2, 12687 symEffect: SymAddr, 12688 asm: x86.ALEAQ, 12689 scale: 8, 12690 reg: regInfo{ 12691 inputs: []inputInfo{ 12692 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12693 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12694 }, 12695 outputs: []outputInfo{ 12696 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12697 }, 12698 }, 12699 }, 12700 { 12701 name: "LEAL8", 12702 auxType: auxSymOff, 12703 argLen: 2, 12704 symEffect: SymAddr, 12705 asm: x86.ALEAL, 12706 scale: 8, 12707 reg: regInfo{ 12708 inputs: []inputInfo{ 12709 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12710 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12711 }, 12712 outputs: []outputInfo{ 12713 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12714 }, 12715 }, 12716 }, 12717 { 12718 name: "LEAW8", 12719 auxType: auxSymOff, 12720 argLen: 2, 12721 symEffect: SymAddr, 12722 asm: x86.ALEAW, 12723 scale: 8, 12724 reg: regInfo{ 12725 inputs: []inputInfo{ 12726 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12727 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12728 }, 12729 outputs: []outputInfo{ 12730 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12731 }, 12732 }, 12733 }, 12734 { 12735 name: "MOVBload", 12736 auxType: auxSymOff, 12737 argLen: 2, 12738 faultOnNilArg0: true, 12739 symEffect: SymRead, 12740 asm: x86.AMOVBLZX, 12741 reg: regInfo{ 12742 inputs: []inputInfo{ 12743 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12744 }, 12745 outputs: []outputInfo{ 12746 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12747 }, 12748 }, 12749 }, 12750 { 12751 name: "MOVBQSXload", 12752 auxType: auxSymOff, 12753 argLen: 2, 12754 faultOnNilArg0: true, 12755 symEffect: SymRead, 12756 asm: x86.AMOVBQSX, 12757 reg: regInfo{ 12758 inputs: []inputInfo{ 12759 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12760 }, 12761 outputs: []outputInfo{ 12762 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12763 }, 12764 }, 12765 }, 12766 { 12767 name: "MOVWload", 12768 auxType: auxSymOff, 12769 argLen: 2, 12770 faultOnNilArg0: true, 12771 symEffect: SymRead, 12772 asm: x86.AMOVWLZX, 12773 reg: regInfo{ 12774 inputs: []inputInfo{ 12775 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12776 }, 12777 outputs: []outputInfo{ 12778 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12779 }, 12780 }, 12781 }, 12782 { 12783 name: "MOVWQSXload", 12784 auxType: auxSymOff, 12785 argLen: 2, 12786 faultOnNilArg0: true, 12787 symEffect: SymRead, 12788 asm: x86.AMOVWQSX, 12789 reg: regInfo{ 12790 inputs: []inputInfo{ 12791 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12792 }, 12793 outputs: []outputInfo{ 12794 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12795 }, 12796 }, 12797 }, 12798 { 12799 name: "MOVLload", 12800 auxType: auxSymOff, 12801 argLen: 2, 12802 faultOnNilArg0: true, 12803 symEffect: SymRead, 12804 asm: x86.AMOVL, 12805 reg: regInfo{ 12806 inputs: []inputInfo{ 12807 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12808 }, 12809 outputs: []outputInfo{ 12810 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12811 }, 12812 }, 12813 }, 12814 { 12815 name: "MOVLQSXload", 12816 auxType: auxSymOff, 12817 argLen: 2, 12818 faultOnNilArg0: true, 12819 symEffect: SymRead, 12820 asm: x86.AMOVLQSX, 12821 reg: regInfo{ 12822 inputs: []inputInfo{ 12823 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12824 }, 12825 outputs: []outputInfo{ 12826 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12827 }, 12828 }, 12829 }, 12830 { 12831 name: "MOVQload", 12832 auxType: auxSymOff, 12833 argLen: 2, 12834 faultOnNilArg0: true, 12835 symEffect: SymRead, 12836 asm: x86.AMOVQ, 12837 reg: regInfo{ 12838 inputs: []inputInfo{ 12839 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12840 }, 12841 outputs: []outputInfo{ 12842 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12843 }, 12844 }, 12845 }, 12846 { 12847 name: "MOVBstore", 12848 auxType: auxSymOff, 12849 argLen: 3, 12850 faultOnNilArg0: true, 12851 symEffect: SymWrite, 12852 asm: x86.AMOVB, 12853 reg: regInfo{ 12854 inputs: []inputInfo{ 12855 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12856 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12857 }, 12858 }, 12859 }, 12860 { 12861 name: "MOVWstore", 12862 auxType: auxSymOff, 12863 argLen: 3, 12864 faultOnNilArg0: true, 12865 symEffect: SymWrite, 12866 asm: x86.AMOVW, 12867 reg: regInfo{ 12868 inputs: []inputInfo{ 12869 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12870 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12871 }, 12872 }, 12873 }, 12874 { 12875 name: "MOVLstore", 12876 auxType: auxSymOff, 12877 argLen: 3, 12878 faultOnNilArg0: true, 12879 symEffect: SymWrite, 12880 asm: x86.AMOVL, 12881 reg: regInfo{ 12882 inputs: []inputInfo{ 12883 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12884 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12885 }, 12886 }, 12887 }, 12888 { 12889 name: "MOVQstore", 12890 auxType: auxSymOff, 12891 argLen: 3, 12892 faultOnNilArg0: true, 12893 symEffect: SymWrite, 12894 asm: x86.AMOVQ, 12895 reg: regInfo{ 12896 inputs: []inputInfo{ 12897 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12898 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12899 }, 12900 }, 12901 }, 12902 { 12903 name: "MOVOload", 12904 auxType: auxSymOff, 12905 argLen: 2, 12906 faultOnNilArg0: true, 12907 symEffect: SymRead, 12908 asm: x86.AMOVUPS, 12909 reg: regInfo{ 12910 inputs: []inputInfo{ 12911 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 12912 }, 12913 outputs: []outputInfo{ 12914 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12915 }, 12916 }, 12917 }, 12918 { 12919 name: "MOVOstore", 12920 auxType: auxSymOff, 12921 argLen: 3, 12922 faultOnNilArg0: true, 12923 symEffect: SymWrite, 12924 asm: x86.AMOVUPS, 12925 reg: regInfo{ 12926 inputs: []inputInfo{ 12927 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 12928 {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB 12929 }, 12930 }, 12931 }, 12932 { 12933 name: "MOVBloadidx1", 12934 auxType: auxSymOff, 12935 argLen: 3, 12936 commutative: true, 12937 symEffect: SymRead, 12938 asm: x86.AMOVBLZX, 12939 scale: 1, 12940 reg: regInfo{ 12941 inputs: []inputInfo{ 12942 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12943 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12944 }, 12945 outputs: []outputInfo{ 12946 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12947 }, 12948 }, 12949 }, 12950 { 12951 name: "MOVWloadidx1", 12952 auxType: auxSymOff, 12953 argLen: 3, 12954 commutative: true, 12955 symEffect: SymRead, 12956 asm: x86.AMOVWLZX, 12957 scale: 1, 12958 reg: regInfo{ 12959 inputs: []inputInfo{ 12960 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12961 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12962 }, 12963 outputs: []outputInfo{ 12964 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12965 }, 12966 }, 12967 }, 12968 { 12969 name: "MOVWloadidx2", 12970 auxType: auxSymOff, 12971 argLen: 3, 12972 symEffect: SymRead, 12973 asm: x86.AMOVWLZX, 12974 scale: 2, 12975 reg: regInfo{ 12976 inputs: []inputInfo{ 12977 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12978 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12979 }, 12980 outputs: []outputInfo{ 12981 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 12982 }, 12983 }, 12984 }, 12985 { 12986 name: "MOVLloadidx1", 12987 auxType: auxSymOff, 12988 argLen: 3, 12989 commutative: true, 12990 symEffect: SymRead, 12991 asm: x86.AMOVL, 12992 scale: 1, 12993 reg: regInfo{ 12994 inputs: []inputInfo{ 12995 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 12996 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 12997 }, 12998 outputs: []outputInfo{ 12999 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13000 }, 13001 }, 13002 }, 13003 { 13004 name: "MOVLloadidx4", 13005 auxType: auxSymOff, 13006 argLen: 3, 13007 symEffect: SymRead, 13008 asm: x86.AMOVL, 13009 scale: 4, 13010 reg: regInfo{ 13011 inputs: []inputInfo{ 13012 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13013 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13014 }, 13015 outputs: []outputInfo{ 13016 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13017 }, 13018 }, 13019 }, 13020 { 13021 name: "MOVLloadidx8", 13022 auxType: auxSymOff, 13023 argLen: 3, 13024 symEffect: SymRead, 13025 asm: x86.AMOVL, 13026 scale: 8, 13027 reg: regInfo{ 13028 inputs: []inputInfo{ 13029 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13030 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13031 }, 13032 outputs: []outputInfo{ 13033 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13034 }, 13035 }, 13036 }, 13037 { 13038 name: "MOVQloadidx1", 13039 auxType: auxSymOff, 13040 argLen: 3, 13041 commutative: true, 13042 symEffect: SymRead, 13043 asm: x86.AMOVQ, 13044 scale: 1, 13045 reg: regInfo{ 13046 inputs: []inputInfo{ 13047 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13048 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13049 }, 13050 outputs: []outputInfo{ 13051 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13052 }, 13053 }, 13054 }, 13055 { 13056 name: "MOVQloadidx8", 13057 auxType: auxSymOff, 13058 argLen: 3, 13059 symEffect: SymRead, 13060 asm: x86.AMOVQ, 13061 scale: 8, 13062 reg: regInfo{ 13063 inputs: []inputInfo{ 13064 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13065 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13066 }, 13067 outputs: []outputInfo{ 13068 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13069 }, 13070 }, 13071 }, 13072 { 13073 name: "MOVBstoreidx1", 13074 auxType: auxSymOff, 13075 argLen: 4, 13076 commutative: true, 13077 symEffect: SymWrite, 13078 asm: x86.AMOVB, 13079 scale: 1, 13080 reg: regInfo{ 13081 inputs: []inputInfo{ 13082 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13083 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13084 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13085 }, 13086 }, 13087 }, 13088 { 13089 name: "MOVWstoreidx1", 13090 auxType: auxSymOff, 13091 argLen: 4, 13092 commutative: true, 13093 symEffect: SymWrite, 13094 asm: x86.AMOVW, 13095 scale: 1, 13096 reg: regInfo{ 13097 inputs: []inputInfo{ 13098 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13099 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13100 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13101 }, 13102 }, 13103 }, 13104 { 13105 name: "MOVWstoreidx2", 13106 auxType: auxSymOff, 13107 argLen: 4, 13108 symEffect: SymWrite, 13109 asm: x86.AMOVW, 13110 scale: 2, 13111 reg: regInfo{ 13112 inputs: []inputInfo{ 13113 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13114 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13115 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13116 }, 13117 }, 13118 }, 13119 { 13120 name: "MOVLstoreidx1", 13121 auxType: auxSymOff, 13122 argLen: 4, 13123 commutative: true, 13124 symEffect: SymWrite, 13125 asm: x86.AMOVL, 13126 scale: 1, 13127 reg: regInfo{ 13128 inputs: []inputInfo{ 13129 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13130 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13131 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13132 }, 13133 }, 13134 }, 13135 { 13136 name: "MOVLstoreidx4", 13137 auxType: auxSymOff, 13138 argLen: 4, 13139 symEffect: SymWrite, 13140 asm: x86.AMOVL, 13141 scale: 4, 13142 reg: regInfo{ 13143 inputs: []inputInfo{ 13144 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13145 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13146 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13147 }, 13148 }, 13149 }, 13150 { 13151 name: "MOVLstoreidx8", 13152 auxType: auxSymOff, 13153 argLen: 4, 13154 symEffect: SymWrite, 13155 asm: x86.AMOVL, 13156 scale: 8, 13157 reg: regInfo{ 13158 inputs: []inputInfo{ 13159 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13160 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13161 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13162 }, 13163 }, 13164 }, 13165 { 13166 name: "MOVQstoreidx1", 13167 auxType: auxSymOff, 13168 argLen: 4, 13169 commutative: true, 13170 symEffect: SymWrite, 13171 asm: x86.AMOVQ, 13172 scale: 1, 13173 reg: regInfo{ 13174 inputs: []inputInfo{ 13175 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13176 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13177 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13178 }, 13179 }, 13180 }, 13181 { 13182 name: "MOVQstoreidx8", 13183 auxType: auxSymOff, 13184 argLen: 4, 13185 symEffect: SymWrite, 13186 asm: x86.AMOVQ, 13187 scale: 8, 13188 reg: regInfo{ 13189 inputs: []inputInfo{ 13190 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13191 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13192 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13193 }, 13194 }, 13195 }, 13196 { 13197 name: "MOVBstoreconst", 13198 auxType: auxSymValAndOff, 13199 argLen: 2, 13200 faultOnNilArg0: true, 13201 symEffect: SymWrite, 13202 asm: x86.AMOVB, 13203 reg: regInfo{ 13204 inputs: []inputInfo{ 13205 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13206 }, 13207 }, 13208 }, 13209 { 13210 name: "MOVWstoreconst", 13211 auxType: auxSymValAndOff, 13212 argLen: 2, 13213 faultOnNilArg0: true, 13214 symEffect: SymWrite, 13215 asm: x86.AMOVW, 13216 reg: regInfo{ 13217 inputs: []inputInfo{ 13218 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13219 }, 13220 }, 13221 }, 13222 { 13223 name: "MOVLstoreconst", 13224 auxType: auxSymValAndOff, 13225 argLen: 2, 13226 faultOnNilArg0: true, 13227 symEffect: SymWrite, 13228 asm: x86.AMOVL, 13229 reg: regInfo{ 13230 inputs: []inputInfo{ 13231 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13232 }, 13233 }, 13234 }, 13235 { 13236 name: "MOVQstoreconst", 13237 auxType: auxSymValAndOff, 13238 argLen: 2, 13239 faultOnNilArg0: true, 13240 symEffect: SymWrite, 13241 asm: x86.AMOVQ, 13242 reg: regInfo{ 13243 inputs: []inputInfo{ 13244 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13245 }, 13246 }, 13247 }, 13248 { 13249 name: "MOVOstoreconst", 13250 auxType: auxSymValAndOff, 13251 argLen: 2, 13252 faultOnNilArg0: true, 13253 symEffect: SymWrite, 13254 asm: x86.AMOVUPS, 13255 reg: regInfo{ 13256 inputs: []inputInfo{ 13257 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13258 }, 13259 }, 13260 }, 13261 { 13262 name: "MOVBstoreconstidx1", 13263 auxType: auxSymValAndOff, 13264 argLen: 3, 13265 commutative: true, 13266 symEffect: SymWrite, 13267 asm: x86.AMOVB, 13268 scale: 1, 13269 reg: regInfo{ 13270 inputs: []inputInfo{ 13271 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13272 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13273 }, 13274 }, 13275 }, 13276 { 13277 name: "MOVWstoreconstidx1", 13278 auxType: auxSymValAndOff, 13279 argLen: 3, 13280 commutative: true, 13281 symEffect: SymWrite, 13282 asm: x86.AMOVW, 13283 scale: 1, 13284 reg: regInfo{ 13285 inputs: []inputInfo{ 13286 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13287 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13288 }, 13289 }, 13290 }, 13291 { 13292 name: "MOVWstoreconstidx2", 13293 auxType: auxSymValAndOff, 13294 argLen: 3, 13295 symEffect: SymWrite, 13296 asm: x86.AMOVW, 13297 scale: 2, 13298 reg: regInfo{ 13299 inputs: []inputInfo{ 13300 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13301 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13302 }, 13303 }, 13304 }, 13305 { 13306 name: "MOVLstoreconstidx1", 13307 auxType: auxSymValAndOff, 13308 argLen: 3, 13309 commutative: true, 13310 symEffect: SymWrite, 13311 asm: x86.AMOVL, 13312 scale: 1, 13313 reg: regInfo{ 13314 inputs: []inputInfo{ 13315 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13316 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13317 }, 13318 }, 13319 }, 13320 { 13321 name: "MOVLstoreconstidx4", 13322 auxType: auxSymValAndOff, 13323 argLen: 3, 13324 symEffect: SymWrite, 13325 asm: x86.AMOVL, 13326 scale: 4, 13327 reg: regInfo{ 13328 inputs: []inputInfo{ 13329 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13330 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13331 }, 13332 }, 13333 }, 13334 { 13335 name: "MOVQstoreconstidx1", 13336 auxType: auxSymValAndOff, 13337 argLen: 3, 13338 commutative: true, 13339 symEffect: SymWrite, 13340 asm: x86.AMOVQ, 13341 scale: 1, 13342 reg: regInfo{ 13343 inputs: []inputInfo{ 13344 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13345 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13346 }, 13347 }, 13348 }, 13349 { 13350 name: "MOVQstoreconstidx8", 13351 auxType: auxSymValAndOff, 13352 argLen: 3, 13353 symEffect: SymWrite, 13354 asm: x86.AMOVQ, 13355 scale: 8, 13356 reg: regInfo{ 13357 inputs: []inputInfo{ 13358 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13359 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13360 }, 13361 }, 13362 }, 13363 { 13364 name: "DUFFZERO", 13365 auxType: auxInt64, 13366 argLen: 2, 13367 faultOnNilArg0: true, 13368 unsafePoint: true, 13369 reg: regInfo{ 13370 inputs: []inputInfo{ 13371 {0, 128}, // DI 13372 }, 13373 clobbers: 128, // DI 13374 }, 13375 }, 13376 { 13377 name: "REPSTOSQ", 13378 argLen: 4, 13379 faultOnNilArg0: true, 13380 reg: regInfo{ 13381 inputs: []inputInfo{ 13382 {0, 128}, // DI 13383 {1, 2}, // CX 13384 {2, 1}, // AX 13385 }, 13386 clobbers: 130, // CX DI 13387 }, 13388 }, 13389 { 13390 name: "CALLstatic", 13391 auxType: auxCallOff, 13392 argLen: -1, 13393 clobberFlags: true, 13394 call: true, 13395 reg: regInfo{ 13396 clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 13397 }, 13398 }, 13399 { 13400 name: "CALLtail", 13401 auxType: auxCallOff, 13402 argLen: -1, 13403 clobberFlags: true, 13404 call: true, 13405 tailCall: true, 13406 reg: regInfo{ 13407 clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 13408 }, 13409 }, 13410 { 13411 name: "CALLclosure", 13412 auxType: auxCallOff, 13413 argLen: -1, 13414 clobberFlags: true, 13415 call: true, 13416 reg: regInfo{ 13417 inputs: []inputInfo{ 13418 {1, 4}, // DX 13419 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13420 }, 13421 clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 13422 }, 13423 }, 13424 { 13425 name: "CALLinter", 13426 auxType: auxCallOff, 13427 argLen: -1, 13428 clobberFlags: true, 13429 call: true, 13430 reg: regInfo{ 13431 inputs: []inputInfo{ 13432 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13433 }, 13434 clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 13435 }, 13436 }, 13437 { 13438 name: "DUFFCOPY", 13439 auxType: auxInt64, 13440 argLen: 3, 13441 clobberFlags: true, 13442 faultOnNilArg0: true, 13443 faultOnNilArg1: true, 13444 unsafePoint: true, 13445 reg: regInfo{ 13446 inputs: []inputInfo{ 13447 {0, 128}, // DI 13448 {1, 64}, // SI 13449 }, 13450 clobbers: 65728, // SI DI X0 13451 }, 13452 }, 13453 { 13454 name: "REPMOVSQ", 13455 argLen: 4, 13456 faultOnNilArg0: true, 13457 faultOnNilArg1: true, 13458 reg: regInfo{ 13459 inputs: []inputInfo{ 13460 {0, 128}, // DI 13461 {1, 64}, // SI 13462 {2, 2}, // CX 13463 }, 13464 clobbers: 194, // CX SI DI 13465 }, 13466 }, 13467 { 13468 name: "InvertFlags", 13469 argLen: 1, 13470 reg: regInfo{}, 13471 }, 13472 { 13473 name: "LoweredGetG", 13474 argLen: 1, 13475 reg: regInfo{ 13476 outputs: []outputInfo{ 13477 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13478 }, 13479 }, 13480 }, 13481 { 13482 name: "LoweredGetClosurePtr", 13483 argLen: 0, 13484 zeroWidth: true, 13485 reg: regInfo{ 13486 outputs: []outputInfo{ 13487 {0, 4}, // DX 13488 }, 13489 }, 13490 }, 13491 { 13492 name: "LoweredGetCallerPC", 13493 argLen: 0, 13494 rematerializeable: true, 13495 reg: regInfo{ 13496 outputs: []outputInfo{ 13497 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13498 }, 13499 }, 13500 }, 13501 { 13502 name: "LoweredGetCallerSP", 13503 argLen: 0, 13504 rematerializeable: true, 13505 reg: regInfo{ 13506 outputs: []outputInfo{ 13507 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13508 }, 13509 }, 13510 }, 13511 { 13512 name: "LoweredNilCheck", 13513 argLen: 2, 13514 clobberFlags: true, 13515 nilCheck: true, 13516 faultOnNilArg0: true, 13517 reg: regInfo{ 13518 inputs: []inputInfo{ 13519 {0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13520 }, 13521 }, 13522 }, 13523 { 13524 name: "LoweredWB", 13525 auxType: auxSym, 13526 argLen: 3, 13527 clobberFlags: true, 13528 symEffect: SymNone, 13529 reg: regInfo{ 13530 inputs: []inputInfo{ 13531 {0, 128}, // DI 13532 {1, 879}, // AX CX DX BX BP SI R8 R9 13533 }, 13534 clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 13535 }, 13536 }, 13537 { 13538 name: "LoweredHasCPUFeature", 13539 auxType: auxSym, 13540 argLen: 0, 13541 rematerializeable: true, 13542 symEffect: SymNone, 13543 reg: regInfo{ 13544 outputs: []outputInfo{ 13545 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13546 }, 13547 }, 13548 }, 13549 { 13550 name: "LoweredPanicBoundsA", 13551 auxType: auxInt64, 13552 argLen: 3, 13553 call: true, 13554 reg: regInfo{ 13555 inputs: []inputInfo{ 13556 {0, 4}, // DX 13557 {1, 8}, // BX 13558 }, 13559 }, 13560 }, 13561 { 13562 name: "LoweredPanicBoundsB", 13563 auxType: auxInt64, 13564 argLen: 3, 13565 call: true, 13566 reg: regInfo{ 13567 inputs: []inputInfo{ 13568 {0, 2}, // CX 13569 {1, 4}, // DX 13570 }, 13571 }, 13572 }, 13573 { 13574 name: "LoweredPanicBoundsC", 13575 auxType: auxInt64, 13576 argLen: 3, 13577 call: true, 13578 reg: regInfo{ 13579 inputs: []inputInfo{ 13580 {0, 1}, // AX 13581 {1, 2}, // CX 13582 }, 13583 }, 13584 }, 13585 { 13586 name: "FlagEQ", 13587 argLen: 0, 13588 reg: regInfo{}, 13589 }, 13590 { 13591 name: "FlagLT_ULT", 13592 argLen: 0, 13593 reg: regInfo{}, 13594 }, 13595 { 13596 name: "FlagLT_UGT", 13597 argLen: 0, 13598 reg: regInfo{}, 13599 }, 13600 { 13601 name: "FlagGT_UGT", 13602 argLen: 0, 13603 reg: regInfo{}, 13604 }, 13605 { 13606 name: "FlagGT_ULT", 13607 argLen: 0, 13608 reg: regInfo{}, 13609 }, 13610 { 13611 name: "MOVBatomicload", 13612 auxType: auxSymOff, 13613 argLen: 2, 13614 faultOnNilArg0: true, 13615 symEffect: SymRead, 13616 asm: x86.AMOVB, 13617 reg: regInfo{ 13618 inputs: []inputInfo{ 13619 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13620 }, 13621 outputs: []outputInfo{ 13622 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13623 }, 13624 }, 13625 }, 13626 { 13627 name: "MOVLatomicload", 13628 auxType: auxSymOff, 13629 argLen: 2, 13630 faultOnNilArg0: true, 13631 symEffect: SymRead, 13632 asm: x86.AMOVL, 13633 reg: regInfo{ 13634 inputs: []inputInfo{ 13635 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13636 }, 13637 outputs: []outputInfo{ 13638 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13639 }, 13640 }, 13641 }, 13642 { 13643 name: "MOVQatomicload", 13644 auxType: auxSymOff, 13645 argLen: 2, 13646 faultOnNilArg0: true, 13647 symEffect: SymRead, 13648 asm: x86.AMOVQ, 13649 reg: regInfo{ 13650 inputs: []inputInfo{ 13651 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13652 }, 13653 outputs: []outputInfo{ 13654 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13655 }, 13656 }, 13657 }, 13658 { 13659 name: "XCHGB", 13660 auxType: auxSymOff, 13661 argLen: 3, 13662 resultInArg0: true, 13663 faultOnNilArg1: true, 13664 hasSideEffects: true, 13665 symEffect: SymRdWr, 13666 asm: x86.AXCHGB, 13667 reg: regInfo{ 13668 inputs: []inputInfo{ 13669 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13670 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13671 }, 13672 outputs: []outputInfo{ 13673 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13674 }, 13675 }, 13676 }, 13677 { 13678 name: "XCHGL", 13679 auxType: auxSymOff, 13680 argLen: 3, 13681 resultInArg0: true, 13682 faultOnNilArg1: true, 13683 hasSideEffects: true, 13684 symEffect: SymRdWr, 13685 asm: x86.AXCHGL, 13686 reg: regInfo{ 13687 inputs: []inputInfo{ 13688 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13689 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13690 }, 13691 outputs: []outputInfo{ 13692 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13693 }, 13694 }, 13695 }, 13696 { 13697 name: "XCHGQ", 13698 auxType: auxSymOff, 13699 argLen: 3, 13700 resultInArg0: true, 13701 faultOnNilArg1: true, 13702 hasSideEffects: true, 13703 symEffect: SymRdWr, 13704 asm: x86.AXCHGQ, 13705 reg: regInfo{ 13706 inputs: []inputInfo{ 13707 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13708 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13709 }, 13710 outputs: []outputInfo{ 13711 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13712 }, 13713 }, 13714 }, 13715 { 13716 name: "XADDLlock", 13717 auxType: auxSymOff, 13718 argLen: 3, 13719 resultInArg0: true, 13720 clobberFlags: true, 13721 faultOnNilArg1: true, 13722 hasSideEffects: true, 13723 symEffect: SymRdWr, 13724 asm: x86.AXADDL, 13725 reg: regInfo{ 13726 inputs: []inputInfo{ 13727 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13728 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13729 }, 13730 outputs: []outputInfo{ 13731 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13732 }, 13733 }, 13734 }, 13735 { 13736 name: "XADDQlock", 13737 auxType: auxSymOff, 13738 argLen: 3, 13739 resultInArg0: true, 13740 clobberFlags: true, 13741 faultOnNilArg1: true, 13742 hasSideEffects: true, 13743 symEffect: SymRdWr, 13744 asm: x86.AXADDQ, 13745 reg: regInfo{ 13746 inputs: []inputInfo{ 13747 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13748 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13749 }, 13750 outputs: []outputInfo{ 13751 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13752 }, 13753 }, 13754 }, 13755 { 13756 name: "AddTupleFirst32", 13757 argLen: 2, 13758 reg: regInfo{}, 13759 }, 13760 { 13761 name: "AddTupleFirst64", 13762 argLen: 2, 13763 reg: regInfo{}, 13764 }, 13765 { 13766 name: "CMPXCHGLlock", 13767 auxType: auxSymOff, 13768 argLen: 4, 13769 clobberFlags: true, 13770 faultOnNilArg0: true, 13771 hasSideEffects: true, 13772 symEffect: SymRdWr, 13773 asm: x86.ACMPXCHGL, 13774 reg: regInfo{ 13775 inputs: []inputInfo{ 13776 {1, 1}, // AX 13777 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13778 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13779 }, 13780 clobbers: 1, // AX 13781 outputs: []outputInfo{ 13782 {1, 0}, 13783 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13784 }, 13785 }, 13786 }, 13787 { 13788 name: "CMPXCHGQlock", 13789 auxType: auxSymOff, 13790 argLen: 4, 13791 clobberFlags: true, 13792 faultOnNilArg0: true, 13793 hasSideEffects: true, 13794 symEffect: SymRdWr, 13795 asm: x86.ACMPXCHGQ, 13796 reg: regInfo{ 13797 inputs: []inputInfo{ 13798 {1, 1}, // AX 13799 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13800 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13801 }, 13802 clobbers: 1, // AX 13803 outputs: []outputInfo{ 13804 {1, 0}, 13805 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13806 }, 13807 }, 13808 }, 13809 { 13810 name: "ANDBlock", 13811 auxType: auxSymOff, 13812 argLen: 3, 13813 clobberFlags: true, 13814 faultOnNilArg0: true, 13815 hasSideEffects: true, 13816 symEffect: SymRdWr, 13817 asm: x86.AANDB, 13818 reg: regInfo{ 13819 inputs: []inputInfo{ 13820 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13821 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13822 }, 13823 }, 13824 }, 13825 { 13826 name: "ANDLlock", 13827 auxType: auxSymOff, 13828 argLen: 3, 13829 clobberFlags: true, 13830 faultOnNilArg0: true, 13831 hasSideEffects: true, 13832 symEffect: SymRdWr, 13833 asm: x86.AANDL, 13834 reg: regInfo{ 13835 inputs: []inputInfo{ 13836 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13837 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13838 }, 13839 }, 13840 }, 13841 { 13842 name: "ORBlock", 13843 auxType: auxSymOff, 13844 argLen: 3, 13845 clobberFlags: true, 13846 faultOnNilArg0: true, 13847 hasSideEffects: true, 13848 symEffect: SymRdWr, 13849 asm: x86.AORB, 13850 reg: regInfo{ 13851 inputs: []inputInfo{ 13852 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13853 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13854 }, 13855 }, 13856 }, 13857 { 13858 name: "ORLlock", 13859 auxType: auxSymOff, 13860 argLen: 3, 13861 clobberFlags: true, 13862 faultOnNilArg0: true, 13863 hasSideEffects: true, 13864 symEffect: SymRdWr, 13865 asm: x86.AORL, 13866 reg: regInfo{ 13867 inputs: []inputInfo{ 13868 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 13869 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13870 }, 13871 }, 13872 }, 13873 { 13874 name: "PrefetchT0", 13875 argLen: 2, 13876 hasSideEffects: true, 13877 asm: x86.APREFETCHT0, 13878 reg: regInfo{ 13879 inputs: []inputInfo{ 13880 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13881 }, 13882 }, 13883 }, 13884 { 13885 name: "PrefetchNTA", 13886 argLen: 2, 13887 hasSideEffects: true, 13888 asm: x86.APREFETCHNTA, 13889 reg: regInfo{ 13890 inputs: []inputInfo{ 13891 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 13892 }, 13893 }, 13894 }, 13895 { 13896 name: "ANDNQ", 13897 argLen: 2, 13898 clobberFlags: true, 13899 asm: x86.AANDNQ, 13900 reg: regInfo{ 13901 inputs: []inputInfo{ 13902 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13903 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13904 }, 13905 outputs: []outputInfo{ 13906 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13907 }, 13908 }, 13909 }, 13910 { 13911 name: "ANDNL", 13912 argLen: 2, 13913 clobberFlags: true, 13914 asm: x86.AANDNL, 13915 reg: regInfo{ 13916 inputs: []inputInfo{ 13917 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13918 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13919 }, 13920 outputs: []outputInfo{ 13921 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13922 }, 13923 }, 13924 }, 13925 { 13926 name: "BLSIQ", 13927 argLen: 1, 13928 clobberFlags: true, 13929 asm: x86.ABLSIQ, 13930 reg: regInfo{ 13931 inputs: []inputInfo{ 13932 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13933 }, 13934 outputs: []outputInfo{ 13935 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13936 }, 13937 }, 13938 }, 13939 { 13940 name: "BLSIL", 13941 argLen: 1, 13942 clobberFlags: true, 13943 asm: x86.ABLSIL, 13944 reg: regInfo{ 13945 inputs: []inputInfo{ 13946 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13947 }, 13948 outputs: []outputInfo{ 13949 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13950 }, 13951 }, 13952 }, 13953 { 13954 name: "BLSMSKQ", 13955 argLen: 1, 13956 clobberFlags: true, 13957 asm: x86.ABLSMSKQ, 13958 reg: regInfo{ 13959 inputs: []inputInfo{ 13960 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13961 }, 13962 outputs: []outputInfo{ 13963 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13964 }, 13965 }, 13966 }, 13967 { 13968 name: "BLSMSKL", 13969 argLen: 1, 13970 clobberFlags: true, 13971 asm: x86.ABLSMSKL, 13972 reg: regInfo{ 13973 inputs: []inputInfo{ 13974 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13975 }, 13976 outputs: []outputInfo{ 13977 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13978 }, 13979 }, 13980 }, 13981 { 13982 name: "BLSRQ", 13983 argLen: 1, 13984 clobberFlags: true, 13985 asm: x86.ABLSRQ, 13986 reg: regInfo{ 13987 inputs: []inputInfo{ 13988 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13989 }, 13990 outputs: []outputInfo{ 13991 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 13992 }, 13993 }, 13994 }, 13995 { 13996 name: "BLSRL", 13997 argLen: 1, 13998 clobberFlags: true, 13999 asm: x86.ABLSRL, 14000 reg: regInfo{ 14001 inputs: []inputInfo{ 14002 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14003 }, 14004 outputs: []outputInfo{ 14005 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14006 }, 14007 }, 14008 }, 14009 { 14010 name: "TZCNTQ", 14011 argLen: 1, 14012 clobberFlags: true, 14013 asm: x86.ATZCNTQ, 14014 reg: regInfo{ 14015 inputs: []inputInfo{ 14016 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14017 }, 14018 outputs: []outputInfo{ 14019 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14020 }, 14021 }, 14022 }, 14023 { 14024 name: "TZCNTL", 14025 argLen: 1, 14026 clobberFlags: true, 14027 asm: x86.ATZCNTL, 14028 reg: regInfo{ 14029 inputs: []inputInfo{ 14030 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14031 }, 14032 outputs: []outputInfo{ 14033 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14034 }, 14035 }, 14036 }, 14037 { 14038 name: "LZCNTQ", 14039 argLen: 1, 14040 clobberFlags: true, 14041 asm: x86.ALZCNTQ, 14042 reg: regInfo{ 14043 inputs: []inputInfo{ 14044 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14045 }, 14046 outputs: []outputInfo{ 14047 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14048 }, 14049 }, 14050 }, 14051 { 14052 name: "LZCNTL", 14053 argLen: 1, 14054 clobberFlags: true, 14055 asm: x86.ALZCNTL, 14056 reg: regInfo{ 14057 inputs: []inputInfo{ 14058 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14059 }, 14060 outputs: []outputInfo{ 14061 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14062 }, 14063 }, 14064 }, 14065 { 14066 name: "MOVBEWstore", 14067 auxType: auxSymOff, 14068 argLen: 3, 14069 faultOnNilArg0: true, 14070 symEffect: SymWrite, 14071 asm: x86.AMOVBEW, 14072 reg: regInfo{ 14073 inputs: []inputInfo{ 14074 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14075 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14076 }, 14077 }, 14078 }, 14079 { 14080 name: "MOVBELload", 14081 auxType: auxSymOff, 14082 argLen: 2, 14083 faultOnNilArg0: true, 14084 symEffect: SymRead, 14085 asm: x86.AMOVBEL, 14086 reg: regInfo{ 14087 inputs: []inputInfo{ 14088 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14089 }, 14090 outputs: []outputInfo{ 14091 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14092 }, 14093 }, 14094 }, 14095 { 14096 name: "MOVBELstore", 14097 auxType: auxSymOff, 14098 argLen: 3, 14099 faultOnNilArg0: true, 14100 symEffect: SymWrite, 14101 asm: x86.AMOVBEL, 14102 reg: regInfo{ 14103 inputs: []inputInfo{ 14104 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14105 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14106 }, 14107 }, 14108 }, 14109 { 14110 name: "MOVBEQload", 14111 auxType: auxSymOff, 14112 argLen: 2, 14113 faultOnNilArg0: true, 14114 symEffect: SymRead, 14115 asm: x86.AMOVBEQ, 14116 reg: regInfo{ 14117 inputs: []inputInfo{ 14118 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14119 }, 14120 outputs: []outputInfo{ 14121 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14122 }, 14123 }, 14124 }, 14125 { 14126 name: "MOVBEQstore", 14127 auxType: auxSymOff, 14128 argLen: 3, 14129 faultOnNilArg0: true, 14130 symEffect: SymWrite, 14131 asm: x86.AMOVBEQ, 14132 reg: regInfo{ 14133 inputs: []inputInfo{ 14134 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14135 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14136 }, 14137 }, 14138 }, 14139 { 14140 name: "MOVBELloadidx1", 14141 auxType: auxSymOff, 14142 argLen: 3, 14143 commutative: true, 14144 symEffect: SymRead, 14145 asm: x86.AMOVBEL, 14146 scale: 1, 14147 reg: regInfo{ 14148 inputs: []inputInfo{ 14149 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14150 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14151 }, 14152 outputs: []outputInfo{ 14153 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14154 }, 14155 }, 14156 }, 14157 { 14158 name: "MOVBELloadidx4", 14159 auxType: auxSymOff, 14160 argLen: 3, 14161 symEffect: SymRead, 14162 asm: x86.AMOVBEL, 14163 scale: 4, 14164 reg: regInfo{ 14165 inputs: []inputInfo{ 14166 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14167 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14168 }, 14169 outputs: []outputInfo{ 14170 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14171 }, 14172 }, 14173 }, 14174 { 14175 name: "MOVBELloadidx8", 14176 auxType: auxSymOff, 14177 argLen: 3, 14178 symEffect: SymRead, 14179 asm: x86.AMOVBEL, 14180 scale: 8, 14181 reg: regInfo{ 14182 inputs: []inputInfo{ 14183 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14184 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14185 }, 14186 outputs: []outputInfo{ 14187 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14188 }, 14189 }, 14190 }, 14191 { 14192 name: "MOVBEQloadidx1", 14193 auxType: auxSymOff, 14194 argLen: 3, 14195 commutative: true, 14196 symEffect: SymRead, 14197 asm: x86.AMOVBEQ, 14198 scale: 1, 14199 reg: regInfo{ 14200 inputs: []inputInfo{ 14201 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14202 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14203 }, 14204 outputs: []outputInfo{ 14205 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14206 }, 14207 }, 14208 }, 14209 { 14210 name: "MOVBEQloadidx8", 14211 auxType: auxSymOff, 14212 argLen: 3, 14213 symEffect: SymRead, 14214 asm: x86.AMOVBEQ, 14215 scale: 8, 14216 reg: regInfo{ 14217 inputs: []inputInfo{ 14218 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14219 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14220 }, 14221 outputs: []outputInfo{ 14222 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14223 }, 14224 }, 14225 }, 14226 { 14227 name: "MOVBEWstoreidx1", 14228 auxType: auxSymOff, 14229 argLen: 4, 14230 commutative: true, 14231 symEffect: SymWrite, 14232 asm: x86.AMOVBEW, 14233 scale: 1, 14234 reg: regInfo{ 14235 inputs: []inputInfo{ 14236 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14237 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14238 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14239 }, 14240 }, 14241 }, 14242 { 14243 name: "MOVBEWstoreidx2", 14244 auxType: auxSymOff, 14245 argLen: 4, 14246 symEffect: SymWrite, 14247 asm: x86.AMOVBEW, 14248 scale: 2, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14252 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14253 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14254 }, 14255 }, 14256 }, 14257 { 14258 name: "MOVBELstoreidx1", 14259 auxType: auxSymOff, 14260 argLen: 4, 14261 commutative: true, 14262 symEffect: SymWrite, 14263 asm: x86.AMOVBEL, 14264 scale: 1, 14265 reg: regInfo{ 14266 inputs: []inputInfo{ 14267 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14268 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14269 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14270 }, 14271 }, 14272 }, 14273 { 14274 name: "MOVBELstoreidx4", 14275 auxType: auxSymOff, 14276 argLen: 4, 14277 symEffect: SymWrite, 14278 asm: x86.AMOVBEL, 14279 scale: 4, 14280 reg: regInfo{ 14281 inputs: []inputInfo{ 14282 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14283 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14284 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14285 }, 14286 }, 14287 }, 14288 { 14289 name: "MOVBELstoreidx8", 14290 auxType: auxSymOff, 14291 argLen: 4, 14292 symEffect: SymWrite, 14293 asm: x86.AMOVBEL, 14294 scale: 8, 14295 reg: regInfo{ 14296 inputs: []inputInfo{ 14297 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14298 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14299 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14300 }, 14301 }, 14302 }, 14303 { 14304 name: "MOVBEQstoreidx1", 14305 auxType: auxSymOff, 14306 argLen: 4, 14307 commutative: true, 14308 symEffect: SymWrite, 14309 asm: x86.AMOVBEQ, 14310 scale: 1, 14311 reg: regInfo{ 14312 inputs: []inputInfo{ 14313 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14314 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14315 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14316 }, 14317 }, 14318 }, 14319 { 14320 name: "MOVBEQstoreidx8", 14321 auxType: auxSymOff, 14322 argLen: 4, 14323 symEffect: SymWrite, 14324 asm: x86.AMOVBEQ, 14325 scale: 8, 14326 reg: regInfo{ 14327 inputs: []inputInfo{ 14328 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14329 {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14330 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14331 }, 14332 }, 14333 }, 14334 { 14335 name: "SARXQ", 14336 argLen: 2, 14337 asm: x86.ASARXQ, 14338 reg: regInfo{ 14339 inputs: []inputInfo{ 14340 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14341 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14342 }, 14343 outputs: []outputInfo{ 14344 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14345 }, 14346 }, 14347 }, 14348 { 14349 name: "SARXL", 14350 argLen: 2, 14351 asm: x86.ASARXL, 14352 reg: regInfo{ 14353 inputs: []inputInfo{ 14354 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14355 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14356 }, 14357 outputs: []outputInfo{ 14358 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14359 }, 14360 }, 14361 }, 14362 { 14363 name: "SHLXQ", 14364 argLen: 2, 14365 asm: x86.ASHLXQ, 14366 reg: regInfo{ 14367 inputs: []inputInfo{ 14368 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14369 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14370 }, 14371 outputs: []outputInfo{ 14372 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14373 }, 14374 }, 14375 }, 14376 { 14377 name: "SHLXL", 14378 argLen: 2, 14379 asm: x86.ASHLXL, 14380 reg: regInfo{ 14381 inputs: []inputInfo{ 14382 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14383 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14384 }, 14385 outputs: []outputInfo{ 14386 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14387 }, 14388 }, 14389 }, 14390 { 14391 name: "SHRXQ", 14392 argLen: 2, 14393 asm: x86.ASHRXQ, 14394 reg: regInfo{ 14395 inputs: []inputInfo{ 14396 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14397 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14398 }, 14399 outputs: []outputInfo{ 14400 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14401 }, 14402 }, 14403 }, 14404 { 14405 name: "SHRXL", 14406 argLen: 2, 14407 asm: x86.ASHRXL, 14408 reg: regInfo{ 14409 inputs: []inputInfo{ 14410 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14411 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14412 }, 14413 outputs: []outputInfo{ 14414 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14415 }, 14416 }, 14417 }, 14418 { 14419 name: "SARXLload", 14420 auxType: auxSymOff, 14421 argLen: 3, 14422 faultOnNilArg0: true, 14423 symEffect: SymRead, 14424 asm: x86.ASARXL, 14425 reg: regInfo{ 14426 inputs: []inputInfo{ 14427 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14428 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14429 }, 14430 outputs: []outputInfo{ 14431 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14432 }, 14433 }, 14434 }, 14435 { 14436 name: "SARXQload", 14437 auxType: auxSymOff, 14438 argLen: 3, 14439 faultOnNilArg0: true, 14440 symEffect: SymRead, 14441 asm: x86.ASARXQ, 14442 reg: regInfo{ 14443 inputs: []inputInfo{ 14444 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14445 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14446 }, 14447 outputs: []outputInfo{ 14448 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14449 }, 14450 }, 14451 }, 14452 { 14453 name: "SHLXLload", 14454 auxType: auxSymOff, 14455 argLen: 3, 14456 faultOnNilArg0: true, 14457 symEffect: SymRead, 14458 asm: x86.ASHLXL, 14459 reg: regInfo{ 14460 inputs: []inputInfo{ 14461 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14462 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14463 }, 14464 outputs: []outputInfo{ 14465 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14466 }, 14467 }, 14468 }, 14469 { 14470 name: "SHLXQload", 14471 auxType: auxSymOff, 14472 argLen: 3, 14473 faultOnNilArg0: true, 14474 symEffect: SymRead, 14475 asm: x86.ASHLXQ, 14476 reg: regInfo{ 14477 inputs: []inputInfo{ 14478 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14479 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14480 }, 14481 outputs: []outputInfo{ 14482 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14483 }, 14484 }, 14485 }, 14486 { 14487 name: "SHRXLload", 14488 auxType: auxSymOff, 14489 argLen: 3, 14490 faultOnNilArg0: true, 14491 symEffect: SymRead, 14492 asm: x86.ASHRXL, 14493 reg: regInfo{ 14494 inputs: []inputInfo{ 14495 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14496 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14497 }, 14498 outputs: []outputInfo{ 14499 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14500 }, 14501 }, 14502 }, 14503 { 14504 name: "SHRXQload", 14505 auxType: auxSymOff, 14506 argLen: 3, 14507 faultOnNilArg0: true, 14508 symEffect: SymRead, 14509 asm: x86.ASHRXQ, 14510 reg: regInfo{ 14511 inputs: []inputInfo{ 14512 {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14513 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14514 }, 14515 outputs: []outputInfo{ 14516 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14517 }, 14518 }, 14519 }, 14520 { 14521 name: "SARXLloadidx1", 14522 auxType: auxSymOff, 14523 argLen: 4, 14524 faultOnNilArg0: true, 14525 symEffect: SymRead, 14526 asm: x86.ASARXL, 14527 scale: 1, 14528 reg: regInfo{ 14529 inputs: []inputInfo{ 14530 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14531 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14532 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14533 }, 14534 outputs: []outputInfo{ 14535 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14536 }, 14537 }, 14538 }, 14539 { 14540 name: "SARXLloadidx4", 14541 auxType: auxSymOff, 14542 argLen: 4, 14543 faultOnNilArg0: true, 14544 symEffect: SymRead, 14545 asm: x86.ASARXL, 14546 scale: 4, 14547 reg: regInfo{ 14548 inputs: []inputInfo{ 14549 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14550 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14551 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14552 }, 14553 outputs: []outputInfo{ 14554 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14555 }, 14556 }, 14557 }, 14558 { 14559 name: "SARXLloadidx8", 14560 auxType: auxSymOff, 14561 argLen: 4, 14562 faultOnNilArg0: true, 14563 symEffect: SymRead, 14564 asm: x86.ASARXL, 14565 scale: 8, 14566 reg: regInfo{ 14567 inputs: []inputInfo{ 14568 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14569 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14570 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14571 }, 14572 outputs: []outputInfo{ 14573 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14574 }, 14575 }, 14576 }, 14577 { 14578 name: "SARXQloadidx1", 14579 auxType: auxSymOff, 14580 argLen: 4, 14581 faultOnNilArg0: true, 14582 symEffect: SymRead, 14583 asm: x86.ASARXQ, 14584 scale: 1, 14585 reg: regInfo{ 14586 inputs: []inputInfo{ 14587 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14588 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14589 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14590 }, 14591 outputs: []outputInfo{ 14592 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14593 }, 14594 }, 14595 }, 14596 { 14597 name: "SARXQloadidx8", 14598 auxType: auxSymOff, 14599 argLen: 4, 14600 faultOnNilArg0: true, 14601 symEffect: SymRead, 14602 asm: x86.ASARXQ, 14603 scale: 8, 14604 reg: regInfo{ 14605 inputs: []inputInfo{ 14606 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14607 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14608 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14609 }, 14610 outputs: []outputInfo{ 14611 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14612 }, 14613 }, 14614 }, 14615 { 14616 name: "SHLXLloadidx1", 14617 auxType: auxSymOff, 14618 argLen: 4, 14619 faultOnNilArg0: true, 14620 symEffect: SymRead, 14621 asm: x86.ASHLXL, 14622 scale: 1, 14623 reg: regInfo{ 14624 inputs: []inputInfo{ 14625 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14626 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14627 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14628 }, 14629 outputs: []outputInfo{ 14630 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14631 }, 14632 }, 14633 }, 14634 { 14635 name: "SHLXLloadidx4", 14636 auxType: auxSymOff, 14637 argLen: 4, 14638 faultOnNilArg0: true, 14639 symEffect: SymRead, 14640 asm: x86.ASHLXL, 14641 scale: 4, 14642 reg: regInfo{ 14643 inputs: []inputInfo{ 14644 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14645 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14646 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14647 }, 14648 outputs: []outputInfo{ 14649 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14650 }, 14651 }, 14652 }, 14653 { 14654 name: "SHLXLloadidx8", 14655 auxType: auxSymOff, 14656 argLen: 4, 14657 faultOnNilArg0: true, 14658 symEffect: SymRead, 14659 asm: x86.ASHLXL, 14660 scale: 8, 14661 reg: regInfo{ 14662 inputs: []inputInfo{ 14663 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14664 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14665 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14666 }, 14667 outputs: []outputInfo{ 14668 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14669 }, 14670 }, 14671 }, 14672 { 14673 name: "SHLXQloadidx1", 14674 auxType: auxSymOff, 14675 argLen: 4, 14676 faultOnNilArg0: true, 14677 symEffect: SymRead, 14678 asm: x86.ASHLXQ, 14679 scale: 1, 14680 reg: regInfo{ 14681 inputs: []inputInfo{ 14682 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14683 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14684 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14685 }, 14686 outputs: []outputInfo{ 14687 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14688 }, 14689 }, 14690 }, 14691 { 14692 name: "SHLXQloadidx8", 14693 auxType: auxSymOff, 14694 argLen: 4, 14695 faultOnNilArg0: true, 14696 symEffect: SymRead, 14697 asm: x86.ASHLXQ, 14698 scale: 8, 14699 reg: regInfo{ 14700 inputs: []inputInfo{ 14701 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14702 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14703 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14704 }, 14705 outputs: []outputInfo{ 14706 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14707 }, 14708 }, 14709 }, 14710 { 14711 name: "SHRXLloadidx1", 14712 auxType: auxSymOff, 14713 argLen: 4, 14714 faultOnNilArg0: true, 14715 symEffect: SymRead, 14716 asm: x86.ASHRXL, 14717 scale: 1, 14718 reg: regInfo{ 14719 inputs: []inputInfo{ 14720 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14721 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14722 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14723 }, 14724 outputs: []outputInfo{ 14725 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14726 }, 14727 }, 14728 }, 14729 { 14730 name: "SHRXLloadidx4", 14731 auxType: auxSymOff, 14732 argLen: 4, 14733 faultOnNilArg0: true, 14734 symEffect: SymRead, 14735 asm: x86.ASHRXL, 14736 scale: 4, 14737 reg: regInfo{ 14738 inputs: []inputInfo{ 14739 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14740 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14741 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14742 }, 14743 outputs: []outputInfo{ 14744 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14745 }, 14746 }, 14747 }, 14748 { 14749 name: "SHRXLloadidx8", 14750 auxType: auxSymOff, 14751 argLen: 4, 14752 faultOnNilArg0: true, 14753 symEffect: SymRead, 14754 asm: x86.ASHRXL, 14755 scale: 8, 14756 reg: regInfo{ 14757 inputs: []inputInfo{ 14758 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14759 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14760 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14761 }, 14762 outputs: []outputInfo{ 14763 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14764 }, 14765 }, 14766 }, 14767 { 14768 name: "SHRXQloadidx1", 14769 auxType: auxSymOff, 14770 argLen: 4, 14771 faultOnNilArg0: true, 14772 symEffect: SymRead, 14773 asm: x86.ASHRXQ, 14774 scale: 1, 14775 reg: regInfo{ 14776 inputs: []inputInfo{ 14777 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14778 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14779 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14780 }, 14781 outputs: []outputInfo{ 14782 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14783 }, 14784 }, 14785 }, 14786 { 14787 name: "SHRXQloadidx8", 14788 auxType: auxSymOff, 14789 argLen: 4, 14790 faultOnNilArg0: true, 14791 symEffect: SymRead, 14792 asm: x86.ASHRXQ, 14793 scale: 8, 14794 reg: regInfo{ 14795 inputs: []inputInfo{ 14796 {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14797 {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 14798 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB 14799 }, 14800 outputs: []outputInfo{ 14801 {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 14802 }, 14803 }, 14804 }, 14805 14806 { 14807 name: "ADD", 14808 argLen: 2, 14809 commutative: true, 14810 asm: arm.AADD, 14811 reg: regInfo{ 14812 inputs: []inputInfo{ 14813 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14814 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14815 }, 14816 outputs: []outputInfo{ 14817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14818 }, 14819 }, 14820 }, 14821 { 14822 name: "ADDconst", 14823 auxType: auxInt32, 14824 argLen: 1, 14825 asm: arm.AADD, 14826 reg: regInfo{ 14827 inputs: []inputInfo{ 14828 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 14829 }, 14830 outputs: []outputInfo{ 14831 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14832 }, 14833 }, 14834 }, 14835 { 14836 name: "SUB", 14837 argLen: 2, 14838 asm: arm.ASUB, 14839 reg: regInfo{ 14840 inputs: []inputInfo{ 14841 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14842 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14843 }, 14844 outputs: []outputInfo{ 14845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14846 }, 14847 }, 14848 }, 14849 { 14850 name: "SUBconst", 14851 auxType: auxInt32, 14852 argLen: 1, 14853 asm: arm.ASUB, 14854 reg: regInfo{ 14855 inputs: []inputInfo{ 14856 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14857 }, 14858 outputs: []outputInfo{ 14859 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14860 }, 14861 }, 14862 }, 14863 { 14864 name: "RSB", 14865 argLen: 2, 14866 asm: arm.ARSB, 14867 reg: regInfo{ 14868 inputs: []inputInfo{ 14869 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14870 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14871 }, 14872 outputs: []outputInfo{ 14873 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14874 }, 14875 }, 14876 }, 14877 { 14878 name: "RSBconst", 14879 auxType: auxInt32, 14880 argLen: 1, 14881 asm: arm.ARSB, 14882 reg: regInfo{ 14883 inputs: []inputInfo{ 14884 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14885 }, 14886 outputs: []outputInfo{ 14887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14888 }, 14889 }, 14890 }, 14891 { 14892 name: "MUL", 14893 argLen: 2, 14894 commutative: true, 14895 asm: arm.AMUL, 14896 reg: regInfo{ 14897 inputs: []inputInfo{ 14898 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14899 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14900 }, 14901 outputs: []outputInfo{ 14902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14903 }, 14904 }, 14905 }, 14906 { 14907 name: "HMUL", 14908 argLen: 2, 14909 commutative: true, 14910 asm: arm.AMULL, 14911 reg: regInfo{ 14912 inputs: []inputInfo{ 14913 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14914 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14915 }, 14916 outputs: []outputInfo{ 14917 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14918 }, 14919 }, 14920 }, 14921 { 14922 name: "HMULU", 14923 argLen: 2, 14924 commutative: true, 14925 asm: arm.AMULLU, 14926 reg: regInfo{ 14927 inputs: []inputInfo{ 14928 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14929 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14930 }, 14931 outputs: []outputInfo{ 14932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14933 }, 14934 }, 14935 }, 14936 { 14937 name: "CALLudiv", 14938 argLen: 2, 14939 clobberFlags: true, 14940 reg: regInfo{ 14941 inputs: []inputInfo{ 14942 {0, 2}, // R1 14943 {1, 1}, // R0 14944 }, 14945 clobbers: 20492, // R2 R3 R12 R14 14946 outputs: []outputInfo{ 14947 {0, 1}, // R0 14948 {1, 2}, // R1 14949 }, 14950 }, 14951 }, 14952 { 14953 name: "ADDS", 14954 argLen: 2, 14955 commutative: true, 14956 asm: arm.AADD, 14957 reg: regInfo{ 14958 inputs: []inputInfo{ 14959 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14960 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14961 }, 14962 outputs: []outputInfo{ 14963 {1, 0}, 14964 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14965 }, 14966 }, 14967 }, 14968 { 14969 name: "ADDSconst", 14970 auxType: auxInt32, 14971 argLen: 1, 14972 asm: arm.AADD, 14973 reg: regInfo{ 14974 inputs: []inputInfo{ 14975 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 14976 }, 14977 outputs: []outputInfo{ 14978 {1, 0}, 14979 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14980 }, 14981 }, 14982 }, 14983 { 14984 name: "ADC", 14985 argLen: 3, 14986 commutative: true, 14987 asm: arm.AADC, 14988 reg: regInfo{ 14989 inputs: []inputInfo{ 14990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14991 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14992 }, 14993 outputs: []outputInfo{ 14994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 14995 }, 14996 }, 14997 }, 14998 { 14999 name: "ADCconst", 15000 auxType: auxInt32, 15001 argLen: 2, 15002 asm: arm.AADC, 15003 reg: regInfo{ 15004 inputs: []inputInfo{ 15005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15006 }, 15007 outputs: []outputInfo{ 15008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15009 }, 15010 }, 15011 }, 15012 { 15013 name: "SUBS", 15014 argLen: 2, 15015 asm: arm.ASUB, 15016 reg: regInfo{ 15017 inputs: []inputInfo{ 15018 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15019 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15020 }, 15021 outputs: []outputInfo{ 15022 {1, 0}, 15023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15024 }, 15025 }, 15026 }, 15027 { 15028 name: "SUBSconst", 15029 auxType: auxInt32, 15030 argLen: 1, 15031 asm: arm.ASUB, 15032 reg: regInfo{ 15033 inputs: []inputInfo{ 15034 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15035 }, 15036 outputs: []outputInfo{ 15037 {1, 0}, 15038 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15039 }, 15040 }, 15041 }, 15042 { 15043 name: "RSBSconst", 15044 auxType: auxInt32, 15045 argLen: 1, 15046 asm: arm.ARSB, 15047 reg: regInfo{ 15048 inputs: []inputInfo{ 15049 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15050 }, 15051 outputs: []outputInfo{ 15052 {1, 0}, 15053 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15054 }, 15055 }, 15056 }, 15057 { 15058 name: "SBC", 15059 argLen: 3, 15060 asm: arm.ASBC, 15061 reg: regInfo{ 15062 inputs: []inputInfo{ 15063 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15064 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15065 }, 15066 outputs: []outputInfo{ 15067 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15068 }, 15069 }, 15070 }, 15071 { 15072 name: "SBCconst", 15073 auxType: auxInt32, 15074 argLen: 2, 15075 asm: arm.ASBC, 15076 reg: regInfo{ 15077 inputs: []inputInfo{ 15078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15079 }, 15080 outputs: []outputInfo{ 15081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15082 }, 15083 }, 15084 }, 15085 { 15086 name: "RSCconst", 15087 auxType: auxInt32, 15088 argLen: 2, 15089 asm: arm.ARSC, 15090 reg: regInfo{ 15091 inputs: []inputInfo{ 15092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15093 }, 15094 outputs: []outputInfo{ 15095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15096 }, 15097 }, 15098 }, 15099 { 15100 name: "MULLU", 15101 argLen: 2, 15102 commutative: true, 15103 asm: arm.AMULLU, 15104 reg: regInfo{ 15105 inputs: []inputInfo{ 15106 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15107 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15108 }, 15109 outputs: []outputInfo{ 15110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15111 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15112 }, 15113 }, 15114 }, 15115 { 15116 name: "MULA", 15117 argLen: 3, 15118 asm: arm.AMULA, 15119 reg: regInfo{ 15120 inputs: []inputInfo{ 15121 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15122 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15123 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15124 }, 15125 outputs: []outputInfo{ 15126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15127 }, 15128 }, 15129 }, 15130 { 15131 name: "MULS", 15132 argLen: 3, 15133 asm: arm.AMULS, 15134 reg: regInfo{ 15135 inputs: []inputInfo{ 15136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15137 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15138 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15139 }, 15140 outputs: []outputInfo{ 15141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15142 }, 15143 }, 15144 }, 15145 { 15146 name: "ADDF", 15147 argLen: 2, 15148 commutative: true, 15149 asm: arm.AADDF, 15150 reg: regInfo{ 15151 inputs: []inputInfo{ 15152 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15153 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15154 }, 15155 outputs: []outputInfo{ 15156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15157 }, 15158 }, 15159 }, 15160 { 15161 name: "ADDD", 15162 argLen: 2, 15163 commutative: true, 15164 asm: arm.AADDD, 15165 reg: regInfo{ 15166 inputs: []inputInfo{ 15167 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15168 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15169 }, 15170 outputs: []outputInfo{ 15171 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15172 }, 15173 }, 15174 }, 15175 { 15176 name: "SUBF", 15177 argLen: 2, 15178 asm: arm.ASUBF, 15179 reg: regInfo{ 15180 inputs: []inputInfo{ 15181 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15182 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15183 }, 15184 outputs: []outputInfo{ 15185 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15186 }, 15187 }, 15188 }, 15189 { 15190 name: "SUBD", 15191 argLen: 2, 15192 asm: arm.ASUBD, 15193 reg: regInfo{ 15194 inputs: []inputInfo{ 15195 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15196 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15197 }, 15198 outputs: []outputInfo{ 15199 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15200 }, 15201 }, 15202 }, 15203 { 15204 name: "MULF", 15205 argLen: 2, 15206 commutative: true, 15207 asm: arm.AMULF, 15208 reg: regInfo{ 15209 inputs: []inputInfo{ 15210 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15211 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15212 }, 15213 outputs: []outputInfo{ 15214 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15215 }, 15216 }, 15217 }, 15218 { 15219 name: "MULD", 15220 argLen: 2, 15221 commutative: true, 15222 asm: arm.AMULD, 15223 reg: regInfo{ 15224 inputs: []inputInfo{ 15225 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15226 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15227 }, 15228 outputs: []outputInfo{ 15229 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15230 }, 15231 }, 15232 }, 15233 { 15234 name: "NMULF", 15235 argLen: 2, 15236 commutative: true, 15237 asm: arm.ANMULF, 15238 reg: regInfo{ 15239 inputs: []inputInfo{ 15240 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15241 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15242 }, 15243 outputs: []outputInfo{ 15244 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15245 }, 15246 }, 15247 }, 15248 { 15249 name: "NMULD", 15250 argLen: 2, 15251 commutative: true, 15252 asm: arm.ANMULD, 15253 reg: regInfo{ 15254 inputs: []inputInfo{ 15255 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15256 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15257 }, 15258 outputs: []outputInfo{ 15259 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15260 }, 15261 }, 15262 }, 15263 { 15264 name: "DIVF", 15265 argLen: 2, 15266 asm: arm.ADIVF, 15267 reg: regInfo{ 15268 inputs: []inputInfo{ 15269 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15270 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15271 }, 15272 outputs: []outputInfo{ 15273 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15274 }, 15275 }, 15276 }, 15277 { 15278 name: "DIVD", 15279 argLen: 2, 15280 asm: arm.ADIVD, 15281 reg: regInfo{ 15282 inputs: []inputInfo{ 15283 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15284 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15285 }, 15286 outputs: []outputInfo{ 15287 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15288 }, 15289 }, 15290 }, 15291 { 15292 name: "MULAF", 15293 argLen: 3, 15294 resultInArg0: true, 15295 asm: arm.AMULAF, 15296 reg: regInfo{ 15297 inputs: []inputInfo{ 15298 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15299 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15300 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15301 }, 15302 outputs: []outputInfo{ 15303 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15304 }, 15305 }, 15306 }, 15307 { 15308 name: "MULAD", 15309 argLen: 3, 15310 resultInArg0: true, 15311 asm: arm.AMULAD, 15312 reg: regInfo{ 15313 inputs: []inputInfo{ 15314 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15315 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15316 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15317 }, 15318 outputs: []outputInfo{ 15319 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15320 }, 15321 }, 15322 }, 15323 { 15324 name: "MULSF", 15325 argLen: 3, 15326 resultInArg0: true, 15327 asm: arm.AMULSF, 15328 reg: regInfo{ 15329 inputs: []inputInfo{ 15330 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15331 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15332 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15333 }, 15334 outputs: []outputInfo{ 15335 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15336 }, 15337 }, 15338 }, 15339 { 15340 name: "MULSD", 15341 argLen: 3, 15342 resultInArg0: true, 15343 asm: arm.AMULSD, 15344 reg: regInfo{ 15345 inputs: []inputInfo{ 15346 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15347 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15348 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15349 }, 15350 outputs: []outputInfo{ 15351 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15352 }, 15353 }, 15354 }, 15355 { 15356 name: "FMULAD", 15357 argLen: 3, 15358 resultInArg0: true, 15359 asm: arm.AFMULAD, 15360 reg: regInfo{ 15361 inputs: []inputInfo{ 15362 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15363 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15364 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15365 }, 15366 outputs: []outputInfo{ 15367 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15368 }, 15369 }, 15370 }, 15371 { 15372 name: "AND", 15373 argLen: 2, 15374 commutative: true, 15375 asm: arm.AAND, 15376 reg: regInfo{ 15377 inputs: []inputInfo{ 15378 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15379 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15380 }, 15381 outputs: []outputInfo{ 15382 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15383 }, 15384 }, 15385 }, 15386 { 15387 name: "ANDconst", 15388 auxType: auxInt32, 15389 argLen: 1, 15390 asm: arm.AAND, 15391 reg: regInfo{ 15392 inputs: []inputInfo{ 15393 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15394 }, 15395 outputs: []outputInfo{ 15396 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15397 }, 15398 }, 15399 }, 15400 { 15401 name: "OR", 15402 argLen: 2, 15403 commutative: true, 15404 asm: arm.AORR, 15405 reg: regInfo{ 15406 inputs: []inputInfo{ 15407 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15408 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15409 }, 15410 outputs: []outputInfo{ 15411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15412 }, 15413 }, 15414 }, 15415 { 15416 name: "ORconst", 15417 auxType: auxInt32, 15418 argLen: 1, 15419 asm: arm.AORR, 15420 reg: regInfo{ 15421 inputs: []inputInfo{ 15422 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15423 }, 15424 outputs: []outputInfo{ 15425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15426 }, 15427 }, 15428 }, 15429 { 15430 name: "XOR", 15431 argLen: 2, 15432 commutative: true, 15433 asm: arm.AEOR, 15434 reg: regInfo{ 15435 inputs: []inputInfo{ 15436 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15437 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15438 }, 15439 outputs: []outputInfo{ 15440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15441 }, 15442 }, 15443 }, 15444 { 15445 name: "XORconst", 15446 auxType: auxInt32, 15447 argLen: 1, 15448 asm: arm.AEOR, 15449 reg: regInfo{ 15450 inputs: []inputInfo{ 15451 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15452 }, 15453 outputs: []outputInfo{ 15454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15455 }, 15456 }, 15457 }, 15458 { 15459 name: "BIC", 15460 argLen: 2, 15461 asm: arm.ABIC, 15462 reg: regInfo{ 15463 inputs: []inputInfo{ 15464 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15465 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15466 }, 15467 outputs: []outputInfo{ 15468 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15469 }, 15470 }, 15471 }, 15472 { 15473 name: "BICconst", 15474 auxType: auxInt32, 15475 argLen: 1, 15476 asm: arm.ABIC, 15477 reg: regInfo{ 15478 inputs: []inputInfo{ 15479 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15480 }, 15481 outputs: []outputInfo{ 15482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15483 }, 15484 }, 15485 }, 15486 { 15487 name: "BFX", 15488 auxType: auxInt32, 15489 argLen: 1, 15490 asm: arm.ABFX, 15491 reg: regInfo{ 15492 inputs: []inputInfo{ 15493 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15494 }, 15495 outputs: []outputInfo{ 15496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15497 }, 15498 }, 15499 }, 15500 { 15501 name: "BFXU", 15502 auxType: auxInt32, 15503 argLen: 1, 15504 asm: arm.ABFXU, 15505 reg: regInfo{ 15506 inputs: []inputInfo{ 15507 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15508 }, 15509 outputs: []outputInfo{ 15510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15511 }, 15512 }, 15513 }, 15514 { 15515 name: "MVN", 15516 argLen: 1, 15517 asm: arm.AMVN, 15518 reg: regInfo{ 15519 inputs: []inputInfo{ 15520 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15521 }, 15522 outputs: []outputInfo{ 15523 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15524 }, 15525 }, 15526 }, 15527 { 15528 name: "NEGF", 15529 argLen: 1, 15530 asm: arm.ANEGF, 15531 reg: regInfo{ 15532 inputs: []inputInfo{ 15533 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15534 }, 15535 outputs: []outputInfo{ 15536 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15537 }, 15538 }, 15539 }, 15540 { 15541 name: "NEGD", 15542 argLen: 1, 15543 asm: arm.ANEGD, 15544 reg: regInfo{ 15545 inputs: []inputInfo{ 15546 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15547 }, 15548 outputs: []outputInfo{ 15549 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15550 }, 15551 }, 15552 }, 15553 { 15554 name: "SQRTD", 15555 argLen: 1, 15556 asm: arm.ASQRTD, 15557 reg: regInfo{ 15558 inputs: []inputInfo{ 15559 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15560 }, 15561 outputs: []outputInfo{ 15562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15563 }, 15564 }, 15565 }, 15566 { 15567 name: "SQRTF", 15568 argLen: 1, 15569 asm: arm.ASQRTF, 15570 reg: regInfo{ 15571 inputs: []inputInfo{ 15572 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15573 }, 15574 outputs: []outputInfo{ 15575 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15576 }, 15577 }, 15578 }, 15579 { 15580 name: "ABSD", 15581 argLen: 1, 15582 asm: arm.AABSD, 15583 reg: regInfo{ 15584 inputs: []inputInfo{ 15585 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15586 }, 15587 outputs: []outputInfo{ 15588 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 15589 }, 15590 }, 15591 }, 15592 { 15593 name: "CLZ", 15594 argLen: 1, 15595 asm: arm.ACLZ, 15596 reg: regInfo{ 15597 inputs: []inputInfo{ 15598 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15599 }, 15600 outputs: []outputInfo{ 15601 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15602 }, 15603 }, 15604 }, 15605 { 15606 name: "REV", 15607 argLen: 1, 15608 asm: arm.AREV, 15609 reg: regInfo{ 15610 inputs: []inputInfo{ 15611 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15612 }, 15613 outputs: []outputInfo{ 15614 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15615 }, 15616 }, 15617 }, 15618 { 15619 name: "REV16", 15620 argLen: 1, 15621 asm: arm.AREV16, 15622 reg: regInfo{ 15623 inputs: []inputInfo{ 15624 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15625 }, 15626 outputs: []outputInfo{ 15627 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15628 }, 15629 }, 15630 }, 15631 { 15632 name: "RBIT", 15633 argLen: 1, 15634 asm: arm.ARBIT, 15635 reg: regInfo{ 15636 inputs: []inputInfo{ 15637 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15638 }, 15639 outputs: []outputInfo{ 15640 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15641 }, 15642 }, 15643 }, 15644 { 15645 name: "SLL", 15646 argLen: 2, 15647 asm: arm.ASLL, 15648 reg: regInfo{ 15649 inputs: []inputInfo{ 15650 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15651 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15652 }, 15653 outputs: []outputInfo{ 15654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15655 }, 15656 }, 15657 }, 15658 { 15659 name: "SLLconst", 15660 auxType: auxInt32, 15661 argLen: 1, 15662 asm: arm.ASLL, 15663 reg: regInfo{ 15664 inputs: []inputInfo{ 15665 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15666 }, 15667 outputs: []outputInfo{ 15668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15669 }, 15670 }, 15671 }, 15672 { 15673 name: "SRL", 15674 argLen: 2, 15675 asm: arm.ASRL, 15676 reg: regInfo{ 15677 inputs: []inputInfo{ 15678 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15679 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15680 }, 15681 outputs: []outputInfo{ 15682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15683 }, 15684 }, 15685 }, 15686 { 15687 name: "SRLconst", 15688 auxType: auxInt32, 15689 argLen: 1, 15690 asm: arm.ASRL, 15691 reg: regInfo{ 15692 inputs: []inputInfo{ 15693 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15694 }, 15695 outputs: []outputInfo{ 15696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15697 }, 15698 }, 15699 }, 15700 { 15701 name: "SRA", 15702 argLen: 2, 15703 asm: arm.ASRA, 15704 reg: regInfo{ 15705 inputs: []inputInfo{ 15706 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15707 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15708 }, 15709 outputs: []outputInfo{ 15710 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15711 }, 15712 }, 15713 }, 15714 { 15715 name: "SRAconst", 15716 auxType: auxInt32, 15717 argLen: 1, 15718 asm: arm.ASRA, 15719 reg: regInfo{ 15720 inputs: []inputInfo{ 15721 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15722 }, 15723 outputs: []outputInfo{ 15724 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15725 }, 15726 }, 15727 }, 15728 { 15729 name: "SRR", 15730 argLen: 2, 15731 reg: regInfo{ 15732 inputs: []inputInfo{ 15733 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15734 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15735 }, 15736 outputs: []outputInfo{ 15737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15738 }, 15739 }, 15740 }, 15741 { 15742 name: "SRRconst", 15743 auxType: auxInt32, 15744 argLen: 1, 15745 reg: regInfo{ 15746 inputs: []inputInfo{ 15747 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15748 }, 15749 outputs: []outputInfo{ 15750 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15751 }, 15752 }, 15753 }, 15754 { 15755 name: "ADDshiftLL", 15756 auxType: auxInt32, 15757 argLen: 2, 15758 asm: arm.AADD, 15759 reg: regInfo{ 15760 inputs: []inputInfo{ 15761 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15762 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15763 }, 15764 outputs: []outputInfo{ 15765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15766 }, 15767 }, 15768 }, 15769 { 15770 name: "ADDshiftRL", 15771 auxType: auxInt32, 15772 argLen: 2, 15773 asm: arm.AADD, 15774 reg: regInfo{ 15775 inputs: []inputInfo{ 15776 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15777 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15778 }, 15779 outputs: []outputInfo{ 15780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15781 }, 15782 }, 15783 }, 15784 { 15785 name: "ADDshiftRA", 15786 auxType: auxInt32, 15787 argLen: 2, 15788 asm: arm.AADD, 15789 reg: regInfo{ 15790 inputs: []inputInfo{ 15791 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15792 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15793 }, 15794 outputs: []outputInfo{ 15795 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15796 }, 15797 }, 15798 }, 15799 { 15800 name: "SUBshiftLL", 15801 auxType: auxInt32, 15802 argLen: 2, 15803 asm: arm.ASUB, 15804 reg: regInfo{ 15805 inputs: []inputInfo{ 15806 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15807 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15808 }, 15809 outputs: []outputInfo{ 15810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15811 }, 15812 }, 15813 }, 15814 { 15815 name: "SUBshiftRL", 15816 auxType: auxInt32, 15817 argLen: 2, 15818 asm: arm.ASUB, 15819 reg: regInfo{ 15820 inputs: []inputInfo{ 15821 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15822 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15823 }, 15824 outputs: []outputInfo{ 15825 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15826 }, 15827 }, 15828 }, 15829 { 15830 name: "SUBshiftRA", 15831 auxType: auxInt32, 15832 argLen: 2, 15833 asm: arm.ASUB, 15834 reg: regInfo{ 15835 inputs: []inputInfo{ 15836 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15837 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15838 }, 15839 outputs: []outputInfo{ 15840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15841 }, 15842 }, 15843 }, 15844 { 15845 name: "RSBshiftLL", 15846 auxType: auxInt32, 15847 argLen: 2, 15848 asm: arm.ARSB, 15849 reg: regInfo{ 15850 inputs: []inputInfo{ 15851 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15852 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15853 }, 15854 outputs: []outputInfo{ 15855 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15856 }, 15857 }, 15858 }, 15859 { 15860 name: "RSBshiftRL", 15861 auxType: auxInt32, 15862 argLen: 2, 15863 asm: arm.ARSB, 15864 reg: regInfo{ 15865 inputs: []inputInfo{ 15866 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15867 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15868 }, 15869 outputs: []outputInfo{ 15870 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15871 }, 15872 }, 15873 }, 15874 { 15875 name: "RSBshiftRA", 15876 auxType: auxInt32, 15877 argLen: 2, 15878 asm: arm.ARSB, 15879 reg: regInfo{ 15880 inputs: []inputInfo{ 15881 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15882 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15883 }, 15884 outputs: []outputInfo{ 15885 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15886 }, 15887 }, 15888 }, 15889 { 15890 name: "ANDshiftLL", 15891 auxType: auxInt32, 15892 argLen: 2, 15893 asm: arm.AAND, 15894 reg: regInfo{ 15895 inputs: []inputInfo{ 15896 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15897 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15898 }, 15899 outputs: []outputInfo{ 15900 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15901 }, 15902 }, 15903 }, 15904 { 15905 name: "ANDshiftRL", 15906 auxType: auxInt32, 15907 argLen: 2, 15908 asm: arm.AAND, 15909 reg: regInfo{ 15910 inputs: []inputInfo{ 15911 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15912 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15913 }, 15914 outputs: []outputInfo{ 15915 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15916 }, 15917 }, 15918 }, 15919 { 15920 name: "ANDshiftRA", 15921 auxType: auxInt32, 15922 argLen: 2, 15923 asm: arm.AAND, 15924 reg: regInfo{ 15925 inputs: []inputInfo{ 15926 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15927 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15928 }, 15929 outputs: []outputInfo{ 15930 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15931 }, 15932 }, 15933 }, 15934 { 15935 name: "ORshiftLL", 15936 auxType: auxInt32, 15937 argLen: 2, 15938 asm: arm.AORR, 15939 reg: regInfo{ 15940 inputs: []inputInfo{ 15941 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15942 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15943 }, 15944 outputs: []outputInfo{ 15945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15946 }, 15947 }, 15948 }, 15949 { 15950 name: "ORshiftRL", 15951 auxType: auxInt32, 15952 argLen: 2, 15953 asm: arm.AORR, 15954 reg: regInfo{ 15955 inputs: []inputInfo{ 15956 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15957 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15958 }, 15959 outputs: []outputInfo{ 15960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15961 }, 15962 }, 15963 }, 15964 { 15965 name: "ORshiftRA", 15966 auxType: auxInt32, 15967 argLen: 2, 15968 asm: arm.AORR, 15969 reg: regInfo{ 15970 inputs: []inputInfo{ 15971 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15972 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15973 }, 15974 outputs: []outputInfo{ 15975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15976 }, 15977 }, 15978 }, 15979 { 15980 name: "XORshiftLL", 15981 auxType: auxInt32, 15982 argLen: 2, 15983 asm: arm.AEOR, 15984 reg: regInfo{ 15985 inputs: []inputInfo{ 15986 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15987 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 15988 }, 15989 outputs: []outputInfo{ 15990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 15991 }, 15992 }, 15993 }, 15994 { 15995 name: "XORshiftRL", 15996 auxType: auxInt32, 15997 argLen: 2, 15998 asm: arm.AEOR, 15999 reg: regInfo{ 16000 inputs: []inputInfo{ 16001 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16002 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16003 }, 16004 outputs: []outputInfo{ 16005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16006 }, 16007 }, 16008 }, 16009 { 16010 name: "XORshiftRA", 16011 auxType: auxInt32, 16012 argLen: 2, 16013 asm: arm.AEOR, 16014 reg: regInfo{ 16015 inputs: []inputInfo{ 16016 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16017 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16018 }, 16019 outputs: []outputInfo{ 16020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16021 }, 16022 }, 16023 }, 16024 { 16025 name: "XORshiftRR", 16026 auxType: auxInt32, 16027 argLen: 2, 16028 asm: arm.AEOR, 16029 reg: regInfo{ 16030 inputs: []inputInfo{ 16031 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16032 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16033 }, 16034 outputs: []outputInfo{ 16035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16036 }, 16037 }, 16038 }, 16039 { 16040 name: "BICshiftLL", 16041 auxType: auxInt32, 16042 argLen: 2, 16043 asm: arm.ABIC, 16044 reg: regInfo{ 16045 inputs: []inputInfo{ 16046 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16047 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16048 }, 16049 outputs: []outputInfo{ 16050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16051 }, 16052 }, 16053 }, 16054 { 16055 name: "BICshiftRL", 16056 auxType: auxInt32, 16057 argLen: 2, 16058 asm: arm.ABIC, 16059 reg: regInfo{ 16060 inputs: []inputInfo{ 16061 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16062 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16063 }, 16064 outputs: []outputInfo{ 16065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16066 }, 16067 }, 16068 }, 16069 { 16070 name: "BICshiftRA", 16071 auxType: auxInt32, 16072 argLen: 2, 16073 asm: arm.ABIC, 16074 reg: regInfo{ 16075 inputs: []inputInfo{ 16076 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16077 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16078 }, 16079 outputs: []outputInfo{ 16080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16081 }, 16082 }, 16083 }, 16084 { 16085 name: "MVNshiftLL", 16086 auxType: auxInt32, 16087 argLen: 1, 16088 asm: arm.AMVN, 16089 reg: regInfo{ 16090 inputs: []inputInfo{ 16091 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16092 }, 16093 outputs: []outputInfo{ 16094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16095 }, 16096 }, 16097 }, 16098 { 16099 name: "MVNshiftRL", 16100 auxType: auxInt32, 16101 argLen: 1, 16102 asm: arm.AMVN, 16103 reg: regInfo{ 16104 inputs: []inputInfo{ 16105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16106 }, 16107 outputs: []outputInfo{ 16108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16109 }, 16110 }, 16111 }, 16112 { 16113 name: "MVNshiftRA", 16114 auxType: auxInt32, 16115 argLen: 1, 16116 asm: arm.AMVN, 16117 reg: regInfo{ 16118 inputs: []inputInfo{ 16119 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16120 }, 16121 outputs: []outputInfo{ 16122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16123 }, 16124 }, 16125 }, 16126 { 16127 name: "ADCshiftLL", 16128 auxType: auxInt32, 16129 argLen: 3, 16130 asm: arm.AADC, 16131 reg: regInfo{ 16132 inputs: []inputInfo{ 16133 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16134 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16135 }, 16136 outputs: []outputInfo{ 16137 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16138 }, 16139 }, 16140 }, 16141 { 16142 name: "ADCshiftRL", 16143 auxType: auxInt32, 16144 argLen: 3, 16145 asm: arm.AADC, 16146 reg: regInfo{ 16147 inputs: []inputInfo{ 16148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16149 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16150 }, 16151 outputs: []outputInfo{ 16152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16153 }, 16154 }, 16155 }, 16156 { 16157 name: "ADCshiftRA", 16158 auxType: auxInt32, 16159 argLen: 3, 16160 asm: arm.AADC, 16161 reg: regInfo{ 16162 inputs: []inputInfo{ 16163 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16164 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16165 }, 16166 outputs: []outputInfo{ 16167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16168 }, 16169 }, 16170 }, 16171 { 16172 name: "SBCshiftLL", 16173 auxType: auxInt32, 16174 argLen: 3, 16175 asm: arm.ASBC, 16176 reg: regInfo{ 16177 inputs: []inputInfo{ 16178 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16179 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16180 }, 16181 outputs: []outputInfo{ 16182 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16183 }, 16184 }, 16185 }, 16186 { 16187 name: "SBCshiftRL", 16188 auxType: auxInt32, 16189 argLen: 3, 16190 asm: arm.ASBC, 16191 reg: regInfo{ 16192 inputs: []inputInfo{ 16193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16194 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16195 }, 16196 outputs: []outputInfo{ 16197 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16198 }, 16199 }, 16200 }, 16201 { 16202 name: "SBCshiftRA", 16203 auxType: auxInt32, 16204 argLen: 3, 16205 asm: arm.ASBC, 16206 reg: regInfo{ 16207 inputs: []inputInfo{ 16208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16209 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16210 }, 16211 outputs: []outputInfo{ 16212 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16213 }, 16214 }, 16215 }, 16216 { 16217 name: "RSCshiftLL", 16218 auxType: auxInt32, 16219 argLen: 3, 16220 asm: arm.ARSC, 16221 reg: regInfo{ 16222 inputs: []inputInfo{ 16223 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16224 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16225 }, 16226 outputs: []outputInfo{ 16227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16228 }, 16229 }, 16230 }, 16231 { 16232 name: "RSCshiftRL", 16233 auxType: auxInt32, 16234 argLen: 3, 16235 asm: arm.ARSC, 16236 reg: regInfo{ 16237 inputs: []inputInfo{ 16238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16239 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16240 }, 16241 outputs: []outputInfo{ 16242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16243 }, 16244 }, 16245 }, 16246 { 16247 name: "RSCshiftRA", 16248 auxType: auxInt32, 16249 argLen: 3, 16250 asm: arm.ARSC, 16251 reg: regInfo{ 16252 inputs: []inputInfo{ 16253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16254 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16255 }, 16256 outputs: []outputInfo{ 16257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16258 }, 16259 }, 16260 }, 16261 { 16262 name: "ADDSshiftLL", 16263 auxType: auxInt32, 16264 argLen: 2, 16265 asm: arm.AADD, 16266 reg: regInfo{ 16267 inputs: []inputInfo{ 16268 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16269 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16270 }, 16271 outputs: []outputInfo{ 16272 {1, 0}, 16273 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16274 }, 16275 }, 16276 }, 16277 { 16278 name: "ADDSshiftRL", 16279 auxType: auxInt32, 16280 argLen: 2, 16281 asm: arm.AADD, 16282 reg: regInfo{ 16283 inputs: []inputInfo{ 16284 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16285 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16286 }, 16287 outputs: []outputInfo{ 16288 {1, 0}, 16289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16290 }, 16291 }, 16292 }, 16293 { 16294 name: "ADDSshiftRA", 16295 auxType: auxInt32, 16296 argLen: 2, 16297 asm: arm.AADD, 16298 reg: regInfo{ 16299 inputs: []inputInfo{ 16300 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16301 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16302 }, 16303 outputs: []outputInfo{ 16304 {1, 0}, 16305 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16306 }, 16307 }, 16308 }, 16309 { 16310 name: "SUBSshiftLL", 16311 auxType: auxInt32, 16312 argLen: 2, 16313 asm: arm.ASUB, 16314 reg: regInfo{ 16315 inputs: []inputInfo{ 16316 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16317 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16318 }, 16319 outputs: []outputInfo{ 16320 {1, 0}, 16321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16322 }, 16323 }, 16324 }, 16325 { 16326 name: "SUBSshiftRL", 16327 auxType: auxInt32, 16328 argLen: 2, 16329 asm: arm.ASUB, 16330 reg: regInfo{ 16331 inputs: []inputInfo{ 16332 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16333 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16334 }, 16335 outputs: []outputInfo{ 16336 {1, 0}, 16337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16338 }, 16339 }, 16340 }, 16341 { 16342 name: "SUBSshiftRA", 16343 auxType: auxInt32, 16344 argLen: 2, 16345 asm: arm.ASUB, 16346 reg: regInfo{ 16347 inputs: []inputInfo{ 16348 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16349 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16350 }, 16351 outputs: []outputInfo{ 16352 {1, 0}, 16353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16354 }, 16355 }, 16356 }, 16357 { 16358 name: "RSBSshiftLL", 16359 auxType: auxInt32, 16360 argLen: 2, 16361 asm: arm.ARSB, 16362 reg: regInfo{ 16363 inputs: []inputInfo{ 16364 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16365 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16366 }, 16367 outputs: []outputInfo{ 16368 {1, 0}, 16369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16370 }, 16371 }, 16372 }, 16373 { 16374 name: "RSBSshiftRL", 16375 auxType: auxInt32, 16376 argLen: 2, 16377 asm: arm.ARSB, 16378 reg: regInfo{ 16379 inputs: []inputInfo{ 16380 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16381 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16382 }, 16383 outputs: []outputInfo{ 16384 {1, 0}, 16385 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16386 }, 16387 }, 16388 }, 16389 { 16390 name: "RSBSshiftRA", 16391 auxType: auxInt32, 16392 argLen: 2, 16393 asm: arm.ARSB, 16394 reg: regInfo{ 16395 inputs: []inputInfo{ 16396 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16397 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16398 }, 16399 outputs: []outputInfo{ 16400 {1, 0}, 16401 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16402 }, 16403 }, 16404 }, 16405 { 16406 name: "ADDshiftLLreg", 16407 argLen: 3, 16408 asm: arm.AADD, 16409 reg: regInfo{ 16410 inputs: []inputInfo{ 16411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16412 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16413 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16414 }, 16415 outputs: []outputInfo{ 16416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16417 }, 16418 }, 16419 }, 16420 { 16421 name: "ADDshiftRLreg", 16422 argLen: 3, 16423 asm: arm.AADD, 16424 reg: regInfo{ 16425 inputs: []inputInfo{ 16426 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16427 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16428 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16429 }, 16430 outputs: []outputInfo{ 16431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16432 }, 16433 }, 16434 }, 16435 { 16436 name: "ADDshiftRAreg", 16437 argLen: 3, 16438 asm: arm.AADD, 16439 reg: regInfo{ 16440 inputs: []inputInfo{ 16441 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16442 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16443 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16444 }, 16445 outputs: []outputInfo{ 16446 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16447 }, 16448 }, 16449 }, 16450 { 16451 name: "SUBshiftLLreg", 16452 argLen: 3, 16453 asm: arm.ASUB, 16454 reg: regInfo{ 16455 inputs: []inputInfo{ 16456 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16457 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16458 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16459 }, 16460 outputs: []outputInfo{ 16461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16462 }, 16463 }, 16464 }, 16465 { 16466 name: "SUBshiftRLreg", 16467 argLen: 3, 16468 asm: arm.ASUB, 16469 reg: regInfo{ 16470 inputs: []inputInfo{ 16471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16472 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16473 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16474 }, 16475 outputs: []outputInfo{ 16476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16477 }, 16478 }, 16479 }, 16480 { 16481 name: "SUBshiftRAreg", 16482 argLen: 3, 16483 asm: arm.ASUB, 16484 reg: regInfo{ 16485 inputs: []inputInfo{ 16486 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16487 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16488 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16489 }, 16490 outputs: []outputInfo{ 16491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16492 }, 16493 }, 16494 }, 16495 { 16496 name: "RSBshiftLLreg", 16497 argLen: 3, 16498 asm: arm.ARSB, 16499 reg: regInfo{ 16500 inputs: []inputInfo{ 16501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16502 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16503 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16504 }, 16505 outputs: []outputInfo{ 16506 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16507 }, 16508 }, 16509 }, 16510 { 16511 name: "RSBshiftRLreg", 16512 argLen: 3, 16513 asm: arm.ARSB, 16514 reg: regInfo{ 16515 inputs: []inputInfo{ 16516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16517 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16518 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16519 }, 16520 outputs: []outputInfo{ 16521 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16522 }, 16523 }, 16524 }, 16525 { 16526 name: "RSBshiftRAreg", 16527 argLen: 3, 16528 asm: arm.ARSB, 16529 reg: regInfo{ 16530 inputs: []inputInfo{ 16531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16532 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16533 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16534 }, 16535 outputs: []outputInfo{ 16536 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16537 }, 16538 }, 16539 }, 16540 { 16541 name: "ANDshiftLLreg", 16542 argLen: 3, 16543 asm: arm.AAND, 16544 reg: regInfo{ 16545 inputs: []inputInfo{ 16546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16547 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16548 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16549 }, 16550 outputs: []outputInfo{ 16551 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16552 }, 16553 }, 16554 }, 16555 { 16556 name: "ANDshiftRLreg", 16557 argLen: 3, 16558 asm: arm.AAND, 16559 reg: regInfo{ 16560 inputs: []inputInfo{ 16561 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16562 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16563 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16564 }, 16565 outputs: []outputInfo{ 16566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16567 }, 16568 }, 16569 }, 16570 { 16571 name: "ANDshiftRAreg", 16572 argLen: 3, 16573 asm: arm.AAND, 16574 reg: regInfo{ 16575 inputs: []inputInfo{ 16576 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16577 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16578 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16579 }, 16580 outputs: []outputInfo{ 16581 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16582 }, 16583 }, 16584 }, 16585 { 16586 name: "ORshiftLLreg", 16587 argLen: 3, 16588 asm: arm.AORR, 16589 reg: regInfo{ 16590 inputs: []inputInfo{ 16591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16592 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16593 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16594 }, 16595 outputs: []outputInfo{ 16596 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16597 }, 16598 }, 16599 }, 16600 { 16601 name: "ORshiftRLreg", 16602 argLen: 3, 16603 asm: arm.AORR, 16604 reg: regInfo{ 16605 inputs: []inputInfo{ 16606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16607 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16608 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16609 }, 16610 outputs: []outputInfo{ 16611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16612 }, 16613 }, 16614 }, 16615 { 16616 name: "ORshiftRAreg", 16617 argLen: 3, 16618 asm: arm.AORR, 16619 reg: regInfo{ 16620 inputs: []inputInfo{ 16621 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16622 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16623 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16624 }, 16625 outputs: []outputInfo{ 16626 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16627 }, 16628 }, 16629 }, 16630 { 16631 name: "XORshiftLLreg", 16632 argLen: 3, 16633 asm: arm.AEOR, 16634 reg: regInfo{ 16635 inputs: []inputInfo{ 16636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16637 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16638 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16639 }, 16640 outputs: []outputInfo{ 16641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16642 }, 16643 }, 16644 }, 16645 { 16646 name: "XORshiftRLreg", 16647 argLen: 3, 16648 asm: arm.AEOR, 16649 reg: regInfo{ 16650 inputs: []inputInfo{ 16651 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16652 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16653 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16654 }, 16655 outputs: []outputInfo{ 16656 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16657 }, 16658 }, 16659 }, 16660 { 16661 name: "XORshiftRAreg", 16662 argLen: 3, 16663 asm: arm.AEOR, 16664 reg: regInfo{ 16665 inputs: []inputInfo{ 16666 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16667 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16668 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16669 }, 16670 outputs: []outputInfo{ 16671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16672 }, 16673 }, 16674 }, 16675 { 16676 name: "BICshiftLLreg", 16677 argLen: 3, 16678 asm: arm.ABIC, 16679 reg: regInfo{ 16680 inputs: []inputInfo{ 16681 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16682 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16683 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16684 }, 16685 outputs: []outputInfo{ 16686 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16687 }, 16688 }, 16689 }, 16690 { 16691 name: "BICshiftRLreg", 16692 argLen: 3, 16693 asm: arm.ABIC, 16694 reg: regInfo{ 16695 inputs: []inputInfo{ 16696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16697 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16698 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16699 }, 16700 outputs: []outputInfo{ 16701 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16702 }, 16703 }, 16704 }, 16705 { 16706 name: "BICshiftRAreg", 16707 argLen: 3, 16708 asm: arm.ABIC, 16709 reg: regInfo{ 16710 inputs: []inputInfo{ 16711 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16712 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16713 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16714 }, 16715 outputs: []outputInfo{ 16716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16717 }, 16718 }, 16719 }, 16720 { 16721 name: "MVNshiftLLreg", 16722 argLen: 2, 16723 asm: arm.AMVN, 16724 reg: regInfo{ 16725 inputs: []inputInfo{ 16726 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16727 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16728 }, 16729 outputs: []outputInfo{ 16730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16731 }, 16732 }, 16733 }, 16734 { 16735 name: "MVNshiftRLreg", 16736 argLen: 2, 16737 asm: arm.AMVN, 16738 reg: regInfo{ 16739 inputs: []inputInfo{ 16740 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16741 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16742 }, 16743 outputs: []outputInfo{ 16744 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16745 }, 16746 }, 16747 }, 16748 { 16749 name: "MVNshiftRAreg", 16750 argLen: 2, 16751 asm: arm.AMVN, 16752 reg: regInfo{ 16753 inputs: []inputInfo{ 16754 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16755 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 16756 }, 16757 outputs: []outputInfo{ 16758 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16759 }, 16760 }, 16761 }, 16762 { 16763 name: "ADCshiftLLreg", 16764 argLen: 4, 16765 asm: arm.AADC, 16766 reg: regInfo{ 16767 inputs: []inputInfo{ 16768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16769 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16770 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16771 }, 16772 outputs: []outputInfo{ 16773 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16774 }, 16775 }, 16776 }, 16777 { 16778 name: "ADCshiftRLreg", 16779 argLen: 4, 16780 asm: arm.AADC, 16781 reg: regInfo{ 16782 inputs: []inputInfo{ 16783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16784 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16785 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16786 }, 16787 outputs: []outputInfo{ 16788 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16789 }, 16790 }, 16791 }, 16792 { 16793 name: "ADCshiftRAreg", 16794 argLen: 4, 16795 asm: arm.AADC, 16796 reg: regInfo{ 16797 inputs: []inputInfo{ 16798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16799 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16800 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16801 }, 16802 outputs: []outputInfo{ 16803 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16804 }, 16805 }, 16806 }, 16807 { 16808 name: "SBCshiftLLreg", 16809 argLen: 4, 16810 asm: arm.ASBC, 16811 reg: regInfo{ 16812 inputs: []inputInfo{ 16813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16814 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16815 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16816 }, 16817 outputs: []outputInfo{ 16818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16819 }, 16820 }, 16821 }, 16822 { 16823 name: "SBCshiftRLreg", 16824 argLen: 4, 16825 asm: arm.ASBC, 16826 reg: regInfo{ 16827 inputs: []inputInfo{ 16828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16829 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16830 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16831 }, 16832 outputs: []outputInfo{ 16833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16834 }, 16835 }, 16836 }, 16837 { 16838 name: "SBCshiftRAreg", 16839 argLen: 4, 16840 asm: arm.ASBC, 16841 reg: regInfo{ 16842 inputs: []inputInfo{ 16843 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16844 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16845 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16846 }, 16847 outputs: []outputInfo{ 16848 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16849 }, 16850 }, 16851 }, 16852 { 16853 name: "RSCshiftLLreg", 16854 argLen: 4, 16855 asm: arm.ARSC, 16856 reg: regInfo{ 16857 inputs: []inputInfo{ 16858 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16859 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16860 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16861 }, 16862 outputs: []outputInfo{ 16863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16864 }, 16865 }, 16866 }, 16867 { 16868 name: "RSCshiftRLreg", 16869 argLen: 4, 16870 asm: arm.ARSC, 16871 reg: regInfo{ 16872 inputs: []inputInfo{ 16873 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16874 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16875 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16876 }, 16877 outputs: []outputInfo{ 16878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16879 }, 16880 }, 16881 }, 16882 { 16883 name: "RSCshiftRAreg", 16884 argLen: 4, 16885 asm: arm.ARSC, 16886 reg: regInfo{ 16887 inputs: []inputInfo{ 16888 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16889 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16890 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16891 }, 16892 outputs: []outputInfo{ 16893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16894 }, 16895 }, 16896 }, 16897 { 16898 name: "ADDSshiftLLreg", 16899 argLen: 3, 16900 asm: arm.AADD, 16901 reg: regInfo{ 16902 inputs: []inputInfo{ 16903 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16904 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16905 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16906 }, 16907 outputs: []outputInfo{ 16908 {1, 0}, 16909 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16910 }, 16911 }, 16912 }, 16913 { 16914 name: "ADDSshiftRLreg", 16915 argLen: 3, 16916 asm: arm.AADD, 16917 reg: regInfo{ 16918 inputs: []inputInfo{ 16919 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16920 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16921 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16922 }, 16923 outputs: []outputInfo{ 16924 {1, 0}, 16925 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16926 }, 16927 }, 16928 }, 16929 { 16930 name: "ADDSshiftRAreg", 16931 argLen: 3, 16932 asm: arm.AADD, 16933 reg: regInfo{ 16934 inputs: []inputInfo{ 16935 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16936 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16937 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16938 }, 16939 outputs: []outputInfo{ 16940 {1, 0}, 16941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16942 }, 16943 }, 16944 }, 16945 { 16946 name: "SUBSshiftLLreg", 16947 argLen: 3, 16948 asm: arm.ASUB, 16949 reg: regInfo{ 16950 inputs: []inputInfo{ 16951 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16952 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16953 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16954 }, 16955 outputs: []outputInfo{ 16956 {1, 0}, 16957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16958 }, 16959 }, 16960 }, 16961 { 16962 name: "SUBSshiftRLreg", 16963 argLen: 3, 16964 asm: arm.ASUB, 16965 reg: regInfo{ 16966 inputs: []inputInfo{ 16967 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16968 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16969 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16970 }, 16971 outputs: []outputInfo{ 16972 {1, 0}, 16973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16974 }, 16975 }, 16976 }, 16977 { 16978 name: "SUBSshiftRAreg", 16979 argLen: 3, 16980 asm: arm.ASUB, 16981 reg: regInfo{ 16982 inputs: []inputInfo{ 16983 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16984 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16985 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16986 }, 16987 outputs: []outputInfo{ 16988 {1, 0}, 16989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 16990 }, 16991 }, 16992 }, 16993 { 16994 name: "RSBSshiftLLreg", 16995 argLen: 3, 16996 asm: arm.ARSB, 16997 reg: regInfo{ 16998 inputs: []inputInfo{ 16999 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17000 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17001 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17002 }, 17003 outputs: []outputInfo{ 17004 {1, 0}, 17005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17006 }, 17007 }, 17008 }, 17009 { 17010 name: "RSBSshiftRLreg", 17011 argLen: 3, 17012 asm: arm.ARSB, 17013 reg: regInfo{ 17014 inputs: []inputInfo{ 17015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17016 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17017 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17018 }, 17019 outputs: []outputInfo{ 17020 {1, 0}, 17021 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17022 }, 17023 }, 17024 }, 17025 { 17026 name: "RSBSshiftRAreg", 17027 argLen: 3, 17028 asm: arm.ARSB, 17029 reg: regInfo{ 17030 inputs: []inputInfo{ 17031 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17032 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17033 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17034 }, 17035 outputs: []outputInfo{ 17036 {1, 0}, 17037 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17038 }, 17039 }, 17040 }, 17041 { 17042 name: "CMP", 17043 argLen: 2, 17044 asm: arm.ACMP, 17045 reg: regInfo{ 17046 inputs: []inputInfo{ 17047 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17048 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17049 }, 17050 }, 17051 }, 17052 { 17053 name: "CMPconst", 17054 auxType: auxInt32, 17055 argLen: 1, 17056 asm: arm.ACMP, 17057 reg: regInfo{ 17058 inputs: []inputInfo{ 17059 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17060 }, 17061 }, 17062 }, 17063 { 17064 name: "CMN", 17065 argLen: 2, 17066 commutative: true, 17067 asm: arm.ACMN, 17068 reg: regInfo{ 17069 inputs: []inputInfo{ 17070 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17071 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17072 }, 17073 }, 17074 }, 17075 { 17076 name: "CMNconst", 17077 auxType: auxInt32, 17078 argLen: 1, 17079 asm: arm.ACMN, 17080 reg: regInfo{ 17081 inputs: []inputInfo{ 17082 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17083 }, 17084 }, 17085 }, 17086 { 17087 name: "TST", 17088 argLen: 2, 17089 commutative: true, 17090 asm: arm.ATST, 17091 reg: regInfo{ 17092 inputs: []inputInfo{ 17093 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17094 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17095 }, 17096 }, 17097 }, 17098 { 17099 name: "TSTconst", 17100 auxType: auxInt32, 17101 argLen: 1, 17102 asm: arm.ATST, 17103 reg: regInfo{ 17104 inputs: []inputInfo{ 17105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17106 }, 17107 }, 17108 }, 17109 { 17110 name: "TEQ", 17111 argLen: 2, 17112 commutative: true, 17113 asm: arm.ATEQ, 17114 reg: regInfo{ 17115 inputs: []inputInfo{ 17116 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17117 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17118 }, 17119 }, 17120 }, 17121 { 17122 name: "TEQconst", 17123 auxType: auxInt32, 17124 argLen: 1, 17125 asm: arm.ATEQ, 17126 reg: regInfo{ 17127 inputs: []inputInfo{ 17128 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17129 }, 17130 }, 17131 }, 17132 { 17133 name: "CMPF", 17134 argLen: 2, 17135 asm: arm.ACMPF, 17136 reg: regInfo{ 17137 inputs: []inputInfo{ 17138 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17139 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17140 }, 17141 }, 17142 }, 17143 { 17144 name: "CMPD", 17145 argLen: 2, 17146 asm: arm.ACMPD, 17147 reg: regInfo{ 17148 inputs: []inputInfo{ 17149 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17150 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17151 }, 17152 }, 17153 }, 17154 { 17155 name: "CMPshiftLL", 17156 auxType: auxInt32, 17157 argLen: 2, 17158 asm: arm.ACMP, 17159 reg: regInfo{ 17160 inputs: []inputInfo{ 17161 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17162 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17163 }, 17164 }, 17165 }, 17166 { 17167 name: "CMPshiftRL", 17168 auxType: auxInt32, 17169 argLen: 2, 17170 asm: arm.ACMP, 17171 reg: regInfo{ 17172 inputs: []inputInfo{ 17173 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17174 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17175 }, 17176 }, 17177 }, 17178 { 17179 name: "CMPshiftRA", 17180 auxType: auxInt32, 17181 argLen: 2, 17182 asm: arm.ACMP, 17183 reg: regInfo{ 17184 inputs: []inputInfo{ 17185 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17186 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17187 }, 17188 }, 17189 }, 17190 { 17191 name: "CMNshiftLL", 17192 auxType: auxInt32, 17193 argLen: 2, 17194 asm: arm.ACMN, 17195 reg: regInfo{ 17196 inputs: []inputInfo{ 17197 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17198 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17199 }, 17200 }, 17201 }, 17202 { 17203 name: "CMNshiftRL", 17204 auxType: auxInt32, 17205 argLen: 2, 17206 asm: arm.ACMN, 17207 reg: regInfo{ 17208 inputs: []inputInfo{ 17209 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17210 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17211 }, 17212 }, 17213 }, 17214 { 17215 name: "CMNshiftRA", 17216 auxType: auxInt32, 17217 argLen: 2, 17218 asm: arm.ACMN, 17219 reg: regInfo{ 17220 inputs: []inputInfo{ 17221 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17222 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17223 }, 17224 }, 17225 }, 17226 { 17227 name: "TSTshiftLL", 17228 auxType: auxInt32, 17229 argLen: 2, 17230 asm: arm.ATST, 17231 reg: regInfo{ 17232 inputs: []inputInfo{ 17233 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17234 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17235 }, 17236 }, 17237 }, 17238 { 17239 name: "TSTshiftRL", 17240 auxType: auxInt32, 17241 argLen: 2, 17242 asm: arm.ATST, 17243 reg: regInfo{ 17244 inputs: []inputInfo{ 17245 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17246 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17247 }, 17248 }, 17249 }, 17250 { 17251 name: "TSTshiftRA", 17252 auxType: auxInt32, 17253 argLen: 2, 17254 asm: arm.ATST, 17255 reg: regInfo{ 17256 inputs: []inputInfo{ 17257 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17258 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17259 }, 17260 }, 17261 }, 17262 { 17263 name: "TEQshiftLL", 17264 auxType: auxInt32, 17265 argLen: 2, 17266 asm: arm.ATEQ, 17267 reg: regInfo{ 17268 inputs: []inputInfo{ 17269 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17270 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17271 }, 17272 }, 17273 }, 17274 { 17275 name: "TEQshiftRL", 17276 auxType: auxInt32, 17277 argLen: 2, 17278 asm: arm.ATEQ, 17279 reg: regInfo{ 17280 inputs: []inputInfo{ 17281 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17282 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17283 }, 17284 }, 17285 }, 17286 { 17287 name: "TEQshiftRA", 17288 auxType: auxInt32, 17289 argLen: 2, 17290 asm: arm.ATEQ, 17291 reg: regInfo{ 17292 inputs: []inputInfo{ 17293 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17294 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17295 }, 17296 }, 17297 }, 17298 { 17299 name: "CMPshiftLLreg", 17300 argLen: 3, 17301 asm: arm.ACMP, 17302 reg: regInfo{ 17303 inputs: []inputInfo{ 17304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17305 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17306 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17307 }, 17308 }, 17309 }, 17310 { 17311 name: "CMPshiftRLreg", 17312 argLen: 3, 17313 asm: arm.ACMP, 17314 reg: regInfo{ 17315 inputs: []inputInfo{ 17316 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17317 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17318 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17319 }, 17320 }, 17321 }, 17322 { 17323 name: "CMPshiftRAreg", 17324 argLen: 3, 17325 asm: arm.ACMP, 17326 reg: regInfo{ 17327 inputs: []inputInfo{ 17328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17329 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17330 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17331 }, 17332 }, 17333 }, 17334 { 17335 name: "CMNshiftLLreg", 17336 argLen: 3, 17337 asm: arm.ACMN, 17338 reg: regInfo{ 17339 inputs: []inputInfo{ 17340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17341 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17342 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17343 }, 17344 }, 17345 }, 17346 { 17347 name: "CMNshiftRLreg", 17348 argLen: 3, 17349 asm: arm.ACMN, 17350 reg: regInfo{ 17351 inputs: []inputInfo{ 17352 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17353 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17354 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17355 }, 17356 }, 17357 }, 17358 { 17359 name: "CMNshiftRAreg", 17360 argLen: 3, 17361 asm: arm.ACMN, 17362 reg: regInfo{ 17363 inputs: []inputInfo{ 17364 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17365 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17366 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17367 }, 17368 }, 17369 }, 17370 { 17371 name: "TSTshiftLLreg", 17372 argLen: 3, 17373 asm: arm.ATST, 17374 reg: regInfo{ 17375 inputs: []inputInfo{ 17376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17377 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17378 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17379 }, 17380 }, 17381 }, 17382 { 17383 name: "TSTshiftRLreg", 17384 argLen: 3, 17385 asm: arm.ATST, 17386 reg: regInfo{ 17387 inputs: []inputInfo{ 17388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17389 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17390 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17391 }, 17392 }, 17393 }, 17394 { 17395 name: "TSTshiftRAreg", 17396 argLen: 3, 17397 asm: arm.ATST, 17398 reg: regInfo{ 17399 inputs: []inputInfo{ 17400 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17401 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17402 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "TEQshiftLLreg", 17408 argLen: 3, 17409 asm: arm.ATEQ, 17410 reg: regInfo{ 17411 inputs: []inputInfo{ 17412 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17413 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17414 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17415 }, 17416 }, 17417 }, 17418 { 17419 name: "TEQshiftRLreg", 17420 argLen: 3, 17421 asm: arm.ATEQ, 17422 reg: regInfo{ 17423 inputs: []inputInfo{ 17424 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17425 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17426 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17427 }, 17428 }, 17429 }, 17430 { 17431 name: "TEQshiftRAreg", 17432 argLen: 3, 17433 asm: arm.ATEQ, 17434 reg: regInfo{ 17435 inputs: []inputInfo{ 17436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17437 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17438 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17439 }, 17440 }, 17441 }, 17442 { 17443 name: "CMPF0", 17444 argLen: 1, 17445 asm: arm.ACMPF, 17446 reg: regInfo{ 17447 inputs: []inputInfo{ 17448 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17449 }, 17450 }, 17451 }, 17452 { 17453 name: "CMPD0", 17454 argLen: 1, 17455 asm: arm.ACMPD, 17456 reg: regInfo{ 17457 inputs: []inputInfo{ 17458 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17459 }, 17460 }, 17461 }, 17462 { 17463 name: "MOVWconst", 17464 auxType: auxInt32, 17465 argLen: 0, 17466 rematerializeable: true, 17467 asm: arm.AMOVW, 17468 reg: regInfo{ 17469 outputs: []outputInfo{ 17470 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17471 }, 17472 }, 17473 }, 17474 { 17475 name: "MOVFconst", 17476 auxType: auxFloat64, 17477 argLen: 0, 17478 rematerializeable: true, 17479 asm: arm.AMOVF, 17480 reg: regInfo{ 17481 outputs: []outputInfo{ 17482 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17483 }, 17484 }, 17485 }, 17486 { 17487 name: "MOVDconst", 17488 auxType: auxFloat64, 17489 argLen: 0, 17490 rematerializeable: true, 17491 asm: arm.AMOVD, 17492 reg: regInfo{ 17493 outputs: []outputInfo{ 17494 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17495 }, 17496 }, 17497 }, 17498 { 17499 name: "MOVWaddr", 17500 auxType: auxSymOff, 17501 argLen: 1, 17502 rematerializeable: true, 17503 symEffect: SymAddr, 17504 asm: arm.AMOVW, 17505 reg: regInfo{ 17506 inputs: []inputInfo{ 17507 {0, 4294975488}, // SP SB 17508 }, 17509 outputs: []outputInfo{ 17510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17511 }, 17512 }, 17513 }, 17514 { 17515 name: "MOVBload", 17516 auxType: auxSymOff, 17517 argLen: 2, 17518 faultOnNilArg0: true, 17519 symEffect: SymRead, 17520 asm: arm.AMOVB, 17521 reg: regInfo{ 17522 inputs: []inputInfo{ 17523 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17524 }, 17525 outputs: []outputInfo{ 17526 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17527 }, 17528 }, 17529 }, 17530 { 17531 name: "MOVBUload", 17532 auxType: auxSymOff, 17533 argLen: 2, 17534 faultOnNilArg0: true, 17535 symEffect: SymRead, 17536 asm: arm.AMOVBU, 17537 reg: regInfo{ 17538 inputs: []inputInfo{ 17539 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17540 }, 17541 outputs: []outputInfo{ 17542 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17543 }, 17544 }, 17545 }, 17546 { 17547 name: "MOVHload", 17548 auxType: auxSymOff, 17549 argLen: 2, 17550 faultOnNilArg0: true, 17551 symEffect: SymRead, 17552 asm: arm.AMOVH, 17553 reg: regInfo{ 17554 inputs: []inputInfo{ 17555 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17556 }, 17557 outputs: []outputInfo{ 17558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17559 }, 17560 }, 17561 }, 17562 { 17563 name: "MOVHUload", 17564 auxType: auxSymOff, 17565 argLen: 2, 17566 faultOnNilArg0: true, 17567 symEffect: SymRead, 17568 asm: arm.AMOVHU, 17569 reg: regInfo{ 17570 inputs: []inputInfo{ 17571 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17572 }, 17573 outputs: []outputInfo{ 17574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17575 }, 17576 }, 17577 }, 17578 { 17579 name: "MOVWload", 17580 auxType: auxSymOff, 17581 argLen: 2, 17582 faultOnNilArg0: true, 17583 symEffect: SymRead, 17584 asm: arm.AMOVW, 17585 reg: regInfo{ 17586 inputs: []inputInfo{ 17587 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17588 }, 17589 outputs: []outputInfo{ 17590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17591 }, 17592 }, 17593 }, 17594 { 17595 name: "MOVFload", 17596 auxType: auxSymOff, 17597 argLen: 2, 17598 faultOnNilArg0: true, 17599 symEffect: SymRead, 17600 asm: arm.AMOVF, 17601 reg: regInfo{ 17602 inputs: []inputInfo{ 17603 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17604 }, 17605 outputs: []outputInfo{ 17606 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17607 }, 17608 }, 17609 }, 17610 { 17611 name: "MOVDload", 17612 auxType: auxSymOff, 17613 argLen: 2, 17614 faultOnNilArg0: true, 17615 symEffect: SymRead, 17616 asm: arm.AMOVD, 17617 reg: regInfo{ 17618 inputs: []inputInfo{ 17619 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17620 }, 17621 outputs: []outputInfo{ 17622 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17623 }, 17624 }, 17625 }, 17626 { 17627 name: "MOVBstore", 17628 auxType: auxSymOff, 17629 argLen: 3, 17630 faultOnNilArg0: true, 17631 symEffect: SymWrite, 17632 asm: arm.AMOVB, 17633 reg: regInfo{ 17634 inputs: []inputInfo{ 17635 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17636 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17637 }, 17638 }, 17639 }, 17640 { 17641 name: "MOVHstore", 17642 auxType: auxSymOff, 17643 argLen: 3, 17644 faultOnNilArg0: true, 17645 symEffect: SymWrite, 17646 asm: arm.AMOVH, 17647 reg: regInfo{ 17648 inputs: []inputInfo{ 17649 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17650 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17651 }, 17652 }, 17653 }, 17654 { 17655 name: "MOVWstore", 17656 auxType: auxSymOff, 17657 argLen: 3, 17658 faultOnNilArg0: true, 17659 symEffect: SymWrite, 17660 asm: arm.AMOVW, 17661 reg: regInfo{ 17662 inputs: []inputInfo{ 17663 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17664 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17665 }, 17666 }, 17667 }, 17668 { 17669 name: "MOVFstore", 17670 auxType: auxSymOff, 17671 argLen: 3, 17672 faultOnNilArg0: true, 17673 symEffect: SymWrite, 17674 asm: arm.AMOVF, 17675 reg: regInfo{ 17676 inputs: []inputInfo{ 17677 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17678 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17679 }, 17680 }, 17681 }, 17682 { 17683 name: "MOVDstore", 17684 auxType: auxSymOff, 17685 argLen: 3, 17686 faultOnNilArg0: true, 17687 symEffect: SymWrite, 17688 asm: arm.AMOVD, 17689 reg: regInfo{ 17690 inputs: []inputInfo{ 17691 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17692 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17693 }, 17694 }, 17695 }, 17696 { 17697 name: "MOVWloadidx", 17698 argLen: 3, 17699 asm: arm.AMOVW, 17700 reg: regInfo{ 17701 inputs: []inputInfo{ 17702 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17703 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17704 }, 17705 outputs: []outputInfo{ 17706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17707 }, 17708 }, 17709 }, 17710 { 17711 name: "MOVWloadshiftLL", 17712 auxType: auxInt32, 17713 argLen: 3, 17714 asm: arm.AMOVW, 17715 reg: regInfo{ 17716 inputs: []inputInfo{ 17717 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17718 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17719 }, 17720 outputs: []outputInfo{ 17721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17722 }, 17723 }, 17724 }, 17725 { 17726 name: "MOVWloadshiftRL", 17727 auxType: auxInt32, 17728 argLen: 3, 17729 asm: arm.AMOVW, 17730 reg: regInfo{ 17731 inputs: []inputInfo{ 17732 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17733 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17734 }, 17735 outputs: []outputInfo{ 17736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17737 }, 17738 }, 17739 }, 17740 { 17741 name: "MOVWloadshiftRA", 17742 auxType: auxInt32, 17743 argLen: 3, 17744 asm: arm.AMOVW, 17745 reg: regInfo{ 17746 inputs: []inputInfo{ 17747 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17748 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17749 }, 17750 outputs: []outputInfo{ 17751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17752 }, 17753 }, 17754 }, 17755 { 17756 name: "MOVBUloadidx", 17757 argLen: 3, 17758 asm: arm.AMOVBU, 17759 reg: regInfo{ 17760 inputs: []inputInfo{ 17761 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17762 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17763 }, 17764 outputs: []outputInfo{ 17765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17766 }, 17767 }, 17768 }, 17769 { 17770 name: "MOVBloadidx", 17771 argLen: 3, 17772 asm: arm.AMOVB, 17773 reg: regInfo{ 17774 inputs: []inputInfo{ 17775 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17776 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17777 }, 17778 outputs: []outputInfo{ 17779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17780 }, 17781 }, 17782 }, 17783 { 17784 name: "MOVHUloadidx", 17785 argLen: 3, 17786 asm: arm.AMOVHU, 17787 reg: regInfo{ 17788 inputs: []inputInfo{ 17789 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17790 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17791 }, 17792 outputs: []outputInfo{ 17793 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17794 }, 17795 }, 17796 }, 17797 { 17798 name: "MOVHloadidx", 17799 argLen: 3, 17800 asm: arm.AMOVH, 17801 reg: regInfo{ 17802 inputs: []inputInfo{ 17803 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17804 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17805 }, 17806 outputs: []outputInfo{ 17807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17808 }, 17809 }, 17810 }, 17811 { 17812 name: "MOVWstoreidx", 17813 argLen: 4, 17814 asm: arm.AMOVW, 17815 reg: regInfo{ 17816 inputs: []inputInfo{ 17817 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17818 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17819 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17820 }, 17821 }, 17822 }, 17823 { 17824 name: "MOVWstoreshiftLL", 17825 auxType: auxInt32, 17826 argLen: 4, 17827 asm: arm.AMOVW, 17828 reg: regInfo{ 17829 inputs: []inputInfo{ 17830 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17831 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17832 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17833 }, 17834 }, 17835 }, 17836 { 17837 name: "MOVWstoreshiftRL", 17838 auxType: auxInt32, 17839 argLen: 4, 17840 asm: arm.AMOVW, 17841 reg: regInfo{ 17842 inputs: []inputInfo{ 17843 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17844 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17845 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17846 }, 17847 }, 17848 }, 17849 { 17850 name: "MOVWstoreshiftRA", 17851 auxType: auxInt32, 17852 argLen: 4, 17853 asm: arm.AMOVW, 17854 reg: regInfo{ 17855 inputs: []inputInfo{ 17856 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17857 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17858 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17859 }, 17860 }, 17861 }, 17862 { 17863 name: "MOVBstoreidx", 17864 argLen: 4, 17865 asm: arm.AMOVB, 17866 reg: regInfo{ 17867 inputs: []inputInfo{ 17868 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17869 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17870 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17871 }, 17872 }, 17873 }, 17874 { 17875 name: "MOVHstoreidx", 17876 argLen: 4, 17877 asm: arm.AMOVH, 17878 reg: regInfo{ 17879 inputs: []inputInfo{ 17880 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17881 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17882 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 17883 }, 17884 }, 17885 }, 17886 { 17887 name: "MOVBreg", 17888 argLen: 1, 17889 asm: arm.AMOVBS, 17890 reg: regInfo{ 17891 inputs: []inputInfo{ 17892 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17893 }, 17894 outputs: []outputInfo{ 17895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17896 }, 17897 }, 17898 }, 17899 { 17900 name: "MOVBUreg", 17901 argLen: 1, 17902 asm: arm.AMOVBU, 17903 reg: regInfo{ 17904 inputs: []inputInfo{ 17905 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17906 }, 17907 outputs: []outputInfo{ 17908 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17909 }, 17910 }, 17911 }, 17912 { 17913 name: "MOVHreg", 17914 argLen: 1, 17915 asm: arm.AMOVHS, 17916 reg: regInfo{ 17917 inputs: []inputInfo{ 17918 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17919 }, 17920 outputs: []outputInfo{ 17921 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17922 }, 17923 }, 17924 }, 17925 { 17926 name: "MOVHUreg", 17927 argLen: 1, 17928 asm: arm.AMOVHU, 17929 reg: regInfo{ 17930 inputs: []inputInfo{ 17931 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17932 }, 17933 outputs: []outputInfo{ 17934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17935 }, 17936 }, 17937 }, 17938 { 17939 name: "MOVWreg", 17940 argLen: 1, 17941 asm: arm.AMOVW, 17942 reg: regInfo{ 17943 inputs: []inputInfo{ 17944 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 17945 }, 17946 outputs: []outputInfo{ 17947 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17948 }, 17949 }, 17950 }, 17951 { 17952 name: "MOVWnop", 17953 argLen: 1, 17954 resultInArg0: true, 17955 reg: regInfo{ 17956 inputs: []inputInfo{ 17957 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17958 }, 17959 outputs: []outputInfo{ 17960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17961 }, 17962 }, 17963 }, 17964 { 17965 name: "MOVWF", 17966 argLen: 1, 17967 asm: arm.AMOVWF, 17968 reg: regInfo{ 17969 inputs: []inputInfo{ 17970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17971 }, 17972 clobbers: 2147483648, // F15 17973 outputs: []outputInfo{ 17974 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17975 }, 17976 }, 17977 }, 17978 { 17979 name: "MOVWD", 17980 argLen: 1, 17981 asm: arm.AMOVWD, 17982 reg: regInfo{ 17983 inputs: []inputInfo{ 17984 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17985 }, 17986 clobbers: 2147483648, // F15 17987 outputs: []outputInfo{ 17988 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 17989 }, 17990 }, 17991 }, 17992 { 17993 name: "MOVWUF", 17994 argLen: 1, 17995 asm: arm.AMOVWF, 17996 reg: regInfo{ 17997 inputs: []inputInfo{ 17998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 17999 }, 18000 clobbers: 2147483648, // F15 18001 outputs: []outputInfo{ 18002 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18003 }, 18004 }, 18005 }, 18006 { 18007 name: "MOVWUD", 18008 argLen: 1, 18009 asm: arm.AMOVWD, 18010 reg: regInfo{ 18011 inputs: []inputInfo{ 18012 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18013 }, 18014 clobbers: 2147483648, // F15 18015 outputs: []outputInfo{ 18016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18017 }, 18018 }, 18019 }, 18020 { 18021 name: "MOVFW", 18022 argLen: 1, 18023 asm: arm.AMOVFW, 18024 reg: regInfo{ 18025 inputs: []inputInfo{ 18026 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18027 }, 18028 clobbers: 2147483648, // F15 18029 outputs: []outputInfo{ 18030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18031 }, 18032 }, 18033 }, 18034 { 18035 name: "MOVDW", 18036 argLen: 1, 18037 asm: arm.AMOVDW, 18038 reg: regInfo{ 18039 inputs: []inputInfo{ 18040 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18041 }, 18042 clobbers: 2147483648, // F15 18043 outputs: []outputInfo{ 18044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18045 }, 18046 }, 18047 }, 18048 { 18049 name: "MOVFWU", 18050 argLen: 1, 18051 asm: arm.AMOVFW, 18052 reg: regInfo{ 18053 inputs: []inputInfo{ 18054 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18055 }, 18056 clobbers: 2147483648, // F15 18057 outputs: []outputInfo{ 18058 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18059 }, 18060 }, 18061 }, 18062 { 18063 name: "MOVDWU", 18064 argLen: 1, 18065 asm: arm.AMOVDW, 18066 reg: regInfo{ 18067 inputs: []inputInfo{ 18068 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18069 }, 18070 clobbers: 2147483648, // F15 18071 outputs: []outputInfo{ 18072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18073 }, 18074 }, 18075 }, 18076 { 18077 name: "MOVFD", 18078 argLen: 1, 18079 asm: arm.AMOVFD, 18080 reg: regInfo{ 18081 inputs: []inputInfo{ 18082 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18083 }, 18084 outputs: []outputInfo{ 18085 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18086 }, 18087 }, 18088 }, 18089 { 18090 name: "MOVDF", 18091 argLen: 1, 18092 asm: arm.AMOVDF, 18093 reg: regInfo{ 18094 inputs: []inputInfo{ 18095 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18096 }, 18097 outputs: []outputInfo{ 18098 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18099 }, 18100 }, 18101 }, 18102 { 18103 name: "CMOVWHSconst", 18104 auxType: auxInt32, 18105 argLen: 2, 18106 resultInArg0: true, 18107 asm: arm.AMOVW, 18108 reg: regInfo{ 18109 inputs: []inputInfo{ 18110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18111 }, 18112 outputs: []outputInfo{ 18113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18114 }, 18115 }, 18116 }, 18117 { 18118 name: "CMOVWLSconst", 18119 auxType: auxInt32, 18120 argLen: 2, 18121 resultInArg0: true, 18122 asm: arm.AMOVW, 18123 reg: regInfo{ 18124 inputs: []inputInfo{ 18125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18126 }, 18127 outputs: []outputInfo{ 18128 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18129 }, 18130 }, 18131 }, 18132 { 18133 name: "SRAcond", 18134 argLen: 3, 18135 asm: arm.ASRA, 18136 reg: regInfo{ 18137 inputs: []inputInfo{ 18138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18139 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18140 }, 18141 outputs: []outputInfo{ 18142 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18143 }, 18144 }, 18145 }, 18146 { 18147 name: "CALLstatic", 18148 auxType: auxCallOff, 18149 argLen: 1, 18150 clobberFlags: true, 18151 call: true, 18152 reg: regInfo{ 18153 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18154 }, 18155 }, 18156 { 18157 name: "CALLtail", 18158 auxType: auxCallOff, 18159 argLen: 1, 18160 clobberFlags: true, 18161 call: true, 18162 tailCall: true, 18163 reg: regInfo{ 18164 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18165 }, 18166 }, 18167 { 18168 name: "CALLclosure", 18169 auxType: auxCallOff, 18170 argLen: 3, 18171 clobberFlags: true, 18172 call: true, 18173 reg: regInfo{ 18174 inputs: []inputInfo{ 18175 {1, 128}, // R7 18176 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 18177 }, 18178 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18179 }, 18180 }, 18181 { 18182 name: "CALLinter", 18183 auxType: auxCallOff, 18184 argLen: 2, 18185 clobberFlags: true, 18186 call: true, 18187 reg: regInfo{ 18188 inputs: []inputInfo{ 18189 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18190 }, 18191 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18192 }, 18193 }, 18194 { 18195 name: "LoweredNilCheck", 18196 argLen: 2, 18197 nilCheck: true, 18198 faultOnNilArg0: true, 18199 reg: regInfo{ 18200 inputs: []inputInfo{ 18201 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 18202 }, 18203 }, 18204 }, 18205 { 18206 name: "Equal", 18207 argLen: 1, 18208 reg: regInfo{ 18209 outputs: []outputInfo{ 18210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18211 }, 18212 }, 18213 }, 18214 { 18215 name: "NotEqual", 18216 argLen: 1, 18217 reg: regInfo{ 18218 outputs: []outputInfo{ 18219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18220 }, 18221 }, 18222 }, 18223 { 18224 name: "LessThan", 18225 argLen: 1, 18226 reg: regInfo{ 18227 outputs: []outputInfo{ 18228 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18229 }, 18230 }, 18231 }, 18232 { 18233 name: "LessEqual", 18234 argLen: 1, 18235 reg: regInfo{ 18236 outputs: []outputInfo{ 18237 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18238 }, 18239 }, 18240 }, 18241 { 18242 name: "GreaterThan", 18243 argLen: 1, 18244 reg: regInfo{ 18245 outputs: []outputInfo{ 18246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18247 }, 18248 }, 18249 }, 18250 { 18251 name: "GreaterEqual", 18252 argLen: 1, 18253 reg: regInfo{ 18254 outputs: []outputInfo{ 18255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18256 }, 18257 }, 18258 }, 18259 { 18260 name: "LessThanU", 18261 argLen: 1, 18262 reg: regInfo{ 18263 outputs: []outputInfo{ 18264 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18265 }, 18266 }, 18267 }, 18268 { 18269 name: "LessEqualU", 18270 argLen: 1, 18271 reg: regInfo{ 18272 outputs: []outputInfo{ 18273 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18274 }, 18275 }, 18276 }, 18277 { 18278 name: "GreaterThanU", 18279 argLen: 1, 18280 reg: regInfo{ 18281 outputs: []outputInfo{ 18282 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18283 }, 18284 }, 18285 }, 18286 { 18287 name: "GreaterEqualU", 18288 argLen: 1, 18289 reg: regInfo{ 18290 outputs: []outputInfo{ 18291 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18292 }, 18293 }, 18294 }, 18295 { 18296 name: "DUFFZERO", 18297 auxType: auxInt64, 18298 argLen: 3, 18299 faultOnNilArg0: true, 18300 reg: regInfo{ 18301 inputs: []inputInfo{ 18302 {0, 2}, // R1 18303 {1, 1}, // R0 18304 }, 18305 clobbers: 20482, // R1 R12 R14 18306 }, 18307 }, 18308 { 18309 name: "DUFFCOPY", 18310 auxType: auxInt64, 18311 argLen: 3, 18312 faultOnNilArg0: true, 18313 faultOnNilArg1: true, 18314 reg: regInfo{ 18315 inputs: []inputInfo{ 18316 {0, 4}, // R2 18317 {1, 2}, // R1 18318 }, 18319 clobbers: 20487, // R0 R1 R2 R12 R14 18320 }, 18321 }, 18322 { 18323 name: "LoweredZero", 18324 auxType: auxInt64, 18325 argLen: 4, 18326 clobberFlags: true, 18327 faultOnNilArg0: true, 18328 reg: regInfo{ 18329 inputs: []inputInfo{ 18330 {0, 2}, // R1 18331 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18332 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18333 }, 18334 clobbers: 2, // R1 18335 }, 18336 }, 18337 { 18338 name: "LoweredMove", 18339 auxType: auxInt64, 18340 argLen: 4, 18341 clobberFlags: true, 18342 faultOnNilArg0: true, 18343 faultOnNilArg1: true, 18344 reg: regInfo{ 18345 inputs: []inputInfo{ 18346 {0, 4}, // R2 18347 {1, 2}, // R1 18348 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18349 }, 18350 clobbers: 6, // R1 R2 18351 }, 18352 }, 18353 { 18354 name: "LoweredGetClosurePtr", 18355 argLen: 0, 18356 zeroWidth: true, 18357 reg: regInfo{ 18358 outputs: []outputInfo{ 18359 {0, 128}, // R7 18360 }, 18361 }, 18362 }, 18363 { 18364 name: "LoweredGetCallerSP", 18365 argLen: 0, 18366 rematerializeable: true, 18367 reg: regInfo{ 18368 outputs: []outputInfo{ 18369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18370 }, 18371 }, 18372 }, 18373 { 18374 name: "LoweredGetCallerPC", 18375 argLen: 0, 18376 rematerializeable: true, 18377 reg: regInfo{ 18378 outputs: []outputInfo{ 18379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 18380 }, 18381 }, 18382 }, 18383 { 18384 name: "LoweredPanicBoundsA", 18385 auxType: auxInt64, 18386 argLen: 3, 18387 call: true, 18388 reg: regInfo{ 18389 inputs: []inputInfo{ 18390 {0, 4}, // R2 18391 {1, 8}, // R3 18392 }, 18393 }, 18394 }, 18395 { 18396 name: "LoweredPanicBoundsB", 18397 auxType: auxInt64, 18398 argLen: 3, 18399 call: true, 18400 reg: regInfo{ 18401 inputs: []inputInfo{ 18402 {0, 2}, // R1 18403 {1, 4}, // R2 18404 }, 18405 }, 18406 }, 18407 { 18408 name: "LoweredPanicBoundsC", 18409 auxType: auxInt64, 18410 argLen: 3, 18411 call: true, 18412 reg: regInfo{ 18413 inputs: []inputInfo{ 18414 {0, 1}, // R0 18415 {1, 2}, // R1 18416 }, 18417 }, 18418 }, 18419 { 18420 name: "LoweredPanicExtendA", 18421 auxType: auxInt64, 18422 argLen: 4, 18423 call: true, 18424 reg: regInfo{ 18425 inputs: []inputInfo{ 18426 {0, 16}, // R4 18427 {1, 4}, // R2 18428 {2, 8}, // R3 18429 }, 18430 }, 18431 }, 18432 { 18433 name: "LoweredPanicExtendB", 18434 auxType: auxInt64, 18435 argLen: 4, 18436 call: true, 18437 reg: regInfo{ 18438 inputs: []inputInfo{ 18439 {0, 16}, // R4 18440 {1, 2}, // R1 18441 {2, 4}, // R2 18442 }, 18443 }, 18444 }, 18445 { 18446 name: "LoweredPanicExtendC", 18447 auxType: auxInt64, 18448 argLen: 4, 18449 call: true, 18450 reg: regInfo{ 18451 inputs: []inputInfo{ 18452 {0, 16}, // R4 18453 {1, 1}, // R0 18454 {2, 2}, // R1 18455 }, 18456 }, 18457 }, 18458 { 18459 name: "FlagConstant", 18460 auxType: auxFlagConstant, 18461 argLen: 0, 18462 reg: regInfo{}, 18463 }, 18464 { 18465 name: "InvertFlags", 18466 argLen: 1, 18467 reg: regInfo{}, 18468 }, 18469 { 18470 name: "LoweredWB", 18471 auxType: auxSym, 18472 argLen: 3, 18473 clobberFlags: true, 18474 symEffect: SymNone, 18475 reg: regInfo{ 18476 inputs: []inputInfo{ 18477 {0, 4}, // R2 18478 {1, 8}, // R3 18479 }, 18480 clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 18481 }, 18482 }, 18483 18484 { 18485 name: "ADCSflags", 18486 argLen: 3, 18487 commutative: true, 18488 asm: arm64.AADCS, 18489 reg: regInfo{ 18490 inputs: []inputInfo{ 18491 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18492 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18493 }, 18494 outputs: []outputInfo{ 18495 {1, 0}, 18496 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18497 }, 18498 }, 18499 }, 18500 { 18501 name: "ADCzerocarry", 18502 argLen: 1, 18503 asm: arm64.AADC, 18504 reg: regInfo{ 18505 outputs: []outputInfo{ 18506 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18507 }, 18508 }, 18509 }, 18510 { 18511 name: "ADD", 18512 argLen: 2, 18513 commutative: true, 18514 asm: arm64.AADD, 18515 reg: regInfo{ 18516 inputs: []inputInfo{ 18517 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18518 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18519 }, 18520 outputs: []outputInfo{ 18521 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18522 }, 18523 }, 18524 }, 18525 { 18526 name: "ADDconst", 18527 auxType: auxInt64, 18528 argLen: 1, 18529 asm: arm64.AADD, 18530 reg: regInfo{ 18531 inputs: []inputInfo{ 18532 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 18533 }, 18534 outputs: []outputInfo{ 18535 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18536 }, 18537 }, 18538 }, 18539 { 18540 name: "ADDSconstflags", 18541 auxType: auxInt64, 18542 argLen: 1, 18543 asm: arm64.AADDS, 18544 reg: regInfo{ 18545 inputs: []inputInfo{ 18546 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18547 }, 18548 outputs: []outputInfo{ 18549 {1, 0}, 18550 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18551 }, 18552 }, 18553 }, 18554 { 18555 name: "ADDSflags", 18556 argLen: 2, 18557 commutative: true, 18558 asm: arm64.AADDS, 18559 reg: regInfo{ 18560 inputs: []inputInfo{ 18561 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18562 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18563 }, 18564 outputs: []outputInfo{ 18565 {1, 0}, 18566 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18567 }, 18568 }, 18569 }, 18570 { 18571 name: "SUB", 18572 argLen: 2, 18573 asm: arm64.ASUB, 18574 reg: regInfo{ 18575 inputs: []inputInfo{ 18576 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18577 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18578 }, 18579 outputs: []outputInfo{ 18580 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18581 }, 18582 }, 18583 }, 18584 { 18585 name: "SUBconst", 18586 auxType: auxInt64, 18587 argLen: 1, 18588 asm: arm64.ASUB, 18589 reg: regInfo{ 18590 inputs: []inputInfo{ 18591 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18592 }, 18593 outputs: []outputInfo{ 18594 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18595 }, 18596 }, 18597 }, 18598 { 18599 name: "SBCSflags", 18600 argLen: 3, 18601 asm: arm64.ASBCS, 18602 reg: regInfo{ 18603 inputs: []inputInfo{ 18604 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18605 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18606 }, 18607 outputs: []outputInfo{ 18608 {1, 0}, 18609 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18610 }, 18611 }, 18612 }, 18613 { 18614 name: "SUBSflags", 18615 argLen: 2, 18616 asm: arm64.ASUBS, 18617 reg: regInfo{ 18618 inputs: []inputInfo{ 18619 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18620 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18621 }, 18622 outputs: []outputInfo{ 18623 {1, 0}, 18624 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18625 }, 18626 }, 18627 }, 18628 { 18629 name: "MUL", 18630 argLen: 2, 18631 commutative: true, 18632 asm: arm64.AMUL, 18633 reg: regInfo{ 18634 inputs: []inputInfo{ 18635 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18636 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18637 }, 18638 outputs: []outputInfo{ 18639 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18640 }, 18641 }, 18642 }, 18643 { 18644 name: "MULW", 18645 argLen: 2, 18646 commutative: true, 18647 asm: arm64.AMULW, 18648 reg: regInfo{ 18649 inputs: []inputInfo{ 18650 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18651 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18652 }, 18653 outputs: []outputInfo{ 18654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18655 }, 18656 }, 18657 }, 18658 { 18659 name: "MNEG", 18660 argLen: 2, 18661 commutative: true, 18662 asm: arm64.AMNEG, 18663 reg: regInfo{ 18664 inputs: []inputInfo{ 18665 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18666 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18667 }, 18668 outputs: []outputInfo{ 18669 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18670 }, 18671 }, 18672 }, 18673 { 18674 name: "MNEGW", 18675 argLen: 2, 18676 commutative: true, 18677 asm: arm64.AMNEGW, 18678 reg: regInfo{ 18679 inputs: []inputInfo{ 18680 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18681 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18682 }, 18683 outputs: []outputInfo{ 18684 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18685 }, 18686 }, 18687 }, 18688 { 18689 name: "MULH", 18690 argLen: 2, 18691 commutative: true, 18692 asm: arm64.ASMULH, 18693 reg: regInfo{ 18694 inputs: []inputInfo{ 18695 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18696 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18697 }, 18698 outputs: []outputInfo{ 18699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18700 }, 18701 }, 18702 }, 18703 { 18704 name: "UMULH", 18705 argLen: 2, 18706 commutative: true, 18707 asm: arm64.AUMULH, 18708 reg: regInfo{ 18709 inputs: []inputInfo{ 18710 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18711 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18712 }, 18713 outputs: []outputInfo{ 18714 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18715 }, 18716 }, 18717 }, 18718 { 18719 name: "MULL", 18720 argLen: 2, 18721 commutative: true, 18722 asm: arm64.ASMULL, 18723 reg: regInfo{ 18724 inputs: []inputInfo{ 18725 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18726 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18727 }, 18728 outputs: []outputInfo{ 18729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18730 }, 18731 }, 18732 }, 18733 { 18734 name: "UMULL", 18735 argLen: 2, 18736 commutative: true, 18737 asm: arm64.AUMULL, 18738 reg: regInfo{ 18739 inputs: []inputInfo{ 18740 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18741 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18742 }, 18743 outputs: []outputInfo{ 18744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18745 }, 18746 }, 18747 }, 18748 { 18749 name: "DIV", 18750 argLen: 2, 18751 asm: arm64.ASDIV, 18752 reg: regInfo{ 18753 inputs: []inputInfo{ 18754 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18755 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18756 }, 18757 outputs: []outputInfo{ 18758 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18759 }, 18760 }, 18761 }, 18762 { 18763 name: "UDIV", 18764 argLen: 2, 18765 asm: arm64.AUDIV, 18766 reg: regInfo{ 18767 inputs: []inputInfo{ 18768 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18769 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18770 }, 18771 outputs: []outputInfo{ 18772 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18773 }, 18774 }, 18775 }, 18776 { 18777 name: "DIVW", 18778 argLen: 2, 18779 asm: arm64.ASDIVW, 18780 reg: regInfo{ 18781 inputs: []inputInfo{ 18782 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18783 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18784 }, 18785 outputs: []outputInfo{ 18786 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18787 }, 18788 }, 18789 }, 18790 { 18791 name: "UDIVW", 18792 argLen: 2, 18793 asm: arm64.AUDIVW, 18794 reg: regInfo{ 18795 inputs: []inputInfo{ 18796 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18797 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18798 }, 18799 outputs: []outputInfo{ 18800 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18801 }, 18802 }, 18803 }, 18804 { 18805 name: "MOD", 18806 argLen: 2, 18807 asm: arm64.AREM, 18808 reg: regInfo{ 18809 inputs: []inputInfo{ 18810 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18811 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18812 }, 18813 outputs: []outputInfo{ 18814 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18815 }, 18816 }, 18817 }, 18818 { 18819 name: "UMOD", 18820 argLen: 2, 18821 asm: arm64.AUREM, 18822 reg: regInfo{ 18823 inputs: []inputInfo{ 18824 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18825 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18826 }, 18827 outputs: []outputInfo{ 18828 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18829 }, 18830 }, 18831 }, 18832 { 18833 name: "MODW", 18834 argLen: 2, 18835 asm: arm64.AREMW, 18836 reg: regInfo{ 18837 inputs: []inputInfo{ 18838 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18839 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18840 }, 18841 outputs: []outputInfo{ 18842 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18843 }, 18844 }, 18845 }, 18846 { 18847 name: "UMODW", 18848 argLen: 2, 18849 asm: arm64.AUREMW, 18850 reg: regInfo{ 18851 inputs: []inputInfo{ 18852 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18853 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 18854 }, 18855 outputs: []outputInfo{ 18856 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 18857 }, 18858 }, 18859 }, 18860 { 18861 name: "FADDS", 18862 argLen: 2, 18863 commutative: true, 18864 asm: arm64.AFADDS, 18865 reg: regInfo{ 18866 inputs: []inputInfo{ 18867 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18868 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18869 }, 18870 outputs: []outputInfo{ 18871 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18872 }, 18873 }, 18874 }, 18875 { 18876 name: "FADDD", 18877 argLen: 2, 18878 commutative: true, 18879 asm: arm64.AFADDD, 18880 reg: regInfo{ 18881 inputs: []inputInfo{ 18882 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18883 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18884 }, 18885 outputs: []outputInfo{ 18886 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18887 }, 18888 }, 18889 }, 18890 { 18891 name: "FSUBS", 18892 argLen: 2, 18893 asm: arm64.AFSUBS, 18894 reg: regInfo{ 18895 inputs: []inputInfo{ 18896 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18897 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18898 }, 18899 outputs: []outputInfo{ 18900 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18901 }, 18902 }, 18903 }, 18904 { 18905 name: "FSUBD", 18906 argLen: 2, 18907 asm: arm64.AFSUBD, 18908 reg: regInfo{ 18909 inputs: []inputInfo{ 18910 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18911 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18912 }, 18913 outputs: []outputInfo{ 18914 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18915 }, 18916 }, 18917 }, 18918 { 18919 name: "FMULS", 18920 argLen: 2, 18921 commutative: true, 18922 asm: arm64.AFMULS, 18923 reg: regInfo{ 18924 inputs: []inputInfo{ 18925 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18926 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18927 }, 18928 outputs: []outputInfo{ 18929 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18930 }, 18931 }, 18932 }, 18933 { 18934 name: "FMULD", 18935 argLen: 2, 18936 commutative: true, 18937 asm: arm64.AFMULD, 18938 reg: regInfo{ 18939 inputs: []inputInfo{ 18940 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18941 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18942 }, 18943 outputs: []outputInfo{ 18944 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18945 }, 18946 }, 18947 }, 18948 { 18949 name: "FNMULS", 18950 argLen: 2, 18951 commutative: true, 18952 asm: arm64.AFNMULS, 18953 reg: regInfo{ 18954 inputs: []inputInfo{ 18955 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18956 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18957 }, 18958 outputs: []outputInfo{ 18959 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18960 }, 18961 }, 18962 }, 18963 { 18964 name: "FNMULD", 18965 argLen: 2, 18966 commutative: true, 18967 asm: arm64.AFNMULD, 18968 reg: regInfo{ 18969 inputs: []inputInfo{ 18970 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18971 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18972 }, 18973 outputs: []outputInfo{ 18974 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18975 }, 18976 }, 18977 }, 18978 { 18979 name: "FDIVS", 18980 argLen: 2, 18981 asm: arm64.AFDIVS, 18982 reg: regInfo{ 18983 inputs: []inputInfo{ 18984 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18985 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18986 }, 18987 outputs: []outputInfo{ 18988 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18989 }, 18990 }, 18991 }, 18992 { 18993 name: "FDIVD", 18994 argLen: 2, 18995 asm: arm64.AFDIVD, 18996 reg: regInfo{ 18997 inputs: []inputInfo{ 18998 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 18999 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19000 }, 19001 outputs: []outputInfo{ 19002 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19003 }, 19004 }, 19005 }, 19006 { 19007 name: "AND", 19008 argLen: 2, 19009 commutative: true, 19010 asm: arm64.AAND, 19011 reg: regInfo{ 19012 inputs: []inputInfo{ 19013 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19014 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19015 }, 19016 outputs: []outputInfo{ 19017 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19018 }, 19019 }, 19020 }, 19021 { 19022 name: "ANDconst", 19023 auxType: auxInt64, 19024 argLen: 1, 19025 asm: arm64.AAND, 19026 reg: regInfo{ 19027 inputs: []inputInfo{ 19028 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19029 }, 19030 outputs: []outputInfo{ 19031 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19032 }, 19033 }, 19034 }, 19035 { 19036 name: "OR", 19037 argLen: 2, 19038 commutative: true, 19039 asm: arm64.AORR, 19040 reg: regInfo{ 19041 inputs: []inputInfo{ 19042 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19043 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19044 }, 19045 outputs: []outputInfo{ 19046 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19047 }, 19048 }, 19049 }, 19050 { 19051 name: "ORconst", 19052 auxType: auxInt64, 19053 argLen: 1, 19054 asm: arm64.AORR, 19055 reg: regInfo{ 19056 inputs: []inputInfo{ 19057 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19058 }, 19059 outputs: []outputInfo{ 19060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19061 }, 19062 }, 19063 }, 19064 { 19065 name: "XOR", 19066 argLen: 2, 19067 commutative: true, 19068 asm: arm64.AEOR, 19069 reg: regInfo{ 19070 inputs: []inputInfo{ 19071 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19072 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19073 }, 19074 outputs: []outputInfo{ 19075 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19076 }, 19077 }, 19078 }, 19079 { 19080 name: "XORconst", 19081 auxType: auxInt64, 19082 argLen: 1, 19083 asm: arm64.AEOR, 19084 reg: regInfo{ 19085 inputs: []inputInfo{ 19086 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19087 }, 19088 outputs: []outputInfo{ 19089 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19090 }, 19091 }, 19092 }, 19093 { 19094 name: "BIC", 19095 argLen: 2, 19096 asm: arm64.ABIC, 19097 reg: regInfo{ 19098 inputs: []inputInfo{ 19099 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19100 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19101 }, 19102 outputs: []outputInfo{ 19103 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19104 }, 19105 }, 19106 }, 19107 { 19108 name: "EON", 19109 argLen: 2, 19110 asm: arm64.AEON, 19111 reg: regInfo{ 19112 inputs: []inputInfo{ 19113 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19114 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19115 }, 19116 outputs: []outputInfo{ 19117 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19118 }, 19119 }, 19120 }, 19121 { 19122 name: "ORN", 19123 argLen: 2, 19124 asm: arm64.AORN, 19125 reg: regInfo{ 19126 inputs: []inputInfo{ 19127 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19128 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19129 }, 19130 outputs: []outputInfo{ 19131 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19132 }, 19133 }, 19134 }, 19135 { 19136 name: "MVN", 19137 argLen: 1, 19138 asm: arm64.AMVN, 19139 reg: regInfo{ 19140 inputs: []inputInfo{ 19141 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19142 }, 19143 outputs: []outputInfo{ 19144 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19145 }, 19146 }, 19147 }, 19148 { 19149 name: "NEG", 19150 argLen: 1, 19151 asm: arm64.ANEG, 19152 reg: regInfo{ 19153 inputs: []inputInfo{ 19154 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19155 }, 19156 outputs: []outputInfo{ 19157 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19158 }, 19159 }, 19160 }, 19161 { 19162 name: "NEGSflags", 19163 argLen: 1, 19164 asm: arm64.ANEGS, 19165 reg: regInfo{ 19166 inputs: []inputInfo{ 19167 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19168 }, 19169 outputs: []outputInfo{ 19170 {1, 0}, 19171 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19172 }, 19173 }, 19174 }, 19175 { 19176 name: "NGCzerocarry", 19177 argLen: 1, 19178 asm: arm64.ANGC, 19179 reg: regInfo{ 19180 outputs: []outputInfo{ 19181 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19182 }, 19183 }, 19184 }, 19185 { 19186 name: "FABSD", 19187 argLen: 1, 19188 asm: arm64.AFABSD, 19189 reg: regInfo{ 19190 inputs: []inputInfo{ 19191 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19192 }, 19193 outputs: []outputInfo{ 19194 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19195 }, 19196 }, 19197 }, 19198 { 19199 name: "FNEGS", 19200 argLen: 1, 19201 asm: arm64.AFNEGS, 19202 reg: regInfo{ 19203 inputs: []inputInfo{ 19204 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19205 }, 19206 outputs: []outputInfo{ 19207 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19208 }, 19209 }, 19210 }, 19211 { 19212 name: "FNEGD", 19213 argLen: 1, 19214 asm: arm64.AFNEGD, 19215 reg: regInfo{ 19216 inputs: []inputInfo{ 19217 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19218 }, 19219 outputs: []outputInfo{ 19220 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19221 }, 19222 }, 19223 }, 19224 { 19225 name: "FSQRTD", 19226 argLen: 1, 19227 asm: arm64.AFSQRTD, 19228 reg: regInfo{ 19229 inputs: []inputInfo{ 19230 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19231 }, 19232 outputs: []outputInfo{ 19233 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19234 }, 19235 }, 19236 }, 19237 { 19238 name: "FSQRTS", 19239 argLen: 1, 19240 asm: arm64.AFSQRTS, 19241 reg: regInfo{ 19242 inputs: []inputInfo{ 19243 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19244 }, 19245 outputs: []outputInfo{ 19246 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19247 }, 19248 }, 19249 }, 19250 { 19251 name: "REV", 19252 argLen: 1, 19253 asm: arm64.AREV, 19254 reg: regInfo{ 19255 inputs: []inputInfo{ 19256 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19257 }, 19258 outputs: []outputInfo{ 19259 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19260 }, 19261 }, 19262 }, 19263 { 19264 name: "REVW", 19265 argLen: 1, 19266 asm: arm64.AREVW, 19267 reg: regInfo{ 19268 inputs: []inputInfo{ 19269 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19270 }, 19271 outputs: []outputInfo{ 19272 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19273 }, 19274 }, 19275 }, 19276 { 19277 name: "REV16", 19278 argLen: 1, 19279 asm: arm64.AREV16, 19280 reg: regInfo{ 19281 inputs: []inputInfo{ 19282 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19283 }, 19284 outputs: []outputInfo{ 19285 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19286 }, 19287 }, 19288 }, 19289 { 19290 name: "REV16W", 19291 argLen: 1, 19292 asm: arm64.AREV16W, 19293 reg: regInfo{ 19294 inputs: []inputInfo{ 19295 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19296 }, 19297 outputs: []outputInfo{ 19298 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19299 }, 19300 }, 19301 }, 19302 { 19303 name: "RBIT", 19304 argLen: 1, 19305 asm: arm64.ARBIT, 19306 reg: regInfo{ 19307 inputs: []inputInfo{ 19308 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19309 }, 19310 outputs: []outputInfo{ 19311 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19312 }, 19313 }, 19314 }, 19315 { 19316 name: "RBITW", 19317 argLen: 1, 19318 asm: arm64.ARBITW, 19319 reg: regInfo{ 19320 inputs: []inputInfo{ 19321 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19322 }, 19323 outputs: []outputInfo{ 19324 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19325 }, 19326 }, 19327 }, 19328 { 19329 name: "CLZ", 19330 argLen: 1, 19331 asm: arm64.ACLZ, 19332 reg: regInfo{ 19333 inputs: []inputInfo{ 19334 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19335 }, 19336 outputs: []outputInfo{ 19337 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19338 }, 19339 }, 19340 }, 19341 { 19342 name: "CLZW", 19343 argLen: 1, 19344 asm: arm64.ACLZW, 19345 reg: regInfo{ 19346 inputs: []inputInfo{ 19347 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19348 }, 19349 outputs: []outputInfo{ 19350 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19351 }, 19352 }, 19353 }, 19354 { 19355 name: "VCNT", 19356 argLen: 1, 19357 asm: arm64.AVCNT, 19358 reg: regInfo{ 19359 inputs: []inputInfo{ 19360 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19361 }, 19362 outputs: []outputInfo{ 19363 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19364 }, 19365 }, 19366 }, 19367 { 19368 name: "VUADDLV", 19369 argLen: 1, 19370 asm: arm64.AVUADDLV, 19371 reg: regInfo{ 19372 inputs: []inputInfo{ 19373 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19374 }, 19375 outputs: []outputInfo{ 19376 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19377 }, 19378 }, 19379 }, 19380 { 19381 name: "LoweredRound32F", 19382 argLen: 1, 19383 resultInArg0: true, 19384 zeroWidth: true, 19385 reg: regInfo{ 19386 inputs: []inputInfo{ 19387 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19388 }, 19389 outputs: []outputInfo{ 19390 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19391 }, 19392 }, 19393 }, 19394 { 19395 name: "LoweredRound64F", 19396 argLen: 1, 19397 resultInArg0: true, 19398 zeroWidth: true, 19399 reg: regInfo{ 19400 inputs: []inputInfo{ 19401 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19402 }, 19403 outputs: []outputInfo{ 19404 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19405 }, 19406 }, 19407 }, 19408 { 19409 name: "FMADDS", 19410 argLen: 3, 19411 asm: arm64.AFMADDS, 19412 reg: regInfo{ 19413 inputs: []inputInfo{ 19414 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19415 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19416 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19417 }, 19418 outputs: []outputInfo{ 19419 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19420 }, 19421 }, 19422 }, 19423 { 19424 name: "FMADDD", 19425 argLen: 3, 19426 asm: arm64.AFMADDD, 19427 reg: regInfo{ 19428 inputs: []inputInfo{ 19429 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19430 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19431 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19432 }, 19433 outputs: []outputInfo{ 19434 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19435 }, 19436 }, 19437 }, 19438 { 19439 name: "FNMADDS", 19440 argLen: 3, 19441 asm: arm64.AFNMADDS, 19442 reg: regInfo{ 19443 inputs: []inputInfo{ 19444 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19445 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19446 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19447 }, 19448 outputs: []outputInfo{ 19449 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19450 }, 19451 }, 19452 }, 19453 { 19454 name: "FNMADDD", 19455 argLen: 3, 19456 asm: arm64.AFNMADDD, 19457 reg: regInfo{ 19458 inputs: []inputInfo{ 19459 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19460 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19461 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19462 }, 19463 outputs: []outputInfo{ 19464 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19465 }, 19466 }, 19467 }, 19468 { 19469 name: "FMSUBS", 19470 argLen: 3, 19471 asm: arm64.AFMSUBS, 19472 reg: regInfo{ 19473 inputs: []inputInfo{ 19474 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19475 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19476 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19477 }, 19478 outputs: []outputInfo{ 19479 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19480 }, 19481 }, 19482 }, 19483 { 19484 name: "FMSUBD", 19485 argLen: 3, 19486 asm: arm64.AFMSUBD, 19487 reg: regInfo{ 19488 inputs: []inputInfo{ 19489 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19490 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19491 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19492 }, 19493 outputs: []outputInfo{ 19494 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19495 }, 19496 }, 19497 }, 19498 { 19499 name: "FNMSUBS", 19500 argLen: 3, 19501 asm: arm64.AFNMSUBS, 19502 reg: regInfo{ 19503 inputs: []inputInfo{ 19504 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19505 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19506 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19507 }, 19508 outputs: []outputInfo{ 19509 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19510 }, 19511 }, 19512 }, 19513 { 19514 name: "FNMSUBD", 19515 argLen: 3, 19516 asm: arm64.AFNMSUBD, 19517 reg: regInfo{ 19518 inputs: []inputInfo{ 19519 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19520 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19521 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19522 }, 19523 outputs: []outputInfo{ 19524 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19525 }, 19526 }, 19527 }, 19528 { 19529 name: "MADD", 19530 argLen: 3, 19531 asm: arm64.AMADD, 19532 reg: regInfo{ 19533 inputs: []inputInfo{ 19534 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19535 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19536 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19537 }, 19538 outputs: []outputInfo{ 19539 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19540 }, 19541 }, 19542 }, 19543 { 19544 name: "MADDW", 19545 argLen: 3, 19546 asm: arm64.AMADDW, 19547 reg: regInfo{ 19548 inputs: []inputInfo{ 19549 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19550 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19551 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19552 }, 19553 outputs: []outputInfo{ 19554 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19555 }, 19556 }, 19557 }, 19558 { 19559 name: "MSUB", 19560 argLen: 3, 19561 asm: arm64.AMSUB, 19562 reg: regInfo{ 19563 inputs: []inputInfo{ 19564 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19565 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19566 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19567 }, 19568 outputs: []outputInfo{ 19569 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19570 }, 19571 }, 19572 }, 19573 { 19574 name: "MSUBW", 19575 argLen: 3, 19576 asm: arm64.AMSUBW, 19577 reg: regInfo{ 19578 inputs: []inputInfo{ 19579 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19580 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19581 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19582 }, 19583 outputs: []outputInfo{ 19584 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19585 }, 19586 }, 19587 }, 19588 { 19589 name: "SLL", 19590 argLen: 2, 19591 asm: arm64.ALSL, 19592 reg: regInfo{ 19593 inputs: []inputInfo{ 19594 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19595 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19596 }, 19597 outputs: []outputInfo{ 19598 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19599 }, 19600 }, 19601 }, 19602 { 19603 name: "SLLconst", 19604 auxType: auxInt64, 19605 argLen: 1, 19606 asm: arm64.ALSL, 19607 reg: regInfo{ 19608 inputs: []inputInfo{ 19609 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19610 }, 19611 outputs: []outputInfo{ 19612 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19613 }, 19614 }, 19615 }, 19616 { 19617 name: "SRL", 19618 argLen: 2, 19619 asm: arm64.ALSR, 19620 reg: regInfo{ 19621 inputs: []inputInfo{ 19622 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19623 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19624 }, 19625 outputs: []outputInfo{ 19626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19627 }, 19628 }, 19629 }, 19630 { 19631 name: "SRLconst", 19632 auxType: auxInt64, 19633 argLen: 1, 19634 asm: arm64.ALSR, 19635 reg: regInfo{ 19636 inputs: []inputInfo{ 19637 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19638 }, 19639 outputs: []outputInfo{ 19640 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19641 }, 19642 }, 19643 }, 19644 { 19645 name: "SRA", 19646 argLen: 2, 19647 asm: arm64.AASR, 19648 reg: regInfo{ 19649 inputs: []inputInfo{ 19650 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19651 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19652 }, 19653 outputs: []outputInfo{ 19654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19655 }, 19656 }, 19657 }, 19658 { 19659 name: "SRAconst", 19660 auxType: auxInt64, 19661 argLen: 1, 19662 asm: arm64.AASR, 19663 reg: regInfo{ 19664 inputs: []inputInfo{ 19665 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19666 }, 19667 outputs: []outputInfo{ 19668 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19669 }, 19670 }, 19671 }, 19672 { 19673 name: "ROR", 19674 argLen: 2, 19675 asm: arm64.AROR, 19676 reg: regInfo{ 19677 inputs: []inputInfo{ 19678 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19680 }, 19681 outputs: []outputInfo{ 19682 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19683 }, 19684 }, 19685 }, 19686 { 19687 name: "RORW", 19688 argLen: 2, 19689 asm: arm64.ARORW, 19690 reg: regInfo{ 19691 inputs: []inputInfo{ 19692 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19693 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19694 }, 19695 outputs: []outputInfo{ 19696 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19697 }, 19698 }, 19699 }, 19700 { 19701 name: "RORconst", 19702 auxType: auxInt64, 19703 argLen: 1, 19704 asm: arm64.AROR, 19705 reg: regInfo{ 19706 inputs: []inputInfo{ 19707 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19708 }, 19709 outputs: []outputInfo{ 19710 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19711 }, 19712 }, 19713 }, 19714 { 19715 name: "RORWconst", 19716 auxType: auxInt64, 19717 argLen: 1, 19718 asm: arm64.ARORW, 19719 reg: regInfo{ 19720 inputs: []inputInfo{ 19721 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19722 }, 19723 outputs: []outputInfo{ 19724 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19725 }, 19726 }, 19727 }, 19728 { 19729 name: "EXTRconst", 19730 auxType: auxInt64, 19731 argLen: 2, 19732 asm: arm64.AEXTR, 19733 reg: regInfo{ 19734 inputs: []inputInfo{ 19735 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19736 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19737 }, 19738 outputs: []outputInfo{ 19739 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19740 }, 19741 }, 19742 }, 19743 { 19744 name: "EXTRWconst", 19745 auxType: auxInt64, 19746 argLen: 2, 19747 asm: arm64.AEXTRW, 19748 reg: regInfo{ 19749 inputs: []inputInfo{ 19750 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19751 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19752 }, 19753 outputs: []outputInfo{ 19754 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19755 }, 19756 }, 19757 }, 19758 { 19759 name: "CMP", 19760 argLen: 2, 19761 asm: arm64.ACMP, 19762 reg: regInfo{ 19763 inputs: []inputInfo{ 19764 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19765 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19766 }, 19767 }, 19768 }, 19769 { 19770 name: "CMPconst", 19771 auxType: auxInt64, 19772 argLen: 1, 19773 asm: arm64.ACMP, 19774 reg: regInfo{ 19775 inputs: []inputInfo{ 19776 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19777 }, 19778 }, 19779 }, 19780 { 19781 name: "CMPW", 19782 argLen: 2, 19783 asm: arm64.ACMPW, 19784 reg: regInfo{ 19785 inputs: []inputInfo{ 19786 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19787 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19788 }, 19789 }, 19790 }, 19791 { 19792 name: "CMPWconst", 19793 auxType: auxInt32, 19794 argLen: 1, 19795 asm: arm64.ACMPW, 19796 reg: regInfo{ 19797 inputs: []inputInfo{ 19798 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19799 }, 19800 }, 19801 }, 19802 { 19803 name: "CMN", 19804 argLen: 2, 19805 commutative: true, 19806 asm: arm64.ACMN, 19807 reg: regInfo{ 19808 inputs: []inputInfo{ 19809 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19810 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19811 }, 19812 }, 19813 }, 19814 { 19815 name: "CMNconst", 19816 auxType: auxInt64, 19817 argLen: 1, 19818 asm: arm64.ACMN, 19819 reg: regInfo{ 19820 inputs: []inputInfo{ 19821 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19822 }, 19823 }, 19824 }, 19825 { 19826 name: "CMNW", 19827 argLen: 2, 19828 commutative: true, 19829 asm: arm64.ACMNW, 19830 reg: regInfo{ 19831 inputs: []inputInfo{ 19832 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19833 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19834 }, 19835 }, 19836 }, 19837 { 19838 name: "CMNWconst", 19839 auxType: auxInt32, 19840 argLen: 1, 19841 asm: arm64.ACMNW, 19842 reg: regInfo{ 19843 inputs: []inputInfo{ 19844 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19845 }, 19846 }, 19847 }, 19848 { 19849 name: "TST", 19850 argLen: 2, 19851 commutative: true, 19852 asm: arm64.ATST, 19853 reg: regInfo{ 19854 inputs: []inputInfo{ 19855 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19856 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19857 }, 19858 }, 19859 }, 19860 { 19861 name: "TSTconst", 19862 auxType: auxInt64, 19863 argLen: 1, 19864 asm: arm64.ATST, 19865 reg: regInfo{ 19866 inputs: []inputInfo{ 19867 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19868 }, 19869 }, 19870 }, 19871 { 19872 name: "TSTW", 19873 argLen: 2, 19874 commutative: true, 19875 asm: arm64.ATSTW, 19876 reg: regInfo{ 19877 inputs: []inputInfo{ 19878 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19879 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19880 }, 19881 }, 19882 }, 19883 { 19884 name: "TSTWconst", 19885 auxType: auxInt32, 19886 argLen: 1, 19887 asm: arm64.ATSTW, 19888 reg: regInfo{ 19889 inputs: []inputInfo{ 19890 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19891 }, 19892 }, 19893 }, 19894 { 19895 name: "FCMPS", 19896 argLen: 2, 19897 asm: arm64.AFCMPS, 19898 reg: regInfo{ 19899 inputs: []inputInfo{ 19900 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19901 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19902 }, 19903 }, 19904 }, 19905 { 19906 name: "FCMPD", 19907 argLen: 2, 19908 asm: arm64.AFCMPD, 19909 reg: regInfo{ 19910 inputs: []inputInfo{ 19911 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19912 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19913 }, 19914 }, 19915 }, 19916 { 19917 name: "FCMPS0", 19918 argLen: 1, 19919 asm: arm64.AFCMPS, 19920 reg: regInfo{ 19921 inputs: []inputInfo{ 19922 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19923 }, 19924 }, 19925 }, 19926 { 19927 name: "FCMPD0", 19928 argLen: 1, 19929 asm: arm64.AFCMPD, 19930 reg: regInfo{ 19931 inputs: []inputInfo{ 19932 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 19933 }, 19934 }, 19935 }, 19936 { 19937 name: "MVNshiftLL", 19938 auxType: auxInt64, 19939 argLen: 1, 19940 asm: arm64.AMVN, 19941 reg: regInfo{ 19942 inputs: []inputInfo{ 19943 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19944 }, 19945 outputs: []outputInfo{ 19946 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19947 }, 19948 }, 19949 }, 19950 { 19951 name: "MVNshiftRL", 19952 auxType: auxInt64, 19953 argLen: 1, 19954 asm: arm64.AMVN, 19955 reg: regInfo{ 19956 inputs: []inputInfo{ 19957 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19958 }, 19959 outputs: []outputInfo{ 19960 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19961 }, 19962 }, 19963 }, 19964 { 19965 name: "MVNshiftRA", 19966 auxType: auxInt64, 19967 argLen: 1, 19968 asm: arm64.AMVN, 19969 reg: regInfo{ 19970 inputs: []inputInfo{ 19971 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19972 }, 19973 outputs: []outputInfo{ 19974 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19975 }, 19976 }, 19977 }, 19978 { 19979 name: "MVNshiftRO", 19980 auxType: auxInt64, 19981 argLen: 1, 19982 asm: arm64.AMVN, 19983 reg: regInfo{ 19984 inputs: []inputInfo{ 19985 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 19986 }, 19987 outputs: []outputInfo{ 19988 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 19989 }, 19990 }, 19991 }, 19992 { 19993 name: "NEGshiftLL", 19994 auxType: auxInt64, 19995 argLen: 1, 19996 asm: arm64.ANEG, 19997 reg: regInfo{ 19998 inputs: []inputInfo{ 19999 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20000 }, 20001 outputs: []outputInfo{ 20002 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20003 }, 20004 }, 20005 }, 20006 { 20007 name: "NEGshiftRL", 20008 auxType: auxInt64, 20009 argLen: 1, 20010 asm: arm64.ANEG, 20011 reg: regInfo{ 20012 inputs: []inputInfo{ 20013 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20014 }, 20015 outputs: []outputInfo{ 20016 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20017 }, 20018 }, 20019 }, 20020 { 20021 name: "NEGshiftRA", 20022 auxType: auxInt64, 20023 argLen: 1, 20024 asm: arm64.ANEG, 20025 reg: regInfo{ 20026 inputs: []inputInfo{ 20027 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20028 }, 20029 outputs: []outputInfo{ 20030 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20031 }, 20032 }, 20033 }, 20034 { 20035 name: "ADDshiftLL", 20036 auxType: auxInt64, 20037 argLen: 2, 20038 asm: arm64.AADD, 20039 reg: regInfo{ 20040 inputs: []inputInfo{ 20041 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20042 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20043 }, 20044 outputs: []outputInfo{ 20045 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20046 }, 20047 }, 20048 }, 20049 { 20050 name: "ADDshiftRL", 20051 auxType: auxInt64, 20052 argLen: 2, 20053 asm: arm64.AADD, 20054 reg: regInfo{ 20055 inputs: []inputInfo{ 20056 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20057 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20058 }, 20059 outputs: []outputInfo{ 20060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20061 }, 20062 }, 20063 }, 20064 { 20065 name: "ADDshiftRA", 20066 auxType: auxInt64, 20067 argLen: 2, 20068 asm: arm64.AADD, 20069 reg: regInfo{ 20070 inputs: []inputInfo{ 20071 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20072 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20073 }, 20074 outputs: []outputInfo{ 20075 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20076 }, 20077 }, 20078 }, 20079 { 20080 name: "SUBshiftLL", 20081 auxType: auxInt64, 20082 argLen: 2, 20083 asm: arm64.ASUB, 20084 reg: regInfo{ 20085 inputs: []inputInfo{ 20086 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20087 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20088 }, 20089 outputs: []outputInfo{ 20090 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20091 }, 20092 }, 20093 }, 20094 { 20095 name: "SUBshiftRL", 20096 auxType: auxInt64, 20097 argLen: 2, 20098 asm: arm64.ASUB, 20099 reg: regInfo{ 20100 inputs: []inputInfo{ 20101 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20102 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20103 }, 20104 outputs: []outputInfo{ 20105 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20106 }, 20107 }, 20108 }, 20109 { 20110 name: "SUBshiftRA", 20111 auxType: auxInt64, 20112 argLen: 2, 20113 asm: arm64.ASUB, 20114 reg: regInfo{ 20115 inputs: []inputInfo{ 20116 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20117 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20118 }, 20119 outputs: []outputInfo{ 20120 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20121 }, 20122 }, 20123 }, 20124 { 20125 name: "ANDshiftLL", 20126 auxType: auxInt64, 20127 argLen: 2, 20128 asm: arm64.AAND, 20129 reg: regInfo{ 20130 inputs: []inputInfo{ 20131 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20132 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20133 }, 20134 outputs: []outputInfo{ 20135 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20136 }, 20137 }, 20138 }, 20139 { 20140 name: "ANDshiftRL", 20141 auxType: auxInt64, 20142 argLen: 2, 20143 asm: arm64.AAND, 20144 reg: regInfo{ 20145 inputs: []inputInfo{ 20146 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20147 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20148 }, 20149 outputs: []outputInfo{ 20150 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20151 }, 20152 }, 20153 }, 20154 { 20155 name: "ANDshiftRA", 20156 auxType: auxInt64, 20157 argLen: 2, 20158 asm: arm64.AAND, 20159 reg: regInfo{ 20160 inputs: []inputInfo{ 20161 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20162 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20163 }, 20164 outputs: []outputInfo{ 20165 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20166 }, 20167 }, 20168 }, 20169 { 20170 name: "ANDshiftRO", 20171 auxType: auxInt64, 20172 argLen: 2, 20173 asm: arm64.AAND, 20174 reg: regInfo{ 20175 inputs: []inputInfo{ 20176 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20177 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20178 }, 20179 outputs: []outputInfo{ 20180 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20181 }, 20182 }, 20183 }, 20184 { 20185 name: "ORshiftLL", 20186 auxType: auxInt64, 20187 argLen: 2, 20188 asm: arm64.AORR, 20189 reg: regInfo{ 20190 inputs: []inputInfo{ 20191 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20192 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20193 }, 20194 outputs: []outputInfo{ 20195 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20196 }, 20197 }, 20198 }, 20199 { 20200 name: "ORshiftRL", 20201 auxType: auxInt64, 20202 argLen: 2, 20203 asm: arm64.AORR, 20204 reg: regInfo{ 20205 inputs: []inputInfo{ 20206 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20207 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20208 }, 20209 outputs: []outputInfo{ 20210 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20211 }, 20212 }, 20213 }, 20214 { 20215 name: "ORshiftRA", 20216 auxType: auxInt64, 20217 argLen: 2, 20218 asm: arm64.AORR, 20219 reg: regInfo{ 20220 inputs: []inputInfo{ 20221 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20222 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20223 }, 20224 outputs: []outputInfo{ 20225 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20226 }, 20227 }, 20228 }, 20229 { 20230 name: "ORshiftRO", 20231 auxType: auxInt64, 20232 argLen: 2, 20233 asm: arm64.AORR, 20234 reg: regInfo{ 20235 inputs: []inputInfo{ 20236 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20237 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20238 }, 20239 outputs: []outputInfo{ 20240 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20241 }, 20242 }, 20243 }, 20244 { 20245 name: "XORshiftLL", 20246 auxType: auxInt64, 20247 argLen: 2, 20248 asm: arm64.AEOR, 20249 reg: regInfo{ 20250 inputs: []inputInfo{ 20251 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20252 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20253 }, 20254 outputs: []outputInfo{ 20255 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20256 }, 20257 }, 20258 }, 20259 { 20260 name: "XORshiftRL", 20261 auxType: auxInt64, 20262 argLen: 2, 20263 asm: arm64.AEOR, 20264 reg: regInfo{ 20265 inputs: []inputInfo{ 20266 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20267 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20268 }, 20269 outputs: []outputInfo{ 20270 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20271 }, 20272 }, 20273 }, 20274 { 20275 name: "XORshiftRA", 20276 auxType: auxInt64, 20277 argLen: 2, 20278 asm: arm64.AEOR, 20279 reg: regInfo{ 20280 inputs: []inputInfo{ 20281 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20282 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20283 }, 20284 outputs: []outputInfo{ 20285 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20286 }, 20287 }, 20288 }, 20289 { 20290 name: "XORshiftRO", 20291 auxType: auxInt64, 20292 argLen: 2, 20293 asm: arm64.AEOR, 20294 reg: regInfo{ 20295 inputs: []inputInfo{ 20296 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20297 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20298 }, 20299 outputs: []outputInfo{ 20300 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20301 }, 20302 }, 20303 }, 20304 { 20305 name: "BICshiftLL", 20306 auxType: auxInt64, 20307 argLen: 2, 20308 asm: arm64.ABIC, 20309 reg: regInfo{ 20310 inputs: []inputInfo{ 20311 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20312 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20313 }, 20314 outputs: []outputInfo{ 20315 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20316 }, 20317 }, 20318 }, 20319 { 20320 name: "BICshiftRL", 20321 auxType: auxInt64, 20322 argLen: 2, 20323 asm: arm64.ABIC, 20324 reg: regInfo{ 20325 inputs: []inputInfo{ 20326 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20327 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20328 }, 20329 outputs: []outputInfo{ 20330 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20331 }, 20332 }, 20333 }, 20334 { 20335 name: "BICshiftRA", 20336 auxType: auxInt64, 20337 argLen: 2, 20338 asm: arm64.ABIC, 20339 reg: regInfo{ 20340 inputs: []inputInfo{ 20341 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20342 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20343 }, 20344 outputs: []outputInfo{ 20345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20346 }, 20347 }, 20348 }, 20349 { 20350 name: "BICshiftRO", 20351 auxType: auxInt64, 20352 argLen: 2, 20353 asm: arm64.ABIC, 20354 reg: regInfo{ 20355 inputs: []inputInfo{ 20356 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20357 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20358 }, 20359 outputs: []outputInfo{ 20360 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20361 }, 20362 }, 20363 }, 20364 { 20365 name: "EONshiftLL", 20366 auxType: auxInt64, 20367 argLen: 2, 20368 asm: arm64.AEON, 20369 reg: regInfo{ 20370 inputs: []inputInfo{ 20371 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20372 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20373 }, 20374 outputs: []outputInfo{ 20375 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20376 }, 20377 }, 20378 }, 20379 { 20380 name: "EONshiftRL", 20381 auxType: auxInt64, 20382 argLen: 2, 20383 asm: arm64.AEON, 20384 reg: regInfo{ 20385 inputs: []inputInfo{ 20386 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20387 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20388 }, 20389 outputs: []outputInfo{ 20390 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20391 }, 20392 }, 20393 }, 20394 { 20395 name: "EONshiftRA", 20396 auxType: auxInt64, 20397 argLen: 2, 20398 asm: arm64.AEON, 20399 reg: regInfo{ 20400 inputs: []inputInfo{ 20401 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20402 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20403 }, 20404 outputs: []outputInfo{ 20405 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20406 }, 20407 }, 20408 }, 20409 { 20410 name: "EONshiftRO", 20411 auxType: auxInt64, 20412 argLen: 2, 20413 asm: arm64.AEON, 20414 reg: regInfo{ 20415 inputs: []inputInfo{ 20416 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20417 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20418 }, 20419 outputs: []outputInfo{ 20420 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20421 }, 20422 }, 20423 }, 20424 { 20425 name: "ORNshiftLL", 20426 auxType: auxInt64, 20427 argLen: 2, 20428 asm: arm64.AORN, 20429 reg: regInfo{ 20430 inputs: []inputInfo{ 20431 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20432 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20433 }, 20434 outputs: []outputInfo{ 20435 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20436 }, 20437 }, 20438 }, 20439 { 20440 name: "ORNshiftRL", 20441 auxType: auxInt64, 20442 argLen: 2, 20443 asm: arm64.AORN, 20444 reg: regInfo{ 20445 inputs: []inputInfo{ 20446 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20447 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20448 }, 20449 outputs: []outputInfo{ 20450 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20451 }, 20452 }, 20453 }, 20454 { 20455 name: "ORNshiftRA", 20456 auxType: auxInt64, 20457 argLen: 2, 20458 asm: arm64.AORN, 20459 reg: regInfo{ 20460 inputs: []inputInfo{ 20461 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20462 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20463 }, 20464 outputs: []outputInfo{ 20465 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20466 }, 20467 }, 20468 }, 20469 { 20470 name: "ORNshiftRO", 20471 auxType: auxInt64, 20472 argLen: 2, 20473 asm: arm64.AORN, 20474 reg: regInfo{ 20475 inputs: []inputInfo{ 20476 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20477 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20478 }, 20479 outputs: []outputInfo{ 20480 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20481 }, 20482 }, 20483 }, 20484 { 20485 name: "CMPshiftLL", 20486 auxType: auxInt64, 20487 argLen: 2, 20488 asm: arm64.ACMP, 20489 reg: regInfo{ 20490 inputs: []inputInfo{ 20491 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20492 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20493 }, 20494 }, 20495 }, 20496 { 20497 name: "CMPshiftRL", 20498 auxType: auxInt64, 20499 argLen: 2, 20500 asm: arm64.ACMP, 20501 reg: regInfo{ 20502 inputs: []inputInfo{ 20503 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20504 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20505 }, 20506 }, 20507 }, 20508 { 20509 name: "CMPshiftRA", 20510 auxType: auxInt64, 20511 argLen: 2, 20512 asm: arm64.ACMP, 20513 reg: regInfo{ 20514 inputs: []inputInfo{ 20515 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20516 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20517 }, 20518 }, 20519 }, 20520 { 20521 name: "CMNshiftLL", 20522 auxType: auxInt64, 20523 argLen: 2, 20524 asm: arm64.ACMN, 20525 reg: regInfo{ 20526 inputs: []inputInfo{ 20527 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20528 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20529 }, 20530 }, 20531 }, 20532 { 20533 name: "CMNshiftRL", 20534 auxType: auxInt64, 20535 argLen: 2, 20536 asm: arm64.ACMN, 20537 reg: regInfo{ 20538 inputs: []inputInfo{ 20539 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20540 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20541 }, 20542 }, 20543 }, 20544 { 20545 name: "CMNshiftRA", 20546 auxType: auxInt64, 20547 argLen: 2, 20548 asm: arm64.ACMN, 20549 reg: regInfo{ 20550 inputs: []inputInfo{ 20551 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20552 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20553 }, 20554 }, 20555 }, 20556 { 20557 name: "TSTshiftLL", 20558 auxType: auxInt64, 20559 argLen: 2, 20560 asm: arm64.ATST, 20561 reg: regInfo{ 20562 inputs: []inputInfo{ 20563 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20564 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20565 }, 20566 }, 20567 }, 20568 { 20569 name: "TSTshiftRL", 20570 auxType: auxInt64, 20571 argLen: 2, 20572 asm: arm64.ATST, 20573 reg: regInfo{ 20574 inputs: []inputInfo{ 20575 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20576 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20577 }, 20578 }, 20579 }, 20580 { 20581 name: "TSTshiftRA", 20582 auxType: auxInt64, 20583 argLen: 2, 20584 asm: arm64.ATST, 20585 reg: regInfo{ 20586 inputs: []inputInfo{ 20587 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20588 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20589 }, 20590 }, 20591 }, 20592 { 20593 name: "TSTshiftRO", 20594 auxType: auxInt64, 20595 argLen: 2, 20596 asm: arm64.ATST, 20597 reg: regInfo{ 20598 inputs: []inputInfo{ 20599 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20600 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20601 }, 20602 }, 20603 }, 20604 { 20605 name: "BFI", 20606 auxType: auxARM64BitField, 20607 argLen: 2, 20608 resultInArg0: true, 20609 asm: arm64.ABFI, 20610 reg: regInfo{ 20611 inputs: []inputInfo{ 20612 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20613 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20614 }, 20615 outputs: []outputInfo{ 20616 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20617 }, 20618 }, 20619 }, 20620 { 20621 name: "BFXIL", 20622 auxType: auxARM64BitField, 20623 argLen: 2, 20624 resultInArg0: true, 20625 asm: arm64.ABFXIL, 20626 reg: regInfo{ 20627 inputs: []inputInfo{ 20628 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20629 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20630 }, 20631 outputs: []outputInfo{ 20632 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20633 }, 20634 }, 20635 }, 20636 { 20637 name: "SBFIZ", 20638 auxType: auxARM64BitField, 20639 argLen: 1, 20640 asm: arm64.ASBFIZ, 20641 reg: regInfo{ 20642 inputs: []inputInfo{ 20643 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20644 }, 20645 outputs: []outputInfo{ 20646 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20647 }, 20648 }, 20649 }, 20650 { 20651 name: "SBFX", 20652 auxType: auxARM64BitField, 20653 argLen: 1, 20654 asm: arm64.ASBFX, 20655 reg: regInfo{ 20656 inputs: []inputInfo{ 20657 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20658 }, 20659 outputs: []outputInfo{ 20660 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20661 }, 20662 }, 20663 }, 20664 { 20665 name: "UBFIZ", 20666 auxType: auxARM64BitField, 20667 argLen: 1, 20668 asm: arm64.AUBFIZ, 20669 reg: regInfo{ 20670 inputs: []inputInfo{ 20671 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20672 }, 20673 outputs: []outputInfo{ 20674 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20675 }, 20676 }, 20677 }, 20678 { 20679 name: "UBFX", 20680 auxType: auxARM64BitField, 20681 argLen: 1, 20682 asm: arm64.AUBFX, 20683 reg: regInfo{ 20684 inputs: []inputInfo{ 20685 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20686 }, 20687 outputs: []outputInfo{ 20688 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20689 }, 20690 }, 20691 }, 20692 { 20693 name: "MOVDconst", 20694 auxType: auxInt64, 20695 argLen: 0, 20696 rematerializeable: true, 20697 asm: arm64.AMOVD, 20698 reg: regInfo{ 20699 outputs: []outputInfo{ 20700 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20701 }, 20702 }, 20703 }, 20704 { 20705 name: "FMOVSconst", 20706 auxType: auxFloat64, 20707 argLen: 0, 20708 rematerializeable: true, 20709 asm: arm64.AFMOVS, 20710 reg: regInfo{ 20711 outputs: []outputInfo{ 20712 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20713 }, 20714 }, 20715 }, 20716 { 20717 name: "FMOVDconst", 20718 auxType: auxFloat64, 20719 argLen: 0, 20720 rematerializeable: true, 20721 asm: arm64.AFMOVD, 20722 reg: regInfo{ 20723 outputs: []outputInfo{ 20724 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20725 }, 20726 }, 20727 }, 20728 { 20729 name: "MOVDaddr", 20730 auxType: auxSymOff, 20731 argLen: 1, 20732 rematerializeable: true, 20733 symEffect: SymAddr, 20734 asm: arm64.AMOVD, 20735 reg: regInfo{ 20736 inputs: []inputInfo{ 20737 {0, 9223372037928517632}, // SP SB 20738 }, 20739 outputs: []outputInfo{ 20740 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20741 }, 20742 }, 20743 }, 20744 { 20745 name: "MOVBload", 20746 auxType: auxSymOff, 20747 argLen: 2, 20748 faultOnNilArg0: true, 20749 symEffect: SymRead, 20750 asm: arm64.AMOVB, 20751 reg: regInfo{ 20752 inputs: []inputInfo{ 20753 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20754 }, 20755 outputs: []outputInfo{ 20756 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20757 }, 20758 }, 20759 }, 20760 { 20761 name: "MOVBUload", 20762 auxType: auxSymOff, 20763 argLen: 2, 20764 faultOnNilArg0: true, 20765 symEffect: SymRead, 20766 asm: arm64.AMOVBU, 20767 reg: regInfo{ 20768 inputs: []inputInfo{ 20769 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20770 }, 20771 outputs: []outputInfo{ 20772 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20773 }, 20774 }, 20775 }, 20776 { 20777 name: "MOVHload", 20778 auxType: auxSymOff, 20779 argLen: 2, 20780 faultOnNilArg0: true, 20781 symEffect: SymRead, 20782 asm: arm64.AMOVH, 20783 reg: regInfo{ 20784 inputs: []inputInfo{ 20785 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20786 }, 20787 outputs: []outputInfo{ 20788 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20789 }, 20790 }, 20791 }, 20792 { 20793 name: "MOVHUload", 20794 auxType: auxSymOff, 20795 argLen: 2, 20796 faultOnNilArg0: true, 20797 symEffect: SymRead, 20798 asm: arm64.AMOVHU, 20799 reg: regInfo{ 20800 inputs: []inputInfo{ 20801 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20802 }, 20803 outputs: []outputInfo{ 20804 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20805 }, 20806 }, 20807 }, 20808 { 20809 name: "MOVWload", 20810 auxType: auxSymOff, 20811 argLen: 2, 20812 faultOnNilArg0: true, 20813 symEffect: SymRead, 20814 asm: arm64.AMOVW, 20815 reg: regInfo{ 20816 inputs: []inputInfo{ 20817 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20818 }, 20819 outputs: []outputInfo{ 20820 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20821 }, 20822 }, 20823 }, 20824 { 20825 name: "MOVWUload", 20826 auxType: auxSymOff, 20827 argLen: 2, 20828 faultOnNilArg0: true, 20829 symEffect: SymRead, 20830 asm: arm64.AMOVWU, 20831 reg: regInfo{ 20832 inputs: []inputInfo{ 20833 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20834 }, 20835 outputs: []outputInfo{ 20836 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20837 }, 20838 }, 20839 }, 20840 { 20841 name: "MOVDload", 20842 auxType: auxSymOff, 20843 argLen: 2, 20844 faultOnNilArg0: true, 20845 symEffect: SymRead, 20846 asm: arm64.AMOVD, 20847 reg: regInfo{ 20848 inputs: []inputInfo{ 20849 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20850 }, 20851 outputs: []outputInfo{ 20852 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20853 }, 20854 }, 20855 }, 20856 { 20857 name: "LDP", 20858 auxType: auxSymOff, 20859 argLen: 2, 20860 faultOnNilArg0: true, 20861 symEffect: SymRead, 20862 asm: arm64.ALDP, 20863 reg: regInfo{ 20864 inputs: []inputInfo{ 20865 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20866 }, 20867 outputs: []outputInfo{ 20868 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20869 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20870 }, 20871 }, 20872 }, 20873 { 20874 name: "FMOVSload", 20875 auxType: auxSymOff, 20876 argLen: 2, 20877 faultOnNilArg0: true, 20878 symEffect: SymRead, 20879 asm: arm64.AFMOVS, 20880 reg: regInfo{ 20881 inputs: []inputInfo{ 20882 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20883 }, 20884 outputs: []outputInfo{ 20885 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20886 }, 20887 }, 20888 }, 20889 { 20890 name: "FMOVDload", 20891 auxType: auxSymOff, 20892 argLen: 2, 20893 faultOnNilArg0: true, 20894 symEffect: SymRead, 20895 asm: arm64.AFMOVD, 20896 reg: regInfo{ 20897 inputs: []inputInfo{ 20898 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20899 }, 20900 outputs: []outputInfo{ 20901 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 20902 }, 20903 }, 20904 }, 20905 { 20906 name: "MOVDloadidx", 20907 argLen: 3, 20908 asm: arm64.AMOVD, 20909 reg: regInfo{ 20910 inputs: []inputInfo{ 20911 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20912 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20913 }, 20914 outputs: []outputInfo{ 20915 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20916 }, 20917 }, 20918 }, 20919 { 20920 name: "MOVWloadidx", 20921 argLen: 3, 20922 asm: arm64.AMOVW, 20923 reg: regInfo{ 20924 inputs: []inputInfo{ 20925 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20926 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20927 }, 20928 outputs: []outputInfo{ 20929 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20930 }, 20931 }, 20932 }, 20933 { 20934 name: "MOVWUloadidx", 20935 argLen: 3, 20936 asm: arm64.AMOVWU, 20937 reg: regInfo{ 20938 inputs: []inputInfo{ 20939 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20940 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20941 }, 20942 outputs: []outputInfo{ 20943 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20944 }, 20945 }, 20946 }, 20947 { 20948 name: "MOVHloadidx", 20949 argLen: 3, 20950 asm: arm64.AMOVH, 20951 reg: regInfo{ 20952 inputs: []inputInfo{ 20953 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20954 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20955 }, 20956 outputs: []outputInfo{ 20957 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20958 }, 20959 }, 20960 }, 20961 { 20962 name: "MOVHUloadidx", 20963 argLen: 3, 20964 asm: arm64.AMOVHU, 20965 reg: regInfo{ 20966 inputs: []inputInfo{ 20967 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20968 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20969 }, 20970 outputs: []outputInfo{ 20971 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20972 }, 20973 }, 20974 }, 20975 { 20976 name: "MOVBloadidx", 20977 argLen: 3, 20978 asm: arm64.AMOVB, 20979 reg: regInfo{ 20980 inputs: []inputInfo{ 20981 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20982 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20983 }, 20984 outputs: []outputInfo{ 20985 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 20986 }, 20987 }, 20988 }, 20989 { 20990 name: "MOVBUloadidx", 20991 argLen: 3, 20992 asm: arm64.AMOVBU, 20993 reg: regInfo{ 20994 inputs: []inputInfo{ 20995 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 20996 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 20997 }, 20998 outputs: []outputInfo{ 20999 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21000 }, 21001 }, 21002 }, 21003 { 21004 name: "FMOVSloadidx", 21005 argLen: 3, 21006 asm: arm64.AFMOVS, 21007 reg: regInfo{ 21008 inputs: []inputInfo{ 21009 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21010 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21011 }, 21012 outputs: []outputInfo{ 21013 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21014 }, 21015 }, 21016 }, 21017 { 21018 name: "FMOVDloadidx", 21019 argLen: 3, 21020 asm: arm64.AFMOVD, 21021 reg: regInfo{ 21022 inputs: []inputInfo{ 21023 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21024 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21025 }, 21026 outputs: []outputInfo{ 21027 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21028 }, 21029 }, 21030 }, 21031 { 21032 name: "MOVHloadidx2", 21033 argLen: 3, 21034 asm: arm64.AMOVH, 21035 reg: regInfo{ 21036 inputs: []inputInfo{ 21037 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21038 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21039 }, 21040 outputs: []outputInfo{ 21041 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21042 }, 21043 }, 21044 }, 21045 { 21046 name: "MOVHUloadidx2", 21047 argLen: 3, 21048 asm: arm64.AMOVHU, 21049 reg: regInfo{ 21050 inputs: []inputInfo{ 21051 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21052 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21053 }, 21054 outputs: []outputInfo{ 21055 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21056 }, 21057 }, 21058 }, 21059 { 21060 name: "MOVWloadidx4", 21061 argLen: 3, 21062 asm: arm64.AMOVW, 21063 reg: regInfo{ 21064 inputs: []inputInfo{ 21065 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21066 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21067 }, 21068 outputs: []outputInfo{ 21069 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21070 }, 21071 }, 21072 }, 21073 { 21074 name: "MOVWUloadidx4", 21075 argLen: 3, 21076 asm: arm64.AMOVWU, 21077 reg: regInfo{ 21078 inputs: []inputInfo{ 21079 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21080 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21081 }, 21082 outputs: []outputInfo{ 21083 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21084 }, 21085 }, 21086 }, 21087 { 21088 name: "MOVDloadidx8", 21089 argLen: 3, 21090 asm: arm64.AMOVD, 21091 reg: regInfo{ 21092 inputs: []inputInfo{ 21093 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21094 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21095 }, 21096 outputs: []outputInfo{ 21097 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21098 }, 21099 }, 21100 }, 21101 { 21102 name: "FMOVSloadidx4", 21103 argLen: 3, 21104 asm: arm64.AFMOVS, 21105 reg: regInfo{ 21106 inputs: []inputInfo{ 21107 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21108 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21109 }, 21110 outputs: []outputInfo{ 21111 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21112 }, 21113 }, 21114 }, 21115 { 21116 name: "FMOVDloadidx8", 21117 argLen: 3, 21118 asm: arm64.AFMOVD, 21119 reg: regInfo{ 21120 inputs: []inputInfo{ 21121 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21122 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21123 }, 21124 outputs: []outputInfo{ 21125 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21126 }, 21127 }, 21128 }, 21129 { 21130 name: "MOVBstore", 21131 auxType: auxSymOff, 21132 argLen: 3, 21133 faultOnNilArg0: true, 21134 symEffect: SymWrite, 21135 asm: arm64.AMOVB, 21136 reg: regInfo{ 21137 inputs: []inputInfo{ 21138 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21139 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21140 }, 21141 }, 21142 }, 21143 { 21144 name: "MOVHstore", 21145 auxType: auxSymOff, 21146 argLen: 3, 21147 faultOnNilArg0: true, 21148 symEffect: SymWrite, 21149 asm: arm64.AMOVH, 21150 reg: regInfo{ 21151 inputs: []inputInfo{ 21152 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21153 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21154 }, 21155 }, 21156 }, 21157 { 21158 name: "MOVWstore", 21159 auxType: auxSymOff, 21160 argLen: 3, 21161 faultOnNilArg0: true, 21162 symEffect: SymWrite, 21163 asm: arm64.AMOVW, 21164 reg: regInfo{ 21165 inputs: []inputInfo{ 21166 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21167 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21168 }, 21169 }, 21170 }, 21171 { 21172 name: "MOVDstore", 21173 auxType: auxSymOff, 21174 argLen: 3, 21175 faultOnNilArg0: true, 21176 symEffect: SymWrite, 21177 asm: arm64.AMOVD, 21178 reg: regInfo{ 21179 inputs: []inputInfo{ 21180 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21181 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21182 }, 21183 }, 21184 }, 21185 { 21186 name: "STP", 21187 auxType: auxSymOff, 21188 argLen: 4, 21189 faultOnNilArg0: true, 21190 symEffect: SymWrite, 21191 asm: arm64.ASTP, 21192 reg: regInfo{ 21193 inputs: []inputInfo{ 21194 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21195 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21196 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21197 }, 21198 }, 21199 }, 21200 { 21201 name: "FMOVSstore", 21202 auxType: auxSymOff, 21203 argLen: 3, 21204 faultOnNilArg0: true, 21205 symEffect: SymWrite, 21206 asm: arm64.AFMOVS, 21207 reg: regInfo{ 21208 inputs: []inputInfo{ 21209 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21210 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21211 }, 21212 }, 21213 }, 21214 { 21215 name: "FMOVDstore", 21216 auxType: auxSymOff, 21217 argLen: 3, 21218 faultOnNilArg0: true, 21219 symEffect: SymWrite, 21220 asm: arm64.AFMOVD, 21221 reg: regInfo{ 21222 inputs: []inputInfo{ 21223 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21224 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21225 }, 21226 }, 21227 }, 21228 { 21229 name: "MOVBstoreidx", 21230 argLen: 4, 21231 asm: arm64.AMOVB, 21232 reg: regInfo{ 21233 inputs: []inputInfo{ 21234 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21235 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21236 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21237 }, 21238 }, 21239 }, 21240 { 21241 name: "MOVHstoreidx", 21242 argLen: 4, 21243 asm: arm64.AMOVH, 21244 reg: regInfo{ 21245 inputs: []inputInfo{ 21246 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21247 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21248 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21249 }, 21250 }, 21251 }, 21252 { 21253 name: "MOVWstoreidx", 21254 argLen: 4, 21255 asm: arm64.AMOVW, 21256 reg: regInfo{ 21257 inputs: []inputInfo{ 21258 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21259 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21260 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21261 }, 21262 }, 21263 }, 21264 { 21265 name: "MOVDstoreidx", 21266 argLen: 4, 21267 asm: arm64.AMOVD, 21268 reg: regInfo{ 21269 inputs: []inputInfo{ 21270 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21271 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21272 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21273 }, 21274 }, 21275 }, 21276 { 21277 name: "FMOVSstoreidx", 21278 argLen: 4, 21279 asm: arm64.AFMOVS, 21280 reg: regInfo{ 21281 inputs: []inputInfo{ 21282 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21283 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21284 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21285 }, 21286 }, 21287 }, 21288 { 21289 name: "FMOVDstoreidx", 21290 argLen: 4, 21291 asm: arm64.AFMOVD, 21292 reg: regInfo{ 21293 inputs: []inputInfo{ 21294 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21295 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21296 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21297 }, 21298 }, 21299 }, 21300 { 21301 name: "MOVHstoreidx2", 21302 argLen: 4, 21303 asm: arm64.AMOVH, 21304 reg: regInfo{ 21305 inputs: []inputInfo{ 21306 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21307 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21308 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21309 }, 21310 }, 21311 }, 21312 { 21313 name: "MOVWstoreidx4", 21314 argLen: 4, 21315 asm: arm64.AMOVW, 21316 reg: regInfo{ 21317 inputs: []inputInfo{ 21318 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21319 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21320 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21321 }, 21322 }, 21323 }, 21324 { 21325 name: "MOVDstoreidx8", 21326 argLen: 4, 21327 asm: arm64.AMOVD, 21328 reg: regInfo{ 21329 inputs: []inputInfo{ 21330 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21331 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21332 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21333 }, 21334 }, 21335 }, 21336 { 21337 name: "FMOVSstoreidx4", 21338 argLen: 4, 21339 asm: arm64.AFMOVS, 21340 reg: regInfo{ 21341 inputs: []inputInfo{ 21342 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21343 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21344 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21345 }, 21346 }, 21347 }, 21348 { 21349 name: "FMOVDstoreidx8", 21350 argLen: 4, 21351 asm: arm64.AFMOVD, 21352 reg: regInfo{ 21353 inputs: []inputInfo{ 21354 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21355 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21356 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21357 }, 21358 }, 21359 }, 21360 { 21361 name: "MOVBstorezero", 21362 auxType: auxSymOff, 21363 argLen: 2, 21364 faultOnNilArg0: true, 21365 symEffect: SymWrite, 21366 asm: arm64.AMOVB, 21367 reg: regInfo{ 21368 inputs: []inputInfo{ 21369 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21370 }, 21371 }, 21372 }, 21373 { 21374 name: "MOVHstorezero", 21375 auxType: auxSymOff, 21376 argLen: 2, 21377 faultOnNilArg0: true, 21378 symEffect: SymWrite, 21379 asm: arm64.AMOVH, 21380 reg: regInfo{ 21381 inputs: []inputInfo{ 21382 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21383 }, 21384 }, 21385 }, 21386 { 21387 name: "MOVWstorezero", 21388 auxType: auxSymOff, 21389 argLen: 2, 21390 faultOnNilArg0: true, 21391 symEffect: SymWrite, 21392 asm: arm64.AMOVW, 21393 reg: regInfo{ 21394 inputs: []inputInfo{ 21395 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21396 }, 21397 }, 21398 }, 21399 { 21400 name: "MOVDstorezero", 21401 auxType: auxSymOff, 21402 argLen: 2, 21403 faultOnNilArg0: true, 21404 symEffect: SymWrite, 21405 asm: arm64.AMOVD, 21406 reg: regInfo{ 21407 inputs: []inputInfo{ 21408 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21409 }, 21410 }, 21411 }, 21412 { 21413 name: "MOVQstorezero", 21414 auxType: auxSymOff, 21415 argLen: 2, 21416 faultOnNilArg0: true, 21417 symEffect: SymWrite, 21418 asm: arm64.ASTP, 21419 reg: regInfo{ 21420 inputs: []inputInfo{ 21421 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21422 }, 21423 }, 21424 }, 21425 { 21426 name: "MOVBstorezeroidx", 21427 argLen: 3, 21428 asm: arm64.AMOVB, 21429 reg: regInfo{ 21430 inputs: []inputInfo{ 21431 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21432 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21433 }, 21434 }, 21435 }, 21436 { 21437 name: "MOVHstorezeroidx", 21438 argLen: 3, 21439 asm: arm64.AMOVH, 21440 reg: regInfo{ 21441 inputs: []inputInfo{ 21442 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21443 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21444 }, 21445 }, 21446 }, 21447 { 21448 name: "MOVWstorezeroidx", 21449 argLen: 3, 21450 asm: arm64.AMOVW, 21451 reg: regInfo{ 21452 inputs: []inputInfo{ 21453 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21454 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21455 }, 21456 }, 21457 }, 21458 { 21459 name: "MOVDstorezeroidx", 21460 argLen: 3, 21461 asm: arm64.AMOVD, 21462 reg: regInfo{ 21463 inputs: []inputInfo{ 21464 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21465 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21466 }, 21467 }, 21468 }, 21469 { 21470 name: "MOVHstorezeroidx2", 21471 argLen: 3, 21472 asm: arm64.AMOVH, 21473 reg: regInfo{ 21474 inputs: []inputInfo{ 21475 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21476 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21477 }, 21478 }, 21479 }, 21480 { 21481 name: "MOVWstorezeroidx4", 21482 argLen: 3, 21483 asm: arm64.AMOVW, 21484 reg: regInfo{ 21485 inputs: []inputInfo{ 21486 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21487 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21488 }, 21489 }, 21490 }, 21491 { 21492 name: "MOVDstorezeroidx8", 21493 argLen: 3, 21494 asm: arm64.AMOVD, 21495 reg: regInfo{ 21496 inputs: []inputInfo{ 21497 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21498 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 21499 }, 21500 }, 21501 }, 21502 { 21503 name: "FMOVDgpfp", 21504 argLen: 1, 21505 asm: arm64.AFMOVD, 21506 reg: regInfo{ 21507 inputs: []inputInfo{ 21508 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21509 }, 21510 outputs: []outputInfo{ 21511 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21512 }, 21513 }, 21514 }, 21515 { 21516 name: "FMOVDfpgp", 21517 argLen: 1, 21518 asm: arm64.AFMOVD, 21519 reg: regInfo{ 21520 inputs: []inputInfo{ 21521 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21522 }, 21523 outputs: []outputInfo{ 21524 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21525 }, 21526 }, 21527 }, 21528 { 21529 name: "FMOVSgpfp", 21530 argLen: 1, 21531 asm: arm64.AFMOVS, 21532 reg: regInfo{ 21533 inputs: []inputInfo{ 21534 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21535 }, 21536 outputs: []outputInfo{ 21537 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21538 }, 21539 }, 21540 }, 21541 { 21542 name: "FMOVSfpgp", 21543 argLen: 1, 21544 asm: arm64.AFMOVS, 21545 reg: regInfo{ 21546 inputs: []inputInfo{ 21547 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21548 }, 21549 outputs: []outputInfo{ 21550 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21551 }, 21552 }, 21553 }, 21554 { 21555 name: "MOVBreg", 21556 argLen: 1, 21557 asm: arm64.AMOVB, 21558 reg: regInfo{ 21559 inputs: []inputInfo{ 21560 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21561 }, 21562 outputs: []outputInfo{ 21563 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21564 }, 21565 }, 21566 }, 21567 { 21568 name: "MOVBUreg", 21569 argLen: 1, 21570 asm: arm64.AMOVBU, 21571 reg: regInfo{ 21572 inputs: []inputInfo{ 21573 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21574 }, 21575 outputs: []outputInfo{ 21576 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21577 }, 21578 }, 21579 }, 21580 { 21581 name: "MOVHreg", 21582 argLen: 1, 21583 asm: arm64.AMOVH, 21584 reg: regInfo{ 21585 inputs: []inputInfo{ 21586 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21587 }, 21588 outputs: []outputInfo{ 21589 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21590 }, 21591 }, 21592 }, 21593 { 21594 name: "MOVHUreg", 21595 argLen: 1, 21596 asm: arm64.AMOVHU, 21597 reg: regInfo{ 21598 inputs: []inputInfo{ 21599 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21600 }, 21601 outputs: []outputInfo{ 21602 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21603 }, 21604 }, 21605 }, 21606 { 21607 name: "MOVWreg", 21608 argLen: 1, 21609 asm: arm64.AMOVW, 21610 reg: regInfo{ 21611 inputs: []inputInfo{ 21612 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21613 }, 21614 outputs: []outputInfo{ 21615 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21616 }, 21617 }, 21618 }, 21619 { 21620 name: "MOVWUreg", 21621 argLen: 1, 21622 asm: arm64.AMOVWU, 21623 reg: regInfo{ 21624 inputs: []inputInfo{ 21625 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21626 }, 21627 outputs: []outputInfo{ 21628 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21629 }, 21630 }, 21631 }, 21632 { 21633 name: "MOVDreg", 21634 argLen: 1, 21635 asm: arm64.AMOVD, 21636 reg: regInfo{ 21637 inputs: []inputInfo{ 21638 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21639 }, 21640 outputs: []outputInfo{ 21641 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21642 }, 21643 }, 21644 }, 21645 { 21646 name: "MOVDnop", 21647 argLen: 1, 21648 resultInArg0: true, 21649 reg: regInfo{ 21650 inputs: []inputInfo{ 21651 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21652 }, 21653 outputs: []outputInfo{ 21654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21655 }, 21656 }, 21657 }, 21658 { 21659 name: "SCVTFWS", 21660 argLen: 1, 21661 asm: arm64.ASCVTFWS, 21662 reg: regInfo{ 21663 inputs: []inputInfo{ 21664 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21665 }, 21666 outputs: []outputInfo{ 21667 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21668 }, 21669 }, 21670 }, 21671 { 21672 name: "SCVTFWD", 21673 argLen: 1, 21674 asm: arm64.ASCVTFWD, 21675 reg: regInfo{ 21676 inputs: []inputInfo{ 21677 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21678 }, 21679 outputs: []outputInfo{ 21680 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21681 }, 21682 }, 21683 }, 21684 { 21685 name: "UCVTFWS", 21686 argLen: 1, 21687 asm: arm64.AUCVTFWS, 21688 reg: regInfo{ 21689 inputs: []inputInfo{ 21690 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21691 }, 21692 outputs: []outputInfo{ 21693 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21694 }, 21695 }, 21696 }, 21697 { 21698 name: "UCVTFWD", 21699 argLen: 1, 21700 asm: arm64.AUCVTFWD, 21701 reg: regInfo{ 21702 inputs: []inputInfo{ 21703 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21704 }, 21705 outputs: []outputInfo{ 21706 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21707 }, 21708 }, 21709 }, 21710 { 21711 name: "SCVTFS", 21712 argLen: 1, 21713 asm: arm64.ASCVTFS, 21714 reg: regInfo{ 21715 inputs: []inputInfo{ 21716 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21717 }, 21718 outputs: []outputInfo{ 21719 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21720 }, 21721 }, 21722 }, 21723 { 21724 name: "SCVTFD", 21725 argLen: 1, 21726 asm: arm64.ASCVTFD, 21727 reg: regInfo{ 21728 inputs: []inputInfo{ 21729 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21730 }, 21731 outputs: []outputInfo{ 21732 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21733 }, 21734 }, 21735 }, 21736 { 21737 name: "UCVTFS", 21738 argLen: 1, 21739 asm: arm64.AUCVTFS, 21740 reg: regInfo{ 21741 inputs: []inputInfo{ 21742 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21743 }, 21744 outputs: []outputInfo{ 21745 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21746 }, 21747 }, 21748 }, 21749 { 21750 name: "UCVTFD", 21751 argLen: 1, 21752 asm: arm64.AUCVTFD, 21753 reg: regInfo{ 21754 inputs: []inputInfo{ 21755 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21756 }, 21757 outputs: []outputInfo{ 21758 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21759 }, 21760 }, 21761 }, 21762 { 21763 name: "FCVTZSSW", 21764 argLen: 1, 21765 asm: arm64.AFCVTZSSW, 21766 reg: regInfo{ 21767 inputs: []inputInfo{ 21768 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21769 }, 21770 outputs: []outputInfo{ 21771 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21772 }, 21773 }, 21774 }, 21775 { 21776 name: "FCVTZSDW", 21777 argLen: 1, 21778 asm: arm64.AFCVTZSDW, 21779 reg: regInfo{ 21780 inputs: []inputInfo{ 21781 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21782 }, 21783 outputs: []outputInfo{ 21784 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21785 }, 21786 }, 21787 }, 21788 { 21789 name: "FCVTZUSW", 21790 argLen: 1, 21791 asm: arm64.AFCVTZUSW, 21792 reg: regInfo{ 21793 inputs: []inputInfo{ 21794 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21795 }, 21796 outputs: []outputInfo{ 21797 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21798 }, 21799 }, 21800 }, 21801 { 21802 name: "FCVTZUDW", 21803 argLen: 1, 21804 asm: arm64.AFCVTZUDW, 21805 reg: regInfo{ 21806 inputs: []inputInfo{ 21807 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21808 }, 21809 outputs: []outputInfo{ 21810 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21811 }, 21812 }, 21813 }, 21814 { 21815 name: "FCVTZSS", 21816 argLen: 1, 21817 asm: arm64.AFCVTZSS, 21818 reg: regInfo{ 21819 inputs: []inputInfo{ 21820 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21821 }, 21822 outputs: []outputInfo{ 21823 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21824 }, 21825 }, 21826 }, 21827 { 21828 name: "FCVTZSD", 21829 argLen: 1, 21830 asm: arm64.AFCVTZSD, 21831 reg: regInfo{ 21832 inputs: []inputInfo{ 21833 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21834 }, 21835 outputs: []outputInfo{ 21836 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21837 }, 21838 }, 21839 }, 21840 { 21841 name: "FCVTZUS", 21842 argLen: 1, 21843 asm: arm64.AFCVTZUS, 21844 reg: regInfo{ 21845 inputs: []inputInfo{ 21846 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21847 }, 21848 outputs: []outputInfo{ 21849 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21850 }, 21851 }, 21852 }, 21853 { 21854 name: "FCVTZUD", 21855 argLen: 1, 21856 asm: arm64.AFCVTZUD, 21857 reg: regInfo{ 21858 inputs: []inputInfo{ 21859 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21860 }, 21861 outputs: []outputInfo{ 21862 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21863 }, 21864 }, 21865 }, 21866 { 21867 name: "FCVTSD", 21868 argLen: 1, 21869 asm: arm64.AFCVTSD, 21870 reg: regInfo{ 21871 inputs: []inputInfo{ 21872 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21873 }, 21874 outputs: []outputInfo{ 21875 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21876 }, 21877 }, 21878 }, 21879 { 21880 name: "FCVTDS", 21881 argLen: 1, 21882 asm: arm64.AFCVTDS, 21883 reg: regInfo{ 21884 inputs: []inputInfo{ 21885 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21886 }, 21887 outputs: []outputInfo{ 21888 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21889 }, 21890 }, 21891 }, 21892 { 21893 name: "FRINTAD", 21894 argLen: 1, 21895 asm: arm64.AFRINTAD, 21896 reg: regInfo{ 21897 inputs: []inputInfo{ 21898 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21899 }, 21900 outputs: []outputInfo{ 21901 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21902 }, 21903 }, 21904 }, 21905 { 21906 name: "FRINTMD", 21907 argLen: 1, 21908 asm: arm64.AFRINTMD, 21909 reg: regInfo{ 21910 inputs: []inputInfo{ 21911 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21912 }, 21913 outputs: []outputInfo{ 21914 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21915 }, 21916 }, 21917 }, 21918 { 21919 name: "FRINTND", 21920 argLen: 1, 21921 asm: arm64.AFRINTND, 21922 reg: regInfo{ 21923 inputs: []inputInfo{ 21924 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21925 }, 21926 outputs: []outputInfo{ 21927 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21928 }, 21929 }, 21930 }, 21931 { 21932 name: "FRINTPD", 21933 argLen: 1, 21934 asm: arm64.AFRINTPD, 21935 reg: regInfo{ 21936 inputs: []inputInfo{ 21937 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21938 }, 21939 outputs: []outputInfo{ 21940 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21941 }, 21942 }, 21943 }, 21944 { 21945 name: "FRINTZD", 21946 argLen: 1, 21947 asm: arm64.AFRINTZD, 21948 reg: regInfo{ 21949 inputs: []inputInfo{ 21950 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21951 }, 21952 outputs: []outputInfo{ 21953 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 21954 }, 21955 }, 21956 }, 21957 { 21958 name: "CSEL", 21959 auxType: auxCCop, 21960 argLen: 3, 21961 asm: arm64.ACSEL, 21962 reg: regInfo{ 21963 inputs: []inputInfo{ 21964 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21965 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21966 }, 21967 outputs: []outputInfo{ 21968 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21969 }, 21970 }, 21971 }, 21972 { 21973 name: "CSEL0", 21974 auxType: auxCCop, 21975 argLen: 2, 21976 asm: arm64.ACSEL, 21977 reg: regInfo{ 21978 inputs: []inputInfo{ 21979 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 21980 }, 21981 outputs: []outputInfo{ 21982 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21983 }, 21984 }, 21985 }, 21986 { 21987 name: "CSINC", 21988 auxType: auxCCop, 21989 argLen: 3, 21990 asm: arm64.ACSINC, 21991 reg: regInfo{ 21992 inputs: []inputInfo{ 21993 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21994 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21995 }, 21996 outputs: []outputInfo{ 21997 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 21998 }, 21999 }, 22000 }, 22001 { 22002 name: "CSINV", 22003 auxType: auxCCop, 22004 argLen: 3, 22005 asm: arm64.ACSINV, 22006 reg: regInfo{ 22007 inputs: []inputInfo{ 22008 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22009 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22010 }, 22011 outputs: []outputInfo{ 22012 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22013 }, 22014 }, 22015 }, 22016 { 22017 name: "CSNEG", 22018 auxType: auxCCop, 22019 argLen: 3, 22020 asm: arm64.ACSNEG, 22021 reg: regInfo{ 22022 inputs: []inputInfo{ 22023 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22024 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22025 }, 22026 outputs: []outputInfo{ 22027 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22028 }, 22029 }, 22030 }, 22031 { 22032 name: "CSETM", 22033 auxType: auxCCop, 22034 argLen: 1, 22035 asm: arm64.ACSETM, 22036 reg: regInfo{ 22037 outputs: []outputInfo{ 22038 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22039 }, 22040 }, 22041 }, 22042 { 22043 name: "CALLstatic", 22044 auxType: auxCallOff, 22045 argLen: -1, 22046 clobberFlags: true, 22047 call: true, 22048 reg: regInfo{ 22049 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22050 }, 22051 }, 22052 { 22053 name: "CALLtail", 22054 auxType: auxCallOff, 22055 argLen: -1, 22056 clobberFlags: true, 22057 call: true, 22058 tailCall: true, 22059 reg: regInfo{ 22060 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22061 }, 22062 }, 22063 { 22064 name: "CALLclosure", 22065 auxType: auxCallOff, 22066 argLen: -1, 22067 clobberFlags: true, 22068 call: true, 22069 reg: regInfo{ 22070 inputs: []inputInfo{ 22071 {1, 67108864}, // R26 22072 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 22073 }, 22074 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22075 }, 22076 }, 22077 { 22078 name: "CALLinter", 22079 auxType: auxCallOff, 22080 argLen: -1, 22081 clobberFlags: true, 22082 call: true, 22083 reg: regInfo{ 22084 inputs: []inputInfo{ 22085 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22086 }, 22087 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22088 }, 22089 }, 22090 { 22091 name: "LoweredNilCheck", 22092 argLen: 2, 22093 nilCheck: true, 22094 faultOnNilArg0: true, 22095 reg: regInfo{ 22096 inputs: []inputInfo{ 22097 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22098 }, 22099 }, 22100 }, 22101 { 22102 name: "Equal", 22103 argLen: 1, 22104 reg: regInfo{ 22105 outputs: []outputInfo{ 22106 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22107 }, 22108 }, 22109 }, 22110 { 22111 name: "NotEqual", 22112 argLen: 1, 22113 reg: regInfo{ 22114 outputs: []outputInfo{ 22115 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22116 }, 22117 }, 22118 }, 22119 { 22120 name: "LessThan", 22121 argLen: 1, 22122 reg: regInfo{ 22123 outputs: []outputInfo{ 22124 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22125 }, 22126 }, 22127 }, 22128 { 22129 name: "LessEqual", 22130 argLen: 1, 22131 reg: regInfo{ 22132 outputs: []outputInfo{ 22133 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22134 }, 22135 }, 22136 }, 22137 { 22138 name: "GreaterThan", 22139 argLen: 1, 22140 reg: regInfo{ 22141 outputs: []outputInfo{ 22142 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22143 }, 22144 }, 22145 }, 22146 { 22147 name: "GreaterEqual", 22148 argLen: 1, 22149 reg: regInfo{ 22150 outputs: []outputInfo{ 22151 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22152 }, 22153 }, 22154 }, 22155 { 22156 name: "LessThanU", 22157 argLen: 1, 22158 reg: regInfo{ 22159 outputs: []outputInfo{ 22160 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22161 }, 22162 }, 22163 }, 22164 { 22165 name: "LessEqualU", 22166 argLen: 1, 22167 reg: regInfo{ 22168 outputs: []outputInfo{ 22169 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22170 }, 22171 }, 22172 }, 22173 { 22174 name: "GreaterThanU", 22175 argLen: 1, 22176 reg: regInfo{ 22177 outputs: []outputInfo{ 22178 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22179 }, 22180 }, 22181 }, 22182 { 22183 name: "GreaterEqualU", 22184 argLen: 1, 22185 reg: regInfo{ 22186 outputs: []outputInfo{ 22187 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22188 }, 22189 }, 22190 }, 22191 { 22192 name: "LessThanF", 22193 argLen: 1, 22194 reg: regInfo{ 22195 outputs: []outputInfo{ 22196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22197 }, 22198 }, 22199 }, 22200 { 22201 name: "LessEqualF", 22202 argLen: 1, 22203 reg: regInfo{ 22204 outputs: []outputInfo{ 22205 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22206 }, 22207 }, 22208 }, 22209 { 22210 name: "GreaterThanF", 22211 argLen: 1, 22212 reg: regInfo{ 22213 outputs: []outputInfo{ 22214 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22215 }, 22216 }, 22217 }, 22218 { 22219 name: "GreaterEqualF", 22220 argLen: 1, 22221 reg: regInfo{ 22222 outputs: []outputInfo{ 22223 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22224 }, 22225 }, 22226 }, 22227 { 22228 name: "NotLessThanF", 22229 argLen: 1, 22230 reg: regInfo{ 22231 outputs: []outputInfo{ 22232 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22233 }, 22234 }, 22235 }, 22236 { 22237 name: "NotLessEqualF", 22238 argLen: 1, 22239 reg: regInfo{ 22240 outputs: []outputInfo{ 22241 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22242 }, 22243 }, 22244 }, 22245 { 22246 name: "NotGreaterThanF", 22247 argLen: 1, 22248 reg: regInfo{ 22249 outputs: []outputInfo{ 22250 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22251 }, 22252 }, 22253 }, 22254 { 22255 name: "NotGreaterEqualF", 22256 argLen: 1, 22257 reg: regInfo{ 22258 outputs: []outputInfo{ 22259 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22260 }, 22261 }, 22262 }, 22263 { 22264 name: "DUFFZERO", 22265 auxType: auxInt64, 22266 argLen: 2, 22267 faultOnNilArg0: true, 22268 unsafePoint: true, 22269 reg: regInfo{ 22270 inputs: []inputInfo{ 22271 {0, 1048576}, // R20 22272 }, 22273 clobbers: 538116096, // R16 R17 R20 R30 22274 }, 22275 }, 22276 { 22277 name: "LoweredZero", 22278 argLen: 3, 22279 clobberFlags: true, 22280 faultOnNilArg0: true, 22281 reg: regInfo{ 22282 inputs: []inputInfo{ 22283 {0, 65536}, // R16 22284 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22285 }, 22286 clobbers: 65536, // R16 22287 }, 22288 }, 22289 { 22290 name: "DUFFCOPY", 22291 auxType: auxInt64, 22292 argLen: 3, 22293 faultOnNilArg0: true, 22294 faultOnNilArg1: true, 22295 unsafePoint: true, 22296 reg: regInfo{ 22297 inputs: []inputInfo{ 22298 {0, 2097152}, // R21 22299 {1, 1048576}, // R20 22300 }, 22301 clobbers: 607322112, // R16 R17 R20 R21 R26 R30 22302 }, 22303 }, 22304 { 22305 name: "LoweredMove", 22306 argLen: 4, 22307 clobberFlags: true, 22308 faultOnNilArg0: true, 22309 faultOnNilArg1: true, 22310 reg: regInfo{ 22311 inputs: []inputInfo{ 22312 {0, 131072}, // R17 22313 {1, 65536}, // R16 22314 {2, 637272063}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 22315 }, 22316 clobbers: 33751040, // R16 R17 R25 22317 }, 22318 }, 22319 { 22320 name: "LoweredGetClosurePtr", 22321 argLen: 0, 22322 zeroWidth: true, 22323 reg: regInfo{ 22324 outputs: []outputInfo{ 22325 {0, 67108864}, // R26 22326 }, 22327 }, 22328 }, 22329 { 22330 name: "LoweredGetCallerSP", 22331 argLen: 0, 22332 rematerializeable: true, 22333 reg: regInfo{ 22334 outputs: []outputInfo{ 22335 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22336 }, 22337 }, 22338 }, 22339 { 22340 name: "LoweredGetCallerPC", 22341 argLen: 0, 22342 rematerializeable: true, 22343 reg: regInfo{ 22344 outputs: []outputInfo{ 22345 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22346 }, 22347 }, 22348 }, 22349 { 22350 name: "FlagConstant", 22351 auxType: auxFlagConstant, 22352 argLen: 0, 22353 reg: regInfo{}, 22354 }, 22355 { 22356 name: "InvertFlags", 22357 argLen: 1, 22358 reg: regInfo{}, 22359 }, 22360 { 22361 name: "LDAR", 22362 argLen: 2, 22363 faultOnNilArg0: true, 22364 asm: arm64.ALDAR, 22365 reg: regInfo{ 22366 inputs: []inputInfo{ 22367 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22368 }, 22369 outputs: []outputInfo{ 22370 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22371 }, 22372 }, 22373 }, 22374 { 22375 name: "LDARB", 22376 argLen: 2, 22377 faultOnNilArg0: true, 22378 asm: arm64.ALDARB, 22379 reg: regInfo{ 22380 inputs: []inputInfo{ 22381 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22382 }, 22383 outputs: []outputInfo{ 22384 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22385 }, 22386 }, 22387 }, 22388 { 22389 name: "LDARW", 22390 argLen: 2, 22391 faultOnNilArg0: true, 22392 asm: arm64.ALDARW, 22393 reg: regInfo{ 22394 inputs: []inputInfo{ 22395 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22396 }, 22397 outputs: []outputInfo{ 22398 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22399 }, 22400 }, 22401 }, 22402 { 22403 name: "STLRB", 22404 argLen: 3, 22405 faultOnNilArg0: true, 22406 hasSideEffects: true, 22407 asm: arm64.ASTLRB, 22408 reg: regInfo{ 22409 inputs: []inputInfo{ 22410 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22411 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22412 }, 22413 }, 22414 }, 22415 { 22416 name: "STLR", 22417 argLen: 3, 22418 faultOnNilArg0: true, 22419 hasSideEffects: true, 22420 asm: arm64.ASTLR, 22421 reg: regInfo{ 22422 inputs: []inputInfo{ 22423 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22424 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22425 }, 22426 }, 22427 }, 22428 { 22429 name: "STLRW", 22430 argLen: 3, 22431 faultOnNilArg0: true, 22432 hasSideEffects: true, 22433 asm: arm64.ASTLRW, 22434 reg: regInfo{ 22435 inputs: []inputInfo{ 22436 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22437 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22438 }, 22439 }, 22440 }, 22441 { 22442 name: "LoweredAtomicExchange64", 22443 argLen: 3, 22444 resultNotInArgs: true, 22445 faultOnNilArg0: true, 22446 hasSideEffects: true, 22447 unsafePoint: true, 22448 reg: regInfo{ 22449 inputs: []inputInfo{ 22450 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22451 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22452 }, 22453 outputs: []outputInfo{ 22454 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22455 }, 22456 }, 22457 }, 22458 { 22459 name: "LoweredAtomicExchange32", 22460 argLen: 3, 22461 resultNotInArgs: true, 22462 faultOnNilArg0: true, 22463 hasSideEffects: true, 22464 unsafePoint: true, 22465 reg: regInfo{ 22466 inputs: []inputInfo{ 22467 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22468 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22469 }, 22470 outputs: []outputInfo{ 22471 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22472 }, 22473 }, 22474 }, 22475 { 22476 name: "LoweredAtomicExchange64Variant", 22477 argLen: 3, 22478 resultNotInArgs: true, 22479 faultOnNilArg0: true, 22480 hasSideEffects: true, 22481 reg: regInfo{ 22482 inputs: []inputInfo{ 22483 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22484 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22485 }, 22486 outputs: []outputInfo{ 22487 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22488 }, 22489 }, 22490 }, 22491 { 22492 name: "LoweredAtomicExchange32Variant", 22493 argLen: 3, 22494 resultNotInArgs: true, 22495 faultOnNilArg0: true, 22496 hasSideEffects: true, 22497 reg: regInfo{ 22498 inputs: []inputInfo{ 22499 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22500 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22501 }, 22502 outputs: []outputInfo{ 22503 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22504 }, 22505 }, 22506 }, 22507 { 22508 name: "LoweredAtomicAdd64", 22509 argLen: 3, 22510 resultNotInArgs: true, 22511 faultOnNilArg0: true, 22512 hasSideEffects: true, 22513 unsafePoint: true, 22514 reg: regInfo{ 22515 inputs: []inputInfo{ 22516 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22517 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22518 }, 22519 outputs: []outputInfo{ 22520 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22521 }, 22522 }, 22523 }, 22524 { 22525 name: "LoweredAtomicAdd32", 22526 argLen: 3, 22527 resultNotInArgs: true, 22528 faultOnNilArg0: true, 22529 hasSideEffects: true, 22530 unsafePoint: true, 22531 reg: regInfo{ 22532 inputs: []inputInfo{ 22533 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22534 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22535 }, 22536 outputs: []outputInfo{ 22537 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22538 }, 22539 }, 22540 }, 22541 { 22542 name: "LoweredAtomicAdd64Variant", 22543 argLen: 3, 22544 resultNotInArgs: true, 22545 faultOnNilArg0: true, 22546 hasSideEffects: true, 22547 reg: regInfo{ 22548 inputs: []inputInfo{ 22549 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22550 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22551 }, 22552 outputs: []outputInfo{ 22553 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22554 }, 22555 }, 22556 }, 22557 { 22558 name: "LoweredAtomicAdd32Variant", 22559 argLen: 3, 22560 resultNotInArgs: true, 22561 faultOnNilArg0: true, 22562 hasSideEffects: true, 22563 reg: regInfo{ 22564 inputs: []inputInfo{ 22565 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22566 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22567 }, 22568 outputs: []outputInfo{ 22569 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22570 }, 22571 }, 22572 }, 22573 { 22574 name: "LoweredAtomicCas64", 22575 argLen: 4, 22576 resultNotInArgs: true, 22577 clobberFlags: true, 22578 faultOnNilArg0: true, 22579 hasSideEffects: true, 22580 unsafePoint: true, 22581 reg: regInfo{ 22582 inputs: []inputInfo{ 22583 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22584 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22585 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22586 }, 22587 outputs: []outputInfo{ 22588 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22589 }, 22590 }, 22591 }, 22592 { 22593 name: "LoweredAtomicCas32", 22594 argLen: 4, 22595 resultNotInArgs: true, 22596 clobberFlags: true, 22597 faultOnNilArg0: true, 22598 hasSideEffects: true, 22599 unsafePoint: true, 22600 reg: regInfo{ 22601 inputs: []inputInfo{ 22602 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22603 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22604 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22605 }, 22606 outputs: []outputInfo{ 22607 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22608 }, 22609 }, 22610 }, 22611 { 22612 name: "LoweredAtomicCas64Variant", 22613 argLen: 4, 22614 resultNotInArgs: true, 22615 clobberFlags: true, 22616 faultOnNilArg0: true, 22617 hasSideEffects: true, 22618 unsafePoint: true, 22619 reg: regInfo{ 22620 inputs: []inputInfo{ 22621 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22622 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22623 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22624 }, 22625 outputs: []outputInfo{ 22626 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22627 }, 22628 }, 22629 }, 22630 { 22631 name: "LoweredAtomicCas32Variant", 22632 argLen: 4, 22633 resultNotInArgs: true, 22634 clobberFlags: true, 22635 faultOnNilArg0: true, 22636 hasSideEffects: true, 22637 unsafePoint: true, 22638 reg: regInfo{ 22639 inputs: []inputInfo{ 22640 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22641 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22642 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22643 }, 22644 outputs: []outputInfo{ 22645 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22646 }, 22647 }, 22648 }, 22649 { 22650 name: "LoweredAtomicAnd8", 22651 argLen: 3, 22652 resultNotInArgs: true, 22653 faultOnNilArg0: true, 22654 hasSideEffects: true, 22655 unsafePoint: true, 22656 asm: arm64.AAND, 22657 reg: regInfo{ 22658 inputs: []inputInfo{ 22659 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22660 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22661 }, 22662 outputs: []outputInfo{ 22663 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22664 }, 22665 }, 22666 }, 22667 { 22668 name: "LoweredAtomicAnd32", 22669 argLen: 3, 22670 resultNotInArgs: true, 22671 faultOnNilArg0: true, 22672 hasSideEffects: true, 22673 unsafePoint: true, 22674 asm: arm64.AAND, 22675 reg: regInfo{ 22676 inputs: []inputInfo{ 22677 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22678 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22679 }, 22680 outputs: []outputInfo{ 22681 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22682 }, 22683 }, 22684 }, 22685 { 22686 name: "LoweredAtomicOr8", 22687 argLen: 3, 22688 resultNotInArgs: true, 22689 faultOnNilArg0: true, 22690 hasSideEffects: true, 22691 unsafePoint: true, 22692 asm: arm64.AORR, 22693 reg: regInfo{ 22694 inputs: []inputInfo{ 22695 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22696 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22697 }, 22698 outputs: []outputInfo{ 22699 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22700 }, 22701 }, 22702 }, 22703 { 22704 name: "LoweredAtomicOr32", 22705 argLen: 3, 22706 resultNotInArgs: true, 22707 faultOnNilArg0: true, 22708 hasSideEffects: true, 22709 unsafePoint: true, 22710 asm: arm64.AORR, 22711 reg: regInfo{ 22712 inputs: []inputInfo{ 22713 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22714 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22715 }, 22716 outputs: []outputInfo{ 22717 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22718 }, 22719 }, 22720 }, 22721 { 22722 name: "LoweredAtomicAnd8Variant", 22723 argLen: 3, 22724 resultNotInArgs: true, 22725 faultOnNilArg0: true, 22726 hasSideEffects: true, 22727 unsafePoint: true, 22728 reg: regInfo{ 22729 inputs: []inputInfo{ 22730 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22731 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22732 }, 22733 outputs: []outputInfo{ 22734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22735 }, 22736 }, 22737 }, 22738 { 22739 name: "LoweredAtomicAnd32Variant", 22740 argLen: 3, 22741 resultNotInArgs: true, 22742 faultOnNilArg0: true, 22743 hasSideEffects: true, 22744 unsafePoint: true, 22745 reg: regInfo{ 22746 inputs: []inputInfo{ 22747 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22748 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22749 }, 22750 outputs: []outputInfo{ 22751 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22752 }, 22753 }, 22754 }, 22755 { 22756 name: "LoweredAtomicOr8Variant", 22757 argLen: 3, 22758 resultNotInArgs: true, 22759 faultOnNilArg0: true, 22760 hasSideEffects: true, 22761 reg: regInfo{ 22762 inputs: []inputInfo{ 22763 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22764 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22765 }, 22766 outputs: []outputInfo{ 22767 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22768 }, 22769 }, 22770 }, 22771 { 22772 name: "LoweredAtomicOr32Variant", 22773 argLen: 3, 22774 resultNotInArgs: true, 22775 faultOnNilArg0: true, 22776 hasSideEffects: true, 22777 reg: regInfo{ 22778 inputs: []inputInfo{ 22779 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 22780 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22781 }, 22782 outputs: []outputInfo{ 22783 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 22784 }, 22785 }, 22786 }, 22787 { 22788 name: "LoweredWB", 22789 auxType: auxSym, 22790 argLen: 3, 22791 clobberFlags: true, 22792 symEffect: SymNone, 22793 reg: regInfo{ 22794 inputs: []inputInfo{ 22795 {0, 4}, // R2 22796 {1, 8}, // R3 22797 }, 22798 clobbers: 9223372035244359680, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22799 }, 22800 }, 22801 { 22802 name: "LoweredPanicBoundsA", 22803 auxType: auxInt64, 22804 argLen: 3, 22805 call: true, 22806 reg: regInfo{ 22807 inputs: []inputInfo{ 22808 {0, 4}, // R2 22809 {1, 8}, // R3 22810 }, 22811 }, 22812 }, 22813 { 22814 name: "LoweredPanicBoundsB", 22815 auxType: auxInt64, 22816 argLen: 3, 22817 call: true, 22818 reg: regInfo{ 22819 inputs: []inputInfo{ 22820 {0, 2}, // R1 22821 {1, 4}, // R2 22822 }, 22823 }, 22824 }, 22825 { 22826 name: "LoweredPanicBoundsC", 22827 auxType: auxInt64, 22828 argLen: 3, 22829 call: true, 22830 reg: regInfo{ 22831 inputs: []inputInfo{ 22832 {0, 1}, // R0 22833 {1, 2}, // R1 22834 }, 22835 }, 22836 }, 22837 { 22838 name: "PRFM", 22839 auxType: auxInt64, 22840 argLen: 2, 22841 hasSideEffects: true, 22842 asm: arm64.APRFM, 22843 reg: regInfo{ 22844 inputs: []inputInfo{ 22845 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 22846 }, 22847 }, 22848 }, 22849 { 22850 name: "DMB", 22851 auxType: auxInt64, 22852 argLen: 1, 22853 hasSideEffects: true, 22854 asm: arm64.ADMB, 22855 reg: regInfo{}, 22856 }, 22857 22858 { 22859 name: "ADDV", 22860 argLen: 2, 22861 commutative: true, 22862 asm: loong64.AADDVU, 22863 reg: regInfo{ 22864 inputs: []inputInfo{ 22865 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22866 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22867 }, 22868 outputs: []outputInfo{ 22869 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22870 }, 22871 }, 22872 }, 22873 { 22874 name: "ADDVconst", 22875 auxType: auxInt64, 22876 argLen: 1, 22877 asm: loong64.AADDVU, 22878 reg: regInfo{ 22879 inputs: []inputInfo{ 22880 {0, 1072693244}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22881 }, 22882 outputs: []outputInfo{ 22883 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22884 }, 22885 }, 22886 }, 22887 { 22888 name: "SUBV", 22889 argLen: 2, 22890 asm: loong64.ASUBVU, 22891 reg: regInfo{ 22892 inputs: []inputInfo{ 22893 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22894 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22895 }, 22896 outputs: []outputInfo{ 22897 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22898 }, 22899 }, 22900 }, 22901 { 22902 name: "SUBVconst", 22903 auxType: auxInt64, 22904 argLen: 1, 22905 asm: loong64.ASUBVU, 22906 reg: regInfo{ 22907 inputs: []inputInfo{ 22908 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22909 }, 22910 outputs: []outputInfo{ 22911 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22912 }, 22913 }, 22914 }, 22915 { 22916 name: "MULV", 22917 argLen: 2, 22918 commutative: true, 22919 resultNotInArgs: true, 22920 reg: regInfo{ 22921 inputs: []inputInfo{ 22922 {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22923 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22924 }, 22925 outputs: []outputInfo{ 22926 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22927 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22928 }, 22929 }, 22930 }, 22931 { 22932 name: "MULVU", 22933 argLen: 2, 22934 commutative: true, 22935 resultNotInArgs: true, 22936 reg: regInfo{ 22937 inputs: []inputInfo{ 22938 {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22939 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22940 }, 22941 outputs: []outputInfo{ 22942 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22943 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22944 }, 22945 }, 22946 }, 22947 { 22948 name: "DIVV", 22949 argLen: 2, 22950 resultNotInArgs: true, 22951 reg: regInfo{ 22952 inputs: []inputInfo{ 22953 {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22954 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22955 }, 22956 outputs: []outputInfo{ 22957 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22958 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22959 }, 22960 }, 22961 }, 22962 { 22963 name: "DIVVU", 22964 argLen: 2, 22965 resultNotInArgs: true, 22966 reg: regInfo{ 22967 inputs: []inputInfo{ 22968 {0, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22969 {1, 1072496632}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 22970 }, 22971 outputs: []outputInfo{ 22972 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22973 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 22974 }, 22975 }, 22976 }, 22977 { 22978 name: "ADDF", 22979 argLen: 2, 22980 commutative: true, 22981 asm: loong64.AADDF, 22982 reg: regInfo{ 22983 inputs: []inputInfo{ 22984 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22985 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22986 }, 22987 outputs: []outputInfo{ 22988 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 22989 }, 22990 }, 22991 }, 22992 { 22993 name: "ADDD", 22994 argLen: 2, 22995 commutative: true, 22996 asm: loong64.AADDD, 22997 reg: regInfo{ 22998 inputs: []inputInfo{ 22999 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23000 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23001 }, 23002 outputs: []outputInfo{ 23003 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23004 }, 23005 }, 23006 }, 23007 { 23008 name: "SUBF", 23009 argLen: 2, 23010 asm: loong64.ASUBF, 23011 reg: regInfo{ 23012 inputs: []inputInfo{ 23013 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23014 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23015 }, 23016 outputs: []outputInfo{ 23017 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23018 }, 23019 }, 23020 }, 23021 { 23022 name: "SUBD", 23023 argLen: 2, 23024 asm: loong64.ASUBD, 23025 reg: regInfo{ 23026 inputs: []inputInfo{ 23027 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23028 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23029 }, 23030 outputs: []outputInfo{ 23031 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23032 }, 23033 }, 23034 }, 23035 { 23036 name: "MULF", 23037 argLen: 2, 23038 commutative: true, 23039 asm: loong64.AMULF, 23040 reg: regInfo{ 23041 inputs: []inputInfo{ 23042 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23043 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23044 }, 23045 outputs: []outputInfo{ 23046 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23047 }, 23048 }, 23049 }, 23050 { 23051 name: "MULD", 23052 argLen: 2, 23053 commutative: true, 23054 asm: loong64.AMULD, 23055 reg: regInfo{ 23056 inputs: []inputInfo{ 23057 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23058 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23059 }, 23060 outputs: []outputInfo{ 23061 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23062 }, 23063 }, 23064 }, 23065 { 23066 name: "DIVF", 23067 argLen: 2, 23068 asm: loong64.ADIVF, 23069 reg: regInfo{ 23070 inputs: []inputInfo{ 23071 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23072 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23073 }, 23074 outputs: []outputInfo{ 23075 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23076 }, 23077 }, 23078 }, 23079 { 23080 name: "DIVD", 23081 argLen: 2, 23082 asm: loong64.ADIVD, 23083 reg: regInfo{ 23084 inputs: []inputInfo{ 23085 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23086 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23087 }, 23088 outputs: []outputInfo{ 23089 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23090 }, 23091 }, 23092 }, 23093 { 23094 name: "AND", 23095 argLen: 2, 23096 commutative: true, 23097 asm: loong64.AAND, 23098 reg: regInfo{ 23099 inputs: []inputInfo{ 23100 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23101 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23102 }, 23103 outputs: []outputInfo{ 23104 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23105 }, 23106 }, 23107 }, 23108 { 23109 name: "ANDconst", 23110 auxType: auxInt64, 23111 argLen: 1, 23112 asm: loong64.AAND, 23113 reg: regInfo{ 23114 inputs: []inputInfo{ 23115 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23116 }, 23117 outputs: []outputInfo{ 23118 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23119 }, 23120 }, 23121 }, 23122 { 23123 name: "OR", 23124 argLen: 2, 23125 commutative: true, 23126 asm: loong64.AOR, 23127 reg: regInfo{ 23128 inputs: []inputInfo{ 23129 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23130 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23131 }, 23132 outputs: []outputInfo{ 23133 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23134 }, 23135 }, 23136 }, 23137 { 23138 name: "ORconst", 23139 auxType: auxInt64, 23140 argLen: 1, 23141 asm: loong64.AOR, 23142 reg: regInfo{ 23143 inputs: []inputInfo{ 23144 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23145 }, 23146 outputs: []outputInfo{ 23147 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23148 }, 23149 }, 23150 }, 23151 { 23152 name: "XOR", 23153 argLen: 2, 23154 commutative: true, 23155 asm: loong64.AXOR, 23156 reg: regInfo{ 23157 inputs: []inputInfo{ 23158 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23159 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23160 }, 23161 outputs: []outputInfo{ 23162 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23163 }, 23164 }, 23165 }, 23166 { 23167 name: "XORconst", 23168 auxType: auxInt64, 23169 argLen: 1, 23170 asm: loong64.AXOR, 23171 reg: regInfo{ 23172 inputs: []inputInfo{ 23173 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23174 }, 23175 outputs: []outputInfo{ 23176 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23177 }, 23178 }, 23179 }, 23180 { 23181 name: "NOR", 23182 argLen: 2, 23183 commutative: true, 23184 asm: loong64.ANOR, 23185 reg: regInfo{ 23186 inputs: []inputInfo{ 23187 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23188 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23189 }, 23190 outputs: []outputInfo{ 23191 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23192 }, 23193 }, 23194 }, 23195 { 23196 name: "NORconst", 23197 auxType: auxInt64, 23198 argLen: 1, 23199 asm: loong64.ANOR, 23200 reg: regInfo{ 23201 inputs: []inputInfo{ 23202 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23203 }, 23204 outputs: []outputInfo{ 23205 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23206 }, 23207 }, 23208 }, 23209 { 23210 name: "NEGV", 23211 argLen: 1, 23212 reg: regInfo{ 23213 inputs: []inputInfo{ 23214 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23215 }, 23216 outputs: []outputInfo{ 23217 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23218 }, 23219 }, 23220 }, 23221 { 23222 name: "NEGF", 23223 argLen: 1, 23224 asm: loong64.ANEGF, 23225 reg: regInfo{ 23226 inputs: []inputInfo{ 23227 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23228 }, 23229 outputs: []outputInfo{ 23230 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23231 }, 23232 }, 23233 }, 23234 { 23235 name: "NEGD", 23236 argLen: 1, 23237 asm: loong64.ANEGD, 23238 reg: regInfo{ 23239 inputs: []inputInfo{ 23240 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23241 }, 23242 outputs: []outputInfo{ 23243 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23244 }, 23245 }, 23246 }, 23247 { 23248 name: "SQRTD", 23249 argLen: 1, 23250 asm: loong64.ASQRTD, 23251 reg: regInfo{ 23252 inputs: []inputInfo{ 23253 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23254 }, 23255 outputs: []outputInfo{ 23256 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23257 }, 23258 }, 23259 }, 23260 { 23261 name: "SQRTF", 23262 argLen: 1, 23263 asm: loong64.ASQRTF, 23264 reg: regInfo{ 23265 inputs: []inputInfo{ 23266 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23267 }, 23268 outputs: []outputInfo{ 23269 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23270 }, 23271 }, 23272 }, 23273 { 23274 name: "MASKEQZ", 23275 argLen: 2, 23276 asm: loong64.AMASKEQZ, 23277 reg: regInfo{ 23278 inputs: []inputInfo{ 23279 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23280 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23281 }, 23282 outputs: []outputInfo{ 23283 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23284 }, 23285 }, 23286 }, 23287 { 23288 name: "MASKNEZ", 23289 argLen: 2, 23290 asm: loong64.AMASKNEZ, 23291 reg: regInfo{ 23292 inputs: []inputInfo{ 23293 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23294 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23295 }, 23296 outputs: []outputInfo{ 23297 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23298 }, 23299 }, 23300 }, 23301 { 23302 name: "SLLV", 23303 argLen: 2, 23304 asm: loong64.ASLLV, 23305 reg: regInfo{ 23306 inputs: []inputInfo{ 23307 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23308 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23309 }, 23310 outputs: []outputInfo{ 23311 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23312 }, 23313 }, 23314 }, 23315 { 23316 name: "SLLVconst", 23317 auxType: auxInt64, 23318 argLen: 1, 23319 asm: loong64.ASLLV, 23320 reg: regInfo{ 23321 inputs: []inputInfo{ 23322 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23323 }, 23324 outputs: []outputInfo{ 23325 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23326 }, 23327 }, 23328 }, 23329 { 23330 name: "SRLV", 23331 argLen: 2, 23332 asm: loong64.ASRLV, 23333 reg: regInfo{ 23334 inputs: []inputInfo{ 23335 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23336 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23337 }, 23338 outputs: []outputInfo{ 23339 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23340 }, 23341 }, 23342 }, 23343 { 23344 name: "SRLVconst", 23345 auxType: auxInt64, 23346 argLen: 1, 23347 asm: loong64.ASRLV, 23348 reg: regInfo{ 23349 inputs: []inputInfo{ 23350 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23351 }, 23352 outputs: []outputInfo{ 23353 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23354 }, 23355 }, 23356 }, 23357 { 23358 name: "SRAV", 23359 argLen: 2, 23360 asm: loong64.ASRAV, 23361 reg: regInfo{ 23362 inputs: []inputInfo{ 23363 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23364 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23365 }, 23366 outputs: []outputInfo{ 23367 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23368 }, 23369 }, 23370 }, 23371 { 23372 name: "SRAVconst", 23373 auxType: auxInt64, 23374 argLen: 1, 23375 asm: loong64.ASRAV, 23376 reg: regInfo{ 23377 inputs: []inputInfo{ 23378 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23379 }, 23380 outputs: []outputInfo{ 23381 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23382 }, 23383 }, 23384 }, 23385 { 23386 name: "ROTR", 23387 argLen: 2, 23388 asm: loong64.AROTR, 23389 reg: regInfo{ 23390 inputs: []inputInfo{ 23391 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23392 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23393 }, 23394 outputs: []outputInfo{ 23395 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23396 }, 23397 }, 23398 }, 23399 { 23400 name: "ROTRV", 23401 argLen: 2, 23402 asm: loong64.AROTRV, 23403 reg: regInfo{ 23404 inputs: []inputInfo{ 23405 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23406 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23407 }, 23408 outputs: []outputInfo{ 23409 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23410 }, 23411 }, 23412 }, 23413 { 23414 name: "ROTRconst", 23415 auxType: auxInt64, 23416 argLen: 1, 23417 asm: loong64.AROTR, 23418 reg: regInfo{ 23419 inputs: []inputInfo{ 23420 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23421 }, 23422 outputs: []outputInfo{ 23423 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23424 }, 23425 }, 23426 }, 23427 { 23428 name: "ROTRVconst", 23429 auxType: auxInt64, 23430 argLen: 1, 23431 asm: loong64.AROTRV, 23432 reg: regInfo{ 23433 inputs: []inputInfo{ 23434 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23435 }, 23436 outputs: []outputInfo{ 23437 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23438 }, 23439 }, 23440 }, 23441 { 23442 name: "SGT", 23443 argLen: 2, 23444 asm: loong64.ASGT, 23445 reg: regInfo{ 23446 inputs: []inputInfo{ 23447 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23448 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23449 }, 23450 outputs: []outputInfo{ 23451 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23452 }, 23453 }, 23454 }, 23455 { 23456 name: "SGTconst", 23457 auxType: auxInt64, 23458 argLen: 1, 23459 asm: loong64.ASGT, 23460 reg: regInfo{ 23461 inputs: []inputInfo{ 23462 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23463 }, 23464 outputs: []outputInfo{ 23465 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23466 }, 23467 }, 23468 }, 23469 { 23470 name: "SGTU", 23471 argLen: 2, 23472 asm: loong64.ASGTU, 23473 reg: regInfo{ 23474 inputs: []inputInfo{ 23475 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23476 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23477 }, 23478 outputs: []outputInfo{ 23479 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23480 }, 23481 }, 23482 }, 23483 { 23484 name: "SGTUconst", 23485 auxType: auxInt64, 23486 argLen: 1, 23487 asm: loong64.ASGTU, 23488 reg: regInfo{ 23489 inputs: []inputInfo{ 23490 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23491 }, 23492 outputs: []outputInfo{ 23493 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23494 }, 23495 }, 23496 }, 23497 { 23498 name: "CMPEQF", 23499 argLen: 2, 23500 asm: loong64.ACMPEQF, 23501 reg: regInfo{ 23502 inputs: []inputInfo{ 23503 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23504 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23505 }, 23506 }, 23507 }, 23508 { 23509 name: "CMPEQD", 23510 argLen: 2, 23511 asm: loong64.ACMPEQD, 23512 reg: regInfo{ 23513 inputs: []inputInfo{ 23514 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23515 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23516 }, 23517 }, 23518 }, 23519 { 23520 name: "CMPGEF", 23521 argLen: 2, 23522 asm: loong64.ACMPGEF, 23523 reg: regInfo{ 23524 inputs: []inputInfo{ 23525 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23526 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23527 }, 23528 }, 23529 }, 23530 { 23531 name: "CMPGED", 23532 argLen: 2, 23533 asm: loong64.ACMPGED, 23534 reg: regInfo{ 23535 inputs: []inputInfo{ 23536 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23537 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23538 }, 23539 }, 23540 }, 23541 { 23542 name: "CMPGTF", 23543 argLen: 2, 23544 asm: loong64.ACMPGTF, 23545 reg: regInfo{ 23546 inputs: []inputInfo{ 23547 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23548 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23549 }, 23550 }, 23551 }, 23552 { 23553 name: "CMPGTD", 23554 argLen: 2, 23555 asm: loong64.ACMPGTD, 23556 reg: regInfo{ 23557 inputs: []inputInfo{ 23558 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23559 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23560 }, 23561 }, 23562 }, 23563 { 23564 name: "MOVVconst", 23565 auxType: auxInt64, 23566 argLen: 0, 23567 rematerializeable: true, 23568 asm: loong64.AMOVV, 23569 reg: regInfo{ 23570 outputs: []outputInfo{ 23571 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23572 }, 23573 }, 23574 }, 23575 { 23576 name: "MOVFconst", 23577 auxType: auxFloat64, 23578 argLen: 0, 23579 rematerializeable: true, 23580 asm: loong64.AMOVF, 23581 reg: regInfo{ 23582 outputs: []outputInfo{ 23583 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23584 }, 23585 }, 23586 }, 23587 { 23588 name: "MOVDconst", 23589 auxType: auxFloat64, 23590 argLen: 0, 23591 rematerializeable: true, 23592 asm: loong64.AMOVD, 23593 reg: regInfo{ 23594 outputs: []outputInfo{ 23595 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23596 }, 23597 }, 23598 }, 23599 { 23600 name: "MOVVaddr", 23601 auxType: auxSymOff, 23602 argLen: 1, 23603 rematerializeable: true, 23604 symEffect: SymAddr, 23605 asm: loong64.AMOVV, 23606 reg: regInfo{ 23607 inputs: []inputInfo{ 23608 {0, 4611686018427387908}, // SP SB 23609 }, 23610 outputs: []outputInfo{ 23611 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23612 }, 23613 }, 23614 }, 23615 { 23616 name: "MOVBload", 23617 auxType: auxSymOff, 23618 argLen: 2, 23619 faultOnNilArg0: true, 23620 symEffect: SymRead, 23621 asm: loong64.AMOVB, 23622 reg: regInfo{ 23623 inputs: []inputInfo{ 23624 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23625 }, 23626 outputs: []outputInfo{ 23627 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23628 }, 23629 }, 23630 }, 23631 { 23632 name: "MOVBUload", 23633 auxType: auxSymOff, 23634 argLen: 2, 23635 faultOnNilArg0: true, 23636 symEffect: SymRead, 23637 asm: loong64.AMOVBU, 23638 reg: regInfo{ 23639 inputs: []inputInfo{ 23640 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23641 }, 23642 outputs: []outputInfo{ 23643 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23644 }, 23645 }, 23646 }, 23647 { 23648 name: "MOVHload", 23649 auxType: auxSymOff, 23650 argLen: 2, 23651 faultOnNilArg0: true, 23652 symEffect: SymRead, 23653 asm: loong64.AMOVH, 23654 reg: regInfo{ 23655 inputs: []inputInfo{ 23656 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23657 }, 23658 outputs: []outputInfo{ 23659 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23660 }, 23661 }, 23662 }, 23663 { 23664 name: "MOVHUload", 23665 auxType: auxSymOff, 23666 argLen: 2, 23667 faultOnNilArg0: true, 23668 symEffect: SymRead, 23669 asm: loong64.AMOVHU, 23670 reg: regInfo{ 23671 inputs: []inputInfo{ 23672 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23673 }, 23674 outputs: []outputInfo{ 23675 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23676 }, 23677 }, 23678 }, 23679 { 23680 name: "MOVWload", 23681 auxType: auxSymOff, 23682 argLen: 2, 23683 faultOnNilArg0: true, 23684 symEffect: SymRead, 23685 asm: loong64.AMOVW, 23686 reg: regInfo{ 23687 inputs: []inputInfo{ 23688 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23689 }, 23690 outputs: []outputInfo{ 23691 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23692 }, 23693 }, 23694 }, 23695 { 23696 name: "MOVWUload", 23697 auxType: auxSymOff, 23698 argLen: 2, 23699 faultOnNilArg0: true, 23700 symEffect: SymRead, 23701 asm: loong64.AMOVWU, 23702 reg: regInfo{ 23703 inputs: []inputInfo{ 23704 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23705 }, 23706 outputs: []outputInfo{ 23707 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23708 }, 23709 }, 23710 }, 23711 { 23712 name: "MOVVload", 23713 auxType: auxSymOff, 23714 argLen: 2, 23715 faultOnNilArg0: true, 23716 symEffect: SymRead, 23717 asm: loong64.AMOVV, 23718 reg: regInfo{ 23719 inputs: []inputInfo{ 23720 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23721 }, 23722 outputs: []outputInfo{ 23723 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23724 }, 23725 }, 23726 }, 23727 { 23728 name: "MOVFload", 23729 auxType: auxSymOff, 23730 argLen: 2, 23731 faultOnNilArg0: true, 23732 symEffect: SymRead, 23733 asm: loong64.AMOVF, 23734 reg: regInfo{ 23735 inputs: []inputInfo{ 23736 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23737 }, 23738 outputs: []outputInfo{ 23739 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23740 }, 23741 }, 23742 }, 23743 { 23744 name: "MOVDload", 23745 auxType: auxSymOff, 23746 argLen: 2, 23747 faultOnNilArg0: true, 23748 symEffect: SymRead, 23749 asm: loong64.AMOVD, 23750 reg: regInfo{ 23751 inputs: []inputInfo{ 23752 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23753 }, 23754 outputs: []outputInfo{ 23755 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23756 }, 23757 }, 23758 }, 23759 { 23760 name: "MOVBstore", 23761 auxType: auxSymOff, 23762 argLen: 3, 23763 faultOnNilArg0: true, 23764 symEffect: SymWrite, 23765 asm: loong64.AMOVB, 23766 reg: regInfo{ 23767 inputs: []inputInfo{ 23768 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23769 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23770 }, 23771 }, 23772 }, 23773 { 23774 name: "MOVHstore", 23775 auxType: auxSymOff, 23776 argLen: 3, 23777 faultOnNilArg0: true, 23778 symEffect: SymWrite, 23779 asm: loong64.AMOVH, 23780 reg: regInfo{ 23781 inputs: []inputInfo{ 23782 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23783 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23784 }, 23785 }, 23786 }, 23787 { 23788 name: "MOVWstore", 23789 auxType: auxSymOff, 23790 argLen: 3, 23791 faultOnNilArg0: true, 23792 symEffect: SymWrite, 23793 asm: loong64.AMOVW, 23794 reg: regInfo{ 23795 inputs: []inputInfo{ 23796 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23797 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23798 }, 23799 }, 23800 }, 23801 { 23802 name: "MOVVstore", 23803 auxType: auxSymOff, 23804 argLen: 3, 23805 faultOnNilArg0: true, 23806 symEffect: SymWrite, 23807 asm: loong64.AMOVV, 23808 reg: regInfo{ 23809 inputs: []inputInfo{ 23810 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23811 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23812 }, 23813 }, 23814 }, 23815 { 23816 name: "MOVFstore", 23817 auxType: auxSymOff, 23818 argLen: 3, 23819 faultOnNilArg0: true, 23820 symEffect: SymWrite, 23821 asm: loong64.AMOVF, 23822 reg: regInfo{ 23823 inputs: []inputInfo{ 23824 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23825 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23826 }, 23827 }, 23828 }, 23829 { 23830 name: "MOVDstore", 23831 auxType: auxSymOff, 23832 argLen: 3, 23833 faultOnNilArg0: true, 23834 symEffect: SymWrite, 23835 asm: loong64.AMOVD, 23836 reg: regInfo{ 23837 inputs: []inputInfo{ 23838 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23839 {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 23840 }, 23841 }, 23842 }, 23843 { 23844 name: "MOVBstorezero", 23845 auxType: auxSymOff, 23846 argLen: 2, 23847 faultOnNilArg0: true, 23848 symEffect: SymWrite, 23849 asm: loong64.AMOVB, 23850 reg: regInfo{ 23851 inputs: []inputInfo{ 23852 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23853 }, 23854 }, 23855 }, 23856 { 23857 name: "MOVHstorezero", 23858 auxType: auxSymOff, 23859 argLen: 2, 23860 faultOnNilArg0: true, 23861 symEffect: SymWrite, 23862 asm: loong64.AMOVH, 23863 reg: regInfo{ 23864 inputs: []inputInfo{ 23865 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23866 }, 23867 }, 23868 }, 23869 { 23870 name: "MOVWstorezero", 23871 auxType: auxSymOff, 23872 argLen: 2, 23873 faultOnNilArg0: true, 23874 symEffect: SymWrite, 23875 asm: loong64.AMOVW, 23876 reg: regInfo{ 23877 inputs: []inputInfo{ 23878 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23879 }, 23880 }, 23881 }, 23882 { 23883 name: "MOVVstorezero", 23884 auxType: auxSymOff, 23885 argLen: 2, 23886 faultOnNilArg0: true, 23887 symEffect: SymWrite, 23888 asm: loong64.AMOVV, 23889 reg: regInfo{ 23890 inputs: []inputInfo{ 23891 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 23892 }, 23893 }, 23894 }, 23895 { 23896 name: "MOVBreg", 23897 argLen: 1, 23898 asm: loong64.AMOVB, 23899 reg: regInfo{ 23900 inputs: []inputInfo{ 23901 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23902 }, 23903 outputs: []outputInfo{ 23904 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23905 }, 23906 }, 23907 }, 23908 { 23909 name: "MOVBUreg", 23910 argLen: 1, 23911 asm: loong64.AMOVBU, 23912 reg: regInfo{ 23913 inputs: []inputInfo{ 23914 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23915 }, 23916 outputs: []outputInfo{ 23917 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23918 }, 23919 }, 23920 }, 23921 { 23922 name: "MOVHreg", 23923 argLen: 1, 23924 asm: loong64.AMOVH, 23925 reg: regInfo{ 23926 inputs: []inputInfo{ 23927 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23928 }, 23929 outputs: []outputInfo{ 23930 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23931 }, 23932 }, 23933 }, 23934 { 23935 name: "MOVHUreg", 23936 argLen: 1, 23937 asm: loong64.AMOVHU, 23938 reg: regInfo{ 23939 inputs: []inputInfo{ 23940 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23941 }, 23942 outputs: []outputInfo{ 23943 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23944 }, 23945 }, 23946 }, 23947 { 23948 name: "MOVWreg", 23949 argLen: 1, 23950 asm: loong64.AMOVW, 23951 reg: regInfo{ 23952 inputs: []inputInfo{ 23953 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23954 }, 23955 outputs: []outputInfo{ 23956 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23957 }, 23958 }, 23959 }, 23960 { 23961 name: "MOVWUreg", 23962 argLen: 1, 23963 asm: loong64.AMOVWU, 23964 reg: regInfo{ 23965 inputs: []inputInfo{ 23966 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23967 }, 23968 outputs: []outputInfo{ 23969 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23970 }, 23971 }, 23972 }, 23973 { 23974 name: "MOVVreg", 23975 argLen: 1, 23976 asm: loong64.AMOVV, 23977 reg: regInfo{ 23978 inputs: []inputInfo{ 23979 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 23980 }, 23981 outputs: []outputInfo{ 23982 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23983 }, 23984 }, 23985 }, 23986 { 23987 name: "MOVVnop", 23988 argLen: 1, 23989 resultInArg0: true, 23990 reg: regInfo{ 23991 inputs: []inputInfo{ 23992 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23993 }, 23994 outputs: []outputInfo{ 23995 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 23996 }, 23997 }, 23998 }, 23999 { 24000 name: "MOVWF", 24001 argLen: 1, 24002 asm: loong64.AMOVWF, 24003 reg: regInfo{ 24004 inputs: []inputInfo{ 24005 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24006 }, 24007 outputs: []outputInfo{ 24008 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24009 }, 24010 }, 24011 }, 24012 { 24013 name: "MOVWD", 24014 argLen: 1, 24015 asm: loong64.AMOVWD, 24016 reg: regInfo{ 24017 inputs: []inputInfo{ 24018 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24019 }, 24020 outputs: []outputInfo{ 24021 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24022 }, 24023 }, 24024 }, 24025 { 24026 name: "MOVVF", 24027 argLen: 1, 24028 asm: loong64.AMOVVF, 24029 reg: regInfo{ 24030 inputs: []inputInfo{ 24031 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24032 }, 24033 outputs: []outputInfo{ 24034 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24035 }, 24036 }, 24037 }, 24038 { 24039 name: "MOVVD", 24040 argLen: 1, 24041 asm: loong64.AMOVVD, 24042 reg: regInfo{ 24043 inputs: []inputInfo{ 24044 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24045 }, 24046 outputs: []outputInfo{ 24047 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24048 }, 24049 }, 24050 }, 24051 { 24052 name: "TRUNCFW", 24053 argLen: 1, 24054 asm: loong64.ATRUNCFW, 24055 reg: regInfo{ 24056 inputs: []inputInfo{ 24057 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24058 }, 24059 outputs: []outputInfo{ 24060 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24061 }, 24062 }, 24063 }, 24064 { 24065 name: "TRUNCDW", 24066 argLen: 1, 24067 asm: loong64.ATRUNCDW, 24068 reg: regInfo{ 24069 inputs: []inputInfo{ 24070 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24071 }, 24072 outputs: []outputInfo{ 24073 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24074 }, 24075 }, 24076 }, 24077 { 24078 name: "TRUNCFV", 24079 argLen: 1, 24080 asm: loong64.ATRUNCFV, 24081 reg: regInfo{ 24082 inputs: []inputInfo{ 24083 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24084 }, 24085 outputs: []outputInfo{ 24086 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24087 }, 24088 }, 24089 }, 24090 { 24091 name: "TRUNCDV", 24092 argLen: 1, 24093 asm: loong64.ATRUNCDV, 24094 reg: regInfo{ 24095 inputs: []inputInfo{ 24096 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24097 }, 24098 outputs: []outputInfo{ 24099 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24100 }, 24101 }, 24102 }, 24103 { 24104 name: "MOVFD", 24105 argLen: 1, 24106 asm: loong64.AMOVFD, 24107 reg: regInfo{ 24108 inputs: []inputInfo{ 24109 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24110 }, 24111 outputs: []outputInfo{ 24112 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24113 }, 24114 }, 24115 }, 24116 { 24117 name: "MOVDF", 24118 argLen: 1, 24119 asm: loong64.AMOVDF, 24120 reg: regInfo{ 24121 inputs: []inputInfo{ 24122 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24123 }, 24124 outputs: []outputInfo{ 24125 {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24126 }, 24127 }, 24128 }, 24129 { 24130 name: "CALLstatic", 24131 auxType: auxCallOff, 24132 argLen: 1, 24133 clobberFlags: true, 24134 call: true, 24135 reg: regInfo{ 24136 clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24137 }, 24138 }, 24139 { 24140 name: "CALLtail", 24141 auxType: auxCallOff, 24142 argLen: 1, 24143 clobberFlags: true, 24144 call: true, 24145 tailCall: true, 24146 reg: regInfo{ 24147 clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24148 }, 24149 }, 24150 { 24151 name: "CALLclosure", 24152 auxType: auxCallOff, 24153 argLen: 3, 24154 clobberFlags: true, 24155 call: true, 24156 reg: regInfo{ 24157 inputs: []inputInfo{ 24158 {1, 268435456}, // R29 24159 {0, 1070596092}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24160 }, 24161 clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24162 }, 24163 }, 24164 { 24165 name: "CALLinter", 24166 auxType: auxCallOff, 24167 argLen: 2, 24168 clobberFlags: true, 24169 call: true, 24170 reg: regInfo{ 24171 inputs: []inputInfo{ 24172 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24173 }, 24174 clobbers: 4611686018426339320, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24175 }, 24176 }, 24177 { 24178 name: "DUFFZERO", 24179 auxType: auxInt64, 24180 argLen: 2, 24181 faultOnNilArg0: true, 24182 reg: regInfo{ 24183 inputs: []inputInfo{ 24184 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24185 }, 24186 clobbers: 262146, // R1 R19 24187 }, 24188 }, 24189 { 24190 name: "DUFFCOPY", 24191 auxType: auxInt64, 24192 argLen: 3, 24193 faultOnNilArg0: true, 24194 faultOnNilArg1: true, 24195 reg: regInfo{ 24196 inputs: []inputInfo{ 24197 {0, 524288}, // R20 24198 {1, 262144}, // R19 24199 }, 24200 clobbers: 786434, // R1 R19 R20 24201 }, 24202 }, 24203 { 24204 name: "LoweredZero", 24205 auxType: auxInt64, 24206 argLen: 3, 24207 clobberFlags: true, 24208 faultOnNilArg0: true, 24209 reg: regInfo{ 24210 inputs: []inputInfo{ 24211 {0, 262144}, // R19 24212 {1, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24213 }, 24214 clobbers: 262144, // R19 24215 }, 24216 }, 24217 { 24218 name: "LoweredMove", 24219 auxType: auxInt64, 24220 argLen: 4, 24221 clobberFlags: true, 24222 faultOnNilArg0: true, 24223 faultOnNilArg1: true, 24224 reg: regInfo{ 24225 inputs: []inputInfo{ 24226 {0, 8}, // R4 24227 {1, 262144}, // R19 24228 {2, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24229 }, 24230 clobbers: 262152, // R4 R19 24231 }, 24232 }, 24233 { 24234 name: "LoweredAtomicLoad8", 24235 argLen: 2, 24236 faultOnNilArg0: true, 24237 reg: regInfo{ 24238 inputs: []inputInfo{ 24239 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24240 }, 24241 outputs: []outputInfo{ 24242 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24243 }, 24244 }, 24245 }, 24246 { 24247 name: "LoweredAtomicLoad32", 24248 argLen: 2, 24249 faultOnNilArg0: true, 24250 reg: regInfo{ 24251 inputs: []inputInfo{ 24252 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24253 }, 24254 outputs: []outputInfo{ 24255 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24256 }, 24257 }, 24258 }, 24259 { 24260 name: "LoweredAtomicLoad64", 24261 argLen: 2, 24262 faultOnNilArg0: true, 24263 reg: regInfo{ 24264 inputs: []inputInfo{ 24265 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24266 }, 24267 outputs: []outputInfo{ 24268 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24269 }, 24270 }, 24271 }, 24272 { 24273 name: "LoweredAtomicStore8", 24274 argLen: 3, 24275 faultOnNilArg0: true, 24276 hasSideEffects: true, 24277 reg: regInfo{ 24278 inputs: []inputInfo{ 24279 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24280 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24281 }, 24282 }, 24283 }, 24284 { 24285 name: "LoweredAtomicStore32", 24286 argLen: 3, 24287 faultOnNilArg0: true, 24288 hasSideEffects: true, 24289 reg: regInfo{ 24290 inputs: []inputInfo{ 24291 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24292 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24293 }, 24294 }, 24295 }, 24296 { 24297 name: "LoweredAtomicStore64", 24298 argLen: 3, 24299 faultOnNilArg0: true, 24300 hasSideEffects: true, 24301 reg: regInfo{ 24302 inputs: []inputInfo{ 24303 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24304 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24305 }, 24306 }, 24307 }, 24308 { 24309 name: "LoweredAtomicStorezero32", 24310 argLen: 2, 24311 faultOnNilArg0: true, 24312 hasSideEffects: true, 24313 reg: regInfo{ 24314 inputs: []inputInfo{ 24315 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24316 }, 24317 }, 24318 }, 24319 { 24320 name: "LoweredAtomicStorezero64", 24321 argLen: 2, 24322 faultOnNilArg0: true, 24323 hasSideEffects: true, 24324 reg: regInfo{ 24325 inputs: []inputInfo{ 24326 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24327 }, 24328 }, 24329 }, 24330 { 24331 name: "LoweredAtomicExchange32", 24332 argLen: 3, 24333 resultNotInArgs: true, 24334 faultOnNilArg0: true, 24335 hasSideEffects: true, 24336 unsafePoint: true, 24337 reg: regInfo{ 24338 inputs: []inputInfo{ 24339 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24340 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24341 }, 24342 outputs: []outputInfo{ 24343 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24344 }, 24345 }, 24346 }, 24347 { 24348 name: "LoweredAtomicExchange64", 24349 argLen: 3, 24350 resultNotInArgs: true, 24351 faultOnNilArg0: true, 24352 hasSideEffects: true, 24353 unsafePoint: true, 24354 reg: regInfo{ 24355 inputs: []inputInfo{ 24356 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24357 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24358 }, 24359 outputs: []outputInfo{ 24360 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24361 }, 24362 }, 24363 }, 24364 { 24365 name: "LoweredAtomicAdd32", 24366 argLen: 3, 24367 resultNotInArgs: true, 24368 faultOnNilArg0: true, 24369 hasSideEffects: true, 24370 unsafePoint: true, 24371 reg: regInfo{ 24372 inputs: []inputInfo{ 24373 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24374 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24375 }, 24376 outputs: []outputInfo{ 24377 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24378 }, 24379 }, 24380 }, 24381 { 24382 name: "LoweredAtomicAdd64", 24383 argLen: 3, 24384 resultNotInArgs: true, 24385 faultOnNilArg0: true, 24386 hasSideEffects: true, 24387 unsafePoint: true, 24388 reg: regInfo{ 24389 inputs: []inputInfo{ 24390 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24391 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24392 }, 24393 outputs: []outputInfo{ 24394 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24395 }, 24396 }, 24397 }, 24398 { 24399 name: "LoweredAtomicAddconst32", 24400 auxType: auxInt32, 24401 argLen: 2, 24402 resultNotInArgs: true, 24403 faultOnNilArg0: true, 24404 hasSideEffects: true, 24405 unsafePoint: true, 24406 reg: regInfo{ 24407 inputs: []inputInfo{ 24408 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24409 }, 24410 outputs: []outputInfo{ 24411 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24412 }, 24413 }, 24414 }, 24415 { 24416 name: "LoweredAtomicAddconst64", 24417 auxType: auxInt64, 24418 argLen: 2, 24419 resultNotInArgs: true, 24420 faultOnNilArg0: true, 24421 hasSideEffects: true, 24422 unsafePoint: true, 24423 reg: regInfo{ 24424 inputs: []inputInfo{ 24425 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24426 }, 24427 outputs: []outputInfo{ 24428 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24429 }, 24430 }, 24431 }, 24432 { 24433 name: "LoweredAtomicCas32", 24434 argLen: 4, 24435 resultNotInArgs: true, 24436 faultOnNilArg0: true, 24437 hasSideEffects: true, 24438 unsafePoint: true, 24439 reg: regInfo{ 24440 inputs: []inputInfo{ 24441 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24442 {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24443 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24444 }, 24445 outputs: []outputInfo{ 24446 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24447 }, 24448 }, 24449 }, 24450 { 24451 name: "LoweredAtomicCas64", 24452 argLen: 4, 24453 resultNotInArgs: true, 24454 faultOnNilArg0: true, 24455 hasSideEffects: true, 24456 unsafePoint: true, 24457 reg: regInfo{ 24458 inputs: []inputInfo{ 24459 {1, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24460 {2, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24461 {0, 4611686019500081148}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 SB 24462 }, 24463 outputs: []outputInfo{ 24464 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24465 }, 24466 }, 24467 }, 24468 { 24469 name: "LoweredNilCheck", 24470 argLen: 2, 24471 nilCheck: true, 24472 faultOnNilArg0: true, 24473 reg: regInfo{ 24474 inputs: []inputInfo{ 24475 {0, 1072693240}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 g R23 R24 R25 R26 R27 R28 R29 R31 24476 }, 24477 }, 24478 }, 24479 { 24480 name: "FPFlagTrue", 24481 argLen: 1, 24482 reg: regInfo{ 24483 outputs: []outputInfo{ 24484 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24485 }, 24486 }, 24487 }, 24488 { 24489 name: "FPFlagFalse", 24490 argLen: 1, 24491 reg: regInfo{ 24492 outputs: []outputInfo{ 24493 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24494 }, 24495 }, 24496 }, 24497 { 24498 name: "LoweredGetClosurePtr", 24499 argLen: 0, 24500 zeroWidth: true, 24501 reg: regInfo{ 24502 outputs: []outputInfo{ 24503 {0, 268435456}, // R29 24504 }, 24505 }, 24506 }, 24507 { 24508 name: "LoweredGetCallerSP", 24509 argLen: 0, 24510 rematerializeable: true, 24511 reg: regInfo{ 24512 outputs: []outputInfo{ 24513 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24514 }, 24515 }, 24516 }, 24517 { 24518 name: "LoweredGetCallerPC", 24519 argLen: 0, 24520 rematerializeable: true, 24521 reg: regInfo{ 24522 outputs: []outputInfo{ 24523 {0, 1070596088}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31 24524 }, 24525 }, 24526 }, 24527 { 24528 name: "LoweredWB", 24529 auxType: auxSym, 24530 argLen: 3, 24531 clobberFlags: true, 24532 symEffect: SymNone, 24533 reg: regInfo{ 24534 inputs: []inputInfo{ 24535 {0, 67108864}, // R27 24536 {1, 134217728}, // R28 24537 }, 24538 clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 24539 }, 24540 }, 24541 { 24542 name: "LoweredPanicBoundsA", 24543 auxType: auxInt64, 24544 argLen: 3, 24545 call: true, 24546 reg: regInfo{ 24547 inputs: []inputInfo{ 24548 {0, 65536}, // R17 24549 {1, 8}, // R4 24550 }, 24551 }, 24552 }, 24553 { 24554 name: "LoweredPanicBoundsB", 24555 auxType: auxInt64, 24556 argLen: 3, 24557 call: true, 24558 reg: regInfo{ 24559 inputs: []inputInfo{ 24560 {0, 131072}, // R18 24561 {1, 65536}, // R17 24562 }, 24563 }, 24564 }, 24565 { 24566 name: "LoweredPanicBoundsC", 24567 auxType: auxInt64, 24568 argLen: 3, 24569 call: true, 24570 reg: regInfo{ 24571 inputs: []inputInfo{ 24572 {0, 262144}, // R19 24573 {1, 131072}, // R18 24574 }, 24575 }, 24576 }, 24577 24578 { 24579 name: "ADD", 24580 argLen: 2, 24581 commutative: true, 24582 asm: mips.AADDU, 24583 reg: regInfo{ 24584 inputs: []inputInfo{ 24585 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24586 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24587 }, 24588 outputs: []outputInfo{ 24589 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24590 }, 24591 }, 24592 }, 24593 { 24594 name: "ADDconst", 24595 auxType: auxInt32, 24596 argLen: 1, 24597 asm: mips.AADDU, 24598 reg: regInfo{ 24599 inputs: []inputInfo{ 24600 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 24601 }, 24602 outputs: []outputInfo{ 24603 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24604 }, 24605 }, 24606 }, 24607 { 24608 name: "SUB", 24609 argLen: 2, 24610 asm: mips.ASUBU, 24611 reg: regInfo{ 24612 inputs: []inputInfo{ 24613 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24614 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24615 }, 24616 outputs: []outputInfo{ 24617 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24618 }, 24619 }, 24620 }, 24621 { 24622 name: "SUBconst", 24623 auxType: auxInt32, 24624 argLen: 1, 24625 asm: mips.ASUBU, 24626 reg: regInfo{ 24627 inputs: []inputInfo{ 24628 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24629 }, 24630 outputs: []outputInfo{ 24631 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24632 }, 24633 }, 24634 }, 24635 { 24636 name: "MUL", 24637 argLen: 2, 24638 commutative: true, 24639 asm: mips.AMUL, 24640 reg: regInfo{ 24641 inputs: []inputInfo{ 24642 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24643 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24644 }, 24645 clobbers: 105553116266496, // HI LO 24646 outputs: []outputInfo{ 24647 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24648 }, 24649 }, 24650 }, 24651 { 24652 name: "MULT", 24653 argLen: 2, 24654 commutative: true, 24655 asm: mips.AMUL, 24656 reg: regInfo{ 24657 inputs: []inputInfo{ 24658 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24659 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24660 }, 24661 outputs: []outputInfo{ 24662 {0, 35184372088832}, // HI 24663 {1, 70368744177664}, // LO 24664 }, 24665 }, 24666 }, 24667 { 24668 name: "MULTU", 24669 argLen: 2, 24670 commutative: true, 24671 asm: mips.AMULU, 24672 reg: regInfo{ 24673 inputs: []inputInfo{ 24674 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24675 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24676 }, 24677 outputs: []outputInfo{ 24678 {0, 35184372088832}, // HI 24679 {1, 70368744177664}, // LO 24680 }, 24681 }, 24682 }, 24683 { 24684 name: "DIV", 24685 argLen: 2, 24686 asm: mips.ADIV, 24687 reg: regInfo{ 24688 inputs: []inputInfo{ 24689 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24690 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24691 }, 24692 outputs: []outputInfo{ 24693 {0, 35184372088832}, // HI 24694 {1, 70368744177664}, // LO 24695 }, 24696 }, 24697 }, 24698 { 24699 name: "DIVU", 24700 argLen: 2, 24701 asm: mips.ADIVU, 24702 reg: regInfo{ 24703 inputs: []inputInfo{ 24704 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24705 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24706 }, 24707 outputs: []outputInfo{ 24708 {0, 35184372088832}, // HI 24709 {1, 70368744177664}, // LO 24710 }, 24711 }, 24712 }, 24713 { 24714 name: "ADDF", 24715 argLen: 2, 24716 commutative: true, 24717 asm: mips.AADDF, 24718 reg: regInfo{ 24719 inputs: []inputInfo{ 24720 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24721 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24722 }, 24723 outputs: []outputInfo{ 24724 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24725 }, 24726 }, 24727 }, 24728 { 24729 name: "ADDD", 24730 argLen: 2, 24731 commutative: true, 24732 asm: mips.AADDD, 24733 reg: regInfo{ 24734 inputs: []inputInfo{ 24735 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24736 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24737 }, 24738 outputs: []outputInfo{ 24739 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24740 }, 24741 }, 24742 }, 24743 { 24744 name: "SUBF", 24745 argLen: 2, 24746 asm: mips.ASUBF, 24747 reg: regInfo{ 24748 inputs: []inputInfo{ 24749 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24750 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24751 }, 24752 outputs: []outputInfo{ 24753 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24754 }, 24755 }, 24756 }, 24757 { 24758 name: "SUBD", 24759 argLen: 2, 24760 asm: mips.ASUBD, 24761 reg: regInfo{ 24762 inputs: []inputInfo{ 24763 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24764 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24765 }, 24766 outputs: []outputInfo{ 24767 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24768 }, 24769 }, 24770 }, 24771 { 24772 name: "MULF", 24773 argLen: 2, 24774 commutative: true, 24775 asm: mips.AMULF, 24776 reg: regInfo{ 24777 inputs: []inputInfo{ 24778 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24779 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24780 }, 24781 outputs: []outputInfo{ 24782 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24783 }, 24784 }, 24785 }, 24786 { 24787 name: "MULD", 24788 argLen: 2, 24789 commutative: true, 24790 asm: mips.AMULD, 24791 reg: regInfo{ 24792 inputs: []inputInfo{ 24793 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24794 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24795 }, 24796 outputs: []outputInfo{ 24797 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24798 }, 24799 }, 24800 }, 24801 { 24802 name: "DIVF", 24803 argLen: 2, 24804 asm: mips.ADIVF, 24805 reg: regInfo{ 24806 inputs: []inputInfo{ 24807 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24808 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24809 }, 24810 outputs: []outputInfo{ 24811 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24812 }, 24813 }, 24814 }, 24815 { 24816 name: "DIVD", 24817 argLen: 2, 24818 asm: mips.ADIVD, 24819 reg: regInfo{ 24820 inputs: []inputInfo{ 24821 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24822 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24823 }, 24824 outputs: []outputInfo{ 24825 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24826 }, 24827 }, 24828 }, 24829 { 24830 name: "AND", 24831 argLen: 2, 24832 commutative: true, 24833 asm: mips.AAND, 24834 reg: regInfo{ 24835 inputs: []inputInfo{ 24836 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24837 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24838 }, 24839 outputs: []outputInfo{ 24840 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24841 }, 24842 }, 24843 }, 24844 { 24845 name: "ANDconst", 24846 auxType: auxInt32, 24847 argLen: 1, 24848 asm: mips.AAND, 24849 reg: regInfo{ 24850 inputs: []inputInfo{ 24851 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24852 }, 24853 outputs: []outputInfo{ 24854 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24855 }, 24856 }, 24857 }, 24858 { 24859 name: "OR", 24860 argLen: 2, 24861 commutative: true, 24862 asm: mips.AOR, 24863 reg: regInfo{ 24864 inputs: []inputInfo{ 24865 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24866 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24867 }, 24868 outputs: []outputInfo{ 24869 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24870 }, 24871 }, 24872 }, 24873 { 24874 name: "ORconst", 24875 auxType: auxInt32, 24876 argLen: 1, 24877 asm: mips.AOR, 24878 reg: regInfo{ 24879 inputs: []inputInfo{ 24880 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24881 }, 24882 outputs: []outputInfo{ 24883 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24884 }, 24885 }, 24886 }, 24887 { 24888 name: "XOR", 24889 argLen: 2, 24890 commutative: true, 24891 asm: mips.AXOR, 24892 reg: regInfo{ 24893 inputs: []inputInfo{ 24894 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24895 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24896 }, 24897 outputs: []outputInfo{ 24898 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24899 }, 24900 }, 24901 }, 24902 { 24903 name: "XORconst", 24904 auxType: auxInt32, 24905 argLen: 1, 24906 asm: mips.AXOR, 24907 reg: regInfo{ 24908 inputs: []inputInfo{ 24909 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24910 }, 24911 outputs: []outputInfo{ 24912 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24913 }, 24914 }, 24915 }, 24916 { 24917 name: "NOR", 24918 argLen: 2, 24919 commutative: true, 24920 asm: mips.ANOR, 24921 reg: regInfo{ 24922 inputs: []inputInfo{ 24923 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24924 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24925 }, 24926 outputs: []outputInfo{ 24927 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24928 }, 24929 }, 24930 }, 24931 { 24932 name: "NORconst", 24933 auxType: auxInt32, 24934 argLen: 1, 24935 asm: mips.ANOR, 24936 reg: regInfo{ 24937 inputs: []inputInfo{ 24938 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24939 }, 24940 outputs: []outputInfo{ 24941 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24942 }, 24943 }, 24944 }, 24945 { 24946 name: "NEG", 24947 argLen: 1, 24948 reg: regInfo{ 24949 inputs: []inputInfo{ 24950 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 24951 }, 24952 outputs: []outputInfo{ 24953 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 24954 }, 24955 }, 24956 }, 24957 { 24958 name: "NEGF", 24959 argLen: 1, 24960 asm: mips.ANEGF, 24961 reg: regInfo{ 24962 inputs: []inputInfo{ 24963 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24964 }, 24965 outputs: []outputInfo{ 24966 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24967 }, 24968 }, 24969 }, 24970 { 24971 name: "NEGD", 24972 argLen: 1, 24973 asm: mips.ANEGD, 24974 reg: regInfo{ 24975 inputs: []inputInfo{ 24976 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24977 }, 24978 outputs: []outputInfo{ 24979 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24980 }, 24981 }, 24982 }, 24983 { 24984 name: "SQRTD", 24985 argLen: 1, 24986 asm: mips.ASQRTD, 24987 reg: regInfo{ 24988 inputs: []inputInfo{ 24989 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24990 }, 24991 outputs: []outputInfo{ 24992 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 24993 }, 24994 }, 24995 }, 24996 { 24997 name: "SQRTF", 24998 argLen: 1, 24999 asm: mips.ASQRTF, 25000 reg: regInfo{ 25001 inputs: []inputInfo{ 25002 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25003 }, 25004 outputs: []outputInfo{ 25005 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25006 }, 25007 }, 25008 }, 25009 { 25010 name: "SLL", 25011 argLen: 2, 25012 asm: mips.ASLL, 25013 reg: regInfo{ 25014 inputs: []inputInfo{ 25015 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25016 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25017 }, 25018 outputs: []outputInfo{ 25019 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25020 }, 25021 }, 25022 }, 25023 { 25024 name: "SLLconst", 25025 auxType: auxInt32, 25026 argLen: 1, 25027 asm: mips.ASLL, 25028 reg: regInfo{ 25029 inputs: []inputInfo{ 25030 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25031 }, 25032 outputs: []outputInfo{ 25033 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25034 }, 25035 }, 25036 }, 25037 { 25038 name: "SRL", 25039 argLen: 2, 25040 asm: mips.ASRL, 25041 reg: regInfo{ 25042 inputs: []inputInfo{ 25043 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25044 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25045 }, 25046 outputs: []outputInfo{ 25047 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25048 }, 25049 }, 25050 }, 25051 { 25052 name: "SRLconst", 25053 auxType: auxInt32, 25054 argLen: 1, 25055 asm: mips.ASRL, 25056 reg: regInfo{ 25057 inputs: []inputInfo{ 25058 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25059 }, 25060 outputs: []outputInfo{ 25061 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25062 }, 25063 }, 25064 }, 25065 { 25066 name: "SRA", 25067 argLen: 2, 25068 asm: mips.ASRA, 25069 reg: regInfo{ 25070 inputs: []inputInfo{ 25071 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25072 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25073 }, 25074 outputs: []outputInfo{ 25075 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25076 }, 25077 }, 25078 }, 25079 { 25080 name: "SRAconst", 25081 auxType: auxInt32, 25082 argLen: 1, 25083 asm: mips.ASRA, 25084 reg: regInfo{ 25085 inputs: []inputInfo{ 25086 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25087 }, 25088 outputs: []outputInfo{ 25089 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25090 }, 25091 }, 25092 }, 25093 { 25094 name: "CLZ", 25095 argLen: 1, 25096 asm: mips.ACLZ, 25097 reg: regInfo{ 25098 inputs: []inputInfo{ 25099 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25100 }, 25101 outputs: []outputInfo{ 25102 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25103 }, 25104 }, 25105 }, 25106 { 25107 name: "SGT", 25108 argLen: 2, 25109 asm: mips.ASGT, 25110 reg: regInfo{ 25111 inputs: []inputInfo{ 25112 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25113 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25114 }, 25115 outputs: []outputInfo{ 25116 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25117 }, 25118 }, 25119 }, 25120 { 25121 name: "SGTconst", 25122 auxType: auxInt32, 25123 argLen: 1, 25124 asm: mips.ASGT, 25125 reg: regInfo{ 25126 inputs: []inputInfo{ 25127 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25128 }, 25129 outputs: []outputInfo{ 25130 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25131 }, 25132 }, 25133 }, 25134 { 25135 name: "SGTzero", 25136 argLen: 1, 25137 asm: mips.ASGT, 25138 reg: regInfo{ 25139 inputs: []inputInfo{ 25140 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25141 }, 25142 outputs: []outputInfo{ 25143 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25144 }, 25145 }, 25146 }, 25147 { 25148 name: "SGTU", 25149 argLen: 2, 25150 asm: mips.ASGTU, 25151 reg: regInfo{ 25152 inputs: []inputInfo{ 25153 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25154 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25155 }, 25156 outputs: []outputInfo{ 25157 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25158 }, 25159 }, 25160 }, 25161 { 25162 name: "SGTUconst", 25163 auxType: auxInt32, 25164 argLen: 1, 25165 asm: mips.ASGTU, 25166 reg: regInfo{ 25167 inputs: []inputInfo{ 25168 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25169 }, 25170 outputs: []outputInfo{ 25171 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25172 }, 25173 }, 25174 }, 25175 { 25176 name: "SGTUzero", 25177 argLen: 1, 25178 asm: mips.ASGTU, 25179 reg: regInfo{ 25180 inputs: []inputInfo{ 25181 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25182 }, 25183 outputs: []outputInfo{ 25184 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25185 }, 25186 }, 25187 }, 25188 { 25189 name: "CMPEQF", 25190 argLen: 2, 25191 asm: mips.ACMPEQF, 25192 reg: regInfo{ 25193 inputs: []inputInfo{ 25194 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25195 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25196 }, 25197 }, 25198 }, 25199 { 25200 name: "CMPEQD", 25201 argLen: 2, 25202 asm: mips.ACMPEQD, 25203 reg: regInfo{ 25204 inputs: []inputInfo{ 25205 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25206 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25207 }, 25208 }, 25209 }, 25210 { 25211 name: "CMPGEF", 25212 argLen: 2, 25213 asm: mips.ACMPGEF, 25214 reg: regInfo{ 25215 inputs: []inputInfo{ 25216 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25217 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25218 }, 25219 }, 25220 }, 25221 { 25222 name: "CMPGED", 25223 argLen: 2, 25224 asm: mips.ACMPGED, 25225 reg: regInfo{ 25226 inputs: []inputInfo{ 25227 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25228 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25229 }, 25230 }, 25231 }, 25232 { 25233 name: "CMPGTF", 25234 argLen: 2, 25235 asm: mips.ACMPGTF, 25236 reg: regInfo{ 25237 inputs: []inputInfo{ 25238 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25239 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25240 }, 25241 }, 25242 }, 25243 { 25244 name: "CMPGTD", 25245 argLen: 2, 25246 asm: mips.ACMPGTD, 25247 reg: regInfo{ 25248 inputs: []inputInfo{ 25249 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25250 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25251 }, 25252 }, 25253 }, 25254 { 25255 name: "MOVWconst", 25256 auxType: auxInt32, 25257 argLen: 0, 25258 rematerializeable: true, 25259 asm: mips.AMOVW, 25260 reg: regInfo{ 25261 outputs: []outputInfo{ 25262 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25263 }, 25264 }, 25265 }, 25266 { 25267 name: "MOVFconst", 25268 auxType: auxFloat32, 25269 argLen: 0, 25270 rematerializeable: true, 25271 asm: mips.AMOVF, 25272 reg: regInfo{ 25273 outputs: []outputInfo{ 25274 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25275 }, 25276 }, 25277 }, 25278 { 25279 name: "MOVDconst", 25280 auxType: auxFloat64, 25281 argLen: 0, 25282 rematerializeable: true, 25283 asm: mips.AMOVD, 25284 reg: regInfo{ 25285 outputs: []outputInfo{ 25286 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25287 }, 25288 }, 25289 }, 25290 { 25291 name: "MOVWaddr", 25292 auxType: auxSymOff, 25293 argLen: 1, 25294 rematerializeable: true, 25295 symEffect: SymAddr, 25296 asm: mips.AMOVW, 25297 reg: regInfo{ 25298 inputs: []inputInfo{ 25299 {0, 140737555464192}, // SP SB 25300 }, 25301 outputs: []outputInfo{ 25302 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25303 }, 25304 }, 25305 }, 25306 { 25307 name: "MOVBload", 25308 auxType: auxSymOff, 25309 argLen: 2, 25310 faultOnNilArg0: true, 25311 symEffect: SymRead, 25312 asm: mips.AMOVB, 25313 reg: regInfo{ 25314 inputs: []inputInfo{ 25315 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25316 }, 25317 outputs: []outputInfo{ 25318 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25319 }, 25320 }, 25321 }, 25322 { 25323 name: "MOVBUload", 25324 auxType: auxSymOff, 25325 argLen: 2, 25326 faultOnNilArg0: true, 25327 symEffect: SymRead, 25328 asm: mips.AMOVBU, 25329 reg: regInfo{ 25330 inputs: []inputInfo{ 25331 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25332 }, 25333 outputs: []outputInfo{ 25334 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25335 }, 25336 }, 25337 }, 25338 { 25339 name: "MOVHload", 25340 auxType: auxSymOff, 25341 argLen: 2, 25342 faultOnNilArg0: true, 25343 symEffect: SymRead, 25344 asm: mips.AMOVH, 25345 reg: regInfo{ 25346 inputs: []inputInfo{ 25347 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25348 }, 25349 outputs: []outputInfo{ 25350 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25351 }, 25352 }, 25353 }, 25354 { 25355 name: "MOVHUload", 25356 auxType: auxSymOff, 25357 argLen: 2, 25358 faultOnNilArg0: true, 25359 symEffect: SymRead, 25360 asm: mips.AMOVHU, 25361 reg: regInfo{ 25362 inputs: []inputInfo{ 25363 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25364 }, 25365 outputs: []outputInfo{ 25366 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25367 }, 25368 }, 25369 }, 25370 { 25371 name: "MOVWload", 25372 auxType: auxSymOff, 25373 argLen: 2, 25374 faultOnNilArg0: true, 25375 symEffect: SymRead, 25376 asm: mips.AMOVW, 25377 reg: regInfo{ 25378 inputs: []inputInfo{ 25379 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25380 }, 25381 outputs: []outputInfo{ 25382 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25383 }, 25384 }, 25385 }, 25386 { 25387 name: "MOVFload", 25388 auxType: auxSymOff, 25389 argLen: 2, 25390 faultOnNilArg0: true, 25391 symEffect: SymRead, 25392 asm: mips.AMOVF, 25393 reg: regInfo{ 25394 inputs: []inputInfo{ 25395 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25396 }, 25397 outputs: []outputInfo{ 25398 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25399 }, 25400 }, 25401 }, 25402 { 25403 name: "MOVDload", 25404 auxType: auxSymOff, 25405 argLen: 2, 25406 faultOnNilArg0: true, 25407 symEffect: SymRead, 25408 asm: mips.AMOVD, 25409 reg: regInfo{ 25410 inputs: []inputInfo{ 25411 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25412 }, 25413 outputs: []outputInfo{ 25414 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25415 }, 25416 }, 25417 }, 25418 { 25419 name: "MOVBstore", 25420 auxType: auxSymOff, 25421 argLen: 3, 25422 faultOnNilArg0: true, 25423 symEffect: SymWrite, 25424 asm: mips.AMOVB, 25425 reg: regInfo{ 25426 inputs: []inputInfo{ 25427 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25428 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25429 }, 25430 }, 25431 }, 25432 { 25433 name: "MOVHstore", 25434 auxType: auxSymOff, 25435 argLen: 3, 25436 faultOnNilArg0: true, 25437 symEffect: SymWrite, 25438 asm: mips.AMOVH, 25439 reg: regInfo{ 25440 inputs: []inputInfo{ 25441 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25442 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25443 }, 25444 }, 25445 }, 25446 { 25447 name: "MOVWstore", 25448 auxType: auxSymOff, 25449 argLen: 3, 25450 faultOnNilArg0: true, 25451 symEffect: SymWrite, 25452 asm: mips.AMOVW, 25453 reg: regInfo{ 25454 inputs: []inputInfo{ 25455 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25456 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25457 }, 25458 }, 25459 }, 25460 { 25461 name: "MOVFstore", 25462 auxType: auxSymOff, 25463 argLen: 3, 25464 faultOnNilArg0: true, 25465 symEffect: SymWrite, 25466 asm: mips.AMOVF, 25467 reg: regInfo{ 25468 inputs: []inputInfo{ 25469 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25470 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25471 }, 25472 }, 25473 }, 25474 { 25475 name: "MOVDstore", 25476 auxType: auxSymOff, 25477 argLen: 3, 25478 faultOnNilArg0: true, 25479 symEffect: SymWrite, 25480 asm: mips.AMOVD, 25481 reg: regInfo{ 25482 inputs: []inputInfo{ 25483 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25484 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25485 }, 25486 }, 25487 }, 25488 { 25489 name: "MOVBstorezero", 25490 auxType: auxSymOff, 25491 argLen: 2, 25492 faultOnNilArg0: true, 25493 symEffect: SymWrite, 25494 asm: mips.AMOVB, 25495 reg: regInfo{ 25496 inputs: []inputInfo{ 25497 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25498 }, 25499 }, 25500 }, 25501 { 25502 name: "MOVHstorezero", 25503 auxType: auxSymOff, 25504 argLen: 2, 25505 faultOnNilArg0: true, 25506 symEffect: SymWrite, 25507 asm: mips.AMOVH, 25508 reg: regInfo{ 25509 inputs: []inputInfo{ 25510 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25511 }, 25512 }, 25513 }, 25514 { 25515 name: "MOVWstorezero", 25516 auxType: auxSymOff, 25517 argLen: 2, 25518 faultOnNilArg0: true, 25519 symEffect: SymWrite, 25520 asm: mips.AMOVW, 25521 reg: regInfo{ 25522 inputs: []inputInfo{ 25523 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25524 }, 25525 }, 25526 }, 25527 { 25528 name: "MOVBreg", 25529 argLen: 1, 25530 asm: mips.AMOVB, 25531 reg: regInfo{ 25532 inputs: []inputInfo{ 25533 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25534 }, 25535 outputs: []outputInfo{ 25536 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25537 }, 25538 }, 25539 }, 25540 { 25541 name: "MOVBUreg", 25542 argLen: 1, 25543 asm: mips.AMOVBU, 25544 reg: regInfo{ 25545 inputs: []inputInfo{ 25546 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25547 }, 25548 outputs: []outputInfo{ 25549 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25550 }, 25551 }, 25552 }, 25553 { 25554 name: "MOVHreg", 25555 argLen: 1, 25556 asm: mips.AMOVH, 25557 reg: regInfo{ 25558 inputs: []inputInfo{ 25559 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25560 }, 25561 outputs: []outputInfo{ 25562 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25563 }, 25564 }, 25565 }, 25566 { 25567 name: "MOVHUreg", 25568 argLen: 1, 25569 asm: mips.AMOVHU, 25570 reg: regInfo{ 25571 inputs: []inputInfo{ 25572 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25573 }, 25574 outputs: []outputInfo{ 25575 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25576 }, 25577 }, 25578 }, 25579 { 25580 name: "MOVWreg", 25581 argLen: 1, 25582 asm: mips.AMOVW, 25583 reg: regInfo{ 25584 inputs: []inputInfo{ 25585 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25586 }, 25587 outputs: []outputInfo{ 25588 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25589 }, 25590 }, 25591 }, 25592 { 25593 name: "MOVWnop", 25594 argLen: 1, 25595 resultInArg0: true, 25596 reg: regInfo{ 25597 inputs: []inputInfo{ 25598 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25599 }, 25600 outputs: []outputInfo{ 25601 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25602 }, 25603 }, 25604 }, 25605 { 25606 name: "CMOVZ", 25607 argLen: 3, 25608 resultInArg0: true, 25609 asm: mips.ACMOVZ, 25610 reg: regInfo{ 25611 inputs: []inputInfo{ 25612 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25613 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25614 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25615 }, 25616 outputs: []outputInfo{ 25617 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25618 }, 25619 }, 25620 }, 25621 { 25622 name: "CMOVZzero", 25623 argLen: 2, 25624 resultInArg0: true, 25625 asm: mips.ACMOVZ, 25626 reg: regInfo{ 25627 inputs: []inputInfo{ 25628 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25629 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25630 }, 25631 outputs: []outputInfo{ 25632 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25633 }, 25634 }, 25635 }, 25636 { 25637 name: "MOVWF", 25638 argLen: 1, 25639 asm: mips.AMOVWF, 25640 reg: regInfo{ 25641 inputs: []inputInfo{ 25642 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25643 }, 25644 outputs: []outputInfo{ 25645 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25646 }, 25647 }, 25648 }, 25649 { 25650 name: "MOVWD", 25651 argLen: 1, 25652 asm: mips.AMOVWD, 25653 reg: regInfo{ 25654 inputs: []inputInfo{ 25655 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25656 }, 25657 outputs: []outputInfo{ 25658 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25659 }, 25660 }, 25661 }, 25662 { 25663 name: "TRUNCFW", 25664 argLen: 1, 25665 asm: mips.ATRUNCFW, 25666 reg: regInfo{ 25667 inputs: []inputInfo{ 25668 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25669 }, 25670 outputs: []outputInfo{ 25671 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25672 }, 25673 }, 25674 }, 25675 { 25676 name: "TRUNCDW", 25677 argLen: 1, 25678 asm: mips.ATRUNCDW, 25679 reg: regInfo{ 25680 inputs: []inputInfo{ 25681 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25682 }, 25683 outputs: []outputInfo{ 25684 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25685 }, 25686 }, 25687 }, 25688 { 25689 name: "MOVFD", 25690 argLen: 1, 25691 asm: mips.AMOVFD, 25692 reg: regInfo{ 25693 inputs: []inputInfo{ 25694 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25695 }, 25696 outputs: []outputInfo{ 25697 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25698 }, 25699 }, 25700 }, 25701 { 25702 name: "MOVDF", 25703 argLen: 1, 25704 asm: mips.AMOVDF, 25705 reg: regInfo{ 25706 inputs: []inputInfo{ 25707 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25708 }, 25709 outputs: []outputInfo{ 25710 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 25711 }, 25712 }, 25713 }, 25714 { 25715 name: "CALLstatic", 25716 auxType: auxCallOff, 25717 argLen: 1, 25718 clobberFlags: true, 25719 call: true, 25720 reg: regInfo{ 25721 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 25722 }, 25723 }, 25724 { 25725 name: "CALLtail", 25726 auxType: auxCallOff, 25727 argLen: 1, 25728 clobberFlags: true, 25729 call: true, 25730 tailCall: true, 25731 reg: regInfo{ 25732 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 25733 }, 25734 }, 25735 { 25736 name: "CALLclosure", 25737 auxType: auxCallOff, 25738 argLen: 3, 25739 clobberFlags: true, 25740 call: true, 25741 reg: regInfo{ 25742 inputs: []inputInfo{ 25743 {1, 4194304}, // R22 25744 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 25745 }, 25746 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 25747 }, 25748 }, 25749 { 25750 name: "CALLinter", 25751 auxType: auxCallOff, 25752 argLen: 2, 25753 clobberFlags: true, 25754 call: true, 25755 reg: regInfo{ 25756 inputs: []inputInfo{ 25757 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25758 }, 25759 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 25760 }, 25761 }, 25762 { 25763 name: "LoweredAtomicLoad8", 25764 argLen: 2, 25765 faultOnNilArg0: true, 25766 reg: regInfo{ 25767 inputs: []inputInfo{ 25768 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25769 }, 25770 outputs: []outputInfo{ 25771 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25772 }, 25773 }, 25774 }, 25775 { 25776 name: "LoweredAtomicLoad32", 25777 argLen: 2, 25778 faultOnNilArg0: true, 25779 reg: regInfo{ 25780 inputs: []inputInfo{ 25781 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25782 }, 25783 outputs: []outputInfo{ 25784 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25785 }, 25786 }, 25787 }, 25788 { 25789 name: "LoweredAtomicStore8", 25790 argLen: 3, 25791 faultOnNilArg0: true, 25792 hasSideEffects: true, 25793 reg: regInfo{ 25794 inputs: []inputInfo{ 25795 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25796 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25797 }, 25798 }, 25799 }, 25800 { 25801 name: "LoweredAtomicStore32", 25802 argLen: 3, 25803 faultOnNilArg0: true, 25804 hasSideEffects: true, 25805 reg: regInfo{ 25806 inputs: []inputInfo{ 25807 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25808 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25809 }, 25810 }, 25811 }, 25812 { 25813 name: "LoweredAtomicStorezero", 25814 argLen: 2, 25815 faultOnNilArg0: true, 25816 hasSideEffects: true, 25817 reg: regInfo{ 25818 inputs: []inputInfo{ 25819 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25820 }, 25821 }, 25822 }, 25823 { 25824 name: "LoweredAtomicExchange", 25825 argLen: 3, 25826 resultNotInArgs: true, 25827 faultOnNilArg0: true, 25828 hasSideEffects: true, 25829 unsafePoint: true, 25830 reg: regInfo{ 25831 inputs: []inputInfo{ 25832 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25833 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25834 }, 25835 outputs: []outputInfo{ 25836 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25837 }, 25838 }, 25839 }, 25840 { 25841 name: "LoweredAtomicAdd", 25842 argLen: 3, 25843 resultNotInArgs: true, 25844 faultOnNilArg0: true, 25845 hasSideEffects: true, 25846 unsafePoint: true, 25847 reg: regInfo{ 25848 inputs: []inputInfo{ 25849 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25850 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25851 }, 25852 outputs: []outputInfo{ 25853 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25854 }, 25855 }, 25856 }, 25857 { 25858 name: "LoweredAtomicAddconst", 25859 auxType: auxInt32, 25860 argLen: 2, 25861 resultNotInArgs: true, 25862 faultOnNilArg0: true, 25863 hasSideEffects: true, 25864 unsafePoint: true, 25865 reg: regInfo{ 25866 inputs: []inputInfo{ 25867 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25868 }, 25869 outputs: []outputInfo{ 25870 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25871 }, 25872 }, 25873 }, 25874 { 25875 name: "LoweredAtomicCas", 25876 argLen: 4, 25877 resultNotInArgs: true, 25878 faultOnNilArg0: true, 25879 hasSideEffects: true, 25880 unsafePoint: true, 25881 reg: regInfo{ 25882 inputs: []inputInfo{ 25883 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25884 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25885 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25886 }, 25887 outputs: []outputInfo{ 25888 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25889 }, 25890 }, 25891 }, 25892 { 25893 name: "LoweredAtomicAnd", 25894 argLen: 3, 25895 faultOnNilArg0: true, 25896 hasSideEffects: true, 25897 unsafePoint: true, 25898 asm: mips.AAND, 25899 reg: regInfo{ 25900 inputs: []inputInfo{ 25901 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25902 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25903 }, 25904 }, 25905 }, 25906 { 25907 name: "LoweredAtomicOr", 25908 argLen: 3, 25909 faultOnNilArg0: true, 25910 hasSideEffects: true, 25911 unsafePoint: true, 25912 asm: mips.AOR, 25913 reg: regInfo{ 25914 inputs: []inputInfo{ 25915 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25916 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 25917 }, 25918 }, 25919 }, 25920 { 25921 name: "LoweredZero", 25922 auxType: auxInt32, 25923 argLen: 3, 25924 faultOnNilArg0: true, 25925 reg: regInfo{ 25926 inputs: []inputInfo{ 25927 {0, 2}, // R1 25928 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25929 }, 25930 clobbers: 2, // R1 25931 }, 25932 }, 25933 { 25934 name: "LoweredMove", 25935 auxType: auxInt32, 25936 argLen: 4, 25937 faultOnNilArg0: true, 25938 faultOnNilArg1: true, 25939 reg: regInfo{ 25940 inputs: []inputInfo{ 25941 {0, 4}, // R2 25942 {1, 2}, // R1 25943 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25944 }, 25945 clobbers: 6, // R1 R2 25946 }, 25947 }, 25948 { 25949 name: "LoweredNilCheck", 25950 argLen: 2, 25951 nilCheck: true, 25952 faultOnNilArg0: true, 25953 reg: regInfo{ 25954 inputs: []inputInfo{ 25955 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 25956 }, 25957 }, 25958 }, 25959 { 25960 name: "FPFlagTrue", 25961 argLen: 1, 25962 reg: regInfo{ 25963 outputs: []outputInfo{ 25964 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25965 }, 25966 }, 25967 }, 25968 { 25969 name: "FPFlagFalse", 25970 argLen: 1, 25971 reg: regInfo{ 25972 outputs: []outputInfo{ 25973 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25974 }, 25975 }, 25976 }, 25977 { 25978 name: "LoweredGetClosurePtr", 25979 argLen: 0, 25980 zeroWidth: true, 25981 reg: regInfo{ 25982 outputs: []outputInfo{ 25983 {0, 4194304}, // R22 25984 }, 25985 }, 25986 }, 25987 { 25988 name: "LoweredGetCallerSP", 25989 argLen: 0, 25990 rematerializeable: true, 25991 reg: regInfo{ 25992 outputs: []outputInfo{ 25993 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 25994 }, 25995 }, 25996 }, 25997 { 25998 name: "LoweredGetCallerPC", 25999 argLen: 0, 26000 rematerializeable: true, 26001 reg: regInfo{ 26002 outputs: []outputInfo{ 26003 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 26004 }, 26005 }, 26006 }, 26007 { 26008 name: "LoweredWB", 26009 auxType: auxSym, 26010 argLen: 3, 26011 clobberFlags: true, 26012 symEffect: SymNone, 26013 reg: regInfo{ 26014 inputs: []inputInfo{ 26015 {0, 1048576}, // R20 26016 {1, 2097152}, // R21 26017 }, 26018 clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 26019 }, 26020 }, 26021 { 26022 name: "LoweredPanicBoundsA", 26023 auxType: auxInt64, 26024 argLen: 3, 26025 call: true, 26026 reg: regInfo{ 26027 inputs: []inputInfo{ 26028 {0, 8}, // R3 26029 {1, 16}, // R4 26030 }, 26031 }, 26032 }, 26033 { 26034 name: "LoweredPanicBoundsB", 26035 auxType: auxInt64, 26036 argLen: 3, 26037 call: true, 26038 reg: regInfo{ 26039 inputs: []inputInfo{ 26040 {0, 4}, // R2 26041 {1, 8}, // R3 26042 }, 26043 }, 26044 }, 26045 { 26046 name: "LoweredPanicBoundsC", 26047 auxType: auxInt64, 26048 argLen: 3, 26049 call: true, 26050 reg: regInfo{ 26051 inputs: []inputInfo{ 26052 {0, 2}, // R1 26053 {1, 4}, // R2 26054 }, 26055 }, 26056 }, 26057 { 26058 name: "LoweredPanicExtendA", 26059 auxType: auxInt64, 26060 argLen: 4, 26061 call: true, 26062 reg: regInfo{ 26063 inputs: []inputInfo{ 26064 {0, 32}, // R5 26065 {1, 8}, // R3 26066 {2, 16}, // R4 26067 }, 26068 }, 26069 }, 26070 { 26071 name: "LoweredPanicExtendB", 26072 auxType: auxInt64, 26073 argLen: 4, 26074 call: true, 26075 reg: regInfo{ 26076 inputs: []inputInfo{ 26077 {0, 32}, // R5 26078 {1, 4}, // R2 26079 {2, 8}, // R3 26080 }, 26081 }, 26082 }, 26083 { 26084 name: "LoweredPanicExtendC", 26085 auxType: auxInt64, 26086 argLen: 4, 26087 call: true, 26088 reg: regInfo{ 26089 inputs: []inputInfo{ 26090 {0, 32}, // R5 26091 {1, 2}, // R1 26092 {2, 4}, // R2 26093 }, 26094 }, 26095 }, 26096 26097 { 26098 name: "ADDV", 26099 argLen: 2, 26100 commutative: true, 26101 asm: mips.AADDVU, 26102 reg: regInfo{ 26103 inputs: []inputInfo{ 26104 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26105 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26106 }, 26107 outputs: []outputInfo{ 26108 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26109 }, 26110 }, 26111 }, 26112 { 26113 name: "ADDVconst", 26114 auxType: auxInt64, 26115 argLen: 1, 26116 asm: mips.AADDVU, 26117 reg: regInfo{ 26118 inputs: []inputInfo{ 26119 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 26120 }, 26121 outputs: []outputInfo{ 26122 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26123 }, 26124 }, 26125 }, 26126 { 26127 name: "SUBV", 26128 argLen: 2, 26129 asm: mips.ASUBVU, 26130 reg: regInfo{ 26131 inputs: []inputInfo{ 26132 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26133 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26134 }, 26135 outputs: []outputInfo{ 26136 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26137 }, 26138 }, 26139 }, 26140 { 26141 name: "SUBVconst", 26142 auxType: auxInt64, 26143 argLen: 1, 26144 asm: mips.ASUBVU, 26145 reg: regInfo{ 26146 inputs: []inputInfo{ 26147 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26148 }, 26149 outputs: []outputInfo{ 26150 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26151 }, 26152 }, 26153 }, 26154 { 26155 name: "MULV", 26156 argLen: 2, 26157 commutative: true, 26158 asm: mips.AMULV, 26159 reg: regInfo{ 26160 inputs: []inputInfo{ 26161 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26162 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26163 }, 26164 outputs: []outputInfo{ 26165 {0, 1152921504606846976}, // HI 26166 {1, 2305843009213693952}, // LO 26167 }, 26168 }, 26169 }, 26170 { 26171 name: "MULVU", 26172 argLen: 2, 26173 commutative: true, 26174 asm: mips.AMULVU, 26175 reg: regInfo{ 26176 inputs: []inputInfo{ 26177 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26178 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26179 }, 26180 outputs: []outputInfo{ 26181 {0, 1152921504606846976}, // HI 26182 {1, 2305843009213693952}, // LO 26183 }, 26184 }, 26185 }, 26186 { 26187 name: "DIVV", 26188 argLen: 2, 26189 asm: mips.ADIVV, 26190 reg: regInfo{ 26191 inputs: []inputInfo{ 26192 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26193 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26194 }, 26195 outputs: []outputInfo{ 26196 {0, 1152921504606846976}, // HI 26197 {1, 2305843009213693952}, // LO 26198 }, 26199 }, 26200 }, 26201 { 26202 name: "DIVVU", 26203 argLen: 2, 26204 asm: mips.ADIVVU, 26205 reg: regInfo{ 26206 inputs: []inputInfo{ 26207 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26208 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26209 }, 26210 outputs: []outputInfo{ 26211 {0, 1152921504606846976}, // HI 26212 {1, 2305843009213693952}, // LO 26213 }, 26214 }, 26215 }, 26216 { 26217 name: "ADDF", 26218 argLen: 2, 26219 commutative: true, 26220 asm: mips.AADDF, 26221 reg: regInfo{ 26222 inputs: []inputInfo{ 26223 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26224 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26225 }, 26226 outputs: []outputInfo{ 26227 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26228 }, 26229 }, 26230 }, 26231 { 26232 name: "ADDD", 26233 argLen: 2, 26234 commutative: true, 26235 asm: mips.AADDD, 26236 reg: regInfo{ 26237 inputs: []inputInfo{ 26238 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26239 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26240 }, 26241 outputs: []outputInfo{ 26242 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26243 }, 26244 }, 26245 }, 26246 { 26247 name: "SUBF", 26248 argLen: 2, 26249 asm: mips.ASUBF, 26250 reg: regInfo{ 26251 inputs: []inputInfo{ 26252 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26253 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26254 }, 26255 outputs: []outputInfo{ 26256 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26257 }, 26258 }, 26259 }, 26260 { 26261 name: "SUBD", 26262 argLen: 2, 26263 asm: mips.ASUBD, 26264 reg: regInfo{ 26265 inputs: []inputInfo{ 26266 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26267 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26268 }, 26269 outputs: []outputInfo{ 26270 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26271 }, 26272 }, 26273 }, 26274 { 26275 name: "MULF", 26276 argLen: 2, 26277 commutative: true, 26278 asm: mips.AMULF, 26279 reg: regInfo{ 26280 inputs: []inputInfo{ 26281 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26282 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26283 }, 26284 outputs: []outputInfo{ 26285 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26286 }, 26287 }, 26288 }, 26289 { 26290 name: "MULD", 26291 argLen: 2, 26292 commutative: true, 26293 asm: mips.AMULD, 26294 reg: regInfo{ 26295 inputs: []inputInfo{ 26296 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26297 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26298 }, 26299 outputs: []outputInfo{ 26300 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26301 }, 26302 }, 26303 }, 26304 { 26305 name: "DIVF", 26306 argLen: 2, 26307 asm: mips.ADIVF, 26308 reg: regInfo{ 26309 inputs: []inputInfo{ 26310 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26311 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26312 }, 26313 outputs: []outputInfo{ 26314 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26315 }, 26316 }, 26317 }, 26318 { 26319 name: "DIVD", 26320 argLen: 2, 26321 asm: mips.ADIVD, 26322 reg: regInfo{ 26323 inputs: []inputInfo{ 26324 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26325 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26326 }, 26327 outputs: []outputInfo{ 26328 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26329 }, 26330 }, 26331 }, 26332 { 26333 name: "AND", 26334 argLen: 2, 26335 commutative: true, 26336 asm: mips.AAND, 26337 reg: regInfo{ 26338 inputs: []inputInfo{ 26339 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26340 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26341 }, 26342 outputs: []outputInfo{ 26343 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26344 }, 26345 }, 26346 }, 26347 { 26348 name: "ANDconst", 26349 auxType: auxInt64, 26350 argLen: 1, 26351 asm: mips.AAND, 26352 reg: regInfo{ 26353 inputs: []inputInfo{ 26354 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26355 }, 26356 outputs: []outputInfo{ 26357 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26358 }, 26359 }, 26360 }, 26361 { 26362 name: "OR", 26363 argLen: 2, 26364 commutative: true, 26365 asm: mips.AOR, 26366 reg: regInfo{ 26367 inputs: []inputInfo{ 26368 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26369 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26370 }, 26371 outputs: []outputInfo{ 26372 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26373 }, 26374 }, 26375 }, 26376 { 26377 name: "ORconst", 26378 auxType: auxInt64, 26379 argLen: 1, 26380 asm: mips.AOR, 26381 reg: regInfo{ 26382 inputs: []inputInfo{ 26383 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26384 }, 26385 outputs: []outputInfo{ 26386 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26387 }, 26388 }, 26389 }, 26390 { 26391 name: "XOR", 26392 argLen: 2, 26393 commutative: true, 26394 asm: mips.AXOR, 26395 reg: regInfo{ 26396 inputs: []inputInfo{ 26397 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26398 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26399 }, 26400 outputs: []outputInfo{ 26401 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26402 }, 26403 }, 26404 }, 26405 { 26406 name: "XORconst", 26407 auxType: auxInt64, 26408 argLen: 1, 26409 asm: mips.AXOR, 26410 reg: regInfo{ 26411 inputs: []inputInfo{ 26412 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26413 }, 26414 outputs: []outputInfo{ 26415 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26416 }, 26417 }, 26418 }, 26419 { 26420 name: "NOR", 26421 argLen: 2, 26422 commutative: true, 26423 asm: mips.ANOR, 26424 reg: regInfo{ 26425 inputs: []inputInfo{ 26426 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26427 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26428 }, 26429 outputs: []outputInfo{ 26430 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26431 }, 26432 }, 26433 }, 26434 { 26435 name: "NORconst", 26436 auxType: auxInt64, 26437 argLen: 1, 26438 asm: mips.ANOR, 26439 reg: regInfo{ 26440 inputs: []inputInfo{ 26441 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26442 }, 26443 outputs: []outputInfo{ 26444 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26445 }, 26446 }, 26447 }, 26448 { 26449 name: "NEGV", 26450 argLen: 1, 26451 reg: regInfo{ 26452 inputs: []inputInfo{ 26453 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26454 }, 26455 outputs: []outputInfo{ 26456 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26457 }, 26458 }, 26459 }, 26460 { 26461 name: "NEGF", 26462 argLen: 1, 26463 asm: mips.ANEGF, 26464 reg: regInfo{ 26465 inputs: []inputInfo{ 26466 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26467 }, 26468 outputs: []outputInfo{ 26469 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26470 }, 26471 }, 26472 }, 26473 { 26474 name: "NEGD", 26475 argLen: 1, 26476 asm: mips.ANEGD, 26477 reg: regInfo{ 26478 inputs: []inputInfo{ 26479 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26480 }, 26481 outputs: []outputInfo{ 26482 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26483 }, 26484 }, 26485 }, 26486 { 26487 name: "SQRTD", 26488 argLen: 1, 26489 asm: mips.ASQRTD, 26490 reg: regInfo{ 26491 inputs: []inputInfo{ 26492 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26493 }, 26494 outputs: []outputInfo{ 26495 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26496 }, 26497 }, 26498 }, 26499 { 26500 name: "SQRTF", 26501 argLen: 1, 26502 asm: mips.ASQRTF, 26503 reg: regInfo{ 26504 inputs: []inputInfo{ 26505 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26506 }, 26507 outputs: []outputInfo{ 26508 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26509 }, 26510 }, 26511 }, 26512 { 26513 name: "SLLV", 26514 argLen: 2, 26515 asm: mips.ASLLV, 26516 reg: regInfo{ 26517 inputs: []inputInfo{ 26518 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26519 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26520 }, 26521 outputs: []outputInfo{ 26522 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26523 }, 26524 }, 26525 }, 26526 { 26527 name: "SLLVconst", 26528 auxType: auxInt64, 26529 argLen: 1, 26530 asm: mips.ASLLV, 26531 reg: regInfo{ 26532 inputs: []inputInfo{ 26533 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26534 }, 26535 outputs: []outputInfo{ 26536 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26537 }, 26538 }, 26539 }, 26540 { 26541 name: "SRLV", 26542 argLen: 2, 26543 asm: mips.ASRLV, 26544 reg: regInfo{ 26545 inputs: []inputInfo{ 26546 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26547 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26548 }, 26549 outputs: []outputInfo{ 26550 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26551 }, 26552 }, 26553 }, 26554 { 26555 name: "SRLVconst", 26556 auxType: auxInt64, 26557 argLen: 1, 26558 asm: mips.ASRLV, 26559 reg: regInfo{ 26560 inputs: []inputInfo{ 26561 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26562 }, 26563 outputs: []outputInfo{ 26564 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26565 }, 26566 }, 26567 }, 26568 { 26569 name: "SRAV", 26570 argLen: 2, 26571 asm: mips.ASRAV, 26572 reg: regInfo{ 26573 inputs: []inputInfo{ 26574 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26575 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26576 }, 26577 outputs: []outputInfo{ 26578 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26579 }, 26580 }, 26581 }, 26582 { 26583 name: "SRAVconst", 26584 auxType: auxInt64, 26585 argLen: 1, 26586 asm: mips.ASRAV, 26587 reg: regInfo{ 26588 inputs: []inputInfo{ 26589 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26590 }, 26591 outputs: []outputInfo{ 26592 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26593 }, 26594 }, 26595 }, 26596 { 26597 name: "SGT", 26598 argLen: 2, 26599 asm: mips.ASGT, 26600 reg: regInfo{ 26601 inputs: []inputInfo{ 26602 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26603 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26604 }, 26605 outputs: []outputInfo{ 26606 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26607 }, 26608 }, 26609 }, 26610 { 26611 name: "SGTconst", 26612 auxType: auxInt64, 26613 argLen: 1, 26614 asm: mips.ASGT, 26615 reg: regInfo{ 26616 inputs: []inputInfo{ 26617 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26618 }, 26619 outputs: []outputInfo{ 26620 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26621 }, 26622 }, 26623 }, 26624 { 26625 name: "SGTU", 26626 argLen: 2, 26627 asm: mips.ASGTU, 26628 reg: regInfo{ 26629 inputs: []inputInfo{ 26630 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26631 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26632 }, 26633 outputs: []outputInfo{ 26634 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26635 }, 26636 }, 26637 }, 26638 { 26639 name: "SGTUconst", 26640 auxType: auxInt64, 26641 argLen: 1, 26642 asm: mips.ASGTU, 26643 reg: regInfo{ 26644 inputs: []inputInfo{ 26645 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26646 }, 26647 outputs: []outputInfo{ 26648 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26649 }, 26650 }, 26651 }, 26652 { 26653 name: "CMPEQF", 26654 argLen: 2, 26655 asm: mips.ACMPEQF, 26656 reg: regInfo{ 26657 inputs: []inputInfo{ 26658 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26659 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26660 }, 26661 }, 26662 }, 26663 { 26664 name: "CMPEQD", 26665 argLen: 2, 26666 asm: mips.ACMPEQD, 26667 reg: regInfo{ 26668 inputs: []inputInfo{ 26669 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26670 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26671 }, 26672 }, 26673 }, 26674 { 26675 name: "CMPGEF", 26676 argLen: 2, 26677 asm: mips.ACMPGEF, 26678 reg: regInfo{ 26679 inputs: []inputInfo{ 26680 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26681 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26682 }, 26683 }, 26684 }, 26685 { 26686 name: "CMPGED", 26687 argLen: 2, 26688 asm: mips.ACMPGED, 26689 reg: regInfo{ 26690 inputs: []inputInfo{ 26691 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26692 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26693 }, 26694 }, 26695 }, 26696 { 26697 name: "CMPGTF", 26698 argLen: 2, 26699 asm: mips.ACMPGTF, 26700 reg: regInfo{ 26701 inputs: []inputInfo{ 26702 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26703 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26704 }, 26705 }, 26706 }, 26707 { 26708 name: "CMPGTD", 26709 argLen: 2, 26710 asm: mips.ACMPGTD, 26711 reg: regInfo{ 26712 inputs: []inputInfo{ 26713 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26714 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26715 }, 26716 }, 26717 }, 26718 { 26719 name: "MOVVconst", 26720 auxType: auxInt64, 26721 argLen: 0, 26722 rematerializeable: true, 26723 asm: mips.AMOVV, 26724 reg: regInfo{ 26725 outputs: []outputInfo{ 26726 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26727 }, 26728 }, 26729 }, 26730 { 26731 name: "MOVFconst", 26732 auxType: auxFloat64, 26733 argLen: 0, 26734 rematerializeable: true, 26735 asm: mips.AMOVF, 26736 reg: regInfo{ 26737 outputs: []outputInfo{ 26738 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26739 }, 26740 }, 26741 }, 26742 { 26743 name: "MOVDconst", 26744 auxType: auxFloat64, 26745 argLen: 0, 26746 rematerializeable: true, 26747 asm: mips.AMOVD, 26748 reg: regInfo{ 26749 outputs: []outputInfo{ 26750 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26751 }, 26752 }, 26753 }, 26754 { 26755 name: "MOVVaddr", 26756 auxType: auxSymOff, 26757 argLen: 1, 26758 rematerializeable: true, 26759 symEffect: SymAddr, 26760 asm: mips.AMOVV, 26761 reg: regInfo{ 26762 inputs: []inputInfo{ 26763 {0, 4611686018460942336}, // SP SB 26764 }, 26765 outputs: []outputInfo{ 26766 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26767 }, 26768 }, 26769 }, 26770 { 26771 name: "MOVBload", 26772 auxType: auxSymOff, 26773 argLen: 2, 26774 faultOnNilArg0: true, 26775 symEffect: SymRead, 26776 asm: mips.AMOVB, 26777 reg: regInfo{ 26778 inputs: []inputInfo{ 26779 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26780 }, 26781 outputs: []outputInfo{ 26782 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26783 }, 26784 }, 26785 }, 26786 { 26787 name: "MOVBUload", 26788 auxType: auxSymOff, 26789 argLen: 2, 26790 faultOnNilArg0: true, 26791 symEffect: SymRead, 26792 asm: mips.AMOVBU, 26793 reg: regInfo{ 26794 inputs: []inputInfo{ 26795 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26796 }, 26797 outputs: []outputInfo{ 26798 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26799 }, 26800 }, 26801 }, 26802 { 26803 name: "MOVHload", 26804 auxType: auxSymOff, 26805 argLen: 2, 26806 faultOnNilArg0: true, 26807 symEffect: SymRead, 26808 asm: mips.AMOVH, 26809 reg: regInfo{ 26810 inputs: []inputInfo{ 26811 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26812 }, 26813 outputs: []outputInfo{ 26814 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26815 }, 26816 }, 26817 }, 26818 { 26819 name: "MOVHUload", 26820 auxType: auxSymOff, 26821 argLen: 2, 26822 faultOnNilArg0: true, 26823 symEffect: SymRead, 26824 asm: mips.AMOVHU, 26825 reg: regInfo{ 26826 inputs: []inputInfo{ 26827 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26828 }, 26829 outputs: []outputInfo{ 26830 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26831 }, 26832 }, 26833 }, 26834 { 26835 name: "MOVWload", 26836 auxType: auxSymOff, 26837 argLen: 2, 26838 faultOnNilArg0: true, 26839 symEffect: SymRead, 26840 asm: mips.AMOVW, 26841 reg: regInfo{ 26842 inputs: []inputInfo{ 26843 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26844 }, 26845 outputs: []outputInfo{ 26846 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26847 }, 26848 }, 26849 }, 26850 { 26851 name: "MOVWUload", 26852 auxType: auxSymOff, 26853 argLen: 2, 26854 faultOnNilArg0: true, 26855 symEffect: SymRead, 26856 asm: mips.AMOVWU, 26857 reg: regInfo{ 26858 inputs: []inputInfo{ 26859 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26860 }, 26861 outputs: []outputInfo{ 26862 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26863 }, 26864 }, 26865 }, 26866 { 26867 name: "MOVVload", 26868 auxType: auxSymOff, 26869 argLen: 2, 26870 faultOnNilArg0: true, 26871 symEffect: SymRead, 26872 asm: mips.AMOVV, 26873 reg: regInfo{ 26874 inputs: []inputInfo{ 26875 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26876 }, 26877 outputs: []outputInfo{ 26878 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 26879 }, 26880 }, 26881 }, 26882 { 26883 name: "MOVFload", 26884 auxType: auxSymOff, 26885 argLen: 2, 26886 faultOnNilArg0: true, 26887 symEffect: SymRead, 26888 asm: mips.AMOVF, 26889 reg: regInfo{ 26890 inputs: []inputInfo{ 26891 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26892 }, 26893 outputs: []outputInfo{ 26894 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26895 }, 26896 }, 26897 }, 26898 { 26899 name: "MOVDload", 26900 auxType: auxSymOff, 26901 argLen: 2, 26902 faultOnNilArg0: true, 26903 symEffect: SymRead, 26904 asm: mips.AMOVD, 26905 reg: regInfo{ 26906 inputs: []inputInfo{ 26907 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26908 }, 26909 outputs: []outputInfo{ 26910 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26911 }, 26912 }, 26913 }, 26914 { 26915 name: "MOVBstore", 26916 auxType: auxSymOff, 26917 argLen: 3, 26918 faultOnNilArg0: true, 26919 symEffect: SymWrite, 26920 asm: mips.AMOVB, 26921 reg: regInfo{ 26922 inputs: []inputInfo{ 26923 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26924 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26925 }, 26926 }, 26927 }, 26928 { 26929 name: "MOVHstore", 26930 auxType: auxSymOff, 26931 argLen: 3, 26932 faultOnNilArg0: true, 26933 symEffect: SymWrite, 26934 asm: mips.AMOVH, 26935 reg: regInfo{ 26936 inputs: []inputInfo{ 26937 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26938 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26939 }, 26940 }, 26941 }, 26942 { 26943 name: "MOVWstore", 26944 auxType: auxSymOff, 26945 argLen: 3, 26946 faultOnNilArg0: true, 26947 symEffect: SymWrite, 26948 asm: mips.AMOVW, 26949 reg: regInfo{ 26950 inputs: []inputInfo{ 26951 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26952 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26953 }, 26954 }, 26955 }, 26956 { 26957 name: "MOVVstore", 26958 auxType: auxSymOff, 26959 argLen: 3, 26960 faultOnNilArg0: true, 26961 symEffect: SymWrite, 26962 asm: mips.AMOVV, 26963 reg: regInfo{ 26964 inputs: []inputInfo{ 26965 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 26966 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26967 }, 26968 }, 26969 }, 26970 { 26971 name: "MOVFstore", 26972 auxType: auxSymOff, 26973 argLen: 3, 26974 faultOnNilArg0: true, 26975 symEffect: SymWrite, 26976 asm: mips.AMOVF, 26977 reg: regInfo{ 26978 inputs: []inputInfo{ 26979 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26980 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26981 }, 26982 }, 26983 }, 26984 { 26985 name: "MOVDstore", 26986 auxType: auxSymOff, 26987 argLen: 3, 26988 faultOnNilArg0: true, 26989 symEffect: SymWrite, 26990 asm: mips.AMOVD, 26991 reg: regInfo{ 26992 inputs: []inputInfo{ 26993 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 26994 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 26995 }, 26996 }, 26997 }, 26998 { 26999 name: "MOVBstorezero", 27000 auxType: auxSymOff, 27001 argLen: 2, 27002 faultOnNilArg0: true, 27003 symEffect: SymWrite, 27004 asm: mips.AMOVB, 27005 reg: regInfo{ 27006 inputs: []inputInfo{ 27007 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27008 }, 27009 }, 27010 }, 27011 { 27012 name: "MOVHstorezero", 27013 auxType: auxSymOff, 27014 argLen: 2, 27015 faultOnNilArg0: true, 27016 symEffect: SymWrite, 27017 asm: mips.AMOVH, 27018 reg: regInfo{ 27019 inputs: []inputInfo{ 27020 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27021 }, 27022 }, 27023 }, 27024 { 27025 name: "MOVWstorezero", 27026 auxType: auxSymOff, 27027 argLen: 2, 27028 faultOnNilArg0: true, 27029 symEffect: SymWrite, 27030 asm: mips.AMOVW, 27031 reg: regInfo{ 27032 inputs: []inputInfo{ 27033 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27034 }, 27035 }, 27036 }, 27037 { 27038 name: "MOVVstorezero", 27039 auxType: auxSymOff, 27040 argLen: 2, 27041 faultOnNilArg0: true, 27042 symEffect: SymWrite, 27043 asm: mips.AMOVV, 27044 reg: regInfo{ 27045 inputs: []inputInfo{ 27046 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27047 }, 27048 }, 27049 }, 27050 { 27051 name: "MOVBreg", 27052 argLen: 1, 27053 asm: mips.AMOVB, 27054 reg: regInfo{ 27055 inputs: []inputInfo{ 27056 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27057 }, 27058 outputs: []outputInfo{ 27059 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27060 }, 27061 }, 27062 }, 27063 { 27064 name: "MOVBUreg", 27065 argLen: 1, 27066 asm: mips.AMOVBU, 27067 reg: regInfo{ 27068 inputs: []inputInfo{ 27069 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27070 }, 27071 outputs: []outputInfo{ 27072 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27073 }, 27074 }, 27075 }, 27076 { 27077 name: "MOVHreg", 27078 argLen: 1, 27079 asm: mips.AMOVH, 27080 reg: regInfo{ 27081 inputs: []inputInfo{ 27082 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27083 }, 27084 outputs: []outputInfo{ 27085 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27086 }, 27087 }, 27088 }, 27089 { 27090 name: "MOVHUreg", 27091 argLen: 1, 27092 asm: mips.AMOVHU, 27093 reg: regInfo{ 27094 inputs: []inputInfo{ 27095 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27096 }, 27097 outputs: []outputInfo{ 27098 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27099 }, 27100 }, 27101 }, 27102 { 27103 name: "MOVWreg", 27104 argLen: 1, 27105 asm: mips.AMOVW, 27106 reg: regInfo{ 27107 inputs: []inputInfo{ 27108 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27109 }, 27110 outputs: []outputInfo{ 27111 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27112 }, 27113 }, 27114 }, 27115 { 27116 name: "MOVWUreg", 27117 argLen: 1, 27118 asm: mips.AMOVWU, 27119 reg: regInfo{ 27120 inputs: []inputInfo{ 27121 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27122 }, 27123 outputs: []outputInfo{ 27124 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27125 }, 27126 }, 27127 }, 27128 { 27129 name: "MOVVreg", 27130 argLen: 1, 27131 asm: mips.AMOVV, 27132 reg: regInfo{ 27133 inputs: []inputInfo{ 27134 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27135 }, 27136 outputs: []outputInfo{ 27137 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27138 }, 27139 }, 27140 }, 27141 { 27142 name: "MOVVnop", 27143 argLen: 1, 27144 resultInArg0: true, 27145 reg: regInfo{ 27146 inputs: []inputInfo{ 27147 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27148 }, 27149 outputs: []outputInfo{ 27150 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27151 }, 27152 }, 27153 }, 27154 { 27155 name: "MOVWF", 27156 argLen: 1, 27157 asm: mips.AMOVWF, 27158 reg: regInfo{ 27159 inputs: []inputInfo{ 27160 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27161 }, 27162 outputs: []outputInfo{ 27163 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27164 }, 27165 }, 27166 }, 27167 { 27168 name: "MOVWD", 27169 argLen: 1, 27170 asm: mips.AMOVWD, 27171 reg: regInfo{ 27172 inputs: []inputInfo{ 27173 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27174 }, 27175 outputs: []outputInfo{ 27176 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27177 }, 27178 }, 27179 }, 27180 { 27181 name: "MOVVF", 27182 argLen: 1, 27183 asm: mips.AMOVVF, 27184 reg: regInfo{ 27185 inputs: []inputInfo{ 27186 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27187 }, 27188 outputs: []outputInfo{ 27189 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27190 }, 27191 }, 27192 }, 27193 { 27194 name: "MOVVD", 27195 argLen: 1, 27196 asm: mips.AMOVVD, 27197 reg: regInfo{ 27198 inputs: []inputInfo{ 27199 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27200 }, 27201 outputs: []outputInfo{ 27202 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27203 }, 27204 }, 27205 }, 27206 { 27207 name: "TRUNCFW", 27208 argLen: 1, 27209 asm: mips.ATRUNCFW, 27210 reg: regInfo{ 27211 inputs: []inputInfo{ 27212 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27213 }, 27214 outputs: []outputInfo{ 27215 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27216 }, 27217 }, 27218 }, 27219 { 27220 name: "TRUNCDW", 27221 argLen: 1, 27222 asm: mips.ATRUNCDW, 27223 reg: regInfo{ 27224 inputs: []inputInfo{ 27225 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27226 }, 27227 outputs: []outputInfo{ 27228 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27229 }, 27230 }, 27231 }, 27232 { 27233 name: "TRUNCFV", 27234 argLen: 1, 27235 asm: mips.ATRUNCFV, 27236 reg: regInfo{ 27237 inputs: []inputInfo{ 27238 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27239 }, 27240 outputs: []outputInfo{ 27241 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27242 }, 27243 }, 27244 }, 27245 { 27246 name: "TRUNCDV", 27247 argLen: 1, 27248 asm: mips.ATRUNCDV, 27249 reg: regInfo{ 27250 inputs: []inputInfo{ 27251 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27252 }, 27253 outputs: []outputInfo{ 27254 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27255 }, 27256 }, 27257 }, 27258 { 27259 name: "MOVFD", 27260 argLen: 1, 27261 asm: mips.AMOVFD, 27262 reg: regInfo{ 27263 inputs: []inputInfo{ 27264 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27265 }, 27266 outputs: []outputInfo{ 27267 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27268 }, 27269 }, 27270 }, 27271 { 27272 name: "MOVDF", 27273 argLen: 1, 27274 asm: mips.AMOVDF, 27275 reg: regInfo{ 27276 inputs: []inputInfo{ 27277 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27278 }, 27279 outputs: []outputInfo{ 27280 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 27281 }, 27282 }, 27283 }, 27284 { 27285 name: "CALLstatic", 27286 auxType: auxCallOff, 27287 argLen: 1, 27288 clobberFlags: true, 27289 call: true, 27290 reg: regInfo{ 27291 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 27292 }, 27293 }, 27294 { 27295 name: "CALLtail", 27296 auxType: auxCallOff, 27297 argLen: 1, 27298 clobberFlags: true, 27299 call: true, 27300 tailCall: true, 27301 reg: regInfo{ 27302 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 27303 }, 27304 }, 27305 { 27306 name: "CALLclosure", 27307 auxType: auxCallOff, 27308 argLen: 3, 27309 clobberFlags: true, 27310 call: true, 27311 reg: regInfo{ 27312 inputs: []inputInfo{ 27313 {1, 4194304}, // R22 27314 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 27315 }, 27316 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 27317 }, 27318 }, 27319 { 27320 name: "CALLinter", 27321 auxType: auxCallOff, 27322 argLen: 2, 27323 clobberFlags: true, 27324 call: true, 27325 reg: regInfo{ 27326 inputs: []inputInfo{ 27327 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27328 }, 27329 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 27330 }, 27331 }, 27332 { 27333 name: "DUFFZERO", 27334 auxType: auxInt64, 27335 argLen: 2, 27336 faultOnNilArg0: true, 27337 reg: regInfo{ 27338 inputs: []inputInfo{ 27339 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27340 }, 27341 clobbers: 134217730, // R1 R31 27342 }, 27343 }, 27344 { 27345 name: "DUFFCOPY", 27346 auxType: auxInt64, 27347 argLen: 3, 27348 faultOnNilArg0: true, 27349 faultOnNilArg1: true, 27350 reg: regInfo{ 27351 inputs: []inputInfo{ 27352 {0, 4}, // R2 27353 {1, 2}, // R1 27354 }, 27355 clobbers: 134217734, // R1 R2 R31 27356 }, 27357 }, 27358 { 27359 name: "LoweredZero", 27360 auxType: auxInt64, 27361 argLen: 3, 27362 clobberFlags: true, 27363 faultOnNilArg0: true, 27364 reg: regInfo{ 27365 inputs: []inputInfo{ 27366 {0, 2}, // R1 27367 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27368 }, 27369 clobbers: 2, // R1 27370 }, 27371 }, 27372 { 27373 name: "LoweredMove", 27374 auxType: auxInt64, 27375 argLen: 4, 27376 clobberFlags: true, 27377 faultOnNilArg0: true, 27378 faultOnNilArg1: true, 27379 reg: regInfo{ 27380 inputs: []inputInfo{ 27381 {0, 4}, // R2 27382 {1, 2}, // R1 27383 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27384 }, 27385 clobbers: 6, // R1 R2 27386 }, 27387 }, 27388 { 27389 name: "LoweredAtomicLoad8", 27390 argLen: 2, 27391 faultOnNilArg0: true, 27392 reg: regInfo{ 27393 inputs: []inputInfo{ 27394 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27395 }, 27396 outputs: []outputInfo{ 27397 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27398 }, 27399 }, 27400 }, 27401 { 27402 name: "LoweredAtomicLoad32", 27403 argLen: 2, 27404 faultOnNilArg0: true, 27405 reg: regInfo{ 27406 inputs: []inputInfo{ 27407 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27408 }, 27409 outputs: []outputInfo{ 27410 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27411 }, 27412 }, 27413 }, 27414 { 27415 name: "LoweredAtomicLoad64", 27416 argLen: 2, 27417 faultOnNilArg0: true, 27418 reg: regInfo{ 27419 inputs: []inputInfo{ 27420 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27421 }, 27422 outputs: []outputInfo{ 27423 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27424 }, 27425 }, 27426 }, 27427 { 27428 name: "LoweredAtomicStore8", 27429 argLen: 3, 27430 faultOnNilArg0: true, 27431 hasSideEffects: true, 27432 reg: regInfo{ 27433 inputs: []inputInfo{ 27434 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27435 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27436 }, 27437 }, 27438 }, 27439 { 27440 name: "LoweredAtomicStore32", 27441 argLen: 3, 27442 faultOnNilArg0: true, 27443 hasSideEffects: true, 27444 reg: regInfo{ 27445 inputs: []inputInfo{ 27446 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27447 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27448 }, 27449 }, 27450 }, 27451 { 27452 name: "LoweredAtomicStore64", 27453 argLen: 3, 27454 faultOnNilArg0: true, 27455 hasSideEffects: true, 27456 reg: regInfo{ 27457 inputs: []inputInfo{ 27458 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27459 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27460 }, 27461 }, 27462 }, 27463 { 27464 name: "LoweredAtomicStorezero32", 27465 argLen: 2, 27466 faultOnNilArg0: true, 27467 hasSideEffects: true, 27468 reg: regInfo{ 27469 inputs: []inputInfo{ 27470 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27471 }, 27472 }, 27473 }, 27474 { 27475 name: "LoweredAtomicStorezero64", 27476 argLen: 2, 27477 faultOnNilArg0: true, 27478 hasSideEffects: true, 27479 reg: regInfo{ 27480 inputs: []inputInfo{ 27481 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27482 }, 27483 }, 27484 }, 27485 { 27486 name: "LoweredAtomicExchange32", 27487 argLen: 3, 27488 resultNotInArgs: true, 27489 faultOnNilArg0: true, 27490 hasSideEffects: true, 27491 unsafePoint: true, 27492 reg: regInfo{ 27493 inputs: []inputInfo{ 27494 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27495 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27496 }, 27497 outputs: []outputInfo{ 27498 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27499 }, 27500 }, 27501 }, 27502 { 27503 name: "LoweredAtomicExchange64", 27504 argLen: 3, 27505 resultNotInArgs: true, 27506 faultOnNilArg0: true, 27507 hasSideEffects: true, 27508 unsafePoint: true, 27509 reg: regInfo{ 27510 inputs: []inputInfo{ 27511 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27512 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27513 }, 27514 outputs: []outputInfo{ 27515 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27516 }, 27517 }, 27518 }, 27519 { 27520 name: "LoweredAtomicAdd32", 27521 argLen: 3, 27522 resultNotInArgs: true, 27523 faultOnNilArg0: true, 27524 hasSideEffects: true, 27525 unsafePoint: true, 27526 reg: regInfo{ 27527 inputs: []inputInfo{ 27528 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27529 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27530 }, 27531 outputs: []outputInfo{ 27532 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27533 }, 27534 }, 27535 }, 27536 { 27537 name: "LoweredAtomicAdd64", 27538 argLen: 3, 27539 resultNotInArgs: true, 27540 faultOnNilArg0: true, 27541 hasSideEffects: true, 27542 unsafePoint: true, 27543 reg: regInfo{ 27544 inputs: []inputInfo{ 27545 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27546 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27547 }, 27548 outputs: []outputInfo{ 27549 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27550 }, 27551 }, 27552 }, 27553 { 27554 name: "LoweredAtomicAddconst32", 27555 auxType: auxInt32, 27556 argLen: 2, 27557 resultNotInArgs: true, 27558 faultOnNilArg0: true, 27559 hasSideEffects: true, 27560 unsafePoint: true, 27561 reg: regInfo{ 27562 inputs: []inputInfo{ 27563 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27564 }, 27565 outputs: []outputInfo{ 27566 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27567 }, 27568 }, 27569 }, 27570 { 27571 name: "LoweredAtomicAddconst64", 27572 auxType: auxInt64, 27573 argLen: 2, 27574 resultNotInArgs: true, 27575 faultOnNilArg0: true, 27576 hasSideEffects: true, 27577 unsafePoint: true, 27578 reg: regInfo{ 27579 inputs: []inputInfo{ 27580 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27581 }, 27582 outputs: []outputInfo{ 27583 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27584 }, 27585 }, 27586 }, 27587 { 27588 name: "LoweredAtomicCas32", 27589 argLen: 4, 27590 resultNotInArgs: true, 27591 faultOnNilArg0: true, 27592 hasSideEffects: true, 27593 unsafePoint: true, 27594 reg: regInfo{ 27595 inputs: []inputInfo{ 27596 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27597 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27598 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27599 }, 27600 outputs: []outputInfo{ 27601 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27602 }, 27603 }, 27604 }, 27605 { 27606 name: "LoweredAtomicCas64", 27607 argLen: 4, 27608 resultNotInArgs: true, 27609 faultOnNilArg0: true, 27610 hasSideEffects: true, 27611 unsafePoint: true, 27612 reg: regInfo{ 27613 inputs: []inputInfo{ 27614 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27615 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27616 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 27617 }, 27618 outputs: []outputInfo{ 27619 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27620 }, 27621 }, 27622 }, 27623 { 27624 name: "LoweredNilCheck", 27625 argLen: 2, 27626 nilCheck: true, 27627 faultOnNilArg0: true, 27628 reg: regInfo{ 27629 inputs: []inputInfo{ 27630 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 27631 }, 27632 }, 27633 }, 27634 { 27635 name: "FPFlagTrue", 27636 argLen: 1, 27637 reg: regInfo{ 27638 outputs: []outputInfo{ 27639 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27640 }, 27641 }, 27642 }, 27643 { 27644 name: "FPFlagFalse", 27645 argLen: 1, 27646 reg: regInfo{ 27647 outputs: []outputInfo{ 27648 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27649 }, 27650 }, 27651 }, 27652 { 27653 name: "LoweredGetClosurePtr", 27654 argLen: 0, 27655 zeroWidth: true, 27656 reg: regInfo{ 27657 outputs: []outputInfo{ 27658 {0, 4194304}, // R22 27659 }, 27660 }, 27661 }, 27662 { 27663 name: "LoweredGetCallerSP", 27664 argLen: 0, 27665 rematerializeable: true, 27666 reg: regInfo{ 27667 outputs: []outputInfo{ 27668 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27669 }, 27670 }, 27671 }, 27672 { 27673 name: "LoweredGetCallerPC", 27674 argLen: 0, 27675 rematerializeable: true, 27676 reg: regInfo{ 27677 outputs: []outputInfo{ 27678 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 27679 }, 27680 }, 27681 }, 27682 { 27683 name: "LoweredWB", 27684 auxType: auxSym, 27685 argLen: 3, 27686 clobberFlags: true, 27687 symEffect: SymNone, 27688 reg: regInfo{ 27689 inputs: []inputInfo{ 27690 {0, 1048576}, // R20 27691 {1, 2097152}, // R21 27692 }, 27693 clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 27694 }, 27695 }, 27696 { 27697 name: "LoweredPanicBoundsA", 27698 auxType: auxInt64, 27699 argLen: 3, 27700 call: true, 27701 reg: regInfo{ 27702 inputs: []inputInfo{ 27703 {0, 8}, // R3 27704 {1, 16}, // R4 27705 }, 27706 }, 27707 }, 27708 { 27709 name: "LoweredPanicBoundsB", 27710 auxType: auxInt64, 27711 argLen: 3, 27712 call: true, 27713 reg: regInfo{ 27714 inputs: []inputInfo{ 27715 {0, 4}, // R2 27716 {1, 8}, // R3 27717 }, 27718 }, 27719 }, 27720 { 27721 name: "LoweredPanicBoundsC", 27722 auxType: auxInt64, 27723 argLen: 3, 27724 call: true, 27725 reg: regInfo{ 27726 inputs: []inputInfo{ 27727 {0, 2}, // R1 27728 {1, 4}, // R2 27729 }, 27730 }, 27731 }, 27732 27733 { 27734 name: "ADD", 27735 argLen: 2, 27736 commutative: true, 27737 asm: ppc64.AADD, 27738 reg: regInfo{ 27739 inputs: []inputInfo{ 27740 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27741 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27742 }, 27743 outputs: []outputInfo{ 27744 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27745 }, 27746 }, 27747 }, 27748 { 27749 name: "ADDconst", 27750 auxType: auxInt64, 27751 argLen: 1, 27752 asm: ppc64.AADD, 27753 reg: regInfo{ 27754 inputs: []inputInfo{ 27755 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27756 }, 27757 outputs: []outputInfo{ 27758 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27759 }, 27760 }, 27761 }, 27762 { 27763 name: "FADD", 27764 argLen: 2, 27765 commutative: true, 27766 asm: ppc64.AFADD, 27767 reg: regInfo{ 27768 inputs: []inputInfo{ 27769 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27770 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27771 }, 27772 outputs: []outputInfo{ 27773 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27774 }, 27775 }, 27776 }, 27777 { 27778 name: "FADDS", 27779 argLen: 2, 27780 commutative: true, 27781 asm: ppc64.AFADDS, 27782 reg: regInfo{ 27783 inputs: []inputInfo{ 27784 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27785 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27786 }, 27787 outputs: []outputInfo{ 27788 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27789 }, 27790 }, 27791 }, 27792 { 27793 name: "SUB", 27794 argLen: 2, 27795 asm: ppc64.ASUB, 27796 reg: regInfo{ 27797 inputs: []inputInfo{ 27798 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27799 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27800 }, 27801 outputs: []outputInfo{ 27802 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27803 }, 27804 }, 27805 }, 27806 { 27807 name: "SUBFCconst", 27808 auxType: auxInt64, 27809 argLen: 1, 27810 asm: ppc64.ASUBC, 27811 reg: regInfo{ 27812 inputs: []inputInfo{ 27813 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27814 }, 27815 clobbers: 9223372036854775808, // XER 27816 outputs: []outputInfo{ 27817 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27818 }, 27819 }, 27820 }, 27821 { 27822 name: "FSUB", 27823 argLen: 2, 27824 asm: ppc64.AFSUB, 27825 reg: regInfo{ 27826 inputs: []inputInfo{ 27827 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27828 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27829 }, 27830 outputs: []outputInfo{ 27831 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27832 }, 27833 }, 27834 }, 27835 { 27836 name: "FSUBS", 27837 argLen: 2, 27838 asm: ppc64.AFSUBS, 27839 reg: regInfo{ 27840 inputs: []inputInfo{ 27841 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27842 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27843 }, 27844 outputs: []outputInfo{ 27845 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27846 }, 27847 }, 27848 }, 27849 { 27850 name: "MULLD", 27851 argLen: 2, 27852 commutative: true, 27853 asm: ppc64.AMULLD, 27854 reg: regInfo{ 27855 inputs: []inputInfo{ 27856 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27857 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27858 }, 27859 outputs: []outputInfo{ 27860 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27861 }, 27862 }, 27863 }, 27864 { 27865 name: "MULLW", 27866 argLen: 2, 27867 commutative: true, 27868 asm: ppc64.AMULLW, 27869 reg: regInfo{ 27870 inputs: []inputInfo{ 27871 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27872 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27873 }, 27874 outputs: []outputInfo{ 27875 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27876 }, 27877 }, 27878 }, 27879 { 27880 name: "MULLDconst", 27881 auxType: auxInt32, 27882 argLen: 1, 27883 asm: ppc64.AMULLD, 27884 reg: regInfo{ 27885 inputs: []inputInfo{ 27886 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27887 }, 27888 outputs: []outputInfo{ 27889 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27890 }, 27891 }, 27892 }, 27893 { 27894 name: "MULLWconst", 27895 auxType: auxInt32, 27896 argLen: 1, 27897 asm: ppc64.AMULLW, 27898 reg: regInfo{ 27899 inputs: []inputInfo{ 27900 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27901 }, 27902 outputs: []outputInfo{ 27903 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27904 }, 27905 }, 27906 }, 27907 { 27908 name: "MADDLD", 27909 argLen: 3, 27910 asm: ppc64.AMADDLD, 27911 reg: regInfo{ 27912 inputs: []inputInfo{ 27913 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27914 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27915 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27916 }, 27917 outputs: []outputInfo{ 27918 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27919 }, 27920 }, 27921 }, 27922 { 27923 name: "MULHD", 27924 argLen: 2, 27925 commutative: true, 27926 asm: ppc64.AMULHD, 27927 reg: regInfo{ 27928 inputs: []inputInfo{ 27929 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27930 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27931 }, 27932 outputs: []outputInfo{ 27933 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27934 }, 27935 }, 27936 }, 27937 { 27938 name: "MULHW", 27939 argLen: 2, 27940 commutative: true, 27941 asm: ppc64.AMULHW, 27942 reg: regInfo{ 27943 inputs: []inputInfo{ 27944 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27945 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27946 }, 27947 outputs: []outputInfo{ 27948 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27949 }, 27950 }, 27951 }, 27952 { 27953 name: "MULHDU", 27954 argLen: 2, 27955 commutative: true, 27956 asm: ppc64.AMULHDU, 27957 reg: regInfo{ 27958 inputs: []inputInfo{ 27959 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27960 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27961 }, 27962 outputs: []outputInfo{ 27963 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27964 }, 27965 }, 27966 }, 27967 { 27968 name: "MULHWU", 27969 argLen: 2, 27970 commutative: true, 27971 asm: ppc64.AMULHWU, 27972 reg: regInfo{ 27973 inputs: []inputInfo{ 27974 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27975 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27976 }, 27977 outputs: []outputInfo{ 27978 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 27979 }, 27980 }, 27981 }, 27982 { 27983 name: "FMUL", 27984 argLen: 2, 27985 commutative: true, 27986 asm: ppc64.AFMUL, 27987 reg: regInfo{ 27988 inputs: []inputInfo{ 27989 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27990 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27991 }, 27992 outputs: []outputInfo{ 27993 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 27994 }, 27995 }, 27996 }, 27997 { 27998 name: "FMULS", 27999 argLen: 2, 28000 commutative: true, 28001 asm: ppc64.AFMULS, 28002 reg: regInfo{ 28003 inputs: []inputInfo{ 28004 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28005 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28006 }, 28007 outputs: []outputInfo{ 28008 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28009 }, 28010 }, 28011 }, 28012 { 28013 name: "FMADD", 28014 argLen: 3, 28015 asm: ppc64.AFMADD, 28016 reg: regInfo{ 28017 inputs: []inputInfo{ 28018 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28019 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28020 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28021 }, 28022 outputs: []outputInfo{ 28023 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28024 }, 28025 }, 28026 }, 28027 { 28028 name: "FMADDS", 28029 argLen: 3, 28030 asm: ppc64.AFMADDS, 28031 reg: regInfo{ 28032 inputs: []inputInfo{ 28033 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28034 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28035 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28036 }, 28037 outputs: []outputInfo{ 28038 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28039 }, 28040 }, 28041 }, 28042 { 28043 name: "FMSUB", 28044 argLen: 3, 28045 asm: ppc64.AFMSUB, 28046 reg: regInfo{ 28047 inputs: []inputInfo{ 28048 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28049 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28050 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28051 }, 28052 outputs: []outputInfo{ 28053 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28054 }, 28055 }, 28056 }, 28057 { 28058 name: "FMSUBS", 28059 argLen: 3, 28060 asm: ppc64.AFMSUBS, 28061 reg: regInfo{ 28062 inputs: []inputInfo{ 28063 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28064 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28065 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28066 }, 28067 outputs: []outputInfo{ 28068 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28069 }, 28070 }, 28071 }, 28072 { 28073 name: "SRAD", 28074 argLen: 2, 28075 asm: ppc64.ASRAD, 28076 reg: regInfo{ 28077 inputs: []inputInfo{ 28078 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28079 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28080 }, 28081 clobbers: 9223372036854775808, // XER 28082 outputs: []outputInfo{ 28083 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28084 }, 28085 }, 28086 }, 28087 { 28088 name: "SRAW", 28089 argLen: 2, 28090 asm: ppc64.ASRAW, 28091 reg: regInfo{ 28092 inputs: []inputInfo{ 28093 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28094 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28095 }, 28096 clobbers: 9223372036854775808, // XER 28097 outputs: []outputInfo{ 28098 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28099 }, 28100 }, 28101 }, 28102 { 28103 name: "SRD", 28104 argLen: 2, 28105 asm: ppc64.ASRD, 28106 reg: regInfo{ 28107 inputs: []inputInfo{ 28108 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28109 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28110 }, 28111 outputs: []outputInfo{ 28112 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28113 }, 28114 }, 28115 }, 28116 { 28117 name: "SRW", 28118 argLen: 2, 28119 asm: ppc64.ASRW, 28120 reg: regInfo{ 28121 inputs: []inputInfo{ 28122 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28123 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28124 }, 28125 outputs: []outputInfo{ 28126 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28127 }, 28128 }, 28129 }, 28130 { 28131 name: "SLD", 28132 argLen: 2, 28133 asm: ppc64.ASLD, 28134 reg: regInfo{ 28135 inputs: []inputInfo{ 28136 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28137 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28138 }, 28139 outputs: []outputInfo{ 28140 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28141 }, 28142 }, 28143 }, 28144 { 28145 name: "SLW", 28146 argLen: 2, 28147 asm: ppc64.ASLW, 28148 reg: regInfo{ 28149 inputs: []inputInfo{ 28150 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28151 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28152 }, 28153 outputs: []outputInfo{ 28154 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28155 }, 28156 }, 28157 }, 28158 { 28159 name: "ROTL", 28160 argLen: 2, 28161 asm: ppc64.AROTL, 28162 reg: regInfo{ 28163 inputs: []inputInfo{ 28164 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28165 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28166 }, 28167 outputs: []outputInfo{ 28168 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28169 }, 28170 }, 28171 }, 28172 { 28173 name: "ROTLW", 28174 argLen: 2, 28175 asm: ppc64.AROTLW, 28176 reg: regInfo{ 28177 inputs: []inputInfo{ 28178 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28179 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28180 }, 28181 outputs: []outputInfo{ 28182 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28183 }, 28184 }, 28185 }, 28186 { 28187 name: "RLDICL", 28188 auxType: auxInt32, 28189 argLen: 1, 28190 asm: ppc64.ARLDICL, 28191 reg: regInfo{ 28192 inputs: []inputInfo{ 28193 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28194 }, 28195 outputs: []outputInfo{ 28196 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28197 }, 28198 }, 28199 }, 28200 { 28201 name: "CLRLSLWI", 28202 auxType: auxInt32, 28203 argLen: 1, 28204 asm: ppc64.ACLRLSLWI, 28205 reg: regInfo{ 28206 inputs: []inputInfo{ 28207 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28208 }, 28209 outputs: []outputInfo{ 28210 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28211 }, 28212 }, 28213 }, 28214 { 28215 name: "CLRLSLDI", 28216 auxType: auxInt32, 28217 argLen: 1, 28218 asm: ppc64.ACLRLSLDI, 28219 reg: regInfo{ 28220 inputs: []inputInfo{ 28221 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28222 }, 28223 outputs: []outputInfo{ 28224 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28225 }, 28226 }, 28227 }, 28228 { 28229 name: "ADDC", 28230 argLen: 2, 28231 commutative: true, 28232 asm: ppc64.AADDC, 28233 reg: regInfo{ 28234 inputs: []inputInfo{ 28235 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28236 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28237 }, 28238 clobbers: 9223372036854775808, // XER 28239 outputs: []outputInfo{ 28240 {1, 9223372036854775808}, // XER 28241 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28242 }, 28243 }, 28244 }, 28245 { 28246 name: "SUBC", 28247 argLen: 2, 28248 asm: ppc64.ASUBC, 28249 reg: regInfo{ 28250 inputs: []inputInfo{ 28251 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28252 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28253 }, 28254 clobbers: 9223372036854775808, // XER 28255 outputs: []outputInfo{ 28256 {1, 9223372036854775808}, // XER 28257 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28258 }, 28259 }, 28260 }, 28261 { 28262 name: "ADDCconst", 28263 auxType: auxInt64, 28264 argLen: 1, 28265 asm: ppc64.AADDC, 28266 reg: regInfo{ 28267 inputs: []inputInfo{ 28268 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28269 }, 28270 outputs: []outputInfo{ 28271 {1, 9223372036854775808}, // XER 28272 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28273 }, 28274 }, 28275 }, 28276 { 28277 name: "SUBCconst", 28278 auxType: auxInt64, 28279 argLen: 1, 28280 asm: ppc64.ASUBC, 28281 reg: regInfo{ 28282 inputs: []inputInfo{ 28283 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28284 }, 28285 outputs: []outputInfo{ 28286 {1, 9223372036854775808}, // XER 28287 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28288 }, 28289 }, 28290 }, 28291 { 28292 name: "ADDE", 28293 argLen: 3, 28294 commutative: true, 28295 asm: ppc64.AADDE, 28296 reg: regInfo{ 28297 inputs: []inputInfo{ 28298 {2, 9223372036854775808}, // XER 28299 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28300 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28301 }, 28302 clobbers: 9223372036854775808, // XER 28303 outputs: []outputInfo{ 28304 {1, 9223372036854775808}, // XER 28305 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28306 }, 28307 }, 28308 }, 28309 { 28310 name: "SUBE", 28311 argLen: 3, 28312 asm: ppc64.ASUBE, 28313 reg: regInfo{ 28314 inputs: []inputInfo{ 28315 {2, 9223372036854775808}, // XER 28316 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28317 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28318 }, 28319 clobbers: 9223372036854775808, // XER 28320 outputs: []outputInfo{ 28321 {1, 9223372036854775808}, // XER 28322 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28323 }, 28324 }, 28325 }, 28326 { 28327 name: "ADDZEzero", 28328 argLen: 1, 28329 asm: ppc64.AADDZE, 28330 reg: regInfo{ 28331 inputs: []inputInfo{ 28332 {0, 9223372036854775808}, // XER 28333 }, 28334 clobbers: 9223372036854775808, // XER 28335 outputs: []outputInfo{ 28336 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28337 }, 28338 }, 28339 }, 28340 { 28341 name: "SUBZEzero", 28342 argLen: 1, 28343 asm: ppc64.ASUBZE, 28344 reg: regInfo{ 28345 inputs: []inputInfo{ 28346 {0, 9223372036854775808}, // XER 28347 }, 28348 clobbers: 9223372036854775808, // XER 28349 outputs: []outputInfo{ 28350 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28351 }, 28352 }, 28353 }, 28354 { 28355 name: "SRADconst", 28356 auxType: auxInt64, 28357 argLen: 1, 28358 asm: ppc64.ASRAD, 28359 reg: regInfo{ 28360 inputs: []inputInfo{ 28361 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28362 }, 28363 clobbers: 9223372036854775808, // XER 28364 outputs: []outputInfo{ 28365 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28366 }, 28367 }, 28368 }, 28369 { 28370 name: "SRAWconst", 28371 auxType: auxInt64, 28372 argLen: 1, 28373 asm: ppc64.ASRAW, 28374 reg: regInfo{ 28375 inputs: []inputInfo{ 28376 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28377 }, 28378 clobbers: 9223372036854775808, // XER 28379 outputs: []outputInfo{ 28380 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28381 }, 28382 }, 28383 }, 28384 { 28385 name: "SRDconst", 28386 auxType: auxInt64, 28387 argLen: 1, 28388 asm: ppc64.ASRD, 28389 reg: regInfo{ 28390 inputs: []inputInfo{ 28391 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28392 }, 28393 outputs: []outputInfo{ 28394 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28395 }, 28396 }, 28397 }, 28398 { 28399 name: "SRWconst", 28400 auxType: auxInt64, 28401 argLen: 1, 28402 asm: ppc64.ASRW, 28403 reg: regInfo{ 28404 inputs: []inputInfo{ 28405 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28406 }, 28407 outputs: []outputInfo{ 28408 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28409 }, 28410 }, 28411 }, 28412 { 28413 name: "SLDconst", 28414 auxType: auxInt64, 28415 argLen: 1, 28416 asm: ppc64.ASLD, 28417 reg: regInfo{ 28418 inputs: []inputInfo{ 28419 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28420 }, 28421 outputs: []outputInfo{ 28422 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28423 }, 28424 }, 28425 }, 28426 { 28427 name: "SLWconst", 28428 auxType: auxInt64, 28429 argLen: 1, 28430 asm: ppc64.ASLW, 28431 reg: regInfo{ 28432 inputs: []inputInfo{ 28433 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28434 }, 28435 outputs: []outputInfo{ 28436 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28437 }, 28438 }, 28439 }, 28440 { 28441 name: "ROTLconst", 28442 auxType: auxInt64, 28443 argLen: 1, 28444 asm: ppc64.AROTL, 28445 reg: regInfo{ 28446 inputs: []inputInfo{ 28447 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28448 }, 28449 outputs: []outputInfo{ 28450 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28451 }, 28452 }, 28453 }, 28454 { 28455 name: "ROTLWconst", 28456 auxType: auxInt64, 28457 argLen: 1, 28458 asm: ppc64.AROTLW, 28459 reg: regInfo{ 28460 inputs: []inputInfo{ 28461 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28462 }, 28463 outputs: []outputInfo{ 28464 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28465 }, 28466 }, 28467 }, 28468 { 28469 name: "EXTSWSLconst", 28470 auxType: auxInt64, 28471 argLen: 1, 28472 asm: ppc64.AEXTSWSLI, 28473 reg: regInfo{ 28474 inputs: []inputInfo{ 28475 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28476 }, 28477 outputs: []outputInfo{ 28478 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28479 }, 28480 }, 28481 }, 28482 { 28483 name: "RLWINM", 28484 auxType: auxInt64, 28485 argLen: 1, 28486 asm: ppc64.ARLWNM, 28487 reg: regInfo{ 28488 inputs: []inputInfo{ 28489 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28490 }, 28491 outputs: []outputInfo{ 28492 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28493 }, 28494 }, 28495 }, 28496 { 28497 name: "RLWNM", 28498 auxType: auxInt64, 28499 argLen: 2, 28500 asm: ppc64.ARLWNM, 28501 reg: regInfo{ 28502 inputs: []inputInfo{ 28503 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28504 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28505 }, 28506 outputs: []outputInfo{ 28507 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28508 }, 28509 }, 28510 }, 28511 { 28512 name: "RLWMI", 28513 auxType: auxInt64, 28514 argLen: 2, 28515 resultInArg0: true, 28516 asm: ppc64.ARLWMI, 28517 reg: regInfo{ 28518 inputs: []inputInfo{ 28519 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28520 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28521 }, 28522 outputs: []outputInfo{ 28523 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28524 }, 28525 }, 28526 }, 28527 { 28528 name: "CNTLZD", 28529 argLen: 1, 28530 clobberFlags: true, 28531 asm: ppc64.ACNTLZD, 28532 reg: regInfo{ 28533 inputs: []inputInfo{ 28534 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28535 }, 28536 outputs: []outputInfo{ 28537 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28538 }, 28539 }, 28540 }, 28541 { 28542 name: "CNTLZW", 28543 argLen: 1, 28544 clobberFlags: true, 28545 asm: ppc64.ACNTLZW, 28546 reg: regInfo{ 28547 inputs: []inputInfo{ 28548 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28549 }, 28550 outputs: []outputInfo{ 28551 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28552 }, 28553 }, 28554 }, 28555 { 28556 name: "CNTTZD", 28557 argLen: 1, 28558 asm: ppc64.ACNTTZD, 28559 reg: regInfo{ 28560 inputs: []inputInfo{ 28561 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28562 }, 28563 outputs: []outputInfo{ 28564 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28565 }, 28566 }, 28567 }, 28568 { 28569 name: "CNTTZW", 28570 argLen: 1, 28571 asm: ppc64.ACNTTZW, 28572 reg: regInfo{ 28573 inputs: []inputInfo{ 28574 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28575 }, 28576 outputs: []outputInfo{ 28577 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28578 }, 28579 }, 28580 }, 28581 { 28582 name: "POPCNTD", 28583 argLen: 1, 28584 asm: ppc64.APOPCNTD, 28585 reg: regInfo{ 28586 inputs: []inputInfo{ 28587 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28588 }, 28589 outputs: []outputInfo{ 28590 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28591 }, 28592 }, 28593 }, 28594 { 28595 name: "POPCNTW", 28596 argLen: 1, 28597 asm: ppc64.APOPCNTW, 28598 reg: regInfo{ 28599 inputs: []inputInfo{ 28600 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28601 }, 28602 outputs: []outputInfo{ 28603 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28604 }, 28605 }, 28606 }, 28607 { 28608 name: "POPCNTB", 28609 argLen: 1, 28610 asm: ppc64.APOPCNTB, 28611 reg: regInfo{ 28612 inputs: []inputInfo{ 28613 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28614 }, 28615 outputs: []outputInfo{ 28616 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28617 }, 28618 }, 28619 }, 28620 { 28621 name: "FDIV", 28622 argLen: 2, 28623 asm: ppc64.AFDIV, 28624 reg: regInfo{ 28625 inputs: []inputInfo{ 28626 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28627 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28628 }, 28629 outputs: []outputInfo{ 28630 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28631 }, 28632 }, 28633 }, 28634 { 28635 name: "FDIVS", 28636 argLen: 2, 28637 asm: ppc64.AFDIVS, 28638 reg: regInfo{ 28639 inputs: []inputInfo{ 28640 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28641 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28642 }, 28643 outputs: []outputInfo{ 28644 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28645 }, 28646 }, 28647 }, 28648 { 28649 name: "DIVD", 28650 argLen: 2, 28651 asm: ppc64.ADIVD, 28652 reg: regInfo{ 28653 inputs: []inputInfo{ 28654 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28655 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28656 }, 28657 outputs: []outputInfo{ 28658 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28659 }, 28660 }, 28661 }, 28662 { 28663 name: "DIVW", 28664 argLen: 2, 28665 asm: ppc64.ADIVW, 28666 reg: regInfo{ 28667 inputs: []inputInfo{ 28668 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28669 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28670 }, 28671 outputs: []outputInfo{ 28672 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28673 }, 28674 }, 28675 }, 28676 { 28677 name: "DIVDU", 28678 argLen: 2, 28679 asm: ppc64.ADIVDU, 28680 reg: regInfo{ 28681 inputs: []inputInfo{ 28682 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28683 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28684 }, 28685 outputs: []outputInfo{ 28686 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28687 }, 28688 }, 28689 }, 28690 { 28691 name: "DIVWU", 28692 argLen: 2, 28693 asm: ppc64.ADIVWU, 28694 reg: regInfo{ 28695 inputs: []inputInfo{ 28696 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28697 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28698 }, 28699 outputs: []outputInfo{ 28700 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28701 }, 28702 }, 28703 }, 28704 { 28705 name: "MODUD", 28706 argLen: 2, 28707 asm: ppc64.AMODUD, 28708 reg: regInfo{ 28709 inputs: []inputInfo{ 28710 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28711 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28712 }, 28713 outputs: []outputInfo{ 28714 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28715 }, 28716 }, 28717 }, 28718 { 28719 name: "MODSD", 28720 argLen: 2, 28721 asm: ppc64.AMODSD, 28722 reg: regInfo{ 28723 inputs: []inputInfo{ 28724 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28725 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28726 }, 28727 outputs: []outputInfo{ 28728 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28729 }, 28730 }, 28731 }, 28732 { 28733 name: "MODUW", 28734 argLen: 2, 28735 asm: ppc64.AMODUW, 28736 reg: regInfo{ 28737 inputs: []inputInfo{ 28738 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28739 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28740 }, 28741 outputs: []outputInfo{ 28742 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28743 }, 28744 }, 28745 }, 28746 { 28747 name: "MODSW", 28748 argLen: 2, 28749 asm: ppc64.AMODSW, 28750 reg: regInfo{ 28751 inputs: []inputInfo{ 28752 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28753 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28754 }, 28755 outputs: []outputInfo{ 28756 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28757 }, 28758 }, 28759 }, 28760 { 28761 name: "FCTIDZ", 28762 argLen: 1, 28763 asm: ppc64.AFCTIDZ, 28764 reg: regInfo{ 28765 inputs: []inputInfo{ 28766 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28767 }, 28768 outputs: []outputInfo{ 28769 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28770 }, 28771 }, 28772 }, 28773 { 28774 name: "FCTIWZ", 28775 argLen: 1, 28776 asm: ppc64.AFCTIWZ, 28777 reg: regInfo{ 28778 inputs: []inputInfo{ 28779 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28780 }, 28781 outputs: []outputInfo{ 28782 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28783 }, 28784 }, 28785 }, 28786 { 28787 name: "FCFID", 28788 argLen: 1, 28789 asm: ppc64.AFCFID, 28790 reg: regInfo{ 28791 inputs: []inputInfo{ 28792 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28793 }, 28794 outputs: []outputInfo{ 28795 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28796 }, 28797 }, 28798 }, 28799 { 28800 name: "FCFIDS", 28801 argLen: 1, 28802 asm: ppc64.AFCFIDS, 28803 reg: regInfo{ 28804 inputs: []inputInfo{ 28805 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28806 }, 28807 outputs: []outputInfo{ 28808 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28809 }, 28810 }, 28811 }, 28812 { 28813 name: "FRSP", 28814 argLen: 1, 28815 asm: ppc64.AFRSP, 28816 reg: regInfo{ 28817 inputs: []inputInfo{ 28818 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28819 }, 28820 outputs: []outputInfo{ 28821 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28822 }, 28823 }, 28824 }, 28825 { 28826 name: "MFVSRD", 28827 argLen: 1, 28828 asm: ppc64.AMFVSRD, 28829 reg: regInfo{ 28830 inputs: []inputInfo{ 28831 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28832 }, 28833 outputs: []outputInfo{ 28834 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28835 }, 28836 }, 28837 }, 28838 { 28839 name: "MTVSRD", 28840 argLen: 1, 28841 asm: ppc64.AMTVSRD, 28842 reg: regInfo{ 28843 inputs: []inputInfo{ 28844 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28845 }, 28846 outputs: []outputInfo{ 28847 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 28848 }, 28849 }, 28850 }, 28851 { 28852 name: "AND", 28853 argLen: 2, 28854 commutative: true, 28855 asm: ppc64.AAND, 28856 reg: regInfo{ 28857 inputs: []inputInfo{ 28858 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28859 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28860 }, 28861 outputs: []outputInfo{ 28862 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28863 }, 28864 }, 28865 }, 28866 { 28867 name: "ANDN", 28868 argLen: 2, 28869 asm: ppc64.AANDN, 28870 reg: regInfo{ 28871 inputs: []inputInfo{ 28872 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28873 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28874 }, 28875 outputs: []outputInfo{ 28876 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28877 }, 28878 }, 28879 }, 28880 { 28881 name: "ANDCC", 28882 argLen: 2, 28883 commutative: true, 28884 clobberFlags: true, 28885 asm: ppc64.AANDCC, 28886 reg: regInfo{ 28887 inputs: []inputInfo{ 28888 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28889 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28890 }, 28891 outputs: []outputInfo{ 28892 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28893 }, 28894 }, 28895 }, 28896 { 28897 name: "OR", 28898 argLen: 2, 28899 commutative: true, 28900 asm: ppc64.AOR, 28901 reg: regInfo{ 28902 inputs: []inputInfo{ 28903 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28904 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28905 }, 28906 outputs: []outputInfo{ 28907 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28908 }, 28909 }, 28910 }, 28911 { 28912 name: "ORN", 28913 argLen: 2, 28914 asm: ppc64.AORN, 28915 reg: regInfo{ 28916 inputs: []inputInfo{ 28917 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28918 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28919 }, 28920 outputs: []outputInfo{ 28921 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28922 }, 28923 }, 28924 }, 28925 { 28926 name: "ORCC", 28927 argLen: 2, 28928 commutative: true, 28929 clobberFlags: true, 28930 asm: ppc64.AORCC, 28931 reg: regInfo{ 28932 inputs: []inputInfo{ 28933 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28934 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28935 }, 28936 outputs: []outputInfo{ 28937 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28938 }, 28939 }, 28940 }, 28941 { 28942 name: "NOR", 28943 argLen: 2, 28944 commutative: true, 28945 asm: ppc64.ANOR, 28946 reg: regInfo{ 28947 inputs: []inputInfo{ 28948 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28949 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28950 }, 28951 outputs: []outputInfo{ 28952 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28953 }, 28954 }, 28955 }, 28956 { 28957 name: "XOR", 28958 argLen: 2, 28959 commutative: true, 28960 asm: ppc64.AXOR, 28961 reg: regInfo{ 28962 inputs: []inputInfo{ 28963 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28964 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28965 }, 28966 outputs: []outputInfo{ 28967 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28968 }, 28969 }, 28970 }, 28971 { 28972 name: "XORCC", 28973 argLen: 2, 28974 commutative: true, 28975 clobberFlags: true, 28976 asm: ppc64.AXORCC, 28977 reg: regInfo{ 28978 inputs: []inputInfo{ 28979 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28980 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28981 }, 28982 outputs: []outputInfo{ 28983 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28984 }, 28985 }, 28986 }, 28987 { 28988 name: "EQV", 28989 argLen: 2, 28990 commutative: true, 28991 asm: ppc64.AEQV, 28992 reg: regInfo{ 28993 inputs: []inputInfo{ 28994 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28995 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28996 }, 28997 outputs: []outputInfo{ 28998 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 28999 }, 29000 }, 29001 }, 29002 { 29003 name: "NEG", 29004 argLen: 1, 29005 asm: ppc64.ANEG, 29006 reg: regInfo{ 29007 inputs: []inputInfo{ 29008 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29009 }, 29010 outputs: []outputInfo{ 29011 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29012 }, 29013 }, 29014 }, 29015 { 29016 name: "FNEG", 29017 argLen: 1, 29018 asm: ppc64.AFNEG, 29019 reg: regInfo{ 29020 inputs: []inputInfo{ 29021 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29022 }, 29023 outputs: []outputInfo{ 29024 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29025 }, 29026 }, 29027 }, 29028 { 29029 name: "FSQRT", 29030 argLen: 1, 29031 asm: ppc64.AFSQRT, 29032 reg: regInfo{ 29033 inputs: []inputInfo{ 29034 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29035 }, 29036 outputs: []outputInfo{ 29037 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29038 }, 29039 }, 29040 }, 29041 { 29042 name: "FSQRTS", 29043 argLen: 1, 29044 asm: ppc64.AFSQRTS, 29045 reg: regInfo{ 29046 inputs: []inputInfo{ 29047 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29048 }, 29049 outputs: []outputInfo{ 29050 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29051 }, 29052 }, 29053 }, 29054 { 29055 name: "FFLOOR", 29056 argLen: 1, 29057 asm: ppc64.AFRIM, 29058 reg: regInfo{ 29059 inputs: []inputInfo{ 29060 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29061 }, 29062 outputs: []outputInfo{ 29063 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29064 }, 29065 }, 29066 }, 29067 { 29068 name: "FCEIL", 29069 argLen: 1, 29070 asm: ppc64.AFRIP, 29071 reg: regInfo{ 29072 inputs: []inputInfo{ 29073 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29074 }, 29075 outputs: []outputInfo{ 29076 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29077 }, 29078 }, 29079 }, 29080 { 29081 name: "FTRUNC", 29082 argLen: 1, 29083 asm: ppc64.AFRIZ, 29084 reg: regInfo{ 29085 inputs: []inputInfo{ 29086 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29087 }, 29088 outputs: []outputInfo{ 29089 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29090 }, 29091 }, 29092 }, 29093 { 29094 name: "FROUND", 29095 argLen: 1, 29096 asm: ppc64.AFRIN, 29097 reg: regInfo{ 29098 inputs: []inputInfo{ 29099 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29100 }, 29101 outputs: []outputInfo{ 29102 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29103 }, 29104 }, 29105 }, 29106 { 29107 name: "FABS", 29108 argLen: 1, 29109 asm: ppc64.AFABS, 29110 reg: regInfo{ 29111 inputs: []inputInfo{ 29112 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29113 }, 29114 outputs: []outputInfo{ 29115 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29116 }, 29117 }, 29118 }, 29119 { 29120 name: "FNABS", 29121 argLen: 1, 29122 asm: ppc64.AFNABS, 29123 reg: regInfo{ 29124 inputs: []inputInfo{ 29125 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29126 }, 29127 outputs: []outputInfo{ 29128 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29129 }, 29130 }, 29131 }, 29132 { 29133 name: "FCPSGN", 29134 argLen: 2, 29135 asm: ppc64.AFCPSGN, 29136 reg: regInfo{ 29137 inputs: []inputInfo{ 29138 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29139 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29140 }, 29141 outputs: []outputInfo{ 29142 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29143 }, 29144 }, 29145 }, 29146 { 29147 name: "ORconst", 29148 auxType: auxInt64, 29149 argLen: 1, 29150 asm: ppc64.AOR, 29151 reg: regInfo{ 29152 inputs: []inputInfo{ 29153 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29154 }, 29155 outputs: []outputInfo{ 29156 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29157 }, 29158 }, 29159 }, 29160 { 29161 name: "XORconst", 29162 auxType: auxInt64, 29163 argLen: 1, 29164 asm: ppc64.AXOR, 29165 reg: regInfo{ 29166 inputs: []inputInfo{ 29167 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29168 }, 29169 outputs: []outputInfo{ 29170 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29171 }, 29172 }, 29173 }, 29174 { 29175 name: "ANDCCconst", 29176 auxType: auxInt64, 29177 argLen: 1, 29178 clobberFlags: true, 29179 asm: ppc64.AANDCC, 29180 reg: regInfo{ 29181 inputs: []inputInfo{ 29182 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29183 }, 29184 outputs: []outputInfo{ 29185 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29186 }, 29187 }, 29188 }, 29189 { 29190 name: "MOVBreg", 29191 argLen: 1, 29192 asm: ppc64.AMOVB, 29193 reg: regInfo{ 29194 inputs: []inputInfo{ 29195 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29196 }, 29197 outputs: []outputInfo{ 29198 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29199 }, 29200 }, 29201 }, 29202 { 29203 name: "MOVBZreg", 29204 argLen: 1, 29205 asm: ppc64.AMOVBZ, 29206 reg: regInfo{ 29207 inputs: []inputInfo{ 29208 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29209 }, 29210 outputs: []outputInfo{ 29211 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29212 }, 29213 }, 29214 }, 29215 { 29216 name: "MOVHreg", 29217 argLen: 1, 29218 asm: ppc64.AMOVH, 29219 reg: regInfo{ 29220 inputs: []inputInfo{ 29221 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29222 }, 29223 outputs: []outputInfo{ 29224 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29225 }, 29226 }, 29227 }, 29228 { 29229 name: "MOVHZreg", 29230 argLen: 1, 29231 asm: ppc64.AMOVHZ, 29232 reg: regInfo{ 29233 inputs: []inputInfo{ 29234 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29235 }, 29236 outputs: []outputInfo{ 29237 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29238 }, 29239 }, 29240 }, 29241 { 29242 name: "MOVWreg", 29243 argLen: 1, 29244 asm: ppc64.AMOVW, 29245 reg: regInfo{ 29246 inputs: []inputInfo{ 29247 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29248 }, 29249 outputs: []outputInfo{ 29250 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29251 }, 29252 }, 29253 }, 29254 { 29255 name: "MOVWZreg", 29256 argLen: 1, 29257 asm: ppc64.AMOVWZ, 29258 reg: regInfo{ 29259 inputs: []inputInfo{ 29260 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29261 }, 29262 outputs: []outputInfo{ 29263 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29264 }, 29265 }, 29266 }, 29267 { 29268 name: "MOVBZload", 29269 auxType: auxSymOff, 29270 argLen: 2, 29271 faultOnNilArg0: true, 29272 symEffect: SymRead, 29273 asm: ppc64.AMOVBZ, 29274 reg: regInfo{ 29275 inputs: []inputInfo{ 29276 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29277 }, 29278 outputs: []outputInfo{ 29279 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29280 }, 29281 }, 29282 }, 29283 { 29284 name: "MOVHload", 29285 auxType: auxSymOff, 29286 argLen: 2, 29287 faultOnNilArg0: true, 29288 symEffect: SymRead, 29289 asm: ppc64.AMOVH, 29290 reg: regInfo{ 29291 inputs: []inputInfo{ 29292 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29293 }, 29294 outputs: []outputInfo{ 29295 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29296 }, 29297 }, 29298 }, 29299 { 29300 name: "MOVHZload", 29301 auxType: auxSymOff, 29302 argLen: 2, 29303 faultOnNilArg0: true, 29304 symEffect: SymRead, 29305 asm: ppc64.AMOVHZ, 29306 reg: regInfo{ 29307 inputs: []inputInfo{ 29308 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29309 }, 29310 outputs: []outputInfo{ 29311 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29312 }, 29313 }, 29314 }, 29315 { 29316 name: "MOVWload", 29317 auxType: auxSymOff, 29318 argLen: 2, 29319 faultOnNilArg0: true, 29320 symEffect: SymRead, 29321 asm: ppc64.AMOVW, 29322 reg: regInfo{ 29323 inputs: []inputInfo{ 29324 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29325 }, 29326 outputs: []outputInfo{ 29327 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29328 }, 29329 }, 29330 }, 29331 { 29332 name: "MOVWZload", 29333 auxType: auxSymOff, 29334 argLen: 2, 29335 faultOnNilArg0: true, 29336 symEffect: SymRead, 29337 asm: ppc64.AMOVWZ, 29338 reg: regInfo{ 29339 inputs: []inputInfo{ 29340 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29341 }, 29342 outputs: []outputInfo{ 29343 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29344 }, 29345 }, 29346 }, 29347 { 29348 name: "MOVDload", 29349 auxType: auxSymOff, 29350 argLen: 2, 29351 faultOnNilArg0: true, 29352 symEffect: SymRead, 29353 asm: ppc64.AMOVD, 29354 reg: regInfo{ 29355 inputs: []inputInfo{ 29356 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29357 }, 29358 outputs: []outputInfo{ 29359 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29360 }, 29361 }, 29362 }, 29363 { 29364 name: "MOVDBRload", 29365 auxType: auxSymOff, 29366 argLen: 2, 29367 faultOnNilArg0: true, 29368 symEffect: SymRead, 29369 asm: ppc64.AMOVDBR, 29370 reg: regInfo{ 29371 inputs: []inputInfo{ 29372 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29373 }, 29374 outputs: []outputInfo{ 29375 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29376 }, 29377 }, 29378 }, 29379 { 29380 name: "MOVWBRload", 29381 auxType: auxSymOff, 29382 argLen: 2, 29383 faultOnNilArg0: true, 29384 symEffect: SymRead, 29385 asm: ppc64.AMOVWBR, 29386 reg: regInfo{ 29387 inputs: []inputInfo{ 29388 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29389 }, 29390 outputs: []outputInfo{ 29391 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29392 }, 29393 }, 29394 }, 29395 { 29396 name: "MOVHBRload", 29397 auxType: auxSymOff, 29398 argLen: 2, 29399 faultOnNilArg0: true, 29400 symEffect: SymRead, 29401 asm: ppc64.AMOVHBR, 29402 reg: regInfo{ 29403 inputs: []inputInfo{ 29404 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29405 }, 29406 outputs: []outputInfo{ 29407 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29408 }, 29409 }, 29410 }, 29411 { 29412 name: "MOVBZloadidx", 29413 argLen: 3, 29414 asm: ppc64.AMOVBZ, 29415 reg: regInfo{ 29416 inputs: []inputInfo{ 29417 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29418 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29419 }, 29420 outputs: []outputInfo{ 29421 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29422 }, 29423 }, 29424 }, 29425 { 29426 name: "MOVHloadidx", 29427 argLen: 3, 29428 asm: ppc64.AMOVH, 29429 reg: regInfo{ 29430 inputs: []inputInfo{ 29431 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29432 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29433 }, 29434 outputs: []outputInfo{ 29435 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29436 }, 29437 }, 29438 }, 29439 { 29440 name: "MOVHZloadidx", 29441 argLen: 3, 29442 asm: ppc64.AMOVHZ, 29443 reg: regInfo{ 29444 inputs: []inputInfo{ 29445 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29446 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29447 }, 29448 outputs: []outputInfo{ 29449 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29450 }, 29451 }, 29452 }, 29453 { 29454 name: "MOVWloadidx", 29455 argLen: 3, 29456 asm: ppc64.AMOVW, 29457 reg: regInfo{ 29458 inputs: []inputInfo{ 29459 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29460 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29461 }, 29462 outputs: []outputInfo{ 29463 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29464 }, 29465 }, 29466 }, 29467 { 29468 name: "MOVWZloadidx", 29469 argLen: 3, 29470 asm: ppc64.AMOVWZ, 29471 reg: regInfo{ 29472 inputs: []inputInfo{ 29473 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29474 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29475 }, 29476 outputs: []outputInfo{ 29477 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29478 }, 29479 }, 29480 }, 29481 { 29482 name: "MOVDloadidx", 29483 argLen: 3, 29484 asm: ppc64.AMOVD, 29485 reg: regInfo{ 29486 inputs: []inputInfo{ 29487 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29488 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29489 }, 29490 outputs: []outputInfo{ 29491 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29492 }, 29493 }, 29494 }, 29495 { 29496 name: "MOVHBRloadidx", 29497 argLen: 3, 29498 asm: ppc64.AMOVHBR, 29499 reg: regInfo{ 29500 inputs: []inputInfo{ 29501 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29502 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29503 }, 29504 outputs: []outputInfo{ 29505 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29506 }, 29507 }, 29508 }, 29509 { 29510 name: "MOVWBRloadidx", 29511 argLen: 3, 29512 asm: ppc64.AMOVWBR, 29513 reg: regInfo{ 29514 inputs: []inputInfo{ 29515 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29516 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29517 }, 29518 outputs: []outputInfo{ 29519 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29520 }, 29521 }, 29522 }, 29523 { 29524 name: "MOVDBRloadidx", 29525 argLen: 3, 29526 asm: ppc64.AMOVDBR, 29527 reg: regInfo{ 29528 inputs: []inputInfo{ 29529 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29530 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29531 }, 29532 outputs: []outputInfo{ 29533 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29534 }, 29535 }, 29536 }, 29537 { 29538 name: "FMOVDloadidx", 29539 argLen: 3, 29540 asm: ppc64.AFMOVD, 29541 reg: regInfo{ 29542 inputs: []inputInfo{ 29543 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29544 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29545 }, 29546 outputs: []outputInfo{ 29547 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29548 }, 29549 }, 29550 }, 29551 { 29552 name: "FMOVSloadidx", 29553 argLen: 3, 29554 asm: ppc64.AFMOVS, 29555 reg: regInfo{ 29556 inputs: []inputInfo{ 29557 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29558 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29559 }, 29560 outputs: []outputInfo{ 29561 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29562 }, 29563 }, 29564 }, 29565 { 29566 name: "DCBT", 29567 auxType: auxInt64, 29568 argLen: 2, 29569 hasSideEffects: true, 29570 asm: ppc64.ADCBT, 29571 reg: regInfo{ 29572 inputs: []inputInfo{ 29573 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29574 }, 29575 }, 29576 }, 29577 { 29578 name: "MOVDBRstore", 29579 auxType: auxSym, 29580 argLen: 3, 29581 faultOnNilArg0: true, 29582 symEffect: SymWrite, 29583 asm: ppc64.AMOVDBR, 29584 reg: regInfo{ 29585 inputs: []inputInfo{ 29586 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29587 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29588 }, 29589 }, 29590 }, 29591 { 29592 name: "MOVWBRstore", 29593 auxType: auxSym, 29594 argLen: 3, 29595 faultOnNilArg0: true, 29596 symEffect: SymWrite, 29597 asm: ppc64.AMOVWBR, 29598 reg: regInfo{ 29599 inputs: []inputInfo{ 29600 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29601 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29602 }, 29603 }, 29604 }, 29605 { 29606 name: "MOVHBRstore", 29607 auxType: auxSym, 29608 argLen: 3, 29609 faultOnNilArg0: true, 29610 symEffect: SymWrite, 29611 asm: ppc64.AMOVHBR, 29612 reg: regInfo{ 29613 inputs: []inputInfo{ 29614 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29615 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29616 }, 29617 }, 29618 }, 29619 { 29620 name: "FMOVDload", 29621 auxType: auxSymOff, 29622 argLen: 2, 29623 faultOnNilArg0: true, 29624 symEffect: SymRead, 29625 asm: ppc64.AFMOVD, 29626 reg: regInfo{ 29627 inputs: []inputInfo{ 29628 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29629 }, 29630 outputs: []outputInfo{ 29631 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29632 }, 29633 }, 29634 }, 29635 { 29636 name: "FMOVSload", 29637 auxType: auxSymOff, 29638 argLen: 2, 29639 faultOnNilArg0: true, 29640 symEffect: SymRead, 29641 asm: ppc64.AFMOVS, 29642 reg: regInfo{ 29643 inputs: []inputInfo{ 29644 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29645 }, 29646 outputs: []outputInfo{ 29647 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29648 }, 29649 }, 29650 }, 29651 { 29652 name: "MOVBstore", 29653 auxType: auxSymOff, 29654 argLen: 3, 29655 faultOnNilArg0: true, 29656 symEffect: SymWrite, 29657 asm: ppc64.AMOVB, 29658 reg: regInfo{ 29659 inputs: []inputInfo{ 29660 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29661 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29662 }, 29663 }, 29664 }, 29665 { 29666 name: "MOVHstore", 29667 auxType: auxSymOff, 29668 argLen: 3, 29669 faultOnNilArg0: true, 29670 symEffect: SymWrite, 29671 asm: ppc64.AMOVH, 29672 reg: regInfo{ 29673 inputs: []inputInfo{ 29674 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29675 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29676 }, 29677 }, 29678 }, 29679 { 29680 name: "MOVWstore", 29681 auxType: auxSymOff, 29682 argLen: 3, 29683 faultOnNilArg0: true, 29684 symEffect: SymWrite, 29685 asm: ppc64.AMOVW, 29686 reg: regInfo{ 29687 inputs: []inputInfo{ 29688 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29689 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29690 }, 29691 }, 29692 }, 29693 { 29694 name: "MOVDstore", 29695 auxType: auxSymOff, 29696 argLen: 3, 29697 faultOnNilArg0: true, 29698 symEffect: SymWrite, 29699 asm: ppc64.AMOVD, 29700 reg: regInfo{ 29701 inputs: []inputInfo{ 29702 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29703 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29704 }, 29705 }, 29706 }, 29707 { 29708 name: "FMOVDstore", 29709 auxType: auxSymOff, 29710 argLen: 3, 29711 faultOnNilArg0: true, 29712 symEffect: SymWrite, 29713 asm: ppc64.AFMOVD, 29714 reg: regInfo{ 29715 inputs: []inputInfo{ 29716 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29717 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29718 }, 29719 }, 29720 }, 29721 { 29722 name: "FMOVSstore", 29723 auxType: auxSymOff, 29724 argLen: 3, 29725 faultOnNilArg0: true, 29726 symEffect: SymWrite, 29727 asm: ppc64.AFMOVS, 29728 reg: regInfo{ 29729 inputs: []inputInfo{ 29730 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29731 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29732 }, 29733 }, 29734 }, 29735 { 29736 name: "MOVBstoreidx", 29737 argLen: 4, 29738 asm: ppc64.AMOVB, 29739 reg: regInfo{ 29740 inputs: []inputInfo{ 29741 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29742 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29743 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29744 }, 29745 }, 29746 }, 29747 { 29748 name: "MOVHstoreidx", 29749 argLen: 4, 29750 asm: ppc64.AMOVH, 29751 reg: regInfo{ 29752 inputs: []inputInfo{ 29753 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29754 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29755 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29756 }, 29757 }, 29758 }, 29759 { 29760 name: "MOVWstoreidx", 29761 argLen: 4, 29762 asm: ppc64.AMOVW, 29763 reg: regInfo{ 29764 inputs: []inputInfo{ 29765 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29766 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29767 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29768 }, 29769 }, 29770 }, 29771 { 29772 name: "MOVDstoreidx", 29773 argLen: 4, 29774 asm: ppc64.AMOVD, 29775 reg: regInfo{ 29776 inputs: []inputInfo{ 29777 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29778 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29779 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29780 }, 29781 }, 29782 }, 29783 { 29784 name: "FMOVDstoreidx", 29785 argLen: 4, 29786 asm: ppc64.AFMOVD, 29787 reg: regInfo{ 29788 inputs: []inputInfo{ 29789 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29790 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29791 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29792 }, 29793 }, 29794 }, 29795 { 29796 name: "FMOVSstoreidx", 29797 argLen: 4, 29798 asm: ppc64.AFMOVS, 29799 reg: regInfo{ 29800 inputs: []inputInfo{ 29801 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29802 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29803 {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29804 }, 29805 }, 29806 }, 29807 { 29808 name: "MOVHBRstoreidx", 29809 argLen: 4, 29810 asm: ppc64.AMOVHBR, 29811 reg: regInfo{ 29812 inputs: []inputInfo{ 29813 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29814 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29815 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29816 }, 29817 }, 29818 }, 29819 { 29820 name: "MOVWBRstoreidx", 29821 argLen: 4, 29822 asm: ppc64.AMOVWBR, 29823 reg: regInfo{ 29824 inputs: []inputInfo{ 29825 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29826 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29827 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29828 }, 29829 }, 29830 }, 29831 { 29832 name: "MOVDBRstoreidx", 29833 argLen: 4, 29834 asm: ppc64.AMOVDBR, 29835 reg: regInfo{ 29836 inputs: []inputInfo{ 29837 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29838 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29839 {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29840 }, 29841 }, 29842 }, 29843 { 29844 name: "MOVBstorezero", 29845 auxType: auxSymOff, 29846 argLen: 2, 29847 faultOnNilArg0: true, 29848 symEffect: SymWrite, 29849 asm: ppc64.AMOVB, 29850 reg: regInfo{ 29851 inputs: []inputInfo{ 29852 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29853 }, 29854 }, 29855 }, 29856 { 29857 name: "MOVHstorezero", 29858 auxType: auxSymOff, 29859 argLen: 2, 29860 faultOnNilArg0: true, 29861 symEffect: SymWrite, 29862 asm: ppc64.AMOVH, 29863 reg: regInfo{ 29864 inputs: []inputInfo{ 29865 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29866 }, 29867 }, 29868 }, 29869 { 29870 name: "MOVWstorezero", 29871 auxType: auxSymOff, 29872 argLen: 2, 29873 faultOnNilArg0: true, 29874 symEffect: SymWrite, 29875 asm: ppc64.AMOVW, 29876 reg: regInfo{ 29877 inputs: []inputInfo{ 29878 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29879 }, 29880 }, 29881 }, 29882 { 29883 name: "MOVDstorezero", 29884 auxType: auxSymOff, 29885 argLen: 2, 29886 faultOnNilArg0: true, 29887 symEffect: SymWrite, 29888 asm: ppc64.AMOVD, 29889 reg: regInfo{ 29890 inputs: []inputInfo{ 29891 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29892 }, 29893 }, 29894 }, 29895 { 29896 name: "MOVDaddr", 29897 auxType: auxSymOff, 29898 argLen: 1, 29899 rematerializeable: true, 29900 symEffect: SymAddr, 29901 asm: ppc64.AMOVD, 29902 reg: regInfo{ 29903 inputs: []inputInfo{ 29904 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29905 }, 29906 outputs: []outputInfo{ 29907 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29908 }, 29909 }, 29910 }, 29911 { 29912 name: "MOVDconst", 29913 auxType: auxInt64, 29914 argLen: 0, 29915 rematerializeable: true, 29916 asm: ppc64.AMOVD, 29917 reg: regInfo{ 29918 outputs: []outputInfo{ 29919 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29920 }, 29921 }, 29922 }, 29923 { 29924 name: "FMOVDconst", 29925 auxType: auxFloat64, 29926 argLen: 0, 29927 rematerializeable: true, 29928 asm: ppc64.AFMOVD, 29929 reg: regInfo{ 29930 outputs: []outputInfo{ 29931 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29932 }, 29933 }, 29934 }, 29935 { 29936 name: "FMOVSconst", 29937 auxType: auxFloat32, 29938 argLen: 0, 29939 rematerializeable: true, 29940 asm: ppc64.AFMOVS, 29941 reg: regInfo{ 29942 outputs: []outputInfo{ 29943 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29944 }, 29945 }, 29946 }, 29947 { 29948 name: "FCMPU", 29949 argLen: 2, 29950 asm: ppc64.AFCMPU, 29951 reg: regInfo{ 29952 inputs: []inputInfo{ 29953 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29954 {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 29955 }, 29956 }, 29957 }, 29958 { 29959 name: "CMP", 29960 argLen: 2, 29961 asm: ppc64.ACMP, 29962 reg: regInfo{ 29963 inputs: []inputInfo{ 29964 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29965 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29966 }, 29967 }, 29968 }, 29969 { 29970 name: "CMPU", 29971 argLen: 2, 29972 asm: ppc64.ACMPU, 29973 reg: regInfo{ 29974 inputs: []inputInfo{ 29975 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29976 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29977 }, 29978 }, 29979 }, 29980 { 29981 name: "CMPW", 29982 argLen: 2, 29983 asm: ppc64.ACMPW, 29984 reg: regInfo{ 29985 inputs: []inputInfo{ 29986 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29987 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29988 }, 29989 }, 29990 }, 29991 { 29992 name: "CMPWU", 29993 argLen: 2, 29994 asm: ppc64.ACMPWU, 29995 reg: regInfo{ 29996 inputs: []inputInfo{ 29997 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29998 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 29999 }, 30000 }, 30001 }, 30002 { 30003 name: "CMPconst", 30004 auxType: auxInt64, 30005 argLen: 1, 30006 asm: ppc64.ACMP, 30007 reg: regInfo{ 30008 inputs: []inputInfo{ 30009 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30010 }, 30011 }, 30012 }, 30013 { 30014 name: "CMPUconst", 30015 auxType: auxInt64, 30016 argLen: 1, 30017 asm: ppc64.ACMPU, 30018 reg: regInfo{ 30019 inputs: []inputInfo{ 30020 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30021 }, 30022 }, 30023 }, 30024 { 30025 name: "CMPWconst", 30026 auxType: auxInt32, 30027 argLen: 1, 30028 asm: ppc64.ACMPW, 30029 reg: regInfo{ 30030 inputs: []inputInfo{ 30031 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30032 }, 30033 }, 30034 }, 30035 { 30036 name: "CMPWUconst", 30037 auxType: auxInt32, 30038 argLen: 1, 30039 asm: ppc64.ACMPWU, 30040 reg: regInfo{ 30041 inputs: []inputInfo{ 30042 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30043 }, 30044 }, 30045 }, 30046 { 30047 name: "ISEL", 30048 auxType: auxInt32, 30049 argLen: 3, 30050 asm: ppc64.AISEL, 30051 reg: regInfo{ 30052 inputs: []inputInfo{ 30053 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30054 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30055 }, 30056 outputs: []outputInfo{ 30057 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30058 }, 30059 }, 30060 }, 30061 { 30062 name: "ISELB", 30063 auxType: auxInt32, 30064 argLen: 2, 30065 asm: ppc64.AISEL, 30066 reg: regInfo{ 30067 inputs: []inputInfo{ 30068 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30069 }, 30070 outputs: []outputInfo{ 30071 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30072 }, 30073 }, 30074 }, 30075 { 30076 name: "ISELZ", 30077 auxType: auxInt32, 30078 argLen: 2, 30079 asm: ppc64.AISEL, 30080 reg: regInfo{ 30081 inputs: []inputInfo{ 30082 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30083 }, 30084 outputs: []outputInfo{ 30085 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30086 }, 30087 }, 30088 }, 30089 { 30090 name: "Equal", 30091 argLen: 1, 30092 reg: regInfo{ 30093 outputs: []outputInfo{ 30094 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30095 }, 30096 }, 30097 }, 30098 { 30099 name: "NotEqual", 30100 argLen: 1, 30101 reg: regInfo{ 30102 outputs: []outputInfo{ 30103 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30104 }, 30105 }, 30106 }, 30107 { 30108 name: "LessThan", 30109 argLen: 1, 30110 reg: regInfo{ 30111 outputs: []outputInfo{ 30112 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30113 }, 30114 }, 30115 }, 30116 { 30117 name: "FLessThan", 30118 argLen: 1, 30119 reg: regInfo{ 30120 outputs: []outputInfo{ 30121 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30122 }, 30123 }, 30124 }, 30125 { 30126 name: "LessEqual", 30127 argLen: 1, 30128 reg: regInfo{ 30129 outputs: []outputInfo{ 30130 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30131 }, 30132 }, 30133 }, 30134 { 30135 name: "FLessEqual", 30136 argLen: 1, 30137 reg: regInfo{ 30138 outputs: []outputInfo{ 30139 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30140 }, 30141 }, 30142 }, 30143 { 30144 name: "GreaterThan", 30145 argLen: 1, 30146 reg: regInfo{ 30147 outputs: []outputInfo{ 30148 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30149 }, 30150 }, 30151 }, 30152 { 30153 name: "FGreaterThan", 30154 argLen: 1, 30155 reg: regInfo{ 30156 outputs: []outputInfo{ 30157 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30158 }, 30159 }, 30160 }, 30161 { 30162 name: "GreaterEqual", 30163 argLen: 1, 30164 reg: regInfo{ 30165 outputs: []outputInfo{ 30166 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30167 }, 30168 }, 30169 }, 30170 { 30171 name: "FGreaterEqual", 30172 argLen: 1, 30173 reg: regInfo{ 30174 outputs: []outputInfo{ 30175 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30176 }, 30177 }, 30178 }, 30179 { 30180 name: "LoweredGetClosurePtr", 30181 argLen: 0, 30182 zeroWidth: true, 30183 reg: regInfo{ 30184 outputs: []outputInfo{ 30185 {0, 2048}, // R11 30186 }, 30187 }, 30188 }, 30189 { 30190 name: "LoweredGetCallerSP", 30191 argLen: 0, 30192 rematerializeable: true, 30193 reg: regInfo{ 30194 outputs: []outputInfo{ 30195 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30196 }, 30197 }, 30198 }, 30199 { 30200 name: "LoweredGetCallerPC", 30201 argLen: 0, 30202 rematerializeable: true, 30203 reg: regInfo{ 30204 outputs: []outputInfo{ 30205 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30206 }, 30207 }, 30208 }, 30209 { 30210 name: "LoweredNilCheck", 30211 argLen: 2, 30212 clobberFlags: true, 30213 nilCheck: true, 30214 faultOnNilArg0: true, 30215 reg: regInfo{ 30216 inputs: []inputInfo{ 30217 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30218 }, 30219 clobbers: 2147483648, // R31 30220 }, 30221 }, 30222 { 30223 name: "LoweredRound32F", 30224 argLen: 1, 30225 resultInArg0: true, 30226 zeroWidth: true, 30227 reg: regInfo{ 30228 inputs: []inputInfo{ 30229 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 30230 }, 30231 outputs: []outputInfo{ 30232 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 30233 }, 30234 }, 30235 }, 30236 { 30237 name: "LoweredRound64F", 30238 argLen: 1, 30239 resultInArg0: true, 30240 zeroWidth: true, 30241 reg: regInfo{ 30242 inputs: []inputInfo{ 30243 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 30244 }, 30245 outputs: []outputInfo{ 30246 {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 30247 }, 30248 }, 30249 }, 30250 { 30251 name: "CALLstatic", 30252 auxType: auxCallOff, 30253 argLen: -1, 30254 clobberFlags: true, 30255 call: true, 30256 reg: regInfo{ 30257 clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER 30258 }, 30259 }, 30260 { 30261 name: "CALLtail", 30262 auxType: auxCallOff, 30263 argLen: -1, 30264 clobberFlags: true, 30265 call: true, 30266 tailCall: true, 30267 reg: regInfo{ 30268 clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER 30269 }, 30270 }, 30271 { 30272 name: "CALLclosure", 30273 auxType: auxCallOff, 30274 argLen: -1, 30275 clobberFlags: true, 30276 call: true, 30277 reg: regInfo{ 30278 inputs: []inputInfo{ 30279 {0, 4096}, // R12 30280 {1, 2048}, // R11 30281 }, 30282 clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER 30283 }, 30284 }, 30285 { 30286 name: "CALLinter", 30287 auxType: auxCallOff, 30288 argLen: -1, 30289 clobberFlags: true, 30290 call: true, 30291 reg: regInfo{ 30292 inputs: []inputInfo{ 30293 {0, 4096}, // R12 30294 }, 30295 clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER 30296 }, 30297 }, 30298 { 30299 name: "LoweredZero", 30300 auxType: auxInt64, 30301 argLen: 2, 30302 clobberFlags: true, 30303 faultOnNilArg0: true, 30304 unsafePoint: true, 30305 reg: regInfo{ 30306 inputs: []inputInfo{ 30307 {0, 1048576}, // R20 30308 }, 30309 clobbers: 1048576, // R20 30310 }, 30311 }, 30312 { 30313 name: "LoweredZeroShort", 30314 auxType: auxInt64, 30315 argLen: 2, 30316 faultOnNilArg0: true, 30317 unsafePoint: true, 30318 reg: regInfo{ 30319 inputs: []inputInfo{ 30320 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30321 }, 30322 }, 30323 }, 30324 { 30325 name: "LoweredQuadZeroShort", 30326 auxType: auxInt64, 30327 argLen: 2, 30328 faultOnNilArg0: true, 30329 unsafePoint: true, 30330 reg: regInfo{ 30331 inputs: []inputInfo{ 30332 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30333 }, 30334 }, 30335 }, 30336 { 30337 name: "LoweredQuadZero", 30338 auxType: auxInt64, 30339 argLen: 2, 30340 clobberFlags: true, 30341 faultOnNilArg0: true, 30342 unsafePoint: true, 30343 reg: regInfo{ 30344 inputs: []inputInfo{ 30345 {0, 1048576}, // R20 30346 }, 30347 clobbers: 1048576, // R20 30348 }, 30349 }, 30350 { 30351 name: "LoweredMove", 30352 auxType: auxInt64, 30353 argLen: 3, 30354 clobberFlags: true, 30355 faultOnNilArg0: true, 30356 faultOnNilArg1: true, 30357 unsafePoint: true, 30358 reg: regInfo{ 30359 inputs: []inputInfo{ 30360 {0, 1048576}, // R20 30361 {1, 2097152}, // R21 30362 }, 30363 clobbers: 3145728, // R20 R21 30364 }, 30365 }, 30366 { 30367 name: "LoweredMoveShort", 30368 auxType: auxInt64, 30369 argLen: 3, 30370 faultOnNilArg0: true, 30371 faultOnNilArg1: true, 30372 unsafePoint: true, 30373 reg: regInfo{ 30374 inputs: []inputInfo{ 30375 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30376 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30377 }, 30378 }, 30379 }, 30380 { 30381 name: "LoweredQuadMove", 30382 auxType: auxInt64, 30383 argLen: 3, 30384 clobberFlags: true, 30385 faultOnNilArg0: true, 30386 faultOnNilArg1: true, 30387 unsafePoint: true, 30388 reg: regInfo{ 30389 inputs: []inputInfo{ 30390 {0, 1048576}, // R20 30391 {1, 2097152}, // R21 30392 }, 30393 clobbers: 3145728, // R20 R21 30394 }, 30395 }, 30396 { 30397 name: "LoweredQuadMoveShort", 30398 auxType: auxInt64, 30399 argLen: 3, 30400 faultOnNilArg0: true, 30401 faultOnNilArg1: true, 30402 unsafePoint: true, 30403 reg: regInfo{ 30404 inputs: []inputInfo{ 30405 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30406 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30407 }, 30408 }, 30409 }, 30410 { 30411 name: "LoweredAtomicStore8", 30412 auxType: auxInt64, 30413 argLen: 3, 30414 faultOnNilArg0: true, 30415 hasSideEffects: true, 30416 reg: regInfo{ 30417 inputs: []inputInfo{ 30418 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30419 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30420 }, 30421 }, 30422 }, 30423 { 30424 name: "LoweredAtomicStore32", 30425 auxType: auxInt64, 30426 argLen: 3, 30427 faultOnNilArg0: true, 30428 hasSideEffects: true, 30429 reg: regInfo{ 30430 inputs: []inputInfo{ 30431 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30432 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30433 }, 30434 }, 30435 }, 30436 { 30437 name: "LoweredAtomicStore64", 30438 auxType: auxInt64, 30439 argLen: 3, 30440 faultOnNilArg0: true, 30441 hasSideEffects: true, 30442 reg: regInfo{ 30443 inputs: []inputInfo{ 30444 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30445 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30446 }, 30447 }, 30448 }, 30449 { 30450 name: "LoweredAtomicLoad8", 30451 auxType: auxInt64, 30452 argLen: 2, 30453 clobberFlags: true, 30454 faultOnNilArg0: true, 30455 reg: regInfo{ 30456 inputs: []inputInfo{ 30457 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30458 }, 30459 outputs: []outputInfo{ 30460 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30461 }, 30462 }, 30463 }, 30464 { 30465 name: "LoweredAtomicLoad32", 30466 auxType: auxInt64, 30467 argLen: 2, 30468 clobberFlags: true, 30469 faultOnNilArg0: true, 30470 reg: regInfo{ 30471 inputs: []inputInfo{ 30472 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30473 }, 30474 outputs: []outputInfo{ 30475 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30476 }, 30477 }, 30478 }, 30479 { 30480 name: "LoweredAtomicLoad64", 30481 auxType: auxInt64, 30482 argLen: 2, 30483 clobberFlags: true, 30484 faultOnNilArg0: true, 30485 reg: regInfo{ 30486 inputs: []inputInfo{ 30487 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30488 }, 30489 outputs: []outputInfo{ 30490 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30491 }, 30492 }, 30493 }, 30494 { 30495 name: "LoweredAtomicLoadPtr", 30496 auxType: auxInt64, 30497 argLen: 2, 30498 clobberFlags: true, 30499 faultOnNilArg0: true, 30500 reg: regInfo{ 30501 inputs: []inputInfo{ 30502 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30503 }, 30504 outputs: []outputInfo{ 30505 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30506 }, 30507 }, 30508 }, 30509 { 30510 name: "LoweredAtomicAdd32", 30511 argLen: 3, 30512 resultNotInArgs: true, 30513 clobberFlags: true, 30514 faultOnNilArg0: true, 30515 hasSideEffects: true, 30516 reg: regInfo{ 30517 inputs: []inputInfo{ 30518 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30519 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30520 }, 30521 outputs: []outputInfo{ 30522 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30523 }, 30524 }, 30525 }, 30526 { 30527 name: "LoweredAtomicAdd64", 30528 argLen: 3, 30529 resultNotInArgs: true, 30530 clobberFlags: true, 30531 faultOnNilArg0: true, 30532 hasSideEffects: true, 30533 reg: regInfo{ 30534 inputs: []inputInfo{ 30535 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30536 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30537 }, 30538 outputs: []outputInfo{ 30539 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30540 }, 30541 }, 30542 }, 30543 { 30544 name: "LoweredAtomicExchange32", 30545 argLen: 3, 30546 resultNotInArgs: true, 30547 clobberFlags: true, 30548 faultOnNilArg0: true, 30549 hasSideEffects: true, 30550 reg: regInfo{ 30551 inputs: []inputInfo{ 30552 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30553 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30554 }, 30555 outputs: []outputInfo{ 30556 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30557 }, 30558 }, 30559 }, 30560 { 30561 name: "LoweredAtomicExchange64", 30562 argLen: 3, 30563 resultNotInArgs: true, 30564 clobberFlags: true, 30565 faultOnNilArg0: true, 30566 hasSideEffects: true, 30567 reg: regInfo{ 30568 inputs: []inputInfo{ 30569 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30570 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30571 }, 30572 outputs: []outputInfo{ 30573 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30574 }, 30575 }, 30576 }, 30577 { 30578 name: "LoweredAtomicCas64", 30579 auxType: auxInt64, 30580 argLen: 4, 30581 resultNotInArgs: true, 30582 clobberFlags: true, 30583 faultOnNilArg0: true, 30584 hasSideEffects: true, 30585 reg: regInfo{ 30586 inputs: []inputInfo{ 30587 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30588 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30589 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30590 }, 30591 outputs: []outputInfo{ 30592 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30593 }, 30594 }, 30595 }, 30596 { 30597 name: "LoweredAtomicCas32", 30598 auxType: auxInt64, 30599 argLen: 4, 30600 resultNotInArgs: true, 30601 clobberFlags: true, 30602 faultOnNilArg0: true, 30603 hasSideEffects: true, 30604 reg: regInfo{ 30605 inputs: []inputInfo{ 30606 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30607 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30608 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30609 }, 30610 outputs: []outputInfo{ 30611 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30612 }, 30613 }, 30614 }, 30615 { 30616 name: "LoweredAtomicAnd8", 30617 argLen: 3, 30618 faultOnNilArg0: true, 30619 hasSideEffects: true, 30620 asm: ppc64.AAND, 30621 reg: regInfo{ 30622 inputs: []inputInfo{ 30623 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30624 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30625 }, 30626 }, 30627 }, 30628 { 30629 name: "LoweredAtomicAnd32", 30630 argLen: 3, 30631 faultOnNilArg0: true, 30632 hasSideEffects: true, 30633 asm: ppc64.AAND, 30634 reg: regInfo{ 30635 inputs: []inputInfo{ 30636 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30637 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30638 }, 30639 }, 30640 }, 30641 { 30642 name: "LoweredAtomicOr8", 30643 argLen: 3, 30644 faultOnNilArg0: true, 30645 hasSideEffects: true, 30646 asm: ppc64.AOR, 30647 reg: regInfo{ 30648 inputs: []inputInfo{ 30649 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30650 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30651 }, 30652 }, 30653 }, 30654 { 30655 name: "LoweredAtomicOr32", 30656 argLen: 3, 30657 faultOnNilArg0: true, 30658 hasSideEffects: true, 30659 asm: ppc64.AOR, 30660 reg: regInfo{ 30661 inputs: []inputInfo{ 30662 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30663 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 30664 }, 30665 }, 30666 }, 30667 { 30668 name: "LoweredWB", 30669 auxType: auxSym, 30670 argLen: 3, 30671 clobberFlags: true, 30672 symEffect: SymNone, 30673 reg: regInfo{ 30674 inputs: []inputInfo{ 30675 {0, 1048576}, // R20 30676 {1, 2097152}, // R21 30677 }, 30678 clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER 30679 }, 30680 }, 30681 { 30682 name: "LoweredPubBarrier", 30683 argLen: 1, 30684 hasSideEffects: true, 30685 asm: ppc64.ALWSYNC, 30686 reg: regInfo{}, 30687 }, 30688 { 30689 name: "LoweredPanicBoundsA", 30690 auxType: auxInt64, 30691 argLen: 3, 30692 call: true, 30693 reg: regInfo{ 30694 inputs: []inputInfo{ 30695 {0, 32}, // R5 30696 {1, 64}, // R6 30697 }, 30698 }, 30699 }, 30700 { 30701 name: "LoweredPanicBoundsB", 30702 auxType: auxInt64, 30703 argLen: 3, 30704 call: true, 30705 reg: regInfo{ 30706 inputs: []inputInfo{ 30707 {0, 16}, // R4 30708 {1, 32}, // R5 30709 }, 30710 }, 30711 }, 30712 { 30713 name: "LoweredPanicBoundsC", 30714 auxType: auxInt64, 30715 argLen: 3, 30716 call: true, 30717 reg: regInfo{ 30718 inputs: []inputInfo{ 30719 {0, 8}, // R3 30720 {1, 16}, // R4 30721 }, 30722 }, 30723 }, 30724 { 30725 name: "InvertFlags", 30726 argLen: 1, 30727 reg: regInfo{}, 30728 }, 30729 { 30730 name: "FlagEQ", 30731 argLen: 0, 30732 reg: regInfo{}, 30733 }, 30734 { 30735 name: "FlagLT", 30736 argLen: 0, 30737 reg: regInfo{}, 30738 }, 30739 { 30740 name: "FlagGT", 30741 argLen: 0, 30742 reg: regInfo{}, 30743 }, 30744 30745 { 30746 name: "ADD", 30747 argLen: 2, 30748 commutative: true, 30749 asm: riscv.AADD, 30750 reg: regInfo{ 30751 inputs: []inputInfo{ 30752 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30753 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30754 }, 30755 outputs: []outputInfo{ 30756 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30757 }, 30758 }, 30759 }, 30760 { 30761 name: "ADDI", 30762 auxType: auxInt64, 30763 argLen: 1, 30764 asm: riscv.AADDI, 30765 reg: regInfo{ 30766 inputs: []inputInfo{ 30767 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 30768 }, 30769 outputs: []outputInfo{ 30770 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30771 }, 30772 }, 30773 }, 30774 { 30775 name: "ADDIW", 30776 auxType: auxInt64, 30777 argLen: 1, 30778 asm: riscv.AADDIW, 30779 reg: regInfo{ 30780 inputs: []inputInfo{ 30781 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30782 }, 30783 outputs: []outputInfo{ 30784 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30785 }, 30786 }, 30787 }, 30788 { 30789 name: "NEG", 30790 argLen: 1, 30791 asm: riscv.ANEG, 30792 reg: regInfo{ 30793 inputs: []inputInfo{ 30794 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30795 }, 30796 outputs: []outputInfo{ 30797 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30798 }, 30799 }, 30800 }, 30801 { 30802 name: "NEGW", 30803 argLen: 1, 30804 asm: riscv.ANEGW, 30805 reg: regInfo{ 30806 inputs: []inputInfo{ 30807 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30808 }, 30809 outputs: []outputInfo{ 30810 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30811 }, 30812 }, 30813 }, 30814 { 30815 name: "SUB", 30816 argLen: 2, 30817 asm: riscv.ASUB, 30818 reg: regInfo{ 30819 inputs: []inputInfo{ 30820 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30821 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30822 }, 30823 outputs: []outputInfo{ 30824 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30825 }, 30826 }, 30827 }, 30828 { 30829 name: "SUBW", 30830 argLen: 2, 30831 asm: riscv.ASUBW, 30832 reg: regInfo{ 30833 inputs: []inputInfo{ 30834 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30835 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30836 }, 30837 outputs: []outputInfo{ 30838 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30839 }, 30840 }, 30841 }, 30842 { 30843 name: "MUL", 30844 argLen: 2, 30845 commutative: true, 30846 asm: riscv.AMUL, 30847 reg: regInfo{ 30848 inputs: []inputInfo{ 30849 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30850 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30851 }, 30852 outputs: []outputInfo{ 30853 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30854 }, 30855 }, 30856 }, 30857 { 30858 name: "MULW", 30859 argLen: 2, 30860 commutative: true, 30861 asm: riscv.AMULW, 30862 reg: regInfo{ 30863 inputs: []inputInfo{ 30864 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30865 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30866 }, 30867 outputs: []outputInfo{ 30868 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30869 }, 30870 }, 30871 }, 30872 { 30873 name: "MULH", 30874 argLen: 2, 30875 commutative: true, 30876 asm: riscv.AMULH, 30877 reg: regInfo{ 30878 inputs: []inputInfo{ 30879 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30880 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30881 }, 30882 outputs: []outputInfo{ 30883 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30884 }, 30885 }, 30886 }, 30887 { 30888 name: "MULHU", 30889 argLen: 2, 30890 commutative: true, 30891 asm: riscv.AMULHU, 30892 reg: regInfo{ 30893 inputs: []inputInfo{ 30894 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30895 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30896 }, 30897 outputs: []outputInfo{ 30898 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30899 }, 30900 }, 30901 }, 30902 { 30903 name: "LoweredMuluhilo", 30904 argLen: 2, 30905 resultNotInArgs: true, 30906 reg: regInfo{ 30907 inputs: []inputInfo{ 30908 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30909 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30910 }, 30911 outputs: []outputInfo{ 30912 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30913 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30914 }, 30915 }, 30916 }, 30917 { 30918 name: "LoweredMuluover", 30919 argLen: 2, 30920 resultNotInArgs: true, 30921 reg: regInfo{ 30922 inputs: []inputInfo{ 30923 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30924 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30925 }, 30926 outputs: []outputInfo{ 30927 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30928 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30929 }, 30930 }, 30931 }, 30932 { 30933 name: "DIV", 30934 argLen: 2, 30935 asm: riscv.ADIV, 30936 reg: regInfo{ 30937 inputs: []inputInfo{ 30938 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30939 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30940 }, 30941 outputs: []outputInfo{ 30942 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30943 }, 30944 }, 30945 }, 30946 { 30947 name: "DIVU", 30948 argLen: 2, 30949 asm: riscv.ADIVU, 30950 reg: regInfo{ 30951 inputs: []inputInfo{ 30952 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30953 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30954 }, 30955 outputs: []outputInfo{ 30956 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30957 }, 30958 }, 30959 }, 30960 { 30961 name: "DIVW", 30962 argLen: 2, 30963 asm: riscv.ADIVW, 30964 reg: regInfo{ 30965 inputs: []inputInfo{ 30966 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30967 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30968 }, 30969 outputs: []outputInfo{ 30970 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30971 }, 30972 }, 30973 }, 30974 { 30975 name: "DIVUW", 30976 argLen: 2, 30977 asm: riscv.ADIVUW, 30978 reg: regInfo{ 30979 inputs: []inputInfo{ 30980 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30981 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30982 }, 30983 outputs: []outputInfo{ 30984 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30985 }, 30986 }, 30987 }, 30988 { 30989 name: "REM", 30990 argLen: 2, 30991 asm: riscv.AREM, 30992 reg: regInfo{ 30993 inputs: []inputInfo{ 30994 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30995 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30996 }, 30997 outputs: []outputInfo{ 30998 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 30999 }, 31000 }, 31001 }, 31002 { 31003 name: "REMU", 31004 argLen: 2, 31005 asm: riscv.AREMU, 31006 reg: regInfo{ 31007 inputs: []inputInfo{ 31008 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31009 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31010 }, 31011 outputs: []outputInfo{ 31012 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31013 }, 31014 }, 31015 }, 31016 { 31017 name: "REMW", 31018 argLen: 2, 31019 asm: riscv.AREMW, 31020 reg: regInfo{ 31021 inputs: []inputInfo{ 31022 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31023 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31024 }, 31025 outputs: []outputInfo{ 31026 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31027 }, 31028 }, 31029 }, 31030 { 31031 name: "REMUW", 31032 argLen: 2, 31033 asm: riscv.AREMUW, 31034 reg: regInfo{ 31035 inputs: []inputInfo{ 31036 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31037 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31038 }, 31039 outputs: []outputInfo{ 31040 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31041 }, 31042 }, 31043 }, 31044 { 31045 name: "MOVaddr", 31046 auxType: auxSymOff, 31047 argLen: 1, 31048 rematerializeable: true, 31049 symEffect: SymRdWr, 31050 asm: riscv.AMOV, 31051 reg: regInfo{ 31052 inputs: []inputInfo{ 31053 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31054 }, 31055 outputs: []outputInfo{ 31056 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31057 }, 31058 }, 31059 }, 31060 { 31061 name: "MOVDconst", 31062 auxType: auxInt64, 31063 argLen: 0, 31064 rematerializeable: true, 31065 asm: riscv.AMOV, 31066 reg: regInfo{ 31067 outputs: []outputInfo{ 31068 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31069 }, 31070 }, 31071 }, 31072 { 31073 name: "MOVBload", 31074 auxType: auxSymOff, 31075 argLen: 2, 31076 faultOnNilArg0: true, 31077 symEffect: SymRead, 31078 asm: riscv.AMOVB, 31079 reg: regInfo{ 31080 inputs: []inputInfo{ 31081 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31082 }, 31083 outputs: []outputInfo{ 31084 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31085 }, 31086 }, 31087 }, 31088 { 31089 name: "MOVHload", 31090 auxType: auxSymOff, 31091 argLen: 2, 31092 faultOnNilArg0: true, 31093 symEffect: SymRead, 31094 asm: riscv.AMOVH, 31095 reg: regInfo{ 31096 inputs: []inputInfo{ 31097 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31098 }, 31099 outputs: []outputInfo{ 31100 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31101 }, 31102 }, 31103 }, 31104 { 31105 name: "MOVWload", 31106 auxType: auxSymOff, 31107 argLen: 2, 31108 faultOnNilArg0: true, 31109 symEffect: SymRead, 31110 asm: riscv.AMOVW, 31111 reg: regInfo{ 31112 inputs: []inputInfo{ 31113 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31114 }, 31115 outputs: []outputInfo{ 31116 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31117 }, 31118 }, 31119 }, 31120 { 31121 name: "MOVDload", 31122 auxType: auxSymOff, 31123 argLen: 2, 31124 faultOnNilArg0: true, 31125 symEffect: SymRead, 31126 asm: riscv.AMOV, 31127 reg: regInfo{ 31128 inputs: []inputInfo{ 31129 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31130 }, 31131 outputs: []outputInfo{ 31132 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31133 }, 31134 }, 31135 }, 31136 { 31137 name: "MOVBUload", 31138 auxType: auxSymOff, 31139 argLen: 2, 31140 faultOnNilArg0: true, 31141 symEffect: SymRead, 31142 asm: riscv.AMOVBU, 31143 reg: regInfo{ 31144 inputs: []inputInfo{ 31145 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31146 }, 31147 outputs: []outputInfo{ 31148 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31149 }, 31150 }, 31151 }, 31152 { 31153 name: "MOVHUload", 31154 auxType: auxSymOff, 31155 argLen: 2, 31156 faultOnNilArg0: true, 31157 symEffect: SymRead, 31158 asm: riscv.AMOVHU, 31159 reg: regInfo{ 31160 inputs: []inputInfo{ 31161 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31162 }, 31163 outputs: []outputInfo{ 31164 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31165 }, 31166 }, 31167 }, 31168 { 31169 name: "MOVWUload", 31170 auxType: auxSymOff, 31171 argLen: 2, 31172 faultOnNilArg0: true, 31173 symEffect: SymRead, 31174 asm: riscv.AMOVWU, 31175 reg: regInfo{ 31176 inputs: []inputInfo{ 31177 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31178 }, 31179 outputs: []outputInfo{ 31180 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31181 }, 31182 }, 31183 }, 31184 { 31185 name: "MOVBstore", 31186 auxType: auxSymOff, 31187 argLen: 3, 31188 faultOnNilArg0: true, 31189 symEffect: SymWrite, 31190 asm: riscv.AMOVB, 31191 reg: regInfo{ 31192 inputs: []inputInfo{ 31193 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31194 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31195 }, 31196 }, 31197 }, 31198 { 31199 name: "MOVHstore", 31200 auxType: auxSymOff, 31201 argLen: 3, 31202 faultOnNilArg0: true, 31203 symEffect: SymWrite, 31204 asm: riscv.AMOVH, 31205 reg: regInfo{ 31206 inputs: []inputInfo{ 31207 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31208 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31209 }, 31210 }, 31211 }, 31212 { 31213 name: "MOVWstore", 31214 auxType: auxSymOff, 31215 argLen: 3, 31216 faultOnNilArg0: true, 31217 symEffect: SymWrite, 31218 asm: riscv.AMOVW, 31219 reg: regInfo{ 31220 inputs: []inputInfo{ 31221 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31222 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31223 }, 31224 }, 31225 }, 31226 { 31227 name: "MOVDstore", 31228 auxType: auxSymOff, 31229 argLen: 3, 31230 faultOnNilArg0: true, 31231 symEffect: SymWrite, 31232 asm: riscv.AMOV, 31233 reg: regInfo{ 31234 inputs: []inputInfo{ 31235 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31236 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31237 }, 31238 }, 31239 }, 31240 { 31241 name: "MOVBstorezero", 31242 auxType: auxSymOff, 31243 argLen: 2, 31244 faultOnNilArg0: true, 31245 symEffect: SymWrite, 31246 asm: riscv.AMOVB, 31247 reg: regInfo{ 31248 inputs: []inputInfo{ 31249 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31250 }, 31251 }, 31252 }, 31253 { 31254 name: "MOVHstorezero", 31255 auxType: auxSymOff, 31256 argLen: 2, 31257 faultOnNilArg0: true, 31258 symEffect: SymWrite, 31259 asm: riscv.AMOVH, 31260 reg: regInfo{ 31261 inputs: []inputInfo{ 31262 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31263 }, 31264 }, 31265 }, 31266 { 31267 name: "MOVWstorezero", 31268 auxType: auxSymOff, 31269 argLen: 2, 31270 faultOnNilArg0: true, 31271 symEffect: SymWrite, 31272 asm: riscv.AMOVW, 31273 reg: regInfo{ 31274 inputs: []inputInfo{ 31275 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31276 }, 31277 }, 31278 }, 31279 { 31280 name: "MOVDstorezero", 31281 auxType: auxSymOff, 31282 argLen: 2, 31283 faultOnNilArg0: true, 31284 symEffect: SymWrite, 31285 asm: riscv.AMOV, 31286 reg: regInfo{ 31287 inputs: []inputInfo{ 31288 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31289 }, 31290 }, 31291 }, 31292 { 31293 name: "MOVBreg", 31294 argLen: 1, 31295 asm: riscv.AMOVB, 31296 reg: regInfo{ 31297 inputs: []inputInfo{ 31298 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31299 }, 31300 outputs: []outputInfo{ 31301 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31302 }, 31303 }, 31304 }, 31305 { 31306 name: "MOVHreg", 31307 argLen: 1, 31308 asm: riscv.AMOVH, 31309 reg: regInfo{ 31310 inputs: []inputInfo{ 31311 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31312 }, 31313 outputs: []outputInfo{ 31314 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31315 }, 31316 }, 31317 }, 31318 { 31319 name: "MOVWreg", 31320 argLen: 1, 31321 asm: riscv.AMOVW, 31322 reg: regInfo{ 31323 inputs: []inputInfo{ 31324 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31325 }, 31326 outputs: []outputInfo{ 31327 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31328 }, 31329 }, 31330 }, 31331 { 31332 name: "MOVDreg", 31333 argLen: 1, 31334 asm: riscv.AMOV, 31335 reg: regInfo{ 31336 inputs: []inputInfo{ 31337 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31338 }, 31339 outputs: []outputInfo{ 31340 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31341 }, 31342 }, 31343 }, 31344 { 31345 name: "MOVBUreg", 31346 argLen: 1, 31347 asm: riscv.AMOVBU, 31348 reg: regInfo{ 31349 inputs: []inputInfo{ 31350 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31351 }, 31352 outputs: []outputInfo{ 31353 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31354 }, 31355 }, 31356 }, 31357 { 31358 name: "MOVHUreg", 31359 argLen: 1, 31360 asm: riscv.AMOVHU, 31361 reg: regInfo{ 31362 inputs: []inputInfo{ 31363 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31364 }, 31365 outputs: []outputInfo{ 31366 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31367 }, 31368 }, 31369 }, 31370 { 31371 name: "MOVWUreg", 31372 argLen: 1, 31373 asm: riscv.AMOVWU, 31374 reg: regInfo{ 31375 inputs: []inputInfo{ 31376 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31377 }, 31378 outputs: []outputInfo{ 31379 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31380 }, 31381 }, 31382 }, 31383 { 31384 name: "MOVDnop", 31385 argLen: 1, 31386 resultInArg0: true, 31387 reg: regInfo{ 31388 inputs: []inputInfo{ 31389 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31390 }, 31391 outputs: []outputInfo{ 31392 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31393 }, 31394 }, 31395 }, 31396 { 31397 name: "SLL", 31398 argLen: 2, 31399 asm: riscv.ASLL, 31400 reg: regInfo{ 31401 inputs: []inputInfo{ 31402 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31403 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31404 }, 31405 outputs: []outputInfo{ 31406 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31407 }, 31408 }, 31409 }, 31410 { 31411 name: "SRA", 31412 argLen: 2, 31413 asm: riscv.ASRA, 31414 reg: regInfo{ 31415 inputs: []inputInfo{ 31416 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31417 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31418 }, 31419 outputs: []outputInfo{ 31420 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31421 }, 31422 }, 31423 }, 31424 { 31425 name: "SRL", 31426 argLen: 2, 31427 asm: riscv.ASRL, 31428 reg: regInfo{ 31429 inputs: []inputInfo{ 31430 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31431 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31432 }, 31433 outputs: []outputInfo{ 31434 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31435 }, 31436 }, 31437 }, 31438 { 31439 name: "SLLI", 31440 auxType: auxInt64, 31441 argLen: 1, 31442 asm: riscv.ASLLI, 31443 reg: regInfo{ 31444 inputs: []inputInfo{ 31445 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31446 }, 31447 outputs: []outputInfo{ 31448 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31449 }, 31450 }, 31451 }, 31452 { 31453 name: "SRAI", 31454 auxType: auxInt64, 31455 argLen: 1, 31456 asm: riscv.ASRAI, 31457 reg: regInfo{ 31458 inputs: []inputInfo{ 31459 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31460 }, 31461 outputs: []outputInfo{ 31462 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31463 }, 31464 }, 31465 }, 31466 { 31467 name: "SRLI", 31468 auxType: auxInt64, 31469 argLen: 1, 31470 asm: riscv.ASRLI, 31471 reg: regInfo{ 31472 inputs: []inputInfo{ 31473 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31474 }, 31475 outputs: []outputInfo{ 31476 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31477 }, 31478 }, 31479 }, 31480 { 31481 name: "XOR", 31482 argLen: 2, 31483 commutative: true, 31484 asm: riscv.AXOR, 31485 reg: regInfo{ 31486 inputs: []inputInfo{ 31487 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31488 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31489 }, 31490 outputs: []outputInfo{ 31491 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31492 }, 31493 }, 31494 }, 31495 { 31496 name: "XORI", 31497 auxType: auxInt64, 31498 argLen: 1, 31499 asm: riscv.AXORI, 31500 reg: regInfo{ 31501 inputs: []inputInfo{ 31502 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31503 }, 31504 outputs: []outputInfo{ 31505 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31506 }, 31507 }, 31508 }, 31509 { 31510 name: "OR", 31511 argLen: 2, 31512 commutative: true, 31513 asm: riscv.AOR, 31514 reg: regInfo{ 31515 inputs: []inputInfo{ 31516 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31517 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31518 }, 31519 outputs: []outputInfo{ 31520 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31521 }, 31522 }, 31523 }, 31524 { 31525 name: "ORI", 31526 auxType: auxInt64, 31527 argLen: 1, 31528 asm: riscv.AORI, 31529 reg: regInfo{ 31530 inputs: []inputInfo{ 31531 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31532 }, 31533 outputs: []outputInfo{ 31534 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31535 }, 31536 }, 31537 }, 31538 { 31539 name: "AND", 31540 argLen: 2, 31541 commutative: true, 31542 asm: riscv.AAND, 31543 reg: regInfo{ 31544 inputs: []inputInfo{ 31545 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31546 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31547 }, 31548 outputs: []outputInfo{ 31549 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31550 }, 31551 }, 31552 }, 31553 { 31554 name: "ANDI", 31555 auxType: auxInt64, 31556 argLen: 1, 31557 asm: riscv.AANDI, 31558 reg: regInfo{ 31559 inputs: []inputInfo{ 31560 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31561 }, 31562 outputs: []outputInfo{ 31563 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31564 }, 31565 }, 31566 }, 31567 { 31568 name: "NOT", 31569 argLen: 1, 31570 asm: riscv.ANOT, 31571 reg: regInfo{ 31572 inputs: []inputInfo{ 31573 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31574 }, 31575 outputs: []outputInfo{ 31576 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31577 }, 31578 }, 31579 }, 31580 { 31581 name: "SEQZ", 31582 argLen: 1, 31583 asm: riscv.ASEQZ, 31584 reg: regInfo{ 31585 inputs: []inputInfo{ 31586 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31587 }, 31588 outputs: []outputInfo{ 31589 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31590 }, 31591 }, 31592 }, 31593 { 31594 name: "SNEZ", 31595 argLen: 1, 31596 asm: riscv.ASNEZ, 31597 reg: regInfo{ 31598 inputs: []inputInfo{ 31599 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31600 }, 31601 outputs: []outputInfo{ 31602 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31603 }, 31604 }, 31605 }, 31606 { 31607 name: "SLT", 31608 argLen: 2, 31609 asm: riscv.ASLT, 31610 reg: regInfo{ 31611 inputs: []inputInfo{ 31612 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31613 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31614 }, 31615 outputs: []outputInfo{ 31616 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31617 }, 31618 }, 31619 }, 31620 { 31621 name: "SLTI", 31622 auxType: auxInt64, 31623 argLen: 1, 31624 asm: riscv.ASLTI, 31625 reg: regInfo{ 31626 inputs: []inputInfo{ 31627 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31628 }, 31629 outputs: []outputInfo{ 31630 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31631 }, 31632 }, 31633 }, 31634 { 31635 name: "SLTU", 31636 argLen: 2, 31637 asm: riscv.ASLTU, 31638 reg: regInfo{ 31639 inputs: []inputInfo{ 31640 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31641 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31642 }, 31643 outputs: []outputInfo{ 31644 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31645 }, 31646 }, 31647 }, 31648 { 31649 name: "SLTIU", 31650 auxType: auxInt64, 31651 argLen: 1, 31652 asm: riscv.ASLTIU, 31653 reg: regInfo{ 31654 inputs: []inputInfo{ 31655 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31656 }, 31657 outputs: []outputInfo{ 31658 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31659 }, 31660 }, 31661 }, 31662 { 31663 name: "MOVconvert", 31664 argLen: 2, 31665 asm: riscv.AMOV, 31666 reg: regInfo{ 31667 inputs: []inputInfo{ 31668 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31669 }, 31670 outputs: []outputInfo{ 31671 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31672 }, 31673 }, 31674 }, 31675 { 31676 name: "CALLstatic", 31677 auxType: auxCallOff, 31678 argLen: -1, 31679 call: true, 31680 reg: regInfo{ 31681 clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 31682 }, 31683 }, 31684 { 31685 name: "CALLtail", 31686 auxType: auxCallOff, 31687 argLen: -1, 31688 call: true, 31689 tailCall: true, 31690 reg: regInfo{ 31691 clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 31692 }, 31693 }, 31694 { 31695 name: "CALLclosure", 31696 auxType: auxCallOff, 31697 argLen: -1, 31698 call: true, 31699 reg: regInfo{ 31700 inputs: []inputInfo{ 31701 {1, 33554432}, // X26 31702 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31703 }, 31704 clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 31705 }, 31706 }, 31707 { 31708 name: "CALLinter", 31709 auxType: auxCallOff, 31710 argLen: -1, 31711 call: true, 31712 reg: regInfo{ 31713 inputs: []inputInfo{ 31714 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31715 }, 31716 clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 31717 }, 31718 }, 31719 { 31720 name: "DUFFZERO", 31721 auxType: auxInt64, 31722 argLen: 2, 31723 faultOnNilArg0: true, 31724 reg: regInfo{ 31725 inputs: []inputInfo{ 31726 {0, 16777216}, // X25 31727 }, 31728 clobbers: 16777216, // X25 31729 }, 31730 }, 31731 { 31732 name: "DUFFCOPY", 31733 auxType: auxInt64, 31734 argLen: 3, 31735 faultOnNilArg0: true, 31736 faultOnNilArg1: true, 31737 reg: regInfo{ 31738 inputs: []inputInfo{ 31739 {0, 16777216}, // X25 31740 {1, 8388608}, // X24 31741 }, 31742 clobbers: 25165824, // X24 X25 31743 }, 31744 }, 31745 { 31746 name: "LoweredZero", 31747 auxType: auxInt64, 31748 argLen: 3, 31749 faultOnNilArg0: true, 31750 reg: regInfo{ 31751 inputs: []inputInfo{ 31752 {0, 16}, // X5 31753 {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31754 }, 31755 clobbers: 16, // X5 31756 }, 31757 }, 31758 { 31759 name: "LoweredMove", 31760 auxType: auxInt64, 31761 argLen: 4, 31762 faultOnNilArg0: true, 31763 faultOnNilArg1: true, 31764 reg: regInfo{ 31765 inputs: []inputInfo{ 31766 {0, 16}, // X5 31767 {1, 32}, // X6 31768 {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31769 }, 31770 clobbers: 112, // X5 X6 X7 31771 }, 31772 }, 31773 { 31774 name: "LoweredAtomicLoad8", 31775 argLen: 2, 31776 faultOnNilArg0: true, 31777 reg: regInfo{ 31778 inputs: []inputInfo{ 31779 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31780 }, 31781 outputs: []outputInfo{ 31782 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31783 }, 31784 }, 31785 }, 31786 { 31787 name: "LoweredAtomicLoad32", 31788 argLen: 2, 31789 faultOnNilArg0: true, 31790 reg: regInfo{ 31791 inputs: []inputInfo{ 31792 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31793 }, 31794 outputs: []outputInfo{ 31795 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31796 }, 31797 }, 31798 }, 31799 { 31800 name: "LoweredAtomicLoad64", 31801 argLen: 2, 31802 faultOnNilArg0: true, 31803 reg: regInfo{ 31804 inputs: []inputInfo{ 31805 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31806 }, 31807 outputs: []outputInfo{ 31808 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31809 }, 31810 }, 31811 }, 31812 { 31813 name: "LoweredAtomicStore8", 31814 argLen: 3, 31815 faultOnNilArg0: true, 31816 hasSideEffects: true, 31817 reg: regInfo{ 31818 inputs: []inputInfo{ 31819 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31820 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31821 }, 31822 }, 31823 }, 31824 { 31825 name: "LoweredAtomicStore32", 31826 argLen: 3, 31827 faultOnNilArg0: true, 31828 hasSideEffects: true, 31829 reg: regInfo{ 31830 inputs: []inputInfo{ 31831 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31832 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31833 }, 31834 }, 31835 }, 31836 { 31837 name: "LoweredAtomicStore64", 31838 argLen: 3, 31839 faultOnNilArg0: true, 31840 hasSideEffects: true, 31841 reg: regInfo{ 31842 inputs: []inputInfo{ 31843 {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31844 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 31845 }, 31846 }, 31847 }, 31848 { 31849 name: "LoweredAtomicExchange32", 31850 argLen: 3, 31851 resultNotInArgs: true, 31852 faultOnNilArg0: true, 31853 hasSideEffects: true, 31854 reg: regInfo{ 31855 inputs: []inputInfo{ 31856 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31857 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31858 }, 31859 outputs: []outputInfo{ 31860 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31861 }, 31862 }, 31863 }, 31864 { 31865 name: "LoweredAtomicExchange64", 31866 argLen: 3, 31867 resultNotInArgs: true, 31868 faultOnNilArg0: true, 31869 hasSideEffects: true, 31870 reg: regInfo{ 31871 inputs: []inputInfo{ 31872 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31873 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31874 }, 31875 outputs: []outputInfo{ 31876 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31877 }, 31878 }, 31879 }, 31880 { 31881 name: "LoweredAtomicAdd32", 31882 argLen: 3, 31883 resultNotInArgs: true, 31884 faultOnNilArg0: true, 31885 hasSideEffects: true, 31886 unsafePoint: true, 31887 reg: regInfo{ 31888 inputs: []inputInfo{ 31889 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31890 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31891 }, 31892 outputs: []outputInfo{ 31893 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31894 }, 31895 }, 31896 }, 31897 { 31898 name: "LoweredAtomicAdd64", 31899 argLen: 3, 31900 resultNotInArgs: true, 31901 faultOnNilArg0: true, 31902 hasSideEffects: true, 31903 unsafePoint: true, 31904 reg: regInfo{ 31905 inputs: []inputInfo{ 31906 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31907 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31908 }, 31909 outputs: []outputInfo{ 31910 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31911 }, 31912 }, 31913 }, 31914 { 31915 name: "LoweredAtomicCas32", 31916 argLen: 4, 31917 resultNotInArgs: true, 31918 faultOnNilArg0: true, 31919 hasSideEffects: true, 31920 unsafePoint: true, 31921 reg: regInfo{ 31922 inputs: []inputInfo{ 31923 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31924 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31925 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31926 }, 31927 outputs: []outputInfo{ 31928 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31929 }, 31930 }, 31931 }, 31932 { 31933 name: "LoweredAtomicCas64", 31934 argLen: 4, 31935 resultNotInArgs: true, 31936 faultOnNilArg0: true, 31937 hasSideEffects: true, 31938 unsafePoint: true, 31939 reg: regInfo{ 31940 inputs: []inputInfo{ 31941 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31942 {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31943 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31944 }, 31945 outputs: []outputInfo{ 31946 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31947 }, 31948 }, 31949 }, 31950 { 31951 name: "LoweredAtomicAnd32", 31952 argLen: 3, 31953 faultOnNilArg0: true, 31954 hasSideEffects: true, 31955 asm: riscv.AAMOANDW, 31956 reg: regInfo{ 31957 inputs: []inputInfo{ 31958 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31959 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31960 }, 31961 }, 31962 }, 31963 { 31964 name: "LoweredAtomicOr32", 31965 argLen: 3, 31966 faultOnNilArg0: true, 31967 hasSideEffects: true, 31968 asm: riscv.AAMOORW, 31969 reg: regInfo{ 31970 inputs: []inputInfo{ 31971 {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 31972 {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB 31973 }, 31974 }, 31975 }, 31976 { 31977 name: "LoweredNilCheck", 31978 argLen: 2, 31979 nilCheck: true, 31980 faultOnNilArg0: true, 31981 reg: regInfo{ 31982 inputs: []inputInfo{ 31983 {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 31984 }, 31985 }, 31986 }, 31987 { 31988 name: "LoweredGetClosurePtr", 31989 argLen: 0, 31990 reg: regInfo{ 31991 outputs: []outputInfo{ 31992 {0, 33554432}, // X26 31993 }, 31994 }, 31995 }, 31996 { 31997 name: "LoweredGetCallerSP", 31998 argLen: 0, 31999 rematerializeable: true, 32000 reg: regInfo{ 32001 outputs: []outputInfo{ 32002 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32003 }, 32004 }, 32005 }, 32006 { 32007 name: "LoweredGetCallerPC", 32008 argLen: 0, 32009 rematerializeable: true, 32010 reg: regInfo{ 32011 outputs: []outputInfo{ 32012 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32013 }, 32014 }, 32015 }, 32016 { 32017 name: "LoweredWB", 32018 auxType: auxSym, 32019 argLen: 3, 32020 clobberFlags: true, 32021 symEffect: SymNone, 32022 reg: regInfo{ 32023 inputs: []inputInfo{ 32024 {0, 16}, // X5 32025 {1, 32}, // X6 32026 }, 32027 clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32028 }, 32029 }, 32030 { 32031 name: "LoweredPanicBoundsA", 32032 auxType: auxInt64, 32033 argLen: 3, 32034 call: true, 32035 reg: regInfo{ 32036 inputs: []inputInfo{ 32037 {0, 64}, // X7 32038 {1, 134217728}, // X28 32039 }, 32040 }, 32041 }, 32042 { 32043 name: "LoweredPanicBoundsB", 32044 auxType: auxInt64, 32045 argLen: 3, 32046 call: true, 32047 reg: regInfo{ 32048 inputs: []inputInfo{ 32049 {0, 32}, // X6 32050 {1, 64}, // X7 32051 }, 32052 }, 32053 }, 32054 { 32055 name: "LoweredPanicBoundsC", 32056 auxType: auxInt64, 32057 argLen: 3, 32058 call: true, 32059 reg: regInfo{ 32060 inputs: []inputInfo{ 32061 {0, 16}, // X5 32062 {1, 32}, // X6 32063 }, 32064 }, 32065 }, 32066 { 32067 name: "FADDS", 32068 argLen: 2, 32069 commutative: true, 32070 asm: riscv.AFADDS, 32071 reg: regInfo{ 32072 inputs: []inputInfo{ 32073 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32074 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32075 }, 32076 outputs: []outputInfo{ 32077 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32078 }, 32079 }, 32080 }, 32081 { 32082 name: "FSUBS", 32083 argLen: 2, 32084 asm: riscv.AFSUBS, 32085 reg: regInfo{ 32086 inputs: []inputInfo{ 32087 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32088 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32089 }, 32090 outputs: []outputInfo{ 32091 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32092 }, 32093 }, 32094 }, 32095 { 32096 name: "FMULS", 32097 argLen: 2, 32098 commutative: true, 32099 asm: riscv.AFMULS, 32100 reg: regInfo{ 32101 inputs: []inputInfo{ 32102 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32103 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32104 }, 32105 outputs: []outputInfo{ 32106 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32107 }, 32108 }, 32109 }, 32110 { 32111 name: "FDIVS", 32112 argLen: 2, 32113 asm: riscv.AFDIVS, 32114 reg: regInfo{ 32115 inputs: []inputInfo{ 32116 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32117 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32118 }, 32119 outputs: []outputInfo{ 32120 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32121 }, 32122 }, 32123 }, 32124 { 32125 name: "FSQRTS", 32126 argLen: 1, 32127 asm: riscv.AFSQRTS, 32128 reg: regInfo{ 32129 inputs: []inputInfo{ 32130 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32131 }, 32132 outputs: []outputInfo{ 32133 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32134 }, 32135 }, 32136 }, 32137 { 32138 name: "FNEGS", 32139 argLen: 1, 32140 asm: riscv.AFNEGS, 32141 reg: regInfo{ 32142 inputs: []inputInfo{ 32143 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32144 }, 32145 outputs: []outputInfo{ 32146 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32147 }, 32148 }, 32149 }, 32150 { 32151 name: "FMVSX", 32152 argLen: 1, 32153 asm: riscv.AFMVSX, 32154 reg: regInfo{ 32155 inputs: []inputInfo{ 32156 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32157 }, 32158 outputs: []outputInfo{ 32159 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32160 }, 32161 }, 32162 }, 32163 { 32164 name: "FCVTSW", 32165 argLen: 1, 32166 asm: riscv.AFCVTSW, 32167 reg: regInfo{ 32168 inputs: []inputInfo{ 32169 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32170 }, 32171 outputs: []outputInfo{ 32172 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32173 }, 32174 }, 32175 }, 32176 { 32177 name: "FCVTSL", 32178 argLen: 1, 32179 asm: riscv.AFCVTSL, 32180 reg: regInfo{ 32181 inputs: []inputInfo{ 32182 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32183 }, 32184 outputs: []outputInfo{ 32185 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32186 }, 32187 }, 32188 }, 32189 { 32190 name: "FCVTWS", 32191 argLen: 1, 32192 asm: riscv.AFCVTWS, 32193 reg: regInfo{ 32194 inputs: []inputInfo{ 32195 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32196 }, 32197 outputs: []outputInfo{ 32198 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32199 }, 32200 }, 32201 }, 32202 { 32203 name: "FCVTLS", 32204 argLen: 1, 32205 asm: riscv.AFCVTLS, 32206 reg: regInfo{ 32207 inputs: []inputInfo{ 32208 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32209 }, 32210 outputs: []outputInfo{ 32211 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32212 }, 32213 }, 32214 }, 32215 { 32216 name: "FMOVWload", 32217 auxType: auxSymOff, 32218 argLen: 2, 32219 faultOnNilArg0: true, 32220 symEffect: SymRead, 32221 asm: riscv.AMOVF, 32222 reg: regInfo{ 32223 inputs: []inputInfo{ 32224 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 32225 }, 32226 outputs: []outputInfo{ 32227 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32228 }, 32229 }, 32230 }, 32231 { 32232 name: "FMOVWstore", 32233 auxType: auxSymOff, 32234 argLen: 3, 32235 faultOnNilArg0: true, 32236 symEffect: SymWrite, 32237 asm: riscv.AMOVF, 32238 reg: regInfo{ 32239 inputs: []inputInfo{ 32240 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 32241 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32242 }, 32243 }, 32244 }, 32245 { 32246 name: "FEQS", 32247 argLen: 2, 32248 commutative: true, 32249 asm: riscv.AFEQS, 32250 reg: regInfo{ 32251 inputs: []inputInfo{ 32252 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32253 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32254 }, 32255 outputs: []outputInfo{ 32256 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32257 }, 32258 }, 32259 }, 32260 { 32261 name: "FNES", 32262 argLen: 2, 32263 commutative: true, 32264 asm: riscv.AFNES, 32265 reg: regInfo{ 32266 inputs: []inputInfo{ 32267 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32268 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32269 }, 32270 outputs: []outputInfo{ 32271 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32272 }, 32273 }, 32274 }, 32275 { 32276 name: "FLTS", 32277 argLen: 2, 32278 asm: riscv.AFLTS, 32279 reg: regInfo{ 32280 inputs: []inputInfo{ 32281 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32282 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32283 }, 32284 outputs: []outputInfo{ 32285 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32286 }, 32287 }, 32288 }, 32289 { 32290 name: "FLES", 32291 argLen: 2, 32292 asm: riscv.AFLES, 32293 reg: regInfo{ 32294 inputs: []inputInfo{ 32295 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32296 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32297 }, 32298 outputs: []outputInfo{ 32299 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32300 }, 32301 }, 32302 }, 32303 { 32304 name: "FADDD", 32305 argLen: 2, 32306 commutative: true, 32307 asm: riscv.AFADDD, 32308 reg: regInfo{ 32309 inputs: []inputInfo{ 32310 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32311 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32312 }, 32313 outputs: []outputInfo{ 32314 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32315 }, 32316 }, 32317 }, 32318 { 32319 name: "FSUBD", 32320 argLen: 2, 32321 asm: riscv.AFSUBD, 32322 reg: regInfo{ 32323 inputs: []inputInfo{ 32324 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32325 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32326 }, 32327 outputs: []outputInfo{ 32328 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32329 }, 32330 }, 32331 }, 32332 { 32333 name: "FMULD", 32334 argLen: 2, 32335 commutative: true, 32336 asm: riscv.AFMULD, 32337 reg: regInfo{ 32338 inputs: []inputInfo{ 32339 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32340 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32341 }, 32342 outputs: []outputInfo{ 32343 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32344 }, 32345 }, 32346 }, 32347 { 32348 name: "FDIVD", 32349 argLen: 2, 32350 asm: riscv.AFDIVD, 32351 reg: regInfo{ 32352 inputs: []inputInfo{ 32353 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32354 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32355 }, 32356 outputs: []outputInfo{ 32357 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32358 }, 32359 }, 32360 }, 32361 { 32362 name: "FMADDD", 32363 argLen: 3, 32364 commutative: true, 32365 asm: riscv.AFMADDD, 32366 reg: regInfo{ 32367 inputs: []inputInfo{ 32368 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32369 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32370 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32371 }, 32372 outputs: []outputInfo{ 32373 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32374 }, 32375 }, 32376 }, 32377 { 32378 name: "FMSUBD", 32379 argLen: 3, 32380 commutative: true, 32381 asm: riscv.AFMSUBD, 32382 reg: regInfo{ 32383 inputs: []inputInfo{ 32384 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32385 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32386 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32387 }, 32388 outputs: []outputInfo{ 32389 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32390 }, 32391 }, 32392 }, 32393 { 32394 name: "FNMADDD", 32395 argLen: 3, 32396 commutative: true, 32397 asm: riscv.AFNMADDD, 32398 reg: regInfo{ 32399 inputs: []inputInfo{ 32400 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32401 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32402 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32403 }, 32404 outputs: []outputInfo{ 32405 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32406 }, 32407 }, 32408 }, 32409 { 32410 name: "FNMSUBD", 32411 argLen: 3, 32412 commutative: true, 32413 asm: riscv.AFNMSUBD, 32414 reg: regInfo{ 32415 inputs: []inputInfo{ 32416 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32417 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32418 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32419 }, 32420 outputs: []outputInfo{ 32421 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32422 }, 32423 }, 32424 }, 32425 { 32426 name: "FSQRTD", 32427 argLen: 1, 32428 asm: riscv.AFSQRTD, 32429 reg: regInfo{ 32430 inputs: []inputInfo{ 32431 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32432 }, 32433 outputs: []outputInfo{ 32434 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32435 }, 32436 }, 32437 }, 32438 { 32439 name: "FNEGD", 32440 argLen: 1, 32441 asm: riscv.AFNEGD, 32442 reg: regInfo{ 32443 inputs: []inputInfo{ 32444 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32445 }, 32446 outputs: []outputInfo{ 32447 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32448 }, 32449 }, 32450 }, 32451 { 32452 name: "FABSD", 32453 argLen: 1, 32454 asm: riscv.AFABSD, 32455 reg: regInfo{ 32456 inputs: []inputInfo{ 32457 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32458 }, 32459 outputs: []outputInfo{ 32460 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32461 }, 32462 }, 32463 }, 32464 { 32465 name: "FSGNJD", 32466 argLen: 2, 32467 asm: riscv.AFSGNJD, 32468 reg: regInfo{ 32469 inputs: []inputInfo{ 32470 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32471 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32472 }, 32473 outputs: []outputInfo{ 32474 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32475 }, 32476 }, 32477 }, 32478 { 32479 name: "FMVDX", 32480 argLen: 1, 32481 asm: riscv.AFMVDX, 32482 reg: regInfo{ 32483 inputs: []inputInfo{ 32484 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32485 }, 32486 outputs: []outputInfo{ 32487 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32488 }, 32489 }, 32490 }, 32491 { 32492 name: "FCVTDW", 32493 argLen: 1, 32494 asm: riscv.AFCVTDW, 32495 reg: regInfo{ 32496 inputs: []inputInfo{ 32497 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32498 }, 32499 outputs: []outputInfo{ 32500 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32501 }, 32502 }, 32503 }, 32504 { 32505 name: "FCVTDL", 32506 argLen: 1, 32507 asm: riscv.AFCVTDL, 32508 reg: regInfo{ 32509 inputs: []inputInfo{ 32510 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32511 }, 32512 outputs: []outputInfo{ 32513 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32514 }, 32515 }, 32516 }, 32517 { 32518 name: "FCVTWD", 32519 argLen: 1, 32520 asm: riscv.AFCVTWD, 32521 reg: regInfo{ 32522 inputs: []inputInfo{ 32523 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32524 }, 32525 outputs: []outputInfo{ 32526 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32527 }, 32528 }, 32529 }, 32530 { 32531 name: "FCVTLD", 32532 argLen: 1, 32533 asm: riscv.AFCVTLD, 32534 reg: regInfo{ 32535 inputs: []inputInfo{ 32536 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32537 }, 32538 outputs: []outputInfo{ 32539 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32540 }, 32541 }, 32542 }, 32543 { 32544 name: "FCVTDS", 32545 argLen: 1, 32546 asm: riscv.AFCVTDS, 32547 reg: regInfo{ 32548 inputs: []inputInfo{ 32549 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32550 }, 32551 outputs: []outputInfo{ 32552 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32553 }, 32554 }, 32555 }, 32556 { 32557 name: "FCVTSD", 32558 argLen: 1, 32559 asm: riscv.AFCVTSD, 32560 reg: regInfo{ 32561 inputs: []inputInfo{ 32562 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32563 }, 32564 outputs: []outputInfo{ 32565 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32566 }, 32567 }, 32568 }, 32569 { 32570 name: "FMOVDload", 32571 auxType: auxSymOff, 32572 argLen: 2, 32573 faultOnNilArg0: true, 32574 symEffect: SymRead, 32575 asm: riscv.AMOVD, 32576 reg: regInfo{ 32577 inputs: []inputInfo{ 32578 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 32579 }, 32580 outputs: []outputInfo{ 32581 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32582 }, 32583 }, 32584 }, 32585 { 32586 name: "FMOVDstore", 32587 auxType: auxSymOff, 32588 argLen: 3, 32589 faultOnNilArg0: true, 32590 symEffect: SymWrite, 32591 asm: riscv.AMOVD, 32592 reg: regInfo{ 32593 inputs: []inputInfo{ 32594 {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB 32595 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32596 }, 32597 }, 32598 }, 32599 { 32600 name: "FEQD", 32601 argLen: 2, 32602 commutative: true, 32603 asm: riscv.AFEQD, 32604 reg: regInfo{ 32605 inputs: []inputInfo{ 32606 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32607 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32608 }, 32609 outputs: []outputInfo{ 32610 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32611 }, 32612 }, 32613 }, 32614 { 32615 name: "FNED", 32616 argLen: 2, 32617 commutative: true, 32618 asm: riscv.AFNED, 32619 reg: regInfo{ 32620 inputs: []inputInfo{ 32621 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32622 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32623 }, 32624 outputs: []outputInfo{ 32625 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32626 }, 32627 }, 32628 }, 32629 { 32630 name: "FLTD", 32631 argLen: 2, 32632 asm: riscv.AFLTD, 32633 reg: regInfo{ 32634 inputs: []inputInfo{ 32635 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32636 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32637 }, 32638 outputs: []outputInfo{ 32639 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32640 }, 32641 }, 32642 }, 32643 { 32644 name: "FLED", 32645 argLen: 2, 32646 asm: riscv.AFLED, 32647 reg: regInfo{ 32648 inputs: []inputInfo{ 32649 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32650 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 32651 }, 32652 outputs: []outputInfo{ 32653 {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 32654 }, 32655 }, 32656 }, 32657 32658 { 32659 name: "FADDS", 32660 argLen: 2, 32661 commutative: true, 32662 resultInArg0: true, 32663 asm: s390x.AFADDS, 32664 reg: regInfo{ 32665 inputs: []inputInfo{ 32666 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32667 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32668 }, 32669 outputs: []outputInfo{ 32670 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32671 }, 32672 }, 32673 }, 32674 { 32675 name: "FADD", 32676 argLen: 2, 32677 commutative: true, 32678 resultInArg0: true, 32679 asm: s390x.AFADD, 32680 reg: regInfo{ 32681 inputs: []inputInfo{ 32682 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32683 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32684 }, 32685 outputs: []outputInfo{ 32686 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32687 }, 32688 }, 32689 }, 32690 { 32691 name: "FSUBS", 32692 argLen: 2, 32693 resultInArg0: true, 32694 asm: s390x.AFSUBS, 32695 reg: regInfo{ 32696 inputs: []inputInfo{ 32697 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32698 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32699 }, 32700 outputs: []outputInfo{ 32701 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32702 }, 32703 }, 32704 }, 32705 { 32706 name: "FSUB", 32707 argLen: 2, 32708 resultInArg0: true, 32709 asm: s390x.AFSUB, 32710 reg: regInfo{ 32711 inputs: []inputInfo{ 32712 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32713 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32714 }, 32715 outputs: []outputInfo{ 32716 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32717 }, 32718 }, 32719 }, 32720 { 32721 name: "FMULS", 32722 argLen: 2, 32723 commutative: true, 32724 resultInArg0: true, 32725 asm: s390x.AFMULS, 32726 reg: regInfo{ 32727 inputs: []inputInfo{ 32728 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32729 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32730 }, 32731 outputs: []outputInfo{ 32732 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32733 }, 32734 }, 32735 }, 32736 { 32737 name: "FMUL", 32738 argLen: 2, 32739 commutative: true, 32740 resultInArg0: true, 32741 asm: s390x.AFMUL, 32742 reg: regInfo{ 32743 inputs: []inputInfo{ 32744 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32745 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32746 }, 32747 outputs: []outputInfo{ 32748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32749 }, 32750 }, 32751 }, 32752 { 32753 name: "FDIVS", 32754 argLen: 2, 32755 resultInArg0: true, 32756 asm: s390x.AFDIVS, 32757 reg: regInfo{ 32758 inputs: []inputInfo{ 32759 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32760 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32761 }, 32762 outputs: []outputInfo{ 32763 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32764 }, 32765 }, 32766 }, 32767 { 32768 name: "FDIV", 32769 argLen: 2, 32770 resultInArg0: true, 32771 asm: s390x.AFDIV, 32772 reg: regInfo{ 32773 inputs: []inputInfo{ 32774 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32775 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32776 }, 32777 outputs: []outputInfo{ 32778 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32779 }, 32780 }, 32781 }, 32782 { 32783 name: "FNEGS", 32784 argLen: 1, 32785 clobberFlags: true, 32786 asm: s390x.AFNEGS, 32787 reg: regInfo{ 32788 inputs: []inputInfo{ 32789 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32790 }, 32791 outputs: []outputInfo{ 32792 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32793 }, 32794 }, 32795 }, 32796 { 32797 name: "FNEG", 32798 argLen: 1, 32799 clobberFlags: true, 32800 asm: s390x.AFNEG, 32801 reg: regInfo{ 32802 inputs: []inputInfo{ 32803 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32804 }, 32805 outputs: []outputInfo{ 32806 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32807 }, 32808 }, 32809 }, 32810 { 32811 name: "FMADDS", 32812 argLen: 3, 32813 resultInArg0: true, 32814 asm: s390x.AFMADDS, 32815 reg: regInfo{ 32816 inputs: []inputInfo{ 32817 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32818 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32819 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32820 }, 32821 outputs: []outputInfo{ 32822 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32823 }, 32824 }, 32825 }, 32826 { 32827 name: "FMADD", 32828 argLen: 3, 32829 resultInArg0: true, 32830 asm: s390x.AFMADD, 32831 reg: regInfo{ 32832 inputs: []inputInfo{ 32833 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32834 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32835 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32836 }, 32837 outputs: []outputInfo{ 32838 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32839 }, 32840 }, 32841 }, 32842 { 32843 name: "FMSUBS", 32844 argLen: 3, 32845 resultInArg0: true, 32846 asm: s390x.AFMSUBS, 32847 reg: regInfo{ 32848 inputs: []inputInfo{ 32849 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32850 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32851 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32852 }, 32853 outputs: []outputInfo{ 32854 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32855 }, 32856 }, 32857 }, 32858 { 32859 name: "FMSUB", 32860 argLen: 3, 32861 resultInArg0: true, 32862 asm: s390x.AFMSUB, 32863 reg: regInfo{ 32864 inputs: []inputInfo{ 32865 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32866 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32867 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32868 }, 32869 outputs: []outputInfo{ 32870 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32871 }, 32872 }, 32873 }, 32874 { 32875 name: "LPDFR", 32876 argLen: 1, 32877 asm: s390x.ALPDFR, 32878 reg: regInfo{ 32879 inputs: []inputInfo{ 32880 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32881 }, 32882 outputs: []outputInfo{ 32883 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32884 }, 32885 }, 32886 }, 32887 { 32888 name: "LNDFR", 32889 argLen: 1, 32890 asm: s390x.ALNDFR, 32891 reg: regInfo{ 32892 inputs: []inputInfo{ 32893 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32894 }, 32895 outputs: []outputInfo{ 32896 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32897 }, 32898 }, 32899 }, 32900 { 32901 name: "CPSDR", 32902 argLen: 2, 32903 asm: s390x.ACPSDR, 32904 reg: regInfo{ 32905 inputs: []inputInfo{ 32906 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32907 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32908 }, 32909 outputs: []outputInfo{ 32910 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32911 }, 32912 }, 32913 }, 32914 { 32915 name: "FIDBR", 32916 auxType: auxInt8, 32917 argLen: 1, 32918 asm: s390x.AFIDBR, 32919 reg: regInfo{ 32920 inputs: []inputInfo{ 32921 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32922 }, 32923 outputs: []outputInfo{ 32924 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32925 }, 32926 }, 32927 }, 32928 { 32929 name: "FMOVSload", 32930 auxType: auxSymOff, 32931 argLen: 2, 32932 faultOnNilArg0: true, 32933 symEffect: SymRead, 32934 asm: s390x.AFMOVS, 32935 reg: regInfo{ 32936 inputs: []inputInfo{ 32937 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 32938 }, 32939 outputs: []outputInfo{ 32940 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32941 }, 32942 }, 32943 }, 32944 { 32945 name: "FMOVDload", 32946 auxType: auxSymOff, 32947 argLen: 2, 32948 faultOnNilArg0: true, 32949 symEffect: SymRead, 32950 asm: s390x.AFMOVD, 32951 reg: regInfo{ 32952 inputs: []inputInfo{ 32953 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 32954 }, 32955 outputs: []outputInfo{ 32956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32957 }, 32958 }, 32959 }, 32960 { 32961 name: "FMOVSconst", 32962 auxType: auxFloat32, 32963 argLen: 0, 32964 rematerializeable: true, 32965 asm: s390x.AFMOVS, 32966 reg: regInfo{ 32967 outputs: []outputInfo{ 32968 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32969 }, 32970 }, 32971 }, 32972 { 32973 name: "FMOVDconst", 32974 auxType: auxFloat64, 32975 argLen: 0, 32976 rematerializeable: true, 32977 asm: s390x.AFMOVD, 32978 reg: regInfo{ 32979 outputs: []outputInfo{ 32980 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32981 }, 32982 }, 32983 }, 32984 { 32985 name: "FMOVSloadidx", 32986 auxType: auxSymOff, 32987 argLen: 3, 32988 symEffect: SymRead, 32989 asm: s390x.AFMOVS, 32990 reg: regInfo{ 32991 inputs: []inputInfo{ 32992 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 32993 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 32994 }, 32995 outputs: []outputInfo{ 32996 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 32997 }, 32998 }, 32999 }, 33000 { 33001 name: "FMOVDloadidx", 33002 auxType: auxSymOff, 33003 argLen: 3, 33004 symEffect: SymRead, 33005 asm: s390x.AFMOVD, 33006 reg: regInfo{ 33007 inputs: []inputInfo{ 33008 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33009 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33010 }, 33011 outputs: []outputInfo{ 33012 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 33013 }, 33014 }, 33015 }, 33016 { 33017 name: "FMOVSstore", 33018 auxType: auxSymOff, 33019 argLen: 3, 33020 faultOnNilArg0: true, 33021 symEffect: SymWrite, 33022 asm: s390x.AFMOVS, 33023 reg: regInfo{ 33024 inputs: []inputInfo{ 33025 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 33026 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 33027 }, 33028 }, 33029 }, 33030 { 33031 name: "FMOVDstore", 33032 auxType: auxSymOff, 33033 argLen: 3, 33034 faultOnNilArg0: true, 33035 symEffect: SymWrite, 33036 asm: s390x.AFMOVD, 33037 reg: regInfo{ 33038 inputs: []inputInfo{ 33039 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 33040 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 33041 }, 33042 }, 33043 }, 33044 { 33045 name: "FMOVSstoreidx", 33046 auxType: auxSymOff, 33047 argLen: 4, 33048 symEffect: SymWrite, 33049 asm: s390x.AFMOVS, 33050 reg: regInfo{ 33051 inputs: []inputInfo{ 33052 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33053 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33054 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 33055 }, 33056 }, 33057 }, 33058 { 33059 name: "FMOVDstoreidx", 33060 auxType: auxSymOff, 33061 argLen: 4, 33062 symEffect: SymWrite, 33063 asm: s390x.AFMOVD, 33064 reg: regInfo{ 33065 inputs: []inputInfo{ 33066 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33067 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33068 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 33069 }, 33070 }, 33071 }, 33072 { 33073 name: "ADD", 33074 argLen: 2, 33075 commutative: true, 33076 clobberFlags: true, 33077 asm: s390x.AADD, 33078 reg: regInfo{ 33079 inputs: []inputInfo{ 33080 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33081 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33082 }, 33083 outputs: []outputInfo{ 33084 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33085 }, 33086 }, 33087 }, 33088 { 33089 name: "ADDW", 33090 argLen: 2, 33091 commutative: true, 33092 clobberFlags: true, 33093 asm: s390x.AADDW, 33094 reg: regInfo{ 33095 inputs: []inputInfo{ 33096 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33097 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33098 }, 33099 outputs: []outputInfo{ 33100 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33101 }, 33102 }, 33103 }, 33104 { 33105 name: "ADDconst", 33106 auxType: auxInt32, 33107 argLen: 1, 33108 clobberFlags: true, 33109 asm: s390x.AADD, 33110 reg: regInfo{ 33111 inputs: []inputInfo{ 33112 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33113 }, 33114 outputs: []outputInfo{ 33115 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33116 }, 33117 }, 33118 }, 33119 { 33120 name: "ADDWconst", 33121 auxType: auxInt32, 33122 argLen: 1, 33123 clobberFlags: true, 33124 asm: s390x.AADDW, 33125 reg: regInfo{ 33126 inputs: []inputInfo{ 33127 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33128 }, 33129 outputs: []outputInfo{ 33130 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33131 }, 33132 }, 33133 }, 33134 { 33135 name: "ADDload", 33136 auxType: auxSymOff, 33137 argLen: 3, 33138 resultInArg0: true, 33139 clobberFlags: true, 33140 faultOnNilArg1: true, 33141 symEffect: SymRead, 33142 asm: s390x.AADD, 33143 reg: regInfo{ 33144 inputs: []inputInfo{ 33145 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33146 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33147 }, 33148 outputs: []outputInfo{ 33149 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33150 }, 33151 }, 33152 }, 33153 { 33154 name: "ADDWload", 33155 auxType: auxSymOff, 33156 argLen: 3, 33157 resultInArg0: true, 33158 clobberFlags: true, 33159 faultOnNilArg1: true, 33160 symEffect: SymRead, 33161 asm: s390x.AADDW, 33162 reg: regInfo{ 33163 inputs: []inputInfo{ 33164 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33165 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33166 }, 33167 outputs: []outputInfo{ 33168 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33169 }, 33170 }, 33171 }, 33172 { 33173 name: "SUB", 33174 argLen: 2, 33175 clobberFlags: true, 33176 asm: s390x.ASUB, 33177 reg: regInfo{ 33178 inputs: []inputInfo{ 33179 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33180 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33181 }, 33182 outputs: []outputInfo{ 33183 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33184 }, 33185 }, 33186 }, 33187 { 33188 name: "SUBW", 33189 argLen: 2, 33190 clobberFlags: true, 33191 asm: s390x.ASUBW, 33192 reg: regInfo{ 33193 inputs: []inputInfo{ 33194 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33195 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33196 }, 33197 outputs: []outputInfo{ 33198 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33199 }, 33200 }, 33201 }, 33202 { 33203 name: "SUBconst", 33204 auxType: auxInt32, 33205 argLen: 1, 33206 resultInArg0: true, 33207 clobberFlags: true, 33208 asm: s390x.ASUB, 33209 reg: regInfo{ 33210 inputs: []inputInfo{ 33211 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33212 }, 33213 outputs: []outputInfo{ 33214 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33215 }, 33216 }, 33217 }, 33218 { 33219 name: "SUBWconst", 33220 auxType: auxInt32, 33221 argLen: 1, 33222 resultInArg0: true, 33223 clobberFlags: true, 33224 asm: s390x.ASUBW, 33225 reg: regInfo{ 33226 inputs: []inputInfo{ 33227 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33228 }, 33229 outputs: []outputInfo{ 33230 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33231 }, 33232 }, 33233 }, 33234 { 33235 name: "SUBload", 33236 auxType: auxSymOff, 33237 argLen: 3, 33238 resultInArg0: true, 33239 clobberFlags: true, 33240 faultOnNilArg1: true, 33241 symEffect: SymRead, 33242 asm: s390x.ASUB, 33243 reg: regInfo{ 33244 inputs: []inputInfo{ 33245 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33246 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33247 }, 33248 outputs: []outputInfo{ 33249 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33250 }, 33251 }, 33252 }, 33253 { 33254 name: "SUBWload", 33255 auxType: auxSymOff, 33256 argLen: 3, 33257 resultInArg0: true, 33258 clobberFlags: true, 33259 faultOnNilArg1: true, 33260 symEffect: SymRead, 33261 asm: s390x.ASUBW, 33262 reg: regInfo{ 33263 inputs: []inputInfo{ 33264 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33265 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33266 }, 33267 outputs: []outputInfo{ 33268 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33269 }, 33270 }, 33271 }, 33272 { 33273 name: "MULLD", 33274 argLen: 2, 33275 commutative: true, 33276 resultInArg0: true, 33277 clobberFlags: true, 33278 asm: s390x.AMULLD, 33279 reg: regInfo{ 33280 inputs: []inputInfo{ 33281 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33282 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33283 }, 33284 outputs: []outputInfo{ 33285 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33286 }, 33287 }, 33288 }, 33289 { 33290 name: "MULLW", 33291 argLen: 2, 33292 commutative: true, 33293 resultInArg0: true, 33294 clobberFlags: true, 33295 asm: s390x.AMULLW, 33296 reg: regInfo{ 33297 inputs: []inputInfo{ 33298 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33299 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33300 }, 33301 outputs: []outputInfo{ 33302 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33303 }, 33304 }, 33305 }, 33306 { 33307 name: "MULLDconst", 33308 auxType: auxInt32, 33309 argLen: 1, 33310 resultInArg0: true, 33311 clobberFlags: true, 33312 asm: s390x.AMULLD, 33313 reg: regInfo{ 33314 inputs: []inputInfo{ 33315 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33316 }, 33317 outputs: []outputInfo{ 33318 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33319 }, 33320 }, 33321 }, 33322 { 33323 name: "MULLWconst", 33324 auxType: auxInt32, 33325 argLen: 1, 33326 resultInArg0: true, 33327 clobberFlags: true, 33328 asm: s390x.AMULLW, 33329 reg: regInfo{ 33330 inputs: []inputInfo{ 33331 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33332 }, 33333 outputs: []outputInfo{ 33334 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33335 }, 33336 }, 33337 }, 33338 { 33339 name: "MULLDload", 33340 auxType: auxSymOff, 33341 argLen: 3, 33342 resultInArg0: true, 33343 clobberFlags: true, 33344 faultOnNilArg1: true, 33345 symEffect: SymRead, 33346 asm: s390x.AMULLD, 33347 reg: regInfo{ 33348 inputs: []inputInfo{ 33349 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33350 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33351 }, 33352 outputs: []outputInfo{ 33353 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33354 }, 33355 }, 33356 }, 33357 { 33358 name: "MULLWload", 33359 auxType: auxSymOff, 33360 argLen: 3, 33361 resultInArg0: true, 33362 clobberFlags: true, 33363 faultOnNilArg1: true, 33364 symEffect: SymRead, 33365 asm: s390x.AMULLW, 33366 reg: regInfo{ 33367 inputs: []inputInfo{ 33368 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33369 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33370 }, 33371 outputs: []outputInfo{ 33372 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33373 }, 33374 }, 33375 }, 33376 { 33377 name: "MULHD", 33378 argLen: 2, 33379 commutative: true, 33380 resultInArg0: true, 33381 clobberFlags: true, 33382 asm: s390x.AMULHD, 33383 reg: regInfo{ 33384 inputs: []inputInfo{ 33385 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33386 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33387 }, 33388 clobbers: 2048, // R11 33389 outputs: []outputInfo{ 33390 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33391 }, 33392 }, 33393 }, 33394 { 33395 name: "MULHDU", 33396 argLen: 2, 33397 commutative: true, 33398 resultInArg0: true, 33399 clobberFlags: true, 33400 asm: s390x.AMULHDU, 33401 reg: regInfo{ 33402 inputs: []inputInfo{ 33403 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33404 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33405 }, 33406 clobbers: 2048, // R11 33407 outputs: []outputInfo{ 33408 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33409 }, 33410 }, 33411 }, 33412 { 33413 name: "DIVD", 33414 argLen: 2, 33415 resultInArg0: true, 33416 clobberFlags: true, 33417 asm: s390x.ADIVD, 33418 reg: regInfo{ 33419 inputs: []inputInfo{ 33420 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33421 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33422 }, 33423 clobbers: 2048, // R11 33424 outputs: []outputInfo{ 33425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33426 }, 33427 }, 33428 }, 33429 { 33430 name: "DIVW", 33431 argLen: 2, 33432 resultInArg0: true, 33433 clobberFlags: true, 33434 asm: s390x.ADIVW, 33435 reg: regInfo{ 33436 inputs: []inputInfo{ 33437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33438 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33439 }, 33440 clobbers: 2048, // R11 33441 outputs: []outputInfo{ 33442 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33443 }, 33444 }, 33445 }, 33446 { 33447 name: "DIVDU", 33448 argLen: 2, 33449 resultInArg0: true, 33450 clobberFlags: true, 33451 asm: s390x.ADIVDU, 33452 reg: regInfo{ 33453 inputs: []inputInfo{ 33454 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33455 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33456 }, 33457 clobbers: 2048, // R11 33458 outputs: []outputInfo{ 33459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33460 }, 33461 }, 33462 }, 33463 { 33464 name: "DIVWU", 33465 argLen: 2, 33466 resultInArg0: true, 33467 clobberFlags: true, 33468 asm: s390x.ADIVWU, 33469 reg: regInfo{ 33470 inputs: []inputInfo{ 33471 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33472 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33473 }, 33474 clobbers: 2048, // R11 33475 outputs: []outputInfo{ 33476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33477 }, 33478 }, 33479 }, 33480 { 33481 name: "MODD", 33482 argLen: 2, 33483 resultInArg0: true, 33484 clobberFlags: true, 33485 asm: s390x.AMODD, 33486 reg: regInfo{ 33487 inputs: []inputInfo{ 33488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33489 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33490 }, 33491 clobbers: 2048, // R11 33492 outputs: []outputInfo{ 33493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33494 }, 33495 }, 33496 }, 33497 { 33498 name: "MODW", 33499 argLen: 2, 33500 resultInArg0: true, 33501 clobberFlags: true, 33502 asm: s390x.AMODW, 33503 reg: regInfo{ 33504 inputs: []inputInfo{ 33505 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33506 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33507 }, 33508 clobbers: 2048, // R11 33509 outputs: []outputInfo{ 33510 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33511 }, 33512 }, 33513 }, 33514 { 33515 name: "MODDU", 33516 argLen: 2, 33517 resultInArg0: true, 33518 clobberFlags: true, 33519 asm: s390x.AMODDU, 33520 reg: regInfo{ 33521 inputs: []inputInfo{ 33522 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33523 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33524 }, 33525 clobbers: 2048, // R11 33526 outputs: []outputInfo{ 33527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33528 }, 33529 }, 33530 }, 33531 { 33532 name: "MODWU", 33533 argLen: 2, 33534 resultInArg0: true, 33535 clobberFlags: true, 33536 asm: s390x.AMODWU, 33537 reg: regInfo{ 33538 inputs: []inputInfo{ 33539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33540 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33541 }, 33542 clobbers: 2048, // R11 33543 outputs: []outputInfo{ 33544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 33545 }, 33546 }, 33547 }, 33548 { 33549 name: "AND", 33550 argLen: 2, 33551 commutative: true, 33552 clobberFlags: true, 33553 asm: s390x.AAND, 33554 reg: regInfo{ 33555 inputs: []inputInfo{ 33556 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33557 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33558 }, 33559 outputs: []outputInfo{ 33560 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33561 }, 33562 }, 33563 }, 33564 { 33565 name: "ANDW", 33566 argLen: 2, 33567 commutative: true, 33568 clobberFlags: true, 33569 asm: s390x.AANDW, 33570 reg: regInfo{ 33571 inputs: []inputInfo{ 33572 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33573 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33574 }, 33575 outputs: []outputInfo{ 33576 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33577 }, 33578 }, 33579 }, 33580 { 33581 name: "ANDconst", 33582 auxType: auxInt64, 33583 argLen: 1, 33584 resultInArg0: true, 33585 clobberFlags: true, 33586 asm: s390x.AAND, 33587 reg: regInfo{ 33588 inputs: []inputInfo{ 33589 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33590 }, 33591 outputs: []outputInfo{ 33592 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33593 }, 33594 }, 33595 }, 33596 { 33597 name: "ANDWconst", 33598 auxType: auxInt32, 33599 argLen: 1, 33600 resultInArg0: true, 33601 clobberFlags: true, 33602 asm: s390x.AANDW, 33603 reg: regInfo{ 33604 inputs: []inputInfo{ 33605 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33606 }, 33607 outputs: []outputInfo{ 33608 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33609 }, 33610 }, 33611 }, 33612 { 33613 name: "ANDload", 33614 auxType: auxSymOff, 33615 argLen: 3, 33616 resultInArg0: true, 33617 clobberFlags: true, 33618 faultOnNilArg1: true, 33619 symEffect: SymRead, 33620 asm: s390x.AAND, 33621 reg: regInfo{ 33622 inputs: []inputInfo{ 33623 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33624 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33625 }, 33626 outputs: []outputInfo{ 33627 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33628 }, 33629 }, 33630 }, 33631 { 33632 name: "ANDWload", 33633 auxType: auxSymOff, 33634 argLen: 3, 33635 resultInArg0: true, 33636 clobberFlags: true, 33637 faultOnNilArg1: true, 33638 symEffect: SymRead, 33639 asm: s390x.AANDW, 33640 reg: regInfo{ 33641 inputs: []inputInfo{ 33642 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33643 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33644 }, 33645 outputs: []outputInfo{ 33646 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33647 }, 33648 }, 33649 }, 33650 { 33651 name: "OR", 33652 argLen: 2, 33653 commutative: true, 33654 clobberFlags: true, 33655 asm: s390x.AOR, 33656 reg: regInfo{ 33657 inputs: []inputInfo{ 33658 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33659 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33660 }, 33661 outputs: []outputInfo{ 33662 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33663 }, 33664 }, 33665 }, 33666 { 33667 name: "ORW", 33668 argLen: 2, 33669 commutative: true, 33670 clobberFlags: true, 33671 asm: s390x.AORW, 33672 reg: regInfo{ 33673 inputs: []inputInfo{ 33674 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33675 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33676 }, 33677 outputs: []outputInfo{ 33678 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33679 }, 33680 }, 33681 }, 33682 { 33683 name: "ORconst", 33684 auxType: auxInt64, 33685 argLen: 1, 33686 resultInArg0: true, 33687 clobberFlags: true, 33688 asm: s390x.AOR, 33689 reg: regInfo{ 33690 inputs: []inputInfo{ 33691 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33692 }, 33693 outputs: []outputInfo{ 33694 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33695 }, 33696 }, 33697 }, 33698 { 33699 name: "ORWconst", 33700 auxType: auxInt32, 33701 argLen: 1, 33702 resultInArg0: true, 33703 clobberFlags: true, 33704 asm: s390x.AORW, 33705 reg: regInfo{ 33706 inputs: []inputInfo{ 33707 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33708 }, 33709 outputs: []outputInfo{ 33710 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33711 }, 33712 }, 33713 }, 33714 { 33715 name: "ORload", 33716 auxType: auxSymOff, 33717 argLen: 3, 33718 resultInArg0: true, 33719 clobberFlags: true, 33720 faultOnNilArg1: true, 33721 symEffect: SymRead, 33722 asm: s390x.AOR, 33723 reg: regInfo{ 33724 inputs: []inputInfo{ 33725 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33726 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33727 }, 33728 outputs: []outputInfo{ 33729 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33730 }, 33731 }, 33732 }, 33733 { 33734 name: "ORWload", 33735 auxType: auxSymOff, 33736 argLen: 3, 33737 resultInArg0: true, 33738 clobberFlags: true, 33739 faultOnNilArg1: true, 33740 symEffect: SymRead, 33741 asm: s390x.AORW, 33742 reg: regInfo{ 33743 inputs: []inputInfo{ 33744 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33745 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33746 }, 33747 outputs: []outputInfo{ 33748 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33749 }, 33750 }, 33751 }, 33752 { 33753 name: "XOR", 33754 argLen: 2, 33755 commutative: true, 33756 clobberFlags: true, 33757 asm: s390x.AXOR, 33758 reg: regInfo{ 33759 inputs: []inputInfo{ 33760 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33761 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33762 }, 33763 outputs: []outputInfo{ 33764 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33765 }, 33766 }, 33767 }, 33768 { 33769 name: "XORW", 33770 argLen: 2, 33771 commutative: true, 33772 clobberFlags: true, 33773 asm: s390x.AXORW, 33774 reg: regInfo{ 33775 inputs: []inputInfo{ 33776 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33777 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33778 }, 33779 outputs: []outputInfo{ 33780 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33781 }, 33782 }, 33783 }, 33784 { 33785 name: "XORconst", 33786 auxType: auxInt64, 33787 argLen: 1, 33788 resultInArg0: true, 33789 clobberFlags: true, 33790 asm: s390x.AXOR, 33791 reg: regInfo{ 33792 inputs: []inputInfo{ 33793 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33794 }, 33795 outputs: []outputInfo{ 33796 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33797 }, 33798 }, 33799 }, 33800 { 33801 name: "XORWconst", 33802 auxType: auxInt32, 33803 argLen: 1, 33804 resultInArg0: true, 33805 clobberFlags: true, 33806 asm: s390x.AXORW, 33807 reg: regInfo{ 33808 inputs: []inputInfo{ 33809 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33810 }, 33811 outputs: []outputInfo{ 33812 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33813 }, 33814 }, 33815 }, 33816 { 33817 name: "XORload", 33818 auxType: auxSymOff, 33819 argLen: 3, 33820 resultInArg0: true, 33821 clobberFlags: true, 33822 faultOnNilArg1: true, 33823 symEffect: SymRead, 33824 asm: s390x.AXOR, 33825 reg: regInfo{ 33826 inputs: []inputInfo{ 33827 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33828 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33829 }, 33830 outputs: []outputInfo{ 33831 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33832 }, 33833 }, 33834 }, 33835 { 33836 name: "XORWload", 33837 auxType: auxSymOff, 33838 argLen: 3, 33839 resultInArg0: true, 33840 clobberFlags: true, 33841 faultOnNilArg1: true, 33842 symEffect: SymRead, 33843 asm: s390x.AXORW, 33844 reg: regInfo{ 33845 inputs: []inputInfo{ 33846 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33847 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33848 }, 33849 outputs: []outputInfo{ 33850 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33851 }, 33852 }, 33853 }, 33854 { 33855 name: "ADDC", 33856 argLen: 2, 33857 commutative: true, 33858 asm: s390x.AADDC, 33859 reg: regInfo{ 33860 inputs: []inputInfo{ 33861 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33862 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33863 }, 33864 outputs: []outputInfo{ 33865 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33866 }, 33867 }, 33868 }, 33869 { 33870 name: "ADDCconst", 33871 auxType: auxInt16, 33872 argLen: 1, 33873 asm: s390x.AADDC, 33874 reg: regInfo{ 33875 inputs: []inputInfo{ 33876 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33877 }, 33878 outputs: []outputInfo{ 33879 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33880 }, 33881 }, 33882 }, 33883 { 33884 name: "ADDE", 33885 argLen: 3, 33886 commutative: true, 33887 resultInArg0: true, 33888 asm: s390x.AADDE, 33889 reg: regInfo{ 33890 inputs: []inputInfo{ 33891 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33892 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33893 }, 33894 outputs: []outputInfo{ 33895 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33896 }, 33897 }, 33898 }, 33899 { 33900 name: "SUBC", 33901 argLen: 2, 33902 asm: s390x.ASUBC, 33903 reg: regInfo{ 33904 inputs: []inputInfo{ 33905 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33906 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33907 }, 33908 outputs: []outputInfo{ 33909 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33910 }, 33911 }, 33912 }, 33913 { 33914 name: "SUBE", 33915 argLen: 3, 33916 resultInArg0: true, 33917 asm: s390x.ASUBE, 33918 reg: regInfo{ 33919 inputs: []inputInfo{ 33920 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33921 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33922 }, 33923 outputs: []outputInfo{ 33924 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 33925 }, 33926 }, 33927 }, 33928 { 33929 name: "CMP", 33930 argLen: 2, 33931 asm: s390x.ACMP, 33932 reg: regInfo{ 33933 inputs: []inputInfo{ 33934 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33935 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33936 }, 33937 }, 33938 }, 33939 { 33940 name: "CMPW", 33941 argLen: 2, 33942 asm: s390x.ACMPW, 33943 reg: regInfo{ 33944 inputs: []inputInfo{ 33945 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33946 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33947 }, 33948 }, 33949 }, 33950 { 33951 name: "CMPU", 33952 argLen: 2, 33953 asm: s390x.ACMPU, 33954 reg: regInfo{ 33955 inputs: []inputInfo{ 33956 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33957 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33958 }, 33959 }, 33960 }, 33961 { 33962 name: "CMPWU", 33963 argLen: 2, 33964 asm: s390x.ACMPWU, 33965 reg: regInfo{ 33966 inputs: []inputInfo{ 33967 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33968 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33969 }, 33970 }, 33971 }, 33972 { 33973 name: "CMPconst", 33974 auxType: auxInt32, 33975 argLen: 1, 33976 asm: s390x.ACMP, 33977 reg: regInfo{ 33978 inputs: []inputInfo{ 33979 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33980 }, 33981 }, 33982 }, 33983 { 33984 name: "CMPWconst", 33985 auxType: auxInt32, 33986 argLen: 1, 33987 asm: s390x.ACMPW, 33988 reg: regInfo{ 33989 inputs: []inputInfo{ 33990 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 33991 }, 33992 }, 33993 }, 33994 { 33995 name: "CMPUconst", 33996 auxType: auxInt32, 33997 argLen: 1, 33998 asm: s390x.ACMPU, 33999 reg: regInfo{ 34000 inputs: []inputInfo{ 34001 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34002 }, 34003 }, 34004 }, 34005 { 34006 name: "CMPWUconst", 34007 auxType: auxInt32, 34008 argLen: 1, 34009 asm: s390x.ACMPWU, 34010 reg: regInfo{ 34011 inputs: []inputInfo{ 34012 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34013 }, 34014 }, 34015 }, 34016 { 34017 name: "FCMPS", 34018 argLen: 2, 34019 asm: s390x.ACEBR, 34020 reg: regInfo{ 34021 inputs: []inputInfo{ 34022 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34023 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34024 }, 34025 }, 34026 }, 34027 { 34028 name: "FCMP", 34029 argLen: 2, 34030 asm: s390x.AFCMPU, 34031 reg: regInfo{ 34032 inputs: []inputInfo{ 34033 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34034 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34035 }, 34036 }, 34037 }, 34038 { 34039 name: "LTDBR", 34040 argLen: 1, 34041 asm: s390x.ALTDBR, 34042 reg: regInfo{ 34043 inputs: []inputInfo{ 34044 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34045 }, 34046 }, 34047 }, 34048 { 34049 name: "LTEBR", 34050 argLen: 1, 34051 asm: s390x.ALTEBR, 34052 reg: regInfo{ 34053 inputs: []inputInfo{ 34054 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34055 }, 34056 }, 34057 }, 34058 { 34059 name: "SLD", 34060 argLen: 2, 34061 asm: s390x.ASLD, 34062 reg: regInfo{ 34063 inputs: []inputInfo{ 34064 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34065 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34066 }, 34067 outputs: []outputInfo{ 34068 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34069 }, 34070 }, 34071 }, 34072 { 34073 name: "SLW", 34074 argLen: 2, 34075 asm: s390x.ASLW, 34076 reg: regInfo{ 34077 inputs: []inputInfo{ 34078 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34079 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34080 }, 34081 outputs: []outputInfo{ 34082 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34083 }, 34084 }, 34085 }, 34086 { 34087 name: "SLDconst", 34088 auxType: auxUInt8, 34089 argLen: 1, 34090 asm: s390x.ASLD, 34091 reg: regInfo{ 34092 inputs: []inputInfo{ 34093 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34094 }, 34095 outputs: []outputInfo{ 34096 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34097 }, 34098 }, 34099 }, 34100 { 34101 name: "SLWconst", 34102 auxType: auxUInt8, 34103 argLen: 1, 34104 asm: s390x.ASLW, 34105 reg: regInfo{ 34106 inputs: []inputInfo{ 34107 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34108 }, 34109 outputs: []outputInfo{ 34110 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34111 }, 34112 }, 34113 }, 34114 { 34115 name: "SRD", 34116 argLen: 2, 34117 asm: s390x.ASRD, 34118 reg: regInfo{ 34119 inputs: []inputInfo{ 34120 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34121 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34122 }, 34123 outputs: []outputInfo{ 34124 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34125 }, 34126 }, 34127 }, 34128 { 34129 name: "SRW", 34130 argLen: 2, 34131 asm: s390x.ASRW, 34132 reg: regInfo{ 34133 inputs: []inputInfo{ 34134 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34135 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34136 }, 34137 outputs: []outputInfo{ 34138 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34139 }, 34140 }, 34141 }, 34142 { 34143 name: "SRDconst", 34144 auxType: auxUInt8, 34145 argLen: 1, 34146 asm: s390x.ASRD, 34147 reg: regInfo{ 34148 inputs: []inputInfo{ 34149 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34150 }, 34151 outputs: []outputInfo{ 34152 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34153 }, 34154 }, 34155 }, 34156 { 34157 name: "SRWconst", 34158 auxType: auxUInt8, 34159 argLen: 1, 34160 asm: s390x.ASRW, 34161 reg: regInfo{ 34162 inputs: []inputInfo{ 34163 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34164 }, 34165 outputs: []outputInfo{ 34166 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34167 }, 34168 }, 34169 }, 34170 { 34171 name: "SRAD", 34172 argLen: 2, 34173 clobberFlags: true, 34174 asm: s390x.ASRAD, 34175 reg: regInfo{ 34176 inputs: []inputInfo{ 34177 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34178 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34179 }, 34180 outputs: []outputInfo{ 34181 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34182 }, 34183 }, 34184 }, 34185 { 34186 name: "SRAW", 34187 argLen: 2, 34188 clobberFlags: true, 34189 asm: s390x.ASRAW, 34190 reg: regInfo{ 34191 inputs: []inputInfo{ 34192 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34193 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34194 }, 34195 outputs: []outputInfo{ 34196 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34197 }, 34198 }, 34199 }, 34200 { 34201 name: "SRADconst", 34202 auxType: auxUInt8, 34203 argLen: 1, 34204 clobberFlags: true, 34205 asm: s390x.ASRAD, 34206 reg: regInfo{ 34207 inputs: []inputInfo{ 34208 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34209 }, 34210 outputs: []outputInfo{ 34211 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34212 }, 34213 }, 34214 }, 34215 { 34216 name: "SRAWconst", 34217 auxType: auxUInt8, 34218 argLen: 1, 34219 clobberFlags: true, 34220 asm: s390x.ASRAW, 34221 reg: regInfo{ 34222 inputs: []inputInfo{ 34223 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34224 }, 34225 outputs: []outputInfo{ 34226 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34227 }, 34228 }, 34229 }, 34230 { 34231 name: "RLLG", 34232 argLen: 2, 34233 asm: s390x.ARLLG, 34234 reg: regInfo{ 34235 inputs: []inputInfo{ 34236 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34237 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34238 }, 34239 outputs: []outputInfo{ 34240 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34241 }, 34242 }, 34243 }, 34244 { 34245 name: "RLL", 34246 argLen: 2, 34247 asm: s390x.ARLL, 34248 reg: regInfo{ 34249 inputs: []inputInfo{ 34250 {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34251 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34252 }, 34253 outputs: []outputInfo{ 34254 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34255 }, 34256 }, 34257 }, 34258 { 34259 name: "RLLconst", 34260 auxType: auxUInt8, 34261 argLen: 1, 34262 asm: s390x.ARLL, 34263 reg: regInfo{ 34264 inputs: []inputInfo{ 34265 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34266 }, 34267 outputs: []outputInfo{ 34268 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34269 }, 34270 }, 34271 }, 34272 { 34273 name: "RXSBG", 34274 auxType: auxS390XRotateParams, 34275 argLen: 2, 34276 resultInArg0: true, 34277 clobberFlags: true, 34278 asm: s390x.ARXSBG, 34279 reg: regInfo{ 34280 inputs: []inputInfo{ 34281 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34282 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34283 }, 34284 outputs: []outputInfo{ 34285 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34286 }, 34287 }, 34288 }, 34289 { 34290 name: "RISBGZ", 34291 auxType: auxS390XRotateParams, 34292 argLen: 1, 34293 clobberFlags: true, 34294 asm: s390x.ARISBGZ, 34295 reg: regInfo{ 34296 inputs: []inputInfo{ 34297 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34298 }, 34299 outputs: []outputInfo{ 34300 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34301 }, 34302 }, 34303 }, 34304 { 34305 name: "NEG", 34306 argLen: 1, 34307 clobberFlags: true, 34308 asm: s390x.ANEG, 34309 reg: regInfo{ 34310 inputs: []inputInfo{ 34311 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34312 }, 34313 outputs: []outputInfo{ 34314 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34315 }, 34316 }, 34317 }, 34318 { 34319 name: "NEGW", 34320 argLen: 1, 34321 clobberFlags: true, 34322 asm: s390x.ANEGW, 34323 reg: regInfo{ 34324 inputs: []inputInfo{ 34325 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34326 }, 34327 outputs: []outputInfo{ 34328 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34329 }, 34330 }, 34331 }, 34332 { 34333 name: "NOT", 34334 argLen: 1, 34335 resultInArg0: true, 34336 clobberFlags: true, 34337 reg: regInfo{ 34338 inputs: []inputInfo{ 34339 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34340 }, 34341 outputs: []outputInfo{ 34342 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34343 }, 34344 }, 34345 }, 34346 { 34347 name: "NOTW", 34348 argLen: 1, 34349 resultInArg0: true, 34350 clobberFlags: true, 34351 reg: regInfo{ 34352 inputs: []inputInfo{ 34353 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34354 }, 34355 outputs: []outputInfo{ 34356 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34357 }, 34358 }, 34359 }, 34360 { 34361 name: "FSQRT", 34362 argLen: 1, 34363 asm: s390x.AFSQRT, 34364 reg: regInfo{ 34365 inputs: []inputInfo{ 34366 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34367 }, 34368 outputs: []outputInfo{ 34369 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34370 }, 34371 }, 34372 }, 34373 { 34374 name: "FSQRTS", 34375 argLen: 1, 34376 asm: s390x.AFSQRTS, 34377 reg: regInfo{ 34378 inputs: []inputInfo{ 34379 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34380 }, 34381 outputs: []outputInfo{ 34382 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34383 }, 34384 }, 34385 }, 34386 { 34387 name: "LOCGR", 34388 auxType: auxS390XCCMask, 34389 argLen: 3, 34390 resultInArg0: true, 34391 asm: s390x.ALOCGR, 34392 reg: regInfo{ 34393 inputs: []inputInfo{ 34394 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34395 {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34396 }, 34397 outputs: []outputInfo{ 34398 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34399 }, 34400 }, 34401 }, 34402 { 34403 name: "MOVBreg", 34404 argLen: 1, 34405 asm: s390x.AMOVB, 34406 reg: regInfo{ 34407 inputs: []inputInfo{ 34408 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34409 }, 34410 outputs: []outputInfo{ 34411 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34412 }, 34413 }, 34414 }, 34415 { 34416 name: "MOVBZreg", 34417 argLen: 1, 34418 asm: s390x.AMOVBZ, 34419 reg: regInfo{ 34420 inputs: []inputInfo{ 34421 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34422 }, 34423 outputs: []outputInfo{ 34424 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34425 }, 34426 }, 34427 }, 34428 { 34429 name: "MOVHreg", 34430 argLen: 1, 34431 asm: s390x.AMOVH, 34432 reg: regInfo{ 34433 inputs: []inputInfo{ 34434 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34435 }, 34436 outputs: []outputInfo{ 34437 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34438 }, 34439 }, 34440 }, 34441 { 34442 name: "MOVHZreg", 34443 argLen: 1, 34444 asm: s390x.AMOVHZ, 34445 reg: regInfo{ 34446 inputs: []inputInfo{ 34447 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34448 }, 34449 outputs: []outputInfo{ 34450 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34451 }, 34452 }, 34453 }, 34454 { 34455 name: "MOVWreg", 34456 argLen: 1, 34457 asm: s390x.AMOVW, 34458 reg: regInfo{ 34459 inputs: []inputInfo{ 34460 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34461 }, 34462 outputs: []outputInfo{ 34463 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34464 }, 34465 }, 34466 }, 34467 { 34468 name: "MOVWZreg", 34469 argLen: 1, 34470 asm: s390x.AMOVWZ, 34471 reg: regInfo{ 34472 inputs: []inputInfo{ 34473 {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34474 }, 34475 outputs: []outputInfo{ 34476 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34477 }, 34478 }, 34479 }, 34480 { 34481 name: "MOVDconst", 34482 auxType: auxInt64, 34483 argLen: 0, 34484 rematerializeable: true, 34485 asm: s390x.AMOVD, 34486 reg: regInfo{ 34487 outputs: []outputInfo{ 34488 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34489 }, 34490 }, 34491 }, 34492 { 34493 name: "LDGR", 34494 argLen: 1, 34495 asm: s390x.ALDGR, 34496 reg: regInfo{ 34497 inputs: []inputInfo{ 34498 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34499 }, 34500 outputs: []outputInfo{ 34501 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34502 }, 34503 }, 34504 }, 34505 { 34506 name: "LGDR", 34507 argLen: 1, 34508 asm: s390x.ALGDR, 34509 reg: regInfo{ 34510 inputs: []inputInfo{ 34511 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34512 }, 34513 outputs: []outputInfo{ 34514 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34515 }, 34516 }, 34517 }, 34518 { 34519 name: "CFDBRA", 34520 argLen: 1, 34521 clobberFlags: true, 34522 asm: s390x.ACFDBRA, 34523 reg: regInfo{ 34524 inputs: []inputInfo{ 34525 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34526 }, 34527 outputs: []outputInfo{ 34528 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34529 }, 34530 }, 34531 }, 34532 { 34533 name: "CGDBRA", 34534 argLen: 1, 34535 clobberFlags: true, 34536 asm: s390x.ACGDBRA, 34537 reg: regInfo{ 34538 inputs: []inputInfo{ 34539 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34540 }, 34541 outputs: []outputInfo{ 34542 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34543 }, 34544 }, 34545 }, 34546 { 34547 name: "CFEBRA", 34548 argLen: 1, 34549 clobberFlags: true, 34550 asm: s390x.ACFEBRA, 34551 reg: regInfo{ 34552 inputs: []inputInfo{ 34553 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34554 }, 34555 outputs: []outputInfo{ 34556 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34557 }, 34558 }, 34559 }, 34560 { 34561 name: "CGEBRA", 34562 argLen: 1, 34563 clobberFlags: true, 34564 asm: s390x.ACGEBRA, 34565 reg: regInfo{ 34566 inputs: []inputInfo{ 34567 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34568 }, 34569 outputs: []outputInfo{ 34570 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34571 }, 34572 }, 34573 }, 34574 { 34575 name: "CEFBRA", 34576 argLen: 1, 34577 clobberFlags: true, 34578 asm: s390x.ACEFBRA, 34579 reg: regInfo{ 34580 inputs: []inputInfo{ 34581 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34582 }, 34583 outputs: []outputInfo{ 34584 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34585 }, 34586 }, 34587 }, 34588 { 34589 name: "CDFBRA", 34590 argLen: 1, 34591 clobberFlags: true, 34592 asm: s390x.ACDFBRA, 34593 reg: regInfo{ 34594 inputs: []inputInfo{ 34595 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34596 }, 34597 outputs: []outputInfo{ 34598 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34599 }, 34600 }, 34601 }, 34602 { 34603 name: "CEGBRA", 34604 argLen: 1, 34605 clobberFlags: true, 34606 asm: s390x.ACEGBRA, 34607 reg: regInfo{ 34608 inputs: []inputInfo{ 34609 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34610 }, 34611 outputs: []outputInfo{ 34612 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34613 }, 34614 }, 34615 }, 34616 { 34617 name: "CDGBRA", 34618 argLen: 1, 34619 clobberFlags: true, 34620 asm: s390x.ACDGBRA, 34621 reg: regInfo{ 34622 inputs: []inputInfo{ 34623 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34624 }, 34625 outputs: []outputInfo{ 34626 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34627 }, 34628 }, 34629 }, 34630 { 34631 name: "CLFEBR", 34632 argLen: 1, 34633 clobberFlags: true, 34634 asm: s390x.ACLFEBR, 34635 reg: regInfo{ 34636 inputs: []inputInfo{ 34637 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34638 }, 34639 outputs: []outputInfo{ 34640 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34641 }, 34642 }, 34643 }, 34644 { 34645 name: "CLFDBR", 34646 argLen: 1, 34647 clobberFlags: true, 34648 asm: s390x.ACLFDBR, 34649 reg: regInfo{ 34650 inputs: []inputInfo{ 34651 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34652 }, 34653 outputs: []outputInfo{ 34654 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34655 }, 34656 }, 34657 }, 34658 { 34659 name: "CLGEBR", 34660 argLen: 1, 34661 clobberFlags: true, 34662 asm: s390x.ACLGEBR, 34663 reg: regInfo{ 34664 inputs: []inputInfo{ 34665 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34666 }, 34667 outputs: []outputInfo{ 34668 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34669 }, 34670 }, 34671 }, 34672 { 34673 name: "CLGDBR", 34674 argLen: 1, 34675 clobberFlags: true, 34676 asm: s390x.ACLGDBR, 34677 reg: regInfo{ 34678 inputs: []inputInfo{ 34679 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34680 }, 34681 outputs: []outputInfo{ 34682 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34683 }, 34684 }, 34685 }, 34686 { 34687 name: "CELFBR", 34688 argLen: 1, 34689 clobberFlags: true, 34690 asm: s390x.ACELFBR, 34691 reg: regInfo{ 34692 inputs: []inputInfo{ 34693 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34694 }, 34695 outputs: []outputInfo{ 34696 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34697 }, 34698 }, 34699 }, 34700 { 34701 name: "CDLFBR", 34702 argLen: 1, 34703 clobberFlags: true, 34704 asm: s390x.ACDLFBR, 34705 reg: regInfo{ 34706 inputs: []inputInfo{ 34707 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34708 }, 34709 outputs: []outputInfo{ 34710 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34711 }, 34712 }, 34713 }, 34714 { 34715 name: "CELGBR", 34716 argLen: 1, 34717 clobberFlags: true, 34718 asm: s390x.ACELGBR, 34719 reg: regInfo{ 34720 inputs: []inputInfo{ 34721 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34722 }, 34723 outputs: []outputInfo{ 34724 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34725 }, 34726 }, 34727 }, 34728 { 34729 name: "CDLGBR", 34730 argLen: 1, 34731 clobberFlags: true, 34732 asm: s390x.ACDLGBR, 34733 reg: regInfo{ 34734 inputs: []inputInfo{ 34735 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34736 }, 34737 outputs: []outputInfo{ 34738 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34739 }, 34740 }, 34741 }, 34742 { 34743 name: "LEDBR", 34744 argLen: 1, 34745 asm: s390x.ALEDBR, 34746 reg: regInfo{ 34747 inputs: []inputInfo{ 34748 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34749 }, 34750 outputs: []outputInfo{ 34751 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34752 }, 34753 }, 34754 }, 34755 { 34756 name: "LDEBR", 34757 argLen: 1, 34758 asm: s390x.ALDEBR, 34759 reg: regInfo{ 34760 inputs: []inputInfo{ 34761 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34762 }, 34763 outputs: []outputInfo{ 34764 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 34765 }, 34766 }, 34767 }, 34768 { 34769 name: "MOVDaddr", 34770 auxType: auxSymOff, 34771 argLen: 1, 34772 rematerializeable: true, 34773 symEffect: SymRead, 34774 reg: regInfo{ 34775 inputs: []inputInfo{ 34776 {0, 4295000064}, // SP SB 34777 }, 34778 outputs: []outputInfo{ 34779 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34780 }, 34781 }, 34782 }, 34783 { 34784 name: "MOVDaddridx", 34785 auxType: auxSymOff, 34786 argLen: 2, 34787 symEffect: SymRead, 34788 reg: regInfo{ 34789 inputs: []inputInfo{ 34790 {0, 4295000064}, // SP SB 34791 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34792 }, 34793 outputs: []outputInfo{ 34794 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34795 }, 34796 }, 34797 }, 34798 { 34799 name: "MOVBZload", 34800 auxType: auxSymOff, 34801 argLen: 2, 34802 faultOnNilArg0: true, 34803 symEffect: SymRead, 34804 asm: s390x.AMOVBZ, 34805 reg: regInfo{ 34806 inputs: []inputInfo{ 34807 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34808 }, 34809 outputs: []outputInfo{ 34810 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34811 }, 34812 }, 34813 }, 34814 { 34815 name: "MOVBload", 34816 auxType: auxSymOff, 34817 argLen: 2, 34818 faultOnNilArg0: true, 34819 symEffect: SymRead, 34820 asm: s390x.AMOVB, 34821 reg: regInfo{ 34822 inputs: []inputInfo{ 34823 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34824 }, 34825 outputs: []outputInfo{ 34826 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34827 }, 34828 }, 34829 }, 34830 { 34831 name: "MOVHZload", 34832 auxType: auxSymOff, 34833 argLen: 2, 34834 faultOnNilArg0: true, 34835 symEffect: SymRead, 34836 asm: s390x.AMOVHZ, 34837 reg: regInfo{ 34838 inputs: []inputInfo{ 34839 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34840 }, 34841 outputs: []outputInfo{ 34842 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34843 }, 34844 }, 34845 }, 34846 { 34847 name: "MOVHload", 34848 auxType: auxSymOff, 34849 argLen: 2, 34850 faultOnNilArg0: true, 34851 symEffect: SymRead, 34852 asm: s390x.AMOVH, 34853 reg: regInfo{ 34854 inputs: []inputInfo{ 34855 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34856 }, 34857 outputs: []outputInfo{ 34858 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34859 }, 34860 }, 34861 }, 34862 { 34863 name: "MOVWZload", 34864 auxType: auxSymOff, 34865 argLen: 2, 34866 faultOnNilArg0: true, 34867 symEffect: SymRead, 34868 asm: s390x.AMOVWZ, 34869 reg: regInfo{ 34870 inputs: []inputInfo{ 34871 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34872 }, 34873 outputs: []outputInfo{ 34874 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34875 }, 34876 }, 34877 }, 34878 { 34879 name: "MOVWload", 34880 auxType: auxSymOff, 34881 argLen: 2, 34882 faultOnNilArg0: true, 34883 symEffect: SymRead, 34884 asm: s390x.AMOVW, 34885 reg: regInfo{ 34886 inputs: []inputInfo{ 34887 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34888 }, 34889 outputs: []outputInfo{ 34890 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34891 }, 34892 }, 34893 }, 34894 { 34895 name: "MOVDload", 34896 auxType: auxSymOff, 34897 argLen: 2, 34898 faultOnNilArg0: true, 34899 symEffect: SymRead, 34900 asm: s390x.AMOVD, 34901 reg: regInfo{ 34902 inputs: []inputInfo{ 34903 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34904 }, 34905 outputs: []outputInfo{ 34906 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34907 }, 34908 }, 34909 }, 34910 { 34911 name: "MOVWBR", 34912 argLen: 1, 34913 asm: s390x.AMOVWBR, 34914 reg: regInfo{ 34915 inputs: []inputInfo{ 34916 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34917 }, 34918 outputs: []outputInfo{ 34919 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34920 }, 34921 }, 34922 }, 34923 { 34924 name: "MOVDBR", 34925 argLen: 1, 34926 asm: s390x.AMOVDBR, 34927 reg: regInfo{ 34928 inputs: []inputInfo{ 34929 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34930 }, 34931 outputs: []outputInfo{ 34932 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34933 }, 34934 }, 34935 }, 34936 { 34937 name: "MOVHBRload", 34938 auxType: auxSymOff, 34939 argLen: 2, 34940 faultOnNilArg0: true, 34941 symEffect: SymRead, 34942 asm: s390x.AMOVHBR, 34943 reg: regInfo{ 34944 inputs: []inputInfo{ 34945 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34946 }, 34947 outputs: []outputInfo{ 34948 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34949 }, 34950 }, 34951 }, 34952 { 34953 name: "MOVWBRload", 34954 auxType: auxSymOff, 34955 argLen: 2, 34956 faultOnNilArg0: true, 34957 symEffect: SymRead, 34958 asm: s390x.AMOVWBR, 34959 reg: regInfo{ 34960 inputs: []inputInfo{ 34961 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34962 }, 34963 outputs: []outputInfo{ 34964 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34965 }, 34966 }, 34967 }, 34968 { 34969 name: "MOVDBRload", 34970 auxType: auxSymOff, 34971 argLen: 2, 34972 faultOnNilArg0: true, 34973 symEffect: SymRead, 34974 asm: s390x.AMOVDBR, 34975 reg: regInfo{ 34976 inputs: []inputInfo{ 34977 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34978 }, 34979 outputs: []outputInfo{ 34980 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 34981 }, 34982 }, 34983 }, 34984 { 34985 name: "MOVBstore", 34986 auxType: auxSymOff, 34987 argLen: 3, 34988 faultOnNilArg0: true, 34989 symEffect: SymWrite, 34990 asm: s390x.AMOVB, 34991 reg: regInfo{ 34992 inputs: []inputInfo{ 34993 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 34994 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 34995 }, 34996 }, 34997 }, 34998 { 34999 name: "MOVHstore", 35000 auxType: auxSymOff, 35001 argLen: 3, 35002 faultOnNilArg0: true, 35003 symEffect: SymWrite, 35004 asm: s390x.AMOVH, 35005 reg: regInfo{ 35006 inputs: []inputInfo{ 35007 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35008 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35009 }, 35010 }, 35011 }, 35012 { 35013 name: "MOVWstore", 35014 auxType: auxSymOff, 35015 argLen: 3, 35016 faultOnNilArg0: true, 35017 symEffect: SymWrite, 35018 asm: s390x.AMOVW, 35019 reg: regInfo{ 35020 inputs: []inputInfo{ 35021 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35022 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35023 }, 35024 }, 35025 }, 35026 { 35027 name: "MOVDstore", 35028 auxType: auxSymOff, 35029 argLen: 3, 35030 faultOnNilArg0: true, 35031 symEffect: SymWrite, 35032 asm: s390x.AMOVD, 35033 reg: regInfo{ 35034 inputs: []inputInfo{ 35035 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35036 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35037 }, 35038 }, 35039 }, 35040 { 35041 name: "MOVHBRstore", 35042 auxType: auxSymOff, 35043 argLen: 3, 35044 faultOnNilArg0: true, 35045 symEffect: SymWrite, 35046 asm: s390x.AMOVHBR, 35047 reg: regInfo{ 35048 inputs: []inputInfo{ 35049 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35050 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35051 }, 35052 }, 35053 }, 35054 { 35055 name: "MOVWBRstore", 35056 auxType: auxSymOff, 35057 argLen: 3, 35058 faultOnNilArg0: true, 35059 symEffect: SymWrite, 35060 asm: s390x.AMOVWBR, 35061 reg: regInfo{ 35062 inputs: []inputInfo{ 35063 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35064 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35065 }, 35066 }, 35067 }, 35068 { 35069 name: "MOVDBRstore", 35070 auxType: auxSymOff, 35071 argLen: 3, 35072 faultOnNilArg0: true, 35073 symEffect: SymWrite, 35074 asm: s390x.AMOVDBR, 35075 reg: regInfo{ 35076 inputs: []inputInfo{ 35077 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35078 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35079 }, 35080 }, 35081 }, 35082 { 35083 name: "MVC", 35084 auxType: auxSymValAndOff, 35085 argLen: 3, 35086 clobberFlags: true, 35087 faultOnNilArg0: true, 35088 faultOnNilArg1: true, 35089 symEffect: SymNone, 35090 asm: s390x.AMVC, 35091 reg: regInfo{ 35092 inputs: []inputInfo{ 35093 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35094 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35095 }, 35096 }, 35097 }, 35098 { 35099 name: "MOVBZloadidx", 35100 auxType: auxSymOff, 35101 argLen: 3, 35102 commutative: true, 35103 symEffect: SymRead, 35104 asm: s390x.AMOVBZ, 35105 reg: regInfo{ 35106 inputs: []inputInfo{ 35107 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35108 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35109 }, 35110 outputs: []outputInfo{ 35111 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35112 }, 35113 }, 35114 }, 35115 { 35116 name: "MOVBloadidx", 35117 auxType: auxSymOff, 35118 argLen: 3, 35119 commutative: true, 35120 symEffect: SymRead, 35121 asm: s390x.AMOVB, 35122 reg: regInfo{ 35123 inputs: []inputInfo{ 35124 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35125 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35126 }, 35127 outputs: []outputInfo{ 35128 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35129 }, 35130 }, 35131 }, 35132 { 35133 name: "MOVHZloadidx", 35134 auxType: auxSymOff, 35135 argLen: 3, 35136 commutative: true, 35137 symEffect: SymRead, 35138 asm: s390x.AMOVHZ, 35139 reg: regInfo{ 35140 inputs: []inputInfo{ 35141 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35142 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35143 }, 35144 outputs: []outputInfo{ 35145 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35146 }, 35147 }, 35148 }, 35149 { 35150 name: "MOVHloadidx", 35151 auxType: auxSymOff, 35152 argLen: 3, 35153 commutative: true, 35154 symEffect: SymRead, 35155 asm: s390x.AMOVH, 35156 reg: regInfo{ 35157 inputs: []inputInfo{ 35158 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35159 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35160 }, 35161 outputs: []outputInfo{ 35162 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35163 }, 35164 }, 35165 }, 35166 { 35167 name: "MOVWZloadidx", 35168 auxType: auxSymOff, 35169 argLen: 3, 35170 commutative: true, 35171 symEffect: SymRead, 35172 asm: s390x.AMOVWZ, 35173 reg: regInfo{ 35174 inputs: []inputInfo{ 35175 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35176 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35177 }, 35178 outputs: []outputInfo{ 35179 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35180 }, 35181 }, 35182 }, 35183 { 35184 name: "MOVWloadidx", 35185 auxType: auxSymOff, 35186 argLen: 3, 35187 commutative: true, 35188 symEffect: SymRead, 35189 asm: s390x.AMOVW, 35190 reg: regInfo{ 35191 inputs: []inputInfo{ 35192 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35193 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35194 }, 35195 outputs: []outputInfo{ 35196 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35197 }, 35198 }, 35199 }, 35200 { 35201 name: "MOVDloadidx", 35202 auxType: auxSymOff, 35203 argLen: 3, 35204 commutative: true, 35205 symEffect: SymRead, 35206 asm: s390x.AMOVD, 35207 reg: regInfo{ 35208 inputs: []inputInfo{ 35209 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35210 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35211 }, 35212 outputs: []outputInfo{ 35213 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35214 }, 35215 }, 35216 }, 35217 { 35218 name: "MOVHBRloadidx", 35219 auxType: auxSymOff, 35220 argLen: 3, 35221 commutative: true, 35222 symEffect: SymRead, 35223 asm: s390x.AMOVHBR, 35224 reg: regInfo{ 35225 inputs: []inputInfo{ 35226 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35227 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35228 }, 35229 outputs: []outputInfo{ 35230 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35231 }, 35232 }, 35233 }, 35234 { 35235 name: "MOVWBRloadidx", 35236 auxType: auxSymOff, 35237 argLen: 3, 35238 commutative: true, 35239 symEffect: SymRead, 35240 asm: s390x.AMOVWBR, 35241 reg: regInfo{ 35242 inputs: []inputInfo{ 35243 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35244 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35245 }, 35246 outputs: []outputInfo{ 35247 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35248 }, 35249 }, 35250 }, 35251 { 35252 name: "MOVDBRloadidx", 35253 auxType: auxSymOff, 35254 argLen: 3, 35255 commutative: true, 35256 symEffect: SymRead, 35257 asm: s390x.AMOVDBR, 35258 reg: regInfo{ 35259 inputs: []inputInfo{ 35260 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35261 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35262 }, 35263 outputs: []outputInfo{ 35264 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35265 }, 35266 }, 35267 }, 35268 { 35269 name: "MOVBstoreidx", 35270 auxType: auxSymOff, 35271 argLen: 4, 35272 commutative: true, 35273 symEffect: SymWrite, 35274 asm: s390x.AMOVB, 35275 reg: regInfo{ 35276 inputs: []inputInfo{ 35277 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35278 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35279 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35280 }, 35281 }, 35282 }, 35283 { 35284 name: "MOVHstoreidx", 35285 auxType: auxSymOff, 35286 argLen: 4, 35287 commutative: true, 35288 symEffect: SymWrite, 35289 asm: s390x.AMOVH, 35290 reg: regInfo{ 35291 inputs: []inputInfo{ 35292 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35293 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35294 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35295 }, 35296 }, 35297 }, 35298 { 35299 name: "MOVWstoreidx", 35300 auxType: auxSymOff, 35301 argLen: 4, 35302 commutative: true, 35303 symEffect: SymWrite, 35304 asm: s390x.AMOVW, 35305 reg: regInfo{ 35306 inputs: []inputInfo{ 35307 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35308 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35309 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35310 }, 35311 }, 35312 }, 35313 { 35314 name: "MOVDstoreidx", 35315 auxType: auxSymOff, 35316 argLen: 4, 35317 commutative: true, 35318 symEffect: SymWrite, 35319 asm: s390x.AMOVD, 35320 reg: regInfo{ 35321 inputs: []inputInfo{ 35322 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35323 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35324 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35325 }, 35326 }, 35327 }, 35328 { 35329 name: "MOVHBRstoreidx", 35330 auxType: auxSymOff, 35331 argLen: 4, 35332 commutative: true, 35333 symEffect: SymWrite, 35334 asm: s390x.AMOVHBR, 35335 reg: regInfo{ 35336 inputs: []inputInfo{ 35337 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35338 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35339 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35340 }, 35341 }, 35342 }, 35343 { 35344 name: "MOVWBRstoreidx", 35345 auxType: auxSymOff, 35346 argLen: 4, 35347 commutative: true, 35348 symEffect: SymWrite, 35349 asm: s390x.AMOVWBR, 35350 reg: regInfo{ 35351 inputs: []inputInfo{ 35352 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35353 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35354 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35355 }, 35356 }, 35357 }, 35358 { 35359 name: "MOVDBRstoreidx", 35360 auxType: auxSymOff, 35361 argLen: 4, 35362 commutative: true, 35363 symEffect: SymWrite, 35364 asm: s390x.AMOVDBR, 35365 reg: regInfo{ 35366 inputs: []inputInfo{ 35367 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35368 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35369 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35370 }, 35371 }, 35372 }, 35373 { 35374 name: "MOVBstoreconst", 35375 auxType: auxSymValAndOff, 35376 argLen: 2, 35377 faultOnNilArg0: true, 35378 symEffect: SymWrite, 35379 asm: s390x.AMOVB, 35380 reg: regInfo{ 35381 inputs: []inputInfo{ 35382 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35383 }, 35384 }, 35385 }, 35386 { 35387 name: "MOVHstoreconst", 35388 auxType: auxSymValAndOff, 35389 argLen: 2, 35390 faultOnNilArg0: true, 35391 symEffect: SymWrite, 35392 asm: s390x.AMOVH, 35393 reg: regInfo{ 35394 inputs: []inputInfo{ 35395 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35396 }, 35397 }, 35398 }, 35399 { 35400 name: "MOVWstoreconst", 35401 auxType: auxSymValAndOff, 35402 argLen: 2, 35403 faultOnNilArg0: true, 35404 symEffect: SymWrite, 35405 asm: s390x.AMOVW, 35406 reg: regInfo{ 35407 inputs: []inputInfo{ 35408 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35409 }, 35410 }, 35411 }, 35412 { 35413 name: "MOVDstoreconst", 35414 auxType: auxSymValAndOff, 35415 argLen: 2, 35416 faultOnNilArg0: true, 35417 symEffect: SymWrite, 35418 asm: s390x.AMOVD, 35419 reg: regInfo{ 35420 inputs: []inputInfo{ 35421 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35422 }, 35423 }, 35424 }, 35425 { 35426 name: "CLEAR", 35427 auxType: auxSymValAndOff, 35428 argLen: 2, 35429 clobberFlags: true, 35430 faultOnNilArg0: true, 35431 symEffect: SymWrite, 35432 asm: s390x.ACLEAR, 35433 reg: regInfo{ 35434 inputs: []inputInfo{ 35435 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35436 }, 35437 }, 35438 }, 35439 { 35440 name: "CALLstatic", 35441 auxType: auxCallOff, 35442 argLen: 1, 35443 clobberFlags: true, 35444 call: true, 35445 reg: regInfo{ 35446 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35447 }, 35448 }, 35449 { 35450 name: "CALLtail", 35451 auxType: auxCallOff, 35452 argLen: 1, 35453 clobberFlags: true, 35454 call: true, 35455 tailCall: true, 35456 reg: regInfo{ 35457 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35458 }, 35459 }, 35460 { 35461 name: "CALLclosure", 35462 auxType: auxCallOff, 35463 argLen: 3, 35464 clobberFlags: true, 35465 call: true, 35466 reg: regInfo{ 35467 inputs: []inputInfo{ 35468 {1, 4096}, // R12 35469 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35470 }, 35471 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35472 }, 35473 }, 35474 { 35475 name: "CALLinter", 35476 auxType: auxCallOff, 35477 argLen: 2, 35478 clobberFlags: true, 35479 call: true, 35480 reg: regInfo{ 35481 inputs: []inputInfo{ 35482 {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35483 }, 35484 clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35485 }, 35486 }, 35487 { 35488 name: "InvertFlags", 35489 argLen: 1, 35490 reg: regInfo{}, 35491 }, 35492 { 35493 name: "LoweredGetG", 35494 argLen: 1, 35495 reg: regInfo{ 35496 outputs: []outputInfo{ 35497 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35498 }, 35499 }, 35500 }, 35501 { 35502 name: "LoweredGetClosurePtr", 35503 argLen: 0, 35504 zeroWidth: true, 35505 reg: regInfo{ 35506 outputs: []outputInfo{ 35507 {0, 4096}, // R12 35508 }, 35509 }, 35510 }, 35511 { 35512 name: "LoweredGetCallerSP", 35513 argLen: 0, 35514 rematerializeable: true, 35515 reg: regInfo{ 35516 outputs: []outputInfo{ 35517 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35518 }, 35519 }, 35520 }, 35521 { 35522 name: "LoweredGetCallerPC", 35523 argLen: 0, 35524 rematerializeable: true, 35525 reg: regInfo{ 35526 outputs: []outputInfo{ 35527 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35528 }, 35529 }, 35530 }, 35531 { 35532 name: "LoweredNilCheck", 35533 argLen: 2, 35534 clobberFlags: true, 35535 nilCheck: true, 35536 faultOnNilArg0: true, 35537 reg: regInfo{ 35538 inputs: []inputInfo{ 35539 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35540 }, 35541 }, 35542 }, 35543 { 35544 name: "LoweredRound32F", 35545 argLen: 1, 35546 resultInArg0: true, 35547 zeroWidth: true, 35548 reg: regInfo{ 35549 inputs: []inputInfo{ 35550 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35551 }, 35552 outputs: []outputInfo{ 35553 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35554 }, 35555 }, 35556 }, 35557 { 35558 name: "LoweredRound64F", 35559 argLen: 1, 35560 resultInArg0: true, 35561 zeroWidth: true, 35562 reg: regInfo{ 35563 inputs: []inputInfo{ 35564 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35565 }, 35566 outputs: []outputInfo{ 35567 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35568 }, 35569 }, 35570 }, 35571 { 35572 name: "LoweredWB", 35573 auxType: auxSym, 35574 argLen: 3, 35575 clobberFlags: true, 35576 symEffect: SymNone, 35577 reg: regInfo{ 35578 inputs: []inputInfo{ 35579 {0, 4}, // R2 35580 {1, 8}, // R3 35581 }, 35582 clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 35583 }, 35584 }, 35585 { 35586 name: "LoweredPanicBoundsA", 35587 auxType: auxInt64, 35588 argLen: 3, 35589 call: true, 35590 reg: regInfo{ 35591 inputs: []inputInfo{ 35592 {0, 4}, // R2 35593 {1, 8}, // R3 35594 }, 35595 }, 35596 }, 35597 { 35598 name: "LoweredPanicBoundsB", 35599 auxType: auxInt64, 35600 argLen: 3, 35601 call: true, 35602 reg: regInfo{ 35603 inputs: []inputInfo{ 35604 {0, 2}, // R1 35605 {1, 4}, // R2 35606 }, 35607 }, 35608 }, 35609 { 35610 name: "LoweredPanicBoundsC", 35611 auxType: auxInt64, 35612 argLen: 3, 35613 call: true, 35614 reg: regInfo{ 35615 inputs: []inputInfo{ 35616 {0, 1}, // R0 35617 {1, 2}, // R1 35618 }, 35619 }, 35620 }, 35621 { 35622 name: "FlagEQ", 35623 argLen: 0, 35624 reg: regInfo{}, 35625 }, 35626 { 35627 name: "FlagLT", 35628 argLen: 0, 35629 reg: regInfo{}, 35630 }, 35631 { 35632 name: "FlagGT", 35633 argLen: 0, 35634 reg: regInfo{}, 35635 }, 35636 { 35637 name: "FlagOV", 35638 argLen: 0, 35639 reg: regInfo{}, 35640 }, 35641 { 35642 name: "SYNC", 35643 argLen: 1, 35644 asm: s390x.ASYNC, 35645 reg: regInfo{}, 35646 }, 35647 { 35648 name: "MOVBZatomicload", 35649 auxType: auxSymOff, 35650 argLen: 2, 35651 faultOnNilArg0: true, 35652 symEffect: SymRead, 35653 asm: s390x.AMOVBZ, 35654 reg: regInfo{ 35655 inputs: []inputInfo{ 35656 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35657 }, 35658 outputs: []outputInfo{ 35659 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35660 }, 35661 }, 35662 }, 35663 { 35664 name: "MOVWZatomicload", 35665 auxType: auxSymOff, 35666 argLen: 2, 35667 faultOnNilArg0: true, 35668 symEffect: SymRead, 35669 asm: s390x.AMOVWZ, 35670 reg: regInfo{ 35671 inputs: []inputInfo{ 35672 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35673 }, 35674 outputs: []outputInfo{ 35675 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35676 }, 35677 }, 35678 }, 35679 { 35680 name: "MOVDatomicload", 35681 auxType: auxSymOff, 35682 argLen: 2, 35683 faultOnNilArg0: true, 35684 symEffect: SymRead, 35685 asm: s390x.AMOVD, 35686 reg: regInfo{ 35687 inputs: []inputInfo{ 35688 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35689 }, 35690 outputs: []outputInfo{ 35691 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35692 }, 35693 }, 35694 }, 35695 { 35696 name: "MOVBatomicstore", 35697 auxType: auxSymOff, 35698 argLen: 3, 35699 clobberFlags: true, 35700 faultOnNilArg0: true, 35701 hasSideEffects: true, 35702 symEffect: SymWrite, 35703 asm: s390x.AMOVB, 35704 reg: regInfo{ 35705 inputs: []inputInfo{ 35706 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35707 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35708 }, 35709 }, 35710 }, 35711 { 35712 name: "MOVWatomicstore", 35713 auxType: auxSymOff, 35714 argLen: 3, 35715 clobberFlags: true, 35716 faultOnNilArg0: true, 35717 hasSideEffects: true, 35718 symEffect: SymWrite, 35719 asm: s390x.AMOVW, 35720 reg: regInfo{ 35721 inputs: []inputInfo{ 35722 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35723 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35724 }, 35725 }, 35726 }, 35727 { 35728 name: "MOVDatomicstore", 35729 auxType: auxSymOff, 35730 argLen: 3, 35731 clobberFlags: true, 35732 faultOnNilArg0: true, 35733 hasSideEffects: true, 35734 symEffect: SymWrite, 35735 asm: s390x.AMOVD, 35736 reg: regInfo{ 35737 inputs: []inputInfo{ 35738 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35739 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35740 }, 35741 }, 35742 }, 35743 { 35744 name: "LAA", 35745 auxType: auxSymOff, 35746 argLen: 3, 35747 clobberFlags: true, 35748 faultOnNilArg0: true, 35749 hasSideEffects: true, 35750 symEffect: SymRdWr, 35751 asm: s390x.ALAA, 35752 reg: regInfo{ 35753 inputs: []inputInfo{ 35754 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35755 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35756 }, 35757 outputs: []outputInfo{ 35758 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35759 }, 35760 }, 35761 }, 35762 { 35763 name: "LAAG", 35764 auxType: auxSymOff, 35765 argLen: 3, 35766 clobberFlags: true, 35767 faultOnNilArg0: true, 35768 hasSideEffects: true, 35769 symEffect: SymRdWr, 35770 asm: s390x.ALAAG, 35771 reg: regInfo{ 35772 inputs: []inputInfo{ 35773 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35774 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35775 }, 35776 outputs: []outputInfo{ 35777 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35778 }, 35779 }, 35780 }, 35781 { 35782 name: "AddTupleFirst32", 35783 argLen: 2, 35784 reg: regInfo{}, 35785 }, 35786 { 35787 name: "AddTupleFirst64", 35788 argLen: 2, 35789 reg: regInfo{}, 35790 }, 35791 { 35792 name: "LAN", 35793 argLen: 3, 35794 clobberFlags: true, 35795 hasSideEffects: true, 35796 asm: s390x.ALAN, 35797 reg: regInfo{ 35798 inputs: []inputInfo{ 35799 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35800 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35801 }, 35802 }, 35803 }, 35804 { 35805 name: "LANfloor", 35806 argLen: 3, 35807 clobberFlags: true, 35808 hasSideEffects: true, 35809 asm: s390x.ALAN, 35810 reg: regInfo{ 35811 inputs: []inputInfo{ 35812 {0, 2}, // R1 35813 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35814 }, 35815 clobbers: 2, // R1 35816 }, 35817 }, 35818 { 35819 name: "LAO", 35820 argLen: 3, 35821 clobberFlags: true, 35822 hasSideEffects: true, 35823 asm: s390x.ALAO, 35824 reg: regInfo{ 35825 inputs: []inputInfo{ 35826 {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB 35827 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35828 }, 35829 }, 35830 }, 35831 { 35832 name: "LAOfloor", 35833 argLen: 3, 35834 clobberFlags: true, 35835 hasSideEffects: true, 35836 asm: s390x.ALAO, 35837 reg: regInfo{ 35838 inputs: []inputInfo{ 35839 {0, 2}, // R1 35840 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35841 }, 35842 clobbers: 2, // R1 35843 }, 35844 }, 35845 { 35846 name: "LoweredAtomicCas32", 35847 auxType: auxSymOff, 35848 argLen: 4, 35849 clobberFlags: true, 35850 faultOnNilArg0: true, 35851 hasSideEffects: true, 35852 symEffect: SymRdWr, 35853 asm: s390x.ACS, 35854 reg: regInfo{ 35855 inputs: []inputInfo{ 35856 {1, 1}, // R0 35857 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35858 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35859 }, 35860 clobbers: 1, // R0 35861 outputs: []outputInfo{ 35862 {1, 0}, 35863 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35864 }, 35865 }, 35866 }, 35867 { 35868 name: "LoweredAtomicCas64", 35869 auxType: auxSymOff, 35870 argLen: 4, 35871 clobberFlags: true, 35872 faultOnNilArg0: true, 35873 hasSideEffects: true, 35874 symEffect: SymRdWr, 35875 asm: s390x.ACSG, 35876 reg: regInfo{ 35877 inputs: []inputInfo{ 35878 {1, 1}, // R0 35879 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35880 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35881 }, 35882 clobbers: 1, // R0 35883 outputs: []outputInfo{ 35884 {1, 0}, 35885 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35886 }, 35887 }, 35888 }, 35889 { 35890 name: "LoweredAtomicExchange32", 35891 auxType: auxSymOff, 35892 argLen: 3, 35893 clobberFlags: true, 35894 faultOnNilArg0: true, 35895 hasSideEffects: true, 35896 symEffect: SymRdWr, 35897 asm: s390x.ACS, 35898 reg: regInfo{ 35899 inputs: []inputInfo{ 35900 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35901 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35902 }, 35903 outputs: []outputInfo{ 35904 {1, 0}, 35905 {0, 1}, // R0 35906 }, 35907 }, 35908 }, 35909 { 35910 name: "LoweredAtomicExchange64", 35911 auxType: auxSymOff, 35912 argLen: 3, 35913 clobberFlags: true, 35914 faultOnNilArg0: true, 35915 hasSideEffects: true, 35916 symEffect: SymRdWr, 35917 asm: s390x.ACSG, 35918 reg: regInfo{ 35919 inputs: []inputInfo{ 35920 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35921 {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 35922 }, 35923 outputs: []outputInfo{ 35924 {1, 0}, 35925 {0, 1}, // R0 35926 }, 35927 }, 35928 }, 35929 { 35930 name: "FLOGR", 35931 argLen: 1, 35932 clobberFlags: true, 35933 asm: s390x.AFLOGR, 35934 reg: regInfo{ 35935 inputs: []inputInfo{ 35936 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35937 }, 35938 clobbers: 2, // R1 35939 outputs: []outputInfo{ 35940 {0, 1}, // R0 35941 }, 35942 }, 35943 }, 35944 { 35945 name: "POPCNT", 35946 argLen: 1, 35947 clobberFlags: true, 35948 asm: s390x.APOPCNT, 35949 reg: regInfo{ 35950 inputs: []inputInfo{ 35951 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35952 }, 35953 outputs: []outputInfo{ 35954 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35955 }, 35956 }, 35957 }, 35958 { 35959 name: "MLGR", 35960 argLen: 2, 35961 asm: s390x.AMLGR, 35962 reg: regInfo{ 35963 inputs: []inputInfo{ 35964 {1, 8}, // R3 35965 {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 35966 }, 35967 outputs: []outputInfo{ 35968 {0, 4}, // R2 35969 {1, 8}, // R3 35970 }, 35971 }, 35972 }, 35973 { 35974 name: "SumBytes2", 35975 argLen: 1, 35976 reg: regInfo{}, 35977 }, 35978 { 35979 name: "SumBytes4", 35980 argLen: 1, 35981 reg: regInfo{}, 35982 }, 35983 { 35984 name: "SumBytes8", 35985 argLen: 1, 35986 reg: regInfo{}, 35987 }, 35988 { 35989 name: "STMG2", 35990 auxType: auxSymOff, 35991 argLen: 4, 35992 clobberFlags: true, 35993 faultOnNilArg0: true, 35994 symEffect: SymWrite, 35995 asm: s390x.ASTMG, 35996 reg: regInfo{ 35997 inputs: []inputInfo{ 35998 {1, 2}, // R1 35999 {2, 4}, // R2 36000 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36001 }, 36002 }, 36003 }, 36004 { 36005 name: "STMG3", 36006 auxType: auxSymOff, 36007 argLen: 5, 36008 clobberFlags: true, 36009 faultOnNilArg0: true, 36010 symEffect: SymWrite, 36011 asm: s390x.ASTMG, 36012 reg: regInfo{ 36013 inputs: []inputInfo{ 36014 {1, 2}, // R1 36015 {2, 4}, // R2 36016 {3, 8}, // R3 36017 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36018 }, 36019 }, 36020 }, 36021 { 36022 name: "STMG4", 36023 auxType: auxSymOff, 36024 argLen: 6, 36025 clobberFlags: true, 36026 faultOnNilArg0: true, 36027 symEffect: SymWrite, 36028 asm: s390x.ASTMG, 36029 reg: regInfo{ 36030 inputs: []inputInfo{ 36031 {1, 2}, // R1 36032 {2, 4}, // R2 36033 {3, 8}, // R3 36034 {4, 16}, // R4 36035 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36036 }, 36037 }, 36038 }, 36039 { 36040 name: "STM2", 36041 auxType: auxSymOff, 36042 argLen: 4, 36043 clobberFlags: true, 36044 faultOnNilArg0: true, 36045 symEffect: SymWrite, 36046 asm: s390x.ASTMY, 36047 reg: regInfo{ 36048 inputs: []inputInfo{ 36049 {1, 2}, // R1 36050 {2, 4}, // R2 36051 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36052 }, 36053 }, 36054 }, 36055 { 36056 name: "STM3", 36057 auxType: auxSymOff, 36058 argLen: 5, 36059 clobberFlags: true, 36060 faultOnNilArg0: true, 36061 symEffect: SymWrite, 36062 asm: s390x.ASTMY, 36063 reg: regInfo{ 36064 inputs: []inputInfo{ 36065 {1, 2}, // R1 36066 {2, 4}, // R2 36067 {3, 8}, // R3 36068 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36069 }, 36070 }, 36071 }, 36072 { 36073 name: "STM4", 36074 auxType: auxSymOff, 36075 argLen: 6, 36076 clobberFlags: true, 36077 faultOnNilArg0: true, 36078 symEffect: SymWrite, 36079 asm: s390x.ASTMY, 36080 reg: regInfo{ 36081 inputs: []inputInfo{ 36082 {1, 2}, // R1 36083 {2, 4}, // R2 36084 {3, 8}, // R3 36085 {4, 16}, // R4 36086 {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36087 }, 36088 }, 36089 }, 36090 { 36091 name: "LoweredMove", 36092 auxType: auxInt64, 36093 argLen: 4, 36094 clobberFlags: true, 36095 faultOnNilArg0: true, 36096 faultOnNilArg1: true, 36097 reg: regInfo{ 36098 inputs: []inputInfo{ 36099 {0, 2}, // R1 36100 {1, 4}, // R2 36101 {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36102 }, 36103 clobbers: 6, // R1 R2 36104 }, 36105 }, 36106 { 36107 name: "LoweredZero", 36108 auxType: auxInt64, 36109 argLen: 3, 36110 clobberFlags: true, 36111 faultOnNilArg0: true, 36112 reg: regInfo{ 36113 inputs: []inputInfo{ 36114 {0, 2}, // R1 36115 {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP 36116 }, 36117 clobbers: 2, // R1 36118 }, 36119 }, 36120 36121 { 36122 name: "LoweredStaticCall", 36123 auxType: auxCallOff, 36124 argLen: 1, 36125 call: true, 36126 reg: regInfo{ 36127 clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g 36128 }, 36129 }, 36130 { 36131 name: "LoweredTailCall", 36132 auxType: auxCallOff, 36133 argLen: 1, 36134 call: true, 36135 tailCall: true, 36136 reg: regInfo{ 36137 clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g 36138 }, 36139 }, 36140 { 36141 name: "LoweredClosureCall", 36142 auxType: auxCallOff, 36143 argLen: 3, 36144 call: true, 36145 reg: regInfo{ 36146 inputs: []inputInfo{ 36147 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36148 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36149 }, 36150 clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g 36151 }, 36152 }, 36153 { 36154 name: "LoweredInterCall", 36155 auxType: auxCallOff, 36156 argLen: 2, 36157 call: true, 36158 reg: regInfo{ 36159 inputs: []inputInfo{ 36160 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36161 }, 36162 clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g 36163 }, 36164 }, 36165 { 36166 name: "LoweredAddr", 36167 auxType: auxSymOff, 36168 argLen: 1, 36169 rematerializeable: true, 36170 symEffect: SymAddr, 36171 reg: regInfo{ 36172 inputs: []inputInfo{ 36173 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36174 }, 36175 outputs: []outputInfo{ 36176 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36177 }, 36178 }, 36179 }, 36180 { 36181 name: "LoweredMove", 36182 auxType: auxInt64, 36183 argLen: 3, 36184 reg: regInfo{ 36185 inputs: []inputInfo{ 36186 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36187 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36188 }, 36189 }, 36190 }, 36191 { 36192 name: "LoweredZero", 36193 auxType: auxInt64, 36194 argLen: 2, 36195 reg: regInfo{ 36196 inputs: []inputInfo{ 36197 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36198 }, 36199 }, 36200 }, 36201 { 36202 name: "LoweredGetClosurePtr", 36203 argLen: 0, 36204 reg: regInfo{ 36205 outputs: []outputInfo{ 36206 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36207 }, 36208 }, 36209 }, 36210 { 36211 name: "LoweredGetCallerPC", 36212 argLen: 0, 36213 rematerializeable: true, 36214 reg: regInfo{ 36215 outputs: []outputInfo{ 36216 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36217 }, 36218 }, 36219 }, 36220 { 36221 name: "LoweredGetCallerSP", 36222 argLen: 0, 36223 rematerializeable: true, 36224 reg: regInfo{ 36225 outputs: []outputInfo{ 36226 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36227 }, 36228 }, 36229 }, 36230 { 36231 name: "LoweredNilCheck", 36232 argLen: 2, 36233 nilCheck: true, 36234 faultOnNilArg0: true, 36235 reg: regInfo{ 36236 inputs: []inputInfo{ 36237 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36238 }, 36239 }, 36240 }, 36241 { 36242 name: "LoweredWB", 36243 auxType: auxSym, 36244 argLen: 3, 36245 symEffect: SymNone, 36246 reg: regInfo{ 36247 inputs: []inputInfo{ 36248 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36249 {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36250 }, 36251 }, 36252 }, 36253 { 36254 name: "LoweredConvert", 36255 argLen: 2, 36256 reg: regInfo{ 36257 inputs: []inputInfo{ 36258 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36259 }, 36260 outputs: []outputInfo{ 36261 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36262 }, 36263 }, 36264 }, 36265 { 36266 name: "Select", 36267 argLen: 3, 36268 asm: wasm.ASelect, 36269 reg: regInfo{ 36270 inputs: []inputInfo{ 36271 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36272 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36273 {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36274 }, 36275 outputs: []outputInfo{ 36276 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36277 }, 36278 }, 36279 }, 36280 { 36281 name: "I64Load8U", 36282 auxType: auxInt64, 36283 argLen: 2, 36284 asm: wasm.AI64Load8U, 36285 reg: regInfo{ 36286 inputs: []inputInfo{ 36287 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36288 }, 36289 outputs: []outputInfo{ 36290 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36291 }, 36292 }, 36293 }, 36294 { 36295 name: "I64Load8S", 36296 auxType: auxInt64, 36297 argLen: 2, 36298 asm: wasm.AI64Load8S, 36299 reg: regInfo{ 36300 inputs: []inputInfo{ 36301 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36302 }, 36303 outputs: []outputInfo{ 36304 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36305 }, 36306 }, 36307 }, 36308 { 36309 name: "I64Load16U", 36310 auxType: auxInt64, 36311 argLen: 2, 36312 asm: wasm.AI64Load16U, 36313 reg: regInfo{ 36314 inputs: []inputInfo{ 36315 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36316 }, 36317 outputs: []outputInfo{ 36318 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36319 }, 36320 }, 36321 }, 36322 { 36323 name: "I64Load16S", 36324 auxType: auxInt64, 36325 argLen: 2, 36326 asm: wasm.AI64Load16S, 36327 reg: regInfo{ 36328 inputs: []inputInfo{ 36329 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36330 }, 36331 outputs: []outputInfo{ 36332 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36333 }, 36334 }, 36335 }, 36336 { 36337 name: "I64Load32U", 36338 auxType: auxInt64, 36339 argLen: 2, 36340 asm: wasm.AI64Load32U, 36341 reg: regInfo{ 36342 inputs: []inputInfo{ 36343 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36344 }, 36345 outputs: []outputInfo{ 36346 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36347 }, 36348 }, 36349 }, 36350 { 36351 name: "I64Load32S", 36352 auxType: auxInt64, 36353 argLen: 2, 36354 asm: wasm.AI64Load32S, 36355 reg: regInfo{ 36356 inputs: []inputInfo{ 36357 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36358 }, 36359 outputs: []outputInfo{ 36360 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36361 }, 36362 }, 36363 }, 36364 { 36365 name: "I64Load", 36366 auxType: auxInt64, 36367 argLen: 2, 36368 asm: wasm.AI64Load, 36369 reg: regInfo{ 36370 inputs: []inputInfo{ 36371 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36372 }, 36373 outputs: []outputInfo{ 36374 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36375 }, 36376 }, 36377 }, 36378 { 36379 name: "I64Store8", 36380 auxType: auxInt64, 36381 argLen: 3, 36382 asm: wasm.AI64Store8, 36383 reg: regInfo{ 36384 inputs: []inputInfo{ 36385 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36386 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36387 }, 36388 }, 36389 }, 36390 { 36391 name: "I64Store16", 36392 auxType: auxInt64, 36393 argLen: 3, 36394 asm: wasm.AI64Store16, 36395 reg: regInfo{ 36396 inputs: []inputInfo{ 36397 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36398 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36399 }, 36400 }, 36401 }, 36402 { 36403 name: "I64Store32", 36404 auxType: auxInt64, 36405 argLen: 3, 36406 asm: wasm.AI64Store32, 36407 reg: regInfo{ 36408 inputs: []inputInfo{ 36409 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36410 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36411 }, 36412 }, 36413 }, 36414 { 36415 name: "I64Store", 36416 auxType: auxInt64, 36417 argLen: 3, 36418 asm: wasm.AI64Store, 36419 reg: regInfo{ 36420 inputs: []inputInfo{ 36421 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36422 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36423 }, 36424 }, 36425 }, 36426 { 36427 name: "F32Load", 36428 auxType: auxInt64, 36429 argLen: 2, 36430 asm: wasm.AF32Load, 36431 reg: regInfo{ 36432 inputs: []inputInfo{ 36433 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36434 }, 36435 outputs: []outputInfo{ 36436 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36437 }, 36438 }, 36439 }, 36440 { 36441 name: "F64Load", 36442 auxType: auxInt64, 36443 argLen: 2, 36444 asm: wasm.AF64Load, 36445 reg: regInfo{ 36446 inputs: []inputInfo{ 36447 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36448 }, 36449 outputs: []outputInfo{ 36450 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36451 }, 36452 }, 36453 }, 36454 { 36455 name: "F32Store", 36456 auxType: auxInt64, 36457 argLen: 3, 36458 asm: wasm.AF32Store, 36459 reg: regInfo{ 36460 inputs: []inputInfo{ 36461 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36462 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36463 }, 36464 }, 36465 }, 36466 { 36467 name: "F64Store", 36468 auxType: auxInt64, 36469 argLen: 3, 36470 asm: wasm.AF64Store, 36471 reg: regInfo{ 36472 inputs: []inputInfo{ 36473 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36474 {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB 36475 }, 36476 }, 36477 }, 36478 { 36479 name: "I64Const", 36480 auxType: auxInt64, 36481 argLen: 0, 36482 rematerializeable: true, 36483 reg: regInfo{ 36484 outputs: []outputInfo{ 36485 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36486 }, 36487 }, 36488 }, 36489 { 36490 name: "F32Const", 36491 auxType: auxFloat32, 36492 argLen: 0, 36493 rematerializeable: true, 36494 reg: regInfo{ 36495 outputs: []outputInfo{ 36496 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36497 }, 36498 }, 36499 }, 36500 { 36501 name: "F64Const", 36502 auxType: auxFloat64, 36503 argLen: 0, 36504 rematerializeable: true, 36505 reg: regInfo{ 36506 outputs: []outputInfo{ 36507 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36508 }, 36509 }, 36510 }, 36511 { 36512 name: "I64Eqz", 36513 argLen: 1, 36514 asm: wasm.AI64Eqz, 36515 reg: regInfo{ 36516 inputs: []inputInfo{ 36517 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36518 }, 36519 outputs: []outputInfo{ 36520 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36521 }, 36522 }, 36523 }, 36524 { 36525 name: "I64Eq", 36526 argLen: 2, 36527 asm: wasm.AI64Eq, 36528 reg: regInfo{ 36529 inputs: []inputInfo{ 36530 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36531 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36532 }, 36533 outputs: []outputInfo{ 36534 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36535 }, 36536 }, 36537 }, 36538 { 36539 name: "I64Ne", 36540 argLen: 2, 36541 asm: wasm.AI64Ne, 36542 reg: regInfo{ 36543 inputs: []inputInfo{ 36544 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36545 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36546 }, 36547 outputs: []outputInfo{ 36548 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36549 }, 36550 }, 36551 }, 36552 { 36553 name: "I64LtS", 36554 argLen: 2, 36555 asm: wasm.AI64LtS, 36556 reg: regInfo{ 36557 inputs: []inputInfo{ 36558 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36559 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36560 }, 36561 outputs: []outputInfo{ 36562 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36563 }, 36564 }, 36565 }, 36566 { 36567 name: "I64LtU", 36568 argLen: 2, 36569 asm: wasm.AI64LtU, 36570 reg: regInfo{ 36571 inputs: []inputInfo{ 36572 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36573 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36574 }, 36575 outputs: []outputInfo{ 36576 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36577 }, 36578 }, 36579 }, 36580 { 36581 name: "I64GtS", 36582 argLen: 2, 36583 asm: wasm.AI64GtS, 36584 reg: regInfo{ 36585 inputs: []inputInfo{ 36586 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36587 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36588 }, 36589 outputs: []outputInfo{ 36590 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36591 }, 36592 }, 36593 }, 36594 { 36595 name: "I64GtU", 36596 argLen: 2, 36597 asm: wasm.AI64GtU, 36598 reg: regInfo{ 36599 inputs: []inputInfo{ 36600 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36601 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36602 }, 36603 outputs: []outputInfo{ 36604 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36605 }, 36606 }, 36607 }, 36608 { 36609 name: "I64LeS", 36610 argLen: 2, 36611 asm: wasm.AI64LeS, 36612 reg: regInfo{ 36613 inputs: []inputInfo{ 36614 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36615 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36616 }, 36617 outputs: []outputInfo{ 36618 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36619 }, 36620 }, 36621 }, 36622 { 36623 name: "I64LeU", 36624 argLen: 2, 36625 asm: wasm.AI64LeU, 36626 reg: regInfo{ 36627 inputs: []inputInfo{ 36628 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36629 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36630 }, 36631 outputs: []outputInfo{ 36632 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36633 }, 36634 }, 36635 }, 36636 { 36637 name: "I64GeS", 36638 argLen: 2, 36639 asm: wasm.AI64GeS, 36640 reg: regInfo{ 36641 inputs: []inputInfo{ 36642 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36643 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36644 }, 36645 outputs: []outputInfo{ 36646 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36647 }, 36648 }, 36649 }, 36650 { 36651 name: "I64GeU", 36652 argLen: 2, 36653 asm: wasm.AI64GeU, 36654 reg: regInfo{ 36655 inputs: []inputInfo{ 36656 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36657 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36658 }, 36659 outputs: []outputInfo{ 36660 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36661 }, 36662 }, 36663 }, 36664 { 36665 name: "F32Eq", 36666 argLen: 2, 36667 asm: wasm.AF32Eq, 36668 reg: regInfo{ 36669 inputs: []inputInfo{ 36670 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36671 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36672 }, 36673 outputs: []outputInfo{ 36674 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36675 }, 36676 }, 36677 }, 36678 { 36679 name: "F32Ne", 36680 argLen: 2, 36681 asm: wasm.AF32Ne, 36682 reg: regInfo{ 36683 inputs: []inputInfo{ 36684 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36685 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36686 }, 36687 outputs: []outputInfo{ 36688 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36689 }, 36690 }, 36691 }, 36692 { 36693 name: "F32Lt", 36694 argLen: 2, 36695 asm: wasm.AF32Lt, 36696 reg: regInfo{ 36697 inputs: []inputInfo{ 36698 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36699 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36700 }, 36701 outputs: []outputInfo{ 36702 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36703 }, 36704 }, 36705 }, 36706 { 36707 name: "F32Gt", 36708 argLen: 2, 36709 asm: wasm.AF32Gt, 36710 reg: regInfo{ 36711 inputs: []inputInfo{ 36712 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36713 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36714 }, 36715 outputs: []outputInfo{ 36716 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36717 }, 36718 }, 36719 }, 36720 { 36721 name: "F32Le", 36722 argLen: 2, 36723 asm: wasm.AF32Le, 36724 reg: regInfo{ 36725 inputs: []inputInfo{ 36726 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36727 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36728 }, 36729 outputs: []outputInfo{ 36730 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36731 }, 36732 }, 36733 }, 36734 { 36735 name: "F32Ge", 36736 argLen: 2, 36737 asm: wasm.AF32Ge, 36738 reg: regInfo{ 36739 inputs: []inputInfo{ 36740 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36741 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 36742 }, 36743 outputs: []outputInfo{ 36744 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36745 }, 36746 }, 36747 }, 36748 { 36749 name: "F64Eq", 36750 argLen: 2, 36751 asm: wasm.AF64Eq, 36752 reg: regInfo{ 36753 inputs: []inputInfo{ 36754 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36755 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36756 }, 36757 outputs: []outputInfo{ 36758 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36759 }, 36760 }, 36761 }, 36762 { 36763 name: "F64Ne", 36764 argLen: 2, 36765 asm: wasm.AF64Ne, 36766 reg: regInfo{ 36767 inputs: []inputInfo{ 36768 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36769 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36770 }, 36771 outputs: []outputInfo{ 36772 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36773 }, 36774 }, 36775 }, 36776 { 36777 name: "F64Lt", 36778 argLen: 2, 36779 asm: wasm.AF64Lt, 36780 reg: regInfo{ 36781 inputs: []inputInfo{ 36782 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36783 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36784 }, 36785 outputs: []outputInfo{ 36786 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36787 }, 36788 }, 36789 }, 36790 { 36791 name: "F64Gt", 36792 argLen: 2, 36793 asm: wasm.AF64Gt, 36794 reg: regInfo{ 36795 inputs: []inputInfo{ 36796 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36797 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36798 }, 36799 outputs: []outputInfo{ 36800 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36801 }, 36802 }, 36803 }, 36804 { 36805 name: "F64Le", 36806 argLen: 2, 36807 asm: wasm.AF64Le, 36808 reg: regInfo{ 36809 inputs: []inputInfo{ 36810 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36811 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36812 }, 36813 outputs: []outputInfo{ 36814 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36815 }, 36816 }, 36817 }, 36818 { 36819 name: "F64Ge", 36820 argLen: 2, 36821 asm: wasm.AF64Ge, 36822 reg: regInfo{ 36823 inputs: []inputInfo{ 36824 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36825 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 36826 }, 36827 outputs: []outputInfo{ 36828 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36829 }, 36830 }, 36831 }, 36832 { 36833 name: "I64Add", 36834 argLen: 2, 36835 asm: wasm.AI64Add, 36836 reg: regInfo{ 36837 inputs: []inputInfo{ 36838 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36839 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36840 }, 36841 outputs: []outputInfo{ 36842 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36843 }, 36844 }, 36845 }, 36846 { 36847 name: "I64AddConst", 36848 auxType: auxInt64, 36849 argLen: 1, 36850 asm: wasm.AI64Add, 36851 reg: regInfo{ 36852 inputs: []inputInfo{ 36853 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36854 }, 36855 outputs: []outputInfo{ 36856 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36857 }, 36858 }, 36859 }, 36860 { 36861 name: "I64Sub", 36862 argLen: 2, 36863 asm: wasm.AI64Sub, 36864 reg: regInfo{ 36865 inputs: []inputInfo{ 36866 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36867 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36868 }, 36869 outputs: []outputInfo{ 36870 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36871 }, 36872 }, 36873 }, 36874 { 36875 name: "I64Mul", 36876 argLen: 2, 36877 asm: wasm.AI64Mul, 36878 reg: regInfo{ 36879 inputs: []inputInfo{ 36880 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36881 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36882 }, 36883 outputs: []outputInfo{ 36884 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36885 }, 36886 }, 36887 }, 36888 { 36889 name: "I64DivS", 36890 argLen: 2, 36891 asm: wasm.AI64DivS, 36892 reg: regInfo{ 36893 inputs: []inputInfo{ 36894 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36895 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36896 }, 36897 outputs: []outputInfo{ 36898 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36899 }, 36900 }, 36901 }, 36902 { 36903 name: "I64DivU", 36904 argLen: 2, 36905 asm: wasm.AI64DivU, 36906 reg: regInfo{ 36907 inputs: []inputInfo{ 36908 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36909 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36910 }, 36911 outputs: []outputInfo{ 36912 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36913 }, 36914 }, 36915 }, 36916 { 36917 name: "I64RemS", 36918 argLen: 2, 36919 asm: wasm.AI64RemS, 36920 reg: regInfo{ 36921 inputs: []inputInfo{ 36922 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36923 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36924 }, 36925 outputs: []outputInfo{ 36926 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36927 }, 36928 }, 36929 }, 36930 { 36931 name: "I64RemU", 36932 argLen: 2, 36933 asm: wasm.AI64RemU, 36934 reg: regInfo{ 36935 inputs: []inputInfo{ 36936 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36937 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36938 }, 36939 outputs: []outputInfo{ 36940 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36941 }, 36942 }, 36943 }, 36944 { 36945 name: "I64And", 36946 argLen: 2, 36947 asm: wasm.AI64And, 36948 reg: regInfo{ 36949 inputs: []inputInfo{ 36950 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36951 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36952 }, 36953 outputs: []outputInfo{ 36954 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36955 }, 36956 }, 36957 }, 36958 { 36959 name: "I64Or", 36960 argLen: 2, 36961 asm: wasm.AI64Or, 36962 reg: regInfo{ 36963 inputs: []inputInfo{ 36964 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36965 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36966 }, 36967 outputs: []outputInfo{ 36968 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36969 }, 36970 }, 36971 }, 36972 { 36973 name: "I64Xor", 36974 argLen: 2, 36975 asm: wasm.AI64Xor, 36976 reg: regInfo{ 36977 inputs: []inputInfo{ 36978 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36979 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36980 }, 36981 outputs: []outputInfo{ 36982 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36983 }, 36984 }, 36985 }, 36986 { 36987 name: "I64Shl", 36988 argLen: 2, 36989 asm: wasm.AI64Shl, 36990 reg: regInfo{ 36991 inputs: []inputInfo{ 36992 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36993 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 36994 }, 36995 outputs: []outputInfo{ 36996 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 36997 }, 36998 }, 36999 }, 37000 { 37001 name: "I64ShrS", 37002 argLen: 2, 37003 asm: wasm.AI64ShrS, 37004 reg: regInfo{ 37005 inputs: []inputInfo{ 37006 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37007 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37008 }, 37009 outputs: []outputInfo{ 37010 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37011 }, 37012 }, 37013 }, 37014 { 37015 name: "I64ShrU", 37016 argLen: 2, 37017 asm: wasm.AI64ShrU, 37018 reg: regInfo{ 37019 inputs: []inputInfo{ 37020 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37021 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37022 }, 37023 outputs: []outputInfo{ 37024 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37025 }, 37026 }, 37027 }, 37028 { 37029 name: "F32Neg", 37030 argLen: 1, 37031 asm: wasm.AF32Neg, 37032 reg: regInfo{ 37033 inputs: []inputInfo{ 37034 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37035 }, 37036 outputs: []outputInfo{ 37037 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37038 }, 37039 }, 37040 }, 37041 { 37042 name: "F32Add", 37043 argLen: 2, 37044 asm: wasm.AF32Add, 37045 reg: regInfo{ 37046 inputs: []inputInfo{ 37047 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37048 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37049 }, 37050 outputs: []outputInfo{ 37051 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37052 }, 37053 }, 37054 }, 37055 { 37056 name: "F32Sub", 37057 argLen: 2, 37058 asm: wasm.AF32Sub, 37059 reg: regInfo{ 37060 inputs: []inputInfo{ 37061 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37062 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37063 }, 37064 outputs: []outputInfo{ 37065 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37066 }, 37067 }, 37068 }, 37069 { 37070 name: "F32Mul", 37071 argLen: 2, 37072 asm: wasm.AF32Mul, 37073 reg: regInfo{ 37074 inputs: []inputInfo{ 37075 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37076 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37077 }, 37078 outputs: []outputInfo{ 37079 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37080 }, 37081 }, 37082 }, 37083 { 37084 name: "F32Div", 37085 argLen: 2, 37086 asm: wasm.AF32Div, 37087 reg: regInfo{ 37088 inputs: []inputInfo{ 37089 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37090 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37091 }, 37092 outputs: []outputInfo{ 37093 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37094 }, 37095 }, 37096 }, 37097 { 37098 name: "F64Neg", 37099 argLen: 1, 37100 asm: wasm.AF64Neg, 37101 reg: regInfo{ 37102 inputs: []inputInfo{ 37103 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37104 }, 37105 outputs: []outputInfo{ 37106 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37107 }, 37108 }, 37109 }, 37110 { 37111 name: "F64Add", 37112 argLen: 2, 37113 asm: wasm.AF64Add, 37114 reg: regInfo{ 37115 inputs: []inputInfo{ 37116 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37117 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37118 }, 37119 outputs: []outputInfo{ 37120 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37121 }, 37122 }, 37123 }, 37124 { 37125 name: "F64Sub", 37126 argLen: 2, 37127 asm: wasm.AF64Sub, 37128 reg: regInfo{ 37129 inputs: []inputInfo{ 37130 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37131 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37132 }, 37133 outputs: []outputInfo{ 37134 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37135 }, 37136 }, 37137 }, 37138 { 37139 name: "F64Mul", 37140 argLen: 2, 37141 asm: wasm.AF64Mul, 37142 reg: regInfo{ 37143 inputs: []inputInfo{ 37144 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37145 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37146 }, 37147 outputs: []outputInfo{ 37148 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37149 }, 37150 }, 37151 }, 37152 { 37153 name: "F64Div", 37154 argLen: 2, 37155 asm: wasm.AF64Div, 37156 reg: regInfo{ 37157 inputs: []inputInfo{ 37158 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37159 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37160 }, 37161 outputs: []outputInfo{ 37162 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37163 }, 37164 }, 37165 }, 37166 { 37167 name: "I64TruncSatF64S", 37168 argLen: 1, 37169 asm: wasm.AI64TruncSatF64S, 37170 reg: regInfo{ 37171 inputs: []inputInfo{ 37172 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37173 }, 37174 outputs: []outputInfo{ 37175 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37176 }, 37177 }, 37178 }, 37179 { 37180 name: "I64TruncSatF64U", 37181 argLen: 1, 37182 asm: wasm.AI64TruncSatF64U, 37183 reg: regInfo{ 37184 inputs: []inputInfo{ 37185 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37186 }, 37187 outputs: []outputInfo{ 37188 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37189 }, 37190 }, 37191 }, 37192 { 37193 name: "I64TruncSatF32S", 37194 argLen: 1, 37195 asm: wasm.AI64TruncSatF32S, 37196 reg: regInfo{ 37197 inputs: []inputInfo{ 37198 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37199 }, 37200 outputs: []outputInfo{ 37201 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37202 }, 37203 }, 37204 }, 37205 { 37206 name: "I64TruncSatF32U", 37207 argLen: 1, 37208 asm: wasm.AI64TruncSatF32U, 37209 reg: regInfo{ 37210 inputs: []inputInfo{ 37211 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37212 }, 37213 outputs: []outputInfo{ 37214 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37215 }, 37216 }, 37217 }, 37218 { 37219 name: "F32ConvertI64S", 37220 argLen: 1, 37221 asm: wasm.AF32ConvertI64S, 37222 reg: regInfo{ 37223 inputs: []inputInfo{ 37224 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37225 }, 37226 outputs: []outputInfo{ 37227 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37228 }, 37229 }, 37230 }, 37231 { 37232 name: "F32ConvertI64U", 37233 argLen: 1, 37234 asm: wasm.AF32ConvertI64U, 37235 reg: regInfo{ 37236 inputs: []inputInfo{ 37237 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37238 }, 37239 outputs: []outputInfo{ 37240 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37241 }, 37242 }, 37243 }, 37244 { 37245 name: "F64ConvertI64S", 37246 argLen: 1, 37247 asm: wasm.AF64ConvertI64S, 37248 reg: regInfo{ 37249 inputs: []inputInfo{ 37250 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37251 }, 37252 outputs: []outputInfo{ 37253 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37254 }, 37255 }, 37256 }, 37257 { 37258 name: "F64ConvertI64U", 37259 argLen: 1, 37260 asm: wasm.AF64ConvertI64U, 37261 reg: regInfo{ 37262 inputs: []inputInfo{ 37263 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37264 }, 37265 outputs: []outputInfo{ 37266 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37267 }, 37268 }, 37269 }, 37270 { 37271 name: "F32DemoteF64", 37272 argLen: 1, 37273 asm: wasm.AF32DemoteF64, 37274 reg: regInfo{ 37275 inputs: []inputInfo{ 37276 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37277 }, 37278 outputs: []outputInfo{ 37279 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37280 }, 37281 }, 37282 }, 37283 { 37284 name: "F64PromoteF32", 37285 argLen: 1, 37286 asm: wasm.AF64PromoteF32, 37287 reg: regInfo{ 37288 inputs: []inputInfo{ 37289 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37290 }, 37291 outputs: []outputInfo{ 37292 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37293 }, 37294 }, 37295 }, 37296 { 37297 name: "I64Extend8S", 37298 argLen: 1, 37299 asm: wasm.AI64Extend8S, 37300 reg: regInfo{ 37301 inputs: []inputInfo{ 37302 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37303 }, 37304 outputs: []outputInfo{ 37305 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37306 }, 37307 }, 37308 }, 37309 { 37310 name: "I64Extend16S", 37311 argLen: 1, 37312 asm: wasm.AI64Extend16S, 37313 reg: regInfo{ 37314 inputs: []inputInfo{ 37315 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37316 }, 37317 outputs: []outputInfo{ 37318 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37319 }, 37320 }, 37321 }, 37322 { 37323 name: "I64Extend32S", 37324 argLen: 1, 37325 asm: wasm.AI64Extend32S, 37326 reg: regInfo{ 37327 inputs: []inputInfo{ 37328 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37329 }, 37330 outputs: []outputInfo{ 37331 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37332 }, 37333 }, 37334 }, 37335 { 37336 name: "F32Sqrt", 37337 argLen: 1, 37338 asm: wasm.AF32Sqrt, 37339 reg: regInfo{ 37340 inputs: []inputInfo{ 37341 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37342 }, 37343 outputs: []outputInfo{ 37344 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37345 }, 37346 }, 37347 }, 37348 { 37349 name: "F32Trunc", 37350 argLen: 1, 37351 asm: wasm.AF32Trunc, 37352 reg: regInfo{ 37353 inputs: []inputInfo{ 37354 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37355 }, 37356 outputs: []outputInfo{ 37357 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37358 }, 37359 }, 37360 }, 37361 { 37362 name: "F32Ceil", 37363 argLen: 1, 37364 asm: wasm.AF32Ceil, 37365 reg: regInfo{ 37366 inputs: []inputInfo{ 37367 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37368 }, 37369 outputs: []outputInfo{ 37370 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37371 }, 37372 }, 37373 }, 37374 { 37375 name: "F32Floor", 37376 argLen: 1, 37377 asm: wasm.AF32Floor, 37378 reg: regInfo{ 37379 inputs: []inputInfo{ 37380 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37381 }, 37382 outputs: []outputInfo{ 37383 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37384 }, 37385 }, 37386 }, 37387 { 37388 name: "F32Nearest", 37389 argLen: 1, 37390 asm: wasm.AF32Nearest, 37391 reg: regInfo{ 37392 inputs: []inputInfo{ 37393 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37394 }, 37395 outputs: []outputInfo{ 37396 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37397 }, 37398 }, 37399 }, 37400 { 37401 name: "F32Abs", 37402 argLen: 1, 37403 asm: wasm.AF32Abs, 37404 reg: regInfo{ 37405 inputs: []inputInfo{ 37406 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37407 }, 37408 outputs: []outputInfo{ 37409 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37410 }, 37411 }, 37412 }, 37413 { 37414 name: "F32Copysign", 37415 argLen: 2, 37416 asm: wasm.AF32Copysign, 37417 reg: regInfo{ 37418 inputs: []inputInfo{ 37419 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37420 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37421 }, 37422 outputs: []outputInfo{ 37423 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 37424 }, 37425 }, 37426 }, 37427 { 37428 name: "F64Sqrt", 37429 argLen: 1, 37430 asm: wasm.AF64Sqrt, 37431 reg: regInfo{ 37432 inputs: []inputInfo{ 37433 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37434 }, 37435 outputs: []outputInfo{ 37436 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37437 }, 37438 }, 37439 }, 37440 { 37441 name: "F64Trunc", 37442 argLen: 1, 37443 asm: wasm.AF64Trunc, 37444 reg: regInfo{ 37445 inputs: []inputInfo{ 37446 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37447 }, 37448 outputs: []outputInfo{ 37449 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37450 }, 37451 }, 37452 }, 37453 { 37454 name: "F64Ceil", 37455 argLen: 1, 37456 asm: wasm.AF64Ceil, 37457 reg: regInfo{ 37458 inputs: []inputInfo{ 37459 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37460 }, 37461 outputs: []outputInfo{ 37462 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37463 }, 37464 }, 37465 }, 37466 { 37467 name: "F64Floor", 37468 argLen: 1, 37469 asm: wasm.AF64Floor, 37470 reg: regInfo{ 37471 inputs: []inputInfo{ 37472 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37473 }, 37474 outputs: []outputInfo{ 37475 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37476 }, 37477 }, 37478 }, 37479 { 37480 name: "F64Nearest", 37481 argLen: 1, 37482 asm: wasm.AF64Nearest, 37483 reg: regInfo{ 37484 inputs: []inputInfo{ 37485 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37486 }, 37487 outputs: []outputInfo{ 37488 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37489 }, 37490 }, 37491 }, 37492 { 37493 name: "F64Abs", 37494 argLen: 1, 37495 asm: wasm.AF64Abs, 37496 reg: regInfo{ 37497 inputs: []inputInfo{ 37498 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37499 }, 37500 outputs: []outputInfo{ 37501 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37502 }, 37503 }, 37504 }, 37505 { 37506 name: "F64Copysign", 37507 argLen: 2, 37508 asm: wasm.AF64Copysign, 37509 reg: regInfo{ 37510 inputs: []inputInfo{ 37511 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37512 {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37513 }, 37514 outputs: []outputInfo{ 37515 {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 37516 }, 37517 }, 37518 }, 37519 { 37520 name: "I64Ctz", 37521 argLen: 1, 37522 asm: wasm.AI64Ctz, 37523 reg: regInfo{ 37524 inputs: []inputInfo{ 37525 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37526 }, 37527 outputs: []outputInfo{ 37528 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37529 }, 37530 }, 37531 }, 37532 { 37533 name: "I64Clz", 37534 argLen: 1, 37535 asm: wasm.AI64Clz, 37536 reg: regInfo{ 37537 inputs: []inputInfo{ 37538 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37539 }, 37540 outputs: []outputInfo{ 37541 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37542 }, 37543 }, 37544 }, 37545 { 37546 name: "I32Rotl", 37547 argLen: 2, 37548 asm: wasm.AI32Rotl, 37549 reg: regInfo{ 37550 inputs: []inputInfo{ 37551 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37552 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37553 }, 37554 outputs: []outputInfo{ 37555 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37556 }, 37557 }, 37558 }, 37559 { 37560 name: "I64Rotl", 37561 argLen: 2, 37562 asm: wasm.AI64Rotl, 37563 reg: regInfo{ 37564 inputs: []inputInfo{ 37565 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37566 {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37567 }, 37568 outputs: []outputInfo{ 37569 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37570 }, 37571 }, 37572 }, 37573 { 37574 name: "I64Popcnt", 37575 argLen: 1, 37576 asm: wasm.AI64Popcnt, 37577 reg: regInfo{ 37578 inputs: []inputInfo{ 37579 {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP 37580 }, 37581 outputs: []outputInfo{ 37582 {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 37583 }, 37584 }, 37585 }, 37586 37587 { 37588 name: "Add8", 37589 argLen: 2, 37590 commutative: true, 37591 generic: true, 37592 }, 37593 { 37594 name: "Add16", 37595 argLen: 2, 37596 commutative: true, 37597 generic: true, 37598 }, 37599 { 37600 name: "Add32", 37601 argLen: 2, 37602 commutative: true, 37603 generic: true, 37604 }, 37605 { 37606 name: "Add64", 37607 argLen: 2, 37608 commutative: true, 37609 generic: true, 37610 }, 37611 { 37612 name: "AddPtr", 37613 argLen: 2, 37614 generic: true, 37615 }, 37616 { 37617 name: "Add32F", 37618 argLen: 2, 37619 commutative: true, 37620 generic: true, 37621 }, 37622 { 37623 name: "Add64F", 37624 argLen: 2, 37625 commutative: true, 37626 generic: true, 37627 }, 37628 { 37629 name: "Sub8", 37630 argLen: 2, 37631 generic: true, 37632 }, 37633 { 37634 name: "Sub16", 37635 argLen: 2, 37636 generic: true, 37637 }, 37638 { 37639 name: "Sub32", 37640 argLen: 2, 37641 generic: true, 37642 }, 37643 { 37644 name: "Sub64", 37645 argLen: 2, 37646 generic: true, 37647 }, 37648 { 37649 name: "SubPtr", 37650 argLen: 2, 37651 generic: true, 37652 }, 37653 { 37654 name: "Sub32F", 37655 argLen: 2, 37656 generic: true, 37657 }, 37658 { 37659 name: "Sub64F", 37660 argLen: 2, 37661 generic: true, 37662 }, 37663 { 37664 name: "Mul8", 37665 argLen: 2, 37666 commutative: true, 37667 generic: true, 37668 }, 37669 { 37670 name: "Mul16", 37671 argLen: 2, 37672 commutative: true, 37673 generic: true, 37674 }, 37675 { 37676 name: "Mul32", 37677 argLen: 2, 37678 commutative: true, 37679 generic: true, 37680 }, 37681 { 37682 name: "Mul64", 37683 argLen: 2, 37684 commutative: true, 37685 generic: true, 37686 }, 37687 { 37688 name: "Mul32F", 37689 argLen: 2, 37690 commutative: true, 37691 generic: true, 37692 }, 37693 { 37694 name: "Mul64F", 37695 argLen: 2, 37696 commutative: true, 37697 generic: true, 37698 }, 37699 { 37700 name: "Div32F", 37701 argLen: 2, 37702 generic: true, 37703 }, 37704 { 37705 name: "Div64F", 37706 argLen: 2, 37707 generic: true, 37708 }, 37709 { 37710 name: "Hmul32", 37711 argLen: 2, 37712 commutative: true, 37713 generic: true, 37714 }, 37715 { 37716 name: "Hmul32u", 37717 argLen: 2, 37718 commutative: true, 37719 generic: true, 37720 }, 37721 { 37722 name: "Hmul64", 37723 argLen: 2, 37724 commutative: true, 37725 generic: true, 37726 }, 37727 { 37728 name: "Hmul64u", 37729 argLen: 2, 37730 commutative: true, 37731 generic: true, 37732 }, 37733 { 37734 name: "Mul32uhilo", 37735 argLen: 2, 37736 commutative: true, 37737 generic: true, 37738 }, 37739 { 37740 name: "Mul64uhilo", 37741 argLen: 2, 37742 commutative: true, 37743 generic: true, 37744 }, 37745 { 37746 name: "Mul32uover", 37747 argLen: 2, 37748 commutative: true, 37749 generic: true, 37750 }, 37751 { 37752 name: "Mul64uover", 37753 argLen: 2, 37754 commutative: true, 37755 generic: true, 37756 }, 37757 { 37758 name: "Avg32u", 37759 argLen: 2, 37760 generic: true, 37761 }, 37762 { 37763 name: "Avg64u", 37764 argLen: 2, 37765 generic: true, 37766 }, 37767 { 37768 name: "Div8", 37769 argLen: 2, 37770 generic: true, 37771 }, 37772 { 37773 name: "Div8u", 37774 argLen: 2, 37775 generic: true, 37776 }, 37777 { 37778 name: "Div16", 37779 auxType: auxBool, 37780 argLen: 2, 37781 generic: true, 37782 }, 37783 { 37784 name: "Div16u", 37785 argLen: 2, 37786 generic: true, 37787 }, 37788 { 37789 name: "Div32", 37790 auxType: auxBool, 37791 argLen: 2, 37792 generic: true, 37793 }, 37794 { 37795 name: "Div32u", 37796 argLen: 2, 37797 generic: true, 37798 }, 37799 { 37800 name: "Div64", 37801 auxType: auxBool, 37802 argLen: 2, 37803 generic: true, 37804 }, 37805 { 37806 name: "Div64u", 37807 argLen: 2, 37808 generic: true, 37809 }, 37810 { 37811 name: "Div128u", 37812 argLen: 3, 37813 generic: true, 37814 }, 37815 { 37816 name: "Mod8", 37817 argLen: 2, 37818 generic: true, 37819 }, 37820 { 37821 name: "Mod8u", 37822 argLen: 2, 37823 generic: true, 37824 }, 37825 { 37826 name: "Mod16", 37827 auxType: auxBool, 37828 argLen: 2, 37829 generic: true, 37830 }, 37831 { 37832 name: "Mod16u", 37833 argLen: 2, 37834 generic: true, 37835 }, 37836 { 37837 name: "Mod32", 37838 auxType: auxBool, 37839 argLen: 2, 37840 generic: true, 37841 }, 37842 { 37843 name: "Mod32u", 37844 argLen: 2, 37845 generic: true, 37846 }, 37847 { 37848 name: "Mod64", 37849 auxType: auxBool, 37850 argLen: 2, 37851 generic: true, 37852 }, 37853 { 37854 name: "Mod64u", 37855 argLen: 2, 37856 generic: true, 37857 }, 37858 { 37859 name: "And8", 37860 argLen: 2, 37861 commutative: true, 37862 generic: true, 37863 }, 37864 { 37865 name: "And16", 37866 argLen: 2, 37867 commutative: true, 37868 generic: true, 37869 }, 37870 { 37871 name: "And32", 37872 argLen: 2, 37873 commutative: true, 37874 generic: true, 37875 }, 37876 { 37877 name: "And64", 37878 argLen: 2, 37879 commutative: true, 37880 generic: true, 37881 }, 37882 { 37883 name: "Or8", 37884 argLen: 2, 37885 commutative: true, 37886 generic: true, 37887 }, 37888 { 37889 name: "Or16", 37890 argLen: 2, 37891 commutative: true, 37892 generic: true, 37893 }, 37894 { 37895 name: "Or32", 37896 argLen: 2, 37897 commutative: true, 37898 generic: true, 37899 }, 37900 { 37901 name: "Or64", 37902 argLen: 2, 37903 commutative: true, 37904 generic: true, 37905 }, 37906 { 37907 name: "Xor8", 37908 argLen: 2, 37909 commutative: true, 37910 generic: true, 37911 }, 37912 { 37913 name: "Xor16", 37914 argLen: 2, 37915 commutative: true, 37916 generic: true, 37917 }, 37918 { 37919 name: "Xor32", 37920 argLen: 2, 37921 commutative: true, 37922 generic: true, 37923 }, 37924 { 37925 name: "Xor64", 37926 argLen: 2, 37927 commutative: true, 37928 generic: true, 37929 }, 37930 { 37931 name: "Lsh8x8", 37932 auxType: auxBool, 37933 argLen: 2, 37934 generic: true, 37935 }, 37936 { 37937 name: "Lsh8x16", 37938 auxType: auxBool, 37939 argLen: 2, 37940 generic: true, 37941 }, 37942 { 37943 name: "Lsh8x32", 37944 auxType: auxBool, 37945 argLen: 2, 37946 generic: true, 37947 }, 37948 { 37949 name: "Lsh8x64", 37950 auxType: auxBool, 37951 argLen: 2, 37952 generic: true, 37953 }, 37954 { 37955 name: "Lsh16x8", 37956 auxType: auxBool, 37957 argLen: 2, 37958 generic: true, 37959 }, 37960 { 37961 name: "Lsh16x16", 37962 auxType: auxBool, 37963 argLen: 2, 37964 generic: true, 37965 }, 37966 { 37967 name: "Lsh16x32", 37968 auxType: auxBool, 37969 argLen: 2, 37970 generic: true, 37971 }, 37972 { 37973 name: "Lsh16x64", 37974 auxType: auxBool, 37975 argLen: 2, 37976 generic: true, 37977 }, 37978 { 37979 name: "Lsh32x8", 37980 auxType: auxBool, 37981 argLen: 2, 37982 generic: true, 37983 }, 37984 { 37985 name: "Lsh32x16", 37986 auxType: auxBool, 37987 argLen: 2, 37988 generic: true, 37989 }, 37990 { 37991 name: "Lsh32x32", 37992 auxType: auxBool, 37993 argLen: 2, 37994 generic: true, 37995 }, 37996 { 37997 name: "Lsh32x64", 37998 auxType: auxBool, 37999 argLen: 2, 38000 generic: true, 38001 }, 38002 { 38003 name: "Lsh64x8", 38004 auxType: auxBool, 38005 argLen: 2, 38006 generic: true, 38007 }, 38008 { 38009 name: "Lsh64x16", 38010 auxType: auxBool, 38011 argLen: 2, 38012 generic: true, 38013 }, 38014 { 38015 name: "Lsh64x32", 38016 auxType: auxBool, 38017 argLen: 2, 38018 generic: true, 38019 }, 38020 { 38021 name: "Lsh64x64", 38022 auxType: auxBool, 38023 argLen: 2, 38024 generic: true, 38025 }, 38026 { 38027 name: "Rsh8x8", 38028 auxType: auxBool, 38029 argLen: 2, 38030 generic: true, 38031 }, 38032 { 38033 name: "Rsh8x16", 38034 auxType: auxBool, 38035 argLen: 2, 38036 generic: true, 38037 }, 38038 { 38039 name: "Rsh8x32", 38040 auxType: auxBool, 38041 argLen: 2, 38042 generic: true, 38043 }, 38044 { 38045 name: "Rsh8x64", 38046 auxType: auxBool, 38047 argLen: 2, 38048 generic: true, 38049 }, 38050 { 38051 name: "Rsh16x8", 38052 auxType: auxBool, 38053 argLen: 2, 38054 generic: true, 38055 }, 38056 { 38057 name: "Rsh16x16", 38058 auxType: auxBool, 38059 argLen: 2, 38060 generic: true, 38061 }, 38062 { 38063 name: "Rsh16x32", 38064 auxType: auxBool, 38065 argLen: 2, 38066 generic: true, 38067 }, 38068 { 38069 name: "Rsh16x64", 38070 auxType: auxBool, 38071 argLen: 2, 38072 generic: true, 38073 }, 38074 { 38075 name: "Rsh32x8", 38076 auxType: auxBool, 38077 argLen: 2, 38078 generic: true, 38079 }, 38080 { 38081 name: "Rsh32x16", 38082 auxType: auxBool, 38083 argLen: 2, 38084 generic: true, 38085 }, 38086 { 38087 name: "Rsh32x32", 38088 auxType: auxBool, 38089 argLen: 2, 38090 generic: true, 38091 }, 38092 { 38093 name: "Rsh32x64", 38094 auxType: auxBool, 38095 argLen: 2, 38096 generic: true, 38097 }, 38098 { 38099 name: "Rsh64x8", 38100 auxType: auxBool, 38101 argLen: 2, 38102 generic: true, 38103 }, 38104 { 38105 name: "Rsh64x16", 38106 auxType: auxBool, 38107 argLen: 2, 38108 generic: true, 38109 }, 38110 { 38111 name: "Rsh64x32", 38112 auxType: auxBool, 38113 argLen: 2, 38114 generic: true, 38115 }, 38116 { 38117 name: "Rsh64x64", 38118 auxType: auxBool, 38119 argLen: 2, 38120 generic: true, 38121 }, 38122 { 38123 name: "Rsh8Ux8", 38124 auxType: auxBool, 38125 argLen: 2, 38126 generic: true, 38127 }, 38128 { 38129 name: "Rsh8Ux16", 38130 auxType: auxBool, 38131 argLen: 2, 38132 generic: true, 38133 }, 38134 { 38135 name: "Rsh8Ux32", 38136 auxType: auxBool, 38137 argLen: 2, 38138 generic: true, 38139 }, 38140 { 38141 name: "Rsh8Ux64", 38142 auxType: auxBool, 38143 argLen: 2, 38144 generic: true, 38145 }, 38146 { 38147 name: "Rsh16Ux8", 38148 auxType: auxBool, 38149 argLen: 2, 38150 generic: true, 38151 }, 38152 { 38153 name: "Rsh16Ux16", 38154 auxType: auxBool, 38155 argLen: 2, 38156 generic: true, 38157 }, 38158 { 38159 name: "Rsh16Ux32", 38160 auxType: auxBool, 38161 argLen: 2, 38162 generic: true, 38163 }, 38164 { 38165 name: "Rsh16Ux64", 38166 auxType: auxBool, 38167 argLen: 2, 38168 generic: true, 38169 }, 38170 { 38171 name: "Rsh32Ux8", 38172 auxType: auxBool, 38173 argLen: 2, 38174 generic: true, 38175 }, 38176 { 38177 name: "Rsh32Ux16", 38178 auxType: auxBool, 38179 argLen: 2, 38180 generic: true, 38181 }, 38182 { 38183 name: "Rsh32Ux32", 38184 auxType: auxBool, 38185 argLen: 2, 38186 generic: true, 38187 }, 38188 { 38189 name: "Rsh32Ux64", 38190 auxType: auxBool, 38191 argLen: 2, 38192 generic: true, 38193 }, 38194 { 38195 name: "Rsh64Ux8", 38196 auxType: auxBool, 38197 argLen: 2, 38198 generic: true, 38199 }, 38200 { 38201 name: "Rsh64Ux16", 38202 auxType: auxBool, 38203 argLen: 2, 38204 generic: true, 38205 }, 38206 { 38207 name: "Rsh64Ux32", 38208 auxType: auxBool, 38209 argLen: 2, 38210 generic: true, 38211 }, 38212 { 38213 name: "Rsh64Ux64", 38214 auxType: auxBool, 38215 argLen: 2, 38216 generic: true, 38217 }, 38218 { 38219 name: "Eq8", 38220 argLen: 2, 38221 commutative: true, 38222 generic: true, 38223 }, 38224 { 38225 name: "Eq16", 38226 argLen: 2, 38227 commutative: true, 38228 generic: true, 38229 }, 38230 { 38231 name: "Eq32", 38232 argLen: 2, 38233 commutative: true, 38234 generic: true, 38235 }, 38236 { 38237 name: "Eq64", 38238 argLen: 2, 38239 commutative: true, 38240 generic: true, 38241 }, 38242 { 38243 name: "EqPtr", 38244 argLen: 2, 38245 commutative: true, 38246 generic: true, 38247 }, 38248 { 38249 name: "EqInter", 38250 argLen: 2, 38251 generic: true, 38252 }, 38253 { 38254 name: "EqSlice", 38255 argLen: 2, 38256 generic: true, 38257 }, 38258 { 38259 name: "Eq32F", 38260 argLen: 2, 38261 commutative: true, 38262 generic: true, 38263 }, 38264 { 38265 name: "Eq64F", 38266 argLen: 2, 38267 commutative: true, 38268 generic: true, 38269 }, 38270 { 38271 name: "Neq8", 38272 argLen: 2, 38273 commutative: true, 38274 generic: true, 38275 }, 38276 { 38277 name: "Neq16", 38278 argLen: 2, 38279 commutative: true, 38280 generic: true, 38281 }, 38282 { 38283 name: "Neq32", 38284 argLen: 2, 38285 commutative: true, 38286 generic: true, 38287 }, 38288 { 38289 name: "Neq64", 38290 argLen: 2, 38291 commutative: true, 38292 generic: true, 38293 }, 38294 { 38295 name: "NeqPtr", 38296 argLen: 2, 38297 commutative: true, 38298 generic: true, 38299 }, 38300 { 38301 name: "NeqInter", 38302 argLen: 2, 38303 generic: true, 38304 }, 38305 { 38306 name: "NeqSlice", 38307 argLen: 2, 38308 generic: true, 38309 }, 38310 { 38311 name: "Neq32F", 38312 argLen: 2, 38313 commutative: true, 38314 generic: true, 38315 }, 38316 { 38317 name: "Neq64F", 38318 argLen: 2, 38319 commutative: true, 38320 generic: true, 38321 }, 38322 { 38323 name: "Less8", 38324 argLen: 2, 38325 generic: true, 38326 }, 38327 { 38328 name: "Less8U", 38329 argLen: 2, 38330 generic: true, 38331 }, 38332 { 38333 name: "Less16", 38334 argLen: 2, 38335 generic: true, 38336 }, 38337 { 38338 name: "Less16U", 38339 argLen: 2, 38340 generic: true, 38341 }, 38342 { 38343 name: "Less32", 38344 argLen: 2, 38345 generic: true, 38346 }, 38347 { 38348 name: "Less32U", 38349 argLen: 2, 38350 generic: true, 38351 }, 38352 { 38353 name: "Less64", 38354 argLen: 2, 38355 generic: true, 38356 }, 38357 { 38358 name: "Less64U", 38359 argLen: 2, 38360 generic: true, 38361 }, 38362 { 38363 name: "Less32F", 38364 argLen: 2, 38365 generic: true, 38366 }, 38367 { 38368 name: "Less64F", 38369 argLen: 2, 38370 generic: true, 38371 }, 38372 { 38373 name: "Leq8", 38374 argLen: 2, 38375 generic: true, 38376 }, 38377 { 38378 name: "Leq8U", 38379 argLen: 2, 38380 generic: true, 38381 }, 38382 { 38383 name: "Leq16", 38384 argLen: 2, 38385 generic: true, 38386 }, 38387 { 38388 name: "Leq16U", 38389 argLen: 2, 38390 generic: true, 38391 }, 38392 { 38393 name: "Leq32", 38394 argLen: 2, 38395 generic: true, 38396 }, 38397 { 38398 name: "Leq32U", 38399 argLen: 2, 38400 generic: true, 38401 }, 38402 { 38403 name: "Leq64", 38404 argLen: 2, 38405 generic: true, 38406 }, 38407 { 38408 name: "Leq64U", 38409 argLen: 2, 38410 generic: true, 38411 }, 38412 { 38413 name: "Leq32F", 38414 argLen: 2, 38415 generic: true, 38416 }, 38417 { 38418 name: "Leq64F", 38419 argLen: 2, 38420 generic: true, 38421 }, 38422 { 38423 name: "CondSelect", 38424 argLen: 3, 38425 generic: true, 38426 }, 38427 { 38428 name: "AndB", 38429 argLen: 2, 38430 commutative: true, 38431 generic: true, 38432 }, 38433 { 38434 name: "OrB", 38435 argLen: 2, 38436 commutative: true, 38437 generic: true, 38438 }, 38439 { 38440 name: "EqB", 38441 argLen: 2, 38442 commutative: true, 38443 generic: true, 38444 }, 38445 { 38446 name: "NeqB", 38447 argLen: 2, 38448 commutative: true, 38449 generic: true, 38450 }, 38451 { 38452 name: "Not", 38453 argLen: 1, 38454 generic: true, 38455 }, 38456 { 38457 name: "Neg8", 38458 argLen: 1, 38459 generic: true, 38460 }, 38461 { 38462 name: "Neg16", 38463 argLen: 1, 38464 generic: true, 38465 }, 38466 { 38467 name: "Neg32", 38468 argLen: 1, 38469 generic: true, 38470 }, 38471 { 38472 name: "Neg64", 38473 argLen: 1, 38474 generic: true, 38475 }, 38476 { 38477 name: "Neg32F", 38478 argLen: 1, 38479 generic: true, 38480 }, 38481 { 38482 name: "Neg64F", 38483 argLen: 1, 38484 generic: true, 38485 }, 38486 { 38487 name: "Com8", 38488 argLen: 1, 38489 generic: true, 38490 }, 38491 { 38492 name: "Com16", 38493 argLen: 1, 38494 generic: true, 38495 }, 38496 { 38497 name: "Com32", 38498 argLen: 1, 38499 generic: true, 38500 }, 38501 { 38502 name: "Com64", 38503 argLen: 1, 38504 generic: true, 38505 }, 38506 { 38507 name: "Ctz8", 38508 argLen: 1, 38509 generic: true, 38510 }, 38511 { 38512 name: "Ctz16", 38513 argLen: 1, 38514 generic: true, 38515 }, 38516 { 38517 name: "Ctz32", 38518 argLen: 1, 38519 generic: true, 38520 }, 38521 { 38522 name: "Ctz64", 38523 argLen: 1, 38524 generic: true, 38525 }, 38526 { 38527 name: "Ctz8NonZero", 38528 argLen: 1, 38529 generic: true, 38530 }, 38531 { 38532 name: "Ctz16NonZero", 38533 argLen: 1, 38534 generic: true, 38535 }, 38536 { 38537 name: "Ctz32NonZero", 38538 argLen: 1, 38539 generic: true, 38540 }, 38541 { 38542 name: "Ctz64NonZero", 38543 argLen: 1, 38544 generic: true, 38545 }, 38546 { 38547 name: "BitLen8", 38548 argLen: 1, 38549 generic: true, 38550 }, 38551 { 38552 name: "BitLen16", 38553 argLen: 1, 38554 generic: true, 38555 }, 38556 { 38557 name: "BitLen32", 38558 argLen: 1, 38559 generic: true, 38560 }, 38561 { 38562 name: "BitLen64", 38563 argLen: 1, 38564 generic: true, 38565 }, 38566 { 38567 name: "Bswap32", 38568 argLen: 1, 38569 generic: true, 38570 }, 38571 { 38572 name: "Bswap64", 38573 argLen: 1, 38574 generic: true, 38575 }, 38576 { 38577 name: "BitRev8", 38578 argLen: 1, 38579 generic: true, 38580 }, 38581 { 38582 name: "BitRev16", 38583 argLen: 1, 38584 generic: true, 38585 }, 38586 { 38587 name: "BitRev32", 38588 argLen: 1, 38589 generic: true, 38590 }, 38591 { 38592 name: "BitRev64", 38593 argLen: 1, 38594 generic: true, 38595 }, 38596 { 38597 name: "PopCount8", 38598 argLen: 1, 38599 generic: true, 38600 }, 38601 { 38602 name: "PopCount16", 38603 argLen: 1, 38604 generic: true, 38605 }, 38606 { 38607 name: "PopCount32", 38608 argLen: 1, 38609 generic: true, 38610 }, 38611 { 38612 name: "PopCount64", 38613 argLen: 1, 38614 generic: true, 38615 }, 38616 { 38617 name: "RotateLeft64", 38618 argLen: 2, 38619 generic: true, 38620 }, 38621 { 38622 name: "RotateLeft32", 38623 argLen: 2, 38624 generic: true, 38625 }, 38626 { 38627 name: "RotateLeft16", 38628 argLen: 2, 38629 generic: true, 38630 }, 38631 { 38632 name: "RotateLeft8", 38633 argLen: 2, 38634 generic: true, 38635 }, 38636 { 38637 name: "Sqrt", 38638 argLen: 1, 38639 generic: true, 38640 }, 38641 { 38642 name: "Sqrt32", 38643 argLen: 1, 38644 generic: true, 38645 }, 38646 { 38647 name: "Floor", 38648 argLen: 1, 38649 generic: true, 38650 }, 38651 { 38652 name: "Ceil", 38653 argLen: 1, 38654 generic: true, 38655 }, 38656 { 38657 name: "Trunc", 38658 argLen: 1, 38659 generic: true, 38660 }, 38661 { 38662 name: "Round", 38663 argLen: 1, 38664 generic: true, 38665 }, 38666 { 38667 name: "RoundToEven", 38668 argLen: 1, 38669 generic: true, 38670 }, 38671 { 38672 name: "Abs", 38673 argLen: 1, 38674 generic: true, 38675 }, 38676 { 38677 name: "Copysign", 38678 argLen: 2, 38679 generic: true, 38680 }, 38681 { 38682 name: "FMA", 38683 argLen: 3, 38684 generic: true, 38685 }, 38686 { 38687 name: "Phi", 38688 argLen: -1, 38689 zeroWidth: true, 38690 generic: true, 38691 }, 38692 { 38693 name: "Copy", 38694 argLen: 1, 38695 generic: true, 38696 }, 38697 { 38698 name: "Convert", 38699 argLen: 2, 38700 resultInArg0: true, 38701 zeroWidth: true, 38702 generic: true, 38703 }, 38704 { 38705 name: "ConstBool", 38706 auxType: auxBool, 38707 argLen: 0, 38708 generic: true, 38709 }, 38710 { 38711 name: "ConstString", 38712 auxType: auxString, 38713 argLen: 0, 38714 generic: true, 38715 }, 38716 { 38717 name: "ConstNil", 38718 argLen: 0, 38719 generic: true, 38720 }, 38721 { 38722 name: "Const8", 38723 auxType: auxInt8, 38724 argLen: 0, 38725 generic: true, 38726 }, 38727 { 38728 name: "Const16", 38729 auxType: auxInt16, 38730 argLen: 0, 38731 generic: true, 38732 }, 38733 { 38734 name: "Const32", 38735 auxType: auxInt32, 38736 argLen: 0, 38737 generic: true, 38738 }, 38739 { 38740 name: "Const64", 38741 auxType: auxInt64, 38742 argLen: 0, 38743 generic: true, 38744 }, 38745 { 38746 name: "Const32F", 38747 auxType: auxFloat32, 38748 argLen: 0, 38749 generic: true, 38750 }, 38751 { 38752 name: "Const64F", 38753 auxType: auxFloat64, 38754 argLen: 0, 38755 generic: true, 38756 }, 38757 { 38758 name: "ConstInterface", 38759 argLen: 0, 38760 generic: true, 38761 }, 38762 { 38763 name: "ConstSlice", 38764 argLen: 0, 38765 generic: true, 38766 }, 38767 { 38768 name: "InitMem", 38769 argLen: 0, 38770 zeroWidth: true, 38771 generic: true, 38772 }, 38773 { 38774 name: "Arg", 38775 auxType: auxSymOff, 38776 argLen: 0, 38777 zeroWidth: true, 38778 symEffect: SymRead, 38779 generic: true, 38780 }, 38781 { 38782 name: "ArgIntReg", 38783 auxType: auxNameOffsetInt8, 38784 argLen: 0, 38785 zeroWidth: true, 38786 generic: true, 38787 }, 38788 { 38789 name: "ArgFloatReg", 38790 auxType: auxNameOffsetInt8, 38791 argLen: 0, 38792 zeroWidth: true, 38793 generic: true, 38794 }, 38795 { 38796 name: "Addr", 38797 auxType: auxSym, 38798 argLen: 1, 38799 symEffect: SymAddr, 38800 generic: true, 38801 }, 38802 { 38803 name: "LocalAddr", 38804 auxType: auxSym, 38805 argLen: 2, 38806 symEffect: SymAddr, 38807 generic: true, 38808 }, 38809 { 38810 name: "SP", 38811 argLen: 0, 38812 zeroWidth: true, 38813 generic: true, 38814 }, 38815 { 38816 name: "SB", 38817 argLen: 0, 38818 zeroWidth: true, 38819 generic: true, 38820 }, 38821 { 38822 name: "Load", 38823 argLen: 2, 38824 generic: true, 38825 }, 38826 { 38827 name: "Dereference", 38828 argLen: 2, 38829 generic: true, 38830 }, 38831 { 38832 name: "Store", 38833 auxType: auxTyp, 38834 argLen: 3, 38835 generic: true, 38836 }, 38837 { 38838 name: "Move", 38839 auxType: auxTypSize, 38840 argLen: 3, 38841 generic: true, 38842 }, 38843 { 38844 name: "Zero", 38845 auxType: auxTypSize, 38846 argLen: 2, 38847 generic: true, 38848 }, 38849 { 38850 name: "StoreWB", 38851 auxType: auxTyp, 38852 argLen: 3, 38853 generic: true, 38854 }, 38855 { 38856 name: "MoveWB", 38857 auxType: auxTypSize, 38858 argLen: 3, 38859 generic: true, 38860 }, 38861 { 38862 name: "ZeroWB", 38863 auxType: auxTypSize, 38864 argLen: 2, 38865 generic: true, 38866 }, 38867 { 38868 name: "WB", 38869 auxType: auxSym, 38870 argLen: 3, 38871 symEffect: SymNone, 38872 generic: true, 38873 }, 38874 { 38875 name: "HasCPUFeature", 38876 auxType: auxSym, 38877 argLen: 0, 38878 symEffect: SymNone, 38879 generic: true, 38880 }, 38881 { 38882 name: "PanicBounds", 38883 auxType: auxInt64, 38884 argLen: 3, 38885 call: true, 38886 generic: true, 38887 }, 38888 { 38889 name: "PanicExtend", 38890 auxType: auxInt64, 38891 argLen: 4, 38892 call: true, 38893 generic: true, 38894 }, 38895 { 38896 name: "ClosureCall", 38897 auxType: auxCallOff, 38898 argLen: -1, 38899 call: true, 38900 generic: true, 38901 }, 38902 { 38903 name: "StaticCall", 38904 auxType: auxCallOff, 38905 argLen: -1, 38906 call: true, 38907 generic: true, 38908 }, 38909 { 38910 name: "InterCall", 38911 auxType: auxCallOff, 38912 argLen: -1, 38913 call: true, 38914 generic: true, 38915 }, 38916 { 38917 name: "TailCall", 38918 auxType: auxCallOff, 38919 argLen: -1, 38920 call: true, 38921 generic: true, 38922 }, 38923 { 38924 name: "ClosureLECall", 38925 auxType: auxCallOff, 38926 argLen: -1, 38927 call: true, 38928 generic: true, 38929 }, 38930 { 38931 name: "StaticLECall", 38932 auxType: auxCallOff, 38933 argLen: -1, 38934 call: true, 38935 generic: true, 38936 }, 38937 { 38938 name: "InterLECall", 38939 auxType: auxCallOff, 38940 argLen: -1, 38941 call: true, 38942 generic: true, 38943 }, 38944 { 38945 name: "TailLECall", 38946 auxType: auxCallOff, 38947 argLen: -1, 38948 call: true, 38949 generic: true, 38950 }, 38951 { 38952 name: "SignExt8to16", 38953 argLen: 1, 38954 generic: true, 38955 }, 38956 { 38957 name: "SignExt8to32", 38958 argLen: 1, 38959 generic: true, 38960 }, 38961 { 38962 name: "SignExt8to64", 38963 argLen: 1, 38964 generic: true, 38965 }, 38966 { 38967 name: "SignExt16to32", 38968 argLen: 1, 38969 generic: true, 38970 }, 38971 { 38972 name: "SignExt16to64", 38973 argLen: 1, 38974 generic: true, 38975 }, 38976 { 38977 name: "SignExt32to64", 38978 argLen: 1, 38979 generic: true, 38980 }, 38981 { 38982 name: "ZeroExt8to16", 38983 argLen: 1, 38984 generic: true, 38985 }, 38986 { 38987 name: "ZeroExt8to32", 38988 argLen: 1, 38989 generic: true, 38990 }, 38991 { 38992 name: "ZeroExt8to64", 38993 argLen: 1, 38994 generic: true, 38995 }, 38996 { 38997 name: "ZeroExt16to32", 38998 argLen: 1, 38999 generic: true, 39000 }, 39001 { 39002 name: "ZeroExt16to64", 39003 argLen: 1, 39004 generic: true, 39005 }, 39006 { 39007 name: "ZeroExt32to64", 39008 argLen: 1, 39009 generic: true, 39010 }, 39011 { 39012 name: "Trunc16to8", 39013 argLen: 1, 39014 generic: true, 39015 }, 39016 { 39017 name: "Trunc32to8", 39018 argLen: 1, 39019 generic: true, 39020 }, 39021 { 39022 name: "Trunc32to16", 39023 argLen: 1, 39024 generic: true, 39025 }, 39026 { 39027 name: "Trunc64to8", 39028 argLen: 1, 39029 generic: true, 39030 }, 39031 { 39032 name: "Trunc64to16", 39033 argLen: 1, 39034 generic: true, 39035 }, 39036 { 39037 name: "Trunc64to32", 39038 argLen: 1, 39039 generic: true, 39040 }, 39041 { 39042 name: "Cvt32to32F", 39043 argLen: 1, 39044 generic: true, 39045 }, 39046 { 39047 name: "Cvt32to64F", 39048 argLen: 1, 39049 generic: true, 39050 }, 39051 { 39052 name: "Cvt64to32F", 39053 argLen: 1, 39054 generic: true, 39055 }, 39056 { 39057 name: "Cvt64to64F", 39058 argLen: 1, 39059 generic: true, 39060 }, 39061 { 39062 name: "Cvt32Fto32", 39063 argLen: 1, 39064 generic: true, 39065 }, 39066 { 39067 name: "Cvt32Fto64", 39068 argLen: 1, 39069 generic: true, 39070 }, 39071 { 39072 name: "Cvt64Fto32", 39073 argLen: 1, 39074 generic: true, 39075 }, 39076 { 39077 name: "Cvt64Fto64", 39078 argLen: 1, 39079 generic: true, 39080 }, 39081 { 39082 name: "Cvt32Fto64F", 39083 argLen: 1, 39084 generic: true, 39085 }, 39086 { 39087 name: "Cvt64Fto32F", 39088 argLen: 1, 39089 generic: true, 39090 }, 39091 { 39092 name: "CvtBoolToUint8", 39093 argLen: 1, 39094 generic: true, 39095 }, 39096 { 39097 name: "Round32F", 39098 argLen: 1, 39099 generic: true, 39100 }, 39101 { 39102 name: "Round64F", 39103 argLen: 1, 39104 generic: true, 39105 }, 39106 { 39107 name: "IsNonNil", 39108 argLen: 1, 39109 generic: true, 39110 }, 39111 { 39112 name: "IsInBounds", 39113 argLen: 2, 39114 generic: true, 39115 }, 39116 { 39117 name: "IsSliceInBounds", 39118 argLen: 2, 39119 generic: true, 39120 }, 39121 { 39122 name: "NilCheck", 39123 argLen: 2, 39124 generic: true, 39125 }, 39126 { 39127 name: "GetG", 39128 argLen: 1, 39129 zeroWidth: true, 39130 generic: true, 39131 }, 39132 { 39133 name: "GetClosurePtr", 39134 argLen: 0, 39135 generic: true, 39136 }, 39137 { 39138 name: "GetCallerPC", 39139 argLen: 0, 39140 generic: true, 39141 }, 39142 { 39143 name: "GetCallerSP", 39144 argLen: 0, 39145 generic: true, 39146 }, 39147 { 39148 name: "PtrIndex", 39149 argLen: 2, 39150 generic: true, 39151 }, 39152 { 39153 name: "OffPtr", 39154 auxType: auxInt64, 39155 argLen: 1, 39156 generic: true, 39157 }, 39158 { 39159 name: "SliceMake", 39160 argLen: 3, 39161 generic: true, 39162 }, 39163 { 39164 name: "SlicePtr", 39165 argLen: 1, 39166 generic: true, 39167 }, 39168 { 39169 name: "SliceLen", 39170 argLen: 1, 39171 generic: true, 39172 }, 39173 { 39174 name: "SliceCap", 39175 argLen: 1, 39176 generic: true, 39177 }, 39178 { 39179 name: "SlicePtrUnchecked", 39180 argLen: 1, 39181 generic: true, 39182 }, 39183 { 39184 name: "ComplexMake", 39185 argLen: 2, 39186 generic: true, 39187 }, 39188 { 39189 name: "ComplexReal", 39190 argLen: 1, 39191 generic: true, 39192 }, 39193 { 39194 name: "ComplexImag", 39195 argLen: 1, 39196 generic: true, 39197 }, 39198 { 39199 name: "StringMake", 39200 argLen: 2, 39201 generic: true, 39202 }, 39203 { 39204 name: "StringPtr", 39205 argLen: 1, 39206 generic: true, 39207 }, 39208 { 39209 name: "StringLen", 39210 argLen: 1, 39211 generic: true, 39212 }, 39213 { 39214 name: "IMake", 39215 argLen: 2, 39216 generic: true, 39217 }, 39218 { 39219 name: "ITab", 39220 argLen: 1, 39221 generic: true, 39222 }, 39223 { 39224 name: "IData", 39225 argLen: 1, 39226 generic: true, 39227 }, 39228 { 39229 name: "StructMake0", 39230 argLen: 0, 39231 generic: true, 39232 }, 39233 { 39234 name: "StructMake1", 39235 argLen: 1, 39236 generic: true, 39237 }, 39238 { 39239 name: "StructMake2", 39240 argLen: 2, 39241 generic: true, 39242 }, 39243 { 39244 name: "StructMake3", 39245 argLen: 3, 39246 generic: true, 39247 }, 39248 { 39249 name: "StructMake4", 39250 argLen: 4, 39251 generic: true, 39252 }, 39253 { 39254 name: "StructSelect", 39255 auxType: auxInt64, 39256 argLen: 1, 39257 generic: true, 39258 }, 39259 { 39260 name: "ArrayMake0", 39261 argLen: 0, 39262 generic: true, 39263 }, 39264 { 39265 name: "ArrayMake1", 39266 argLen: 1, 39267 generic: true, 39268 }, 39269 { 39270 name: "ArraySelect", 39271 auxType: auxInt64, 39272 argLen: 1, 39273 generic: true, 39274 }, 39275 { 39276 name: "StoreReg", 39277 argLen: 1, 39278 generic: true, 39279 }, 39280 { 39281 name: "LoadReg", 39282 argLen: 1, 39283 generic: true, 39284 }, 39285 { 39286 name: "FwdRef", 39287 auxType: auxSym, 39288 argLen: 0, 39289 symEffect: SymNone, 39290 generic: true, 39291 }, 39292 { 39293 name: "Unknown", 39294 argLen: 0, 39295 generic: true, 39296 }, 39297 { 39298 name: "VarDef", 39299 auxType: auxSym, 39300 argLen: 1, 39301 zeroWidth: true, 39302 symEffect: SymNone, 39303 generic: true, 39304 }, 39305 { 39306 name: "VarLive", 39307 auxType: auxSym, 39308 argLen: 1, 39309 zeroWidth: true, 39310 symEffect: SymRead, 39311 generic: true, 39312 }, 39313 { 39314 name: "KeepAlive", 39315 argLen: 2, 39316 zeroWidth: true, 39317 generic: true, 39318 }, 39319 { 39320 name: "InlMark", 39321 auxType: auxInt32, 39322 argLen: 1, 39323 generic: true, 39324 }, 39325 { 39326 name: "Int64Make", 39327 argLen: 2, 39328 generic: true, 39329 }, 39330 { 39331 name: "Int64Hi", 39332 argLen: 1, 39333 generic: true, 39334 }, 39335 { 39336 name: "Int64Lo", 39337 argLen: 1, 39338 generic: true, 39339 }, 39340 { 39341 name: "Add32carry", 39342 argLen: 2, 39343 commutative: true, 39344 generic: true, 39345 }, 39346 { 39347 name: "Add32withcarry", 39348 argLen: 3, 39349 commutative: true, 39350 generic: true, 39351 }, 39352 { 39353 name: "Sub32carry", 39354 argLen: 2, 39355 generic: true, 39356 }, 39357 { 39358 name: "Sub32withcarry", 39359 argLen: 3, 39360 generic: true, 39361 }, 39362 { 39363 name: "Add64carry", 39364 argLen: 3, 39365 commutative: true, 39366 generic: true, 39367 }, 39368 { 39369 name: "Sub64borrow", 39370 argLen: 3, 39371 generic: true, 39372 }, 39373 { 39374 name: "Signmask", 39375 argLen: 1, 39376 generic: true, 39377 }, 39378 { 39379 name: "Zeromask", 39380 argLen: 1, 39381 generic: true, 39382 }, 39383 { 39384 name: "Slicemask", 39385 argLen: 1, 39386 generic: true, 39387 }, 39388 { 39389 name: "SpectreIndex", 39390 argLen: 2, 39391 generic: true, 39392 }, 39393 { 39394 name: "SpectreSliceIndex", 39395 argLen: 2, 39396 generic: true, 39397 }, 39398 { 39399 name: "Cvt32Uto32F", 39400 argLen: 1, 39401 generic: true, 39402 }, 39403 { 39404 name: "Cvt32Uto64F", 39405 argLen: 1, 39406 generic: true, 39407 }, 39408 { 39409 name: "Cvt32Fto32U", 39410 argLen: 1, 39411 generic: true, 39412 }, 39413 { 39414 name: "Cvt64Fto32U", 39415 argLen: 1, 39416 generic: true, 39417 }, 39418 { 39419 name: "Cvt64Uto32F", 39420 argLen: 1, 39421 generic: true, 39422 }, 39423 { 39424 name: "Cvt64Uto64F", 39425 argLen: 1, 39426 generic: true, 39427 }, 39428 { 39429 name: "Cvt32Fto64U", 39430 argLen: 1, 39431 generic: true, 39432 }, 39433 { 39434 name: "Cvt64Fto64U", 39435 argLen: 1, 39436 generic: true, 39437 }, 39438 { 39439 name: "Select0", 39440 argLen: 1, 39441 zeroWidth: true, 39442 generic: true, 39443 }, 39444 { 39445 name: "Select1", 39446 argLen: 1, 39447 zeroWidth: true, 39448 generic: true, 39449 }, 39450 { 39451 name: "SelectN", 39452 auxType: auxInt64, 39453 argLen: 1, 39454 generic: true, 39455 }, 39456 { 39457 name: "SelectNAddr", 39458 auxType: auxInt64, 39459 argLen: 1, 39460 generic: true, 39461 }, 39462 { 39463 name: "MakeResult", 39464 argLen: -1, 39465 generic: true, 39466 }, 39467 { 39468 name: "AtomicLoad8", 39469 argLen: 2, 39470 generic: true, 39471 }, 39472 { 39473 name: "AtomicLoad32", 39474 argLen: 2, 39475 generic: true, 39476 }, 39477 { 39478 name: "AtomicLoad64", 39479 argLen: 2, 39480 generic: true, 39481 }, 39482 { 39483 name: "AtomicLoadPtr", 39484 argLen: 2, 39485 generic: true, 39486 }, 39487 { 39488 name: "AtomicLoadAcq32", 39489 argLen: 2, 39490 generic: true, 39491 }, 39492 { 39493 name: "AtomicLoadAcq64", 39494 argLen: 2, 39495 generic: true, 39496 }, 39497 { 39498 name: "AtomicStore8", 39499 argLen: 3, 39500 hasSideEffects: true, 39501 generic: true, 39502 }, 39503 { 39504 name: "AtomicStore32", 39505 argLen: 3, 39506 hasSideEffects: true, 39507 generic: true, 39508 }, 39509 { 39510 name: "AtomicStore64", 39511 argLen: 3, 39512 hasSideEffects: true, 39513 generic: true, 39514 }, 39515 { 39516 name: "AtomicStorePtrNoWB", 39517 argLen: 3, 39518 hasSideEffects: true, 39519 generic: true, 39520 }, 39521 { 39522 name: "AtomicStoreRel32", 39523 argLen: 3, 39524 hasSideEffects: true, 39525 generic: true, 39526 }, 39527 { 39528 name: "AtomicStoreRel64", 39529 argLen: 3, 39530 hasSideEffects: true, 39531 generic: true, 39532 }, 39533 { 39534 name: "AtomicExchange32", 39535 argLen: 3, 39536 hasSideEffects: true, 39537 generic: true, 39538 }, 39539 { 39540 name: "AtomicExchange64", 39541 argLen: 3, 39542 hasSideEffects: true, 39543 generic: true, 39544 }, 39545 { 39546 name: "AtomicAdd32", 39547 argLen: 3, 39548 hasSideEffects: true, 39549 generic: true, 39550 }, 39551 { 39552 name: "AtomicAdd64", 39553 argLen: 3, 39554 hasSideEffects: true, 39555 generic: true, 39556 }, 39557 { 39558 name: "AtomicCompareAndSwap32", 39559 argLen: 4, 39560 hasSideEffects: true, 39561 generic: true, 39562 }, 39563 { 39564 name: "AtomicCompareAndSwap64", 39565 argLen: 4, 39566 hasSideEffects: true, 39567 generic: true, 39568 }, 39569 { 39570 name: "AtomicCompareAndSwapRel32", 39571 argLen: 4, 39572 hasSideEffects: true, 39573 generic: true, 39574 }, 39575 { 39576 name: "AtomicAnd8", 39577 argLen: 3, 39578 hasSideEffects: true, 39579 generic: true, 39580 }, 39581 { 39582 name: "AtomicAnd32", 39583 argLen: 3, 39584 hasSideEffects: true, 39585 generic: true, 39586 }, 39587 { 39588 name: "AtomicOr8", 39589 argLen: 3, 39590 hasSideEffects: true, 39591 generic: true, 39592 }, 39593 { 39594 name: "AtomicOr32", 39595 argLen: 3, 39596 hasSideEffects: true, 39597 generic: true, 39598 }, 39599 { 39600 name: "AtomicAdd32Variant", 39601 argLen: 3, 39602 hasSideEffects: true, 39603 generic: true, 39604 }, 39605 { 39606 name: "AtomicAdd64Variant", 39607 argLen: 3, 39608 hasSideEffects: true, 39609 generic: true, 39610 }, 39611 { 39612 name: "AtomicExchange32Variant", 39613 argLen: 3, 39614 hasSideEffects: true, 39615 generic: true, 39616 }, 39617 { 39618 name: "AtomicExchange64Variant", 39619 argLen: 3, 39620 hasSideEffects: true, 39621 generic: true, 39622 }, 39623 { 39624 name: "AtomicCompareAndSwap32Variant", 39625 argLen: 4, 39626 hasSideEffects: true, 39627 generic: true, 39628 }, 39629 { 39630 name: "AtomicCompareAndSwap64Variant", 39631 argLen: 4, 39632 hasSideEffects: true, 39633 generic: true, 39634 }, 39635 { 39636 name: "AtomicAnd8Variant", 39637 argLen: 3, 39638 hasSideEffects: true, 39639 generic: true, 39640 }, 39641 { 39642 name: "AtomicAnd32Variant", 39643 argLen: 3, 39644 hasSideEffects: true, 39645 generic: true, 39646 }, 39647 { 39648 name: "AtomicOr8Variant", 39649 argLen: 3, 39650 hasSideEffects: true, 39651 generic: true, 39652 }, 39653 { 39654 name: "AtomicOr32Variant", 39655 argLen: 3, 39656 hasSideEffects: true, 39657 generic: true, 39658 }, 39659 { 39660 name: "PubBarrier", 39661 argLen: 1, 39662 hasSideEffects: true, 39663 generic: true, 39664 }, 39665 { 39666 name: "Clobber", 39667 auxType: auxSymOff, 39668 argLen: 0, 39669 symEffect: SymNone, 39670 generic: true, 39671 }, 39672 { 39673 name: "ClobberReg", 39674 argLen: 0, 39675 generic: true, 39676 }, 39677 { 39678 name: "PrefetchCache", 39679 argLen: 2, 39680 hasSideEffects: true, 39681 generic: true, 39682 }, 39683 { 39684 name: "PrefetchCacheStreamed", 39685 argLen: 2, 39686 hasSideEffects: true, 39687 generic: true, 39688 }, 39689 } 39690 39691 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 39692 func (o Op) Scale() int16 { return int16(opcodeTable[o].scale) } 39693 func (o Op) String() string { return opcodeTable[o].name } 39694 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 39695 func (o Op) IsCall() bool { return opcodeTable[o].call } 39696 func (o Op) IsTailCall() bool { return opcodeTable[o].tailCall } 39697 func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects } 39698 func (o Op) UnsafePoint() bool { return opcodeTable[o].unsafePoint } 39699 func (o Op) ResultInArg0() bool { return opcodeTable[o].resultInArg0 } 39700 39701 var registers386 = [...]Register{ 39702 {0, x86.REG_AX, 0, "AX"}, 39703 {1, x86.REG_CX, 1, "CX"}, 39704 {2, x86.REG_DX, 2, "DX"}, 39705 {3, x86.REG_BX, 3, "BX"}, 39706 {4, x86.REGSP, -1, "SP"}, 39707 {5, x86.REG_BP, 4, "BP"}, 39708 {6, x86.REG_SI, 5, "SI"}, 39709 {7, x86.REG_DI, 6, "DI"}, 39710 {8, x86.REG_X0, -1, "X0"}, 39711 {9, x86.REG_X1, -1, "X1"}, 39712 {10, x86.REG_X2, -1, "X2"}, 39713 {11, x86.REG_X3, -1, "X3"}, 39714 {12, x86.REG_X4, -1, "X4"}, 39715 {13, x86.REG_X5, -1, "X5"}, 39716 {14, x86.REG_X6, -1, "X6"}, 39717 {15, x86.REG_X7, -1, "X7"}, 39718 {16, 0, -1, "SB"}, 39719 } 39720 var paramIntReg386 = []int8(nil) 39721 var paramFloatReg386 = []int8(nil) 39722 var gpRegMask386 = regMask(239) 39723 var fpRegMask386 = regMask(65280) 39724 var specialRegMask386 = regMask(0) 39725 var framepointerReg386 = int8(5) 39726 var linkReg386 = int8(-1) 39727 var registersAMD64 = [...]Register{ 39728 {0, x86.REG_AX, 0, "AX"}, 39729 {1, x86.REG_CX, 1, "CX"}, 39730 {2, x86.REG_DX, 2, "DX"}, 39731 {3, x86.REG_BX, 3, "BX"}, 39732 {4, x86.REGSP, -1, "SP"}, 39733 {5, x86.REG_BP, 4, "BP"}, 39734 {6, x86.REG_SI, 5, "SI"}, 39735 {7, x86.REG_DI, 6, "DI"}, 39736 {8, x86.REG_R8, 7, "R8"}, 39737 {9, x86.REG_R9, 8, "R9"}, 39738 {10, x86.REG_R10, 9, "R10"}, 39739 {11, x86.REG_R11, 10, "R11"}, 39740 {12, x86.REG_R12, 11, "R12"}, 39741 {13, x86.REG_R13, 12, "R13"}, 39742 {14, x86.REGG, -1, "g"}, 39743 {15, x86.REG_R15, 13, "R15"}, 39744 {16, x86.REG_X0, -1, "X0"}, 39745 {17, x86.REG_X1, -1, "X1"}, 39746 {18, x86.REG_X2, -1, "X2"}, 39747 {19, x86.REG_X3, -1, "X3"}, 39748 {20, x86.REG_X4, -1, "X4"}, 39749 {21, x86.REG_X5, -1, "X5"}, 39750 {22, x86.REG_X6, -1, "X6"}, 39751 {23, x86.REG_X7, -1, "X7"}, 39752 {24, x86.REG_X8, -1, "X8"}, 39753 {25, x86.REG_X9, -1, "X9"}, 39754 {26, x86.REG_X10, -1, "X10"}, 39755 {27, x86.REG_X11, -1, "X11"}, 39756 {28, x86.REG_X12, -1, "X12"}, 39757 {29, x86.REG_X13, -1, "X13"}, 39758 {30, x86.REG_X14, -1, "X14"}, 39759 {31, x86.REG_X15, -1, "X15"}, 39760 {32, 0, -1, "SB"}, 39761 } 39762 var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} 39763 var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} 39764 var gpRegMaskAMD64 = regMask(49135) 39765 var fpRegMaskAMD64 = regMask(2147418112) 39766 var specialRegMaskAMD64 = regMask(2147483648) 39767 var framepointerRegAMD64 = int8(5) 39768 var linkRegAMD64 = int8(-1) 39769 var registersARM = [...]Register{ 39770 {0, arm.REG_R0, 0, "R0"}, 39771 {1, arm.REG_R1, 1, "R1"}, 39772 {2, arm.REG_R2, 2, "R2"}, 39773 {3, arm.REG_R3, 3, "R3"}, 39774 {4, arm.REG_R4, 4, "R4"}, 39775 {5, arm.REG_R5, 5, "R5"}, 39776 {6, arm.REG_R6, 6, "R6"}, 39777 {7, arm.REG_R7, 7, "R7"}, 39778 {8, arm.REG_R8, 8, "R8"}, 39779 {9, arm.REG_R9, 9, "R9"}, 39780 {10, arm.REGG, -1, "g"}, 39781 {11, arm.REG_R11, -1, "R11"}, 39782 {12, arm.REG_R12, 10, "R12"}, 39783 {13, arm.REGSP, -1, "SP"}, 39784 {14, arm.REG_R14, 11, "R14"}, 39785 {15, arm.REG_R15, -1, "R15"}, 39786 {16, arm.REG_F0, -1, "F0"}, 39787 {17, arm.REG_F1, -1, "F1"}, 39788 {18, arm.REG_F2, -1, "F2"}, 39789 {19, arm.REG_F3, -1, "F3"}, 39790 {20, arm.REG_F4, -1, "F4"}, 39791 {21, arm.REG_F5, -1, "F5"}, 39792 {22, arm.REG_F6, -1, "F6"}, 39793 {23, arm.REG_F7, -1, "F7"}, 39794 {24, arm.REG_F8, -1, "F8"}, 39795 {25, arm.REG_F9, -1, "F9"}, 39796 {26, arm.REG_F10, -1, "F10"}, 39797 {27, arm.REG_F11, -1, "F11"}, 39798 {28, arm.REG_F12, -1, "F12"}, 39799 {29, arm.REG_F13, -1, "F13"}, 39800 {30, arm.REG_F14, -1, "F14"}, 39801 {31, arm.REG_F15, -1, "F15"}, 39802 {32, 0, -1, "SB"}, 39803 } 39804 var paramIntRegARM = []int8(nil) 39805 var paramFloatRegARM = []int8(nil) 39806 var gpRegMaskARM = regMask(21503) 39807 var fpRegMaskARM = regMask(4294901760) 39808 var specialRegMaskARM = regMask(0) 39809 var framepointerRegARM = int8(-1) 39810 var linkRegARM = int8(14) 39811 var registersARM64 = [...]Register{ 39812 {0, arm64.REG_R0, 0, "R0"}, 39813 {1, arm64.REG_R1, 1, "R1"}, 39814 {2, arm64.REG_R2, 2, "R2"}, 39815 {3, arm64.REG_R3, 3, "R3"}, 39816 {4, arm64.REG_R4, 4, "R4"}, 39817 {5, arm64.REG_R5, 5, "R5"}, 39818 {6, arm64.REG_R6, 6, "R6"}, 39819 {7, arm64.REG_R7, 7, "R7"}, 39820 {8, arm64.REG_R8, 8, "R8"}, 39821 {9, arm64.REG_R9, 9, "R9"}, 39822 {10, arm64.REG_R10, 10, "R10"}, 39823 {11, arm64.REG_R11, 11, "R11"}, 39824 {12, arm64.REG_R12, 12, "R12"}, 39825 {13, arm64.REG_R13, 13, "R13"}, 39826 {14, arm64.REG_R14, 14, "R14"}, 39827 {15, arm64.REG_R15, 15, "R15"}, 39828 {16, arm64.REG_R16, 16, "R16"}, 39829 {17, arm64.REG_R17, 17, "R17"}, 39830 {18, arm64.REG_R18, -1, "R18"}, 39831 {19, arm64.REG_R19, 18, "R19"}, 39832 {20, arm64.REG_R20, 19, "R20"}, 39833 {21, arm64.REG_R21, 20, "R21"}, 39834 {22, arm64.REG_R22, 21, "R22"}, 39835 {23, arm64.REG_R23, 22, "R23"}, 39836 {24, arm64.REG_R24, 23, "R24"}, 39837 {25, arm64.REG_R25, 24, "R25"}, 39838 {26, arm64.REG_R26, 25, "R26"}, 39839 {27, arm64.REGG, -1, "g"}, 39840 {28, arm64.REG_R29, -1, "R29"}, 39841 {29, arm64.REG_R30, 26, "R30"}, 39842 {30, arm64.REGSP, -1, "SP"}, 39843 {31, arm64.REG_F0, -1, "F0"}, 39844 {32, arm64.REG_F1, -1, "F1"}, 39845 {33, arm64.REG_F2, -1, "F2"}, 39846 {34, arm64.REG_F3, -1, "F3"}, 39847 {35, arm64.REG_F4, -1, "F4"}, 39848 {36, arm64.REG_F5, -1, "F5"}, 39849 {37, arm64.REG_F6, -1, "F6"}, 39850 {38, arm64.REG_F7, -1, "F7"}, 39851 {39, arm64.REG_F8, -1, "F8"}, 39852 {40, arm64.REG_F9, -1, "F9"}, 39853 {41, arm64.REG_F10, -1, "F10"}, 39854 {42, arm64.REG_F11, -1, "F11"}, 39855 {43, arm64.REG_F12, -1, "F12"}, 39856 {44, arm64.REG_F13, -1, "F13"}, 39857 {45, arm64.REG_F14, -1, "F14"}, 39858 {46, arm64.REG_F15, -1, "F15"}, 39859 {47, arm64.REG_F16, -1, "F16"}, 39860 {48, arm64.REG_F17, -1, "F17"}, 39861 {49, arm64.REG_F18, -1, "F18"}, 39862 {50, arm64.REG_F19, -1, "F19"}, 39863 {51, arm64.REG_F20, -1, "F20"}, 39864 {52, arm64.REG_F21, -1, "F21"}, 39865 {53, arm64.REG_F22, -1, "F22"}, 39866 {54, arm64.REG_F23, -1, "F23"}, 39867 {55, arm64.REG_F24, -1, "F24"}, 39868 {56, arm64.REG_F25, -1, "F25"}, 39869 {57, arm64.REG_F26, -1, "F26"}, 39870 {58, arm64.REG_F27, -1, "F27"}, 39871 {59, arm64.REG_F28, -1, "F28"}, 39872 {60, arm64.REG_F29, -1, "F29"}, 39873 {61, arm64.REG_F30, -1, "F30"}, 39874 {62, arm64.REG_F31, -1, "F31"}, 39875 {63, 0, -1, "SB"}, 39876 } 39877 var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} 39878 var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46} 39879 var gpRegMaskARM64 = regMask(670826495) 39880 var fpRegMaskARM64 = regMask(9223372034707292160) 39881 var specialRegMaskARM64 = regMask(0) 39882 var framepointerRegARM64 = int8(-1) 39883 var linkRegARM64 = int8(29) 39884 var registersLOONG64 = [...]Register{ 39885 {0, loong64.REG_R0, -1, "R0"}, 39886 {1, loong64.REG_R1, -1, "R1"}, 39887 {2, loong64.REGSP, -1, "SP"}, 39888 {3, loong64.REG_R4, 0, "R4"}, 39889 {4, loong64.REG_R5, 1, "R5"}, 39890 {5, loong64.REG_R6, 2, "R6"}, 39891 {6, loong64.REG_R7, 3, "R7"}, 39892 {7, loong64.REG_R8, 4, "R8"}, 39893 {8, loong64.REG_R9, 5, "R9"}, 39894 {9, loong64.REG_R10, 6, "R10"}, 39895 {10, loong64.REG_R11, 7, "R11"}, 39896 {11, loong64.REG_R12, 8, "R12"}, 39897 {12, loong64.REG_R13, 9, "R13"}, 39898 {13, loong64.REG_R14, 10, "R14"}, 39899 {14, loong64.REG_R15, 11, "R15"}, 39900 {15, loong64.REG_R16, 12, "R16"}, 39901 {16, loong64.REG_R17, 13, "R17"}, 39902 {17, loong64.REG_R18, 14, "R18"}, 39903 {18, loong64.REG_R19, 15, "R19"}, 39904 {19, loong64.REG_R20, 16, "R20"}, 39905 {20, loong64.REG_R21, -1, "R21"}, 39906 {21, loong64.REGG, -1, "g"}, 39907 {22, loong64.REG_R23, 17, "R23"}, 39908 {23, loong64.REG_R24, 18, "R24"}, 39909 {24, loong64.REG_R25, 19, "R25"}, 39910 {25, loong64.REG_R26, 20, "R26"}, 39911 {26, loong64.REG_R27, 21, "R27"}, 39912 {27, loong64.REG_R28, 22, "R28"}, 39913 {28, loong64.REG_R29, 23, "R29"}, 39914 {29, loong64.REG_R31, 24, "R31"}, 39915 {30, loong64.REG_F0, -1, "F0"}, 39916 {31, loong64.REG_F1, -1, "F1"}, 39917 {32, loong64.REG_F2, -1, "F2"}, 39918 {33, loong64.REG_F3, -1, "F3"}, 39919 {34, loong64.REG_F4, -1, "F4"}, 39920 {35, loong64.REG_F5, -1, "F5"}, 39921 {36, loong64.REG_F6, -1, "F6"}, 39922 {37, loong64.REG_F7, -1, "F7"}, 39923 {38, loong64.REG_F8, -1, "F8"}, 39924 {39, loong64.REG_F9, -1, "F9"}, 39925 {40, loong64.REG_F10, -1, "F10"}, 39926 {41, loong64.REG_F11, -1, "F11"}, 39927 {42, loong64.REG_F12, -1, "F12"}, 39928 {43, loong64.REG_F13, -1, "F13"}, 39929 {44, loong64.REG_F14, -1, "F14"}, 39930 {45, loong64.REG_F15, -1, "F15"}, 39931 {46, loong64.REG_F16, -1, "F16"}, 39932 {47, loong64.REG_F17, -1, "F17"}, 39933 {48, loong64.REG_F18, -1, "F18"}, 39934 {49, loong64.REG_F19, -1, "F19"}, 39935 {50, loong64.REG_F20, -1, "F20"}, 39936 {51, loong64.REG_F21, -1, "F21"}, 39937 {52, loong64.REG_F22, -1, "F22"}, 39938 {53, loong64.REG_F23, -1, "F23"}, 39939 {54, loong64.REG_F24, -1, "F24"}, 39940 {55, loong64.REG_F25, -1, "F25"}, 39941 {56, loong64.REG_F26, -1, "F26"}, 39942 {57, loong64.REG_F27, -1, "F27"}, 39943 {58, loong64.REG_F28, -1, "F28"}, 39944 {59, loong64.REG_F29, -1, "F29"}, 39945 {60, loong64.REG_F30, -1, "F30"}, 39946 {61, loong64.REG_F31, -1, "F31"}, 39947 {62, 0, -1, "SB"}, 39948 } 39949 var paramIntRegLOONG64 = []int8{3, 4, 5, 6, 7, 8, 9, 10} 39950 var paramFloatRegLOONG64 = []int8{30, 31, 32, 33, 34, 35, 36, 37} 39951 var gpRegMaskLOONG64 = regMask(1070596088) 39952 var fpRegMaskLOONG64 = regMask(4611686017353646080) 39953 var specialRegMaskLOONG64 = regMask(0) 39954 var framepointerRegLOONG64 = int8(-1) 39955 var linkRegLOONG64 = int8(1) 39956 var registersMIPS = [...]Register{ 39957 {0, mips.REG_R0, -1, "R0"}, 39958 {1, mips.REG_R1, 0, "R1"}, 39959 {2, mips.REG_R2, 1, "R2"}, 39960 {3, mips.REG_R3, 2, "R3"}, 39961 {4, mips.REG_R4, 3, "R4"}, 39962 {5, mips.REG_R5, 4, "R5"}, 39963 {6, mips.REG_R6, 5, "R6"}, 39964 {7, mips.REG_R7, 6, "R7"}, 39965 {8, mips.REG_R8, 7, "R8"}, 39966 {9, mips.REG_R9, 8, "R9"}, 39967 {10, mips.REG_R10, 9, "R10"}, 39968 {11, mips.REG_R11, 10, "R11"}, 39969 {12, mips.REG_R12, 11, "R12"}, 39970 {13, mips.REG_R13, 12, "R13"}, 39971 {14, mips.REG_R14, 13, "R14"}, 39972 {15, mips.REG_R15, 14, "R15"}, 39973 {16, mips.REG_R16, 15, "R16"}, 39974 {17, mips.REG_R17, 16, "R17"}, 39975 {18, mips.REG_R18, 17, "R18"}, 39976 {19, mips.REG_R19, 18, "R19"}, 39977 {20, mips.REG_R20, 19, "R20"}, 39978 {21, mips.REG_R21, 20, "R21"}, 39979 {22, mips.REG_R22, 21, "R22"}, 39980 {23, mips.REG_R24, 22, "R24"}, 39981 {24, mips.REG_R25, 23, "R25"}, 39982 {25, mips.REG_R28, 24, "R28"}, 39983 {26, mips.REGSP, -1, "SP"}, 39984 {27, mips.REGG, -1, "g"}, 39985 {28, mips.REG_R31, 25, "R31"}, 39986 {29, mips.REG_F0, -1, "F0"}, 39987 {30, mips.REG_F2, -1, "F2"}, 39988 {31, mips.REG_F4, -1, "F4"}, 39989 {32, mips.REG_F6, -1, "F6"}, 39990 {33, mips.REG_F8, -1, "F8"}, 39991 {34, mips.REG_F10, -1, "F10"}, 39992 {35, mips.REG_F12, -1, "F12"}, 39993 {36, mips.REG_F14, -1, "F14"}, 39994 {37, mips.REG_F16, -1, "F16"}, 39995 {38, mips.REG_F18, -1, "F18"}, 39996 {39, mips.REG_F20, -1, "F20"}, 39997 {40, mips.REG_F22, -1, "F22"}, 39998 {41, mips.REG_F24, -1, "F24"}, 39999 {42, mips.REG_F26, -1, "F26"}, 40000 {43, mips.REG_F28, -1, "F28"}, 40001 {44, mips.REG_F30, -1, "F30"}, 40002 {45, mips.REG_HI, -1, "HI"}, 40003 {46, mips.REG_LO, -1, "LO"}, 40004 {47, 0, -1, "SB"}, 40005 } 40006 var paramIntRegMIPS = []int8(nil) 40007 var paramFloatRegMIPS = []int8(nil) 40008 var gpRegMaskMIPS = regMask(335544318) 40009 var fpRegMaskMIPS = regMask(35183835217920) 40010 var specialRegMaskMIPS = regMask(105553116266496) 40011 var framepointerRegMIPS = int8(-1) 40012 var linkRegMIPS = int8(28) 40013 var registersMIPS64 = [...]Register{ 40014 {0, mips.REG_R0, -1, "R0"}, 40015 {1, mips.REG_R1, 0, "R1"}, 40016 {2, mips.REG_R2, 1, "R2"}, 40017 {3, mips.REG_R3, 2, "R3"}, 40018 {4, mips.REG_R4, 3, "R4"}, 40019 {5, mips.REG_R5, 4, "R5"}, 40020 {6, mips.REG_R6, 5, "R6"}, 40021 {7, mips.REG_R7, 6, "R7"}, 40022 {8, mips.REG_R8, 7, "R8"}, 40023 {9, mips.REG_R9, 8, "R9"}, 40024 {10, mips.REG_R10, 9, "R10"}, 40025 {11, mips.REG_R11, 10, "R11"}, 40026 {12, mips.REG_R12, 11, "R12"}, 40027 {13, mips.REG_R13, 12, "R13"}, 40028 {14, mips.REG_R14, 13, "R14"}, 40029 {15, mips.REG_R15, 14, "R15"}, 40030 {16, mips.REG_R16, 15, "R16"}, 40031 {17, mips.REG_R17, 16, "R17"}, 40032 {18, mips.REG_R18, 17, "R18"}, 40033 {19, mips.REG_R19, 18, "R19"}, 40034 {20, mips.REG_R20, 19, "R20"}, 40035 {21, mips.REG_R21, 20, "R21"}, 40036 {22, mips.REG_R22, 21, "R22"}, 40037 {23, mips.REG_R24, 22, "R24"}, 40038 {24, mips.REG_R25, 23, "R25"}, 40039 {25, mips.REGSP, -1, "SP"}, 40040 {26, mips.REGG, -1, "g"}, 40041 {27, mips.REG_R31, 24, "R31"}, 40042 {28, mips.REG_F0, -1, "F0"}, 40043 {29, mips.REG_F1, -1, "F1"}, 40044 {30, mips.REG_F2, -1, "F2"}, 40045 {31, mips.REG_F3, -1, "F3"}, 40046 {32, mips.REG_F4, -1, "F4"}, 40047 {33, mips.REG_F5, -1, "F5"}, 40048 {34, mips.REG_F6, -1, "F6"}, 40049 {35, mips.REG_F7, -1, "F7"}, 40050 {36, mips.REG_F8, -1, "F8"}, 40051 {37, mips.REG_F9, -1, "F9"}, 40052 {38, mips.REG_F10, -1, "F10"}, 40053 {39, mips.REG_F11, -1, "F11"}, 40054 {40, mips.REG_F12, -1, "F12"}, 40055 {41, mips.REG_F13, -1, "F13"}, 40056 {42, mips.REG_F14, -1, "F14"}, 40057 {43, mips.REG_F15, -1, "F15"}, 40058 {44, mips.REG_F16, -1, "F16"}, 40059 {45, mips.REG_F17, -1, "F17"}, 40060 {46, mips.REG_F18, -1, "F18"}, 40061 {47, mips.REG_F19, -1, "F19"}, 40062 {48, mips.REG_F20, -1, "F20"}, 40063 {49, mips.REG_F21, -1, "F21"}, 40064 {50, mips.REG_F22, -1, "F22"}, 40065 {51, mips.REG_F23, -1, "F23"}, 40066 {52, mips.REG_F24, -1, "F24"}, 40067 {53, mips.REG_F25, -1, "F25"}, 40068 {54, mips.REG_F26, -1, "F26"}, 40069 {55, mips.REG_F27, -1, "F27"}, 40070 {56, mips.REG_F28, -1, "F28"}, 40071 {57, mips.REG_F29, -1, "F29"}, 40072 {58, mips.REG_F30, -1, "F30"}, 40073 {59, mips.REG_F31, -1, "F31"}, 40074 {60, mips.REG_HI, -1, "HI"}, 40075 {61, mips.REG_LO, -1, "LO"}, 40076 {62, 0, -1, "SB"}, 40077 } 40078 var paramIntRegMIPS64 = []int8(nil) 40079 var paramFloatRegMIPS64 = []int8(nil) 40080 var gpRegMaskMIPS64 = regMask(167772158) 40081 var fpRegMaskMIPS64 = regMask(1152921504338411520) 40082 var specialRegMaskMIPS64 = regMask(3458764513820540928) 40083 var framepointerRegMIPS64 = int8(-1) 40084 var linkRegMIPS64 = int8(27) 40085 var registersPPC64 = [...]Register{ 40086 {0, ppc64.REG_R0, -1, "R0"}, 40087 {1, ppc64.REGSP, -1, "SP"}, 40088 {2, 0, -1, "SB"}, 40089 {3, ppc64.REG_R3, 0, "R3"}, 40090 {4, ppc64.REG_R4, 1, "R4"}, 40091 {5, ppc64.REG_R5, 2, "R5"}, 40092 {6, ppc64.REG_R6, 3, "R6"}, 40093 {7, ppc64.REG_R7, 4, "R7"}, 40094 {8, ppc64.REG_R8, 5, "R8"}, 40095 {9, ppc64.REG_R9, 6, "R9"}, 40096 {10, ppc64.REG_R10, 7, "R10"}, 40097 {11, ppc64.REG_R11, 8, "R11"}, 40098 {12, ppc64.REG_R12, 9, "R12"}, 40099 {13, ppc64.REG_R13, -1, "R13"}, 40100 {14, ppc64.REG_R14, 10, "R14"}, 40101 {15, ppc64.REG_R15, 11, "R15"}, 40102 {16, ppc64.REG_R16, 12, "R16"}, 40103 {17, ppc64.REG_R17, 13, "R17"}, 40104 {18, ppc64.REG_R18, 14, "R18"}, 40105 {19, ppc64.REG_R19, 15, "R19"}, 40106 {20, ppc64.REG_R20, 16, "R20"}, 40107 {21, ppc64.REG_R21, 17, "R21"}, 40108 {22, ppc64.REG_R22, 18, "R22"}, 40109 {23, ppc64.REG_R23, 19, "R23"}, 40110 {24, ppc64.REG_R24, 20, "R24"}, 40111 {25, ppc64.REG_R25, 21, "R25"}, 40112 {26, ppc64.REG_R26, 22, "R26"}, 40113 {27, ppc64.REG_R27, 23, "R27"}, 40114 {28, ppc64.REG_R28, 24, "R28"}, 40115 {29, ppc64.REG_R29, 25, "R29"}, 40116 {30, ppc64.REGG, -1, "g"}, 40117 {31, ppc64.REG_R31, -1, "R31"}, 40118 {32, ppc64.REG_F0, -1, "F0"}, 40119 {33, ppc64.REG_F1, -1, "F1"}, 40120 {34, ppc64.REG_F2, -1, "F2"}, 40121 {35, ppc64.REG_F3, -1, "F3"}, 40122 {36, ppc64.REG_F4, -1, "F4"}, 40123 {37, ppc64.REG_F5, -1, "F5"}, 40124 {38, ppc64.REG_F6, -1, "F6"}, 40125 {39, ppc64.REG_F7, -1, "F7"}, 40126 {40, ppc64.REG_F8, -1, "F8"}, 40127 {41, ppc64.REG_F9, -1, "F9"}, 40128 {42, ppc64.REG_F10, -1, "F10"}, 40129 {43, ppc64.REG_F11, -1, "F11"}, 40130 {44, ppc64.REG_F12, -1, "F12"}, 40131 {45, ppc64.REG_F13, -1, "F13"}, 40132 {46, ppc64.REG_F14, -1, "F14"}, 40133 {47, ppc64.REG_F15, -1, "F15"}, 40134 {48, ppc64.REG_F16, -1, "F16"}, 40135 {49, ppc64.REG_F17, -1, "F17"}, 40136 {50, ppc64.REG_F18, -1, "F18"}, 40137 {51, ppc64.REG_F19, -1, "F19"}, 40138 {52, ppc64.REG_F20, -1, "F20"}, 40139 {53, ppc64.REG_F21, -1, "F21"}, 40140 {54, ppc64.REG_F22, -1, "F22"}, 40141 {55, ppc64.REG_F23, -1, "F23"}, 40142 {56, ppc64.REG_F24, -1, "F24"}, 40143 {57, ppc64.REG_F25, -1, "F25"}, 40144 {58, ppc64.REG_F26, -1, "F26"}, 40145 {59, ppc64.REG_F27, -1, "F27"}, 40146 {60, ppc64.REG_F28, -1, "F28"}, 40147 {61, ppc64.REG_F29, -1, "F29"}, 40148 {62, ppc64.REG_F30, -1, "F30"}, 40149 {63, ppc64.REG_XER, -1, "XER"}, 40150 } 40151 var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17} 40152 var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44} 40153 var gpRegMaskPPC64 = regMask(1073733624) 40154 var fpRegMaskPPC64 = regMask(9223372032559808512) 40155 var specialRegMaskPPC64 = regMask(9223372036854775808) 40156 var framepointerRegPPC64 = int8(-1) 40157 var linkRegPPC64 = int8(-1) 40158 var registersRISCV64 = [...]Register{ 40159 {0, riscv.REG_X0, -1, "X0"}, 40160 {1, riscv.REGSP, -1, "SP"}, 40161 {2, riscv.REG_X3, -1, "X3"}, 40162 {3, riscv.REG_X4, -1, "X4"}, 40163 {4, riscv.REG_X5, 0, "X5"}, 40164 {5, riscv.REG_X6, 1, "X6"}, 40165 {6, riscv.REG_X7, 2, "X7"}, 40166 {7, riscv.REG_X8, 3, "X8"}, 40167 {8, riscv.REG_X9, 4, "X9"}, 40168 {9, riscv.REG_X10, 5, "X10"}, 40169 {10, riscv.REG_X11, 6, "X11"}, 40170 {11, riscv.REG_X12, 7, "X12"}, 40171 {12, riscv.REG_X13, 8, "X13"}, 40172 {13, riscv.REG_X14, 9, "X14"}, 40173 {14, riscv.REG_X15, 10, "X15"}, 40174 {15, riscv.REG_X16, 11, "X16"}, 40175 {16, riscv.REG_X17, 12, "X17"}, 40176 {17, riscv.REG_X18, 13, "X18"}, 40177 {18, riscv.REG_X19, 14, "X19"}, 40178 {19, riscv.REG_X20, 15, "X20"}, 40179 {20, riscv.REG_X21, 16, "X21"}, 40180 {21, riscv.REG_X22, 17, "X22"}, 40181 {22, riscv.REG_X23, 18, "X23"}, 40182 {23, riscv.REG_X24, 19, "X24"}, 40183 {24, riscv.REG_X25, 20, "X25"}, 40184 {25, riscv.REG_X26, 21, "X26"}, 40185 {26, riscv.REGG, -1, "g"}, 40186 {27, riscv.REG_X28, 22, "X28"}, 40187 {28, riscv.REG_X29, 23, "X29"}, 40188 {29, riscv.REG_X30, 24, "X30"}, 40189 {30, riscv.REG_X31, -1, "X31"}, 40190 {31, riscv.REG_F0, -1, "F0"}, 40191 {32, riscv.REG_F1, -1, "F1"}, 40192 {33, riscv.REG_F2, -1, "F2"}, 40193 {34, riscv.REG_F3, -1, "F3"}, 40194 {35, riscv.REG_F4, -1, "F4"}, 40195 {36, riscv.REG_F5, -1, "F5"}, 40196 {37, riscv.REG_F6, -1, "F6"}, 40197 {38, riscv.REG_F7, -1, "F7"}, 40198 {39, riscv.REG_F8, -1, "F8"}, 40199 {40, riscv.REG_F9, -1, "F9"}, 40200 {41, riscv.REG_F10, -1, "F10"}, 40201 {42, riscv.REG_F11, -1, "F11"}, 40202 {43, riscv.REG_F12, -1, "F12"}, 40203 {44, riscv.REG_F13, -1, "F13"}, 40204 {45, riscv.REG_F14, -1, "F14"}, 40205 {46, riscv.REG_F15, -1, "F15"}, 40206 {47, riscv.REG_F16, -1, "F16"}, 40207 {48, riscv.REG_F17, -1, "F17"}, 40208 {49, riscv.REG_F18, -1, "F18"}, 40209 {50, riscv.REG_F19, -1, "F19"}, 40210 {51, riscv.REG_F20, -1, "F20"}, 40211 {52, riscv.REG_F21, -1, "F21"}, 40212 {53, riscv.REG_F22, -1, "F22"}, 40213 {54, riscv.REG_F23, -1, "F23"}, 40214 {55, riscv.REG_F24, -1, "F24"}, 40215 {56, riscv.REG_F25, -1, "F25"}, 40216 {57, riscv.REG_F26, -1, "F26"}, 40217 {58, riscv.REG_F27, -1, "F27"}, 40218 {59, riscv.REG_F28, -1, "F28"}, 40219 {60, riscv.REG_F29, -1, "F29"}, 40220 {61, riscv.REG_F30, -1, "F30"}, 40221 {62, riscv.REG_F31, -1, "F31"}, 40222 {63, 0, -1, "SB"}, 40223 } 40224 var paramIntRegRISCV64 = []int8{9, 10, 11, 12, 13, 14, 15, 16, 7, 8, 17, 18, 19, 20, 21, 22} 40225 var paramFloatRegRISCV64 = []int8{41, 42, 43, 44, 45, 46, 47, 48, 39, 40, 49, 50, 51, 52, 53, 54} 40226 var gpRegMaskRISCV64 = regMask(1006632944) 40227 var fpRegMaskRISCV64 = regMask(9223372034707292160) 40228 var specialRegMaskRISCV64 = regMask(0) 40229 var framepointerRegRISCV64 = int8(-1) 40230 var linkRegRISCV64 = int8(0) 40231 var registersS390X = [...]Register{ 40232 {0, s390x.REG_R0, 0, "R0"}, 40233 {1, s390x.REG_R1, 1, "R1"}, 40234 {2, s390x.REG_R2, 2, "R2"}, 40235 {3, s390x.REG_R3, 3, "R3"}, 40236 {4, s390x.REG_R4, 4, "R4"}, 40237 {5, s390x.REG_R5, 5, "R5"}, 40238 {6, s390x.REG_R6, 6, "R6"}, 40239 {7, s390x.REG_R7, 7, "R7"}, 40240 {8, s390x.REG_R8, 8, "R8"}, 40241 {9, s390x.REG_R9, 9, "R9"}, 40242 {10, s390x.REG_R10, -1, "R10"}, 40243 {11, s390x.REG_R11, 10, "R11"}, 40244 {12, s390x.REG_R12, 11, "R12"}, 40245 {13, s390x.REGG, -1, "g"}, 40246 {14, s390x.REG_R14, 12, "R14"}, 40247 {15, s390x.REGSP, -1, "SP"}, 40248 {16, s390x.REG_F0, -1, "F0"}, 40249 {17, s390x.REG_F1, -1, "F1"}, 40250 {18, s390x.REG_F2, -1, "F2"}, 40251 {19, s390x.REG_F3, -1, "F3"}, 40252 {20, s390x.REG_F4, -1, "F4"}, 40253 {21, s390x.REG_F5, -1, "F5"}, 40254 {22, s390x.REG_F6, -1, "F6"}, 40255 {23, s390x.REG_F7, -1, "F7"}, 40256 {24, s390x.REG_F8, -1, "F8"}, 40257 {25, s390x.REG_F9, -1, "F9"}, 40258 {26, s390x.REG_F10, -1, "F10"}, 40259 {27, s390x.REG_F11, -1, "F11"}, 40260 {28, s390x.REG_F12, -1, "F12"}, 40261 {29, s390x.REG_F13, -1, "F13"}, 40262 {30, s390x.REG_F14, -1, "F14"}, 40263 {31, s390x.REG_F15, -1, "F15"}, 40264 {32, 0, -1, "SB"}, 40265 } 40266 var paramIntRegS390X = []int8(nil) 40267 var paramFloatRegS390X = []int8(nil) 40268 var gpRegMaskS390X = regMask(23551) 40269 var fpRegMaskS390X = regMask(4294901760) 40270 var specialRegMaskS390X = regMask(0) 40271 var framepointerRegS390X = int8(-1) 40272 var linkRegS390X = int8(14) 40273 var registersWasm = [...]Register{ 40274 {0, wasm.REG_R0, 0, "R0"}, 40275 {1, wasm.REG_R1, 1, "R1"}, 40276 {2, wasm.REG_R2, 2, "R2"}, 40277 {3, wasm.REG_R3, 3, "R3"}, 40278 {4, wasm.REG_R4, 4, "R4"}, 40279 {5, wasm.REG_R5, 5, "R5"}, 40280 {6, wasm.REG_R6, 6, "R6"}, 40281 {7, wasm.REG_R7, 7, "R7"}, 40282 {8, wasm.REG_R8, 8, "R8"}, 40283 {9, wasm.REG_R9, 9, "R9"}, 40284 {10, wasm.REG_R10, 10, "R10"}, 40285 {11, wasm.REG_R11, 11, "R11"}, 40286 {12, wasm.REG_R12, 12, "R12"}, 40287 {13, wasm.REG_R13, 13, "R13"}, 40288 {14, wasm.REG_R14, 14, "R14"}, 40289 {15, wasm.REG_R15, 15, "R15"}, 40290 {16, wasm.REG_F0, -1, "F0"}, 40291 {17, wasm.REG_F1, -1, "F1"}, 40292 {18, wasm.REG_F2, -1, "F2"}, 40293 {19, wasm.REG_F3, -1, "F3"}, 40294 {20, wasm.REG_F4, -1, "F4"}, 40295 {21, wasm.REG_F5, -1, "F5"}, 40296 {22, wasm.REG_F6, -1, "F6"}, 40297 {23, wasm.REG_F7, -1, "F7"}, 40298 {24, wasm.REG_F8, -1, "F8"}, 40299 {25, wasm.REG_F9, -1, "F9"}, 40300 {26, wasm.REG_F10, -1, "F10"}, 40301 {27, wasm.REG_F11, -1, "F11"}, 40302 {28, wasm.REG_F12, -1, "F12"}, 40303 {29, wasm.REG_F13, -1, "F13"}, 40304 {30, wasm.REG_F14, -1, "F14"}, 40305 {31, wasm.REG_F15, -1, "F15"}, 40306 {32, wasm.REG_F16, -1, "F16"}, 40307 {33, wasm.REG_F17, -1, "F17"}, 40308 {34, wasm.REG_F18, -1, "F18"}, 40309 {35, wasm.REG_F19, -1, "F19"}, 40310 {36, wasm.REG_F20, -1, "F20"}, 40311 {37, wasm.REG_F21, -1, "F21"}, 40312 {38, wasm.REG_F22, -1, "F22"}, 40313 {39, wasm.REG_F23, -1, "F23"}, 40314 {40, wasm.REG_F24, -1, "F24"}, 40315 {41, wasm.REG_F25, -1, "F25"}, 40316 {42, wasm.REG_F26, -1, "F26"}, 40317 {43, wasm.REG_F27, -1, "F27"}, 40318 {44, wasm.REG_F28, -1, "F28"}, 40319 {45, wasm.REG_F29, -1, "F29"}, 40320 {46, wasm.REG_F30, -1, "F30"}, 40321 {47, wasm.REG_F31, -1, "F31"}, 40322 {48, wasm.REGSP, -1, "SP"}, 40323 {49, wasm.REGG, -1, "g"}, 40324 {50, 0, -1, "SB"}, 40325 } 40326 var paramIntRegWasm = []int8(nil) 40327 var paramFloatRegWasm = []int8(nil) 40328 var gpRegMaskWasm = regMask(65535) 40329 var fpRegMaskWasm = regMask(281474976645120) 40330 var fp32RegMaskWasm = regMask(4294901760) 40331 var fp64RegMaskWasm = regMask(281470681743360) 40332 var specialRegMaskWasm = regMask(0) 40333 var framepointerRegWasm = int8(-1) 40334 var linkRegWasm = int8(-1)