github.com/bir3/gocompiler@v0.3.205/src/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "github.com/bir3/gocompiler/src/cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 147 ) 148 149 // bits 0-4 indicates register: Vn 150 // bits 5-8 indicates arrangement: <T> 151 const ( 152 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> 153 REG_ELEM // Vn.<T>[index] 154 REG_ELEM_END 155 ) 156 157 // Not registers, but flags that can be combined with regular register 158 // constants to indicate extended register conversion. When checking, 159 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 160 // indicates extended register, bits 8-10 select the conversion mode. 161 // REG_LSL is the index shift specifier, bit 9 indicates shifted offset register. 162 const REG_LSL = obj.RBaseARM64 + 1<<9 163 const REG_EXT = obj.RBaseARM64 + 1<<11 164 165 const ( 166 REG_UXTB = REG_EXT + iota<<8 167 REG_UXTH 168 REG_UXTW 169 REG_UXTX 170 REG_SXTB 171 REG_SXTH 172 REG_SXTW 173 REG_SXTX 174 ) 175 176 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 177 // a special register and the low bits select the register. 178 // SYSREG_END is the last item in the automatically generated system register 179 // declaration, and it is defined in the sysRegEnc.go file. 180 // Define the special register after REG_SPECIAL, the first value of it should be 181 // REG_{name} = SYSREG_END + iota. 182 const ( 183 REG_SPECIAL = obj.RBaseARM64 + 1<<12 184 ) 185 186 // Register assignments: 187 // 188 // compiler allocates R0 up as temps 189 // compiler allocates register variables R7-R25 190 // compiler allocates external registers R26 down 191 // 192 // compiler allocates register variables F7-F26 193 // compiler allocates external registers F26 down 194 const ( 195 REGMIN = REG_R7 // register variables allocated from here to REGMAX 196 REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline 197 REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline 198 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 199 REGMAX = REG_R25 200 201 REGCTXT = REG_R26 // environment for closures 202 REGTMP = REG_R27 // reserved for liblink 203 REGG = REG_R28 // G 204 REGFP = REG_R29 // frame pointer 205 REGLINK = REG_R30 206 207 // ARM64 uses R31 as both stack pointer and zero register, 208 // depending on the instruction. To differentiate RSP from ZR, 209 // we use a different numeric value for REGZERO and REGSP. 210 REGZERO = REG_R31 211 REGSP = REG_RSP 212 213 FREGRET = REG_F0 214 FREGMIN = REG_F7 // first register variable 215 FREGMAX = REG_F26 // last register variable for 7g only 216 FREGEXT = REG_F26 // first external register 217 ) 218 219 // http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf 220 var ARM64DWARFRegisters = map[int16]int16{ 221 REG_R0: 0, 222 REG_R1: 1, 223 REG_R2: 2, 224 REG_R3: 3, 225 REG_R4: 4, 226 REG_R5: 5, 227 REG_R6: 6, 228 REG_R7: 7, 229 REG_R8: 8, 230 REG_R9: 9, 231 REG_R10: 10, 232 REG_R11: 11, 233 REG_R12: 12, 234 REG_R13: 13, 235 REG_R14: 14, 236 REG_R15: 15, 237 REG_R16: 16, 238 REG_R17: 17, 239 REG_R18: 18, 240 REG_R19: 19, 241 REG_R20: 20, 242 REG_R21: 21, 243 REG_R22: 22, 244 REG_R23: 23, 245 REG_R24: 24, 246 REG_R25: 25, 247 REG_R26: 26, 248 REG_R27: 27, 249 REG_R28: 28, 250 REG_R29: 29, 251 REG_R30: 30, 252 253 // floating point 254 REG_F0: 64, 255 REG_F1: 65, 256 REG_F2: 66, 257 REG_F3: 67, 258 REG_F4: 68, 259 REG_F5: 69, 260 REG_F6: 70, 261 REG_F7: 71, 262 REG_F8: 72, 263 REG_F9: 73, 264 REG_F10: 74, 265 REG_F11: 75, 266 REG_F12: 76, 267 REG_F13: 77, 268 REG_F14: 78, 269 REG_F15: 79, 270 REG_F16: 80, 271 REG_F17: 81, 272 REG_F18: 82, 273 REG_F19: 83, 274 REG_F20: 84, 275 REG_F21: 85, 276 REG_F22: 86, 277 REG_F23: 87, 278 REG_F24: 88, 279 REG_F25: 89, 280 REG_F26: 90, 281 REG_F27: 91, 282 REG_F28: 92, 283 REG_F29: 93, 284 REG_F30: 94, 285 REG_F31: 95, 286 287 // SIMD 288 REG_V0: 64, 289 REG_V1: 65, 290 REG_V2: 66, 291 REG_V3: 67, 292 REG_V4: 68, 293 REG_V5: 69, 294 REG_V6: 70, 295 REG_V7: 71, 296 REG_V8: 72, 297 REG_V9: 73, 298 REG_V10: 74, 299 REG_V11: 75, 300 REG_V12: 76, 301 REG_V13: 77, 302 REG_V14: 78, 303 REG_V15: 79, 304 REG_V16: 80, 305 REG_V17: 81, 306 REG_V18: 82, 307 REG_V19: 83, 308 REG_V20: 84, 309 REG_V21: 85, 310 REG_V22: 86, 311 REG_V23: 87, 312 REG_V24: 88, 313 REG_V25: 89, 314 REG_V26: 90, 315 REG_V27: 91, 316 REG_V28: 92, 317 REG_V29: 93, 318 REG_V30: 94, 319 REG_V31: 95, 320 } 321 322 const ( 323 BIG = 2048 - 8 324 ) 325 326 const ( 327 /* mark flags */ 328 LABEL = 1 << iota 329 LEAF 330 FLOAT 331 BRANCH 332 LOAD 333 FCMP 334 SYNC 335 LIST 336 FOLL 337 NOSCHED 338 ) 339 340 const ( 341 // optab is sorted based on the order of these constants 342 // and the first match is chosen. 343 // The more specific class needs to come earlier. 344 C_NONE = iota 345 C_REG // R0..R30 346 C_ZREG // R0..R30, ZR 347 C_RSP // R0..R30, RSP 348 C_FREG // F0..F31 349 C_VREG // V0..V31 350 C_PAIR // (Rn, Rm) 351 C_SHIFT // Rn<<2 352 C_EXTREG // Rn.UXTB[<<3] 353 C_SPR // REG_NZCV 354 C_COND // condition code, EQ, NE, etc. 355 C_SPOP // special operand, PLDL1KEEP, VMALLE1IS, etc. 356 C_ARNG // Vn.<T> 357 C_ELEM // Vn.<T>[index] 358 C_LIST // [V1, V2, V3] 359 360 C_ZCON // $0 361 C_ABCON0 // could be C_ADDCON0 or C_BITCON 362 C_ADDCON0 // 12-bit unsigned, unshifted 363 C_ABCON // could be C_ADDCON or C_BITCON 364 C_AMCON // could be C_ADDCON or C_MOVCON 365 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 366 C_MBCON // could be C_MOVCON or C_BITCON 367 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 368 C_BITCON // bitfield and logical immediate masks 369 C_ADDCON2 // 24-bit constant 370 C_LCON // 32-bit constant 371 C_MOVCON2 // a constant that can be loaded with one MOVZ/MOVN and one MOVK 372 C_MOVCON3 // a constant that can be loaded with one MOVZ/MOVN and two MOVKs 373 C_VCON // 64-bit constant 374 C_FCON // floating-point constant 375 C_VCONADDR // 64-bit memory address 376 377 C_AACON // ADDCON offset in auto constant $a(FP) 378 C_AACON2 // 24-bit offset in auto constant $a(FP) 379 C_LACON // 32-bit offset in auto constant $a(FP) 380 C_AECON // ADDCON offset in extern constant $e(SB) 381 382 // TODO(aram): only one branch class should be enough 383 C_SBRA // for TYPE_BRANCH 384 C_LBRA 385 386 C_ZAUTO // 0(RSP) 387 C_NSAUTO_16 // -256 <= x < 0, 0 mod 16 388 C_NSAUTO_8 // -256 <= x < 0, 0 mod 8 389 C_NSAUTO_4 // -256 <= x < 0, 0 mod 4 390 C_NSAUTO // -256 <= x < 0 391 C_NPAUTO_16 // -512 <= x < 0, 0 mod 16 392 C_NPAUTO // -512 <= x < 0, 0 mod 8 393 C_NQAUTO_16 // -1024 <= x < 0, 0 mod 16 394 C_NAUTO4K // -4095 <= x < 0 395 C_PSAUTO_16 // 0 to 255, 0 mod 16 396 C_PSAUTO_8 // 0 to 255, 0 mod 8 397 C_PSAUTO_4 // 0 to 255, 0 mod 4 398 C_PSAUTO // 0 to 255 399 C_PPAUTO_16 // 0 to 504, 0 mod 16 400 C_PPAUTO // 0 to 504, 0 mod 8 401 C_PQAUTO_16 // 0 to 1008, 0 mod 16 402 C_UAUTO4K_16 // 0 to 4095, 0 mod 16 403 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 404 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 405 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 406 C_UAUTO4K // 0 to 4095 407 C_UAUTO8K_16 // 0 to 8190, 0 mod 16 408 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 409 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 410 C_UAUTO8K // 0 to 8190, 0 mod 2 + C_PSAUTO 411 C_UAUTO16K_16 // 0 to 16380, 0 mod 16 412 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 413 C_UAUTO16K // 0 to 16380, 0 mod 4 + C_PSAUTO 414 C_UAUTO32K_16 // 0 to 32760, 0 mod 16 + C_PSAUTO 415 C_UAUTO32K // 0 to 32760, 0 mod 8 + C_PSAUTO 416 C_UAUTO64K // 0 to 65520, 0 mod 16 + C_PSAUTO 417 C_LAUTO // any other 32-bit constant 418 419 C_SEXT1 // 0 to 4095, direct 420 C_SEXT2 // 0 to 8190 421 C_SEXT4 // 0 to 16380 422 C_SEXT8 // 0 to 32760 423 C_SEXT16 // 0 to 65520 424 C_LEXT 425 426 C_ZOREG // 0(R) 427 C_NSOREG_16 // must mirror C_NSAUTO_16, etc 428 C_NSOREG_8 429 C_NSOREG_4 430 C_NSOREG 431 C_NPOREG_16 432 C_NPOREG 433 C_NQOREG_16 434 C_NOREG4K 435 C_PSOREG_16 436 C_PSOREG_8 437 C_PSOREG_4 438 C_PSOREG 439 C_PPOREG_16 440 C_PPOREG 441 C_PQOREG_16 442 C_UOREG4K_16 443 C_UOREG4K_8 444 C_UOREG4K_4 445 C_UOREG4K_2 446 C_UOREG4K 447 C_UOREG8K_16 448 C_UOREG8K_8 449 C_UOREG8K_4 450 C_UOREG8K 451 C_UOREG16K_16 452 C_UOREG16K_8 453 C_UOREG16K 454 C_UOREG32K_16 455 C_UOREG32K 456 C_UOREG64K 457 C_LOREG 458 459 C_ADDR // TODO(aram): explain difference from C_VCONADDR 460 461 // The GOT slot for a symbol in -dynlink mode. 462 C_GOTADDR 463 464 // TLS "var" in local exec mode: will become a constant offset from 465 // thread local base that is ultimately chosen by the program linker. 466 C_TLS_LE 467 468 // TLS "var" in initial exec mode: will become a memory address (chosen 469 // by the program linker) that the dynamic linker will fill with the 470 // offset from the thread local base. 471 C_TLS_IE 472 473 C_ROFF // register offset (including register extended) 474 475 C_GOK 476 C_TEXTSIZE 477 C_NCLASS // must be last 478 ) 479 480 const ( 481 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 482 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 483 ) 484 485 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 486 487 const ( 488 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 489 AADCS 490 AADCSW 491 AADCW 492 AADD 493 AADDS 494 AADDSW 495 AADDW 496 AADR 497 AADRP 498 AAND 499 AANDS 500 AANDSW 501 AANDW 502 AASR 503 AASRW 504 AAT 505 ABFI 506 ABFIW 507 ABFM 508 ABFMW 509 ABFXIL 510 ABFXILW 511 ABIC 512 ABICS 513 ABICSW 514 ABICW 515 ABRK 516 ACBNZ 517 ACBNZW 518 ACBZ 519 ACBZW 520 ACCMN 521 ACCMNW 522 ACCMP 523 ACCMPW 524 ACINC 525 ACINCW 526 ACINV 527 ACINVW 528 ACLREX 529 ACLS 530 ACLSW 531 ACLZ 532 ACLZW 533 ACMN 534 ACMNW 535 ACMP 536 ACMPW 537 ACNEG 538 ACNEGW 539 ACRC32B 540 ACRC32CB 541 ACRC32CH 542 ACRC32CW 543 ACRC32CX 544 ACRC32H 545 ACRC32W 546 ACRC32X 547 ACSEL 548 ACSELW 549 ACSET 550 ACSETM 551 ACSETMW 552 ACSETW 553 ACSINC 554 ACSINCW 555 ACSINV 556 ACSINVW 557 ACSNEG 558 ACSNEGW 559 ADC 560 ADCPS1 561 ADCPS2 562 ADCPS3 563 ADMB 564 ADRPS 565 ADSB 566 AEON 567 AEONW 568 AEOR 569 AEORW 570 AERET 571 AEXTR 572 AEXTRW 573 AHINT 574 AHLT 575 AHVC 576 AIC 577 AISB 578 ALDADDAB 579 ALDADDAD 580 ALDADDAH 581 ALDADDAW 582 ALDADDALB 583 ALDADDALD 584 ALDADDALH 585 ALDADDALW 586 ALDADDB 587 ALDADDD 588 ALDADDH 589 ALDADDW 590 ALDADDLB 591 ALDADDLD 592 ALDADDLH 593 ALDADDLW 594 ALDAR 595 ALDARB 596 ALDARH 597 ALDARW 598 ALDAXP 599 ALDAXPW 600 ALDAXR 601 ALDAXRB 602 ALDAXRH 603 ALDAXRW 604 ALDCLRAB 605 ALDCLRAD 606 ALDCLRAH 607 ALDCLRAW 608 ALDCLRALB 609 ALDCLRALD 610 ALDCLRALH 611 ALDCLRALW 612 ALDCLRB 613 ALDCLRD 614 ALDCLRH 615 ALDCLRW 616 ALDCLRLB 617 ALDCLRLD 618 ALDCLRLH 619 ALDCLRLW 620 ALDEORAB 621 ALDEORAD 622 ALDEORAH 623 ALDEORAW 624 ALDEORALB 625 ALDEORALD 626 ALDEORALH 627 ALDEORALW 628 ALDEORB 629 ALDEORD 630 ALDEORH 631 ALDEORW 632 ALDEORLB 633 ALDEORLD 634 ALDEORLH 635 ALDEORLW 636 ALDORAB 637 ALDORAD 638 ALDORAH 639 ALDORAW 640 ALDORALB 641 ALDORALD 642 ALDORALH 643 ALDORALW 644 ALDORB 645 ALDORD 646 ALDORH 647 ALDORW 648 ALDORLB 649 ALDORLD 650 ALDORLH 651 ALDORLW 652 ALDP 653 ALDPW 654 ALDPSW 655 ALDXR 656 ALDXRB 657 ALDXRH 658 ALDXRW 659 ALDXP 660 ALDXPW 661 ALSL 662 ALSLW 663 ALSR 664 ALSRW 665 AMADD 666 AMADDW 667 AMNEG 668 AMNEGW 669 AMOVK 670 AMOVKW 671 AMOVN 672 AMOVNW 673 AMOVZ 674 AMOVZW 675 AMRS 676 AMSR 677 AMSUB 678 AMSUBW 679 AMUL 680 AMULW 681 AMVN 682 AMVNW 683 ANEG 684 ANEGS 685 ANEGSW 686 ANEGW 687 ANGC 688 ANGCS 689 ANGCSW 690 ANGCW 691 ANOOP 692 AORN 693 AORNW 694 AORR 695 AORRW 696 APRFM 697 APRFUM 698 ARBIT 699 ARBITW 700 AREM 701 AREMW 702 AREV 703 AREV16 704 AREV16W 705 AREV32 706 AREVW 707 AROR 708 ARORW 709 ASBC 710 ASBCS 711 ASBCSW 712 ASBCW 713 ASBFIZ 714 ASBFIZW 715 ASBFM 716 ASBFMW 717 ASBFX 718 ASBFXW 719 ASDIV 720 ASDIVW 721 ASEV 722 ASEVL 723 ASMADDL 724 ASMC 725 ASMNEGL 726 ASMSUBL 727 ASMULH 728 ASMULL 729 ASTXR 730 ASTXRB 731 ASTXRH 732 ASTXP 733 ASTXPW 734 ASTXRW 735 ASTLP 736 ASTLPW 737 ASTLR 738 ASTLRB 739 ASTLRH 740 ASTLRW 741 ASTLXP 742 ASTLXPW 743 ASTLXR 744 ASTLXRB 745 ASTLXRH 746 ASTLXRW 747 ASTP 748 ASTPW 749 ASUB 750 ASUBS 751 ASUBSW 752 ASUBW 753 ASVC 754 ASXTB 755 ASXTBW 756 ASXTH 757 ASXTHW 758 ASXTW 759 ASYS 760 ASYSL 761 ATBNZ 762 ATBZ 763 ATLBI 764 ATST 765 ATSTW 766 AUBFIZ 767 AUBFIZW 768 AUBFM 769 AUBFMW 770 AUBFX 771 AUBFXW 772 AUDIV 773 AUDIVW 774 AUMADDL 775 AUMNEGL 776 AUMSUBL 777 AUMULH 778 AUMULL 779 AUREM 780 AUREMW 781 AUXTB 782 AUXTH 783 AUXTW 784 AUXTBW 785 AUXTHW 786 AWFE 787 AWFI 788 AYIELD 789 AMOVB 790 AMOVBU 791 AMOVH 792 AMOVHU 793 AMOVW 794 AMOVWU 795 AMOVD 796 AMOVNP 797 AMOVNPW 798 AMOVP 799 AMOVPD 800 AMOVPQ 801 AMOVPS 802 AMOVPSW 803 AMOVPW 804 ASWPAD 805 ASWPAW 806 ASWPAH 807 ASWPAB 808 ASWPALD 809 ASWPALW 810 ASWPALH 811 ASWPALB 812 ASWPD 813 ASWPW 814 ASWPH 815 ASWPB 816 ASWPLD 817 ASWPLW 818 ASWPLH 819 ASWPLB 820 ACASD 821 ACASW 822 ACASH 823 ACASB 824 ACASAD 825 ACASAW 826 ACASLD 827 ACASLW 828 ACASALD 829 ACASALW 830 ACASALH 831 ACASALB 832 ACASPD 833 ACASPW 834 ABEQ 835 ABNE 836 ABCS 837 ABHS 838 ABCC 839 ABLO 840 ABMI 841 ABPL 842 ABVS 843 ABVC 844 ABHI 845 ABLS 846 ABGE 847 ABLT 848 ABGT 849 ABLE 850 AFABSD 851 AFABSS 852 AFADDD 853 AFADDS 854 AFCCMPD 855 AFCCMPED 856 AFCCMPS 857 AFCCMPES 858 AFCMPD 859 AFCMPED 860 AFCMPES 861 AFCMPS 862 AFCVTSD 863 AFCVTDS 864 AFCVTZSD 865 AFCVTZSDW 866 AFCVTZSS 867 AFCVTZSSW 868 AFCVTZUD 869 AFCVTZUDW 870 AFCVTZUS 871 AFCVTZUSW 872 AFDIVD 873 AFDIVS 874 AFLDPD 875 AFLDPQ 876 AFLDPS 877 AFMOVQ 878 AFMOVD 879 AFMOVS 880 AVMOVQ 881 AVMOVD 882 AVMOVS 883 AFMULD 884 AFMULS 885 AFNEGD 886 AFNEGS 887 AFSQRTD 888 AFSQRTS 889 AFSTPD 890 AFSTPQ 891 AFSTPS 892 AFSUBD 893 AFSUBS 894 ASCVTFD 895 ASCVTFS 896 ASCVTFWD 897 ASCVTFWS 898 AUCVTFD 899 AUCVTFS 900 AUCVTFWD 901 AUCVTFWS 902 AWORD 903 ADWORD 904 AFCSELS 905 AFCSELD 906 AFMAXS 907 AFMINS 908 AFMAXD 909 AFMIND 910 AFMAXNMS 911 AFMAXNMD 912 AFNMULS 913 AFNMULD 914 AFRINTNS 915 AFRINTND 916 AFRINTPS 917 AFRINTPD 918 AFRINTMS 919 AFRINTMD 920 AFRINTZS 921 AFRINTZD 922 AFRINTAS 923 AFRINTAD 924 AFRINTXS 925 AFRINTXD 926 AFRINTIS 927 AFRINTID 928 AFMADDS 929 AFMADDD 930 AFMSUBS 931 AFMSUBD 932 AFNMADDS 933 AFNMADDD 934 AFNMSUBS 935 AFNMSUBD 936 AFMINNMS 937 AFMINNMD 938 AFCVTDH 939 AFCVTHS 940 AFCVTHD 941 AFCVTSH 942 AAESD 943 AAESE 944 AAESIMC 945 AAESMC 946 ASHA1C 947 ASHA1H 948 ASHA1M 949 ASHA1P 950 ASHA1SU0 951 ASHA1SU1 952 ASHA256H 953 ASHA256H2 954 ASHA256SU0 955 ASHA256SU1 956 ASHA512H 957 ASHA512H2 958 ASHA512SU0 959 ASHA512SU1 960 AVADD 961 AVADDP 962 AVAND 963 AVBIF 964 AVBCAX 965 AVCMEQ 966 AVCNT 967 AVEOR 968 AVEOR3 969 AVMOV 970 AVLD1 971 AVLD2 972 AVLD3 973 AVLD4 974 AVLD1R 975 AVLD2R 976 AVLD3R 977 AVLD4R 978 AVORR 979 AVREV16 980 AVREV32 981 AVREV64 982 AVST1 983 AVST2 984 AVST3 985 AVST4 986 AVDUP 987 AVADDV 988 AVMOVI 989 AVUADDLV 990 AVSUB 991 AVFMLA 992 AVFMLS 993 AVPMULL 994 AVPMULL2 995 AVEXT 996 AVRBIT 997 AVRAX1 998 AVUMAX 999 AVUMIN 1000 AVUSHR 1001 AVUSHLL 1002 AVUSHLL2 1003 AVUXTL 1004 AVUXTL2 1005 AVUZP1 1006 AVUZP2 1007 AVSHL 1008 AVSRI 1009 AVSLI 1010 AVBSL 1011 AVBIT 1012 AVTBL 1013 AVTBX 1014 AVXAR 1015 AVZIP1 1016 AVZIP2 1017 AVCMTST 1018 AVUADDW2 1019 AVUADDW 1020 AVUSRA 1021 AVTRN1 1022 AVTRN2 1023 ALAST 1024 AB = obj.AJMP 1025 ABL = obj.ACALL 1026 ) 1027 1028 const ( 1029 // shift types 1030 SHIFT_LL = 0 << 22 1031 SHIFT_LR = 1 << 22 1032 SHIFT_AR = 2 << 22 1033 SHIFT_ROR = 3 << 22 1034 ) 1035 1036 // Arrangement for ARM64 SIMD instructions 1037 const ( 1038 // arrangement types 1039 ARNG_8B = iota 1040 ARNG_16B 1041 ARNG_1D 1042 ARNG_4H 1043 ARNG_8H 1044 ARNG_2S 1045 ARNG_4S 1046 ARNG_2D 1047 ARNG_1Q 1048 ARNG_B 1049 ARNG_H 1050 ARNG_S 1051 ARNG_D 1052 ) 1053 1054 //go:generate stringer -type SpecialOperand -trimprefix SPOP_ 1055 type SpecialOperand int 1056 1057 const ( 1058 // PRFM 1059 SPOP_PLDL1KEEP SpecialOperand = iota // must be the first one 1060 SPOP_BEGIN SpecialOperand = iota - 1 // set as the lower bound 1061 SPOP_PLDL1STRM 1062 SPOP_PLDL2KEEP 1063 SPOP_PLDL2STRM 1064 SPOP_PLDL3KEEP 1065 SPOP_PLDL3STRM 1066 SPOP_PLIL1KEEP 1067 SPOP_PLIL1STRM 1068 SPOP_PLIL2KEEP 1069 SPOP_PLIL2STRM 1070 SPOP_PLIL3KEEP 1071 SPOP_PLIL3STRM 1072 SPOP_PSTL1KEEP 1073 SPOP_PSTL1STRM 1074 SPOP_PSTL2KEEP 1075 SPOP_PSTL2STRM 1076 SPOP_PSTL3KEEP 1077 SPOP_PSTL3STRM 1078 1079 // TLBI 1080 SPOP_VMALLE1IS 1081 SPOP_VAE1IS 1082 SPOP_ASIDE1IS 1083 SPOP_VAAE1IS 1084 SPOP_VALE1IS 1085 SPOP_VAALE1IS 1086 SPOP_VMALLE1 1087 SPOP_VAE1 1088 SPOP_ASIDE1 1089 SPOP_VAAE1 1090 SPOP_VALE1 1091 SPOP_VAALE1 1092 SPOP_IPAS2E1IS 1093 SPOP_IPAS2LE1IS 1094 SPOP_ALLE2IS 1095 SPOP_VAE2IS 1096 SPOP_ALLE1IS 1097 SPOP_VALE2IS 1098 SPOP_VMALLS12E1IS 1099 SPOP_IPAS2E1 1100 SPOP_IPAS2LE1 1101 SPOP_ALLE2 1102 SPOP_VAE2 1103 SPOP_ALLE1 1104 SPOP_VALE2 1105 SPOP_VMALLS12E1 1106 SPOP_ALLE3IS 1107 SPOP_VAE3IS 1108 SPOP_VALE3IS 1109 SPOP_ALLE3 1110 SPOP_VAE3 1111 SPOP_VALE3 1112 SPOP_VMALLE1OS 1113 SPOP_VAE1OS 1114 SPOP_ASIDE1OS 1115 SPOP_VAAE1OS 1116 SPOP_VALE1OS 1117 SPOP_VAALE1OS 1118 SPOP_RVAE1IS 1119 SPOP_RVAAE1IS 1120 SPOP_RVALE1IS 1121 SPOP_RVAALE1IS 1122 SPOP_RVAE1OS 1123 SPOP_RVAAE1OS 1124 SPOP_RVALE1OS 1125 SPOP_RVAALE1OS 1126 SPOP_RVAE1 1127 SPOP_RVAAE1 1128 SPOP_RVALE1 1129 SPOP_RVAALE1 1130 SPOP_RIPAS2E1IS 1131 SPOP_RIPAS2LE1IS 1132 SPOP_ALLE2OS 1133 SPOP_VAE2OS 1134 SPOP_ALLE1OS 1135 SPOP_VALE2OS 1136 SPOP_VMALLS12E1OS 1137 SPOP_RVAE2IS 1138 SPOP_RVALE2IS 1139 SPOP_IPAS2E1OS 1140 SPOP_RIPAS2E1 1141 SPOP_RIPAS2E1OS 1142 SPOP_IPAS2LE1OS 1143 SPOP_RIPAS2LE1 1144 SPOP_RIPAS2LE1OS 1145 SPOP_RVAE2OS 1146 SPOP_RVALE2OS 1147 SPOP_RVAE2 1148 SPOP_RVALE2 1149 SPOP_ALLE3OS 1150 SPOP_VAE3OS 1151 SPOP_VALE3OS 1152 SPOP_RVAE3IS 1153 SPOP_RVALE3IS 1154 SPOP_RVAE3OS 1155 SPOP_RVALE3OS 1156 SPOP_RVAE3 1157 SPOP_RVALE3 1158 1159 // DC 1160 SPOP_IVAC 1161 SPOP_ISW 1162 SPOP_CSW 1163 SPOP_CISW 1164 SPOP_ZVA 1165 SPOP_CVAC 1166 SPOP_CVAU 1167 SPOP_CIVAC 1168 SPOP_IGVAC 1169 SPOP_IGSW 1170 SPOP_IGDVAC 1171 SPOP_IGDSW 1172 SPOP_CGSW 1173 SPOP_CGDSW 1174 SPOP_CIGSW 1175 SPOP_CIGDSW 1176 SPOP_GVA 1177 SPOP_GZVA 1178 SPOP_CGVAC 1179 SPOP_CGDVAC 1180 SPOP_CGVAP 1181 SPOP_CGDVAP 1182 SPOP_CGVADP 1183 SPOP_CGDVADP 1184 SPOP_CIGVAC 1185 SPOP_CIGDVAC 1186 SPOP_CVAP 1187 SPOP_CVADP 1188 1189 // PSTATE fields 1190 SPOP_DAIFSet 1191 SPOP_DAIFClr 1192 1193 // Condition code, EQ, NE, etc. Their relative order to EQ is matter. 1194 SPOP_EQ 1195 SPOP_NE 1196 SPOP_HS 1197 SPOP_LO 1198 SPOP_MI 1199 SPOP_PL 1200 SPOP_VS 1201 SPOP_VC 1202 SPOP_HI 1203 SPOP_LS 1204 SPOP_GE 1205 SPOP_LT 1206 SPOP_GT 1207 SPOP_LE 1208 SPOP_AL 1209 SPOP_NV 1210 // Condition code end. 1211 1212 SPOP_END 1213 )