github.com/bir3/gocompiler@v0.3.205/src/cmd/internal/obj/loong64/a.out.go (about) 1 // Copyright 2022 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 package loong64 6 7 import ( 8 "github.com/bir3/gocompiler/src/cmd/internal/obj" 9 ) 10 11 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64 12 13 const ( 14 NSNAME = 8 15 NSYM = 50 16 NREG = 32 // number of general registers 17 NFREG = 32 // number of floating point registers 18 ) 19 20 const ( 21 REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32 22 REG_R1 23 REG_R2 24 REG_R3 25 REG_R4 26 REG_R5 27 REG_R6 28 REG_R7 29 REG_R8 30 REG_R9 31 REG_R10 32 REG_R11 33 REG_R12 34 REG_R13 35 REG_R14 36 REG_R15 37 REG_R16 38 REG_R17 39 REG_R18 40 REG_R19 41 REG_R20 42 REG_R21 43 REG_R22 44 REG_R23 45 REG_R24 46 REG_R25 47 REG_R26 48 REG_R27 49 REG_R28 50 REG_R29 51 REG_R30 52 REG_R31 53 54 REG_F0 // must be a multiple of 32 55 REG_F1 56 REG_F2 57 REG_F3 58 REG_F4 59 REG_F5 60 REG_F6 61 REG_F7 62 REG_F8 63 REG_F9 64 REG_F10 65 REG_F11 66 REG_F12 67 REG_F13 68 REG_F14 69 REG_F15 70 REG_F16 71 REG_F17 72 REG_F18 73 REG_F19 74 REG_F20 75 REG_F21 76 REG_F22 77 REG_F23 78 REG_F24 79 REG_F25 80 REG_F26 81 REG_F27 82 REG_F28 83 REG_F29 84 REG_F30 85 REG_F31 86 87 REG_FCSR0 // must be a multiple of 32 88 REG_FCSR1 89 REG_FCSR2 90 REG_FCSR3 // only four registers are needed 91 REG_FCSR4 92 REG_FCSR5 93 REG_FCSR6 94 REG_FCSR7 95 REG_FCSR8 96 REG_FCSR9 97 REG_FCSR10 98 REG_FCSR11 99 REG_FCSR12 100 REG_FCSR13 101 REG_FCSR14 102 REG_FCSR15 103 REG_FCSR16 104 REG_FCSR17 105 REG_FCSR18 106 REG_FCSR19 107 REG_FCSR20 108 REG_FCSR21 109 REG_FCSR22 110 REG_FCSR23 111 REG_FCSR24 112 REG_FCSR25 113 REG_FCSR26 114 REG_FCSR27 115 REG_FCSR28 116 REG_FCSR29 117 REG_FCSR30 118 REG_FCSR31 119 120 REG_FCC0 // must be a multiple of 32 121 REG_FCC1 122 REG_FCC2 123 REG_FCC3 124 REG_FCC4 125 REG_FCC5 126 REG_FCC6 127 REG_FCC7 // only eight registers are needed 128 REG_FCC8 129 REG_FCC9 130 REG_FCC10 131 REG_FCC11 132 REG_FCC12 133 REG_FCC13 134 REG_FCC14 135 REG_FCC15 136 REG_FCC16 137 REG_FCC17 138 REG_FCC18 139 REG_FCC19 140 REG_FCC20 141 REG_FCC21 142 REG_FCC22 143 REG_FCC23 144 REG_FCC24 145 REG_FCC25 146 REG_FCC26 147 REG_FCC27 148 REG_FCC28 149 REG_FCC29 150 REG_FCC30 151 REG_FCC31 152 153 REG_LAST = REG_FCC31 // the last defined register 154 155 REG_SPECIAL = REG_FCSR0 156 157 REGZERO = REG_R0 // set to zero 158 REGLINK = REG_R1 159 REGSP = REG_R3 160 REGRET = REG_R19 161 REGARG = -1 // -1 disables passing the first argument in register 162 REGRT1 = REG_R19 // reserved for runtime, duffzero and duffcopy 163 REGRT2 = REG_R20 // reserved for runtime, duffcopy 164 REGCTXT = REG_R29 // context for closures 165 REGG = REG_R22 // G in loong64 166 REGTMP = REG_R30 // used by the assembler 167 FREGRET = REG_F0 168 ) 169 170 var LOONG64DWARFRegisters = map[int16]int16{} 171 172 func init() { 173 // f assigns dwarfregisters[from:to] = (base):(to-from+base) 174 f := func(from, to, base int16) { 175 for r := int16(from); r <= to; r++ { 176 LOONG64DWARFRegisters[r] = (r - from) + base 177 } 178 } 179 f(REG_R0, REG_R31, 0) 180 f(REG_F0, REG_F31, 32) 181 182 } 183 184 const ( 185 BIG = 2046 186 ) 187 188 const ( 189 // mark flags 190 LABEL = 1 << 0 191 LEAF = 1 << 1 192 SYNC = 1 << 2 193 BRANCH = 1 << 3 194 ) 195 196 const ( 197 C_NONE = iota 198 C_REG 199 C_FREG 200 C_FCSRREG 201 C_FCCREG 202 C_ZCON 203 C_SCON // 12 bit signed 204 C_UCON // 32 bit signed, low 12 bits 0 205 C_ADD0CON 206 C_AND0CON 207 C_ADDCON // -0x800 <= v < 0 208 C_ANDCON // 0 < v <= 0xFFF 209 C_LCON // other 32 210 C_DCON // other 64 (could subdivide further) 211 C_SACON // $n(REG) where n <= int12 212 C_SECON 213 C_LACON // $n(REG) where int12 < n <= int32 214 C_LECON 215 C_DACON // $n(REG) where int32 < n 216 C_STCON // $tlsvar 217 C_SBRA 218 C_LBRA 219 C_SAUTO 220 C_LAUTO 221 C_SEXT 222 C_LEXT 223 C_ZOREG 224 C_SOREG 225 C_LOREG 226 C_GOK 227 C_ADDR 228 C_TLS 229 C_TEXTSIZE 230 231 C_NCLASS // must be the last 232 ) 233 234 const ( 235 AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota 236 AABSF 237 AADD 238 AADDD 239 AADDF 240 AADDU 241 242 AADDW 243 AAND 244 ABEQ 245 ABGEZ 246 ABLEZ 247 ABGTZ 248 ABLTZ 249 ABFPF 250 ABFPT 251 252 ABNE 253 ABREAK 254 ACLO 255 ACLZ 256 257 ACMPEQD 258 ACMPEQF 259 260 ACMPGED // ACMPGED -> fcmp.sle.d 261 ACMPGEF // ACMPGEF -> fcmp.sle.s 262 ACMPGTD // ACMPGTD -> fcmp.slt.d 263 ACMPGTF // ACMPGTF -> fcmp.slt.s 264 265 ALU12IW 266 ALU32ID 267 ALU52ID 268 APCADDU12I 269 AJIRL 270 ABGE 271 ABLT 272 ABLTU 273 ABGEU 274 275 ADIV 276 ADIVD 277 ADIVF 278 ADIVU 279 ADIVW 280 281 ALL 282 ALLV 283 284 ALUI 285 286 AMOVB 287 AMOVBU 288 289 AMOVD 290 AMOVDF 291 AMOVDW 292 AMOVF 293 AMOVFD 294 AMOVFW 295 296 AMOVH 297 AMOVHU 298 AMOVW 299 300 AMOVWD 301 AMOVWF 302 303 AMOVWL 304 AMOVWR 305 306 AMUL 307 AMULD 308 AMULF 309 AMULU 310 AMULH 311 AMULHU 312 AMULW 313 ANEGD 314 ANEGF 315 316 ANEGW 317 ANEGV 318 319 ANOOP // hardware nop 320 ANOR 321 AOR 322 AREM 323 AREMU 324 325 ARFE 326 327 ASC 328 ASCV 329 330 ASGT 331 ASGTU 332 333 ASLL 334 ASQRTD 335 ASQRTF 336 ASRA 337 ASRL 338 AROTR 339 ASUB 340 ASUBD 341 ASUBF 342 343 ASUBU 344 ASUBW 345 ADBAR 346 ASYSCALL 347 348 ATEQ 349 ATNE 350 351 AWORD 352 353 AXOR 354 355 AMASKEQZ 356 AMASKNEZ 357 358 // 64-bit 359 AMOVV 360 AMOVVL 361 AMOVVR 362 363 ASLLV 364 ASRAV 365 ASRLV 366 AROTRV 367 ADIVV 368 ADIVVU 369 370 AREMV 371 AREMVU 372 373 AMULV 374 AMULVU 375 AMULHV 376 AMULHVU 377 AADDV 378 AADDVU 379 ASUBV 380 ASUBVU 381 382 // 64-bit FP 383 ATRUNCFV 384 ATRUNCDV 385 ATRUNCFW 386 ATRUNCDW 387 388 AMOVWU 389 AMOVFV 390 AMOVDV 391 AMOVVF 392 AMOVVD 393 394 ALAST 395 396 // aliases 397 AJMP = obj.AJMP 398 AJAL = obj.ACALL 399 ARET = obj.ARET 400 ) 401 402 func init() { 403 // The asm encoder generally assumes that the lowest 5 bits of the 404 // REG_XX constants match the machine instruction encoding, i.e. 405 // the lowest 5 bits is the register number. 406 // Check this here. 407 if REG_R0%32 != 0 { 408 panic("REG_R0 is not a multiple of 32") 409 } 410 if REG_F0%32 != 0 { 411 panic("REG_F0 is not a multiple of 32") 412 } 413 if REG_FCSR0%32 != 0 { 414 panic("REG_FCSR0 is not a multiple of 32") 415 } 416 if REG_FCC0%32 != 0 { 417 panic("REG_FCC0 is not a multiple of 32") 418 } 419 }