github.com/bir3/gocompiler@v0.3.205/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "github.com/bir3/gocompiler/src/cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 83 REG_CR0LT 84 REG_CR0GT 85 REG_CR0EQ 86 REG_CR0SO 87 REG_CR1LT 88 REG_CR1GT 89 REG_CR1EQ 90 REG_CR1SO 91 REG_CR2LT 92 REG_CR2GT 93 REG_CR2EQ 94 REG_CR2SO 95 REG_CR3LT 96 REG_CR3GT 97 REG_CR3EQ 98 REG_CR3SO 99 REG_CR4LT 100 REG_CR4GT 101 REG_CR4EQ 102 REG_CR4SO 103 REG_CR5LT 104 REG_CR5GT 105 REG_CR5EQ 106 REG_CR5SO 107 REG_CR6LT 108 REG_CR6GT 109 REG_CR6EQ 110 REG_CR6SO 111 REG_CR7LT 112 REG_CR7GT 113 REG_CR7EQ 114 REG_CR7SO 115 116 /* Align FPR and VSR vectors such that when masked with 0x3F they produce 117 an equivalent VSX register. */ 118 /* F0=4160 ... F31=4191 */ 119 REG_F0 120 REG_F1 121 REG_F2 122 REG_F3 123 REG_F4 124 REG_F5 125 REG_F6 126 REG_F7 127 REG_F8 128 REG_F9 129 REG_F10 130 REG_F11 131 REG_F12 132 REG_F13 133 REG_F14 134 REG_F15 135 REG_F16 136 REG_F17 137 REG_F18 138 REG_F19 139 REG_F20 140 REG_F21 141 REG_F22 142 REG_F23 143 REG_F24 144 REG_F25 145 REG_F26 146 REG_F27 147 REG_F28 148 REG_F29 149 REG_F30 150 REG_F31 151 152 /* V0=4192 ... V31=4223 */ 153 REG_V0 154 REG_V1 155 REG_V2 156 REG_V3 157 REG_V4 158 REG_V5 159 REG_V6 160 REG_V7 161 REG_V8 162 REG_V9 163 REG_V10 164 REG_V11 165 REG_V12 166 REG_V13 167 REG_V14 168 REG_V15 169 REG_V16 170 REG_V17 171 REG_V18 172 REG_V19 173 REG_V20 174 REG_V21 175 REG_V22 176 REG_V23 177 REG_V24 178 REG_V25 179 REG_V26 180 REG_V27 181 REG_V28 182 REG_V29 183 REG_V30 184 REG_V31 185 186 /* VS0=4224 ... VS63=4287 */ 187 REG_VS0 188 REG_VS1 189 REG_VS2 190 REG_VS3 191 REG_VS4 192 REG_VS5 193 REG_VS6 194 REG_VS7 195 REG_VS8 196 REG_VS9 197 REG_VS10 198 REG_VS11 199 REG_VS12 200 REG_VS13 201 REG_VS14 202 REG_VS15 203 REG_VS16 204 REG_VS17 205 REG_VS18 206 REG_VS19 207 REG_VS20 208 REG_VS21 209 REG_VS22 210 REG_VS23 211 REG_VS24 212 REG_VS25 213 REG_VS26 214 REG_VS27 215 REG_VS28 216 REG_VS29 217 REG_VS30 218 REG_VS31 219 REG_VS32 220 REG_VS33 221 REG_VS34 222 REG_VS35 223 REG_VS36 224 REG_VS37 225 REG_VS38 226 REG_VS39 227 REG_VS40 228 REG_VS41 229 REG_VS42 230 REG_VS43 231 REG_VS44 232 REG_VS45 233 REG_VS46 234 REG_VS47 235 REG_VS48 236 REG_VS49 237 REG_VS50 238 REG_VS51 239 REG_VS52 240 REG_VS53 241 REG_VS54 242 REG_VS55 243 REG_VS56 244 REG_VS57 245 REG_VS58 246 REG_VS59 247 REG_VS60 248 REG_VS61 249 REG_VS62 250 REG_VS63 251 252 REG_CR0 253 REG_CR1 254 REG_CR2 255 REG_CR3 256 REG_CR4 257 REG_CR5 258 REG_CR6 259 REG_CR7 260 261 // MMA accumulator registers, these shadow VSR 0-31 262 // e.g MMAx shadows VSRx*4-VSRx*4+3 or 263 // MMA0 shadows VSR0-VSR3 264 REG_A0 265 REG_A1 266 REG_A2 267 REG_A3 268 REG_A4 269 REG_A5 270 REG_A6 271 REG_A7 272 273 REG_MSR 274 REG_FPSCR 275 REG_CR 276 277 REG_SPECIAL = REG_CR0 278 279 REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0 280 281 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 282 283 REG_XER = REG_SPR0 + 1 284 REG_LR = REG_SPR0 + 8 285 REG_CTR = REG_SPR0 + 9 286 287 REGZERO = REG_R0 /* set to zero */ 288 REGSP = REG_R1 289 REGSB = REG_R2 290 REGRET = REG_R3 291 REGARG = -1 /* -1 disables passing the first argument in register */ 292 REGRT1 = REG_R20 /* reserved for runtime, duffzero and duffcopy */ 293 REGRT2 = REG_R21 /* reserved for runtime, duffcopy */ 294 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 295 REGCTXT = REG_R11 /* context for closures */ 296 REGTLS = REG_R13 /* C ABI TLS base pointer */ 297 REGMAX = REG_R27 298 REGEXT = REG_R30 /* external registers allocated from here down */ 299 REGG = REG_R30 /* G */ 300 REGTMP = REG_R31 /* used by the linker */ 301 FREGRET = REG_F0 302 FREGMIN = REG_F17 /* first register variable */ 303 FREGMAX = REG_F26 /* last register variable for 9g only */ 304 FREGEXT = REG_F26 /* first external register */ 305 ) 306 307 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 308 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 309 var PPC64DWARFRegisters = map[int16]int16{} 310 311 func init() { 312 // f assigns dwarfregister[from:to] = (base):(to-from+base) 313 f := func(from, to, base int16) { 314 for r := int16(from); r <= to; r++ { 315 PPC64DWARFRegisters[r] = r - from + base 316 } 317 } 318 f(REG_R0, REG_R31, 0) 319 f(REG_F0, REG_F31, 32) 320 f(REG_V0, REG_V31, 77) 321 f(REG_CR0, REG_CR7, 68) 322 323 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31 324 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31 325 PPC64DWARFRegisters[REG_LR] = 65 326 PPC64DWARFRegisters[REG_CTR] = 66 327 PPC64DWARFRegisters[REG_XER] = 76 328 } 329 330 /* 331 * GENERAL: 332 * 333 * compiler allocates R3 up as temps 334 * compiler allocates register variables R7-R27 335 * compiler allocates external registers R30 down 336 * 337 * compiler allocates register variables F17-F26 338 * compiler allocates external registers F26 down 339 */ 340 const ( 341 BIG = 32768 - 8 342 ) 343 344 const ( 345 /* mark flags */ 346 LABEL = 1 << 0 347 LEAF = 1 << 1 348 FLOAT = 1 << 2 349 BRANCH = 1 << 3 350 LOAD = 1 << 4 351 FCMP = 1 << 5 352 SYNC = 1 << 6 353 LIST = 1 << 7 354 FOLL = 1 << 8 355 NOSCHED = 1 << 9 356 PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary 357 ) 358 359 // Values for use in branch instruction BC 360 // BC B0,BI,label 361 // BO is type of branch + likely bits described below 362 // BI is CR value + branch type 363 // ex: BEQ CR2,label is BC 12,10,label 364 // 12 = BO_BCR 365 // 10 = BI_CR2 + BI_EQ 366 367 const ( 368 BI_CR0 = 0 369 BI_CR1 = 4 370 BI_CR2 = 8 371 BI_CR3 = 12 372 BI_CR4 = 16 373 BI_CR5 = 20 374 BI_CR6 = 24 375 BI_CR7 = 28 376 BI_LT = 0 377 BI_GT = 1 378 BI_EQ = 2 379 BI_FU = 3 380 ) 381 382 // Common values for the BO field. 383 384 const ( 385 BO_ALWAYS = 20 // branch unconditionally 386 BO_BCTR = 16 // decrement ctr, branch on ctr != 0 387 BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0 388 BO_BCR = 12 // branch on cr value 389 BO_BCRBCTR = 8 // decrement ctr, branch on ctr != 0 and cr value 390 BO_NOTBCR = 4 // branch on not cr value 391 ) 392 393 // Bit settings from the CR 394 395 const ( 396 C_COND_LT = iota // 0 result is negative 397 C_COND_GT // 1 result is positive 398 C_COND_EQ // 2 result is zero 399 C_COND_SO // 3 summary overflow or FP compare w/ NaN 400 ) 401 402 const ( 403 C_NONE = iota 404 C_REGP /* An even numbered gpr which can be used a gpr pair argument */ 405 C_REG /* Any gpr register */ 406 C_FREGP /* An even numbered fpr which can be used a fpr pair argument */ 407 C_FREG /* Any fpr register */ 408 C_VREG /* Any vector register */ 409 C_VSREGP /* An even numbered vsx register which can be used as a vsx register pair argument */ 410 C_VSREG /* Any vector-scalar register */ 411 C_CREG /* The condition registor (CR) */ 412 C_CRBIT /* A single bit of the CR register (0-31) */ 413 C_SPR /* special processor register */ 414 C_AREG /* MMA accumulator register */ 415 C_ZCON /* The constant zero */ 416 C_U1CON /* 1 bit unsigned constant */ 417 C_U2CON /* 2 bit unsigned constant */ 418 C_U3CON /* 3 bit unsigned constant */ 419 C_U4CON /* 4 bit unsigned constant */ 420 C_U5CON /* 5 bit unsigned constant */ 421 C_U8CON /* 8 bit unsigned constant */ 422 C_U15CON /* 15 bit unsigned constant */ 423 C_S16CON /* 16 bit signed constant */ 424 C_U16CON /* 16 bit unsigned constant */ 425 C_32S16CON /* Any 32 bit constant of the form 0x....0000, signed or unsigned */ 426 C_32CON /* Any constant which fits into 32 bits. Can be signed or unsigned */ 427 C_S34CON /* 34 bit signed constant */ 428 C_64CON /* Any constant which fits into 64 bits. Can be signed or unsigned */ 429 C_SACON /* $n(REG) where n <= int16 */ 430 C_LACON /* $n(REG) where n <= int32 */ 431 C_DACON /* $n(REG) where n <= int64 */ 432 C_SBRA /* A short offset argument to a branching instruction */ 433 C_LBRA /* A long offset argument to a branching instruction */ 434 C_LBRAPIC /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */ 435 C_ZOREG /* An $0+reg memory op */ 436 C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ 437 C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ 438 C_XOREG /* An reg+reg memory arg */ 439 C_FPSCR /* The fpscr register */ 440 C_XER /* The xer, holds the carry bit */ 441 C_LR /* The link register */ 442 C_CTR /* The count register */ 443 C_ANY /* Any argument */ 444 C_GOK /* A non-matched argument */ 445 C_ADDR /* A symbolic memory location */ 446 C_TLS_LE /* A thread local, local-exec, type memory arg */ 447 C_TLS_IE /* A thread local, initial-exec, type memory arg */ 448 C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */ 449 450 C_NCLASS /* must be the last */ 451 452 /* Aliased names which should be cleaned up, or integrated. */ 453 C_SCON = C_U15CON 454 C_UCON = C_32S16CON 455 C_ADDCON = C_S16CON 456 C_ANDCON = C_U16CON 457 C_LCON = C_32CON 458 459 /* Aliased names which may be generated by ppc64map for the optab. */ 460 C_S3216CON = C_32S16CON // TODO: these should be treated differently (e.g xoris vs addis) 461 C_U3216CON = C_32S16CON 462 C_S32CON = C_32CON 463 C_U32CON = C_32CON 464 ) 465 466 const ( 467 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 468 AADDCC 469 AADDIS 470 AADDV 471 AADDVCC 472 AADDC 473 AADDCCC 474 AADDCV 475 AADDCVCC 476 AADDME 477 AADDMECC 478 AADDMEVCC 479 AADDMEV 480 AADDE 481 AADDECC 482 AADDEVCC 483 AADDEV 484 AADDZE 485 AADDZECC 486 AADDZEVCC 487 AADDZEV 488 AADDEX 489 AAND 490 AANDCC 491 AANDN 492 AANDNCC 493 AANDISCC 494 ABC 495 ABCL 496 ABEQ 497 ABGE // not LT = G/E/U 498 ABGT 499 ABLE // not GT = L/E/U 500 ABLT 501 ABNE // not EQ = L/G/U 502 ABVC // Branch if float not unordered (also branch on not summary overflow) 503 ABVS // Branch if float unordered (also branch on summary overflow) 504 ABDNZ // Decrement CTR, and branch if CTR != 0 505 ABDZ // Decrement CTR, and branch if CTR == 0 506 ACMP 507 ACMPU 508 ACMPEQB 509 ACNTLZW 510 ACNTLZWCC 511 ACRAND 512 ACRANDN 513 ACREQV 514 ACRNAND 515 ACRNOR 516 ACROR 517 ACRORN 518 ACRXOR 519 ADIVW 520 ADIVWCC 521 ADIVWVCC 522 ADIVWV 523 ADIVWU 524 ADIVWUCC 525 ADIVWUVCC 526 ADIVWUV 527 AMODUD 528 AMODUW 529 AMODSD 530 AMODSW 531 AEQV 532 AEQVCC 533 AEXTSB 534 AEXTSBCC 535 AEXTSH 536 AEXTSHCC 537 AFABS 538 AFABSCC 539 AFADD 540 AFADDCC 541 AFADDS 542 AFADDSCC 543 AFCMPO 544 AFCMPU 545 AFCTIW 546 AFCTIWCC 547 AFCTIWZ 548 AFCTIWZCC 549 AFDIV 550 AFDIVCC 551 AFDIVS 552 AFDIVSCC 553 AFMADD 554 AFMADDCC 555 AFMADDS 556 AFMADDSCC 557 AFMOVD 558 AFMOVDCC 559 AFMOVDU 560 AFMOVS 561 AFMOVSU 562 AFMOVSX 563 AFMOVSZ 564 AFMSUB 565 AFMSUBCC 566 AFMSUBS 567 AFMSUBSCC 568 AFMUL 569 AFMULCC 570 AFMULS 571 AFMULSCC 572 AFNABS 573 AFNABSCC 574 AFNEG 575 AFNEGCC 576 AFNMADD 577 AFNMADDCC 578 AFNMADDS 579 AFNMADDSCC 580 AFNMSUB 581 AFNMSUBCC 582 AFNMSUBS 583 AFNMSUBSCC 584 AFRSP 585 AFRSPCC 586 AFSUB 587 AFSUBCC 588 AFSUBS 589 AFSUBSCC 590 AISEL 591 AMOVMW 592 ALBAR 593 ALHAR 594 ALSW 595 ALWAR 596 ALWSYNC 597 AMOVDBR 598 AMOVWBR 599 AMOVB 600 AMOVBU 601 AMOVBZ 602 AMOVBZU 603 AMOVH 604 AMOVHBR 605 AMOVHU 606 AMOVHZ 607 AMOVHZU 608 AMOVW 609 AMOVWU 610 AMOVFL 611 AMOVCRFS 612 AMTFSB0 613 AMTFSB0CC 614 AMTFSB1 615 AMTFSB1CC 616 AMULHW 617 AMULHWCC 618 AMULHWU 619 AMULHWUCC 620 AMULLW 621 AMULLWCC 622 AMULLWVCC 623 AMULLWV 624 ANAND 625 ANANDCC 626 ANEG 627 ANEGCC 628 ANEGVCC 629 ANEGV 630 ANOR 631 ANORCC 632 AOR 633 AORCC 634 AORN 635 AORNCC 636 AORIS 637 AREM 638 AREMU 639 ARFI 640 ARLWMI 641 ARLWMICC 642 ARLWNM 643 ARLWNMCC 644 ACLRLSLWI 645 ASLW 646 ASLWCC 647 ASRW 648 ASRAW 649 ASRAWCC 650 ASRWCC 651 ASTBCCC 652 ASTHCCC 653 ASTSW 654 ASTWCCC 655 ASUB 656 ASUBCC 657 ASUBVCC 658 ASUBC 659 ASUBCCC 660 ASUBCV 661 ASUBCVCC 662 ASUBME 663 ASUBMECC 664 ASUBMEVCC 665 ASUBMEV 666 ASUBV 667 ASUBE 668 ASUBECC 669 ASUBEV 670 ASUBEVCC 671 ASUBZE 672 ASUBZECC 673 ASUBZEVCC 674 ASUBZEV 675 ASYNC 676 AXOR 677 AXORCC 678 AXORIS 679 680 ADCBF 681 ADCBI 682 ADCBST 683 ADCBT 684 ADCBTST 685 ADCBZ 686 AEIEIO 687 AICBI 688 AISYNC 689 APTESYNC 690 ATLBIE 691 ATLBIEL 692 ATLBSYNC 693 ATW 694 695 ASYSCALL 696 AWORD 697 698 ARFCI 699 700 AFCPSGN 701 AFCPSGNCC 702 /* optional on 32-bit */ 703 AFRES 704 AFRESCC 705 AFRIM 706 AFRIMCC 707 AFRIP 708 AFRIPCC 709 AFRIZ 710 AFRIZCC 711 AFRIN 712 AFRINCC 713 AFRSQRTE 714 AFRSQRTECC 715 AFSEL 716 AFSELCC 717 AFSQRT 718 AFSQRTCC 719 AFSQRTS 720 AFSQRTSCC 721 722 /* 64-bit */ 723 724 ACNTLZD 725 ACNTLZDCC 726 ACMPW /* CMP with L=0 */ 727 ACMPWU 728 ACMPB 729 AFTDIV 730 AFTSQRT 731 ADIVD 732 ADIVDCC 733 ADIVDE 734 ADIVDECC 735 ADIVDEU 736 ADIVDEUCC 737 ADIVDVCC 738 ADIVDV 739 ADIVDU 740 ADIVDUCC 741 ADIVDUVCC 742 ADIVDUV 743 AEXTSW 744 AEXTSWCC 745 /* AFCFIW; AFCFIWCC */ 746 AFCFID 747 AFCFIDCC 748 AFCFIDU 749 AFCFIDUCC 750 AFCFIDS 751 AFCFIDSCC 752 AFCTID 753 AFCTIDCC 754 AFCTIDZ 755 AFCTIDZCC 756 ALDAR 757 AMOVD 758 AMOVDU 759 AMOVWZ 760 AMOVWZU 761 AMULHD 762 AMULHDCC 763 AMULHDU 764 AMULHDUCC 765 AMULLD 766 AMULLDCC 767 AMULLDVCC 768 AMULLDV 769 ARFID 770 ARLDMI 771 ARLDMICC 772 ARLDIMI 773 ARLDIMICC 774 ARLDC 775 ARLDCCC 776 ARLDCR 777 ARLDCRCC 778 ARLDICR 779 ARLDICRCC 780 ARLDCL 781 ARLDCLCC 782 ARLDICL 783 ARLDICLCC 784 ARLDIC 785 ARLDICCC 786 ACLRLSLDI 787 AROTL 788 AROTLW 789 ASLBIA 790 ASLBIE 791 ASLBMFEE 792 ASLBMFEV 793 ASLBMTE 794 ASLD 795 ASLDCC 796 ASRD 797 ASRAD 798 ASRADCC 799 ASRDCC 800 AEXTSWSLI 801 AEXTSWSLICC 802 ASTDCCC 803 ATD 804 805 /* 64-bit pseudo operation */ 806 ADWORD 807 AREMD 808 AREMDU 809 810 /* more 64-bit operations */ 811 AHRFID 812 APOPCNTD 813 APOPCNTW 814 APOPCNTB 815 ACNTTZW 816 ACNTTZWCC 817 ACNTTZD 818 ACNTTZDCC 819 ACOPY 820 APASTECC 821 ADARN 822 AMADDHD 823 AMADDHDU 824 AMADDLD 825 826 /* Vector */ 827 ALVEBX 828 ALVEHX 829 ALVEWX 830 ALVX 831 ALVXL 832 ALVSL 833 ALVSR 834 ASTVEBX 835 ASTVEHX 836 ASTVEWX 837 ASTVX 838 ASTVXL 839 AVAND 840 AVANDC 841 AVNAND 842 AVOR 843 AVORC 844 AVNOR 845 AVXOR 846 AVEQV 847 AVADDUM 848 AVADDUBM 849 AVADDUHM 850 AVADDUWM 851 AVADDUDM 852 AVADDUQM 853 AVADDCU 854 AVADDCUQ 855 AVADDCUW 856 AVADDUS 857 AVADDUBS 858 AVADDUHS 859 AVADDUWS 860 AVADDSS 861 AVADDSBS 862 AVADDSHS 863 AVADDSWS 864 AVADDE 865 AVADDEUQM 866 AVADDECUQ 867 AVSUBUM 868 AVSUBUBM 869 AVSUBUHM 870 AVSUBUWM 871 AVSUBUDM 872 AVSUBUQM 873 AVSUBCU 874 AVSUBCUQ 875 AVSUBCUW 876 AVSUBUS 877 AVSUBUBS 878 AVSUBUHS 879 AVSUBUWS 880 AVSUBSS 881 AVSUBSBS 882 AVSUBSHS 883 AVSUBSWS 884 AVSUBE 885 AVSUBEUQM 886 AVSUBECUQ 887 AVMULESB 888 AVMULOSB 889 AVMULEUB 890 AVMULOUB 891 AVMULESH 892 AVMULOSH 893 AVMULEUH 894 AVMULOUH 895 AVMULESW 896 AVMULOSW 897 AVMULEUW 898 AVMULOUW 899 AVMULUWM 900 AVPMSUM 901 AVPMSUMB 902 AVPMSUMH 903 AVPMSUMW 904 AVPMSUMD 905 AVMSUMUDM 906 AVR 907 AVRLB 908 AVRLH 909 AVRLW 910 AVRLD 911 AVS 912 AVSLB 913 AVSLH 914 AVSLW 915 AVSL 916 AVSLO 917 AVSRB 918 AVSRH 919 AVSRW 920 AVSR 921 AVSRO 922 AVSLD 923 AVSRD 924 AVSA 925 AVSRAB 926 AVSRAH 927 AVSRAW 928 AVSRAD 929 AVSOI 930 AVSLDOI 931 AVCLZ 932 AVCLZB 933 AVCLZH 934 AVCLZW 935 AVCLZD 936 AVPOPCNT 937 AVPOPCNTB 938 AVPOPCNTH 939 AVPOPCNTW 940 AVPOPCNTD 941 AVCMPEQ 942 AVCMPEQUB 943 AVCMPEQUBCC 944 AVCMPEQUH 945 AVCMPEQUHCC 946 AVCMPEQUW 947 AVCMPEQUWCC 948 AVCMPEQUD 949 AVCMPEQUDCC 950 AVCMPGT 951 AVCMPGTUB 952 AVCMPGTUBCC 953 AVCMPGTUH 954 AVCMPGTUHCC 955 AVCMPGTUW 956 AVCMPGTUWCC 957 AVCMPGTUD 958 AVCMPGTUDCC 959 AVCMPGTSB 960 AVCMPGTSBCC 961 AVCMPGTSH 962 AVCMPGTSHCC 963 AVCMPGTSW 964 AVCMPGTSWCC 965 AVCMPGTSD 966 AVCMPGTSDCC 967 AVCMPNEZB 968 AVCMPNEZBCC 969 AVCMPNEB 970 AVCMPNEBCC 971 AVCMPNEH 972 AVCMPNEHCC 973 AVCMPNEW 974 AVCMPNEWCC 975 AVPERM 976 AVPERMXOR 977 AVPERMR 978 AVBPERMQ 979 AVBPERMD 980 AVSEL 981 AVSPLTB 982 AVSPLTH 983 AVSPLTW 984 AVSPLTISB 985 AVSPLTISH 986 AVSPLTISW 987 AVCIPH 988 AVCIPHER 989 AVCIPHERLAST 990 AVNCIPH 991 AVNCIPHER 992 AVNCIPHERLAST 993 AVSBOX 994 AVSHASIGMA 995 AVSHASIGMAW 996 AVSHASIGMAD 997 AVMRGEW 998 AVMRGOW 999 1000 /* VSX */ 1001 ALXV 1002 ALXVL 1003 ALXVLL 1004 ALXVD2X 1005 ALXVW4X 1006 ALXVH8X 1007 ALXVB16X 1008 ALXVX 1009 ALXVDSX 1010 ASTXV 1011 ASTXVL 1012 ASTXVLL 1013 ASTXVD2X 1014 ASTXVW4X 1015 ASTXVH8X 1016 ASTXVB16X 1017 ASTXVX 1018 ALXSDX 1019 ASTXSDX 1020 ALXSIWAX 1021 ALXSIWZX 1022 ASTXSIWX 1023 AMFVSRD 1024 AMFFPRD 1025 AMFVRD 1026 AMFVSRWZ 1027 AMFVSRLD 1028 AMTVSRD 1029 AMTFPRD 1030 AMTVRD 1031 AMTVSRWA 1032 AMTVSRWZ 1033 AMTVSRDD 1034 AMTVSRWS 1035 AXXLAND 1036 AXXLANDC 1037 AXXLEQV 1038 AXXLNAND 1039 AXXLOR 1040 AXXLORC 1041 AXXLNOR 1042 AXXLORQ 1043 AXXLXOR 1044 AXXSEL 1045 AXXMRGHW 1046 AXXMRGLW 1047 AXXSPLTW 1048 AXXSPLTIB 1049 AXXPERM 1050 AXXPERMDI 1051 AXXSLDWI 1052 AXXBRQ 1053 AXXBRD 1054 AXXBRW 1055 AXXBRH 1056 AXSCVDPSP 1057 AXSCVSPDP 1058 AXSCVDPSPN 1059 AXSCVSPDPN 1060 AXVCVDPSP 1061 AXVCVSPDP 1062 AXSCVDPSXDS 1063 AXSCVDPSXWS 1064 AXSCVDPUXDS 1065 AXSCVDPUXWS 1066 AXSCVSXDDP 1067 AXSCVUXDDP 1068 AXSCVSXDSP 1069 AXSCVUXDSP 1070 AXVCVDPSXDS 1071 AXVCVDPSXWS 1072 AXVCVDPUXDS 1073 AXVCVDPUXWS 1074 AXVCVSPSXDS 1075 AXVCVSPSXWS 1076 AXVCVSPUXDS 1077 AXVCVSPUXWS 1078 AXVCVSXDDP 1079 AXVCVSXWDP 1080 AXVCVUXDDP 1081 AXVCVUXWDP 1082 AXVCVSXDSP 1083 AXVCVSXWSP 1084 AXVCVUXDSP 1085 AXVCVUXWSP 1086 ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map. 1087 1088 // aliases 1089 ABR = obj.AJMP 1090 ABL = obj.ACALL 1091 ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table. 1092 )