github.com/bir3/gocompiler@v0.3.205/src/cmd/internal/obj/riscv/cpu.go (about) 1 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 2 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 3 // Portions Copyright © 1997-1999 Vita Nuova Limited 4 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 5 // Portions Copyright © 2004,2006 Bruce Ellis 6 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 7 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 8 // Portions Copyright © 2009 The Go Authors. All rights reserved. 9 // Portions Copyright © 2019 The Go Authors. All rights reserved. 10 // 11 // Permission is hereby granted, free of charge, to any person obtaining a copy 12 // of this software and associated documentation files (the "Software"), to deal 13 // in the Software without restriction, including without limitation the rights 14 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 // copies of the Software, and to permit persons to whom the Software is 16 // furnished to do so, subject to the following conditions: 17 // 18 // The above copyright notice and this permission notice shall be included in 19 // all copies or substantial portions of the Software. 20 // 21 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 24 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 // THE SOFTWARE. 28 29 package riscv 30 31 import "github.com/bir3/gocompiler/src/cmd/internal/obj" 32 33 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv 34 35 const ( 36 // Base register numberings. 37 REG_X0 = obj.RBaseRISCV + iota 38 REG_X1 39 REG_X2 40 REG_X3 41 REG_X4 42 REG_X5 43 REG_X6 44 REG_X7 45 REG_X8 46 REG_X9 47 REG_X10 48 REG_X11 49 REG_X12 50 REG_X13 51 REG_X14 52 REG_X15 53 REG_X16 54 REG_X17 55 REG_X18 56 REG_X19 57 REG_X20 58 REG_X21 59 REG_X22 60 REG_X23 61 REG_X24 62 REG_X25 63 REG_X26 64 REG_X27 65 REG_X28 66 REG_X29 67 REG_X30 68 REG_X31 69 70 // FP register numberings. 71 REG_F0 72 REG_F1 73 REG_F2 74 REG_F3 75 REG_F4 76 REG_F5 77 REG_F6 78 REG_F7 79 REG_F8 80 REG_F9 81 REG_F10 82 REG_F11 83 REG_F12 84 REG_F13 85 REG_F14 86 REG_F15 87 REG_F16 88 REG_F17 89 REG_F18 90 REG_F19 91 REG_F20 92 REG_F21 93 REG_F22 94 REG_F23 95 REG_F24 96 REG_F25 97 REG_F26 98 REG_F27 99 REG_F28 100 REG_F29 101 REG_F30 102 REG_F31 103 104 // This marks the end of the register numbering. 105 REG_END 106 107 // General registers reassigned to ABI names. 108 REG_ZERO = REG_X0 109 REG_RA = REG_X1 // aka REG_LR 110 REG_SP = REG_X2 111 REG_GP = REG_X3 // aka REG_SB 112 REG_TP = REG_X4 113 REG_T0 = REG_X5 114 REG_T1 = REG_X6 115 REG_T2 = REG_X7 116 REG_S0 = REG_X8 117 REG_S1 = REG_X9 118 REG_A0 = REG_X10 119 REG_A1 = REG_X11 120 REG_A2 = REG_X12 121 REG_A3 = REG_X13 122 REG_A4 = REG_X14 123 REG_A5 = REG_X15 124 REG_A6 = REG_X16 125 REG_A7 = REG_X17 126 REG_S2 = REG_X18 127 REG_S3 = REG_X19 128 REG_S4 = REG_X20 129 REG_S5 = REG_X21 130 REG_S6 = REG_X22 131 REG_S7 = REG_X23 132 REG_S8 = REG_X24 133 REG_S9 = REG_X25 134 REG_S10 = REG_X26 // aka REG_CTXT 135 REG_S11 = REG_X27 // aka REG_G 136 REG_T3 = REG_X28 137 REG_T4 = REG_X29 138 REG_T5 = REG_X30 139 REG_T6 = REG_X31 // aka REG_TMP 140 141 // Go runtime register names. 142 REG_CTXT = REG_S10 // Context for closures. 143 REG_G = REG_S11 // G pointer. 144 REG_LR = REG_RA // Link register. 145 REG_TMP = REG_T6 // Reserved for assembler use. 146 147 // ABI names for floating point registers. 148 REG_FT0 = REG_F0 149 REG_FT1 = REG_F1 150 REG_FT2 = REG_F2 151 REG_FT3 = REG_F3 152 REG_FT4 = REG_F4 153 REG_FT5 = REG_F5 154 REG_FT6 = REG_F6 155 REG_FT7 = REG_F7 156 REG_FS0 = REG_F8 157 REG_FS1 = REG_F9 158 REG_FA0 = REG_F10 159 REG_FA1 = REG_F11 160 REG_FA2 = REG_F12 161 REG_FA3 = REG_F13 162 REG_FA4 = REG_F14 163 REG_FA5 = REG_F15 164 REG_FA6 = REG_F16 165 REG_FA7 = REG_F17 166 REG_FS2 = REG_F18 167 REG_FS3 = REG_F19 168 REG_FS4 = REG_F20 169 REG_FS5 = REG_F21 170 REG_FS6 = REG_F22 171 REG_FS7 = REG_F23 172 REG_FS8 = REG_F24 173 REG_FS9 = REG_F25 174 REG_FS10 = REG_F26 175 REG_FS11 = REG_F27 176 REG_FT8 = REG_F28 177 REG_FT9 = REG_F29 178 REG_FT10 = REG_F30 179 REG_FT11 = REG_F31 180 181 // Names generated by the SSA compiler. 182 REGSP = REG_SP 183 REGG = REG_G 184 ) 185 186 // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers 187 var RISCV64DWARFRegisters = map[int16]int16{ 188 // Integer Registers. 189 REG_X0: 0, 190 REG_X1: 1, 191 REG_X2: 2, 192 REG_X3: 3, 193 REG_X4: 4, 194 REG_X5: 5, 195 REG_X6: 6, 196 REG_X7: 7, 197 REG_X8: 8, 198 REG_X9: 9, 199 REG_X10: 10, 200 REG_X11: 11, 201 REG_X12: 12, 202 REG_X13: 13, 203 REG_X14: 14, 204 REG_X15: 15, 205 REG_X16: 16, 206 REG_X17: 17, 207 REG_X18: 18, 208 REG_X19: 19, 209 REG_X20: 20, 210 REG_X21: 21, 211 REG_X22: 22, 212 REG_X23: 23, 213 REG_X24: 24, 214 REG_X25: 25, 215 REG_X26: 26, 216 REG_X27: 27, 217 REG_X28: 28, 218 REG_X29: 29, 219 REG_X30: 30, 220 REG_X31: 31, 221 222 // Floating-Point Registers. 223 REG_F0: 32, 224 REG_F1: 33, 225 REG_F2: 34, 226 REG_F3: 35, 227 REG_F4: 36, 228 REG_F5: 37, 229 REG_F6: 38, 230 REG_F7: 39, 231 REG_F8: 40, 232 REG_F9: 41, 233 REG_F10: 42, 234 REG_F11: 43, 235 REG_F12: 44, 236 REG_F13: 45, 237 REG_F14: 46, 238 REG_F15: 47, 239 REG_F16: 48, 240 REG_F17: 49, 241 REG_F18: 50, 242 REG_F19: 51, 243 REG_F20: 52, 244 REG_F21: 53, 245 REG_F22: 54, 246 REG_F23: 55, 247 REG_F24: 56, 248 REG_F25: 57, 249 REG_F26: 58, 250 REG_F27: 59, 251 REG_F28: 60, 252 REG_F29: 61, 253 REG_F30: 62, 254 REG_F31: 63, 255 } 256 257 // Prog.Mark flags. 258 const ( 259 // USES_REG_TMP indicates that a machine instruction generated from the 260 // corresponding *obj.Prog uses the temporary register. 261 USES_REG_TMP = 1 << iota 262 263 // NEED_CALL_RELOC is set on JAL instructions to indicate that a 264 // R_RISCV_CALL relocation is needed. 265 NEED_CALL_RELOC 266 267 // NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that 268 // it is the first instruction in an AUIPC + I-type pair that needs a 269 // R_RISCV_PCREL_ITYPE relocation. 270 NEED_PCREL_ITYPE_RELOC 271 272 // NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that 273 // it is the first instruction in an AUIPC + S-type pair that needs a 274 // R_RISCV_PCREL_STYPE relocation. 275 NEED_PCREL_STYPE_RELOC 276 ) 277 278 // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files 279 // at https://github.com/riscv/riscv-opcodes. 280 // 281 // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. 282 // 283 // See also "The RISC-V Instruction Set Manual" at https://riscv.org/specifications/. 284 // 285 // If you modify this table, you MUST run 'go generate' to regenerate anames.go! 286 const ( 287 // Unprivileged ISA (Document Version 20190608-Base-Ratified) 288 289 // 2.4: Integer Computational Instructions 290 AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota 291 ASLTI 292 ASLTIU 293 AANDI 294 AORI 295 AXORI 296 ASLLI 297 ASRLI 298 ASRAI 299 ALUI 300 AAUIPC 301 AADD 302 ASLT 303 ASLTU 304 AAND 305 AOR 306 AXOR 307 ASLL 308 ASRL 309 ASUB 310 ASRA 311 312 // The SLL/SRL/SRA instructions differ slightly between RV32 and RV64, 313 // hence there are pseudo-opcodes for the RV32 specific versions. 314 ASLLIRV32 315 ASRLIRV32 316 ASRAIRV32 317 318 // 2.5: Control Transfer Instructions 319 AJAL 320 AJALR 321 ABEQ 322 ABNE 323 ABLT 324 ABLTU 325 ABGE 326 ABGEU 327 328 // 2.6: Load and Store Instructions 329 ALW 330 ALWU 331 ALH 332 ALHU 333 ALB 334 ALBU 335 ASW 336 ASH 337 ASB 338 339 // 2.7: Memory Ordering Instructions 340 AFENCE 341 AFENCEI 342 AFENCETSO 343 344 // 5.2: Integer Computational Instructions (RV64I) 345 AADDIW 346 ASLLIW 347 ASRLIW 348 ASRAIW 349 AADDW 350 ASLLW 351 ASRLW 352 ASUBW 353 ASRAW 354 355 // 5.3: Load and Store Instructions (RV64I) 356 ALD 357 ASD 358 359 // 7.1: Multiplication Operations 360 AMUL 361 AMULH 362 AMULHU 363 AMULHSU 364 AMULW 365 ADIV 366 ADIVU 367 AREM 368 AREMU 369 ADIVW 370 ADIVUW 371 AREMW 372 AREMUW 373 374 // 8.2: Load-Reserved/Store-Conditional Instructions 375 ALRD 376 ASCD 377 ALRW 378 ASCW 379 380 // 8.3: Atomic Memory Operations 381 AAMOSWAPD 382 AAMOADDD 383 AAMOANDD 384 AAMOORD 385 AAMOXORD 386 AAMOMAXD 387 AAMOMAXUD 388 AAMOMIND 389 AAMOMINUD 390 AAMOSWAPW 391 AAMOADDW 392 AAMOANDW 393 AAMOORW 394 AAMOXORW 395 AAMOMAXW 396 AAMOMAXUW 397 AAMOMINW 398 AAMOMINUW 399 400 // 10.1: Base Counters and Timers 401 ARDCYCLE 402 ARDCYCLEH 403 ARDTIME 404 ARDTIMEH 405 ARDINSTRET 406 ARDINSTRETH 407 408 // 11.2: Floating-Point Control and Status Register 409 AFRCSR 410 AFSCSR 411 AFRRM 412 AFSRM 413 AFRFLAGS 414 AFSFLAGS 415 AFSRMI 416 AFSFLAGSI 417 418 // 11.5: Single-Precision Load and Store Instructions 419 AFLW 420 AFSW 421 422 // 11.6: Single-Precision Floating-Point Computational Instructions 423 AFADDS 424 AFSUBS 425 AFMULS 426 AFDIVS 427 AFMINS 428 AFMAXS 429 AFSQRTS 430 AFMADDS 431 AFMSUBS 432 AFNMADDS 433 AFNMSUBS 434 435 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions 436 AFCVTWS 437 AFCVTLS 438 AFCVTSW 439 AFCVTSL 440 AFCVTWUS 441 AFCVTLUS 442 AFCVTSWU 443 AFCVTSLU 444 AFSGNJS 445 AFSGNJNS 446 AFSGNJXS 447 AFMVXS 448 AFMVSX 449 AFMVXW 450 AFMVWX 451 452 // 11.8: Single-Precision Floating-Point Compare Instructions 453 AFEQS 454 AFLTS 455 AFLES 456 457 // 11.9: Single-Precision Floating-Point Classify Instruction 458 AFCLASSS 459 460 // 12.3: Double-Precision Load and Store Instructions 461 AFLD 462 AFSD 463 464 // 12.4: Double-Precision Floating-Point Computational Instructions 465 AFADDD 466 AFSUBD 467 AFMULD 468 AFDIVD 469 AFMIND 470 AFMAXD 471 AFSQRTD 472 AFMADDD 473 AFMSUBD 474 AFNMADDD 475 AFNMSUBD 476 477 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions 478 AFCVTWD 479 AFCVTLD 480 AFCVTDW 481 AFCVTDL 482 AFCVTWUD 483 AFCVTLUD 484 AFCVTDWU 485 AFCVTDLU 486 AFCVTSD 487 AFCVTDS 488 AFSGNJD 489 AFSGNJND 490 AFSGNJXD 491 AFMVXD 492 AFMVDX 493 494 // 12.6: Double-Precision Floating-Point Compare Instructions 495 AFEQD 496 AFLTD 497 AFLED 498 499 // 12.7: Double-Precision Floating-Point Classify Instruction 500 AFCLASSD 501 502 // 13.1 Quad-Precision Load and Store Instructions 503 AFLQ 504 AFSQ 505 506 // 13.2: Quad-Precision Computational Instructions 507 AFADDQ 508 AFSUBQ 509 AFMULQ 510 AFDIVQ 511 AFMINQ 512 AFMAXQ 513 AFSQRTQ 514 AFMADDQ 515 AFMSUBQ 516 AFNMADDQ 517 AFNMSUBQ 518 519 // 13.3 Quad-Precision Convert and Move Instructions 520 AFCVTWQ 521 AFCVTLQ 522 AFCVTSQ 523 AFCVTDQ 524 AFCVTQW 525 AFCVTQL 526 AFCVTQS 527 AFCVTQD 528 AFCVTWUQ 529 AFCVTLUQ 530 AFCVTQWU 531 AFCVTQLU 532 AFSGNJQ 533 AFSGNJNQ 534 AFSGNJXQ 535 AFMVXQ 536 AFMVQX 537 538 // 13.4 Quad-Precision Floating-Point Compare Instructions 539 AFEQQ 540 AFLEQ 541 AFLTQ 542 543 // 13.5 Quad-Precision Floating-Point Classify Instruction 544 AFCLASSQ 545 546 // Privileged ISA (Version 20190608-Priv-MSU-Ratified) 547 548 // 3.1.9: Instructions to Access CSRs 549 ACSRRW 550 ACSRRS 551 ACSRRC 552 ACSRRWI 553 ACSRRSI 554 ACSRRCI 555 556 // 3.2.1: Environment Call and Breakpoint 557 AECALL 558 ASCALL 559 AEBREAK 560 ASBREAK 561 562 // 3.2.2: Trap-Return Instructions 563 AMRET 564 ASRET 565 AURET 566 ADRET 567 568 // 3.2.3: Wait for Interrupt 569 AWFI 570 571 // 4.2.1: Supervisor Memory-Management Fence Instruction 572 ASFENCEVMA 573 574 // Hypervisor Memory-Management Instructions 575 AHFENCEGVMA 576 AHFENCEVVMA 577 578 // The escape hatch. Inserts a single 32-bit word. 579 AWORD 580 581 // Pseudo-instructions. These get translated by the assembler into other 582 // instructions, based on their operands. 583 ABEQZ 584 ABGEZ 585 ABGT 586 ABGTU 587 ABGTZ 588 ABLE 589 ABLEU 590 ABLEZ 591 ABLTZ 592 ABNEZ 593 AFABSD 594 AFABSS 595 AFNEGD 596 AFNEGS 597 AFNED 598 AFNES 599 AMOV 600 AMOVB 601 AMOVBU 602 AMOVF 603 AMOVD 604 AMOVH 605 AMOVHU 606 AMOVW 607 AMOVWU 608 ANEG 609 ANEGW 610 ANOT 611 ASEQZ 612 ASNEZ 613 614 // End marker 615 ALAST 616 ) 617 618 // All unary instructions which write to their arguments (as opposed to reading 619 // from them) go here. The assembly parser uses this information to populate 620 // its AST in a semantically reasonable way. 621 // 622 // Any instructions not listed here are assumed to either be non-unary or to read 623 // from its argument. 624 var unaryDst = map[obj.As]bool{ 625 ARDCYCLE: true, 626 ARDCYCLEH: true, 627 ARDTIME: true, 628 ARDTIMEH: true, 629 ARDINSTRET: true, 630 ARDINSTRETH: true, 631 } 632 633 // Instruction encoding masks. 634 const ( 635 // JTypeImmMask is a mask including only the immediate portion of 636 // J-type instructions. 637 JTypeImmMask = 0xfffff000 638 639 // ITypeImmMask is a mask including only the immediate portion of 640 // I-type instructions. 641 ITypeImmMask = 0xfff00000 642 643 // STypeImmMask is a mask including only the immediate portion of 644 // S-type instructions. 645 STypeImmMask = 0xfe000f80 646 647 // UTypeImmMask is a mask including only the immediate portion of 648 // U-type instructions. 649 UTypeImmMask = 0xfffff000 650 )