github.com/bir3/gocompiler@v0.9.2202/src/cmd/compile/internal/ssa/_gen/ARM64.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 (Add(Ptr|64|32|16|8) ...) => (ADD ...) 6 (Add(32|64)F ...) => (FADD(S|D) ...) 7 8 (Sub(Ptr|64|32|16|8) ...) => (SUB ...) 9 (Sub(32|64)F ...) => (FSUB(S|D) ...) 10 11 (Mul64 ...) => (MUL ...) 12 (Mul(32|16|8) ...) => (MULW ...) 13 (Mul(32|64)F ...) => (FMUL(S|D) ...) 14 15 (Hmul64 ...) => (MULH ...) 16 (Hmul64u ...) => (UMULH ...) 17 (Hmul32 x y) => (SRAconst (MULL <typ.Int64> x y) [32]) 18 (Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32]) 19 (Select0 (Mul64uhilo x y)) => (UMULH x y) 20 (Select1 (Mul64uhilo x y)) => (MUL x y) 21 22 (Div64 [false] x y) => (DIV x y) 23 (Div32 [false] x y) => (DIVW x y) 24 (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y)) 25 (Div16u x y) => (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y)) 26 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y)) 27 (Div8u x y) => (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y)) 28 (Div64u ...) => (UDIV ...) 29 (Div32u ...) => (UDIVW ...) 30 (Div32F ...) => (FDIVS ...) 31 (Div64F ...) => (FDIVD ...) 32 33 (Mod64 x y) => (MOD x y) 34 (Mod32 x y) => (MODW x y) 35 (Mod64u ...) => (UMOD ...) 36 (Mod32u ...) => (UMODW ...) 37 (Mod(16|8) x y) => (MODW (SignExt(16|8)to32 x) (SignExt(16|8)to32 y)) 38 (Mod(16|8)u x y) => (UMODW (ZeroExt(16|8)to32 x) (ZeroExt(16|8)to32 y)) 39 40 // (x + y) / 2 with x>=y => (x - y) / 2 + y 41 (Avg64u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y) 42 43 (And(64|32|16|8) ...) => (AND ...) 44 (Or(64|32|16|8) ...) => (OR ...) 45 (Xor(64|32|16|8) ...) => (XOR ...) 46 47 // unary ops 48 (Neg(64|32|16|8) ...) => (NEG ...) 49 (Neg(32|64)F ...) => (FNEG(S|D) ...) 50 (Com(64|32|16|8) ...) => (MVN ...) 51 52 // math package intrinsics 53 (Abs ...) => (FABSD ...) 54 (Sqrt ...) => (FSQRTD ...) 55 (Ceil ...) => (FRINTPD ...) 56 (Floor ...) => (FRINTMD ...) 57 (Round ...) => (FRINTAD ...) 58 (RoundToEven ...) => (FRINTND ...) 59 (Trunc ...) => (FRINTZD ...) 60 (FMA x y z) => (FMADDD z x y) 61 62 (Sqrt32 ...) => (FSQRTS ...) 63 64 (Min(64|32)F ...) => (FMIN(D|S) ...) 65 (Max(64|32)F ...) => (FMAX(D|S) ...) 66 67 // lowering rotates 68 // we do rotate detection in generic rules, if the following rules need to be changed, check generic rules first. 69 (RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7]))) 70 (RotateLeft8 <t> x y) => (OR <t> (SLL <t> x (ANDconst <typ.Int64> [7] y)) (SRL <t> (ZeroExt8to64 x) (ANDconst <typ.Int64> [7] (NEG <typ.Int64> y)))) 71 (RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15]))) 72 (RotateLeft16 <t> x y) => (RORW <t> (ORshiftLL <typ.UInt32> (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG <typ.Int64> y)) 73 (RotateLeft32 x y) => (RORW x (NEG <y.Type> y)) 74 (RotateLeft64 x y) => (ROR x (NEG <y.Type> y)) 75 76 (Ctz(64|32|16|8)NonZero ...) => (Ctz(64|32|32|32) ...) 77 78 (Ctz64 <t> x) => (CLZ (RBIT <t> x)) 79 (Ctz32 <t> x) => (CLZW (RBITW <t> x)) 80 (Ctz16 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x10000] x))) 81 (Ctz8 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x100] x))) 82 83 (PopCount64 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> x)))) 84 (PopCount32 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt32to64 x))))) 85 (PopCount16 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt16to64 x))))) 86 87 // Load args directly into the register class where it will be used. 88 (FMOVDgpfp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym}) 89 (FMOVDfpgp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym}) 90 91 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set. 92 (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) => (FMOVDstore [off] {sym} ptr val mem) 93 (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) => (MOVDstore [off] {sym} ptr val mem) 94 (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) => (FMOVSstore [off] {sym} ptr val mem) 95 (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem) 96 97 // float <=> int register moves, with no conversion. 98 // These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}. 99 (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) => (FMOVDfpgp val) 100 (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (FMOVDgpfp val) 101 (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) => (FMOVSfpgp val) 102 (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (FMOVSgpfp val) 103 104 (BitLen64 x) => (SUB (MOVDconst [64]) (CLZ <typ.Int> x)) 105 (BitLen32 x) => (SUB (MOVDconst [32]) (CLZW <typ.Int> x)) 106 107 (Bswap64 ...) => (REV ...) 108 (Bswap32 ...) => (REVW ...) 109 (Bswap16 ...) => (REV16W ...) 110 111 (BitRev64 ...) => (RBIT ...) 112 (BitRev32 ...) => (RBITW ...) 113 (BitRev16 x) => (SRLconst [48] (RBIT <typ.UInt64> x)) 114 (BitRev8 x) => (SRLconst [56] (RBIT <typ.UInt64> x)) 115 116 // In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into 117 // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or 118 // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant. 119 // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass. 120 (UMOD <typ.UInt64> x y) => (MSUB <typ.UInt64> x y (UDIV <typ.UInt64> x y)) 121 (UMODW <typ.UInt32> x y) => (MSUBW <typ.UInt32> x y (UDIVW <typ.UInt32> x y)) 122 123 // 64-bit addition with carry. 124 (Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c)))) 125 (Select1 (Add64carry x y c)) => (ADCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c))))) 126 127 // 64-bit subtraction with borrowing. 128 (Select0 (Sub64borrow x y bo)) => (Select0 <typ.UInt64> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo)))) 129 (Select1 (Sub64borrow x y bo)) => (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo)))))) 130 131 // boolean ops -- booleans are represented with 0=false, 1=true 132 (AndB ...) => (AND ...) 133 (OrB ...) => (OR ...) 134 (EqB x y) => (XOR (MOVDconst [1]) (XOR <typ.Bool> x y)) 135 (NeqB ...) => (XOR ...) 136 (Not x) => (XOR (MOVDconst [1]) x) 137 138 // shifts 139 // hardware instruction uses only the low 6 bits of the shift 140 // we compare to 64 to ensure Go semantics for large shifts 141 // Rules about rotates with non-const shift are based on the following rules, 142 // if the following rules change, please also modify the rules based on them. 143 144 // check shiftIsBounded first, if shift value is proved to be valid then we 145 // can do the shift directly. 146 // left shift 147 (Lsh(64|32|16|8)x64 <t> x y) && shiftIsBounded(v) => (SLL <t> x y) 148 (Lsh(64|32|16|8)x32 <t> x y) && shiftIsBounded(v) => (SLL <t> x y) 149 (Lsh(64|32|16|8)x16 <t> x y) && shiftIsBounded(v) => (SLL <t> x y) 150 (Lsh(64|32|16|8)x8 <t> x y) && shiftIsBounded(v) => (SLL <t> x y) 151 152 // signed right shift 153 (Rsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> x y) 154 (Rsh32x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt32to64 x) y) 155 (Rsh16x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt16to64 x) y) 156 (Rsh8x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt8to64 x) y) 157 158 // unsigned right shift 159 (Rsh64Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> x y) 160 (Rsh32Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt32to64 x) y) 161 (Rsh16Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt16to64 x) y) 162 (Rsh8Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> (ZeroExt8to64 x) y) 163 164 // shift value may be out of range, use CMP + CSEL instead 165 (Lsh64x64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y)) 166 (Lsh64x(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 167 168 (Lsh32x64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y)) 169 (Lsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 170 171 (Lsh16x64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y)) 172 (Lsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 173 174 (Lsh8x64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y)) 175 (Lsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 176 177 (Rsh64Ux64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPconst [64] y)) 178 (Rsh64Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 179 180 (Rsh32Ux64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt32to64 x) y) (Const64 <t> [0]) (CMPconst [64] y)) 181 (Rsh32Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt32to64 x) y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 182 183 (Rsh16Ux64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt16to64 x) y) (Const64 <t> [0]) (CMPconst [64] y)) 184 (Rsh16Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt16to64 x) y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 185 186 (Rsh8Ux64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt8to64 x) y) (Const64 <t> [0]) (CMPconst [64] y)) 187 (Rsh8Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> (ZeroExt8to64 x) y) (Const64 <t> [0]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y))) 188 189 (Rsh64x64 x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y))) 190 (Rsh64x(32|16|8) x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) 191 192 (Rsh32x64 x y) && !shiftIsBounded(v) => (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y))) 193 (Rsh32x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt32to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) 194 195 (Rsh16x64 x y) && !shiftIsBounded(v) => (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y))) 196 (Rsh16x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt16to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) 197 198 (Rsh8x64 x y) && !shiftIsBounded(v) => (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y))) 199 (Rsh8x(32|16|8) x y) && !shiftIsBounded(v) => (SRA (SignExt8to64 x) (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] ((ZeroExt32to64|ZeroExt16to64|ZeroExt8to64) y)))) 200 201 // constants 202 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)]) 203 (Const(32|64)F [val]) => (FMOV(S|D)const [float64(val)]) 204 (ConstNil) => (MOVDconst [0]) 205 (ConstBool [t]) => (MOVDconst [b2i(t)]) 206 207 (Slicemask <t> x) => (SRAconst (NEG <t> x) [63]) 208 209 // truncations 210 // Because we ignore high parts of registers, truncates are just copies. 211 (Trunc16to8 ...) => (Copy ...) 212 (Trunc32to8 ...) => (Copy ...) 213 (Trunc32to16 ...) => (Copy ...) 214 (Trunc64to8 ...) => (Copy ...) 215 (Trunc64to16 ...) => (Copy ...) 216 (Trunc64to32 ...) => (Copy ...) 217 218 // Zero-/Sign-extensions 219 (ZeroExt8to16 ...) => (MOVBUreg ...) 220 (ZeroExt8to32 ...) => (MOVBUreg ...) 221 (ZeroExt16to32 ...) => (MOVHUreg ...) 222 (ZeroExt8to64 ...) => (MOVBUreg ...) 223 (ZeroExt16to64 ...) => (MOVHUreg ...) 224 (ZeroExt32to64 ...) => (MOVWUreg ...) 225 226 (SignExt8to16 ...) => (MOVBreg ...) 227 (SignExt8to32 ...) => (MOVBreg ...) 228 (SignExt16to32 ...) => (MOVHreg ...) 229 (SignExt8to64 ...) => (MOVBreg ...) 230 (SignExt16to64 ...) => (MOVHreg ...) 231 (SignExt32to64 ...) => (MOVWreg ...) 232 233 // float <=> int conversion 234 (Cvt32to32F ...) => (SCVTFWS ...) 235 (Cvt32to64F ...) => (SCVTFWD ...) 236 (Cvt64to32F ...) => (SCVTFS ...) 237 (Cvt64to64F ...) => (SCVTFD ...) 238 (Cvt32Uto32F ...) => (UCVTFWS ...) 239 (Cvt32Uto64F ...) => (UCVTFWD ...) 240 (Cvt64Uto32F ...) => (UCVTFS ...) 241 (Cvt64Uto64F ...) => (UCVTFD ...) 242 (Cvt32Fto32 ...) => (FCVTZSSW ...) 243 (Cvt64Fto32 ...) => (FCVTZSDW ...) 244 (Cvt32Fto64 ...) => (FCVTZSS ...) 245 (Cvt64Fto64 ...) => (FCVTZSD ...) 246 (Cvt32Fto32U ...) => (FCVTZUSW ...) 247 (Cvt64Fto32U ...) => (FCVTZUDW ...) 248 (Cvt32Fto64U ...) => (FCVTZUS ...) 249 (Cvt64Fto64U ...) => (FCVTZUD ...) 250 (Cvt32Fto64F ...) => (FCVTSD ...) 251 (Cvt64Fto32F ...) => (FCVTDS ...) 252 253 (CvtBoolToUint8 ...) => (Copy ...) 254 255 (Round32F ...) => (LoweredRound32F ...) 256 (Round64F ...) => (LoweredRound64F ...) 257 258 // comparisons 259 (Eq8 x y) => (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 260 (Eq16 x y) => (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 261 (Eq32 x y) => (Equal (CMPW x y)) 262 (Eq64 x y) => (Equal (CMP x y)) 263 (EqPtr x y) => (Equal (CMP x y)) 264 (Eq32F x y) => (Equal (FCMPS x y)) 265 (Eq64F x y) => (Equal (FCMPD x y)) 266 267 (Neq8 x y) => (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 268 (Neq16 x y) => (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 269 (Neq32 x y) => (NotEqual (CMPW x y)) 270 (Neq64 x y) => (NotEqual (CMP x y)) 271 (NeqPtr x y) => (NotEqual (CMP x y)) 272 (Neq(32|64)F x y) => (NotEqual (FCMP(S|D) x y)) 273 274 (Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y))) 275 (Less32 x y) => (LessThan (CMPW x y)) 276 (Less64 x y) => (LessThan (CMP x y)) 277 278 // Set condition flags for floating-point comparisons "x < y" 279 // and "x <= y". Because if either or both of the operands are 280 // NaNs, all three of (x < y), (x == y) and (x > y) are false, 281 // and ARM Manual says FCMP instruction sets PSTATE.<N,Z,C,V> 282 // of this case to (0, 0, 1, 1). 283 (Less32F x y) => (LessThanF (FCMPS x y)) 284 (Less64F x y) => (LessThanF (FCMPD x y)) 285 286 // For an unsigned integer x, the following rules are useful when combining branch 287 // 0 < x => x != 0 288 // x <= 0 => x == 0 289 // x < 1 => x == 0 290 // 1 <= x => x != 0 291 (Less(8U|16U|32U|64U) zero:(MOVDconst [0]) x) => (Neq(8|16|32|64) zero x) 292 (Leq(8U|16U|32U|64U) x zero:(MOVDconst [0])) => (Eq(8|16|32|64) x zero) 293 (Less(8U|16U|32U|64U) x (MOVDconst [1])) => (Eq(8|16|32|64) x (MOVDconst [0])) 294 (Leq(8U|16U|32U|64U) (MOVDconst [1]) x) => (Neq(8|16|32|64) (MOVDconst [0]) x) 295 296 (Less8U x y) => (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 297 (Less16U x y) => (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 298 (Less32U x y) => (LessThanU (CMPW x y)) 299 (Less64U x y) => (LessThanU (CMP x y)) 300 301 (Leq8 x y) => (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) 302 (Leq16 x y) => (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) 303 (Leq32 x y) => (LessEqual (CMPW x y)) 304 (Leq64 x y) => (LessEqual (CMP x y)) 305 306 // Refer to the comments for op Less64F above. 307 (Leq32F x y) => (LessEqualF (FCMPS x y)) 308 (Leq64F x y) => (LessEqualF (FCMPD x y)) 309 310 (Leq8U x y) => (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 311 (Leq16U x y) => (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 312 (Leq32U x y) => (LessEqualU (CMPW x y)) 313 (Leq64U x y) => (LessEqualU (CMP x y)) 314 315 // Optimize comparison between a floating-point value and 0.0 with "FCMP $(0.0), Fn" 316 (FCMPS x (FMOVSconst [0])) => (FCMPS0 x) 317 (FCMPS (FMOVSconst [0]) x) => (InvertFlags (FCMPS0 x)) 318 (FCMPD x (FMOVDconst [0])) => (FCMPD0 x) 319 (FCMPD (FMOVDconst [0]) x) => (InvertFlags (FCMPD0 x)) 320 321 // CSEL needs a flag-generating argument. Synthesize a TSTW if necessary. 322 (CondSelect x y boolval) && flagArg(boolval) != nil => (CSEL [boolval.Op] x y flagArg(boolval)) 323 (CondSelect x y boolval) && flagArg(boolval) == nil => (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval)) 324 325 (OffPtr [off] ptr:(SP)) && is32Bit(off) => (MOVDaddr [int32(off)] ptr) 326 (OffPtr [off] ptr) => (ADDconst [off] ptr) 327 328 (Addr {sym} base) => (MOVDaddr {sym} base) 329 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem)) 330 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base) 331 332 // loads 333 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem) 334 (Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem) 335 (Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem) 336 (Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem) 337 (Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem) 338 (Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem) 339 (Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem) 340 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem) 341 (Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem) 342 (Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem) 343 344 // stores 345 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem) 346 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem) 347 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem) 348 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem) 349 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem) 350 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem) 351 352 // zeroing 353 (Zero [0] _ mem) => mem 354 (Zero [1] ptr mem) => (MOVBstore ptr (MOVDconst [0]) mem) 355 (Zero [2] ptr mem) => (MOVHstore ptr (MOVDconst [0]) mem) 356 (Zero [4] ptr mem) => (MOVWstore ptr (MOVDconst [0]) mem) 357 (Zero [3] ptr mem) => 358 (MOVBstore [2] ptr (MOVDconst [0]) 359 (MOVHstore ptr (MOVDconst [0]) mem)) 360 (Zero [5] ptr mem) => 361 (MOVBstore [4] ptr (MOVDconst [0]) 362 (MOVWstore ptr (MOVDconst [0]) mem)) 363 (Zero [6] ptr mem) => 364 (MOVHstore [4] ptr (MOVDconst [0]) 365 (MOVWstore ptr (MOVDconst [0]) mem)) 366 (Zero [7] ptr mem) => 367 (MOVWstore [3] ptr (MOVDconst [0]) 368 (MOVWstore ptr (MOVDconst [0]) mem)) 369 (Zero [8] ptr mem) => (MOVDstore ptr (MOVDconst [0]) mem) 370 (Zero [9] ptr mem) => 371 (MOVBstore [8] ptr (MOVDconst [0]) 372 (MOVDstore ptr (MOVDconst [0]) mem)) 373 (Zero [10] ptr mem) => 374 (MOVHstore [8] ptr (MOVDconst [0]) 375 (MOVDstore ptr (MOVDconst [0]) mem)) 376 (Zero [11] ptr mem) => 377 (MOVDstore [3] ptr (MOVDconst [0]) 378 (MOVDstore ptr (MOVDconst [0]) mem)) 379 (Zero [12] ptr mem) => 380 (MOVWstore [8] ptr (MOVDconst [0]) 381 (MOVDstore ptr (MOVDconst [0]) mem)) 382 (Zero [13] ptr mem) => 383 (MOVDstore [5] ptr (MOVDconst [0]) 384 (MOVDstore ptr (MOVDconst [0]) mem)) 385 (Zero [14] ptr mem) => 386 (MOVDstore [6] ptr (MOVDconst [0]) 387 (MOVDstore ptr (MOVDconst [0]) mem)) 388 (Zero [15] ptr mem) => 389 (MOVDstore [7] ptr (MOVDconst [0]) 390 (MOVDstore ptr (MOVDconst [0]) mem)) 391 (Zero [16] ptr mem) => 392 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem) 393 394 (Zero [32] ptr mem) => 395 (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) 396 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)) 397 398 (Zero [48] ptr mem) => 399 (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) 400 (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) 401 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem))) 402 403 (Zero [64] ptr mem) => 404 (STP [48] ptr (MOVDconst [0]) (MOVDconst [0]) 405 (STP [32] ptr (MOVDconst [0]) (MOVDconst [0]) 406 (STP [16] ptr (MOVDconst [0]) (MOVDconst [0]) 407 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)))) 408 409 // strip off fractional word zeroing 410 (Zero [s] ptr mem) && s%16 != 0 && s%16 <= 8 && s > 16 => 411 (Zero [8] 412 (OffPtr <ptr.Type> ptr [s-8]) 413 (Zero [s-s%16] ptr mem)) 414 (Zero [s] ptr mem) && s%16 != 0 && s%16 > 8 && s > 16 => 415 (Zero [16] 416 (OffPtr <ptr.Type> ptr [s-16]) 417 (Zero [s-s%16] ptr mem)) 418 419 // medium zeroing uses a duff device 420 // 4, 16, and 64 are magic constants, see runtime/mkduff.go 421 (Zero [s] ptr mem) 422 && s%16 == 0 && s > 64 && s <= 16*64 423 && !config.noDuffDevice => 424 (DUFFZERO [4 * (64 - s/16)] ptr mem) 425 426 // large zeroing uses a loop 427 (Zero [s] ptr mem) 428 && s%16 == 0 && (s > 16*64 || config.noDuffDevice) => 429 (LoweredZero 430 ptr 431 (ADDconst <ptr.Type> [s-16] ptr) 432 mem) 433 434 // moves 435 (Move [0] _ _ mem) => mem 436 (Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem) 437 (Move [2] dst src mem) => (MOVHstore dst (MOVHUload src mem) mem) 438 (Move [3] dst src mem) => 439 (MOVBstore [2] dst (MOVBUload [2] src mem) 440 (MOVHstore dst (MOVHUload src mem) mem)) 441 (Move [4] dst src mem) => (MOVWstore dst (MOVWUload src mem) mem) 442 (Move [5] dst src mem) => 443 (MOVBstore [4] dst (MOVBUload [4] src mem) 444 (MOVWstore dst (MOVWUload src mem) mem)) 445 (Move [6] dst src mem) => 446 (MOVHstore [4] dst (MOVHUload [4] src mem) 447 (MOVWstore dst (MOVWUload src mem) mem)) 448 (Move [7] dst src mem) => 449 (MOVWstore [3] dst (MOVWUload [3] src mem) 450 (MOVWstore dst (MOVWUload src mem) mem)) 451 (Move [8] dst src mem) => (MOVDstore dst (MOVDload src mem) mem) 452 (Move [9] dst src mem) => 453 (MOVBstore [8] dst (MOVBUload [8] src mem) 454 (MOVDstore dst (MOVDload src mem) mem)) 455 (Move [10] dst src mem) => 456 (MOVHstore [8] dst (MOVHUload [8] src mem) 457 (MOVDstore dst (MOVDload src mem) mem)) 458 (Move [11] dst src mem) => 459 (MOVDstore [3] dst (MOVDload [3] src mem) 460 (MOVDstore dst (MOVDload src mem) mem)) 461 (Move [12] dst src mem) => 462 (MOVWstore [8] dst (MOVWUload [8] src mem) 463 (MOVDstore dst (MOVDload src mem) mem)) 464 (Move [13] dst src mem) => 465 (MOVDstore [5] dst (MOVDload [5] src mem) 466 (MOVDstore dst (MOVDload src mem) mem)) 467 (Move [14] dst src mem) => 468 (MOVDstore [6] dst (MOVDload [6] src mem) 469 (MOVDstore dst (MOVDload src mem) mem)) 470 (Move [15] dst src mem) => 471 (MOVDstore [7] dst (MOVDload [7] src mem) 472 (MOVDstore dst (MOVDload src mem) mem)) 473 (Move [16] dst src mem) => 474 (STP dst (Select0 <typ.UInt64> (LDP src mem)) (Select1 <typ.UInt64> (LDP src mem)) mem) 475 (Move [32] dst src mem) => 476 (STP [16] dst (Select0 <typ.UInt64> (LDP [16] src mem)) (Select1 <typ.UInt64> (LDP [16] src mem)) 477 (STP dst (Select0 <typ.UInt64> (LDP src mem)) (Select1 <typ.UInt64> (LDP src mem)) mem)) 478 (Move [48] dst src mem) => 479 (STP [32] dst (Select0 <typ.UInt64> (LDP [32] src mem)) (Select1 <typ.UInt64> (LDP [32] src mem)) 480 (STP [16] dst (Select0 <typ.UInt64> (LDP [16] src mem)) (Select1 <typ.UInt64> (LDP [16] src mem)) 481 (STP dst (Select0 <typ.UInt64> (LDP src mem)) (Select1 <typ.UInt64> (LDP src mem)) mem))) 482 (Move [64] dst src mem) => 483 (STP [48] dst (Select0 <typ.UInt64> (LDP [48] src mem)) (Select1 <typ.UInt64> (LDP [48] src mem)) 484 (STP [32] dst (Select0 <typ.UInt64> (LDP [32] src mem)) (Select1 <typ.UInt64> (LDP [32] src mem)) 485 (STP [16] dst (Select0 <typ.UInt64> (LDP [16] src mem)) (Select1 <typ.UInt64> (LDP [16] src mem)) 486 (STP dst (Select0 <typ.UInt64> (LDP src mem)) (Select1 <typ.UInt64> (LDP src mem)) mem)))) 487 488 (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i+8] ptr mem)) && x.Uses == 1 && setPos(v, x.Pos) && clobber(x) => (MOVQstorezero {s} [i] ptr mem) 489 (MOVDstorezero {s} [i] ptr x:(MOVDstorezero {s} [i-8] ptr mem)) && x.Uses == 1 && setPos(v, x.Pos) && clobber(x) => (MOVQstorezero {s} [i-8] ptr mem) 490 491 // strip off fractional word move 492 (Move [s] dst src mem) && s%16 != 0 && s%16 <= 8 && s > 16 => 493 (Move [8] 494 (OffPtr <dst.Type> dst [s-8]) 495 (OffPtr <src.Type> src [s-8]) 496 (Move [s-s%16] dst src mem)) 497 (Move [s] dst src mem) && s%16 != 0 && s%16 > 8 && s > 16 => 498 (Move [16] 499 (OffPtr <dst.Type> dst [s-16]) 500 (OffPtr <src.Type> src [s-16]) 501 (Move [s-s%16] dst src mem)) 502 503 // medium move uses a duff device 504 (Move [s] dst src mem) 505 && s > 64 && s <= 16*64 && s%16 == 0 506 && !config.noDuffDevice && logLargeCopy(v, s) => 507 (DUFFCOPY [8 * (64 - s/16)] dst src mem) 508 // 8 is the number of bytes to encode: 509 // 510 // LDP.P 16(R16), (R26, R27) 511 // STP.P (R26, R27), 16(R17) 512 // 513 // 64 is number of these blocks. See runtime/duff_arm64.s:duffcopy 514 515 // large move uses a loop 516 (Move [s] dst src mem) 517 && s%16 == 0 && (s > 16*64 || config.noDuffDevice) 518 && logLargeCopy(v, s) => 519 (LoweredMove 520 dst 521 src 522 (ADDconst <src.Type> src [s-16]) 523 mem) 524 525 // calls 526 (StaticCall ...) => (CALLstatic ...) 527 (ClosureCall ...) => (CALLclosure ...) 528 (InterCall ...) => (CALLinter ...) 529 (TailCall ...) => (CALLtail ...) 530 531 // checks 532 (NilCheck ...) => (LoweredNilCheck ...) 533 (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr)) 534 (IsInBounds idx len) => (LessThanU (CMP idx len)) 535 (IsSliceInBounds idx len) => (LessEqualU (CMP idx len)) 536 537 // pseudo-ops 538 (GetClosurePtr ...) => (LoweredGetClosurePtr ...) 539 (GetCallerSP ...) => (LoweredGetCallerSP ...) 540 (GetCallerPC ...) => (LoweredGetCallerPC ...) 541 542 // Absorb pseudo-ops into blocks. 543 (If (Equal cc) yes no) => (EQ cc yes no) 544 (If (NotEqual cc) yes no) => (NE cc yes no) 545 (If (LessThan cc) yes no) => (LT cc yes no) 546 (If (LessThanU cc) yes no) => (ULT cc yes no) 547 (If (LessEqual cc) yes no) => (LE cc yes no) 548 (If (LessEqualU cc) yes no) => (ULE cc yes no) 549 (If (GreaterThan cc) yes no) => (GT cc yes no) 550 (If (GreaterThanU cc) yes no) => (UGT cc yes no) 551 (If (GreaterEqual cc) yes no) => (GE cc yes no) 552 (If (GreaterEqualU cc) yes no) => (UGE cc yes no) 553 (If (LessThanF cc) yes no) => (FLT cc yes no) 554 (If (LessEqualF cc) yes no) => (FLE cc yes no) 555 (If (GreaterThanF cc) yes no) => (FGT cc yes no) 556 (If (GreaterEqualF cc) yes no) => (FGE cc yes no) 557 558 (If cond yes no) => (TBNZ [0] cond yes no) 559 560 (JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr <typ.Uintptr> {makeJumpTableSym(b)} (SB))) 561 562 // atomic intrinsics 563 // Note: these ops do not accept offset. 564 (AtomicLoad8 ...) => (LDARB ...) 565 (AtomicLoad32 ...) => (LDARW ...) 566 (AtomicLoad64 ...) => (LDAR ...) 567 (AtomicLoadPtr ...) => (LDAR ...) 568 569 (AtomicStore8 ...) => (STLRB ...) 570 (AtomicStore32 ...) => (STLRW ...) 571 (AtomicStore64 ...) => (STLR ...) 572 (AtomicStorePtrNoWB ...) => (STLR ...) 573 574 (AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...) 575 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...) 576 (AtomicCompareAndSwap(32|64) ...) => (LoweredAtomicCas(32|64) ...) 577 578 (AtomicAdd(32|64)Variant ...) => (LoweredAtomicAdd(32|64)Variant ...) 579 (AtomicExchange(32|64)Variant ...) => (LoweredAtomicExchange(32|64)Variant ...) 580 (AtomicCompareAndSwap(32|64)Variant ...) => (LoweredAtomicCas(32|64)Variant ...) 581 582 // Currently the updated value is not used, but we need a register to temporarily hold it. 583 (AtomicAnd(8|32) ptr val mem) => (Select1 (LoweredAtomicAnd(8|32) ptr val mem)) 584 (AtomicOr(8|32) ptr val mem) => (Select1 (LoweredAtomicOr(8|32) ptr val mem)) 585 (AtomicAnd(8|32)Variant ptr val mem) => (Select1 (LoweredAtomicAnd(8|32)Variant ptr val mem)) 586 (AtomicOr(8|32)Variant ptr val mem) => (Select1 (LoweredAtomicOr(8|32)Variant ptr val mem)) 587 588 // Write barrier. 589 (WB ...) => (LoweredWB ...) 590 591 // Publication barrier (0xe is ST option) 592 (PubBarrier mem) => (DMB [0xe] mem) 593 594 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem) 595 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem) 596 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem) 597 598 // Optimizations 599 600 // Absorb boolean tests into block 601 (NZ (Equal cc) yes no) => (EQ cc yes no) 602 (NZ (NotEqual cc) yes no) => (NE cc yes no) 603 (NZ (LessThan cc) yes no) => (LT cc yes no) 604 (NZ (LessThanU cc) yes no) => (ULT cc yes no) 605 (NZ (LessEqual cc) yes no) => (LE cc yes no) 606 (NZ (LessEqualU cc) yes no) => (ULE cc yes no) 607 (NZ (GreaterThan cc) yes no) => (GT cc yes no) 608 (NZ (GreaterThanU cc) yes no) => (UGT cc yes no) 609 (NZ (GreaterEqual cc) yes no) => (GE cc yes no) 610 (NZ (GreaterEqualU cc) yes no) => (UGE cc yes no) 611 (NZ (LessThanF cc) yes no) => (FLT cc yes no) 612 (NZ (LessEqualF cc) yes no) => (FLE cc yes no) 613 (NZ (GreaterThanF cc) yes no) => (FGT cc yes no) 614 (NZ (GreaterEqualF cc) yes no) => (FGE cc yes no) 615 616 (TBNZ [0] (Equal cc) yes no) => (EQ cc yes no) 617 (TBNZ [0] (NotEqual cc) yes no) => (NE cc yes no) 618 (TBNZ [0] (LessThan cc) yes no) => (LT cc yes no) 619 (TBNZ [0] (LessThanU cc) yes no) => (ULT cc yes no) 620 (TBNZ [0] (LessEqual cc) yes no) => (LE cc yes no) 621 (TBNZ [0] (LessEqualU cc) yes no) => (ULE cc yes no) 622 (TBNZ [0] (GreaterThan cc) yes no) => (GT cc yes no) 623 (TBNZ [0] (GreaterThanU cc) yes no) => (UGT cc yes no) 624 (TBNZ [0] (GreaterEqual cc) yes no) => (GE cc yes no) 625 (TBNZ [0] (GreaterEqualU cc) yes no) => (UGE cc yes no) 626 (TBNZ [0] (LessThanF cc) yes no) => (FLT cc yes no) 627 (TBNZ [0] (LessEqualF cc) yes no) => (FLE cc yes no) 628 (TBNZ [0] (GreaterThanF cc) yes no) => (FGT cc yes no) 629 (TBNZ [0] (GreaterEqualF cc) yes no) => (FGE cc yes no) 630 631 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TST x y) yes no) 632 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTconst [c] y) yes no) 633 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTW x y) yes no) 634 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTWconst [int32(c)] y) yes no) 635 636 // For conditional instructions such as CSET, CSEL. 637 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] z:(AND x y))) && z.Uses == 1 => 638 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TST x y)) 639 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] x:(ANDconst [c] y))) && x.Uses == 1 => 640 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTWconst [int32(c)] y)) 641 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] z:(AND x y))) && z.Uses == 1 => 642 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTW x y)) 643 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] x:(ANDconst [c] y))) && x.Uses == 1 => 644 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTconst [c] y)) 645 646 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNconst [c] y) yes no) 647 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNWconst [int32(c)] y) yes no) 648 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN x y) yes no) 649 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW x y) yes no) 650 651 // CMP(x,-y) -> CMN(x,y) is only valid for unordered comparison, if y can be -1<<63 652 ((EQ|NE) (CMP x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMN x y) yes no) 653 ((Equal|NotEqual) (CMP x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMN x y)) 654 655 // CMPW(x,-y) -> CMNW(x,y) is only valid for unordered comparison, if y can be -1<<31 656 ((EQ|NE) (CMPW x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMNW x y) yes no) 657 ((Equal|NotEqual) (CMPW x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMNW x y)) 658 659 // For conditional instructions such as CSET, CSEL. 660 // TODO: add support for LE, GT, overflow needs to be considered. 661 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNconst [c] y)) 662 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNWconst [int32(c)] y)) 663 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN x y)) 664 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW x y)) 665 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(MADD a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN a (MUL <x.Type> x y))) 666 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(MSUB a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMP a (MUL <x.Type> x y))) 667 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(MADDW a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW a (MULW <x.Type> x y))) 668 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(MSUBW a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMPW a (MULW <x.Type> x y))) 669 670 ((CMPconst|CMNconst) [c] y) && c < 0 && c != -1<<63 => ((CMNconst|CMPconst) [-c] y) 671 ((CMPWconst|CMNWconst) [c] y) && c < 0 && c != -1<<31 => ((CMNWconst|CMPWconst) [-c] y) 672 673 ((EQ|NE) (CMPconst [0] x) yes no) => ((Z|NZ) x yes no) 674 ((EQ|NE) (CMPWconst [0] x) yes no) => ((ZW|NZW) x yes no) 675 676 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(MADD a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN a (MUL <x.Type> x y)) yes no) 677 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(MSUB a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMP a (MUL <x.Type> x y)) yes no) 678 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(MADDW a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW a (MULW <x.Type> x y)) yes no) 679 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(MSUBW a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMPW a (MULW <x.Type> x y)) yes no) 680 681 // Absorb bit-tests into block 682 (Z (ANDconst [c] x) yes no) && oneBit(c) => (TBZ [int64(ntz64(c))] x yes no) 683 (NZ (ANDconst [c] x) yes no) && oneBit(c) => (TBNZ [int64(ntz64(c))] x yes no) 684 (ZW (ANDconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) 685 (NZW (ANDconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) 686 (EQ (TSTconst [c] x) yes no) && oneBit(c) => (TBZ [int64(ntz64(c))] x yes no) 687 (NE (TSTconst [c] x) yes no) && oneBit(c) => (TBNZ [int64(ntz64(c))] x yes no) 688 (EQ (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBZ [int64(ntz64(int64(uint32(c))))] x yes no) 689 (NE (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no) 690 691 // Test sign-bit for signed comparisons against zero 692 (GE (CMPWconst [0] x) yes no) => (TBZ [31] x yes no) 693 (GE (CMPconst [0] x) yes no) => (TBZ [63] x yes no) 694 (LT (CMPWconst [0] x) yes no) => (TBNZ [31] x yes no) 695 (LT (CMPconst [0] x) yes no) => (TBNZ [63] x yes no) 696 697 // fold offset into address 698 (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => 699 (MOVDaddr [int32(off1)+off2] {sym} ptr) 700 701 // fold address into load/store. 702 // Do not fold global variable access in -dynlink mode, where it will 703 // be rewritten to use the GOT via REGTMP, which currently cannot handle 704 // large offset. 705 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 706 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 707 (MOVBload [off1+int32(off2)] {sym} ptr mem) 708 (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 709 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 710 (MOVBUload [off1+int32(off2)] {sym} ptr mem) 711 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 712 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 713 (MOVHload [off1+int32(off2)] {sym} ptr mem) 714 (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 715 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 716 (MOVHUload [off1+int32(off2)] {sym} ptr mem) 717 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 718 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 719 (MOVWload [off1+int32(off2)] {sym} ptr mem) 720 (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 721 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 722 (MOVWUload [off1+int32(off2)] {sym} ptr mem) 723 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 724 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 725 (MOVDload [off1+int32(off2)] {sym} ptr mem) 726 (LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 727 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 728 (LDP [off1+int32(off2)] {sym} ptr mem) 729 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 730 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 731 (FMOVSload [off1+int32(off2)] {sym} ptr mem) 732 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 733 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 734 (FMOVDload [off1+int32(off2)] {sym} ptr mem) 735 736 // register indexed load 737 (MOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem) 738 (MOVWUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem) 739 (MOVWload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem) 740 (MOVHUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem) 741 (MOVHload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem) 742 (MOVBUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem) 743 (MOVBload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem) 744 (FMOVSload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx ptr idx mem) 745 (FMOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx ptr idx mem) 746 747 (MOVDloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem) 748 (MOVDloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem) 749 (MOVWUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem) 750 (MOVWUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem) 751 (MOVWloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem) 752 (MOVWloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem) 753 (MOVHUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem) 754 (MOVHUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem) 755 (MOVHloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem) 756 (MOVHloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem) 757 (MOVBUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem) 758 (MOVBUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem) 759 (MOVBloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem) 760 (MOVBloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem) 761 (FMOVSloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (FMOVSload [int32(c)] ptr mem) 762 (FMOVSloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (FMOVSload [int32(c)] ptr mem) 763 (FMOVDloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (FMOVDload [int32(c)] ptr mem) 764 (FMOVDloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (FMOVDload [int32(c)] ptr mem) 765 766 // shifted register indexed load 767 (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx8 ptr idx mem) 768 (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx4 ptr idx mem) 769 (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx4 ptr idx mem) 770 (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx2 ptr idx mem) 771 (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx2 ptr idx mem) 772 (MOVDloadidx ptr (SLLconst [3] idx) mem) => (MOVDloadidx8 ptr idx mem) 773 (MOVWloadidx ptr (SLLconst [2] idx) mem) => (MOVWloadidx4 ptr idx mem) 774 (MOVWUloadidx ptr (SLLconst [2] idx) mem) => (MOVWUloadidx4 ptr idx mem) 775 (MOVHloadidx ptr (SLLconst [1] idx) mem) => (MOVHloadidx2 ptr idx mem) 776 (MOVHUloadidx ptr (SLLconst [1] idx) mem) => (MOVHUloadidx2 ptr idx mem) 777 (MOVHloadidx ptr (ADD idx idx) mem) => (MOVHloadidx2 ptr idx mem) 778 (MOVHUloadidx ptr (ADD idx idx) mem) => (MOVHUloadidx2 ptr idx mem) 779 (MOVDloadidx (SLLconst [3] idx) ptr mem) => (MOVDloadidx8 ptr idx mem) 780 (MOVWloadidx (SLLconst [2] idx) ptr mem) => (MOVWloadidx4 ptr idx mem) 781 (MOVWUloadidx (SLLconst [2] idx) ptr mem) => (MOVWUloadidx4 ptr idx mem) 782 (MOVHloadidx (ADD idx idx) ptr mem) => (MOVHloadidx2 ptr idx mem) 783 (MOVHUloadidx (ADD idx idx) ptr mem) => (MOVHUloadidx2 ptr idx mem) 784 (MOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (MOVDload [int32(c)<<3] ptr mem) 785 (MOVWUloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWUload [int32(c)<<2] ptr mem) 786 (MOVWloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWload [int32(c)<<2] ptr mem) 787 (MOVHUloadidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHUload [int32(c)<<1] ptr mem) 788 (MOVHloadidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHload [int32(c)<<1] ptr mem) 789 790 (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx8 ptr idx mem) 791 (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx4 ptr idx mem) 792 (FMOVDloadidx ptr (SLLconst [3] idx) mem) => (FMOVDloadidx8 ptr idx mem) 793 (FMOVSloadidx ptr (SLLconst [2] idx) mem) => (FMOVSloadidx4 ptr idx mem) 794 (FMOVDloadidx (SLLconst [3] idx) ptr mem) => (FMOVDloadidx8 ptr idx mem) 795 (FMOVSloadidx (SLLconst [2] idx) ptr mem) => (FMOVSloadidx4 ptr idx mem) 796 (FMOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem) 797 (FMOVSloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem) 798 799 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 800 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 801 (MOVBstore [off1+int32(off2)] {sym} ptr val mem) 802 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 803 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 804 (MOVHstore [off1+int32(off2)] {sym} ptr val mem) 805 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 806 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 807 (MOVWstore [off1+int32(off2)] {sym} ptr val mem) 808 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 809 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 810 (MOVDstore [off1+int32(off2)] {sym} ptr val mem) 811 (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2) 812 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 813 (STP [off1+int32(off2)] {sym} ptr val1 val2 mem) 814 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 815 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 816 (FMOVSstore [off1+int32(off2)] {sym} ptr val mem) 817 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) 818 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 819 (FMOVDstore [off1+int32(off2)] {sym} ptr val mem) 820 (MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 821 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 822 (MOVBstorezero [off1+int32(off2)] {sym} ptr mem) 823 (MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 824 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 825 (MOVHstorezero [off1+int32(off2)] {sym} ptr mem) 826 (MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 827 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 828 (MOVWstorezero [off1+int32(off2)] {sym} ptr mem) 829 (MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 830 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 831 (MOVDstorezero [off1+int32(off2)] {sym} ptr mem) 832 (MOVQstorezero [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) 833 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 834 (MOVQstorezero [off1+int32(off2)] {sym} ptr mem) 835 836 // register indexed store 837 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem) 838 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem) 839 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem) 840 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem) 841 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx ptr idx val mem) 842 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx ptr idx val mem) 843 (MOVDstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVDstore [int32(c)] ptr val mem) 844 (MOVDstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVDstore [int32(c)] idx val mem) 845 (MOVWstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVWstore [int32(c)] ptr val mem) 846 (MOVWstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVWstore [int32(c)] idx val mem) 847 (MOVHstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVHstore [int32(c)] ptr val mem) 848 (MOVHstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVHstore [int32(c)] idx val mem) 849 (MOVBstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVBstore [int32(c)] ptr val mem) 850 (MOVBstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVBstore [int32(c)] idx val mem) 851 (FMOVDstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (FMOVDstore [int32(c)] ptr val mem) 852 (FMOVDstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (FMOVDstore [int32(c)] idx val mem) 853 (FMOVSstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (FMOVSstore [int32(c)] ptr val mem) 854 (FMOVSstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (FMOVSstore [int32(c)] idx val mem) 855 856 // shifted register indexed store 857 (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx8 ptr idx val mem) 858 (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx4 ptr idx val mem) 859 (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx2 ptr idx val mem) 860 (MOVDstoreidx ptr (SLLconst [3] idx) val mem) => (MOVDstoreidx8 ptr idx val mem) 861 (MOVWstoreidx ptr (SLLconst [2] idx) val mem) => (MOVWstoreidx4 ptr idx val mem) 862 (MOVHstoreidx ptr (SLLconst [1] idx) val mem) => (MOVHstoreidx2 ptr idx val mem) 863 (MOVHstoreidx ptr (ADD idx idx) val mem) => (MOVHstoreidx2 ptr idx val mem) 864 (MOVDstoreidx (SLLconst [3] idx) ptr val mem) => (MOVDstoreidx8 ptr idx val mem) 865 (MOVWstoreidx (SLLconst [2] idx) ptr val mem) => (MOVWstoreidx4 ptr idx val mem) 866 (MOVHstoreidx (SLLconst [1] idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem) 867 (MOVHstoreidx (ADD idx idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem) 868 (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) && is32Bit(c<<3) => (MOVDstore [int32(c)<<3] ptr val mem) 869 (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (MOVWstore [int32(c)<<2] ptr val mem) 870 (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) && is32Bit(c<<1) => (MOVHstore [int32(c)<<1] ptr val mem) 871 872 (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx8 ptr idx val mem) 873 (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx4 ptr idx val mem) 874 (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) => (FMOVDstoreidx8 ptr idx val mem) 875 (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) => (FMOVSstoreidx4 ptr idx val mem) 876 (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) => (FMOVDstoreidx8 ptr idx val mem) 877 (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) => (FMOVSstoreidx4 ptr idx val mem) 878 (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) && is32Bit(c<<3) => (FMOVDstore [int32(c)<<3] ptr val mem) 879 (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem) 880 881 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 882 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 883 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 884 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 885 (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 886 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 887 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 888 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 889 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 890 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 891 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 892 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 893 (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 894 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 895 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 896 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 897 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 898 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 899 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 900 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 901 (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 902 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 903 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 904 (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 905 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 906 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 907 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 908 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 909 (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 910 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 911 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 912 (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 913 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 914 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 915 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 916 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 917 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 918 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 919 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 920 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 921 922 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 923 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 924 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 925 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 926 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 927 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 928 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 929 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 930 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 931 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 932 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 933 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 934 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 935 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 936 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 937 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 938 (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem) 939 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 940 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 941 (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem) 942 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 943 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 944 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 945 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 946 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) 947 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 948 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 949 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 950 (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 951 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 952 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 953 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 954 (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 955 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 956 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 957 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 958 (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 959 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 960 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 961 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 962 (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 963 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 964 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 965 (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 966 (MOVQstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) 967 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) 968 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) => 969 (MOVQstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 970 971 // store zero 972 (MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem) 973 (MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem) 974 (MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem) 975 (MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) => (MOVDstorezero [off] {sym} ptr mem) 976 (STP [off] {sym} ptr (MOVDconst [0]) (MOVDconst [0]) mem) => (MOVQstorezero [off] {sym} ptr mem) 977 978 // register indexed store zero 979 (MOVDstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDstorezeroidx ptr idx mem) 980 (MOVWstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWstorezeroidx ptr idx mem) 981 (MOVHstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHstorezeroidx ptr idx mem) 982 (MOVBstorezero [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBstorezeroidx ptr idx mem) 983 (MOVDstoreidx ptr idx (MOVDconst [0]) mem) => (MOVDstorezeroidx ptr idx mem) 984 (MOVWstoreidx ptr idx (MOVDconst [0]) mem) => (MOVWstorezeroidx ptr idx mem) 985 (MOVHstoreidx ptr idx (MOVDconst [0]) mem) => (MOVHstorezeroidx ptr idx mem) 986 (MOVBstoreidx ptr idx (MOVDconst [0]) mem) => (MOVBstorezeroidx ptr idx mem) 987 (MOVDstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVDstorezero [int32(c)] ptr mem) 988 (MOVDstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVDstorezero [int32(c)] idx mem) 989 (MOVWstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWstorezero [int32(c)] ptr mem) 990 (MOVWstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVWstorezero [int32(c)] idx mem) 991 (MOVHstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHstorezero [int32(c)] ptr mem) 992 (MOVHstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVHstorezero [int32(c)] idx mem) 993 (MOVBstorezeroidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBstorezero [int32(c)] ptr mem) 994 (MOVBstorezeroidx (MOVDconst [c]) idx mem) && is32Bit(c) => (MOVBstorezero [int32(c)] idx mem) 995 996 // shifted register indexed store zero 997 (MOVDstorezero [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (MOVDstorezeroidx8 ptr idx mem) 998 (MOVWstorezero [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWstorezeroidx4 ptr idx mem) 999 (MOVHstorezero [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHstorezeroidx2 ptr idx mem) 1000 (MOVDstorezeroidx ptr (SLLconst [3] idx) mem) => (MOVDstorezeroidx8 ptr idx mem) 1001 (MOVWstorezeroidx ptr (SLLconst [2] idx) mem) => (MOVWstorezeroidx4 ptr idx mem) 1002 (MOVHstorezeroidx ptr (SLLconst [1] idx) mem) => (MOVHstorezeroidx2 ptr idx mem) 1003 (MOVHstorezeroidx ptr (ADD idx idx) mem) => (MOVHstorezeroidx2 ptr idx mem) 1004 (MOVDstorezeroidx (SLLconst [3] idx) ptr mem) => (MOVDstorezeroidx8 ptr idx mem) 1005 (MOVWstorezeroidx (SLLconst [2] idx) ptr mem) => (MOVWstorezeroidx4 ptr idx mem) 1006 (MOVHstorezeroidx (SLLconst [1] idx) ptr mem) => (MOVHstorezeroidx2 ptr idx mem) 1007 (MOVHstorezeroidx (ADD idx idx) ptr mem) => (MOVHstorezeroidx2 ptr idx mem) 1008 (MOVDstoreidx8 ptr idx (MOVDconst [0]) mem) => (MOVDstorezeroidx8 ptr idx mem) 1009 (MOVWstoreidx4 ptr idx (MOVDconst [0]) mem) => (MOVWstorezeroidx4 ptr idx mem) 1010 (MOVHstoreidx2 ptr idx (MOVDconst [0]) mem) => (MOVHstorezeroidx2 ptr idx mem) 1011 (MOVDstorezeroidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (MOVDstorezero [int32(c<<3)] ptr mem) 1012 (MOVWstorezeroidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWstorezero [int32(c<<2)] ptr mem) 1013 (MOVHstorezeroidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHstorezero [int32(c<<1)] ptr mem) 1014 1015 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) 1016 // these seem to have bad interaction with other rules, resulting in slower code 1017 //(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBreg x) 1018 //(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBUreg x) 1019 //(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHreg x) 1020 //(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHUreg x) 1021 //(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWreg x) 1022 //(MOVWUload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWUreg x) 1023 //(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 1024 //(FMOVSload [off] {sym} ptr (FMOVSstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 1025 //(FMOVDload [off] {sym} ptr (FMOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 1026 //(LDP [off] {sym} ptr (STP [off2] {sym2} ptr2 x y _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x y 1027 1028 (MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1029 (MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1030 (MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1031 (MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1032 (MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1033 (MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1034 (MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVDconst [0]) 1035 1036 (MOVBloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) 1037 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1038 (MOVBUloadidx ptr idx (MOVBstorezeroidx ptr2 idx2 _)) 1039 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1040 (MOVHloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) 1041 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1042 (MOVHUloadidx ptr idx (MOVHstorezeroidx ptr2 idx2 _)) 1043 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1044 (MOVWloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) 1045 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1046 (MOVWUloadidx ptr idx (MOVWstorezeroidx ptr2 idx2 _)) 1047 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1048 (MOVDloadidx ptr idx (MOVDstorezeroidx ptr2 idx2 _)) 1049 && (isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) || isSamePtr(ptr, idx2) && isSamePtr(idx, ptr2)) => (MOVDconst [0]) 1050 1051 (MOVHloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) 1052 (MOVHUloadidx2 ptr idx (MOVHstorezeroidx2 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) 1053 (MOVWloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) 1054 (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) 1055 (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) 1056 1057 // don't extend after proper load 1058 (MOVBreg x:(MOVBload _ _)) => (MOVDreg x) 1059 (MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x) 1060 (MOVHreg x:(MOVBload _ _)) => (MOVDreg x) 1061 (MOVHreg x:(MOVBUload _ _)) => (MOVDreg x) 1062 (MOVHreg x:(MOVHload _ _)) => (MOVDreg x) 1063 (MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x) 1064 (MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x) 1065 (MOVWreg x:(MOVBload _ _)) => (MOVDreg x) 1066 (MOVWreg x:(MOVBUload _ _)) => (MOVDreg x) 1067 (MOVWreg x:(MOVHload _ _)) => (MOVDreg x) 1068 (MOVWreg x:(MOVHUload _ _)) => (MOVDreg x) 1069 (MOVWreg x:(MOVWload _ _)) => (MOVDreg x) 1070 (MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x) 1071 (MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x) 1072 (MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x) 1073 (MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) 1074 (MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) 1075 (MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) 1076 (MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) 1077 (MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) 1078 (MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) 1079 (MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) 1080 (MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) 1081 (MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) 1082 (MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) 1083 (MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) 1084 (MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x) 1085 (MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) 1086 (MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) 1087 (MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x) 1088 (MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) 1089 (MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) 1090 (MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) 1091 (MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) 1092 (MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x) 1093 (MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) 1094 (MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x) 1095 1096 // fold double extensions 1097 (MOVBreg x:(MOVBreg _)) => (MOVDreg x) 1098 (MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) 1099 (MOVHreg x:(MOVBreg _)) => (MOVDreg x) 1100 (MOVHreg x:(MOVBUreg _)) => (MOVDreg x) 1101 (MOVHreg x:(MOVHreg _)) => (MOVDreg x) 1102 (MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) 1103 (MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) 1104 (MOVWreg x:(MOVBreg _)) => (MOVDreg x) 1105 (MOVWreg x:(MOVBUreg _)) => (MOVDreg x) 1106 (MOVWreg x:(MOVHreg _)) => (MOVDreg x) 1107 (MOVWreg x:(MOVWreg _)) => (MOVDreg x) 1108 (MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) 1109 (MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) 1110 (MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) 1111 1112 // don't extend before store 1113 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1114 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1115 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1116 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1117 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1118 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 1119 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 1120 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 1121 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 1122 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 1123 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem) 1124 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem) 1125 (MOVBstoreidx ptr idx (MOVBreg x) mem) => (MOVBstoreidx ptr idx x mem) 1126 (MOVBstoreidx ptr idx (MOVBUreg x) mem) => (MOVBstoreidx ptr idx x mem) 1127 (MOVBstoreidx ptr idx (MOVHreg x) mem) => (MOVBstoreidx ptr idx x mem) 1128 (MOVBstoreidx ptr idx (MOVHUreg x) mem) => (MOVBstoreidx ptr idx x mem) 1129 (MOVBstoreidx ptr idx (MOVWreg x) mem) => (MOVBstoreidx ptr idx x mem) 1130 (MOVBstoreidx ptr idx (MOVWUreg x) mem) => (MOVBstoreidx ptr idx x mem) 1131 (MOVHstoreidx ptr idx (MOVHreg x) mem) => (MOVHstoreidx ptr idx x mem) 1132 (MOVHstoreidx ptr idx (MOVHUreg x) mem) => (MOVHstoreidx ptr idx x mem) 1133 (MOVHstoreidx ptr idx (MOVWreg x) mem) => (MOVHstoreidx ptr idx x mem) 1134 (MOVHstoreidx ptr idx (MOVWUreg x) mem) => (MOVHstoreidx ptr idx x mem) 1135 (MOVWstoreidx ptr idx (MOVWreg x) mem) => (MOVWstoreidx ptr idx x mem) 1136 (MOVWstoreidx ptr idx (MOVWUreg x) mem) => (MOVWstoreidx ptr idx x mem) 1137 (MOVHstoreidx2 ptr idx (MOVHreg x) mem) => (MOVHstoreidx2 ptr idx x mem) 1138 (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) => (MOVHstoreidx2 ptr idx x mem) 1139 (MOVHstoreidx2 ptr idx (MOVWreg x) mem) => (MOVHstoreidx2 ptr idx x mem) 1140 (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) => (MOVHstoreidx2 ptr idx x mem) 1141 (MOVWstoreidx4 ptr idx (MOVWreg x) mem) => (MOVWstoreidx4 ptr idx x mem) 1142 (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) => (MOVWstoreidx4 ptr idx x mem) 1143 1144 // if a register move has only 1 use, just use the same register without emitting instruction 1145 // MOVDnop doesn't emit instruction, only for ensuring the type. 1146 (MOVDreg x) && x.Uses == 1 => (MOVDnop x) 1147 1148 // TODO: we should be able to get rid of MOVDnop all together. 1149 // But for now, this is enough to get rid of lots of them. 1150 (MOVDnop (MOVDconst [c])) => (MOVDconst [c]) 1151 1152 // fold constant into arithmetic ops 1153 (ADD x (MOVDconst <t> [c])) && !t.IsPtr() => (ADDconst [c] x) 1154 (SUB x (MOVDconst [c])) => (SUBconst [c] x) 1155 (AND x (MOVDconst [c])) => (ANDconst [c] x) 1156 (OR x (MOVDconst [c])) => (ORconst [c] x) 1157 (XOR x (MOVDconst [c])) => (XORconst [c] x) 1158 (TST x (MOVDconst [c])) => (TSTconst [c] x) 1159 (TSTW x (MOVDconst [c])) => (TSTWconst [int32(c)] x) 1160 (CMN x (MOVDconst [c])) => (CMNconst [c] x) 1161 (CMNW x (MOVDconst [c])) => (CMNWconst [int32(c)] x) 1162 (BIC x (MOVDconst [c])) => (ANDconst [^c] x) 1163 (EON x (MOVDconst [c])) => (XORconst [^c] x) 1164 (ORN x (MOVDconst [c])) => (ORconst [^c] x) 1165 1166 (SLL x (MOVDconst [c])) => (SLLconst x [c&63]) 1167 (SRL x (MOVDconst [c])) => (SRLconst x [c&63]) 1168 (SRA x (MOVDconst [c])) => (SRAconst x [c&63]) 1169 (SLL x (ANDconst [63] y)) => (SLL x y) 1170 (SRL x (ANDconst [63] y)) => (SRL x y) 1171 (SRA x (ANDconst [63] y)) => (SRA x y) 1172 1173 (CMP x (MOVDconst [c])) => (CMPconst [c] x) 1174 (CMP (MOVDconst [c]) x) => (InvertFlags (CMPconst [c] x)) 1175 (CMPW x (MOVDconst [c])) => (CMPWconst [int32(c)] x) 1176 (CMPW (MOVDconst [c]) x) => (InvertFlags (CMPWconst [int32(c)] x)) 1177 1178 (ROR x (MOVDconst [c])) => (RORconst x [c&63]) 1179 (RORW x (MOVDconst [c])) => (RORWconst x [c&31]) 1180 1181 (ADDSflags x (MOVDconst [c])) => (ADDSconstflags [c] x) 1182 1183 (ADDconst [c] y) && c < 0 => (SUBconst [-c] y) 1184 1185 // Canonicalize the order of arguments to comparisons - helps with CSE. 1186 ((CMP|CMPW) x y) && canonLessThan(x,y) => (InvertFlags ((CMP|CMPW) y x)) 1187 1188 // mul-neg => mneg 1189 (NEG (MUL x y)) => (MNEG x y) 1190 (NEG (MULW x y)) && v.Type.Size() <= 4 => (MNEGW x y) 1191 (MUL (NEG x) y) => (MNEG x y) 1192 (MULW (NEG x) y) => (MNEGW x y) 1193 1194 // madd/msub 1195 (ADD a l:(MUL x y)) && l.Uses==1 && clobber(l) => (MADD a x y) 1196 (SUB a l:(MUL x y)) && l.Uses==1 && clobber(l) => (MSUB a x y) 1197 (ADD a l:(MNEG x y)) && l.Uses==1 && clobber(l) => (MSUB a x y) 1198 (SUB a l:(MNEG x y)) && l.Uses==1 && clobber(l) => (MADD a x y) 1199 1200 (ADD a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MADDW a x y) 1201 (SUB a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MSUBW a x y) 1202 (ADD a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MSUBW a x y) 1203 (SUB a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MADDW a x y) 1204 1205 // optimize ADCSflags, SBCSflags and friends 1206 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (ADCzerocarry <typ.UInt64> c)))) => (ADCSflags x y c) 1207 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0])))) => (ADDSflags x y) 1208 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> bo))))) => (SBCSflags x y bo) 1209 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (MOVDconst [0])))) => (SUBSflags x y) 1210 1211 // mul by constant 1212 (MUL x (MOVDconst [-1])) => (NEG x) 1213 (MUL _ (MOVDconst [0])) => (MOVDconst [0]) 1214 (MUL x (MOVDconst [1])) => x 1215 (MUL x (MOVDconst [c])) && isPowerOfTwo64(c) => (SLLconst [log64(c)] x) 1216 (MUL x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c >= 3 => (ADDshiftLL x x [log64(c-1)]) 1217 (MUL x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c >= 7 => (ADDshiftLL (NEG <x.Type> x) x [log64(c+1)]) 1218 (MUL x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SLLconst [log64(c/3)] (ADDshiftLL <x.Type> x x [1])) 1219 (MUL x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (SLLconst [log64(c/5)] (ADDshiftLL <x.Type> x x [2])) 1220 (MUL x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SLLconst [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3])) 1221 (MUL x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (SLLconst [log64(c/9)] (ADDshiftLL <x.Type> x x [3])) 1222 1223 (MULW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (NEG <x.Type> x)) 1224 (MULW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0]) 1225 (MULW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg x) 1226 (MULW x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (SLLconst <x.Type> [log64(c)] x)) 1227 (MULW x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c) >= 3 => (MOVWUreg (ADDshiftLL <x.Type> x x [log64(c-1)])) 1228 (MULW x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c) >= 7 => (MOVWUreg (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])) 1229 (MULW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (ADDshiftLL <x.Type> x x [1]))) 1230 (MULW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))) 1231 (MULW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))) 1232 (MULW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))) 1233 1234 // mneg by constant 1235 (MNEG x (MOVDconst [-1])) => x 1236 (MNEG _ (MOVDconst [0])) => (MOVDconst [0]) 1237 (MNEG x (MOVDconst [1])) => (NEG x) 1238 (MNEG x (MOVDconst [c])) && isPowerOfTwo64(c) => (NEG (SLLconst <x.Type> [log64(c)] x)) 1239 (MNEG x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c >= 3 => (NEG (ADDshiftLL <x.Type> x x [log64(c-1)])) 1240 (MNEG x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c >= 7 => (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])) 1241 (MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2])) 1242 (MNEG x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (NEG (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))) 1243 (MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3])) 1244 (MNEG x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (NEG (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))) 1245 1246 1247 (MNEGW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg x) 1248 (MNEGW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0]) 1249 (MNEGW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (NEG <x.Type> x)) 1250 (MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c) => (NEG (SLLconst <x.Type> [log64(c)] x)) 1251 (MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c) >= 3 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [log64(c-1)]))) 1252 (MNEGW x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c) >= 7 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))) 1253 (MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2]))) 1254 (MNEGW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))) 1255 (MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3]))) 1256 (MNEGW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))) 1257 1258 1259 (MADD a x (MOVDconst [-1])) => (SUB a x) 1260 (MADD a _ (MOVDconst [0])) => a 1261 (MADD a x (MOVDconst [1])) => (ADD a x) 1262 (MADD a x (MOVDconst [c])) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)]) 1263 (MADD a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)])) 1264 (MADD a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)])) 1265 (MADD a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]) 1266 (MADD a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]) 1267 (MADD a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]) 1268 (MADD a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]) 1269 1270 (MADD a (MOVDconst [-1]) x) => (SUB a x) 1271 (MADD a (MOVDconst [0]) _) => a 1272 (MADD a (MOVDconst [1]) x) => (ADD a x) 1273 (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)]) 1274 (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)])) 1275 (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)])) 1276 (MADD a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]) 1277 (MADD a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]) 1278 (MADD a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]) 1279 (MADD a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]) 1280 1281 (MADDW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x)) 1282 (MADDW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a) 1283 (MADDW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x)) 1284 (MADDW a x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)])) 1285 (MADDW a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)]))) 1286 (MADDW a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)]))) 1287 (MADDW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])) 1288 (MADDW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])) 1289 (MADDW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])) 1290 (MADDW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])) 1291 1292 (MADDW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x)) 1293 (MADDW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a) 1294 (MADDW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x)) 1295 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)])) 1296 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)]))) 1297 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)]))) 1298 (MADDW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])) 1299 (MADDW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])) 1300 (MADDW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])) 1301 (MADDW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])) 1302 1303 (MSUB a x (MOVDconst [-1])) => (ADD a x) 1304 (MSUB a _ (MOVDconst [0])) => a 1305 (MSUB a x (MOVDconst [1])) => (SUB a x) 1306 (MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c) => (SUBshiftLL a x [log64(c)]) 1307 (MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)])) 1308 (MSUB a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)])) 1309 (MSUB a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]) 1310 (MSUB a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]) 1311 (MSUB a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]) 1312 (MSUB a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]) 1313 1314 (MSUB a (MOVDconst [-1]) x) => (ADD a x) 1315 (MSUB a (MOVDconst [0]) _) => a 1316 (MSUB a (MOVDconst [1]) x) => (SUB a x) 1317 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (SUBshiftLL a x [log64(c)]) 1318 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)])) 1319 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)])) 1320 (MSUB a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]) 1321 (MSUB a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]) 1322 (MSUB a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]) 1323 (MSUB a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]) 1324 1325 (MSUBW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x)) 1326 (MSUBW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a) 1327 (MSUBW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x)) 1328 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)])) 1329 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)]))) 1330 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo64(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)]))) 1331 (MSUBW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])) 1332 (MSUBW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])) 1333 (MSUBW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])) 1334 (MSUBW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])) 1335 1336 (MSUBW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x)) 1337 (MSUBW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a) 1338 (MSUBW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x)) 1339 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)])) 1340 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)]))) 1341 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)]))) 1342 (MSUBW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo64(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])) 1343 (MSUBW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo64(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])) 1344 (MSUBW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo64(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])) 1345 (MSUBW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo64(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])) 1346 1347 // div by constant 1348 (UDIV x (MOVDconst [1])) => x 1349 (UDIV x (MOVDconst [c])) && isPowerOfTwo64(c) => (SRLconst [log64(c)] x) 1350 (UDIVW x (MOVDconst [c])) && uint32(c)==1 => (MOVWUreg x) 1351 (UDIVW x (MOVDconst [c])) && isPowerOfTwo64(c) && is32Bit(c) => (SRLconst [log64(c)] (MOVWUreg <v.Type> x)) 1352 (UMOD _ (MOVDconst [1])) => (MOVDconst [0]) 1353 (UMOD x (MOVDconst [c])) && isPowerOfTwo64(c) => (ANDconst [c-1] x) 1354 (UMODW _ (MOVDconst [c])) && uint32(c)==1 => (MOVDconst [0]) 1355 (UMODW x (MOVDconst [c])) && isPowerOfTwo64(c) && is32Bit(c) => (ANDconst [c-1] x) 1356 1357 // generic simplifications 1358 (ADD x (NEG y)) => (SUB x y) 1359 (SUB x x) => (MOVDconst [0]) 1360 (AND x x) => x 1361 (OR x x) => x 1362 (XOR x x) => (MOVDconst [0]) 1363 (BIC x x) => (MOVDconst [0]) 1364 (EON x x) => (MOVDconst [-1]) 1365 (ORN x x) => (MOVDconst [-1]) 1366 (AND x (MVN y)) => (BIC x y) 1367 (XOR x (MVN y)) => (EON x y) 1368 (OR x (MVN y)) => (ORN x y) 1369 (MVN (XOR x y)) => (EON x y) 1370 (NEG (NEG x)) => x 1371 1372 (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) => (CSETM [cc] flag) 1373 (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) => (CSETM [arm64Negate(cc)] flag) 1374 (CSEL [cc] x (MOVDconst [0]) flag) => (CSEL0 [cc] x flag) 1375 (CSEL [cc] (MOVDconst [0]) y flag) => (CSEL0 [arm64Negate(cc)] y flag) 1376 (CSEL [cc] x (ADDconst [1] a) flag) => (CSINC [cc] x a flag) 1377 (CSEL [cc] (ADDconst [1] a) x flag) => (CSINC [arm64Negate(cc)] x a flag) 1378 (CSEL [cc] x (MVN a) flag) => (CSINV [cc] x a flag) 1379 (CSEL [cc] (MVN a) x flag) => (CSINV [arm64Negate(cc)] x a flag) 1380 (CSEL [cc] x (NEG a) flag) => (CSNEG [cc] x a flag) 1381 (CSEL [cc] (NEG a) x flag) => (CSNEG [arm64Negate(cc)] x a flag) 1382 1383 (SUB x (SUB y z)) => (SUB (ADD <v.Type> x z) y) 1384 (SUB (SUB x y) z) => (SUB x (ADD <y.Type> y z)) 1385 1386 // remove redundant *const ops 1387 (ADDconst [0] x) => x 1388 (SUBconst [0] x) => x 1389 (ANDconst [0] _) => (MOVDconst [0]) 1390 (ANDconst [-1] x) => x 1391 (ORconst [0] x) => x 1392 (ORconst [-1] _) => (MOVDconst [-1]) 1393 (XORconst [0] x) => x 1394 (XORconst [-1] x) => (MVN x) 1395 1396 // generic constant folding 1397 (ADDconst [c] (MOVDconst [d])) => (MOVDconst [c+d]) 1398 (ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x) 1399 (ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x) 1400 (SUBconst [c] (MOVDconst [d])) => (MOVDconst [d-c]) 1401 (SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x) 1402 (SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x) 1403 (SLLconst [c] (MOVDconst [d])) => (MOVDconst [d<<uint64(c)]) 1404 (SRLconst [c] (MOVDconst [d])) => (MOVDconst [int64(uint64(d)>>uint64(c))]) 1405 (SRAconst [c] (MOVDconst [d])) => (MOVDconst [d>>uint64(c)]) 1406 (MUL (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c*d]) 1407 (MNEG (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [-c*d]) 1408 (MULW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(c*d))]) 1409 (MNEGW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(-c*d))]) 1410 (MADD (MOVDconst [c]) x y) => (ADDconst [c] (MUL <x.Type> x y)) 1411 (MSUB (MOVDconst [c]) x y) => (ADDconst [c] (MNEG <x.Type> x y)) 1412 (MADD a (MOVDconst [c]) (MOVDconst [d])) => (ADDconst [c*d] a) 1413 (MSUB a (MOVDconst [c]) (MOVDconst [d])) => (SUBconst [c*d] a) 1414 (MADDW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MULW <x.Type> x y))) 1415 (MSUBW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MNEGW <x.Type> x y))) 1416 (MADDW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (ADDconst <a.Type> [c*d] a)) 1417 (MSUBW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (SUBconst <a.Type> [c*d] a)) 1418 (DIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c/d]) 1419 (UDIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)/uint64(d))]) 1420 (DIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)/int32(d)))]) 1421 (UDIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)/uint32(d))]) 1422 (MOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c%d]) 1423 (UMOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)%uint64(d))]) 1424 (MODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)%int32(d)))]) 1425 (UMODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)%uint32(d))]) 1426 (ANDconst [c] (MOVDconst [d])) => (MOVDconst [c&d]) 1427 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) 1428 (ANDconst [c] (MOVWUreg x)) => (ANDconst [c&(1<<32-1)] x) 1429 (ANDconst [c] (MOVHUreg x)) => (ANDconst [c&(1<<16-1)] x) 1430 (ANDconst [c] (MOVBUreg x)) => (ANDconst [c&(1<<8-1)] x) 1431 (MOVWUreg (ANDconst [c] x)) => (ANDconst [c&(1<<32-1)] x) 1432 (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&(1<<16-1)] x) 1433 (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&(1<<8-1)] x) 1434 (ORconst [c] (MOVDconst [d])) => (MOVDconst [c|d]) 1435 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x) 1436 (XORconst [c] (MOVDconst [d])) => (MOVDconst [c^d]) 1437 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x) 1438 (MVN (MOVDconst [c])) => (MOVDconst [^c]) 1439 (NEG (MOVDconst [c])) => (MOVDconst [-c]) 1440 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))]) 1441 (MOVBUreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))]) 1442 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))]) 1443 (MOVHUreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))]) 1444 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))]) 1445 (MOVWUreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))]) 1446 (MOVDreg (MOVDconst [c])) => (MOVDconst [c]) 1447 1448 // constant comparisons 1449 (CMPconst (MOVDconst [x]) [y]) => (FlagConstant [subFlags64(x,y)]) 1450 (CMPWconst (MOVDconst [x]) [y]) => (FlagConstant [subFlags32(int32(x),y)]) 1451 (TSTconst (MOVDconst [x]) [y]) => (FlagConstant [logicFlags64(x&y)]) 1452 (TSTWconst (MOVDconst [x]) [y]) => (FlagConstant [logicFlags32(int32(x)&y)]) 1453 (CMNconst (MOVDconst [x]) [y]) => (FlagConstant [addFlags64(x,y)]) 1454 (CMNWconst (MOVDconst [x]) [y]) => (FlagConstant [addFlags32(int32(x),y)]) 1455 1456 // other known comparisons 1457 (CMPconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [subFlags64(0,1)]) 1458 (CMPconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [subFlags64(0,1)]) 1459 (CMPconst (MOVWUreg _) [c]) && 0xffffffff < c => (FlagConstant [subFlags64(0,1)]) 1460 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n => (FlagConstant [subFlags64(0,1)]) 1461 (CMPconst (SRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n) => (FlagConstant [subFlags64(0,1)]) 1462 (CMPWconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [subFlags64(0,1)]) 1463 (CMPWconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [subFlags64(0,1)]) 1464 1465 // absorb flag constants into branches 1466 (EQ (FlagConstant [fc]) yes no) && fc.eq() => (First yes no) 1467 (EQ (FlagConstant [fc]) yes no) && !fc.eq() => (First no yes) 1468 1469 (NE (FlagConstant [fc]) yes no) && fc.ne() => (First yes no) 1470 (NE (FlagConstant [fc]) yes no) && !fc.ne() => (First no yes) 1471 1472 (LT (FlagConstant [fc]) yes no) && fc.lt() => (First yes no) 1473 (LT (FlagConstant [fc]) yes no) && !fc.lt() => (First no yes) 1474 1475 (LE (FlagConstant [fc]) yes no) && fc.le() => (First yes no) 1476 (LE (FlagConstant [fc]) yes no) && !fc.le() => (First no yes) 1477 1478 (GT (FlagConstant [fc]) yes no) && fc.gt() => (First yes no) 1479 (GT (FlagConstant [fc]) yes no) && !fc.gt() => (First no yes) 1480 1481 (GE (FlagConstant [fc]) yes no) && fc.ge() => (First yes no) 1482 (GE (FlagConstant [fc]) yes no) && !fc.ge() => (First no yes) 1483 1484 (ULT (FlagConstant [fc]) yes no) && fc.ult() => (First yes no) 1485 (ULT (FlagConstant [fc]) yes no) && !fc.ult() => (First no yes) 1486 1487 (ULE (FlagConstant [fc]) yes no) && fc.ule() => (First yes no) 1488 (ULE (FlagConstant [fc]) yes no) && !fc.ule() => (First no yes) 1489 1490 (UGT (FlagConstant [fc]) yes no) && fc.ugt() => (First yes no) 1491 (UGT (FlagConstant [fc]) yes no) && !fc.ugt() => (First no yes) 1492 1493 (UGE (FlagConstant [fc]) yes no) && fc.uge() => (First yes no) 1494 (UGE (FlagConstant [fc]) yes no) && !fc.uge() => (First no yes) 1495 1496 (LTnoov (FlagConstant [fc]) yes no) && fc.ltNoov() => (First yes no) 1497 (LTnoov (FlagConstant [fc]) yes no) && !fc.ltNoov() => (First no yes) 1498 1499 (LEnoov (FlagConstant [fc]) yes no) && fc.leNoov() => (First yes no) 1500 (LEnoov (FlagConstant [fc]) yes no) && !fc.leNoov() => (First no yes) 1501 1502 (GTnoov (FlagConstant [fc]) yes no) && fc.gtNoov() => (First yes no) 1503 (GTnoov (FlagConstant [fc]) yes no) && !fc.gtNoov() => (First no yes) 1504 1505 (GEnoov (FlagConstant [fc]) yes no) && fc.geNoov() => (First yes no) 1506 (GEnoov (FlagConstant [fc]) yes no) && !fc.geNoov() => (First no yes) 1507 1508 (Z (MOVDconst [0]) yes no) => (First yes no) 1509 (Z (MOVDconst [c]) yes no) && c != 0 => (First no yes) 1510 (NZ (MOVDconst [0]) yes no) => (First no yes) 1511 (NZ (MOVDconst [c]) yes no) && c != 0 => (First yes no) 1512 (ZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First yes no) 1513 (ZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First no yes) 1514 (NZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First no yes) 1515 (NZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First yes no) 1516 1517 // absorb InvertFlags into branches 1518 (LT (InvertFlags cmp) yes no) => (GT cmp yes no) 1519 (GT (InvertFlags cmp) yes no) => (LT cmp yes no) 1520 (LE (InvertFlags cmp) yes no) => (GE cmp yes no) 1521 (GE (InvertFlags cmp) yes no) => (LE cmp yes no) 1522 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no) 1523 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no) 1524 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no) 1525 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no) 1526 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no) 1527 (NE (InvertFlags cmp) yes no) => (NE cmp yes no) 1528 (FLT (InvertFlags cmp) yes no) => (FGT cmp yes no) 1529 (FGT (InvertFlags cmp) yes no) => (FLT cmp yes no) 1530 (FLE (InvertFlags cmp) yes no) => (FGE cmp yes no) 1531 (FGE (InvertFlags cmp) yes no) => (FLE cmp yes no) 1532 (LTnoov (InvertFlags cmp) yes no) => (GTnoov cmp yes no) 1533 (GEnoov (InvertFlags cmp) yes no) => (LEnoov cmp yes no) 1534 (LEnoov (InvertFlags cmp) yes no) => (GEnoov cmp yes no) 1535 (GTnoov (InvertFlags cmp) yes no) => (LTnoov cmp yes no) 1536 1537 // absorb InvertFlags into conditional instructions 1538 (CSEL [cc] x y (InvertFlags cmp)) => (CSEL [arm64Invert(cc)] x y cmp) 1539 (CSEL0 [cc] x (InvertFlags cmp)) => (CSEL0 [arm64Invert(cc)] x cmp) 1540 (CSETM [cc] (InvertFlags cmp)) => (CSETM [arm64Invert(cc)] cmp) 1541 (CSINC [cc] x y (InvertFlags cmp)) => (CSINC [arm64Invert(cc)] x y cmp) 1542 (CSINV [cc] x y (InvertFlags cmp)) => (CSINV [arm64Invert(cc)] x y cmp) 1543 (CSNEG [cc] x y (InvertFlags cmp)) => (CSNEG [arm64Invert(cc)] x y cmp) 1544 1545 // absorb flag constants into boolean values 1546 (Equal (FlagConstant [fc])) => (MOVDconst [b2i(fc.eq())]) 1547 (NotEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.ne())]) 1548 (LessThan (FlagConstant [fc])) => (MOVDconst [b2i(fc.lt())]) 1549 (LessThanU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ult())]) 1550 (LessEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.le())]) 1551 (LessEqualU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ule())]) 1552 (GreaterThan (FlagConstant [fc])) => (MOVDconst [b2i(fc.gt())]) 1553 (GreaterThanU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ugt())]) 1554 (GreaterEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.ge())]) 1555 (GreaterEqualU (FlagConstant [fc])) => (MOVDconst [b2i(fc.uge())]) 1556 1557 // absorb InvertFlags into boolean values 1558 (Equal (InvertFlags x)) => (Equal x) 1559 (NotEqual (InvertFlags x)) => (NotEqual x) 1560 (LessThan (InvertFlags x)) => (GreaterThan x) 1561 (LessThanU (InvertFlags x)) => (GreaterThanU x) 1562 (GreaterThan (InvertFlags x)) => (LessThan x) 1563 (GreaterThanU (InvertFlags x)) => (LessThanU x) 1564 (LessEqual (InvertFlags x)) => (GreaterEqual x) 1565 (LessEqualU (InvertFlags x)) => (GreaterEqualU x) 1566 (GreaterEqual (InvertFlags x)) => (LessEqual x) 1567 (GreaterEqualU (InvertFlags x)) => (LessEqualU x) 1568 (LessThanF (InvertFlags x)) => (GreaterThanF x) 1569 (LessEqualF (InvertFlags x)) => (GreaterEqualF x) 1570 (GreaterThanF (InvertFlags x)) => (LessThanF x) 1571 (GreaterEqualF (InvertFlags x)) => (LessEqualF x) 1572 (LessThanNoov (InvertFlags x)) => (CSEL0 [OpARM64NotEqual] (GreaterEqualNoov <typ.Bool> x) x) 1573 (GreaterEqualNoov (InvertFlags x)) => (CSINC [OpARM64NotEqual] (LessThanNoov <typ.Bool> x) (MOVDconst [0]) x) 1574 1575 // Boolean-generating instructions (NOTE: NOT all boolean Values) always 1576 // zero upper bit of the register; no need to zero-extend 1577 (MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => (MOVDreg x) 1578 1579 // Don't bother extending if we're not using the higher bits. 1580 (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x 1581 (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x 1582 (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x 1583 1584 // omit unsign extension 1585 (MOVWUreg x) && zeroUpper32Bits(x, 3) => x 1586 1587 // omit sign extension 1588 (MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c]) 1589 (MOVHreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffff8000) == 0 => (ANDconst <t> x [c]) 1590 (MOVBreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffffff80) == 0 => (ANDconst <t> x [c]) 1591 1592 // absorb flag constants into conditional instructions 1593 (CSEL [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x 1594 (CSEL [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => y 1595 (CSEL0 [cc] x flag) && ccARM64Eval(cc, flag) > 0 => x 1596 (CSEL0 [cc] _ flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0]) 1597 (CSNEG [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x 1598 (CSNEG [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (NEG y) 1599 (CSINV [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x 1600 (CSINV [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (Not y) 1601 (CSINC [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x 1602 (CSINC [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (ADDconst [1] y) 1603 (CSETM [cc] flag) && ccARM64Eval(cc, flag) > 0 => (MOVDconst [-1]) 1604 (CSETM [cc] flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0]) 1605 1606 // absorb flags back into boolean CSEL 1607 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == OpARM64NotEqual && flagArg(boolval) != nil => 1608 (CSEL [boolval.Op] x y flagArg(boolval)) 1609 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == OpARM64Equal && flagArg(boolval) != nil => 1610 (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval)) 1611 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == OpARM64NotEqual && flagArg(boolval) != nil => 1612 (CSEL0 [boolval.Op] x flagArg(boolval)) 1613 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == OpARM64Equal && flagArg(boolval) != nil => 1614 (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval)) 1615 1616 // absorb shifts into ops 1617 (NEG x:(SLLconst [c] y)) && clobberIfDead(x) => (NEGshiftLL [c] y) 1618 (NEG x:(SRLconst [c] y)) && clobberIfDead(x) => (NEGshiftRL [c] y) 1619 (NEG x:(SRAconst [c] y)) && clobberIfDead(x) => (NEGshiftRA [c] y) 1620 (MVN x:(SLLconst [c] y)) && clobberIfDead(x) => (MVNshiftLL [c] y) 1621 (MVN x:(SRLconst [c] y)) && clobberIfDead(x) => (MVNshiftRL [c] y) 1622 (MVN x:(SRAconst [c] y)) && clobberIfDead(x) => (MVNshiftRA [c] y) 1623 (MVN x:(RORconst [c] y)) && clobberIfDead(x) => (MVNshiftRO [c] y) 1624 (ADD x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ADDshiftLL x0 y [c]) 1625 (ADD x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ADDshiftRL x0 y [c]) 1626 (ADD x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ADDshiftRA x0 y [c]) 1627 (SUB x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (SUBshiftLL x0 y [c]) 1628 (SUB x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (SUBshiftRL x0 y [c]) 1629 (SUB x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (SUBshiftRA x0 y [c]) 1630 (AND x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ANDshiftLL x0 y [c]) 1631 (AND x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ANDshiftRL x0 y [c]) 1632 (AND x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ANDshiftRA x0 y [c]) 1633 (AND x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ANDshiftRO x0 y [c]) 1634 (OR x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ORshiftLL x0 y [c]) // useful for combined load 1635 (OR x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ORshiftRL x0 y [c]) 1636 (OR x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ORshiftRA x0 y [c]) 1637 (OR x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ORshiftRO x0 y [c]) 1638 (XOR x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (XORshiftLL x0 y [c]) 1639 (XOR x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (XORshiftRL x0 y [c]) 1640 (XOR x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (XORshiftRA x0 y [c]) 1641 (XOR x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (XORshiftRO x0 y [c]) 1642 (BIC x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (BICshiftLL x0 y [c]) 1643 (BIC x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (BICshiftRL x0 y [c]) 1644 (BIC x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (BICshiftRA x0 y [c]) 1645 (BIC x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (BICshiftRO x0 y [c]) 1646 (ORN x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ORNshiftLL x0 y [c]) 1647 (ORN x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ORNshiftRL x0 y [c]) 1648 (ORN x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ORNshiftRA x0 y [c]) 1649 (ORN x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ORNshiftRO x0 y [c]) 1650 (EON x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (EONshiftLL x0 y [c]) 1651 (EON x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (EONshiftRL x0 y [c]) 1652 (EON x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (EONshiftRA x0 y [c]) 1653 (EON x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (EONshiftRO x0 y [c]) 1654 (CMP x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (CMPshiftLL x0 y [c]) 1655 (CMP x0:(SLLconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftLL x1 y [c])) 1656 (CMP x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (CMPshiftRL x0 y [c]) 1657 (CMP x0:(SRLconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftRL x1 y [c])) 1658 (CMP x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (CMPshiftRA x0 y [c]) 1659 (CMP x0:(SRAconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftRA x1 y [c])) 1660 (CMN x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (CMNshiftLL x0 y [c]) 1661 (CMN x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (CMNshiftRL x0 y [c]) 1662 (CMN x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (CMNshiftRA x0 y [c]) 1663 (TST x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (TSTshiftLL x0 y [c]) 1664 (TST x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (TSTshiftRL x0 y [c]) 1665 (TST x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (TSTshiftRA x0 y [c]) 1666 (TST x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (TSTshiftRO x0 y [c]) 1667 1668 // prefer *const ops to *shift ops 1669 (ADDshiftLL (MOVDconst [c]) x [d]) => (ADDconst [c] (SLLconst <x.Type> x [d])) 1670 (ADDshiftRL (MOVDconst [c]) x [d]) => (ADDconst [c] (SRLconst <x.Type> x [d])) 1671 (ADDshiftRA (MOVDconst [c]) x [d]) => (ADDconst [c] (SRAconst <x.Type> x [d])) 1672 (ANDshiftLL (MOVDconst [c]) x [d]) => (ANDconst [c] (SLLconst <x.Type> x [d])) 1673 (ANDshiftRL (MOVDconst [c]) x [d]) => (ANDconst [c] (SRLconst <x.Type> x [d])) 1674 (ANDshiftRA (MOVDconst [c]) x [d]) => (ANDconst [c] (SRAconst <x.Type> x [d])) 1675 (ANDshiftRO (MOVDconst [c]) x [d]) => (ANDconst [c] (RORconst <x.Type> x [d])) 1676 (ORshiftLL (MOVDconst [c]) x [d]) => (ORconst [c] (SLLconst <x.Type> x [d])) 1677 (ORshiftRL (MOVDconst [c]) x [d]) => (ORconst [c] (SRLconst <x.Type> x [d])) 1678 (ORshiftRA (MOVDconst [c]) x [d]) => (ORconst [c] (SRAconst <x.Type> x [d])) 1679 (ORshiftRO (MOVDconst [c]) x [d]) => (ORconst [c] (RORconst <x.Type> x [d])) 1680 (XORshiftLL (MOVDconst [c]) x [d]) => (XORconst [c] (SLLconst <x.Type> x [d])) 1681 (XORshiftRL (MOVDconst [c]) x [d]) => (XORconst [c] (SRLconst <x.Type> x [d])) 1682 (XORshiftRA (MOVDconst [c]) x [d]) => (XORconst [c] (SRAconst <x.Type> x [d])) 1683 (XORshiftRO (MOVDconst [c]) x [d]) => (XORconst [c] (RORconst <x.Type> x [d])) 1684 (CMPshiftLL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d]))) 1685 (CMPshiftRL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d]))) 1686 (CMPshiftRA (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d]))) 1687 (CMNshiftLL (MOVDconst [c]) x [d]) => (CMNconst [c] (SLLconst <x.Type> x [d])) 1688 (CMNshiftRL (MOVDconst [c]) x [d]) => (CMNconst [c] (SRLconst <x.Type> x [d])) 1689 (CMNshiftRA (MOVDconst [c]) x [d]) => (CMNconst [c] (SRAconst <x.Type> x [d])) 1690 (TSTshiftLL (MOVDconst [c]) x [d]) => (TSTconst [c] (SLLconst <x.Type> x [d])) 1691 (TSTshiftRL (MOVDconst [c]) x [d]) => (TSTconst [c] (SRLconst <x.Type> x [d])) 1692 (TSTshiftRA (MOVDconst [c]) x [d]) => (TSTconst [c] (SRAconst <x.Type> x [d])) 1693 (TSTshiftRO (MOVDconst [c]) x [d]) => (TSTconst [c] (RORconst <x.Type> x [d])) 1694 1695 // constant folding in *shift ops 1696 (MVNshiftLL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)<<uint64(d))]) 1697 (MVNshiftRL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)>>uint64(d))]) 1698 (MVNshiftRA (MOVDconst [c]) [d]) => (MOVDconst [^(c>>uint64(d))]) 1699 (MVNshiftRO (MOVDconst [c]) [d]) => (MOVDconst [^rotateRight64(c, d)]) 1700 (NEGshiftLL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)<<uint64(d))]) 1701 (NEGshiftRL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)>>uint64(d))]) 1702 (NEGshiftRA (MOVDconst [c]) [d]) => (MOVDconst [-(c>>uint64(d))]) 1703 (ADDshiftLL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)<<uint64(d))]) 1704 (ADDshiftRL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)>>uint64(d))]) 1705 (ADDshiftRA x (MOVDconst [c]) [d]) => (ADDconst x [c>>uint64(d)]) 1706 (SUBshiftLL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)<<uint64(d))]) 1707 (SUBshiftRL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)>>uint64(d))]) 1708 (SUBshiftRA x (MOVDconst [c]) [d]) => (SUBconst x [c>>uint64(d)]) 1709 (ANDshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)<<uint64(d))]) 1710 (ANDshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)>>uint64(d))]) 1711 (ANDshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [c>>uint64(d)]) 1712 (ANDshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [rotateRight64(c, d)]) 1713 (ORshiftLL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)<<uint64(d))]) 1714 (ORshiftRL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)>>uint64(d))]) 1715 (ORshiftRA x (MOVDconst [c]) [d]) => (ORconst x [c>>uint64(d)]) 1716 (ORshiftRO x (MOVDconst [c]) [d]) => (ORconst x [rotateRight64(c, d)]) 1717 (XORshiftLL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)<<uint64(d))]) 1718 (XORshiftRL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)>>uint64(d))]) 1719 (XORshiftRA x (MOVDconst [c]) [d]) => (XORconst x [c>>uint64(d)]) 1720 (XORshiftRO x (MOVDconst [c]) [d]) => (XORconst x [rotateRight64(c, d)]) 1721 (BICshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)<<uint64(d))]) 1722 (BICshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)>>uint64(d))]) 1723 (BICshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [^(c>>uint64(d))]) 1724 (BICshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [^rotateRight64(c, d)]) 1725 (ORNshiftLL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)<<uint64(d))]) 1726 (ORNshiftRL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)>>uint64(d))]) 1727 (ORNshiftRA x (MOVDconst [c]) [d]) => (ORconst x [^(c>>uint64(d))]) 1728 (ORNshiftRO x (MOVDconst [c]) [d]) => (ORconst x [^rotateRight64(c, d)]) 1729 (EONshiftLL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)<<uint64(d))]) 1730 (EONshiftRL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)>>uint64(d))]) 1731 (EONshiftRA x (MOVDconst [c]) [d]) => (XORconst x [^(c>>uint64(d))]) 1732 (EONshiftRO x (MOVDconst [c]) [d]) => (XORconst x [^rotateRight64(c, d)]) 1733 (CMPshiftLL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)<<uint64(d))]) 1734 (CMPshiftRL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)>>uint64(d))]) 1735 (CMPshiftRA x (MOVDconst [c]) [d]) => (CMPconst x [c>>uint64(d)]) 1736 (CMNshiftLL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)<<uint64(d))]) 1737 (CMNshiftRL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)>>uint64(d))]) 1738 (CMNshiftRA x (MOVDconst [c]) [d]) => (CMNconst x [c>>uint64(d)]) 1739 (TSTshiftLL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)<<uint64(d))]) 1740 (TSTshiftRL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)>>uint64(d))]) 1741 (TSTshiftRA x (MOVDconst [c]) [d]) => (TSTconst x [c>>uint64(d)]) 1742 (TSTshiftRO x (MOVDconst [c]) [d]) => (TSTconst x [rotateRight64(c, d)]) 1743 1744 // simplification with *shift ops 1745 (SUBshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0]) 1746 (SUBshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0]) 1747 (SUBshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0]) 1748 (ANDshiftLL y:(SLLconst x [c]) x [c]) => y 1749 (ANDshiftRL y:(SRLconst x [c]) x [c]) => y 1750 (ANDshiftRA y:(SRAconst x [c]) x [c]) => y 1751 (ANDshiftRO y:(RORconst x [c]) x [c]) => y 1752 (ORshiftLL y:(SLLconst x [c]) x [c]) => y 1753 (ORshiftRL y:(SRLconst x [c]) x [c]) => y 1754 (ORshiftRA y:(SRAconst x [c]) x [c]) => y 1755 (ORshiftRO y:(RORconst x [c]) x [c]) => y 1756 (XORshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0]) 1757 (XORshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0]) 1758 (XORshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0]) 1759 (XORshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0]) 1760 (BICshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0]) 1761 (BICshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0]) 1762 (BICshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0]) 1763 (BICshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0]) 1764 (EONshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1]) 1765 (EONshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1]) 1766 (EONshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1]) 1767 (EONshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1]) 1768 (ORNshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1]) 1769 (ORNshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1]) 1770 (ORNshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1]) 1771 (ORNshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1]) 1772 1773 // rev16w | rev16 1774 // ((x>>8) | (x<<8)) => (REV16W x), the type of x is uint16, "|" can also be "^" or "+". 1775 ((ADDshiftLL|ORshiftLL|XORshiftLL) <typ.UInt16> [8] (UBFX <typ.UInt16> [armBFAuxInt(8, 8)] x) x) => (REV16W x) 1776 1777 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+". 1778 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x)) 1779 && uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff 1780 => (REV16W x) 1781 1782 // ((x & 0xff00ff00ff00ff00)>>8) | ((x & 0x00ff00ff00ff00ff)<<8), "|" can also be "^" or "+". 1783 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) 1784 && (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff) 1785 => (REV16 x) 1786 1787 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+". 1788 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x)) 1789 && (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff) 1790 => (REV16 (ANDconst <x.Type> [0xffffffff] x)) 1791 1792 // Extract from reg pair 1793 (ADDshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x) 1794 ( ORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x) 1795 (XORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x) 1796 1797 (ADDshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) 1798 => (EXTRWconst [32-c] x2 x) 1799 ( ORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) 1800 => (EXTRWconst [32-c] x2 x) 1801 (XORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c) 1802 => (EXTRWconst [32-c] x2 x) 1803 1804 // Rewrite special pairs of shifts to AND. 1805 // On ARM64 the bitmask can fit into an instruction. 1806 (SRLconst [c] (SLLconst [c] x)) && 0 < c && c < 64 => (ANDconst [1<<uint(64-c)-1] x) // mask out high bits 1807 (SLLconst [c] (SRLconst [c] x)) && 0 < c && c < 64 => (ANDconst [^(1<<uint(c)-1)] x) // mask out low bits 1808 1809 // Special case setting bit as 1. An example is math.Copysign(c,-1) 1810 (ORconst [c1] (ANDconst [c2] x)) && c2|c1 == ^0 => (ORconst [c1] x) 1811 1812 // If the shift amount is larger than the datasize(32, 16, 8), we can optimize to constant 0. 1813 (MOVWUreg (SLLconst [lc] x)) && lc >= 32 => (MOVDconst [0]) 1814 (MOVHUreg (SLLconst [lc] x)) && lc >= 16 => (MOVDconst [0]) 1815 (MOVBUreg (SLLconst [lc] x)) && lc >= 8 => (MOVDconst [0]) 1816 1817 // After zero extension, the upper (64-datasize(32|16|8)) bits are zero, we can optimiza to constant 0. 1818 (SRLconst [rc] (MOVWUreg x)) && rc >= 32 => (MOVDconst [0]) 1819 (SRLconst [rc] (MOVHUreg x)) && rc >= 16 => (MOVDconst [0]) 1820 (SRLconst [rc] (MOVBUreg x)) && rc >= 8 => (MOVDconst [0]) 1821 1822 // bitfield ops 1823 1824 // sbfiz 1825 // (x << lc) >> rc 1826 (SRAconst [rc] (SLLconst [lc] x)) && lc > rc => (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) 1827 // int64(x << lc) 1828 (MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [armBFAuxInt(lc, 32-lc)] x) 1829 (MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [armBFAuxInt(lc, 16-lc)] x) 1830 (MOVBreg (SLLconst [lc] x)) && lc < 8 => (SBFIZ [armBFAuxInt(lc, 8-lc)] x) 1831 // int64(x) << lc 1832 (SLLconst [lc] (MOVWreg x)) => (SBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x) 1833 (SLLconst [lc] (MOVHreg x)) => (SBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x) 1834 (SLLconst [lc] (MOVBreg x)) => (SBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x) 1835 1836 // sbfx 1837 // (x << lc) >> rc 1838 (SRAconst [rc] (SLLconst [lc] x)) && lc <= rc => (SBFX [armBFAuxInt(rc-lc, 64-rc)] x) 1839 // int64(x) >> rc 1840 (SRAconst [rc] (MOVWreg x)) && rc < 32 => (SBFX [armBFAuxInt(rc, 32-rc)] x) 1841 (SRAconst [rc] (MOVHreg x)) && rc < 16 => (SBFX [armBFAuxInt(rc, 16-rc)] x) 1842 (SRAconst [rc] (MOVBreg x)) && rc < 8 => (SBFX [armBFAuxInt(rc, 8-rc)] x) 1843 // merge sbfx and sign-extension into sbfx 1844 (MOVWreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <= 32 => (SBFX [bfc] x) 1845 (MOVHreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <= 16 => (SBFX [bfc] x) 1846 (MOVBreg (SBFX [bfc] x)) && bfc.getARM64BFwidth() <= 8 => (SBFX [bfc] x) 1847 1848 // sbfiz/sbfx combinations: merge shifts into bitfield ops 1849 (SRAconst [sc] (SBFIZ [bfc] x)) && sc < bfc.getARM64BFlsb() 1850 => (SBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) 1851 (SRAconst [sc] (SBFIZ [bfc] x)) && sc >= bfc.getARM64BFlsb() 1852 && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() 1853 => (SBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) 1854 1855 // ubfiz 1856 // (x << lc) >> rc 1857 (SRLconst [rc] (SLLconst [lc] x)) && lc > rc => (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) 1858 // uint64(x) << lc 1859 (SLLconst [lc] (MOVWUreg x)) => (UBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x) 1860 (SLLconst [lc] (MOVHUreg x)) => (UBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x) 1861 (SLLconst [lc] (MOVBUreg x)) => (UBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x) 1862 // uint64(x << lc) 1863 (MOVWUreg (SLLconst [lc] x)) && lc < 32 => (UBFIZ [armBFAuxInt(lc, 32-lc)] x) 1864 (MOVHUreg (SLLconst [lc] x)) && lc < 16 => (UBFIZ [armBFAuxInt(lc, 16-lc)] x) 1865 (MOVBUreg (SLLconst [lc] x)) && lc < 8 => (UBFIZ [armBFAuxInt(lc, 8-lc)] x) 1866 1867 // merge ANDconst into ubfiz 1868 // (x & ac) << sc 1869 (SLLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, 0) 1870 => (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) 1871 // (x << sc) & ac 1872 (ANDconst [ac] (SLLconst [sc] x)) && isARM64BFMask(sc, ac, sc) 1873 => (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) 1874 1875 // ubfx 1876 // (x << lc) >> rc 1877 (SRLconst [rc] (SLLconst [lc] x)) && lc < rc => (UBFX [armBFAuxInt(rc-lc, 64-rc)] x) 1878 // uint64(x) >> rc 1879 (SRLconst [rc] (MOVWUreg x)) && rc < 32 => (UBFX [armBFAuxInt(rc, 32-rc)] x) 1880 (SRLconst [rc] (MOVHUreg x)) && rc < 16 => (UBFX [armBFAuxInt(rc, 16-rc)] x) 1881 (SRLconst [rc] (MOVBUreg x)) && rc < 8 => (UBFX [armBFAuxInt(rc, 8-rc)] x) 1882 // uint64(x >> rc) 1883 (MOVWUreg (SRLconst [rc] x)) && rc < 32 => (UBFX [armBFAuxInt(rc, 32)] x) 1884 (MOVHUreg (SRLconst [rc] x)) && rc < 16 => (UBFX [armBFAuxInt(rc, 16)] x) 1885 (MOVBUreg (SRLconst [rc] x)) && rc < 8 => (UBFX [armBFAuxInt(rc, 8)] x) 1886 // merge ANDconst into ubfx 1887 // (x >> sc) & ac 1888 (ANDconst [ac] (SRLconst [sc] x)) && isARM64BFMask(sc, ac, 0) 1889 => (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x) 1890 // (x & ac) >> sc 1891 (SRLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, sc) 1892 => (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x) 1893 // merge ANDconst and ubfx into ubfx 1894 (ANDconst [c] (UBFX [bfc] x)) && isARM64BFMask(0, c, 0) => 1895 (UBFX [armBFAuxInt(bfc.getARM64BFlsb(), min(bfc.getARM64BFwidth(), arm64BFWidth(c, 0)))] x) 1896 (UBFX [bfc] (ANDconst [c] x)) && isARM64BFMask(0, c, 0) && bfc.getARM64BFlsb() + bfc.getARM64BFwidth() <= arm64BFWidth(c, 0) => 1897 (UBFX [bfc] x) 1898 // merge ubfx and zerso-extension into ubfx 1899 (MOVWUreg (UBFX [bfc] x)) && bfc.getARM64BFwidth() <= 32 => (UBFX [bfc] x) 1900 (MOVHUreg (UBFX [bfc] x)) && bfc.getARM64BFwidth() <= 16 => (UBFX [bfc] x) 1901 (MOVBUreg (UBFX [bfc] x)) && bfc.getARM64BFwidth() <= 8 => (UBFX [bfc] x) 1902 1903 // ubfiz/ubfx combinations: merge shifts into bitfield ops 1904 (SRLconst [sc] (UBFX [bfc] x)) && sc < bfc.getARM64BFwidth() 1905 => (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) 1906 (UBFX [bfc] (SRLconst [sc] x)) && sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 1907 => (UBFX [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) 1908 (SLLconst [sc] (UBFIZ [bfc] x)) && sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 1909 => (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) 1910 (UBFIZ [bfc] (SLLconst [sc] x)) && sc < bfc.getARM64BFwidth() 1911 => (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth()-sc)] x) 1912 // ((x << c1) >> c2) >> c3 1913 (SRLconst [sc] (UBFIZ [bfc] x)) && sc == bfc.getARM64BFlsb() 1914 => (ANDconst [1<<uint(bfc.getARM64BFwidth())-1] x) 1915 (SRLconst [sc] (UBFIZ [bfc] x)) && sc < bfc.getARM64BFlsb() 1916 => (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) 1917 (SRLconst [sc] (UBFIZ [bfc] x)) && sc > bfc.getARM64BFlsb() 1918 && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() 1919 => (UBFX [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) 1920 // ((x << c1) << c2) >> c3 1921 (UBFX [bfc] (SLLconst [sc] x)) && sc == bfc.getARM64BFlsb() 1922 => (ANDconst [1<<uint(bfc.getARM64BFwidth())-1] x) 1923 (UBFX [bfc] (SLLconst [sc] x)) && sc < bfc.getARM64BFlsb() 1924 => (UBFX [armBFAuxInt(bfc.getARM64BFlsb()-sc, bfc.getARM64BFwidth())] x) 1925 (UBFX [bfc] (SLLconst [sc] x)) && sc > bfc.getARM64BFlsb() 1926 && sc < bfc.getARM64BFlsb()+bfc.getARM64BFwidth() 1927 => (UBFIZ [armBFAuxInt(sc-bfc.getARM64BFlsb(), bfc.getARM64BFlsb()+bfc.getARM64BFwidth()-sc)] x) 1928 1929 // bfi 1930 (OR (UBFIZ [bfc] x) (ANDconst [ac] y)) 1931 && ac == ^((1<<uint(bfc.getARM64BFwidth())-1) << uint(bfc.getARM64BFlsb())) 1932 => (BFI [bfc] y x) 1933 (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y)) 1934 && lc > rc && ac == ^((1<<uint(64-lc)-1) << uint64(lc-rc)) 1935 => (BFI [armBFAuxInt(lc-rc, 64-lc)] x y) 1936 // bfxil 1937 (OR (UBFX [bfc] x) (ANDconst [ac] y)) && ac == ^(1<<uint(bfc.getARM64BFwidth())-1) 1938 => (BFXIL [bfc] y x) 1939 (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) && sc == bfc.getARM64BFwidth() 1940 => (BFXIL [bfc] y x) 1941 (ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x)) && lc < rc && ac == ^((1<<uint(64-rc)-1)) 1942 => (BFXIL [armBFAuxInt(rc-lc, 64-rc)] y x) 1943 1944 // FP simplification 1945 (FNEGS (FMULS x y)) => (FNMULS x y) 1946 (FNEGD (FMULD x y)) => (FNMULD x y) 1947 (FMULS (FNEGS x) y) => (FNMULS x y) 1948 (FMULD (FNEGD x) y) => (FNMULD x y) 1949 (FNEGS (FNMULS x y)) => (FMULS x y) 1950 (FNEGD (FNMULD x y)) => (FMULD x y) 1951 (FNMULS (FNEGS x) y) => (FMULS x y) 1952 (FNMULD (FNEGD x) y) => (FMULD x y) 1953 1954 (FADDS a (FMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS a x y) 1955 (FADDD a (FMULD x y)) && a.Block.Func.useFMA(v) => (FMADDD a x y) 1956 (FSUBS a (FMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS a x y) 1957 (FSUBD a (FMULD x y)) && a.Block.Func.useFMA(v) => (FMSUBD a x y) 1958 (FSUBS (FMULS x y) a) && a.Block.Func.useFMA(v) => (FNMSUBS a x y) 1959 (FSUBD (FMULD x y) a) && a.Block.Func.useFMA(v) => (FNMSUBD a x y) 1960 (FADDS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS a x y) 1961 (FADDD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMSUBD a x y) 1962 (FSUBS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS a x y) 1963 (FSUBD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMADDD a x y) 1964 (FSUBS (FNMULS x y) a) && a.Block.Func.useFMA(v) => (FNMADDS a x y) 1965 (FSUBD (FNMULD x y) a) && a.Block.Func.useFMA(v) => (FNMADDD a x y) 1966 1967 (MOVBUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read8(sym, int64(off)))]) 1968 (MOVHUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))]) 1969 (MOVWUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))]) 1970 (MOVDload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))]) 1971 1972 // Prefetch instructions (aux is option: 0 - PLDL1KEEP; 1 - PLDL1STRM) 1973 (PrefetchCache addr mem) => (PRFM [0] addr mem) 1974 (PrefetchCacheStreamed addr mem) => (PRFM [1] addr mem) 1975 1976 // Arch-specific inlining for small or disjoint runtime.memmove 1977 (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem))))) 1978 && sz >= 0 1979 && isSameCall(sym, "runtime.memmove") 1980 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 1981 && isInlinableMemmove(dst, src, sz, config) 1982 && clobber(s1, s2, s3, call) 1983 => (Move [sz] dst src mem) 1984 1985 // Match post-lowering calls, register version. 1986 (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem)) 1987 && sz >= 0 1988 && isSameCall(sym, "runtime.memmove") 1989 && call.Uses == 1 1990 && isInlinableMemmove(dst, src, sz, config) 1991 && clobber(call) 1992 => (Move [sz] dst src mem) 1993 1994 ((REV|REVW) ((REV|REVW) p)) => p 1995 1996 // runtime/internal/math.MulUintptr intrinsics 1997 1998 (Select0 (Mul64uover x y)) => (MUL x y) 1999 (Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH <typ.UInt64> x y) [0]))