github.com/bir3/gocompiler@v0.9.2202/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "github.com/bir3/gocompiler/src/cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32 83 REG_CR0LT 84 REG_CR0GT 85 REG_CR0EQ 86 REG_CR0SO 87 REG_CR1LT 88 REG_CR1GT 89 REG_CR1EQ 90 REG_CR1SO 91 REG_CR2LT 92 REG_CR2GT 93 REG_CR2EQ 94 REG_CR2SO 95 REG_CR3LT 96 REG_CR3GT 97 REG_CR3EQ 98 REG_CR3SO 99 REG_CR4LT 100 REG_CR4GT 101 REG_CR4EQ 102 REG_CR4SO 103 REG_CR5LT 104 REG_CR5GT 105 REG_CR5EQ 106 REG_CR5SO 107 REG_CR6LT 108 REG_CR6GT 109 REG_CR6EQ 110 REG_CR6SO 111 REG_CR7LT 112 REG_CR7GT 113 REG_CR7EQ 114 REG_CR7SO 115 116 /* Align FPR and VSR vectors such that when masked with 0x3F they produce 117 an equivalent VSX register. */ 118 /* F0=4160 ... F31=4191 */ 119 REG_F0 120 REG_F1 121 REG_F2 122 REG_F3 123 REG_F4 124 REG_F5 125 REG_F6 126 REG_F7 127 REG_F8 128 REG_F9 129 REG_F10 130 REG_F11 131 REG_F12 132 REG_F13 133 REG_F14 134 REG_F15 135 REG_F16 136 REG_F17 137 REG_F18 138 REG_F19 139 REG_F20 140 REG_F21 141 REG_F22 142 REG_F23 143 REG_F24 144 REG_F25 145 REG_F26 146 REG_F27 147 REG_F28 148 REG_F29 149 REG_F30 150 REG_F31 151 152 /* V0=4192 ... V31=4223 */ 153 REG_V0 154 REG_V1 155 REG_V2 156 REG_V3 157 REG_V4 158 REG_V5 159 REG_V6 160 REG_V7 161 REG_V8 162 REG_V9 163 REG_V10 164 REG_V11 165 REG_V12 166 REG_V13 167 REG_V14 168 REG_V15 169 REG_V16 170 REG_V17 171 REG_V18 172 REG_V19 173 REG_V20 174 REG_V21 175 REG_V22 176 REG_V23 177 REG_V24 178 REG_V25 179 REG_V26 180 REG_V27 181 REG_V28 182 REG_V29 183 REG_V30 184 REG_V31 185 186 /* VS0=4224 ... VS63=4287 */ 187 REG_VS0 188 REG_VS1 189 REG_VS2 190 REG_VS3 191 REG_VS4 192 REG_VS5 193 REG_VS6 194 REG_VS7 195 REG_VS8 196 REG_VS9 197 REG_VS10 198 REG_VS11 199 REG_VS12 200 REG_VS13 201 REG_VS14 202 REG_VS15 203 REG_VS16 204 REG_VS17 205 REG_VS18 206 REG_VS19 207 REG_VS20 208 REG_VS21 209 REG_VS22 210 REG_VS23 211 REG_VS24 212 REG_VS25 213 REG_VS26 214 REG_VS27 215 REG_VS28 216 REG_VS29 217 REG_VS30 218 REG_VS31 219 REG_VS32 220 REG_VS33 221 REG_VS34 222 REG_VS35 223 REG_VS36 224 REG_VS37 225 REG_VS38 226 REG_VS39 227 REG_VS40 228 REG_VS41 229 REG_VS42 230 REG_VS43 231 REG_VS44 232 REG_VS45 233 REG_VS46 234 REG_VS47 235 REG_VS48 236 REG_VS49 237 REG_VS50 238 REG_VS51 239 REG_VS52 240 REG_VS53 241 REG_VS54 242 REG_VS55 243 REG_VS56 244 REG_VS57 245 REG_VS58 246 REG_VS59 247 REG_VS60 248 REG_VS61 249 REG_VS62 250 REG_VS63 251 252 REG_CR0 253 REG_CR1 254 REG_CR2 255 REG_CR3 256 REG_CR4 257 REG_CR5 258 REG_CR6 259 REG_CR7 260 261 // MMA accumulator registers, these shadow VSR 0-31 262 // e.g MMAx shadows VSRx*4-VSRx*4+3 or 263 // MMA0 shadows VSR0-VSR3 264 REG_A0 265 REG_A1 266 REG_A2 267 REG_A3 268 REG_A4 269 REG_A5 270 REG_A6 271 REG_A7 272 273 REG_MSR 274 REG_FPSCR 275 REG_CR 276 277 REG_SPECIAL = REG_CR0 278 279 REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0 280 281 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 282 283 REG_XER = REG_SPR0 + 1 284 REG_LR = REG_SPR0 + 8 285 REG_CTR = REG_SPR0 + 9 286 287 REGZERO = REG_R0 /* set to zero */ 288 REGSP = REG_R1 289 REGSB = REG_R2 290 REGRET = REG_R3 291 REGARG = -1 /* -1 disables passing the first argument in register */ 292 REGRT1 = REG_R20 /* reserved for runtime, duffzero and duffcopy */ 293 REGRT2 = REG_R21 /* reserved for runtime, duffcopy */ 294 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 295 REGCTXT = REG_R11 /* context for closures */ 296 REGTLS = REG_R13 /* C ABI TLS base pointer */ 297 REGMAX = REG_R27 298 REGEXT = REG_R30 /* external registers allocated from here down */ 299 REGG = REG_R30 /* G */ 300 REGTMP = REG_R31 /* used by the linker */ 301 FREGRET = REG_F0 302 FREGMIN = REG_F17 /* first register variable */ 303 FREGMAX = REG_F26 /* last register variable for 9g only */ 304 FREGEXT = REG_F26 /* first external register */ 305 ) 306 307 // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI 308 // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 309 var PPC64DWARFRegisters = map[int16]int16{} 310 311 func init() { 312 // f assigns dwarfregister[from:to] = (base):(to-from+base) 313 f := func(from, to, base int16) { 314 for r := int16(from); r <= to; r++ { 315 PPC64DWARFRegisters[r] = r - from + base 316 } 317 } 318 f(REG_R0, REG_R31, 0) 319 f(REG_F0, REG_F31, 32) 320 f(REG_V0, REG_V31, 77) 321 f(REG_CR0, REG_CR7, 68) 322 323 f(REG_VS0, REG_VS31, 32) // overlaps F0-F31 324 f(REG_VS32, REG_VS63, 77) // overlaps V0-V31 325 PPC64DWARFRegisters[REG_LR] = 65 326 PPC64DWARFRegisters[REG_CTR] = 66 327 PPC64DWARFRegisters[REG_XER] = 76 328 } 329 330 /* 331 * GENERAL: 332 * 333 * compiler allocates R3 up as temps 334 * compiler allocates register variables R7-R27 335 * compiler allocates external registers R30 down 336 * 337 * compiler allocates register variables F17-F26 338 * compiler allocates external registers F26 down 339 */ 340 const ( 341 BIG = 32768 - 8 342 ) 343 344 const ( 345 /* mark flags */ 346 LABEL = 1 << 0 347 LEAF = 1 << 1 348 FLOAT = 1 << 2 349 BRANCH = 1 << 3 350 LOAD = 1 << 4 351 FCMP = 1 << 5 352 SYNC = 1 << 6 353 LIST = 1 << 7 354 FOLL = 1 << 8 355 NOSCHED = 1 << 9 356 PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary 357 ) 358 359 // Values for use in branch instruction BC 360 // BC B0,BI,label 361 // BO is type of branch + likely bits described below 362 // BI is CR value + branch type 363 // ex: BEQ CR2,label is BC 12,10,label 364 // 12 = BO_BCR 365 // 10 = BI_CR2 + BI_EQ 366 367 const ( 368 BI_CR0 = 0 369 BI_CR1 = 4 370 BI_CR2 = 8 371 BI_CR3 = 12 372 BI_CR4 = 16 373 BI_CR5 = 20 374 BI_CR6 = 24 375 BI_CR7 = 28 376 BI_LT = 0 377 BI_GT = 1 378 BI_EQ = 2 379 BI_FU = 3 380 ) 381 382 // Common values for the BO field. 383 384 const ( 385 BO_ALWAYS = 20 // branch unconditionally 386 BO_BCTR = 16 // decrement ctr, branch on ctr != 0 387 BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0 388 BO_BCR = 12 // branch on cr value 389 BO_BCRBCTR = 8 // decrement ctr, branch on ctr != 0 and cr value 390 BO_NOTBCR = 4 // branch on not cr value 391 ) 392 393 // Bit settings from the CR 394 395 const ( 396 C_COND_LT = iota // 0 result is negative 397 C_COND_GT // 1 result is positive 398 C_COND_EQ // 2 result is zero 399 C_COND_SO // 3 summary overflow or FP compare w/ NaN 400 ) 401 402 const ( 403 C_NONE = iota 404 C_REGP /* An even numbered gpr which can be used a gpr pair argument */ 405 C_REG /* Any gpr register */ 406 C_FREGP /* An even numbered fpr which can be used a fpr pair argument */ 407 C_FREG /* Any fpr register */ 408 C_VREG /* Any vector register */ 409 C_VSREGP /* An even numbered vsx register which can be used as a vsx register pair argument */ 410 C_VSREG /* Any vector-scalar register */ 411 C_CREG /* The condition registor (CR) */ 412 C_CRBIT /* A single bit of the CR register (0-31) */ 413 C_SPR /* special processor register */ 414 C_AREG /* MMA accumulator register */ 415 C_ZCON /* The constant zero */ 416 C_U1CON /* 1 bit unsigned constant */ 417 C_U2CON /* 2 bit unsigned constant */ 418 C_U3CON /* 3 bit unsigned constant */ 419 C_U4CON /* 4 bit unsigned constant */ 420 C_U5CON /* 5 bit unsigned constant */ 421 C_U8CON /* 8 bit unsigned constant */ 422 C_U15CON /* 15 bit unsigned constant */ 423 C_S16CON /* 16 bit signed constant */ 424 C_U16CON /* 16 bit unsigned constant */ 425 C_32CON /* Any constant which fits into 32 bits. Can be signed or unsigned */ 426 C_S34CON /* 34 bit signed constant */ 427 C_64CON /* Any constant which fits into 64 bits. Can be signed or unsigned */ 428 C_SACON /* $n(REG) where n <= int16 */ 429 C_LACON /* $n(REG) where n <= int32 */ 430 C_DACON /* $n(REG) where n <= int64 */ 431 C_SBRA /* A short offset argument to a branching instruction */ 432 C_LBRA /* A long offset argument to a branching instruction */ 433 C_LBRAPIC /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */ 434 C_ZOREG /* An $0+reg memory op */ 435 C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */ 436 C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */ 437 C_XOREG /* An reg+reg memory arg */ 438 C_FPSCR /* The fpscr register */ 439 C_LR /* The link register */ 440 C_CTR /* The count register */ 441 C_ANY /* Any argument */ 442 C_GOK /* A non-matched argument */ 443 C_ADDR /* A symbolic memory location */ 444 C_TLS_LE /* A thread local, local-exec, type memory arg */ 445 C_TLS_IE /* A thread local, initial-exec, type memory arg */ 446 C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */ 447 448 C_NCLASS /* must be the last */ 449 450 /* Aliased names which should be cleaned up, or integrated. */ 451 C_SCON = C_U15CON 452 C_ADDCON = C_S16CON 453 C_ANDCON = C_U16CON 454 C_LCON = C_32CON 455 456 /* Aliased names which may be generated by ppc64map for the optab. */ 457 C_S32CON = C_32CON 458 C_U32CON = C_32CON 459 ) 460 461 const ( 462 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 463 AADDCC 464 AADDIS 465 AADDV 466 AADDVCC 467 AADDC 468 AADDCCC 469 AADDCV 470 AADDCVCC 471 AADDME 472 AADDMECC 473 AADDMEVCC 474 AADDMEV 475 AADDE 476 AADDECC 477 AADDEVCC 478 AADDEV 479 AADDZE 480 AADDZECC 481 AADDZEVCC 482 AADDZEV 483 AADDEX 484 AAND 485 AANDCC 486 AANDN 487 AANDNCC 488 AANDISCC 489 ABC 490 ABCL 491 ABEQ 492 ABGE // not LT = G/E/U 493 ABGT 494 ABLE // not GT = L/E/U 495 ABLT 496 ABNE // not EQ = L/G/U 497 ABVC // Branch if float not unordered (also branch on not summary overflow) 498 ABVS // Branch if float unordered (also branch on summary overflow) 499 ABDNZ // Decrement CTR, and branch if CTR != 0 500 ABDZ // Decrement CTR, and branch if CTR == 0 501 ACMP 502 ACMPU 503 ACMPEQB 504 ACNTLZW 505 ACNTLZWCC 506 ACRAND 507 ACRANDN 508 ACREQV 509 ACRNAND 510 ACRNOR 511 ACROR 512 ACRORN 513 ACRXOR 514 ADIVW 515 ADIVWCC 516 ADIVWVCC 517 ADIVWV 518 ADIVWU 519 ADIVWUCC 520 ADIVWUVCC 521 ADIVWUV 522 AMODUD 523 AMODUW 524 AMODSD 525 AMODSW 526 AEQV 527 AEQVCC 528 AEXTSB 529 AEXTSBCC 530 AEXTSH 531 AEXTSHCC 532 AFABS 533 AFABSCC 534 AFADD 535 AFADDCC 536 AFADDS 537 AFADDSCC 538 AFCMPO 539 AFCMPU 540 AFCTIW 541 AFCTIWCC 542 AFCTIWZ 543 AFCTIWZCC 544 AFDIV 545 AFDIVCC 546 AFDIVS 547 AFDIVSCC 548 AFMADD 549 AFMADDCC 550 AFMADDS 551 AFMADDSCC 552 AFMOVD 553 AFMOVDCC 554 AFMOVDU 555 AFMOVS 556 AFMOVSU 557 AFMOVSX 558 AFMOVSZ 559 AFMSUB 560 AFMSUBCC 561 AFMSUBS 562 AFMSUBSCC 563 AFMUL 564 AFMULCC 565 AFMULS 566 AFMULSCC 567 AFNABS 568 AFNABSCC 569 AFNEG 570 AFNEGCC 571 AFNMADD 572 AFNMADDCC 573 AFNMADDS 574 AFNMADDSCC 575 AFNMSUB 576 AFNMSUBCC 577 AFNMSUBS 578 AFNMSUBSCC 579 AFRSP 580 AFRSPCC 581 AFSUB 582 AFSUBCC 583 AFSUBS 584 AFSUBSCC 585 AISEL 586 AMOVMW 587 ALBAR 588 ALHAR 589 ALSW 590 ALWAR 591 ALWSYNC 592 AMOVDBR 593 AMOVWBR 594 AMOVB 595 AMOVBU 596 AMOVBZ 597 AMOVBZU 598 AMOVH 599 AMOVHBR 600 AMOVHU 601 AMOVHZ 602 AMOVHZU 603 AMOVW 604 AMOVWU 605 AMOVFL 606 AMOVCRFS 607 AMTFSB0 608 AMTFSB0CC 609 AMTFSB1 610 AMTFSB1CC 611 AMULHW 612 AMULHWCC 613 AMULHWU 614 AMULHWUCC 615 AMULLW 616 AMULLWCC 617 AMULLWVCC 618 AMULLWV 619 ANAND 620 ANANDCC 621 ANEG 622 ANEGCC 623 ANEGVCC 624 ANEGV 625 ANOR 626 ANORCC 627 AOR 628 AORCC 629 AORN 630 AORNCC 631 AORIS 632 AREM 633 AREMU 634 ARFI 635 ARLWMI 636 ARLWMICC 637 ARLWNM 638 ARLWNMCC 639 ACLRLSLWI 640 ASLW 641 ASLWCC 642 ASRW 643 ASRAW 644 ASRAWCC 645 ASRWCC 646 ASTBCCC 647 ASTHCCC 648 ASTSW 649 ASTWCCC 650 ASUB 651 ASUBCC 652 ASUBVCC 653 ASUBC 654 ASUBCCC 655 ASUBCV 656 ASUBCVCC 657 ASUBME 658 ASUBMECC 659 ASUBMEVCC 660 ASUBMEV 661 ASUBV 662 ASUBE 663 ASUBECC 664 ASUBEV 665 ASUBEVCC 666 ASUBZE 667 ASUBZECC 668 ASUBZEVCC 669 ASUBZEV 670 ASYNC 671 AXOR 672 AXORCC 673 AXORIS 674 675 ADCBF 676 ADCBI 677 ADCBST 678 ADCBT 679 ADCBTST 680 ADCBZ 681 AEIEIO 682 AICBI 683 AISYNC 684 APTESYNC 685 ATLBIE 686 ATLBIEL 687 ATLBSYNC 688 ATW 689 690 ASYSCALL 691 AWORD 692 693 ARFCI 694 695 AFCPSGN 696 AFCPSGNCC 697 /* optional on 32-bit */ 698 AFRES 699 AFRESCC 700 AFRIM 701 AFRIMCC 702 AFRIP 703 AFRIPCC 704 AFRIZ 705 AFRIZCC 706 AFRIN 707 AFRINCC 708 AFRSQRTE 709 AFRSQRTECC 710 AFSEL 711 AFSELCC 712 AFSQRT 713 AFSQRTCC 714 AFSQRTS 715 AFSQRTSCC 716 717 /* 64-bit */ 718 719 ACNTLZD 720 ACNTLZDCC 721 ACMPW /* CMP with L=0 */ 722 ACMPWU 723 ACMPB 724 AFTDIV 725 AFTSQRT 726 ADIVD 727 ADIVDCC 728 ADIVDE 729 ADIVDECC 730 ADIVDEU 731 ADIVDEUCC 732 ADIVDVCC 733 ADIVDV 734 ADIVDU 735 ADIVDUCC 736 ADIVDUVCC 737 ADIVDUV 738 AEXTSW 739 AEXTSWCC 740 /* AFCFIW; AFCFIWCC */ 741 AFCFID 742 AFCFIDCC 743 AFCFIDU 744 AFCFIDUCC 745 AFCFIDS 746 AFCFIDSCC 747 AFCTID 748 AFCTIDCC 749 AFCTIDZ 750 AFCTIDZCC 751 ALDAR 752 AMOVD 753 AMOVDU 754 AMOVWZ 755 AMOVWZU 756 AMULHD 757 AMULHDCC 758 AMULHDU 759 AMULHDUCC 760 AMULLD 761 AMULLDCC 762 AMULLDVCC 763 AMULLDV 764 ARFID 765 ARLDMI 766 ARLDMICC 767 ARLDIMI 768 ARLDIMICC 769 ARLDC 770 ARLDCCC 771 ARLDCR 772 ARLDCRCC 773 ARLDICR 774 ARLDICRCC 775 ARLDCL 776 ARLDCLCC 777 ARLDICL 778 ARLDICLCC 779 ARLDIC 780 ARLDICCC 781 ACLRLSLDI 782 AROTL 783 AROTLW 784 ASLBIA 785 ASLBIE 786 ASLBMFEE 787 ASLBMFEV 788 ASLBMTE 789 ASLD 790 ASLDCC 791 ASRD 792 ASRAD 793 ASRADCC 794 ASRDCC 795 AEXTSWSLI 796 AEXTSWSLICC 797 ASTDCCC 798 ATD 799 ASETB 800 801 /* 64-bit pseudo operation */ 802 ADWORD 803 AREMD 804 AREMDU 805 806 /* more 64-bit operations */ 807 AHRFID 808 APOPCNTD 809 APOPCNTW 810 APOPCNTB 811 ACNTTZW 812 ACNTTZWCC 813 ACNTTZD 814 ACNTTZDCC 815 ACOPY 816 APASTECC 817 ADARN 818 AMADDHD 819 AMADDHDU 820 AMADDLD 821 822 /* Vector */ 823 ALVEBX 824 ALVEHX 825 ALVEWX 826 ALVX 827 ALVXL 828 ALVSL 829 ALVSR 830 ASTVEBX 831 ASTVEHX 832 ASTVEWX 833 ASTVX 834 ASTVXL 835 AVAND 836 AVANDC 837 AVNAND 838 AVOR 839 AVORC 840 AVNOR 841 AVXOR 842 AVEQV 843 AVADDUM 844 AVADDUBM 845 AVADDUHM 846 AVADDUWM 847 AVADDUDM 848 AVADDUQM 849 AVADDCU 850 AVADDCUQ 851 AVADDCUW 852 AVADDUS 853 AVADDUBS 854 AVADDUHS 855 AVADDUWS 856 AVADDSS 857 AVADDSBS 858 AVADDSHS 859 AVADDSWS 860 AVADDE 861 AVADDEUQM 862 AVADDECUQ 863 AVSUBUM 864 AVSUBUBM 865 AVSUBUHM 866 AVSUBUWM 867 AVSUBUDM 868 AVSUBUQM 869 AVSUBCU 870 AVSUBCUQ 871 AVSUBCUW 872 AVSUBUS 873 AVSUBUBS 874 AVSUBUHS 875 AVSUBUWS 876 AVSUBSS 877 AVSUBSBS 878 AVSUBSHS 879 AVSUBSWS 880 AVSUBE 881 AVSUBEUQM 882 AVSUBECUQ 883 AVMULESB 884 AVMULOSB 885 AVMULEUB 886 AVMULOUB 887 AVMULESH 888 AVMULOSH 889 AVMULEUH 890 AVMULOUH 891 AVMULESW 892 AVMULOSW 893 AVMULEUW 894 AVMULOUW 895 AVMULUWM 896 AVPMSUM 897 AVPMSUMB 898 AVPMSUMH 899 AVPMSUMW 900 AVPMSUMD 901 AVMSUMUDM 902 AVR 903 AVRLB 904 AVRLH 905 AVRLW 906 AVRLD 907 AVS 908 AVSLB 909 AVSLH 910 AVSLW 911 AVSL 912 AVSLO 913 AVSRB 914 AVSRH 915 AVSRW 916 AVSR 917 AVSRO 918 AVSLD 919 AVSRD 920 AVSA 921 AVSRAB 922 AVSRAH 923 AVSRAW 924 AVSRAD 925 AVSOI 926 AVSLDOI 927 AVCLZ 928 AVCLZB 929 AVCLZH 930 AVCLZW 931 AVCLZD 932 AVPOPCNT 933 AVPOPCNTB 934 AVPOPCNTH 935 AVPOPCNTW 936 AVPOPCNTD 937 AVCMPEQ 938 AVCMPEQUB 939 AVCMPEQUBCC 940 AVCMPEQUH 941 AVCMPEQUHCC 942 AVCMPEQUW 943 AVCMPEQUWCC 944 AVCMPEQUD 945 AVCMPEQUDCC 946 AVCMPGT 947 AVCMPGTUB 948 AVCMPGTUBCC 949 AVCMPGTUH 950 AVCMPGTUHCC 951 AVCMPGTUW 952 AVCMPGTUWCC 953 AVCMPGTUD 954 AVCMPGTUDCC 955 AVCMPGTSB 956 AVCMPGTSBCC 957 AVCMPGTSH 958 AVCMPGTSHCC 959 AVCMPGTSW 960 AVCMPGTSWCC 961 AVCMPGTSD 962 AVCMPGTSDCC 963 AVCMPNEZB 964 AVCMPNEZBCC 965 AVCMPNEB 966 AVCMPNEBCC 967 AVCMPNEH 968 AVCMPNEHCC 969 AVCMPNEW 970 AVCMPNEWCC 971 AVPERM 972 AVPERMXOR 973 AVPERMR 974 AVBPERMQ 975 AVBPERMD 976 AVSEL 977 AVSPLTB 978 AVSPLTH 979 AVSPLTW 980 AVSPLTISB 981 AVSPLTISH 982 AVSPLTISW 983 AVCIPH 984 AVCIPHER 985 AVCIPHERLAST 986 AVNCIPH 987 AVNCIPHER 988 AVNCIPHERLAST 989 AVSBOX 990 AVSHASIGMA 991 AVSHASIGMAW 992 AVSHASIGMAD 993 AVMRGEW 994 AVMRGOW 995 AVCLZLSBB 996 AVCTZLSBB 997 998 /* VSX */ 999 ALXV 1000 ALXVL 1001 ALXVLL 1002 ALXVD2X 1003 ALXVW4X 1004 ALXVH8X 1005 ALXVB16X 1006 ALXVX 1007 ALXVDSX 1008 ASTXV 1009 ASTXVL 1010 ASTXVLL 1011 ASTXVD2X 1012 ASTXVW4X 1013 ASTXVH8X 1014 ASTXVB16X 1015 ASTXVX 1016 ALXSDX 1017 ASTXSDX 1018 ALXSIWAX 1019 ALXSIWZX 1020 ASTXSIWX 1021 AMFVSRD 1022 AMFFPRD 1023 AMFVRD 1024 AMFVSRWZ 1025 AMFVSRLD 1026 AMTVSRD 1027 AMTFPRD 1028 AMTVRD 1029 AMTVSRWA 1030 AMTVSRWZ 1031 AMTVSRDD 1032 AMTVSRWS 1033 AXXLAND 1034 AXXLANDC 1035 AXXLEQV 1036 AXXLNAND 1037 AXXLOR 1038 AXXLORC 1039 AXXLNOR 1040 AXXLORQ 1041 AXXLXOR 1042 AXXSEL 1043 AXXMRGHW 1044 AXXMRGLW 1045 AXXSPLTW 1046 AXXSPLTIB 1047 AXXPERM 1048 AXXPERMDI 1049 AXXSLDWI 1050 AXXBRQ 1051 AXXBRD 1052 AXXBRW 1053 AXXBRH 1054 AXSCVDPSP 1055 AXSCVSPDP 1056 AXSCVDPSPN 1057 AXSCVSPDPN 1058 AXVCVDPSP 1059 AXVCVSPDP 1060 AXSCVDPSXDS 1061 AXSCVDPSXWS 1062 AXSCVDPUXDS 1063 AXSCVDPUXWS 1064 AXSCVSXDDP 1065 AXSCVUXDDP 1066 AXSCVSXDSP 1067 AXSCVUXDSP 1068 AXVCVDPSXDS 1069 AXVCVDPSXWS 1070 AXVCVDPUXDS 1071 AXVCVDPUXWS 1072 AXVCVSPSXDS 1073 AXVCVSPSXWS 1074 AXVCVSPUXDS 1075 AXVCVSPUXWS 1076 AXVCVSXDDP 1077 AXVCVSXWDP 1078 AXVCVUXDDP 1079 AXVCVUXWDP 1080 AXVCVSXDSP 1081 AXVCVSXWSP 1082 AXVCVUXDSP 1083 AXVCVUXWSP 1084 ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map. 1085 1086 // aliases 1087 ABR = obj.AJMP 1088 ABL = obj.ACALL 1089 ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table. 1090 )