github.com/bir3/gocompiler@v0.9.2202/src/cmd/internal/obj/riscv/cpu.go (about) 1 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 2 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 3 // Portions Copyright © 1997-1999 Vita Nuova Limited 4 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 5 // Portions Copyright © 2004,2006 Bruce Ellis 6 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 7 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 8 // Portions Copyright © 2009 The Go Authors. All rights reserved. 9 // Portions Copyright © 2019 The Go Authors. All rights reserved. 10 // 11 // Permission is hereby granted, free of charge, to any person obtaining a copy 12 // of this software and associated documentation files (the "Software"), to deal 13 // in the Software without restriction, including without limitation the rights 14 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 // copies of the Software, and to permit persons to whom the Software is 16 // furnished to do so, subject to the following conditions: 17 // 18 // The above copyright notice and this permission notice shall be included in 19 // all copies or substantial portions of the Software. 20 // 21 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 24 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 // THE SOFTWARE. 28 29 package riscv 30 31 import "github.com/bir3/gocompiler/src/cmd/internal/obj" 32 33 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv 34 35 const ( 36 // Base register numberings. 37 REG_X0 = obj.RBaseRISCV + iota 38 REG_X1 39 REG_X2 40 REG_X3 41 REG_X4 42 REG_X5 43 REG_X6 44 REG_X7 45 REG_X8 46 REG_X9 47 REG_X10 48 REG_X11 49 REG_X12 50 REG_X13 51 REG_X14 52 REG_X15 53 REG_X16 54 REG_X17 55 REG_X18 56 REG_X19 57 REG_X20 58 REG_X21 59 REG_X22 60 REG_X23 61 REG_X24 62 REG_X25 63 REG_X26 64 REG_X27 65 REG_X28 66 REG_X29 67 REG_X30 68 REG_X31 69 70 // FP register numberings. 71 REG_F0 72 REG_F1 73 REG_F2 74 REG_F3 75 REG_F4 76 REG_F5 77 REG_F6 78 REG_F7 79 REG_F8 80 REG_F9 81 REG_F10 82 REG_F11 83 REG_F12 84 REG_F13 85 REG_F14 86 REG_F15 87 REG_F16 88 REG_F17 89 REG_F18 90 REG_F19 91 REG_F20 92 REG_F21 93 REG_F22 94 REG_F23 95 REG_F24 96 REG_F25 97 REG_F26 98 REG_F27 99 REG_F28 100 REG_F29 101 REG_F30 102 REG_F31 103 104 // This marks the end of the register numbering. 105 REG_END 106 107 // General registers reassigned to ABI names. 108 REG_ZERO = REG_X0 109 REG_RA = REG_X1 // aka REG_LR 110 REG_SP = REG_X2 111 REG_GP = REG_X3 // aka REG_SB 112 REG_TP = REG_X4 113 REG_T0 = REG_X5 114 REG_T1 = REG_X6 115 REG_T2 = REG_X7 116 REG_S0 = REG_X8 117 REG_S1 = REG_X9 118 REG_A0 = REG_X10 119 REG_A1 = REG_X11 120 REG_A2 = REG_X12 121 REG_A3 = REG_X13 122 REG_A4 = REG_X14 123 REG_A5 = REG_X15 124 REG_A6 = REG_X16 125 REG_A7 = REG_X17 126 REG_S2 = REG_X18 127 REG_S3 = REG_X19 128 REG_S4 = REG_X20 129 REG_S5 = REG_X21 130 REG_S6 = REG_X22 131 REG_S7 = REG_X23 132 REG_S8 = REG_X24 133 REG_S9 = REG_X25 134 REG_S10 = REG_X26 // aka REG_CTXT 135 REG_S11 = REG_X27 // aka REG_G 136 REG_T3 = REG_X28 137 REG_T4 = REG_X29 138 REG_T5 = REG_X30 139 REG_T6 = REG_X31 // aka REG_TMP 140 141 // Go runtime register names. 142 REG_CTXT = REG_S10 // Context for closures. 143 REG_G = REG_S11 // G pointer. 144 REG_LR = REG_RA // Link register. 145 REG_TMP = REG_T6 // Reserved for assembler use. 146 147 // ABI names for floating point registers. 148 REG_FT0 = REG_F0 149 REG_FT1 = REG_F1 150 REG_FT2 = REG_F2 151 REG_FT3 = REG_F3 152 REG_FT4 = REG_F4 153 REG_FT5 = REG_F5 154 REG_FT6 = REG_F6 155 REG_FT7 = REG_F7 156 REG_FS0 = REG_F8 157 REG_FS1 = REG_F9 158 REG_FA0 = REG_F10 159 REG_FA1 = REG_F11 160 REG_FA2 = REG_F12 161 REG_FA3 = REG_F13 162 REG_FA4 = REG_F14 163 REG_FA5 = REG_F15 164 REG_FA6 = REG_F16 165 REG_FA7 = REG_F17 166 REG_FS2 = REG_F18 167 REG_FS3 = REG_F19 168 REG_FS4 = REG_F20 169 REG_FS5 = REG_F21 170 REG_FS6 = REG_F22 171 REG_FS7 = REG_F23 172 REG_FS8 = REG_F24 173 REG_FS9 = REG_F25 174 REG_FS10 = REG_F26 175 REG_FS11 = REG_F27 176 REG_FT8 = REG_F28 177 REG_FT9 = REG_F29 178 REG_FT10 = REG_F30 179 REG_FT11 = REG_F31 180 181 // Names generated by the SSA compiler. 182 REGSP = REG_SP 183 REGG = REG_G 184 ) 185 186 // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers 187 var RISCV64DWARFRegisters = map[int16]int16{ 188 // Integer Registers. 189 REG_X0: 0, 190 REG_X1: 1, 191 REG_X2: 2, 192 REG_X3: 3, 193 REG_X4: 4, 194 REG_X5: 5, 195 REG_X6: 6, 196 REG_X7: 7, 197 REG_X8: 8, 198 REG_X9: 9, 199 REG_X10: 10, 200 REG_X11: 11, 201 REG_X12: 12, 202 REG_X13: 13, 203 REG_X14: 14, 204 REG_X15: 15, 205 REG_X16: 16, 206 REG_X17: 17, 207 REG_X18: 18, 208 REG_X19: 19, 209 REG_X20: 20, 210 REG_X21: 21, 211 REG_X22: 22, 212 REG_X23: 23, 213 REG_X24: 24, 214 REG_X25: 25, 215 REG_X26: 26, 216 REG_X27: 27, 217 REG_X28: 28, 218 REG_X29: 29, 219 REG_X30: 30, 220 REG_X31: 31, 221 222 // Floating-Point Registers. 223 REG_F0: 32, 224 REG_F1: 33, 225 REG_F2: 34, 226 REG_F3: 35, 227 REG_F4: 36, 228 REG_F5: 37, 229 REG_F6: 38, 230 REG_F7: 39, 231 REG_F8: 40, 232 REG_F9: 41, 233 REG_F10: 42, 234 REG_F11: 43, 235 REG_F12: 44, 236 REG_F13: 45, 237 REG_F14: 46, 238 REG_F15: 47, 239 REG_F16: 48, 240 REG_F17: 49, 241 REG_F18: 50, 242 REG_F19: 51, 243 REG_F20: 52, 244 REG_F21: 53, 245 REG_F22: 54, 246 REG_F23: 55, 247 REG_F24: 56, 248 REG_F25: 57, 249 REG_F26: 58, 250 REG_F27: 59, 251 REG_F28: 60, 252 REG_F29: 61, 253 REG_F30: 62, 254 REG_F31: 63, 255 } 256 257 // Prog.Mark flags. 258 const ( 259 // USES_REG_TMP indicates that a machine instruction generated from the 260 // corresponding *obj.Prog uses the temporary register. 261 USES_REG_TMP = 1 << iota 262 263 // NEED_JAL_RELOC is set on JAL instructions to indicate that a 264 // R_RISCV_JAL relocation is needed. 265 NEED_JAL_RELOC 266 267 // NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it 268 // is the first instruction in an AUIPC + JAL pair that needs a 269 // R_RISCV_CALL relocation. 270 NEED_CALL_RELOC 271 272 // NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that 273 // it is the first instruction in an AUIPC + I-type pair that needs a 274 // R_RISCV_PCREL_ITYPE relocation. 275 NEED_PCREL_ITYPE_RELOC 276 277 // NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that 278 // it is the first instruction in an AUIPC + S-type pair that needs a 279 // R_RISCV_PCREL_STYPE relocation. 280 NEED_PCREL_STYPE_RELOC 281 ) 282 283 // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files 284 // at https://github.com/riscv/riscv-opcodes. 285 // 286 // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler. 287 // 288 // See also "The RISC-V Instruction Set Manual" at https://riscv.org/specifications/. 289 // 290 // If you modify this table, you MUST run 'go generate' to regenerate anames.go! 291 const ( 292 // Unprivileged ISA (Document Version 20190608-Base-Ratified) 293 294 // 2.4: Integer Computational Instructions 295 AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota 296 ASLTI 297 ASLTIU 298 AANDI 299 AORI 300 AXORI 301 ASLLI 302 ASRLI 303 ASRAI 304 ALUI 305 AAUIPC 306 AADD 307 ASLT 308 ASLTU 309 AAND 310 AOR 311 AXOR 312 ASLL 313 ASRL 314 ASUB 315 ASRA 316 317 // 2.5: Control Transfer Instructions 318 AJAL 319 AJALR 320 ABEQ 321 ABNE 322 ABLT 323 ABLTU 324 ABGE 325 ABGEU 326 327 // 2.6: Load and Store Instructions 328 ALW 329 ALWU 330 ALH 331 ALHU 332 ALB 333 ALBU 334 ASW 335 ASH 336 ASB 337 338 // 2.7: Memory Ordering Instructions 339 AFENCE 340 AFENCETSO 341 APAUSE 342 343 // 5.2: Integer Computational Instructions (RV64I) 344 AADDIW 345 ASLLIW 346 ASRLIW 347 ASRAIW 348 AADDW 349 ASLLW 350 ASRLW 351 ASUBW 352 ASRAW 353 354 // 5.3: Load and Store Instructions (RV64I) 355 ALD 356 ASD 357 358 // 7.1: Multiplication Operations 359 AMUL 360 AMULH 361 AMULHU 362 AMULHSU 363 AMULW 364 ADIV 365 ADIVU 366 AREM 367 AREMU 368 ADIVW 369 ADIVUW 370 AREMW 371 AREMUW 372 373 // 8.2: Load-Reserved/Store-Conditional Instructions 374 ALRD 375 ASCD 376 ALRW 377 ASCW 378 379 // 8.3: Atomic Memory Operations 380 AAMOSWAPD 381 AAMOADDD 382 AAMOANDD 383 AAMOORD 384 AAMOXORD 385 AAMOMAXD 386 AAMOMAXUD 387 AAMOMIND 388 AAMOMINUD 389 AAMOSWAPW 390 AAMOADDW 391 AAMOANDW 392 AAMOORW 393 AAMOXORW 394 AAMOMAXW 395 AAMOMAXUW 396 AAMOMINW 397 AAMOMINUW 398 399 // 10.1: Base Counters and Timers 400 ARDCYCLE 401 ARDCYCLEH 402 ARDTIME 403 ARDTIMEH 404 ARDINSTRET 405 ARDINSTRETH 406 407 // 11.2: Floating-Point Control and Status Register 408 AFRCSR 409 AFSCSR 410 AFRRM 411 AFSRM 412 AFRFLAGS 413 AFSFLAGS 414 AFSRMI 415 AFSFLAGSI 416 417 // 11.5: Single-Precision Load and Store Instructions 418 AFLW 419 AFSW 420 421 // 11.6: Single-Precision Floating-Point Computational Instructions 422 AFADDS 423 AFSUBS 424 AFMULS 425 AFDIVS 426 AFMINS 427 AFMAXS 428 AFSQRTS 429 AFMADDS 430 AFMSUBS 431 AFNMADDS 432 AFNMSUBS 433 434 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions 435 AFCVTWS 436 AFCVTLS 437 AFCVTSW 438 AFCVTSL 439 AFCVTWUS 440 AFCVTLUS 441 AFCVTSWU 442 AFCVTSLU 443 AFSGNJS 444 AFSGNJNS 445 AFSGNJXS 446 AFMVXS 447 AFMVSX 448 AFMVXW 449 AFMVWX 450 451 // 11.8: Single-Precision Floating-Point Compare Instructions 452 AFEQS 453 AFLTS 454 AFLES 455 456 // 11.9: Single-Precision Floating-Point Classify Instruction 457 AFCLASSS 458 459 // 12.3: Double-Precision Load and Store Instructions 460 AFLD 461 AFSD 462 463 // 12.4: Double-Precision Floating-Point Computational Instructions 464 AFADDD 465 AFSUBD 466 AFMULD 467 AFDIVD 468 AFMIND 469 AFMAXD 470 AFSQRTD 471 AFMADDD 472 AFMSUBD 473 AFNMADDD 474 AFNMSUBD 475 476 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions 477 AFCVTWD 478 AFCVTLD 479 AFCVTDW 480 AFCVTDL 481 AFCVTWUD 482 AFCVTLUD 483 AFCVTDWU 484 AFCVTDLU 485 AFCVTSD 486 AFCVTDS 487 AFSGNJD 488 AFSGNJND 489 AFSGNJXD 490 AFMVXD 491 AFMVDX 492 493 // 12.6: Double-Precision Floating-Point Compare Instructions 494 AFEQD 495 AFLTD 496 AFLED 497 498 // 12.7: Double-Precision Floating-Point Classify Instruction 499 AFCLASSD 500 501 // 13.1 Quad-Precision Load and Store Instructions 502 AFLQ 503 AFSQ 504 505 // 13.2: Quad-Precision Computational Instructions 506 AFADDQ 507 AFSUBQ 508 AFMULQ 509 AFDIVQ 510 AFMINQ 511 AFMAXQ 512 AFSQRTQ 513 AFMADDQ 514 AFMSUBQ 515 AFNMADDQ 516 AFNMSUBQ 517 518 // 13.3 Quad-Precision Convert and Move Instructions 519 AFCVTWQ 520 AFCVTLQ 521 AFCVTSQ 522 AFCVTDQ 523 AFCVTQW 524 AFCVTQL 525 AFCVTQS 526 AFCVTQD 527 AFCVTWUQ 528 AFCVTLUQ 529 AFCVTQWU 530 AFCVTQLU 531 AFSGNJQ 532 AFSGNJNQ 533 AFSGNJXQ 534 535 // 13.4 Quad-Precision Floating-Point Compare Instructions 536 AFEQQ 537 AFLEQ 538 AFLTQ 539 540 // 13.5 Quad-Precision Floating-Point Classify Instruction 541 AFCLASSQ 542 543 // Privileged ISA (Version 20190608-Priv-MSU-Ratified) 544 545 // 3.1.9: Instructions to Access CSRs 546 ACSRRW 547 ACSRRS 548 ACSRRC 549 ACSRRWI 550 ACSRRSI 551 ACSRRCI 552 553 // 3.2.1: Environment Call and Breakpoint 554 AECALL 555 ASCALL 556 AEBREAK 557 ASBREAK 558 559 // 3.2.2: Trap-Return Instructions 560 AMRET 561 ASRET 562 ADRET 563 564 // 3.2.3: Wait for Interrupt 565 AWFI 566 567 // 4.2.1: Supervisor Memory-Management Fence Instruction 568 ASFENCEVMA 569 570 // The escape hatch. Inserts a single 32-bit word. 571 AWORD 572 573 // Pseudo-instructions. These get translated by the assembler into other 574 // instructions, based on their operands. 575 ABEQZ 576 ABGEZ 577 ABGT 578 ABGTU 579 ABGTZ 580 ABLE 581 ABLEU 582 ABLEZ 583 ABLTZ 584 ABNEZ 585 AFABSD 586 AFABSS 587 AFNEGD 588 AFNEGS 589 AFNED 590 AFNES 591 AMOV 592 AMOVB 593 AMOVBU 594 AMOVF 595 AMOVD 596 AMOVH 597 AMOVHU 598 AMOVW 599 AMOVWU 600 ANEG 601 ANEGW 602 ANOT 603 ASEQZ 604 ASNEZ 605 606 // End marker 607 ALAST 608 ) 609 610 // All unary instructions which write to their arguments (as opposed to reading 611 // from them) go here. The assembly parser uses this information to populate 612 // its AST in a semantically reasonable way. 613 // 614 // Any instructions not listed here are assumed to either be non-unary or to read 615 // from its argument. 616 var unaryDst = map[obj.As]bool{ 617 ARDCYCLE: true, 618 ARDCYCLEH: true, 619 ARDTIME: true, 620 ARDTIMEH: true, 621 ARDINSTRET: true, 622 ARDINSTRETH: true, 623 } 624 625 // Instruction encoding masks. 626 const ( 627 // BTypeImmMask is a mask including only the immediate portion of 628 // B-type instructions. 629 BTypeImmMask = 0xfe000f80 630 631 // CBTypeImmMask is a mask including only the immediate portion of 632 // CB-type instructions. 633 CBTypeImmMask = 0x1c7c 634 635 // CJTypeImmMask is a mask including only the immediate portion of 636 // CJ-type instructions. 637 CJTypeImmMask = 0x1f7c 638 639 // ITypeImmMask is a mask including only the immediate portion of 640 // I-type instructions. 641 ITypeImmMask = 0xfff00000 642 643 // JTypeImmMask is a mask including only the immediate portion of 644 // J-type instructions. 645 JTypeImmMask = 0xfffff000 646 647 // STypeImmMask is a mask including only the immediate portion of 648 // S-type instructions. 649 STypeImmMask = 0xfe000f80 650 651 // UTypeImmMask is a mask including only the immediate portion of 652 // U-type instructions. 653 UTypeImmMask = 0xfffff000 654 )