github.com/c9s/go@v0.0.0-20180120015821-984e81f64e0c/src/sync/atomic/asm_darwin_arm.s (about)

     1  // Copyright 2012 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  #include "textflag.h"
     6  
     7  // Darwin/ARM atomic operations.
     8  
     9  #define DMB_ISHST_7 \
    10      WORD    $0xf57ff05a // dmb ishst
    11  
    12  #define DMB_ISH_7 \
    13      WORD    $0xf57ff05b // dmb ish
    14  
    15  TEXT ·CompareAndSwapInt32(SB),NOSPLIT,$0
    16  	B ·CompareAndSwapUint32(SB)
    17  
    18  TEXT ·CompareAndSwapUint32(SB),NOSPLIT,$0
    19  	B ·armCompareAndSwapUint32(SB)
    20  
    21  TEXT ·CompareAndSwapUintptr(SB),NOSPLIT,$0
    22  	B ·CompareAndSwapUint32(SB)
    23  
    24  TEXT ·AddInt32(SB),NOSPLIT,$0
    25  	B ·AddUint32(SB)
    26  
    27  TEXT ·AddUint32(SB),NOSPLIT,$0
    28  	B ·armAddUint32(SB)
    29  
    30  TEXT ·AddUintptr(SB),NOSPLIT,$0
    31  	B ·AddUint32(SB)
    32  
    33  TEXT ·SwapInt32(SB),NOSPLIT,$0
    34  	B ·SwapUint32(SB)
    35  
    36  TEXT ·SwapUint32(SB),NOSPLIT,$0
    37  	B ·armSwapUint32(SB)
    38  
    39  TEXT ·SwapUintptr(SB),NOSPLIT,$0
    40  	B ·SwapUint32(SB)
    41  
    42  TEXT ·CompareAndSwapInt64(SB),NOSPLIT,$0
    43  	B ·CompareAndSwapUint64(SB)
    44  
    45  TEXT ·CompareAndSwapUint64(SB),NOSPLIT,$-4
    46  	B ·armCompareAndSwapUint64(SB)
    47  
    48  TEXT ·AddInt64(SB),NOSPLIT,$0
    49  	B ·addUint64(SB)
    50  
    51  TEXT ·AddUint64(SB),NOSPLIT,$0
    52  	B ·addUint64(SB)
    53  
    54  TEXT ·SwapInt64(SB),NOSPLIT,$0
    55  	B ·swapUint64(SB)
    56  
    57  TEXT ·SwapUint64(SB),NOSPLIT,$0
    58  	B ·swapUint64(SB)
    59  
    60  TEXT ·LoadInt32(SB),NOSPLIT,$0
    61  	B ·LoadUint32(SB)
    62  
    63  TEXT ·LoadUint32(SB),NOSPLIT,$0-8
    64  	MOVW addr+0(FP), R1
    65  load32loop:
    66  	LDREX (R1), R2		// loads R2
    67  	DMB_ISHST_7
    68  	STREX R2, (R1), R0	// stores R2
    69  	CMP $0, R0
    70  	BNE load32loop
    71  	DMB_ISH_7
    72  	MOVW R2, val+4(FP)
    73  	RET
    74  
    75  TEXT ·LoadInt64(SB),NOSPLIT,$0
    76  	B ·loadUint64(SB)
    77  
    78  TEXT ·LoadUint64(SB),NOSPLIT,$0
    79  	B ·loadUint64(SB)
    80  
    81  TEXT ·LoadUintptr(SB),NOSPLIT,$0
    82  	B ·LoadUint32(SB)
    83  
    84  TEXT ·LoadPointer(SB),NOSPLIT,$0
    85  	B ·LoadUint32(SB)
    86  
    87  TEXT ·StoreInt32(SB),NOSPLIT,$0
    88  	B ·StoreUint32(SB)
    89  
    90  TEXT ·StoreUint32(SB),NOSPLIT,$0-8
    91  	MOVW addr+0(FP), R1
    92  	MOVW val+4(FP), R2
    93  storeloop:
    94  	LDREX (R1), R4		// loads R4
    95  	DMB_ISHST_7
    96  	STREX R2, (R1), R0	// stores R2
    97  	CMP $0, R0
    98  	BNE storeloop
    99  	DMB_ISH_7
   100  	RET
   101  
   102  TEXT ·StoreInt64(SB),NOSPLIT,$0
   103  	B ·storeUint64(SB)
   104  
   105  TEXT ·StoreUint64(SB),NOSPLIT,$0
   106  	B ·storeUint64(SB)
   107  
   108  TEXT ·StoreUintptr(SB),NOSPLIT,$0
   109  	B ·StoreUint32(SB)