github.com/corona10/go@v0.0.0-20180224231303-7a218942be57/src/cmd/compile/internal/ssa/gen/MIPS64.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 (Add(Ptr|64|32|16|8) x y) -> (ADDV x y) 6 (Add(32|64)F x y) -> (ADD(F|D) x y) 7 8 (Sub(Ptr|64|32|16|8) x y) -> (SUBV x y) 9 (Sub(32|64)F x y) -> (SUB(F|D) x y) 10 11 (Mul(64|32|16|8) x y) -> (Select1 (MULVU x y)) 12 (Mul(32|64)F x y) -> (MUL(F|D) x y) 13 14 (Hmul64 x y) -> (Select0 (MULV x y)) 15 (Hmul64u x y) -> (Select0 (MULVU x y)) 16 (Hmul32 x y) -> (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32]) 17 (Hmul32u x y) -> (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32]) 18 19 (Div64 x y) -> (Select1 (DIVV x y)) 20 (Div64u x y) -> (Select1 (DIVVU x y)) 21 (Div32 x y) -> (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 22 (Div32u x y) -> (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 23 (Div16 x y) -> (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 24 (Div16u x y) -> (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 25 (Div8 x y) -> (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 26 (Div8u x y) -> (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 27 (Div(32|64)F x y) -> (DIV(F|D) x y) 28 29 (Mod64 x y) -> (Select0 (DIVV x y)) 30 (Mod64u x y) -> (Select0 (DIVVU x y)) 31 (Mod32 x y) -> (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 32 (Mod32u x y) -> (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 33 (Mod16 x y) -> (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 34 (Mod16u x y) -> (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 35 (Mod8 x y) -> (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 36 (Mod8u x y) -> (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 37 38 // (x + y) / 2 with x>=y -> (x - y) / 2 + y 39 (Avg64u <t> x y) -> (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y) 40 41 (And(64|32|16|8) x y) -> (AND x y) 42 (Or(64|32|16|8) x y) -> (OR x y) 43 (Xor(64|32|16|8) x y) -> (XOR x y) 44 45 // shifts 46 // hardware instruction uses only the low 6 bits of the shift 47 // we compare to 64 to ensure Go semantics for large shifts 48 (Lsh64x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 49 (Lsh64x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 50 (Lsh64x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 51 (Lsh64x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 52 53 (Lsh32x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 54 (Lsh32x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 55 (Lsh32x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 56 (Lsh32x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 57 58 (Lsh16x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 59 (Lsh16x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 60 (Lsh16x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 61 (Lsh16x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 62 63 (Lsh8x64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y)) 64 (Lsh8x32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 65 (Lsh8x16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 66 (Lsh8x8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 67 68 (Rsh64Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y)) 69 (Rsh64Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y))) 70 (Rsh64Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y))) 71 (Rsh64Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y))) 72 73 (Rsh32Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y)) 74 (Rsh32Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y))) 75 (Rsh32Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y))) 76 (Rsh32Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y))) 77 78 (Rsh16Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y)) 79 (Rsh16Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y))) 80 (Rsh16Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y))) 81 (Rsh16Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y))) 82 83 (Rsh8Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y)) 84 (Rsh8Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y))) 85 (Rsh8Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y))) 86 (Rsh8Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y))) 87 88 (Rsh64x64 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 89 (Rsh64x32 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 90 (Rsh64x16 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 91 (Rsh64x8 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 92 93 (Rsh32x64 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 94 (Rsh32x32 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 95 (Rsh32x16 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 96 (Rsh32x8 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 97 98 (Rsh16x64 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 99 (Rsh16x32 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 100 (Rsh16x16 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 101 (Rsh16x8 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 102 103 (Rsh8x64 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y)) 104 (Rsh8x32 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y))) 105 (Rsh8x16 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y))) 106 (Rsh8x8 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y))) 107 108 // unary ops 109 (Neg(64|32|16|8) x) -> (NEGV x) 110 (Neg(32|64)F x) -> (NEG(F|D) x) 111 112 (Com(64|32|16|8) x) -> (NOR (MOVVconst [0]) x) 113 114 (Sqrt x) -> (SQRTD x) 115 116 // boolean ops -- booleans are represented with 0=false, 1=true 117 (AndB x y) -> (AND x y) 118 (OrB x y) -> (OR x y) 119 (EqB x y) -> (XOR (MOVVconst [1]) (XOR <typ.Bool> x y)) 120 (NeqB x y) -> (XOR x y) 121 (Not x) -> (XORconst [1] x) 122 123 // constants 124 (Const(64|32|16|8) [val]) -> (MOVVconst [val]) 125 (Const(32|64)F [val]) -> (MOV(F|D)const [val]) 126 (ConstNil) -> (MOVVconst [0]) 127 (ConstBool [b]) -> (MOVVconst [b]) 128 129 (Slicemask <t> x) -> (SRAVconst (NEGV <t> x) [63]) 130 131 // truncations 132 // Because we ignore high parts of registers, truncates are just copies. 133 (Trunc16to8 x) -> x 134 (Trunc32to8 x) -> x 135 (Trunc32to16 x) -> x 136 (Trunc64to8 x) -> x 137 (Trunc64to16 x) -> x 138 (Trunc64to32 x) -> x 139 140 // Zero-/Sign-extensions 141 (ZeroExt8to16 x) -> (MOVBUreg x) 142 (ZeroExt8to32 x) -> (MOVBUreg x) 143 (ZeroExt16to32 x) -> (MOVHUreg x) 144 (ZeroExt8to64 x) -> (MOVBUreg x) 145 (ZeroExt16to64 x) -> (MOVHUreg x) 146 (ZeroExt32to64 x) -> (MOVWUreg x) 147 148 (SignExt8to16 x) -> (MOVBreg x) 149 (SignExt8to32 x) -> (MOVBreg x) 150 (SignExt16to32 x) -> (MOVHreg x) 151 (SignExt8to64 x) -> (MOVBreg x) 152 (SignExt16to64 x) -> (MOVHreg x) 153 (SignExt32to64 x) -> (MOVWreg x) 154 155 // float <-> int conversion 156 (Cvt32to32F x) -> (MOVWF x) 157 (Cvt32to64F x) -> (MOVWD x) 158 (Cvt64to32F x) -> (MOVVF x) 159 (Cvt64to64F x) -> (MOVVD x) 160 (Cvt32Fto32 x) -> (TRUNCFW x) 161 (Cvt64Fto32 x) -> (TRUNCDW x) 162 (Cvt32Fto64 x) -> (TRUNCFV x) 163 (Cvt64Fto64 x) -> (TRUNCDV x) 164 (Cvt32Fto64F x) -> (MOVFD x) 165 (Cvt64Fto32F x) -> (MOVDF x) 166 167 (Round(32|64)F x) -> x 168 169 // comparisons 170 (Eq8 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) 171 (Eq16 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) 172 (Eq32 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) 173 (Eq64 x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 174 (EqPtr x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 175 (Eq(32|64)F x y) -> (FPFlagTrue (CMPEQ(F|D) x y)) 176 177 (Neq8 x y) -> (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0])) 178 (Neq16 x y) -> (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0])) 179 (Neq32 x y) -> (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0])) 180 (Neq64 x y) -> (SGTU (XOR x y) (MOVVconst [0])) 181 (NeqPtr x y) -> (SGTU (XOR x y) (MOVVconst [0])) 182 (Neq(32|64)F x y) -> (FPFlagFalse (CMPEQ(F|D) x y)) 183 184 (Less8 x y) -> (SGT (SignExt8to64 y) (SignExt8to64 x)) 185 (Less16 x y) -> (SGT (SignExt16to64 y) (SignExt16to64 x)) 186 (Less32 x y) -> (SGT (SignExt32to64 y) (SignExt32to64 x)) 187 (Less64 x y) -> (SGT y x) 188 (Less(32|64)F x y) -> (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN 189 190 (Less8U x y) -> (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x)) 191 (Less16U x y) -> (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x)) 192 (Less32U x y) -> (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x)) 193 (Less64U x y) -> (SGTU y x) 194 195 (Leq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y))) 196 (Leq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y))) 197 (Leq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y))) 198 (Leq64 x y) -> (XOR (MOVVconst [1]) (SGT x y)) 199 (Leq(32|64)F x y) -> (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN 200 201 (Leq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y))) 202 (Leq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y))) 203 (Leq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y))) 204 (Leq64U x y) -> (XOR (MOVVconst [1]) (SGTU x y)) 205 206 (Greater8 x y) -> (SGT (SignExt8to64 x) (SignExt8to64 y)) 207 (Greater16 x y) -> (SGT (SignExt16to64 x) (SignExt16to64 y)) 208 (Greater32 x y) -> (SGT (SignExt32to64 x) (SignExt32to64 y)) 209 (Greater64 x y) -> (SGT x y) 210 (Greater(32|64)F x y) -> (FPFlagTrue (CMPGT(F|D) x y)) 211 212 (Greater8U x y) -> (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)) 213 (Greater16U x y) -> (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)) 214 (Greater32U x y) -> (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)) 215 (Greater64U x y) -> (SGTU x y) 216 217 (Geq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 y) (SignExt8to64 x))) 218 (Geq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 y) (SignExt16to64 x))) 219 (Geq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 y) (SignExt32to64 x))) 220 (Geq64 x y) -> (XOR (MOVVconst [1]) (SGT y x)) 221 (Geq(32|64)F x y) -> (FPFlagTrue (CMPGE(F|D) x y)) 222 223 (Geq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))) 224 (Geq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))) 225 (Geq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))) 226 (Geq64U x y) -> (XOR (MOVVconst [1]) (SGTU y x)) 227 228 (OffPtr [off] ptr:(SP)) -> (MOVVaddr [off] ptr) 229 (OffPtr [off] ptr) -> (ADDVconst [off] ptr) 230 231 (Addr {sym} base) -> (MOVVaddr {sym} base) 232 233 // loads 234 (Load <t> ptr mem) && t.IsBoolean() -> (MOVBUload ptr mem) 235 (Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) -> (MOVBload ptr mem) 236 (Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) -> (MOVBUload ptr mem) 237 (Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) -> (MOVHload ptr mem) 238 (Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) -> (MOVHUload ptr mem) 239 (Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) -> (MOVWload ptr mem) 240 (Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) -> (MOVWUload ptr mem) 241 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVVload ptr mem) 242 (Load <t> ptr mem) && is32BitFloat(t) -> (MOVFload ptr mem) 243 (Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem) 244 245 // stores 246 (Store {t} ptr val mem) && t.(*types.Type).Size() == 1 -> (MOVBstore ptr val mem) 247 (Store {t} ptr val mem) && t.(*types.Type).Size() == 2 -> (MOVHstore ptr val mem) 248 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem) 249 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && !is64BitFloat(val.Type) -> (MOVVstore ptr val mem) 250 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) -> (MOVFstore ptr val mem) 251 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) -> (MOVDstore ptr val mem) 252 253 // zeroing 254 (Zero [0] _ mem) -> mem 255 (Zero [1] ptr mem) -> (MOVBstore ptr (MOVVconst [0]) mem) 256 (Zero [2] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 257 (MOVHstore ptr (MOVVconst [0]) mem) 258 (Zero [2] ptr mem) -> 259 (MOVBstore [1] ptr (MOVVconst [0]) 260 (MOVBstore [0] ptr (MOVVconst [0]) mem)) 261 (Zero [4] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 262 (MOVWstore ptr (MOVVconst [0]) mem) 263 (Zero [4] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 264 (MOVHstore [2] ptr (MOVVconst [0]) 265 (MOVHstore [0] ptr (MOVVconst [0]) mem)) 266 (Zero [4] ptr mem) -> 267 (MOVBstore [3] ptr (MOVVconst [0]) 268 (MOVBstore [2] ptr (MOVVconst [0]) 269 (MOVBstore [1] ptr (MOVVconst [0]) 270 (MOVBstore [0] ptr (MOVVconst [0]) mem)))) 271 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 272 (MOVVstore ptr (MOVVconst [0]) mem) 273 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 274 (MOVWstore [4] ptr (MOVVconst [0]) 275 (MOVWstore [0] ptr (MOVVconst [0]) mem)) 276 (Zero [8] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 277 (MOVHstore [6] ptr (MOVVconst [0]) 278 (MOVHstore [4] ptr (MOVVconst [0]) 279 (MOVHstore [2] ptr (MOVVconst [0]) 280 (MOVHstore [0] ptr (MOVVconst [0]) mem)))) 281 282 (Zero [3] ptr mem) -> 283 (MOVBstore [2] ptr (MOVVconst [0]) 284 (MOVBstore [1] ptr (MOVVconst [0]) 285 (MOVBstore [0] ptr (MOVVconst [0]) mem))) 286 (Zero [6] {t} ptr mem) && t.(*types.Type).Alignment()%2 == 0 -> 287 (MOVHstore [4] ptr (MOVVconst [0]) 288 (MOVHstore [2] ptr (MOVVconst [0]) 289 (MOVHstore [0] ptr (MOVVconst [0]) mem))) 290 (Zero [12] {t} ptr mem) && t.(*types.Type).Alignment()%4 == 0 -> 291 (MOVWstore [8] ptr (MOVVconst [0]) 292 (MOVWstore [4] ptr (MOVVconst [0]) 293 (MOVWstore [0] ptr (MOVVconst [0]) mem))) 294 (Zero [16] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 295 (MOVVstore [8] ptr (MOVVconst [0]) 296 (MOVVstore [0] ptr (MOVVconst [0]) mem)) 297 (Zero [24] {t} ptr mem) && t.(*types.Type).Alignment()%8 == 0 -> 298 (MOVVstore [16] ptr (MOVVconst [0]) 299 (MOVVstore [8] ptr (MOVVconst [0]) 300 (MOVVstore [0] ptr (MOVVconst [0]) mem))) 301 302 // medium zeroing uses a duff device 303 // 8, and 128 are magic constants, see runtime/mkduff.go 304 (Zero [s] {t} ptr mem) 305 && s%8 == 0 && s > 24 && s <= 8*128 306 && t.(*types.Type).Alignment()%8 == 0 && !config.noDuffDevice -> 307 (DUFFZERO [8 * (128 - int64(s/8))] ptr mem) 308 309 // large or unaligned zeroing uses a loop 310 (Zero [s] {t} ptr mem) 311 && (s > 8*128 || config.noDuffDevice) || t.(*types.Type).Alignment()%8 != 0 -> 312 (LoweredZero [t.(*types.Type).Alignment()] 313 ptr 314 (ADDVconst <ptr.Type> ptr [s-moveSize(t.(*types.Type).Alignment(), config)]) 315 mem) 316 317 // moves 318 (Move [0] _ _ mem) -> mem 319 (Move [1] dst src mem) -> (MOVBstore dst (MOVBload src mem) mem) 320 (Move [2] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 321 (MOVHstore dst (MOVHload src mem) mem) 322 (Move [2] dst src mem) -> 323 (MOVBstore [1] dst (MOVBload [1] src mem) 324 (MOVBstore dst (MOVBload src mem) mem)) 325 (Move [4] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 326 (MOVWstore dst (MOVWload src mem) mem) 327 (Move [4] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 328 (MOVHstore [2] dst (MOVHload [2] src mem) 329 (MOVHstore dst (MOVHload src mem) mem)) 330 (Move [4] dst src mem) -> 331 (MOVBstore [3] dst (MOVBload [3] src mem) 332 (MOVBstore [2] dst (MOVBload [2] src mem) 333 (MOVBstore [1] dst (MOVBload [1] src mem) 334 (MOVBstore dst (MOVBload src mem) mem)))) 335 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 336 (MOVVstore dst (MOVVload src mem) mem) 337 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 338 (MOVWstore [4] dst (MOVWload [4] src mem) 339 (MOVWstore dst (MOVWload src mem) mem)) 340 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 341 (MOVHstore [6] dst (MOVHload [6] src mem) 342 (MOVHstore [4] dst (MOVHload [4] src mem) 343 (MOVHstore [2] dst (MOVHload [2] src mem) 344 (MOVHstore dst (MOVHload src mem) mem)))) 345 346 (Move [3] dst src mem) -> 347 (MOVBstore [2] dst (MOVBload [2] src mem) 348 (MOVBstore [1] dst (MOVBload [1] src mem) 349 (MOVBstore dst (MOVBload src mem) mem))) 350 (Move [6] {t} dst src mem) && t.(*types.Type).Alignment()%2 == 0 -> 351 (MOVHstore [4] dst (MOVHload [4] src mem) 352 (MOVHstore [2] dst (MOVHload [2] src mem) 353 (MOVHstore dst (MOVHload src mem) mem))) 354 (Move [12] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 355 (MOVWstore [8] dst (MOVWload [8] src mem) 356 (MOVWstore [4] dst (MOVWload [4] src mem) 357 (MOVWstore dst (MOVWload src mem) mem))) 358 (Move [16] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 359 (MOVVstore [8] dst (MOVVload [8] src mem) 360 (MOVVstore dst (MOVVload src mem) mem)) 361 (Move [24] {t} dst src mem) && t.(*types.Type).Alignment()%8 == 0 -> 362 (MOVVstore [16] dst (MOVVload [16] src mem) 363 (MOVVstore [8] dst (MOVVload [8] src mem) 364 (MOVVstore dst (MOVVload src mem) mem))) 365 366 // large or unaligned move uses a loop 367 (Move [s] {t} dst src mem) 368 && s > 24 || t.(*types.Type).Alignment()%8 != 0 -> 369 (LoweredMove [t.(*types.Type).Alignment()] 370 dst 371 src 372 (ADDVconst <src.Type> src [s-moveSize(t.(*types.Type).Alignment(), config)]) 373 mem) 374 375 // calls 376 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 377 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 378 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 379 380 // atomic intrinsics 381 (AtomicLoad32 ptr mem) -> (LoweredAtomicLoad32 ptr mem) 382 (AtomicLoad64 ptr mem) -> (LoweredAtomicLoad64 ptr mem) 383 (AtomicLoadPtr ptr mem) -> (LoweredAtomicLoad64 ptr mem) 384 385 (AtomicStore32 ptr val mem) -> (LoweredAtomicStore32 ptr val mem) 386 (AtomicStore64 ptr val mem) -> (LoweredAtomicStore64 ptr val mem) 387 (AtomicStorePtrNoWB ptr val mem) -> (LoweredAtomicStore64 ptr val mem) 388 389 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 390 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 391 392 (AtomicAdd32 ptr val mem) -> (LoweredAtomicAdd32 ptr val mem) 393 (AtomicAdd64 ptr val mem) -> (LoweredAtomicAdd64 ptr val mem) 394 395 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 396 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 397 398 // checks 399 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 400 (IsNonNil ptr) -> (SGTU ptr (MOVVconst [0])) 401 (IsInBounds idx len) -> (SGTU len idx) 402 (IsSliceInBounds idx len) -> (XOR (MOVVconst [1]) (SGTU idx len)) 403 404 // pseudo-ops 405 (GetClosurePtr) -> (LoweredGetClosurePtr) 406 (GetCallerSP) -> (LoweredGetCallerSP) 407 (Convert x mem) -> (MOVVconvert x mem) 408 409 (If cond yes no) -> (NE cond yes no) 410 411 // Write barrier. 412 (WB {fn} destptr srcptr mem) -> (LoweredWB {fn} destptr srcptr mem) 413 414 // Optimizations 415 416 // Absorb boolean tests into block 417 (NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no) 418 (NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no) 419 (EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no) 420 (EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no) 421 (NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no) 422 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no) 423 (NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no) 424 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no) 425 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no) 426 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no) 427 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no) 428 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no) 429 (NE (SGTUconst [1] x) yes no) -> (EQ x yes no) 430 (EQ (SGTUconst [1] x) yes no) -> (NE x yes no) 431 (NE (SGTU x (MOVVconst [0])) yes no) -> (NE x yes no) 432 (EQ (SGTU x (MOVVconst [0])) yes no) -> (EQ x yes no) 433 (NE (SGTconst [0] x) yes no) -> (LTZ x yes no) 434 (EQ (SGTconst [0] x) yes no) -> (GEZ x yes no) 435 (NE (SGT x (MOVVconst [0])) yes no) -> (GTZ x yes no) 436 (EQ (SGT x (MOVVconst [0])) yes no) -> (LEZ x yes no) 437 438 // fold offset into address 439 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) -> (MOVVaddr [off1+off2] {sym} ptr) 440 441 // fold address into load/store 442 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 443 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem) 444 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem) 445 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem) 446 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 447 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem) 448 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem) 449 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem) 450 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 451 452 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 453 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 454 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 455 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVVstore [off1+off2] {sym} ptr val mem) 456 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVFstore [off1+off2] {sym} ptr val mem) 457 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 458 (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBstorezero [off1+off2] {sym} ptr mem) 459 (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHstorezero [off1+off2] {sym} ptr mem) 460 (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWstorezero [off1+off2] {sym} ptr mem) 461 (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVstorezero [off1+off2] {sym} ptr mem) 462 463 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 464 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 465 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 466 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 467 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 468 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 469 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 470 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 471 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 472 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 473 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 474 (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 475 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 476 (MOVVload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 477 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 478 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 479 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 480 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 481 482 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 483 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 484 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 485 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 486 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 487 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 488 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 489 (MOVVstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 490 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 491 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 492 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 493 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 494 (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 495 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 496 (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 497 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 498 (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 499 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 500 (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 501 (MOVVstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 502 503 // store zero 504 (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem) 505 (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem) 506 (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem) 507 (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVVstorezero [off] {sym} ptr mem) 508 509 // don't extend after proper load 510 (MOVBreg x:(MOVBload _ _)) -> (MOVVreg x) 511 (MOVBUreg x:(MOVBUload _ _)) -> (MOVVreg x) 512 (MOVHreg x:(MOVBload _ _)) -> (MOVVreg x) 513 (MOVHreg x:(MOVBUload _ _)) -> (MOVVreg x) 514 (MOVHreg x:(MOVHload _ _)) -> (MOVVreg x) 515 (MOVHUreg x:(MOVBUload _ _)) -> (MOVVreg x) 516 (MOVHUreg x:(MOVHUload _ _)) -> (MOVVreg x) 517 (MOVWreg x:(MOVBload _ _)) -> (MOVVreg x) 518 (MOVWreg x:(MOVBUload _ _)) -> (MOVVreg x) 519 (MOVWreg x:(MOVHload _ _)) -> (MOVVreg x) 520 (MOVWreg x:(MOVHUload _ _)) -> (MOVVreg x) 521 (MOVWreg x:(MOVWload _ _)) -> (MOVVreg x) 522 (MOVWUreg x:(MOVBUload _ _)) -> (MOVVreg x) 523 (MOVWUreg x:(MOVHUload _ _)) -> (MOVVreg x) 524 (MOVWUreg x:(MOVWUload _ _)) -> (MOVVreg x) 525 526 // fold double extensions 527 (MOVBreg x:(MOVBreg _)) -> (MOVVreg x) 528 (MOVBUreg x:(MOVBUreg _)) -> (MOVVreg x) 529 (MOVHreg x:(MOVBreg _)) -> (MOVVreg x) 530 (MOVHreg x:(MOVBUreg _)) -> (MOVVreg x) 531 (MOVHreg x:(MOVHreg _)) -> (MOVVreg x) 532 (MOVHUreg x:(MOVBUreg _)) -> (MOVVreg x) 533 (MOVHUreg x:(MOVHUreg _)) -> (MOVVreg x) 534 (MOVWreg x:(MOVBreg _)) -> (MOVVreg x) 535 (MOVWreg x:(MOVBUreg _)) -> (MOVVreg x) 536 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 537 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 538 (MOVWreg x:(MOVWreg _)) -> (MOVVreg x) 539 (MOVWUreg x:(MOVBUreg _)) -> (MOVVreg x) 540 (MOVWUreg x:(MOVHUreg _)) -> (MOVVreg x) 541 (MOVWUreg x:(MOVWUreg _)) -> (MOVVreg x) 542 543 // don't extend before store 544 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 545 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 546 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 547 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 548 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 549 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 550 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 551 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 552 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 553 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 554 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 555 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 556 557 // if a register move has only 1 use, just use the same register without emitting instruction 558 // MOVVnop doesn't emit instruction, only for ensuring the type. 559 (MOVVreg x) && x.Uses == 1 -> (MOVVnop x) 560 561 // fold constant into arithmatic ops 562 (ADDV x (MOVVconst [c])) && is32Bit(c) -> (ADDVconst [c] x) 563 (SUBV x (MOVVconst [c])) && is32Bit(c) -> (SUBVconst [c] x) 564 (AND x (MOVVconst [c])) && is32Bit(c) -> (ANDconst [c] x) 565 (OR x (MOVVconst [c])) && is32Bit(c) -> (ORconst [c] x) 566 (XOR x (MOVVconst [c])) && is32Bit(c) -> (XORconst [c] x) 567 (NOR x (MOVVconst [c])) && is32Bit(c) -> (NORconst [c] x) 568 569 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 570 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 571 (SRAV x (MOVVconst [c])) && uint64(c)>=64 -> (SRAVconst x [63]) 572 (SLLV x (MOVVconst [c])) -> (SLLVconst x [c]) 573 (SRLV x (MOVVconst [c])) -> (SRLVconst x [c]) 574 (SRAV x (MOVVconst [c])) -> (SRAVconst x [c]) 575 576 (SGT (MOVVconst [c]) x) && is32Bit(c) -> (SGTconst [c] x) 577 (SGTU (MOVVconst [c]) x) && is32Bit(c) -> (SGTUconst [c] x) 578 579 // mul by constant 580 (Select1 (MULVU x (MOVVconst [-1]))) -> (NEGV x) 581 (Select1 (MULVU _ (MOVVconst [0]))) -> (MOVVconst [0]) 582 (Select1 (MULVU x (MOVVconst [1]))) -> x 583 (Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 584 585 (Select1 (MULVU (MOVVconst [-1]) x)) -> (NEGV x) 586 (Select1 (MULVU (MOVVconst [0]) _)) -> (MOVVconst [0]) 587 (Select1 (MULVU (MOVVconst [1]) x)) -> x 588 (Select1 (MULVU (MOVVconst [c]) x)) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 589 590 // div by constant 591 (Select1 (DIVVU x (MOVVconst [1]))) -> x 592 (Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SRLVconst [log2(c)] x) 593 (Select0 (DIVVU _ (MOVVconst [1]))) -> (MOVVconst [0]) // mod 594 (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x) // mod 595 596 // generic simplifications 597 (ADDV x (NEGV y)) -> (SUBV x y) 598 (SUBV x x) -> (MOVVconst [0]) 599 (SUBV (MOVVconst [0]) x) -> (NEGV x) 600 (AND x x) -> x 601 (OR x x) -> x 602 (XOR x x) -> (MOVVconst [0]) 603 604 // remove redundant *const ops 605 (ADDVconst [0] x) -> x 606 (SUBVconst [0] x) -> x 607 (ANDconst [0] _) -> (MOVVconst [0]) 608 (ANDconst [-1] x) -> x 609 (ORconst [0] x) -> x 610 (ORconst [-1] _) -> (MOVVconst [-1]) 611 (XORconst [0] x) -> x 612 (XORconst [-1] x) -> (NORconst [0] x) 613 614 // generic constant folding 615 (ADDVconst [c] (MOVVconst [d])) -> (MOVVconst [c+d]) 616 (ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) -> (ADDVconst [c+d] x) 617 (ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) -> (ADDVconst [c-d] x) 618 (SUBVconst [c] (MOVVconst [d])) -> (MOVVconst [d-c]) 619 (SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) -> (ADDVconst [-c-d] x) 620 (SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) -> (ADDVconst [-c+d] x) 621 (SLLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)<<uint64(c)]) 622 (SRLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(uint64(d)>>uint64(c))]) 623 (SRAVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)>>uint64(c)]) 624 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [c*d]) 625 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)/int64(d)]) 626 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)/uint64(d))]) 627 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)%int64(d)]) // mod 628 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)%uint64(d))]) // mod 629 (ANDconst [c] (MOVVconst [d])) -> (MOVVconst [c&d]) 630 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x) 631 (ORconst [c] (MOVVconst [d])) -> (MOVVconst [c|d]) 632 (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) -> (ORconst [c|d] x) 633 (XORconst [c] (MOVVconst [d])) -> (MOVVconst [c^d]) 634 (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) -> (XORconst [c^d] x) 635 (NORconst [c] (MOVVconst [d])) -> (MOVVconst [^(c|d)]) 636 (NEGV (MOVVconst [c])) -> (MOVVconst [-c]) 637 (MOVBreg (MOVVconst [c])) -> (MOVVconst [int64(int8(c))]) 638 (MOVBUreg (MOVVconst [c])) -> (MOVVconst [int64(uint8(c))]) 639 (MOVHreg (MOVVconst [c])) -> (MOVVconst [int64(int16(c))]) 640 (MOVHUreg (MOVVconst [c])) -> (MOVVconst [int64(uint16(c))]) 641 (MOVWreg (MOVVconst [c])) -> (MOVVconst [int64(int32(c))]) 642 (MOVWUreg (MOVVconst [c])) -> (MOVVconst [int64(uint32(c))]) 643 (MOVVreg (MOVVconst [c])) -> (MOVVconst [c]) 644 (LoweredAtomicStore32 ptr (MOVVconst [0]) mem) -> (LoweredAtomicStorezero32 ptr mem) 645 (LoweredAtomicStore64 ptr (MOVVconst [0]) mem) -> (LoweredAtomicStorezero64 ptr mem) 646 (LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) -> (LoweredAtomicAddconst32 [c] ptr mem) 647 (LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) -> (LoweredAtomicAddconst64 [c] ptr mem) 648 649 // constant comparisons 650 (SGTconst [c] (MOVVconst [d])) && int64(c)>int64(d) -> (MOVVconst [1]) 651 (SGTconst [c] (MOVVconst [d])) && int64(c)<=int64(d) -> (MOVVconst [0]) 652 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) -> (MOVVconst [1]) 653 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) -> (MOVVconst [0]) 654 655 // other known comparisons 656 (SGTconst [c] (MOVBreg _)) && 0x7f < int64(c) -> (MOVVconst [1]) 657 (SGTconst [c] (MOVBreg _)) && int64(c) <= -0x80 -> (MOVVconst [0]) 658 (SGTconst [c] (MOVBUreg _)) && 0xff < int64(c) -> (MOVVconst [1]) 659 (SGTconst [c] (MOVBUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 660 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) -> (MOVVconst [1]) 661 (SGTconst [c] (MOVHreg _)) && 0x7fff < int64(c) -> (MOVVconst [1]) 662 (SGTconst [c] (MOVHreg _)) && int64(c) <= -0x8000 -> (MOVVconst [0]) 663 (SGTconst [c] (MOVHUreg _)) && 0xffff < int64(c) -> (MOVVconst [1]) 664 (SGTconst [c] (MOVHUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 665 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) -> (MOVVconst [1]) 666 (SGTconst [c] (MOVWUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 667 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c -> (MOVVconst [1]) 668 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) -> (MOVVconst [1]) 669 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 1<<uint64(64-d) <= c -> (MOVVconst [1]) 670 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 1<<uint64(64-d) <= uint64(c) -> (MOVVconst [1]) 671 672 // absorb constants into branches 673 (EQ (MOVVconst [0]) yes no) -> (First nil yes no) 674 (EQ (MOVVconst [c]) yes no) && c != 0 -> (First nil no yes) 675 (NE (MOVVconst [0]) yes no) -> (First nil no yes) 676 (NE (MOVVconst [c]) yes no) && c != 0 -> (First nil yes no) 677 (LTZ (MOVVconst [c]) yes no) && c < 0 -> (First nil yes no) 678 (LTZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil no yes) 679 (LEZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil yes no) 680 (LEZ (MOVVconst [c]) yes no) && c > 0 -> (First nil no yes) 681 (GTZ (MOVVconst [c]) yes no) && c > 0 -> (First nil yes no) 682 (GTZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil no yes) 683 (GEZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil yes no) 684 (GEZ (MOVVconst [c]) yes no) && c < 0 -> (First nil no yes)