github.com/corona10/go@v0.0.0-20180224231303-7a218942be57/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 BlockARM64TBZ 74 BlockARM64TBNZ 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockS390XEQ 106 BlockS390XNE 107 BlockS390XLT 108 BlockS390XLE 109 BlockS390XGT 110 BlockS390XGE 111 BlockS390XGTF 112 BlockS390XGEF 113 114 BlockPlain 115 BlockIf 116 BlockDefer 117 BlockRet 118 BlockRetJmp 119 BlockExit 120 BlockFirst 121 ) 122 123 var blockString = [...]string{ 124 BlockInvalid: "BlockInvalid", 125 126 Block386EQ: "EQ", 127 Block386NE: "NE", 128 Block386LT: "LT", 129 Block386LE: "LE", 130 Block386GT: "GT", 131 Block386GE: "GE", 132 Block386ULT: "ULT", 133 Block386ULE: "ULE", 134 Block386UGT: "UGT", 135 Block386UGE: "UGE", 136 Block386EQF: "EQF", 137 Block386NEF: "NEF", 138 Block386ORD: "ORD", 139 Block386NAN: "NAN", 140 141 BlockAMD64EQ: "EQ", 142 BlockAMD64NE: "NE", 143 BlockAMD64LT: "LT", 144 BlockAMD64LE: "LE", 145 BlockAMD64GT: "GT", 146 BlockAMD64GE: "GE", 147 BlockAMD64ULT: "ULT", 148 BlockAMD64ULE: "ULE", 149 BlockAMD64UGT: "UGT", 150 BlockAMD64UGE: "UGE", 151 BlockAMD64EQF: "EQF", 152 BlockAMD64NEF: "NEF", 153 BlockAMD64ORD: "ORD", 154 BlockAMD64NAN: "NAN", 155 156 BlockARMEQ: "EQ", 157 BlockARMNE: "NE", 158 BlockARMLT: "LT", 159 BlockARMLE: "LE", 160 BlockARMGT: "GT", 161 BlockARMGE: "GE", 162 BlockARMULT: "ULT", 163 BlockARMULE: "ULE", 164 BlockARMUGT: "UGT", 165 BlockARMUGE: "UGE", 166 167 BlockARM64EQ: "EQ", 168 BlockARM64NE: "NE", 169 BlockARM64LT: "LT", 170 BlockARM64LE: "LE", 171 BlockARM64GT: "GT", 172 BlockARM64GE: "GE", 173 BlockARM64ULT: "ULT", 174 BlockARM64ULE: "ULE", 175 BlockARM64UGT: "UGT", 176 BlockARM64UGE: "UGE", 177 BlockARM64Z: "Z", 178 BlockARM64NZ: "NZ", 179 BlockARM64ZW: "ZW", 180 BlockARM64NZW: "NZW", 181 BlockARM64TBZ: "TBZ", 182 BlockARM64TBNZ: "TBNZ", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockS390XEQ: "EQ", 214 BlockS390XNE: "NE", 215 BlockS390XLT: "LT", 216 BlockS390XLE: "LE", 217 BlockS390XGT: "GT", 218 BlockS390XGE: "GE", 219 BlockS390XGTF: "GTF", 220 BlockS390XGEF: "GEF", 221 222 BlockPlain: "Plain", 223 BlockIf: "If", 224 BlockDefer: "Defer", 225 BlockRet: "Ret", 226 BlockRetJmp: "RetJmp", 227 BlockExit: "Exit", 228 BlockFirst: "First", 229 } 230 231 func (k BlockKind) String() string { return blockString[k] } 232 233 const ( 234 OpInvalid Op = iota 235 236 Op386ADDSS 237 Op386ADDSD 238 Op386SUBSS 239 Op386SUBSD 240 Op386MULSS 241 Op386MULSD 242 Op386DIVSS 243 Op386DIVSD 244 Op386MOVSSload 245 Op386MOVSDload 246 Op386MOVSSconst 247 Op386MOVSDconst 248 Op386MOVSSloadidx1 249 Op386MOVSSloadidx4 250 Op386MOVSDloadidx1 251 Op386MOVSDloadidx8 252 Op386MOVSSstore 253 Op386MOVSDstore 254 Op386MOVSSstoreidx1 255 Op386MOVSSstoreidx4 256 Op386MOVSDstoreidx1 257 Op386MOVSDstoreidx8 258 Op386ADDL 259 Op386ADDLconst 260 Op386ADDLcarry 261 Op386ADDLconstcarry 262 Op386ADCL 263 Op386ADCLconst 264 Op386SUBL 265 Op386SUBLconst 266 Op386SUBLcarry 267 Op386SUBLconstcarry 268 Op386SBBL 269 Op386SBBLconst 270 Op386MULL 271 Op386MULLconst 272 Op386HMULL 273 Op386HMULLU 274 Op386MULLQU 275 Op386AVGLU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLinter 394 Op386DUFFCOPY 395 Op386REPMOVSL 396 Op386InvertFlags 397 Op386LoweredGetG 398 Op386LoweredGetClosurePtr 399 Op386LoweredGetCallerPC 400 Op386LoweredGetCallerSP 401 Op386LoweredNilCheck 402 Op386LoweredWB 403 Op386MOVLconvert 404 Op386FlagEQ 405 Op386FlagLT_ULT 406 Op386FlagLT_UGT 407 Op386FlagGT_UGT 408 Op386FlagGT_ULT 409 Op386FCHS 410 Op386MOVSSconst1 411 Op386MOVSDconst1 412 Op386MOVSSconst2 413 Op386MOVSDconst2 414 415 OpAMD64ADDSS 416 OpAMD64ADDSD 417 OpAMD64SUBSS 418 OpAMD64SUBSD 419 OpAMD64MULSS 420 OpAMD64MULSD 421 OpAMD64DIVSS 422 OpAMD64DIVSD 423 OpAMD64MOVSSload 424 OpAMD64MOVSDload 425 OpAMD64MOVSSconst 426 OpAMD64MOVSDconst 427 OpAMD64MOVSSloadidx1 428 OpAMD64MOVSSloadidx4 429 OpAMD64MOVSDloadidx1 430 OpAMD64MOVSDloadidx8 431 OpAMD64MOVSSstore 432 OpAMD64MOVSDstore 433 OpAMD64MOVSSstoreidx1 434 OpAMD64MOVSSstoreidx4 435 OpAMD64MOVSDstoreidx1 436 OpAMD64MOVSDstoreidx8 437 OpAMD64ADDSSmem 438 OpAMD64ADDSDmem 439 OpAMD64SUBSSmem 440 OpAMD64SUBSDmem 441 OpAMD64MULSSmem 442 OpAMD64MULSDmem 443 OpAMD64ADDQ 444 OpAMD64ADDL 445 OpAMD64ADDQconst 446 OpAMD64ADDLconst 447 OpAMD64ADDQconstmem 448 OpAMD64ADDLconstmem 449 OpAMD64SUBQ 450 OpAMD64SUBL 451 OpAMD64SUBQconst 452 OpAMD64SUBLconst 453 OpAMD64MULQ 454 OpAMD64MULL 455 OpAMD64MULQconst 456 OpAMD64MULLconst 457 OpAMD64HMULQ 458 OpAMD64HMULL 459 OpAMD64HMULQU 460 OpAMD64HMULLU 461 OpAMD64AVGQU 462 OpAMD64DIVQ 463 OpAMD64DIVL 464 OpAMD64DIVW 465 OpAMD64DIVQU 466 OpAMD64DIVLU 467 OpAMD64DIVWU 468 OpAMD64MULQU2 469 OpAMD64DIVQU2 470 OpAMD64ANDQ 471 OpAMD64ANDL 472 OpAMD64ANDQconst 473 OpAMD64ANDLconst 474 OpAMD64ORQ 475 OpAMD64ORL 476 OpAMD64ORQconst 477 OpAMD64ORLconst 478 OpAMD64XORQ 479 OpAMD64XORL 480 OpAMD64XORQconst 481 OpAMD64XORLconst 482 OpAMD64CMPQ 483 OpAMD64CMPL 484 OpAMD64CMPW 485 OpAMD64CMPB 486 OpAMD64CMPQconst 487 OpAMD64CMPLconst 488 OpAMD64CMPWconst 489 OpAMD64CMPBconst 490 OpAMD64UCOMISS 491 OpAMD64UCOMISD 492 OpAMD64BTL 493 OpAMD64BTQ 494 OpAMD64BTLconst 495 OpAMD64BTQconst 496 OpAMD64TESTQ 497 OpAMD64TESTL 498 OpAMD64TESTW 499 OpAMD64TESTB 500 OpAMD64TESTQconst 501 OpAMD64TESTLconst 502 OpAMD64TESTWconst 503 OpAMD64TESTBconst 504 OpAMD64SHLQ 505 OpAMD64SHLL 506 OpAMD64SHLQconst 507 OpAMD64SHLLconst 508 OpAMD64SHRQ 509 OpAMD64SHRL 510 OpAMD64SHRW 511 OpAMD64SHRB 512 OpAMD64SHRQconst 513 OpAMD64SHRLconst 514 OpAMD64SHRWconst 515 OpAMD64SHRBconst 516 OpAMD64SARQ 517 OpAMD64SARL 518 OpAMD64SARW 519 OpAMD64SARB 520 OpAMD64SARQconst 521 OpAMD64SARLconst 522 OpAMD64SARWconst 523 OpAMD64SARBconst 524 OpAMD64ROLQ 525 OpAMD64ROLL 526 OpAMD64ROLW 527 OpAMD64ROLB 528 OpAMD64RORQ 529 OpAMD64RORL 530 OpAMD64RORW 531 OpAMD64RORB 532 OpAMD64ROLQconst 533 OpAMD64ROLLconst 534 OpAMD64ROLWconst 535 OpAMD64ROLBconst 536 OpAMD64ADDLmem 537 OpAMD64ADDQmem 538 OpAMD64SUBQmem 539 OpAMD64SUBLmem 540 OpAMD64ANDLmem 541 OpAMD64ANDQmem 542 OpAMD64ORQmem 543 OpAMD64ORLmem 544 OpAMD64XORQmem 545 OpAMD64XORLmem 546 OpAMD64NEGQ 547 OpAMD64NEGL 548 OpAMD64NOTQ 549 OpAMD64NOTL 550 OpAMD64BSFQ 551 OpAMD64BSFL 552 OpAMD64BSRQ 553 OpAMD64BSRL 554 OpAMD64CMOVQEQ 555 OpAMD64CMOVLEQ 556 OpAMD64BSWAPQ 557 OpAMD64BSWAPL 558 OpAMD64POPCNTQ 559 OpAMD64POPCNTL 560 OpAMD64SQRTSD 561 OpAMD64ROUNDSD 562 OpAMD64SBBQcarrymask 563 OpAMD64SBBLcarrymask 564 OpAMD64SETEQ 565 OpAMD64SETNE 566 OpAMD64SETL 567 OpAMD64SETLE 568 OpAMD64SETG 569 OpAMD64SETGE 570 OpAMD64SETB 571 OpAMD64SETBE 572 OpAMD64SETA 573 OpAMD64SETAE 574 OpAMD64SETEQmem 575 OpAMD64SETNEmem 576 OpAMD64SETLmem 577 OpAMD64SETLEmem 578 OpAMD64SETGmem 579 OpAMD64SETGEmem 580 OpAMD64SETBmem 581 OpAMD64SETBEmem 582 OpAMD64SETAmem 583 OpAMD64SETAEmem 584 OpAMD64SETEQF 585 OpAMD64SETNEF 586 OpAMD64SETORD 587 OpAMD64SETNAN 588 OpAMD64SETGF 589 OpAMD64SETGEF 590 OpAMD64MOVBQSX 591 OpAMD64MOVBQZX 592 OpAMD64MOVWQSX 593 OpAMD64MOVWQZX 594 OpAMD64MOVLQSX 595 OpAMD64MOVLQZX 596 OpAMD64MOVLconst 597 OpAMD64MOVQconst 598 OpAMD64CVTTSD2SL 599 OpAMD64CVTTSD2SQ 600 OpAMD64CVTTSS2SL 601 OpAMD64CVTTSS2SQ 602 OpAMD64CVTSL2SS 603 OpAMD64CVTSL2SD 604 OpAMD64CVTSQ2SS 605 OpAMD64CVTSQ2SD 606 OpAMD64CVTSD2SS 607 OpAMD64CVTSS2SD 608 OpAMD64MOVQi2f 609 OpAMD64MOVQf2i 610 OpAMD64MOVLi2f 611 OpAMD64MOVLf2i 612 OpAMD64PXOR 613 OpAMD64LEAQ 614 OpAMD64LEAQ1 615 OpAMD64LEAQ2 616 OpAMD64LEAQ4 617 OpAMD64LEAQ8 618 OpAMD64LEAL 619 OpAMD64MOVBload 620 OpAMD64MOVBQSXload 621 OpAMD64MOVWload 622 OpAMD64MOVWQSXload 623 OpAMD64MOVLload 624 OpAMD64MOVLQSXload 625 OpAMD64MOVQload 626 OpAMD64MOVBstore 627 OpAMD64MOVWstore 628 OpAMD64MOVLstore 629 OpAMD64MOVQstore 630 OpAMD64MOVOload 631 OpAMD64MOVOstore 632 OpAMD64MOVBloadidx1 633 OpAMD64MOVWloadidx1 634 OpAMD64MOVWloadidx2 635 OpAMD64MOVLloadidx1 636 OpAMD64MOVLloadidx4 637 OpAMD64MOVLloadidx8 638 OpAMD64MOVQloadidx1 639 OpAMD64MOVQloadidx8 640 OpAMD64MOVBstoreidx1 641 OpAMD64MOVWstoreidx1 642 OpAMD64MOVWstoreidx2 643 OpAMD64MOVLstoreidx1 644 OpAMD64MOVLstoreidx4 645 OpAMD64MOVLstoreidx8 646 OpAMD64MOVQstoreidx1 647 OpAMD64MOVQstoreidx8 648 OpAMD64MOVBstoreconst 649 OpAMD64MOVWstoreconst 650 OpAMD64MOVLstoreconst 651 OpAMD64MOVQstoreconst 652 OpAMD64MOVBstoreconstidx1 653 OpAMD64MOVWstoreconstidx1 654 OpAMD64MOVWstoreconstidx2 655 OpAMD64MOVLstoreconstidx1 656 OpAMD64MOVLstoreconstidx4 657 OpAMD64MOVQstoreconstidx1 658 OpAMD64MOVQstoreconstidx8 659 OpAMD64DUFFZERO 660 OpAMD64MOVOconst 661 OpAMD64REPSTOSQ 662 OpAMD64CALLstatic 663 OpAMD64CALLclosure 664 OpAMD64CALLinter 665 OpAMD64DUFFCOPY 666 OpAMD64REPMOVSQ 667 OpAMD64InvertFlags 668 OpAMD64LoweredGetG 669 OpAMD64LoweredGetClosurePtr 670 OpAMD64LoweredGetCallerPC 671 OpAMD64LoweredGetCallerSP 672 OpAMD64LoweredNilCheck 673 OpAMD64LoweredWB 674 OpAMD64MOVQconvert 675 OpAMD64MOVLconvert 676 OpAMD64FlagEQ 677 OpAMD64FlagLT_ULT 678 OpAMD64FlagLT_UGT 679 OpAMD64FlagGT_UGT 680 OpAMD64FlagGT_ULT 681 OpAMD64MOVLatomicload 682 OpAMD64MOVQatomicload 683 OpAMD64XCHGL 684 OpAMD64XCHGQ 685 OpAMD64XADDLlock 686 OpAMD64XADDQlock 687 OpAMD64AddTupleFirst32 688 OpAMD64AddTupleFirst64 689 OpAMD64CMPXCHGLlock 690 OpAMD64CMPXCHGQlock 691 OpAMD64ANDBlock 692 OpAMD64ORBlock 693 694 OpARMADD 695 OpARMADDconst 696 OpARMSUB 697 OpARMSUBconst 698 OpARMRSB 699 OpARMRSBconst 700 OpARMMUL 701 OpARMHMUL 702 OpARMHMULU 703 OpARMCALLudiv 704 OpARMADDS 705 OpARMADDSconst 706 OpARMADC 707 OpARMADCconst 708 OpARMSUBS 709 OpARMSUBSconst 710 OpARMRSBSconst 711 OpARMSBC 712 OpARMSBCconst 713 OpARMRSCconst 714 OpARMMULLU 715 OpARMMULA 716 OpARMMULS 717 OpARMADDF 718 OpARMADDD 719 OpARMSUBF 720 OpARMSUBD 721 OpARMMULF 722 OpARMMULD 723 OpARMNMULF 724 OpARMNMULD 725 OpARMDIVF 726 OpARMDIVD 727 OpARMMULAF 728 OpARMMULAD 729 OpARMMULSF 730 OpARMMULSD 731 OpARMAND 732 OpARMANDconst 733 OpARMOR 734 OpARMORconst 735 OpARMXOR 736 OpARMXORconst 737 OpARMBIC 738 OpARMBICconst 739 OpARMBFX 740 OpARMBFXU 741 OpARMMVN 742 OpARMNEGF 743 OpARMNEGD 744 OpARMSQRTD 745 OpARMCLZ 746 OpARMREV 747 OpARMRBIT 748 OpARMSLL 749 OpARMSLLconst 750 OpARMSRL 751 OpARMSRLconst 752 OpARMSRA 753 OpARMSRAconst 754 OpARMSRRconst 755 OpARMADDshiftLL 756 OpARMADDshiftRL 757 OpARMADDshiftRA 758 OpARMSUBshiftLL 759 OpARMSUBshiftRL 760 OpARMSUBshiftRA 761 OpARMRSBshiftLL 762 OpARMRSBshiftRL 763 OpARMRSBshiftRA 764 OpARMANDshiftLL 765 OpARMANDshiftRL 766 OpARMANDshiftRA 767 OpARMORshiftLL 768 OpARMORshiftRL 769 OpARMORshiftRA 770 OpARMXORshiftLL 771 OpARMXORshiftRL 772 OpARMXORshiftRA 773 OpARMXORshiftRR 774 OpARMBICshiftLL 775 OpARMBICshiftRL 776 OpARMBICshiftRA 777 OpARMMVNshiftLL 778 OpARMMVNshiftRL 779 OpARMMVNshiftRA 780 OpARMADCshiftLL 781 OpARMADCshiftRL 782 OpARMADCshiftRA 783 OpARMSBCshiftLL 784 OpARMSBCshiftRL 785 OpARMSBCshiftRA 786 OpARMRSCshiftLL 787 OpARMRSCshiftRL 788 OpARMRSCshiftRA 789 OpARMADDSshiftLL 790 OpARMADDSshiftRL 791 OpARMADDSshiftRA 792 OpARMSUBSshiftLL 793 OpARMSUBSshiftRL 794 OpARMSUBSshiftRA 795 OpARMRSBSshiftLL 796 OpARMRSBSshiftRL 797 OpARMRSBSshiftRA 798 OpARMADDshiftLLreg 799 OpARMADDshiftRLreg 800 OpARMADDshiftRAreg 801 OpARMSUBshiftLLreg 802 OpARMSUBshiftRLreg 803 OpARMSUBshiftRAreg 804 OpARMRSBshiftLLreg 805 OpARMRSBshiftRLreg 806 OpARMRSBshiftRAreg 807 OpARMANDshiftLLreg 808 OpARMANDshiftRLreg 809 OpARMANDshiftRAreg 810 OpARMORshiftLLreg 811 OpARMORshiftRLreg 812 OpARMORshiftRAreg 813 OpARMXORshiftLLreg 814 OpARMXORshiftRLreg 815 OpARMXORshiftRAreg 816 OpARMBICshiftLLreg 817 OpARMBICshiftRLreg 818 OpARMBICshiftRAreg 819 OpARMMVNshiftLLreg 820 OpARMMVNshiftRLreg 821 OpARMMVNshiftRAreg 822 OpARMADCshiftLLreg 823 OpARMADCshiftRLreg 824 OpARMADCshiftRAreg 825 OpARMSBCshiftLLreg 826 OpARMSBCshiftRLreg 827 OpARMSBCshiftRAreg 828 OpARMRSCshiftLLreg 829 OpARMRSCshiftRLreg 830 OpARMRSCshiftRAreg 831 OpARMADDSshiftLLreg 832 OpARMADDSshiftRLreg 833 OpARMADDSshiftRAreg 834 OpARMSUBSshiftLLreg 835 OpARMSUBSshiftRLreg 836 OpARMSUBSshiftRAreg 837 OpARMRSBSshiftLLreg 838 OpARMRSBSshiftRLreg 839 OpARMRSBSshiftRAreg 840 OpARMCMP 841 OpARMCMPconst 842 OpARMCMN 843 OpARMCMNconst 844 OpARMTST 845 OpARMTSTconst 846 OpARMTEQ 847 OpARMTEQconst 848 OpARMCMPF 849 OpARMCMPD 850 OpARMCMPshiftLL 851 OpARMCMPshiftRL 852 OpARMCMPshiftRA 853 OpARMCMNshiftLL 854 OpARMCMNshiftRL 855 OpARMCMNshiftRA 856 OpARMTSTshiftLL 857 OpARMTSTshiftRL 858 OpARMTSTshiftRA 859 OpARMTEQshiftLL 860 OpARMTEQshiftRL 861 OpARMTEQshiftRA 862 OpARMCMPshiftLLreg 863 OpARMCMPshiftRLreg 864 OpARMCMPshiftRAreg 865 OpARMCMNshiftLLreg 866 OpARMCMNshiftRLreg 867 OpARMCMNshiftRAreg 868 OpARMTSTshiftLLreg 869 OpARMTSTshiftRLreg 870 OpARMTSTshiftRAreg 871 OpARMTEQshiftLLreg 872 OpARMTEQshiftRLreg 873 OpARMTEQshiftRAreg 874 OpARMCMPF0 875 OpARMCMPD0 876 OpARMMOVWconst 877 OpARMMOVFconst 878 OpARMMOVDconst 879 OpARMMOVWaddr 880 OpARMMOVBload 881 OpARMMOVBUload 882 OpARMMOVHload 883 OpARMMOVHUload 884 OpARMMOVWload 885 OpARMMOVFload 886 OpARMMOVDload 887 OpARMMOVBstore 888 OpARMMOVHstore 889 OpARMMOVWstore 890 OpARMMOVFstore 891 OpARMMOVDstore 892 OpARMMOVWloadidx 893 OpARMMOVWloadshiftLL 894 OpARMMOVWloadshiftRL 895 OpARMMOVWloadshiftRA 896 OpARMMOVBUloadidx 897 OpARMMOVBloadidx 898 OpARMMOVHUloadidx 899 OpARMMOVHloadidx 900 OpARMMOVWstoreidx 901 OpARMMOVWstoreshiftLL 902 OpARMMOVWstoreshiftRL 903 OpARMMOVWstoreshiftRA 904 OpARMMOVBstoreidx 905 OpARMMOVHstoreidx 906 OpARMMOVBreg 907 OpARMMOVBUreg 908 OpARMMOVHreg 909 OpARMMOVHUreg 910 OpARMMOVWreg 911 OpARMMOVWnop 912 OpARMMOVWF 913 OpARMMOVWD 914 OpARMMOVWUF 915 OpARMMOVWUD 916 OpARMMOVFW 917 OpARMMOVDW 918 OpARMMOVFWU 919 OpARMMOVDWU 920 OpARMMOVFD 921 OpARMMOVDF 922 OpARMCMOVWHSconst 923 OpARMCMOVWLSconst 924 OpARMSRAcond 925 OpARMCALLstatic 926 OpARMCALLclosure 927 OpARMCALLinter 928 OpARMLoweredNilCheck 929 OpARMEqual 930 OpARMNotEqual 931 OpARMLessThan 932 OpARMLessEqual 933 OpARMGreaterThan 934 OpARMGreaterEqual 935 OpARMLessThanU 936 OpARMLessEqualU 937 OpARMGreaterThanU 938 OpARMGreaterEqualU 939 OpARMDUFFZERO 940 OpARMDUFFCOPY 941 OpARMLoweredZero 942 OpARMLoweredMove 943 OpARMLoweredGetClosurePtr 944 OpARMLoweredGetCallerSP 945 OpARMMOVWconvert 946 OpARMFlagEQ 947 OpARMFlagLT_ULT 948 OpARMFlagLT_UGT 949 OpARMFlagGT_UGT 950 OpARMFlagGT_ULT 951 OpARMInvertFlags 952 OpARMLoweredWB 953 954 OpARM64ADD 955 OpARM64ADDconst 956 OpARM64SUB 957 OpARM64SUBconst 958 OpARM64MUL 959 OpARM64MULW 960 OpARM64MNEG 961 OpARM64MNEGW 962 OpARM64MULH 963 OpARM64UMULH 964 OpARM64MULL 965 OpARM64UMULL 966 OpARM64DIV 967 OpARM64UDIV 968 OpARM64DIVW 969 OpARM64UDIVW 970 OpARM64MOD 971 OpARM64UMOD 972 OpARM64MODW 973 OpARM64UMODW 974 OpARM64FADDS 975 OpARM64FADDD 976 OpARM64FSUBS 977 OpARM64FSUBD 978 OpARM64FMULS 979 OpARM64FMULD 980 OpARM64FNMULS 981 OpARM64FNMULD 982 OpARM64FDIVS 983 OpARM64FDIVD 984 OpARM64AND 985 OpARM64ANDconst 986 OpARM64OR 987 OpARM64ORconst 988 OpARM64XOR 989 OpARM64XORconst 990 OpARM64BIC 991 OpARM64BICconst 992 OpARM64MVN 993 OpARM64NEG 994 OpARM64FNEGS 995 OpARM64FNEGD 996 OpARM64FSQRTD 997 OpARM64REV 998 OpARM64REVW 999 OpARM64REV16W 1000 OpARM64RBIT 1001 OpARM64RBITW 1002 OpARM64CLZ 1003 OpARM64CLZW 1004 OpARM64VCNT 1005 OpARM64VUADDLV 1006 OpARM64LoweredRound32F 1007 OpARM64LoweredRound64F 1008 OpARM64FMADDS 1009 OpARM64FMADDD 1010 OpARM64FNMADDS 1011 OpARM64FNMADDD 1012 OpARM64FMSUBS 1013 OpARM64FMSUBD 1014 OpARM64FNMSUBS 1015 OpARM64FNMSUBD 1016 OpARM64SLL 1017 OpARM64SLLconst 1018 OpARM64SRL 1019 OpARM64SRLconst 1020 OpARM64SRA 1021 OpARM64SRAconst 1022 OpARM64RORconst 1023 OpARM64RORWconst 1024 OpARM64CMP 1025 OpARM64CMPconst 1026 OpARM64CMPW 1027 OpARM64CMPWconst 1028 OpARM64CMN 1029 OpARM64CMNconst 1030 OpARM64CMNW 1031 OpARM64CMNWconst 1032 OpARM64FCMPS 1033 OpARM64FCMPD 1034 OpARM64ADDshiftLL 1035 OpARM64ADDshiftRL 1036 OpARM64ADDshiftRA 1037 OpARM64SUBshiftLL 1038 OpARM64SUBshiftRL 1039 OpARM64SUBshiftRA 1040 OpARM64ANDshiftLL 1041 OpARM64ANDshiftRL 1042 OpARM64ANDshiftRA 1043 OpARM64ORshiftLL 1044 OpARM64ORshiftRL 1045 OpARM64ORshiftRA 1046 OpARM64XORshiftLL 1047 OpARM64XORshiftRL 1048 OpARM64XORshiftRA 1049 OpARM64BICshiftLL 1050 OpARM64BICshiftRL 1051 OpARM64BICshiftRA 1052 OpARM64CMPshiftLL 1053 OpARM64CMPshiftRL 1054 OpARM64CMPshiftRA 1055 OpARM64MOVDconst 1056 OpARM64FMOVSconst 1057 OpARM64FMOVDconst 1058 OpARM64MOVDaddr 1059 OpARM64MOVBload 1060 OpARM64MOVBUload 1061 OpARM64MOVHload 1062 OpARM64MOVHUload 1063 OpARM64MOVWload 1064 OpARM64MOVWUload 1065 OpARM64MOVDload 1066 OpARM64FMOVSload 1067 OpARM64FMOVDload 1068 OpARM64MOVBstore 1069 OpARM64MOVHstore 1070 OpARM64MOVWstore 1071 OpARM64MOVDstore 1072 OpARM64STP 1073 OpARM64FMOVSstore 1074 OpARM64FMOVDstore 1075 OpARM64MOVBstorezero 1076 OpARM64MOVHstorezero 1077 OpARM64MOVWstorezero 1078 OpARM64MOVDstorezero 1079 OpARM64MOVQstorezero 1080 OpARM64FMOVDgpfp 1081 OpARM64FMOVDfpgp 1082 OpARM64MOVBreg 1083 OpARM64MOVBUreg 1084 OpARM64MOVHreg 1085 OpARM64MOVHUreg 1086 OpARM64MOVWreg 1087 OpARM64MOVWUreg 1088 OpARM64MOVDreg 1089 OpARM64MOVDnop 1090 OpARM64SCVTFWS 1091 OpARM64SCVTFWD 1092 OpARM64UCVTFWS 1093 OpARM64UCVTFWD 1094 OpARM64SCVTFS 1095 OpARM64SCVTFD 1096 OpARM64UCVTFS 1097 OpARM64UCVTFD 1098 OpARM64FCVTZSSW 1099 OpARM64FCVTZSDW 1100 OpARM64FCVTZUSW 1101 OpARM64FCVTZUDW 1102 OpARM64FCVTZSS 1103 OpARM64FCVTZSD 1104 OpARM64FCVTZUS 1105 OpARM64FCVTZUD 1106 OpARM64FCVTSD 1107 OpARM64FCVTDS 1108 OpARM64FRINTAD 1109 OpARM64FRINTMD 1110 OpARM64FRINTPD 1111 OpARM64FRINTZD 1112 OpARM64CSEL 1113 OpARM64CSEL0 1114 OpARM64CALLstatic 1115 OpARM64CALLclosure 1116 OpARM64CALLinter 1117 OpARM64LoweredNilCheck 1118 OpARM64Equal 1119 OpARM64NotEqual 1120 OpARM64LessThan 1121 OpARM64LessEqual 1122 OpARM64GreaterThan 1123 OpARM64GreaterEqual 1124 OpARM64LessThanU 1125 OpARM64LessEqualU 1126 OpARM64GreaterThanU 1127 OpARM64GreaterEqualU 1128 OpARM64DUFFZERO 1129 OpARM64LoweredZero 1130 OpARM64DUFFCOPY 1131 OpARM64LoweredMove 1132 OpARM64LoweredGetClosurePtr 1133 OpARM64LoweredGetCallerSP 1134 OpARM64MOVDconvert 1135 OpARM64FlagEQ 1136 OpARM64FlagLT_ULT 1137 OpARM64FlagLT_UGT 1138 OpARM64FlagGT_UGT 1139 OpARM64FlagGT_ULT 1140 OpARM64InvertFlags 1141 OpARM64LDAR 1142 OpARM64LDARW 1143 OpARM64STLR 1144 OpARM64STLRW 1145 OpARM64LoweredAtomicExchange64 1146 OpARM64LoweredAtomicExchange32 1147 OpARM64LoweredAtomicAdd64 1148 OpARM64LoweredAtomicAdd32 1149 OpARM64LoweredAtomicCas64 1150 OpARM64LoweredAtomicCas32 1151 OpARM64LoweredAtomicAnd8 1152 OpARM64LoweredAtomicOr8 1153 OpARM64LoweredWB 1154 1155 OpMIPSADD 1156 OpMIPSADDconst 1157 OpMIPSSUB 1158 OpMIPSSUBconst 1159 OpMIPSMUL 1160 OpMIPSMULT 1161 OpMIPSMULTU 1162 OpMIPSDIV 1163 OpMIPSDIVU 1164 OpMIPSADDF 1165 OpMIPSADDD 1166 OpMIPSSUBF 1167 OpMIPSSUBD 1168 OpMIPSMULF 1169 OpMIPSMULD 1170 OpMIPSDIVF 1171 OpMIPSDIVD 1172 OpMIPSAND 1173 OpMIPSANDconst 1174 OpMIPSOR 1175 OpMIPSORconst 1176 OpMIPSXOR 1177 OpMIPSXORconst 1178 OpMIPSNOR 1179 OpMIPSNORconst 1180 OpMIPSNEG 1181 OpMIPSNEGF 1182 OpMIPSNEGD 1183 OpMIPSSQRTD 1184 OpMIPSSLL 1185 OpMIPSSLLconst 1186 OpMIPSSRL 1187 OpMIPSSRLconst 1188 OpMIPSSRA 1189 OpMIPSSRAconst 1190 OpMIPSCLZ 1191 OpMIPSSGT 1192 OpMIPSSGTconst 1193 OpMIPSSGTzero 1194 OpMIPSSGTU 1195 OpMIPSSGTUconst 1196 OpMIPSSGTUzero 1197 OpMIPSCMPEQF 1198 OpMIPSCMPEQD 1199 OpMIPSCMPGEF 1200 OpMIPSCMPGED 1201 OpMIPSCMPGTF 1202 OpMIPSCMPGTD 1203 OpMIPSMOVWconst 1204 OpMIPSMOVFconst 1205 OpMIPSMOVDconst 1206 OpMIPSMOVWaddr 1207 OpMIPSMOVBload 1208 OpMIPSMOVBUload 1209 OpMIPSMOVHload 1210 OpMIPSMOVHUload 1211 OpMIPSMOVWload 1212 OpMIPSMOVFload 1213 OpMIPSMOVDload 1214 OpMIPSMOVBstore 1215 OpMIPSMOVHstore 1216 OpMIPSMOVWstore 1217 OpMIPSMOVFstore 1218 OpMIPSMOVDstore 1219 OpMIPSMOVBstorezero 1220 OpMIPSMOVHstorezero 1221 OpMIPSMOVWstorezero 1222 OpMIPSMOVBreg 1223 OpMIPSMOVBUreg 1224 OpMIPSMOVHreg 1225 OpMIPSMOVHUreg 1226 OpMIPSMOVWreg 1227 OpMIPSMOVWnop 1228 OpMIPSCMOVZ 1229 OpMIPSCMOVZzero 1230 OpMIPSMOVWF 1231 OpMIPSMOVWD 1232 OpMIPSTRUNCFW 1233 OpMIPSTRUNCDW 1234 OpMIPSMOVFD 1235 OpMIPSMOVDF 1236 OpMIPSCALLstatic 1237 OpMIPSCALLclosure 1238 OpMIPSCALLinter 1239 OpMIPSLoweredAtomicLoad 1240 OpMIPSLoweredAtomicStore 1241 OpMIPSLoweredAtomicStorezero 1242 OpMIPSLoweredAtomicExchange 1243 OpMIPSLoweredAtomicAdd 1244 OpMIPSLoweredAtomicAddconst 1245 OpMIPSLoweredAtomicCas 1246 OpMIPSLoweredAtomicAnd 1247 OpMIPSLoweredAtomicOr 1248 OpMIPSLoweredZero 1249 OpMIPSLoweredMove 1250 OpMIPSLoweredNilCheck 1251 OpMIPSFPFlagTrue 1252 OpMIPSFPFlagFalse 1253 OpMIPSLoweredGetClosurePtr 1254 OpMIPSLoweredGetCallerSP 1255 OpMIPSLoweredWB 1256 OpMIPSMOVWconvert 1257 1258 OpMIPS64ADDV 1259 OpMIPS64ADDVconst 1260 OpMIPS64SUBV 1261 OpMIPS64SUBVconst 1262 OpMIPS64MULV 1263 OpMIPS64MULVU 1264 OpMIPS64DIVV 1265 OpMIPS64DIVVU 1266 OpMIPS64ADDF 1267 OpMIPS64ADDD 1268 OpMIPS64SUBF 1269 OpMIPS64SUBD 1270 OpMIPS64MULF 1271 OpMIPS64MULD 1272 OpMIPS64DIVF 1273 OpMIPS64DIVD 1274 OpMIPS64AND 1275 OpMIPS64ANDconst 1276 OpMIPS64OR 1277 OpMIPS64ORconst 1278 OpMIPS64XOR 1279 OpMIPS64XORconst 1280 OpMIPS64NOR 1281 OpMIPS64NORconst 1282 OpMIPS64NEGV 1283 OpMIPS64NEGF 1284 OpMIPS64NEGD 1285 OpMIPS64SQRTD 1286 OpMIPS64SLLV 1287 OpMIPS64SLLVconst 1288 OpMIPS64SRLV 1289 OpMIPS64SRLVconst 1290 OpMIPS64SRAV 1291 OpMIPS64SRAVconst 1292 OpMIPS64SGT 1293 OpMIPS64SGTconst 1294 OpMIPS64SGTU 1295 OpMIPS64SGTUconst 1296 OpMIPS64CMPEQF 1297 OpMIPS64CMPEQD 1298 OpMIPS64CMPGEF 1299 OpMIPS64CMPGED 1300 OpMIPS64CMPGTF 1301 OpMIPS64CMPGTD 1302 OpMIPS64MOVVconst 1303 OpMIPS64MOVFconst 1304 OpMIPS64MOVDconst 1305 OpMIPS64MOVVaddr 1306 OpMIPS64MOVBload 1307 OpMIPS64MOVBUload 1308 OpMIPS64MOVHload 1309 OpMIPS64MOVHUload 1310 OpMIPS64MOVWload 1311 OpMIPS64MOVWUload 1312 OpMIPS64MOVVload 1313 OpMIPS64MOVFload 1314 OpMIPS64MOVDload 1315 OpMIPS64MOVBstore 1316 OpMIPS64MOVHstore 1317 OpMIPS64MOVWstore 1318 OpMIPS64MOVVstore 1319 OpMIPS64MOVFstore 1320 OpMIPS64MOVDstore 1321 OpMIPS64MOVBstorezero 1322 OpMIPS64MOVHstorezero 1323 OpMIPS64MOVWstorezero 1324 OpMIPS64MOVVstorezero 1325 OpMIPS64MOVBreg 1326 OpMIPS64MOVBUreg 1327 OpMIPS64MOVHreg 1328 OpMIPS64MOVHUreg 1329 OpMIPS64MOVWreg 1330 OpMIPS64MOVWUreg 1331 OpMIPS64MOVVreg 1332 OpMIPS64MOVVnop 1333 OpMIPS64MOVWF 1334 OpMIPS64MOVWD 1335 OpMIPS64MOVVF 1336 OpMIPS64MOVVD 1337 OpMIPS64TRUNCFW 1338 OpMIPS64TRUNCDW 1339 OpMIPS64TRUNCFV 1340 OpMIPS64TRUNCDV 1341 OpMIPS64MOVFD 1342 OpMIPS64MOVDF 1343 OpMIPS64CALLstatic 1344 OpMIPS64CALLclosure 1345 OpMIPS64CALLinter 1346 OpMIPS64DUFFZERO 1347 OpMIPS64LoweredZero 1348 OpMIPS64LoweredMove 1349 OpMIPS64LoweredAtomicLoad32 1350 OpMIPS64LoweredAtomicLoad64 1351 OpMIPS64LoweredAtomicStore32 1352 OpMIPS64LoweredAtomicStore64 1353 OpMIPS64LoweredAtomicStorezero32 1354 OpMIPS64LoweredAtomicStorezero64 1355 OpMIPS64LoweredAtomicExchange32 1356 OpMIPS64LoweredAtomicExchange64 1357 OpMIPS64LoweredAtomicAdd32 1358 OpMIPS64LoweredAtomicAdd64 1359 OpMIPS64LoweredAtomicAddconst32 1360 OpMIPS64LoweredAtomicAddconst64 1361 OpMIPS64LoweredAtomicCas32 1362 OpMIPS64LoweredAtomicCas64 1363 OpMIPS64LoweredNilCheck 1364 OpMIPS64FPFlagTrue 1365 OpMIPS64FPFlagFalse 1366 OpMIPS64LoweredGetClosurePtr 1367 OpMIPS64LoweredGetCallerSP 1368 OpMIPS64LoweredWB 1369 OpMIPS64MOVVconvert 1370 1371 OpPPC64ADD 1372 OpPPC64ADDconst 1373 OpPPC64FADD 1374 OpPPC64FADDS 1375 OpPPC64SUB 1376 OpPPC64FSUB 1377 OpPPC64FSUBS 1378 OpPPC64MULLD 1379 OpPPC64MULLW 1380 OpPPC64MULHD 1381 OpPPC64MULHW 1382 OpPPC64MULHDU 1383 OpPPC64MULHWU 1384 OpPPC64FMUL 1385 OpPPC64FMULS 1386 OpPPC64FMADD 1387 OpPPC64FMADDS 1388 OpPPC64FMSUB 1389 OpPPC64FMSUBS 1390 OpPPC64SRAD 1391 OpPPC64SRAW 1392 OpPPC64SRD 1393 OpPPC64SRW 1394 OpPPC64SLD 1395 OpPPC64SLW 1396 OpPPC64ROTL 1397 OpPPC64ROTLW 1398 OpPPC64ADDconstForCarry 1399 OpPPC64MaskIfNotCarry 1400 OpPPC64SRADconst 1401 OpPPC64SRAWconst 1402 OpPPC64SRDconst 1403 OpPPC64SRWconst 1404 OpPPC64SLDconst 1405 OpPPC64SLWconst 1406 OpPPC64ROTLconst 1407 OpPPC64ROTLWconst 1408 OpPPC64CNTLZD 1409 OpPPC64CNTLZW 1410 OpPPC64POPCNTD 1411 OpPPC64POPCNTW 1412 OpPPC64POPCNTB 1413 OpPPC64FDIV 1414 OpPPC64FDIVS 1415 OpPPC64DIVD 1416 OpPPC64DIVW 1417 OpPPC64DIVDU 1418 OpPPC64DIVWU 1419 OpPPC64FCTIDZ 1420 OpPPC64FCTIWZ 1421 OpPPC64FCFID 1422 OpPPC64FCFIDS 1423 OpPPC64FRSP 1424 OpPPC64MFVSRD 1425 OpPPC64MTVSRD 1426 OpPPC64AND 1427 OpPPC64ANDN 1428 OpPPC64OR 1429 OpPPC64ORN 1430 OpPPC64NOR 1431 OpPPC64XOR 1432 OpPPC64EQV 1433 OpPPC64NEG 1434 OpPPC64FNEG 1435 OpPPC64FSQRT 1436 OpPPC64FSQRTS 1437 OpPPC64FFLOOR 1438 OpPPC64FCEIL 1439 OpPPC64FTRUNC 1440 OpPPC64FABS 1441 OpPPC64FNABS 1442 OpPPC64FCPSGN 1443 OpPPC64ORconst 1444 OpPPC64XORconst 1445 OpPPC64ANDconst 1446 OpPPC64ANDCCconst 1447 OpPPC64MOVBreg 1448 OpPPC64MOVBZreg 1449 OpPPC64MOVHreg 1450 OpPPC64MOVHZreg 1451 OpPPC64MOVWreg 1452 OpPPC64MOVWZreg 1453 OpPPC64MOVBZload 1454 OpPPC64MOVHload 1455 OpPPC64MOVHZload 1456 OpPPC64MOVWload 1457 OpPPC64MOVWZload 1458 OpPPC64MOVDload 1459 OpPPC64FMOVDload 1460 OpPPC64FMOVSload 1461 OpPPC64MOVBstore 1462 OpPPC64MOVHstore 1463 OpPPC64MOVWstore 1464 OpPPC64MOVDstore 1465 OpPPC64FMOVDstore 1466 OpPPC64FMOVSstore 1467 OpPPC64MOVBstorezero 1468 OpPPC64MOVHstorezero 1469 OpPPC64MOVWstorezero 1470 OpPPC64MOVDstorezero 1471 OpPPC64MOVDaddr 1472 OpPPC64MOVDconst 1473 OpPPC64FMOVDconst 1474 OpPPC64FMOVSconst 1475 OpPPC64FCMPU 1476 OpPPC64CMP 1477 OpPPC64CMPU 1478 OpPPC64CMPW 1479 OpPPC64CMPWU 1480 OpPPC64CMPconst 1481 OpPPC64CMPUconst 1482 OpPPC64CMPWconst 1483 OpPPC64CMPWUconst 1484 OpPPC64Equal 1485 OpPPC64NotEqual 1486 OpPPC64LessThan 1487 OpPPC64FLessThan 1488 OpPPC64LessEqual 1489 OpPPC64FLessEqual 1490 OpPPC64GreaterThan 1491 OpPPC64FGreaterThan 1492 OpPPC64GreaterEqual 1493 OpPPC64FGreaterEqual 1494 OpPPC64LoweredGetClosurePtr 1495 OpPPC64LoweredGetCallerSP 1496 OpPPC64LoweredNilCheck 1497 OpPPC64LoweredRound32F 1498 OpPPC64LoweredRound64F 1499 OpPPC64MOVDconvert 1500 OpPPC64CALLstatic 1501 OpPPC64CALLclosure 1502 OpPPC64CALLinter 1503 OpPPC64LoweredZero 1504 OpPPC64LoweredMove 1505 OpPPC64LoweredAtomicStore32 1506 OpPPC64LoweredAtomicStore64 1507 OpPPC64LoweredAtomicLoad32 1508 OpPPC64LoweredAtomicLoad64 1509 OpPPC64LoweredAtomicLoadPtr 1510 OpPPC64LoweredAtomicAdd32 1511 OpPPC64LoweredAtomicAdd64 1512 OpPPC64LoweredAtomicExchange32 1513 OpPPC64LoweredAtomicExchange64 1514 OpPPC64LoweredAtomicCas64 1515 OpPPC64LoweredAtomicCas32 1516 OpPPC64LoweredAtomicAnd8 1517 OpPPC64LoweredAtomicOr8 1518 OpPPC64LoweredWB 1519 OpPPC64InvertFlags 1520 OpPPC64FlagEQ 1521 OpPPC64FlagLT 1522 OpPPC64FlagGT 1523 1524 OpS390XFADDS 1525 OpS390XFADD 1526 OpS390XFSUBS 1527 OpS390XFSUB 1528 OpS390XFMULS 1529 OpS390XFMUL 1530 OpS390XFDIVS 1531 OpS390XFDIV 1532 OpS390XFNEGS 1533 OpS390XFNEG 1534 OpS390XFMADDS 1535 OpS390XFMADD 1536 OpS390XFMSUBS 1537 OpS390XFMSUB 1538 OpS390XLPDFR 1539 OpS390XLNDFR 1540 OpS390XCPSDR 1541 OpS390XFIDBR 1542 OpS390XFMOVSload 1543 OpS390XFMOVDload 1544 OpS390XFMOVSconst 1545 OpS390XFMOVDconst 1546 OpS390XFMOVSloadidx 1547 OpS390XFMOVDloadidx 1548 OpS390XFMOVSstore 1549 OpS390XFMOVDstore 1550 OpS390XFMOVSstoreidx 1551 OpS390XFMOVDstoreidx 1552 OpS390XADD 1553 OpS390XADDW 1554 OpS390XADDconst 1555 OpS390XADDWconst 1556 OpS390XADDload 1557 OpS390XADDWload 1558 OpS390XSUB 1559 OpS390XSUBW 1560 OpS390XSUBconst 1561 OpS390XSUBWconst 1562 OpS390XSUBload 1563 OpS390XSUBWload 1564 OpS390XMULLD 1565 OpS390XMULLW 1566 OpS390XMULLDconst 1567 OpS390XMULLWconst 1568 OpS390XMULLDload 1569 OpS390XMULLWload 1570 OpS390XMULHD 1571 OpS390XMULHDU 1572 OpS390XDIVD 1573 OpS390XDIVW 1574 OpS390XDIVDU 1575 OpS390XDIVWU 1576 OpS390XMODD 1577 OpS390XMODW 1578 OpS390XMODDU 1579 OpS390XMODWU 1580 OpS390XAND 1581 OpS390XANDW 1582 OpS390XANDconst 1583 OpS390XANDWconst 1584 OpS390XANDload 1585 OpS390XANDWload 1586 OpS390XOR 1587 OpS390XORW 1588 OpS390XORconst 1589 OpS390XORWconst 1590 OpS390XORload 1591 OpS390XORWload 1592 OpS390XXOR 1593 OpS390XXORW 1594 OpS390XXORconst 1595 OpS390XXORWconst 1596 OpS390XXORload 1597 OpS390XXORWload 1598 OpS390XCMP 1599 OpS390XCMPW 1600 OpS390XCMPU 1601 OpS390XCMPWU 1602 OpS390XCMPconst 1603 OpS390XCMPWconst 1604 OpS390XCMPUconst 1605 OpS390XCMPWUconst 1606 OpS390XFCMPS 1607 OpS390XFCMP 1608 OpS390XSLD 1609 OpS390XSLW 1610 OpS390XSLDconst 1611 OpS390XSLWconst 1612 OpS390XSRD 1613 OpS390XSRW 1614 OpS390XSRDconst 1615 OpS390XSRWconst 1616 OpS390XSRAD 1617 OpS390XSRAW 1618 OpS390XSRADconst 1619 OpS390XSRAWconst 1620 OpS390XRLLGconst 1621 OpS390XRLLconst 1622 OpS390XNEG 1623 OpS390XNEGW 1624 OpS390XNOT 1625 OpS390XNOTW 1626 OpS390XFSQRT 1627 OpS390XSUBEcarrymask 1628 OpS390XSUBEWcarrymask 1629 OpS390XMOVDEQ 1630 OpS390XMOVDNE 1631 OpS390XMOVDLT 1632 OpS390XMOVDLE 1633 OpS390XMOVDGT 1634 OpS390XMOVDGE 1635 OpS390XMOVDGTnoinv 1636 OpS390XMOVDGEnoinv 1637 OpS390XMOVBreg 1638 OpS390XMOVBZreg 1639 OpS390XMOVHreg 1640 OpS390XMOVHZreg 1641 OpS390XMOVWreg 1642 OpS390XMOVWZreg 1643 OpS390XMOVDreg 1644 OpS390XMOVDnop 1645 OpS390XMOVDconst 1646 OpS390XLDGR 1647 OpS390XLGDR 1648 OpS390XCFDBRA 1649 OpS390XCGDBRA 1650 OpS390XCFEBRA 1651 OpS390XCGEBRA 1652 OpS390XCEFBRA 1653 OpS390XCDFBRA 1654 OpS390XCEGBRA 1655 OpS390XCDGBRA 1656 OpS390XLEDBR 1657 OpS390XLDEBR 1658 OpS390XMOVDaddr 1659 OpS390XMOVDaddridx 1660 OpS390XMOVBZload 1661 OpS390XMOVBload 1662 OpS390XMOVHZload 1663 OpS390XMOVHload 1664 OpS390XMOVWZload 1665 OpS390XMOVWload 1666 OpS390XMOVDload 1667 OpS390XMOVWBR 1668 OpS390XMOVDBR 1669 OpS390XMOVHBRload 1670 OpS390XMOVWBRload 1671 OpS390XMOVDBRload 1672 OpS390XMOVBstore 1673 OpS390XMOVHstore 1674 OpS390XMOVWstore 1675 OpS390XMOVDstore 1676 OpS390XMOVHBRstore 1677 OpS390XMOVWBRstore 1678 OpS390XMOVDBRstore 1679 OpS390XMVC 1680 OpS390XMOVBZloadidx 1681 OpS390XMOVBloadidx 1682 OpS390XMOVHZloadidx 1683 OpS390XMOVHloadidx 1684 OpS390XMOVWZloadidx 1685 OpS390XMOVWloadidx 1686 OpS390XMOVDloadidx 1687 OpS390XMOVHBRloadidx 1688 OpS390XMOVWBRloadidx 1689 OpS390XMOVDBRloadidx 1690 OpS390XMOVBstoreidx 1691 OpS390XMOVHstoreidx 1692 OpS390XMOVWstoreidx 1693 OpS390XMOVDstoreidx 1694 OpS390XMOVHBRstoreidx 1695 OpS390XMOVWBRstoreidx 1696 OpS390XMOVDBRstoreidx 1697 OpS390XMOVBstoreconst 1698 OpS390XMOVHstoreconst 1699 OpS390XMOVWstoreconst 1700 OpS390XMOVDstoreconst 1701 OpS390XCLEAR 1702 OpS390XCALLstatic 1703 OpS390XCALLclosure 1704 OpS390XCALLinter 1705 OpS390XInvertFlags 1706 OpS390XLoweredGetG 1707 OpS390XLoweredGetClosurePtr 1708 OpS390XLoweredGetCallerSP 1709 OpS390XLoweredNilCheck 1710 OpS390XLoweredRound32F 1711 OpS390XLoweredRound64F 1712 OpS390XLoweredWB 1713 OpS390XMOVDconvert 1714 OpS390XFlagEQ 1715 OpS390XFlagLT 1716 OpS390XFlagGT 1717 OpS390XMOVWZatomicload 1718 OpS390XMOVDatomicload 1719 OpS390XMOVWatomicstore 1720 OpS390XMOVDatomicstore 1721 OpS390XLAA 1722 OpS390XLAAG 1723 OpS390XAddTupleFirst32 1724 OpS390XAddTupleFirst64 1725 OpS390XLoweredAtomicCas32 1726 OpS390XLoweredAtomicCas64 1727 OpS390XLoweredAtomicExchange32 1728 OpS390XLoweredAtomicExchange64 1729 OpS390XFLOGR 1730 OpS390XSTMG2 1731 OpS390XSTMG3 1732 OpS390XSTMG4 1733 OpS390XSTM2 1734 OpS390XSTM3 1735 OpS390XSTM4 1736 OpS390XLoweredMove 1737 OpS390XLoweredZero 1738 1739 OpAdd8 1740 OpAdd16 1741 OpAdd32 1742 OpAdd64 1743 OpAddPtr 1744 OpAdd32F 1745 OpAdd64F 1746 OpSub8 1747 OpSub16 1748 OpSub32 1749 OpSub64 1750 OpSubPtr 1751 OpSub32F 1752 OpSub64F 1753 OpMul8 1754 OpMul16 1755 OpMul32 1756 OpMul64 1757 OpMul32F 1758 OpMul64F 1759 OpDiv32F 1760 OpDiv64F 1761 OpHmul32 1762 OpHmul32u 1763 OpHmul64 1764 OpHmul64u 1765 OpMul32uhilo 1766 OpMul64uhilo 1767 OpAvg32u 1768 OpAvg64u 1769 OpDiv8 1770 OpDiv8u 1771 OpDiv16 1772 OpDiv16u 1773 OpDiv32 1774 OpDiv32u 1775 OpDiv64 1776 OpDiv64u 1777 OpDiv128u 1778 OpMod8 1779 OpMod8u 1780 OpMod16 1781 OpMod16u 1782 OpMod32 1783 OpMod32u 1784 OpMod64 1785 OpMod64u 1786 OpAnd8 1787 OpAnd16 1788 OpAnd32 1789 OpAnd64 1790 OpOr8 1791 OpOr16 1792 OpOr32 1793 OpOr64 1794 OpXor8 1795 OpXor16 1796 OpXor32 1797 OpXor64 1798 OpLsh8x8 1799 OpLsh8x16 1800 OpLsh8x32 1801 OpLsh8x64 1802 OpLsh16x8 1803 OpLsh16x16 1804 OpLsh16x32 1805 OpLsh16x64 1806 OpLsh32x8 1807 OpLsh32x16 1808 OpLsh32x32 1809 OpLsh32x64 1810 OpLsh64x8 1811 OpLsh64x16 1812 OpLsh64x32 1813 OpLsh64x64 1814 OpRsh8x8 1815 OpRsh8x16 1816 OpRsh8x32 1817 OpRsh8x64 1818 OpRsh16x8 1819 OpRsh16x16 1820 OpRsh16x32 1821 OpRsh16x64 1822 OpRsh32x8 1823 OpRsh32x16 1824 OpRsh32x32 1825 OpRsh32x64 1826 OpRsh64x8 1827 OpRsh64x16 1828 OpRsh64x32 1829 OpRsh64x64 1830 OpRsh8Ux8 1831 OpRsh8Ux16 1832 OpRsh8Ux32 1833 OpRsh8Ux64 1834 OpRsh16Ux8 1835 OpRsh16Ux16 1836 OpRsh16Ux32 1837 OpRsh16Ux64 1838 OpRsh32Ux8 1839 OpRsh32Ux16 1840 OpRsh32Ux32 1841 OpRsh32Ux64 1842 OpRsh64Ux8 1843 OpRsh64Ux16 1844 OpRsh64Ux32 1845 OpRsh64Ux64 1846 OpEq8 1847 OpEq16 1848 OpEq32 1849 OpEq64 1850 OpEqPtr 1851 OpEqInter 1852 OpEqSlice 1853 OpEq32F 1854 OpEq64F 1855 OpNeq8 1856 OpNeq16 1857 OpNeq32 1858 OpNeq64 1859 OpNeqPtr 1860 OpNeqInter 1861 OpNeqSlice 1862 OpNeq32F 1863 OpNeq64F 1864 OpLess8 1865 OpLess8U 1866 OpLess16 1867 OpLess16U 1868 OpLess32 1869 OpLess32U 1870 OpLess64 1871 OpLess64U 1872 OpLess32F 1873 OpLess64F 1874 OpLeq8 1875 OpLeq8U 1876 OpLeq16 1877 OpLeq16U 1878 OpLeq32 1879 OpLeq32U 1880 OpLeq64 1881 OpLeq64U 1882 OpLeq32F 1883 OpLeq64F 1884 OpGreater8 1885 OpGreater8U 1886 OpGreater16 1887 OpGreater16U 1888 OpGreater32 1889 OpGreater32U 1890 OpGreater64 1891 OpGreater64U 1892 OpGreater32F 1893 OpGreater64F 1894 OpGeq8 1895 OpGeq8U 1896 OpGeq16 1897 OpGeq16U 1898 OpGeq32 1899 OpGeq32U 1900 OpGeq64 1901 OpGeq64U 1902 OpGeq32F 1903 OpGeq64F 1904 OpCondSelect 1905 OpAndB 1906 OpOrB 1907 OpEqB 1908 OpNeqB 1909 OpNot 1910 OpNeg8 1911 OpNeg16 1912 OpNeg32 1913 OpNeg64 1914 OpNeg32F 1915 OpNeg64F 1916 OpCom8 1917 OpCom16 1918 OpCom32 1919 OpCom64 1920 OpCtz32 1921 OpCtz64 1922 OpBitLen32 1923 OpBitLen64 1924 OpBswap32 1925 OpBswap64 1926 OpBitRev8 1927 OpBitRev16 1928 OpBitRev32 1929 OpBitRev64 1930 OpPopCount8 1931 OpPopCount16 1932 OpPopCount32 1933 OpPopCount64 1934 OpSqrt 1935 OpFloor 1936 OpCeil 1937 OpTrunc 1938 OpRound 1939 OpRoundToEven 1940 OpAbs 1941 OpCopysign 1942 OpPhi 1943 OpCopy 1944 OpConvert 1945 OpConstBool 1946 OpConstString 1947 OpConstNil 1948 OpConst8 1949 OpConst16 1950 OpConst32 1951 OpConst64 1952 OpConst32F 1953 OpConst64F 1954 OpConstInterface 1955 OpConstSlice 1956 OpInitMem 1957 OpArg 1958 OpAddr 1959 OpSP 1960 OpSB 1961 OpLoad 1962 OpStore 1963 OpMove 1964 OpZero 1965 OpStoreWB 1966 OpMoveWB 1967 OpZeroWB 1968 OpWB 1969 OpClosureCall 1970 OpStaticCall 1971 OpInterCall 1972 OpSignExt8to16 1973 OpSignExt8to32 1974 OpSignExt8to64 1975 OpSignExt16to32 1976 OpSignExt16to64 1977 OpSignExt32to64 1978 OpZeroExt8to16 1979 OpZeroExt8to32 1980 OpZeroExt8to64 1981 OpZeroExt16to32 1982 OpZeroExt16to64 1983 OpZeroExt32to64 1984 OpTrunc16to8 1985 OpTrunc32to8 1986 OpTrunc32to16 1987 OpTrunc64to8 1988 OpTrunc64to16 1989 OpTrunc64to32 1990 OpCvt32to32F 1991 OpCvt32to64F 1992 OpCvt64to32F 1993 OpCvt64to64F 1994 OpCvt32Fto32 1995 OpCvt32Fto64 1996 OpCvt64Fto32 1997 OpCvt64Fto64 1998 OpCvt32Fto64F 1999 OpCvt64Fto32F 2000 OpRound32F 2001 OpRound64F 2002 OpIsNonNil 2003 OpIsInBounds 2004 OpIsSliceInBounds 2005 OpNilCheck 2006 OpGetG 2007 OpGetClosurePtr 2008 OpGetCallerPC 2009 OpGetCallerSP 2010 OpPtrIndex 2011 OpOffPtr 2012 OpSliceMake 2013 OpSlicePtr 2014 OpSliceLen 2015 OpSliceCap 2016 OpComplexMake 2017 OpComplexReal 2018 OpComplexImag 2019 OpStringMake 2020 OpStringPtr 2021 OpStringLen 2022 OpIMake 2023 OpITab 2024 OpIData 2025 OpStructMake0 2026 OpStructMake1 2027 OpStructMake2 2028 OpStructMake3 2029 OpStructMake4 2030 OpStructSelect 2031 OpArrayMake0 2032 OpArrayMake1 2033 OpArraySelect 2034 OpStoreReg 2035 OpLoadReg 2036 OpFwdRef 2037 OpUnknown 2038 OpVarDef 2039 OpVarKill 2040 OpVarLive 2041 OpKeepAlive 2042 OpInt64Make 2043 OpInt64Hi 2044 OpInt64Lo 2045 OpAdd32carry 2046 OpAdd32withcarry 2047 OpSub32carry 2048 OpSub32withcarry 2049 OpSignmask 2050 OpZeromask 2051 OpSlicemask 2052 OpCvt32Uto32F 2053 OpCvt32Uto64F 2054 OpCvt32Fto32U 2055 OpCvt64Fto32U 2056 OpCvt64Uto32F 2057 OpCvt64Uto64F 2058 OpCvt32Fto64U 2059 OpCvt64Fto64U 2060 OpSelect0 2061 OpSelect1 2062 OpAtomicLoad32 2063 OpAtomicLoad64 2064 OpAtomicLoadPtr 2065 OpAtomicStore32 2066 OpAtomicStore64 2067 OpAtomicStorePtrNoWB 2068 OpAtomicExchange32 2069 OpAtomicExchange64 2070 OpAtomicAdd32 2071 OpAtomicAdd64 2072 OpAtomicCompareAndSwap32 2073 OpAtomicCompareAndSwap64 2074 OpAtomicAnd8 2075 OpAtomicOr8 2076 OpClobber 2077 ) 2078 2079 var opcodeTable = [...]opInfo{ 2080 {name: "OpInvalid"}, 2081 2082 { 2083 name: "ADDSS", 2084 argLen: 2, 2085 commutative: true, 2086 resultInArg0: true, 2087 usesScratch: true, 2088 asm: x86.AADDSS, 2089 reg: regInfo{ 2090 inputs: []inputInfo{ 2091 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2092 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2093 }, 2094 outputs: []outputInfo{ 2095 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2096 }, 2097 }, 2098 }, 2099 { 2100 name: "ADDSD", 2101 argLen: 2, 2102 commutative: true, 2103 resultInArg0: true, 2104 asm: x86.AADDSD, 2105 reg: regInfo{ 2106 inputs: []inputInfo{ 2107 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2108 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2109 }, 2110 outputs: []outputInfo{ 2111 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2112 }, 2113 }, 2114 }, 2115 { 2116 name: "SUBSS", 2117 argLen: 2, 2118 resultInArg0: true, 2119 usesScratch: true, 2120 asm: x86.ASUBSS, 2121 reg: regInfo{ 2122 inputs: []inputInfo{ 2123 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2124 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2125 }, 2126 outputs: []outputInfo{ 2127 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2128 }, 2129 }, 2130 }, 2131 { 2132 name: "SUBSD", 2133 argLen: 2, 2134 resultInArg0: true, 2135 asm: x86.ASUBSD, 2136 reg: regInfo{ 2137 inputs: []inputInfo{ 2138 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2139 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2140 }, 2141 outputs: []outputInfo{ 2142 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2143 }, 2144 }, 2145 }, 2146 { 2147 name: "MULSS", 2148 argLen: 2, 2149 commutative: true, 2150 resultInArg0: true, 2151 usesScratch: true, 2152 asm: x86.AMULSS, 2153 reg: regInfo{ 2154 inputs: []inputInfo{ 2155 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2156 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2157 }, 2158 outputs: []outputInfo{ 2159 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2160 }, 2161 }, 2162 }, 2163 { 2164 name: "MULSD", 2165 argLen: 2, 2166 commutative: true, 2167 resultInArg0: true, 2168 asm: x86.AMULSD, 2169 reg: regInfo{ 2170 inputs: []inputInfo{ 2171 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2172 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2173 }, 2174 outputs: []outputInfo{ 2175 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2176 }, 2177 }, 2178 }, 2179 { 2180 name: "DIVSS", 2181 argLen: 2, 2182 resultInArg0: true, 2183 usesScratch: true, 2184 asm: x86.ADIVSS, 2185 reg: regInfo{ 2186 inputs: []inputInfo{ 2187 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2188 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2189 }, 2190 outputs: []outputInfo{ 2191 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2192 }, 2193 }, 2194 }, 2195 { 2196 name: "DIVSD", 2197 argLen: 2, 2198 resultInArg0: true, 2199 asm: x86.ADIVSD, 2200 reg: regInfo{ 2201 inputs: []inputInfo{ 2202 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2203 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2204 }, 2205 outputs: []outputInfo{ 2206 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2207 }, 2208 }, 2209 }, 2210 { 2211 name: "MOVSSload", 2212 auxType: auxSymOff, 2213 argLen: 2, 2214 faultOnNilArg0: true, 2215 symEffect: SymRead, 2216 asm: x86.AMOVSS, 2217 reg: regInfo{ 2218 inputs: []inputInfo{ 2219 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2220 }, 2221 outputs: []outputInfo{ 2222 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2223 }, 2224 }, 2225 }, 2226 { 2227 name: "MOVSDload", 2228 auxType: auxSymOff, 2229 argLen: 2, 2230 faultOnNilArg0: true, 2231 symEffect: SymRead, 2232 asm: x86.AMOVSD, 2233 reg: regInfo{ 2234 inputs: []inputInfo{ 2235 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2236 }, 2237 outputs: []outputInfo{ 2238 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2239 }, 2240 }, 2241 }, 2242 { 2243 name: "MOVSSconst", 2244 auxType: auxFloat32, 2245 argLen: 0, 2246 rematerializeable: true, 2247 asm: x86.AMOVSS, 2248 reg: regInfo{ 2249 outputs: []outputInfo{ 2250 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2251 }, 2252 }, 2253 }, 2254 { 2255 name: "MOVSDconst", 2256 auxType: auxFloat64, 2257 argLen: 0, 2258 rematerializeable: true, 2259 asm: x86.AMOVSD, 2260 reg: regInfo{ 2261 outputs: []outputInfo{ 2262 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2263 }, 2264 }, 2265 }, 2266 { 2267 name: "MOVSSloadidx1", 2268 auxType: auxSymOff, 2269 argLen: 3, 2270 symEffect: SymRead, 2271 asm: x86.AMOVSS, 2272 reg: regInfo{ 2273 inputs: []inputInfo{ 2274 {1, 255}, // AX CX DX BX SP BP SI DI 2275 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2276 }, 2277 outputs: []outputInfo{ 2278 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2279 }, 2280 }, 2281 }, 2282 { 2283 name: "MOVSSloadidx4", 2284 auxType: auxSymOff, 2285 argLen: 3, 2286 symEffect: SymRead, 2287 asm: x86.AMOVSS, 2288 reg: regInfo{ 2289 inputs: []inputInfo{ 2290 {1, 255}, // AX CX DX BX SP BP SI DI 2291 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2292 }, 2293 outputs: []outputInfo{ 2294 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2295 }, 2296 }, 2297 }, 2298 { 2299 name: "MOVSDloadidx1", 2300 auxType: auxSymOff, 2301 argLen: 3, 2302 symEffect: SymRead, 2303 asm: x86.AMOVSD, 2304 reg: regInfo{ 2305 inputs: []inputInfo{ 2306 {1, 255}, // AX CX DX BX SP BP SI DI 2307 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2308 }, 2309 outputs: []outputInfo{ 2310 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2311 }, 2312 }, 2313 }, 2314 { 2315 name: "MOVSDloadidx8", 2316 auxType: auxSymOff, 2317 argLen: 3, 2318 symEffect: SymRead, 2319 asm: x86.AMOVSD, 2320 reg: regInfo{ 2321 inputs: []inputInfo{ 2322 {1, 255}, // AX CX DX BX SP BP SI DI 2323 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2324 }, 2325 outputs: []outputInfo{ 2326 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2327 }, 2328 }, 2329 }, 2330 { 2331 name: "MOVSSstore", 2332 auxType: auxSymOff, 2333 argLen: 3, 2334 faultOnNilArg0: true, 2335 symEffect: SymWrite, 2336 asm: x86.AMOVSS, 2337 reg: regInfo{ 2338 inputs: []inputInfo{ 2339 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2340 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2341 }, 2342 }, 2343 }, 2344 { 2345 name: "MOVSDstore", 2346 auxType: auxSymOff, 2347 argLen: 3, 2348 faultOnNilArg0: true, 2349 symEffect: SymWrite, 2350 asm: x86.AMOVSD, 2351 reg: regInfo{ 2352 inputs: []inputInfo{ 2353 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2354 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2355 }, 2356 }, 2357 }, 2358 { 2359 name: "MOVSSstoreidx1", 2360 auxType: auxSymOff, 2361 argLen: 4, 2362 symEffect: SymWrite, 2363 asm: x86.AMOVSS, 2364 reg: regInfo{ 2365 inputs: []inputInfo{ 2366 {1, 255}, // AX CX DX BX SP BP SI DI 2367 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2368 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2369 }, 2370 }, 2371 }, 2372 { 2373 name: "MOVSSstoreidx4", 2374 auxType: auxSymOff, 2375 argLen: 4, 2376 symEffect: SymWrite, 2377 asm: x86.AMOVSS, 2378 reg: regInfo{ 2379 inputs: []inputInfo{ 2380 {1, 255}, // AX CX DX BX SP BP SI DI 2381 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2382 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2383 }, 2384 }, 2385 }, 2386 { 2387 name: "MOVSDstoreidx1", 2388 auxType: auxSymOff, 2389 argLen: 4, 2390 symEffect: SymWrite, 2391 asm: x86.AMOVSD, 2392 reg: regInfo{ 2393 inputs: []inputInfo{ 2394 {1, 255}, // AX CX DX BX SP BP SI DI 2395 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2396 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2397 }, 2398 }, 2399 }, 2400 { 2401 name: "MOVSDstoreidx8", 2402 auxType: auxSymOff, 2403 argLen: 4, 2404 symEffect: SymWrite, 2405 asm: x86.AMOVSD, 2406 reg: regInfo{ 2407 inputs: []inputInfo{ 2408 {1, 255}, // AX CX DX BX SP BP SI DI 2409 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2410 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2411 }, 2412 }, 2413 }, 2414 { 2415 name: "ADDL", 2416 argLen: 2, 2417 commutative: true, 2418 clobberFlags: true, 2419 asm: x86.AADDL, 2420 reg: regInfo{ 2421 inputs: []inputInfo{ 2422 {1, 239}, // AX CX DX BX BP SI DI 2423 {0, 255}, // AX CX DX BX SP BP SI DI 2424 }, 2425 outputs: []outputInfo{ 2426 {0, 239}, // AX CX DX BX BP SI DI 2427 }, 2428 }, 2429 }, 2430 { 2431 name: "ADDLconst", 2432 auxType: auxInt32, 2433 argLen: 1, 2434 clobberFlags: true, 2435 asm: x86.AADDL, 2436 reg: regInfo{ 2437 inputs: []inputInfo{ 2438 {0, 255}, // AX CX DX BX SP BP SI DI 2439 }, 2440 outputs: []outputInfo{ 2441 {0, 239}, // AX CX DX BX BP SI DI 2442 }, 2443 }, 2444 }, 2445 { 2446 name: "ADDLcarry", 2447 argLen: 2, 2448 commutative: true, 2449 resultInArg0: true, 2450 asm: x86.AADDL, 2451 reg: regInfo{ 2452 inputs: []inputInfo{ 2453 {0, 239}, // AX CX DX BX BP SI DI 2454 {1, 239}, // AX CX DX BX BP SI DI 2455 }, 2456 outputs: []outputInfo{ 2457 {1, 0}, 2458 {0, 239}, // AX CX DX BX BP SI DI 2459 }, 2460 }, 2461 }, 2462 { 2463 name: "ADDLconstcarry", 2464 auxType: auxInt32, 2465 argLen: 1, 2466 resultInArg0: true, 2467 asm: x86.AADDL, 2468 reg: regInfo{ 2469 inputs: []inputInfo{ 2470 {0, 239}, // AX CX DX BX BP SI DI 2471 }, 2472 outputs: []outputInfo{ 2473 {1, 0}, 2474 {0, 239}, // AX CX DX BX BP SI DI 2475 }, 2476 }, 2477 }, 2478 { 2479 name: "ADCL", 2480 argLen: 3, 2481 commutative: true, 2482 resultInArg0: true, 2483 clobberFlags: true, 2484 asm: x86.AADCL, 2485 reg: regInfo{ 2486 inputs: []inputInfo{ 2487 {0, 239}, // AX CX DX BX BP SI DI 2488 {1, 239}, // AX CX DX BX BP SI DI 2489 }, 2490 outputs: []outputInfo{ 2491 {0, 239}, // AX CX DX BX BP SI DI 2492 }, 2493 }, 2494 }, 2495 { 2496 name: "ADCLconst", 2497 auxType: auxInt32, 2498 argLen: 2, 2499 resultInArg0: true, 2500 clobberFlags: true, 2501 asm: x86.AADCL, 2502 reg: regInfo{ 2503 inputs: []inputInfo{ 2504 {0, 239}, // AX CX DX BX BP SI DI 2505 }, 2506 outputs: []outputInfo{ 2507 {0, 239}, // AX CX DX BX BP SI DI 2508 }, 2509 }, 2510 }, 2511 { 2512 name: "SUBL", 2513 argLen: 2, 2514 resultInArg0: true, 2515 clobberFlags: true, 2516 asm: x86.ASUBL, 2517 reg: regInfo{ 2518 inputs: []inputInfo{ 2519 {0, 239}, // AX CX DX BX BP SI DI 2520 {1, 239}, // AX CX DX BX BP SI DI 2521 }, 2522 outputs: []outputInfo{ 2523 {0, 239}, // AX CX DX BX BP SI DI 2524 }, 2525 }, 2526 }, 2527 { 2528 name: "SUBLconst", 2529 auxType: auxInt32, 2530 argLen: 1, 2531 resultInArg0: true, 2532 clobberFlags: true, 2533 asm: x86.ASUBL, 2534 reg: regInfo{ 2535 inputs: []inputInfo{ 2536 {0, 239}, // AX CX DX BX BP SI DI 2537 }, 2538 outputs: []outputInfo{ 2539 {0, 239}, // AX CX DX BX BP SI DI 2540 }, 2541 }, 2542 }, 2543 { 2544 name: "SUBLcarry", 2545 argLen: 2, 2546 resultInArg0: true, 2547 asm: x86.ASUBL, 2548 reg: regInfo{ 2549 inputs: []inputInfo{ 2550 {0, 239}, // AX CX DX BX BP SI DI 2551 {1, 239}, // AX CX DX BX BP SI DI 2552 }, 2553 outputs: []outputInfo{ 2554 {1, 0}, 2555 {0, 239}, // AX CX DX BX BP SI DI 2556 }, 2557 }, 2558 }, 2559 { 2560 name: "SUBLconstcarry", 2561 auxType: auxInt32, 2562 argLen: 1, 2563 resultInArg0: true, 2564 asm: x86.ASUBL, 2565 reg: regInfo{ 2566 inputs: []inputInfo{ 2567 {0, 239}, // AX CX DX BX BP SI DI 2568 }, 2569 outputs: []outputInfo{ 2570 {1, 0}, 2571 {0, 239}, // AX CX DX BX BP SI DI 2572 }, 2573 }, 2574 }, 2575 { 2576 name: "SBBL", 2577 argLen: 3, 2578 resultInArg0: true, 2579 clobberFlags: true, 2580 asm: x86.ASBBL, 2581 reg: regInfo{ 2582 inputs: []inputInfo{ 2583 {0, 239}, // AX CX DX BX BP SI DI 2584 {1, 239}, // AX CX DX BX BP SI DI 2585 }, 2586 outputs: []outputInfo{ 2587 {0, 239}, // AX CX DX BX BP SI DI 2588 }, 2589 }, 2590 }, 2591 { 2592 name: "SBBLconst", 2593 auxType: auxInt32, 2594 argLen: 2, 2595 resultInArg0: true, 2596 clobberFlags: true, 2597 asm: x86.ASBBL, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {0, 239}, // AX CX DX BX BP SI DI 2601 }, 2602 outputs: []outputInfo{ 2603 {0, 239}, // AX CX DX BX BP SI DI 2604 }, 2605 }, 2606 }, 2607 { 2608 name: "MULL", 2609 argLen: 2, 2610 commutative: true, 2611 resultInArg0: true, 2612 clobberFlags: true, 2613 asm: x86.AIMULL, 2614 reg: regInfo{ 2615 inputs: []inputInfo{ 2616 {0, 239}, // AX CX DX BX BP SI DI 2617 {1, 239}, // AX CX DX BX BP SI DI 2618 }, 2619 outputs: []outputInfo{ 2620 {0, 239}, // AX CX DX BX BP SI DI 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "MULLconst", 2626 auxType: auxInt32, 2627 argLen: 1, 2628 resultInArg0: true, 2629 clobberFlags: true, 2630 asm: x86.AIMULL, 2631 reg: regInfo{ 2632 inputs: []inputInfo{ 2633 {0, 239}, // AX CX DX BX BP SI DI 2634 }, 2635 outputs: []outputInfo{ 2636 {0, 239}, // AX CX DX BX BP SI DI 2637 }, 2638 }, 2639 }, 2640 { 2641 name: "HMULL", 2642 argLen: 2, 2643 commutative: true, 2644 clobberFlags: true, 2645 asm: x86.AIMULL, 2646 reg: regInfo{ 2647 inputs: []inputInfo{ 2648 {0, 1}, // AX 2649 {1, 255}, // AX CX DX BX SP BP SI DI 2650 }, 2651 clobbers: 1, // AX 2652 outputs: []outputInfo{ 2653 {0, 4}, // DX 2654 }, 2655 }, 2656 }, 2657 { 2658 name: "HMULLU", 2659 argLen: 2, 2660 commutative: true, 2661 clobberFlags: true, 2662 asm: x86.AMULL, 2663 reg: regInfo{ 2664 inputs: []inputInfo{ 2665 {0, 1}, // AX 2666 {1, 255}, // AX CX DX BX SP BP SI DI 2667 }, 2668 clobbers: 1, // AX 2669 outputs: []outputInfo{ 2670 {0, 4}, // DX 2671 }, 2672 }, 2673 }, 2674 { 2675 name: "MULLQU", 2676 argLen: 2, 2677 commutative: true, 2678 clobberFlags: true, 2679 asm: x86.AMULL, 2680 reg: regInfo{ 2681 inputs: []inputInfo{ 2682 {0, 1}, // AX 2683 {1, 255}, // AX CX DX BX SP BP SI DI 2684 }, 2685 outputs: []outputInfo{ 2686 {0, 4}, // DX 2687 {1, 1}, // AX 2688 }, 2689 }, 2690 }, 2691 { 2692 name: "AVGLU", 2693 argLen: 2, 2694 commutative: true, 2695 resultInArg0: true, 2696 clobberFlags: true, 2697 reg: regInfo{ 2698 inputs: []inputInfo{ 2699 {0, 239}, // AX CX DX BX BP SI DI 2700 {1, 239}, // AX CX DX BX BP SI DI 2701 }, 2702 outputs: []outputInfo{ 2703 {0, 239}, // AX CX DX BX BP SI DI 2704 }, 2705 }, 2706 }, 2707 { 2708 name: "DIVL", 2709 argLen: 2, 2710 clobberFlags: true, 2711 asm: x86.AIDIVL, 2712 reg: regInfo{ 2713 inputs: []inputInfo{ 2714 {0, 1}, // AX 2715 {1, 251}, // AX CX BX SP BP SI DI 2716 }, 2717 clobbers: 4, // DX 2718 outputs: []outputInfo{ 2719 {0, 1}, // AX 2720 }, 2721 }, 2722 }, 2723 { 2724 name: "DIVW", 2725 argLen: 2, 2726 clobberFlags: true, 2727 asm: x86.AIDIVW, 2728 reg: regInfo{ 2729 inputs: []inputInfo{ 2730 {0, 1}, // AX 2731 {1, 251}, // AX CX BX SP BP SI DI 2732 }, 2733 clobbers: 4, // DX 2734 outputs: []outputInfo{ 2735 {0, 1}, // AX 2736 }, 2737 }, 2738 }, 2739 { 2740 name: "DIVLU", 2741 argLen: 2, 2742 clobberFlags: true, 2743 asm: x86.ADIVL, 2744 reg: regInfo{ 2745 inputs: []inputInfo{ 2746 {0, 1}, // AX 2747 {1, 251}, // AX CX BX SP BP SI DI 2748 }, 2749 clobbers: 4, // DX 2750 outputs: []outputInfo{ 2751 {0, 1}, // AX 2752 }, 2753 }, 2754 }, 2755 { 2756 name: "DIVWU", 2757 argLen: 2, 2758 clobberFlags: true, 2759 asm: x86.ADIVW, 2760 reg: regInfo{ 2761 inputs: []inputInfo{ 2762 {0, 1}, // AX 2763 {1, 251}, // AX CX BX SP BP SI DI 2764 }, 2765 clobbers: 4, // DX 2766 outputs: []outputInfo{ 2767 {0, 1}, // AX 2768 }, 2769 }, 2770 }, 2771 { 2772 name: "MODL", 2773 argLen: 2, 2774 clobberFlags: true, 2775 asm: x86.AIDIVL, 2776 reg: regInfo{ 2777 inputs: []inputInfo{ 2778 {0, 1}, // AX 2779 {1, 251}, // AX CX BX SP BP SI DI 2780 }, 2781 clobbers: 1, // AX 2782 outputs: []outputInfo{ 2783 {0, 4}, // DX 2784 }, 2785 }, 2786 }, 2787 { 2788 name: "MODW", 2789 argLen: 2, 2790 clobberFlags: true, 2791 asm: x86.AIDIVW, 2792 reg: regInfo{ 2793 inputs: []inputInfo{ 2794 {0, 1}, // AX 2795 {1, 251}, // AX CX BX SP BP SI DI 2796 }, 2797 clobbers: 1, // AX 2798 outputs: []outputInfo{ 2799 {0, 4}, // DX 2800 }, 2801 }, 2802 }, 2803 { 2804 name: "MODLU", 2805 argLen: 2, 2806 clobberFlags: true, 2807 asm: x86.ADIVL, 2808 reg: regInfo{ 2809 inputs: []inputInfo{ 2810 {0, 1}, // AX 2811 {1, 251}, // AX CX BX SP BP SI DI 2812 }, 2813 clobbers: 1, // AX 2814 outputs: []outputInfo{ 2815 {0, 4}, // DX 2816 }, 2817 }, 2818 }, 2819 { 2820 name: "MODWU", 2821 argLen: 2, 2822 clobberFlags: true, 2823 asm: x86.ADIVW, 2824 reg: regInfo{ 2825 inputs: []inputInfo{ 2826 {0, 1}, // AX 2827 {1, 251}, // AX CX BX SP BP SI DI 2828 }, 2829 clobbers: 1, // AX 2830 outputs: []outputInfo{ 2831 {0, 4}, // DX 2832 }, 2833 }, 2834 }, 2835 { 2836 name: "ANDL", 2837 argLen: 2, 2838 commutative: true, 2839 resultInArg0: true, 2840 clobberFlags: true, 2841 asm: x86.AANDL, 2842 reg: regInfo{ 2843 inputs: []inputInfo{ 2844 {0, 239}, // AX CX DX BX BP SI DI 2845 {1, 239}, // AX CX DX BX BP SI DI 2846 }, 2847 outputs: []outputInfo{ 2848 {0, 239}, // AX CX DX BX BP SI DI 2849 }, 2850 }, 2851 }, 2852 { 2853 name: "ANDLconst", 2854 auxType: auxInt32, 2855 argLen: 1, 2856 resultInArg0: true, 2857 clobberFlags: true, 2858 asm: x86.AANDL, 2859 reg: regInfo{ 2860 inputs: []inputInfo{ 2861 {0, 239}, // AX CX DX BX BP SI DI 2862 }, 2863 outputs: []outputInfo{ 2864 {0, 239}, // AX CX DX BX BP SI DI 2865 }, 2866 }, 2867 }, 2868 { 2869 name: "ORL", 2870 argLen: 2, 2871 commutative: true, 2872 resultInArg0: true, 2873 clobberFlags: true, 2874 asm: x86.AORL, 2875 reg: regInfo{ 2876 inputs: []inputInfo{ 2877 {0, 239}, // AX CX DX BX BP SI DI 2878 {1, 239}, // AX CX DX BX BP SI DI 2879 }, 2880 outputs: []outputInfo{ 2881 {0, 239}, // AX CX DX BX BP SI DI 2882 }, 2883 }, 2884 }, 2885 { 2886 name: "ORLconst", 2887 auxType: auxInt32, 2888 argLen: 1, 2889 resultInArg0: true, 2890 clobberFlags: true, 2891 asm: x86.AORL, 2892 reg: regInfo{ 2893 inputs: []inputInfo{ 2894 {0, 239}, // AX CX DX BX BP SI DI 2895 }, 2896 outputs: []outputInfo{ 2897 {0, 239}, // AX CX DX BX BP SI DI 2898 }, 2899 }, 2900 }, 2901 { 2902 name: "XORL", 2903 argLen: 2, 2904 commutative: true, 2905 resultInArg0: true, 2906 clobberFlags: true, 2907 asm: x86.AXORL, 2908 reg: regInfo{ 2909 inputs: []inputInfo{ 2910 {0, 239}, // AX CX DX BX BP SI DI 2911 {1, 239}, // AX CX DX BX BP SI DI 2912 }, 2913 outputs: []outputInfo{ 2914 {0, 239}, // AX CX DX BX BP SI DI 2915 }, 2916 }, 2917 }, 2918 { 2919 name: "XORLconst", 2920 auxType: auxInt32, 2921 argLen: 1, 2922 resultInArg0: true, 2923 clobberFlags: true, 2924 asm: x86.AXORL, 2925 reg: regInfo{ 2926 inputs: []inputInfo{ 2927 {0, 239}, // AX CX DX BX BP SI DI 2928 }, 2929 outputs: []outputInfo{ 2930 {0, 239}, // AX CX DX BX BP SI DI 2931 }, 2932 }, 2933 }, 2934 { 2935 name: "CMPL", 2936 argLen: 2, 2937 asm: x86.ACMPL, 2938 reg: regInfo{ 2939 inputs: []inputInfo{ 2940 {0, 255}, // AX CX DX BX SP BP SI DI 2941 {1, 255}, // AX CX DX BX SP BP SI DI 2942 }, 2943 }, 2944 }, 2945 { 2946 name: "CMPW", 2947 argLen: 2, 2948 asm: x86.ACMPW, 2949 reg: regInfo{ 2950 inputs: []inputInfo{ 2951 {0, 255}, // AX CX DX BX SP BP SI DI 2952 {1, 255}, // AX CX DX BX SP BP SI DI 2953 }, 2954 }, 2955 }, 2956 { 2957 name: "CMPB", 2958 argLen: 2, 2959 asm: x86.ACMPB, 2960 reg: regInfo{ 2961 inputs: []inputInfo{ 2962 {0, 255}, // AX CX DX BX SP BP SI DI 2963 {1, 255}, // AX CX DX BX SP BP SI DI 2964 }, 2965 }, 2966 }, 2967 { 2968 name: "CMPLconst", 2969 auxType: auxInt32, 2970 argLen: 1, 2971 asm: x86.ACMPL, 2972 reg: regInfo{ 2973 inputs: []inputInfo{ 2974 {0, 255}, // AX CX DX BX SP BP SI DI 2975 }, 2976 }, 2977 }, 2978 { 2979 name: "CMPWconst", 2980 auxType: auxInt16, 2981 argLen: 1, 2982 asm: x86.ACMPW, 2983 reg: regInfo{ 2984 inputs: []inputInfo{ 2985 {0, 255}, // AX CX DX BX SP BP SI DI 2986 }, 2987 }, 2988 }, 2989 { 2990 name: "CMPBconst", 2991 auxType: auxInt8, 2992 argLen: 1, 2993 asm: x86.ACMPB, 2994 reg: regInfo{ 2995 inputs: []inputInfo{ 2996 {0, 255}, // AX CX DX BX SP BP SI DI 2997 }, 2998 }, 2999 }, 3000 { 3001 name: "UCOMISS", 3002 argLen: 2, 3003 usesScratch: true, 3004 asm: x86.AUCOMISS, 3005 reg: regInfo{ 3006 inputs: []inputInfo{ 3007 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3008 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3009 }, 3010 }, 3011 }, 3012 { 3013 name: "UCOMISD", 3014 argLen: 2, 3015 usesScratch: true, 3016 asm: x86.AUCOMISD, 3017 reg: regInfo{ 3018 inputs: []inputInfo{ 3019 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3020 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3021 }, 3022 }, 3023 }, 3024 { 3025 name: "TESTL", 3026 argLen: 2, 3027 commutative: true, 3028 asm: x86.ATESTL, 3029 reg: regInfo{ 3030 inputs: []inputInfo{ 3031 {0, 255}, // AX CX DX BX SP BP SI DI 3032 {1, 255}, // AX CX DX BX SP BP SI DI 3033 }, 3034 }, 3035 }, 3036 { 3037 name: "TESTW", 3038 argLen: 2, 3039 commutative: true, 3040 asm: x86.ATESTW, 3041 reg: regInfo{ 3042 inputs: []inputInfo{ 3043 {0, 255}, // AX CX DX BX SP BP SI DI 3044 {1, 255}, // AX CX DX BX SP BP SI DI 3045 }, 3046 }, 3047 }, 3048 { 3049 name: "TESTB", 3050 argLen: 2, 3051 commutative: true, 3052 asm: x86.ATESTB, 3053 reg: regInfo{ 3054 inputs: []inputInfo{ 3055 {0, 255}, // AX CX DX BX SP BP SI DI 3056 {1, 255}, // AX CX DX BX SP BP SI DI 3057 }, 3058 }, 3059 }, 3060 { 3061 name: "TESTLconst", 3062 auxType: auxInt32, 3063 argLen: 1, 3064 asm: x86.ATESTL, 3065 reg: regInfo{ 3066 inputs: []inputInfo{ 3067 {0, 255}, // AX CX DX BX SP BP SI DI 3068 }, 3069 }, 3070 }, 3071 { 3072 name: "TESTWconst", 3073 auxType: auxInt16, 3074 argLen: 1, 3075 asm: x86.ATESTW, 3076 reg: regInfo{ 3077 inputs: []inputInfo{ 3078 {0, 255}, // AX CX DX BX SP BP SI DI 3079 }, 3080 }, 3081 }, 3082 { 3083 name: "TESTBconst", 3084 auxType: auxInt8, 3085 argLen: 1, 3086 asm: x86.ATESTB, 3087 reg: regInfo{ 3088 inputs: []inputInfo{ 3089 {0, 255}, // AX CX DX BX SP BP SI DI 3090 }, 3091 }, 3092 }, 3093 { 3094 name: "SHLL", 3095 argLen: 2, 3096 resultInArg0: true, 3097 clobberFlags: true, 3098 asm: x86.ASHLL, 3099 reg: regInfo{ 3100 inputs: []inputInfo{ 3101 {1, 2}, // CX 3102 {0, 239}, // AX CX DX BX BP SI DI 3103 }, 3104 outputs: []outputInfo{ 3105 {0, 239}, // AX CX DX BX BP SI DI 3106 }, 3107 }, 3108 }, 3109 { 3110 name: "SHLLconst", 3111 auxType: auxInt32, 3112 argLen: 1, 3113 resultInArg0: true, 3114 clobberFlags: true, 3115 asm: x86.ASHLL, 3116 reg: regInfo{ 3117 inputs: []inputInfo{ 3118 {0, 239}, // AX CX DX BX BP SI DI 3119 }, 3120 outputs: []outputInfo{ 3121 {0, 239}, // AX CX DX BX BP SI DI 3122 }, 3123 }, 3124 }, 3125 { 3126 name: "SHRL", 3127 argLen: 2, 3128 resultInArg0: true, 3129 clobberFlags: true, 3130 asm: x86.ASHRL, 3131 reg: regInfo{ 3132 inputs: []inputInfo{ 3133 {1, 2}, // CX 3134 {0, 239}, // AX CX DX BX BP SI DI 3135 }, 3136 outputs: []outputInfo{ 3137 {0, 239}, // AX CX DX BX BP SI DI 3138 }, 3139 }, 3140 }, 3141 { 3142 name: "SHRW", 3143 argLen: 2, 3144 resultInArg0: true, 3145 clobberFlags: true, 3146 asm: x86.ASHRW, 3147 reg: regInfo{ 3148 inputs: []inputInfo{ 3149 {1, 2}, // CX 3150 {0, 239}, // AX CX DX BX BP SI DI 3151 }, 3152 outputs: []outputInfo{ 3153 {0, 239}, // AX CX DX BX BP SI DI 3154 }, 3155 }, 3156 }, 3157 { 3158 name: "SHRB", 3159 argLen: 2, 3160 resultInArg0: true, 3161 clobberFlags: true, 3162 asm: x86.ASHRB, 3163 reg: regInfo{ 3164 inputs: []inputInfo{ 3165 {1, 2}, // CX 3166 {0, 239}, // AX CX DX BX BP SI DI 3167 }, 3168 outputs: []outputInfo{ 3169 {0, 239}, // AX CX DX BX BP SI DI 3170 }, 3171 }, 3172 }, 3173 { 3174 name: "SHRLconst", 3175 auxType: auxInt32, 3176 argLen: 1, 3177 resultInArg0: true, 3178 clobberFlags: true, 3179 asm: x86.ASHRL, 3180 reg: regInfo{ 3181 inputs: []inputInfo{ 3182 {0, 239}, // AX CX DX BX BP SI DI 3183 }, 3184 outputs: []outputInfo{ 3185 {0, 239}, // AX CX DX BX BP SI DI 3186 }, 3187 }, 3188 }, 3189 { 3190 name: "SHRWconst", 3191 auxType: auxInt16, 3192 argLen: 1, 3193 resultInArg0: true, 3194 clobberFlags: true, 3195 asm: x86.ASHRW, 3196 reg: regInfo{ 3197 inputs: []inputInfo{ 3198 {0, 239}, // AX CX DX BX BP SI DI 3199 }, 3200 outputs: []outputInfo{ 3201 {0, 239}, // AX CX DX BX BP SI DI 3202 }, 3203 }, 3204 }, 3205 { 3206 name: "SHRBconst", 3207 auxType: auxInt8, 3208 argLen: 1, 3209 resultInArg0: true, 3210 clobberFlags: true, 3211 asm: x86.ASHRB, 3212 reg: regInfo{ 3213 inputs: []inputInfo{ 3214 {0, 239}, // AX CX DX BX BP SI DI 3215 }, 3216 outputs: []outputInfo{ 3217 {0, 239}, // AX CX DX BX BP SI DI 3218 }, 3219 }, 3220 }, 3221 { 3222 name: "SARL", 3223 argLen: 2, 3224 resultInArg0: true, 3225 clobberFlags: true, 3226 asm: x86.ASARL, 3227 reg: regInfo{ 3228 inputs: []inputInfo{ 3229 {1, 2}, // CX 3230 {0, 239}, // AX CX DX BX BP SI DI 3231 }, 3232 outputs: []outputInfo{ 3233 {0, 239}, // AX CX DX BX BP SI DI 3234 }, 3235 }, 3236 }, 3237 { 3238 name: "SARW", 3239 argLen: 2, 3240 resultInArg0: true, 3241 clobberFlags: true, 3242 asm: x86.ASARW, 3243 reg: regInfo{ 3244 inputs: []inputInfo{ 3245 {1, 2}, // CX 3246 {0, 239}, // AX CX DX BX BP SI DI 3247 }, 3248 outputs: []outputInfo{ 3249 {0, 239}, // AX CX DX BX BP SI DI 3250 }, 3251 }, 3252 }, 3253 { 3254 name: "SARB", 3255 argLen: 2, 3256 resultInArg0: true, 3257 clobberFlags: true, 3258 asm: x86.ASARB, 3259 reg: regInfo{ 3260 inputs: []inputInfo{ 3261 {1, 2}, // CX 3262 {0, 239}, // AX CX DX BX BP SI DI 3263 }, 3264 outputs: []outputInfo{ 3265 {0, 239}, // AX CX DX BX BP SI DI 3266 }, 3267 }, 3268 }, 3269 { 3270 name: "SARLconst", 3271 auxType: auxInt32, 3272 argLen: 1, 3273 resultInArg0: true, 3274 clobberFlags: true, 3275 asm: x86.ASARL, 3276 reg: regInfo{ 3277 inputs: []inputInfo{ 3278 {0, 239}, // AX CX DX BX BP SI DI 3279 }, 3280 outputs: []outputInfo{ 3281 {0, 239}, // AX CX DX BX BP SI DI 3282 }, 3283 }, 3284 }, 3285 { 3286 name: "SARWconst", 3287 auxType: auxInt16, 3288 argLen: 1, 3289 resultInArg0: true, 3290 clobberFlags: true, 3291 asm: x86.ASARW, 3292 reg: regInfo{ 3293 inputs: []inputInfo{ 3294 {0, 239}, // AX CX DX BX BP SI DI 3295 }, 3296 outputs: []outputInfo{ 3297 {0, 239}, // AX CX DX BX BP SI DI 3298 }, 3299 }, 3300 }, 3301 { 3302 name: "SARBconst", 3303 auxType: auxInt8, 3304 argLen: 1, 3305 resultInArg0: true, 3306 clobberFlags: true, 3307 asm: x86.ASARB, 3308 reg: regInfo{ 3309 inputs: []inputInfo{ 3310 {0, 239}, // AX CX DX BX BP SI DI 3311 }, 3312 outputs: []outputInfo{ 3313 {0, 239}, // AX CX DX BX BP SI DI 3314 }, 3315 }, 3316 }, 3317 { 3318 name: "ROLLconst", 3319 auxType: auxInt32, 3320 argLen: 1, 3321 resultInArg0: true, 3322 clobberFlags: true, 3323 asm: x86.AROLL, 3324 reg: regInfo{ 3325 inputs: []inputInfo{ 3326 {0, 239}, // AX CX DX BX BP SI DI 3327 }, 3328 outputs: []outputInfo{ 3329 {0, 239}, // AX CX DX BX BP SI DI 3330 }, 3331 }, 3332 }, 3333 { 3334 name: "ROLWconst", 3335 auxType: auxInt16, 3336 argLen: 1, 3337 resultInArg0: true, 3338 clobberFlags: true, 3339 asm: x86.AROLW, 3340 reg: regInfo{ 3341 inputs: []inputInfo{ 3342 {0, 239}, // AX CX DX BX BP SI DI 3343 }, 3344 outputs: []outputInfo{ 3345 {0, 239}, // AX CX DX BX BP SI DI 3346 }, 3347 }, 3348 }, 3349 { 3350 name: "ROLBconst", 3351 auxType: auxInt8, 3352 argLen: 1, 3353 resultInArg0: true, 3354 clobberFlags: true, 3355 asm: x86.AROLB, 3356 reg: regInfo{ 3357 inputs: []inputInfo{ 3358 {0, 239}, // AX CX DX BX BP SI DI 3359 }, 3360 outputs: []outputInfo{ 3361 {0, 239}, // AX CX DX BX BP SI DI 3362 }, 3363 }, 3364 }, 3365 { 3366 name: "NEGL", 3367 argLen: 1, 3368 resultInArg0: true, 3369 clobberFlags: true, 3370 asm: x86.ANEGL, 3371 reg: regInfo{ 3372 inputs: []inputInfo{ 3373 {0, 239}, // AX CX DX BX BP SI DI 3374 }, 3375 outputs: []outputInfo{ 3376 {0, 239}, // AX CX DX BX BP SI DI 3377 }, 3378 }, 3379 }, 3380 { 3381 name: "NOTL", 3382 argLen: 1, 3383 resultInArg0: true, 3384 clobberFlags: true, 3385 asm: x86.ANOTL, 3386 reg: regInfo{ 3387 inputs: []inputInfo{ 3388 {0, 239}, // AX CX DX BX BP SI DI 3389 }, 3390 outputs: []outputInfo{ 3391 {0, 239}, // AX CX DX BX BP SI DI 3392 }, 3393 }, 3394 }, 3395 { 3396 name: "BSFL", 3397 argLen: 1, 3398 clobberFlags: true, 3399 asm: x86.ABSFL, 3400 reg: regInfo{ 3401 inputs: []inputInfo{ 3402 {0, 239}, // AX CX DX BX BP SI DI 3403 }, 3404 outputs: []outputInfo{ 3405 {0, 239}, // AX CX DX BX BP SI DI 3406 }, 3407 }, 3408 }, 3409 { 3410 name: "BSFW", 3411 argLen: 1, 3412 clobberFlags: true, 3413 asm: x86.ABSFW, 3414 reg: regInfo{ 3415 inputs: []inputInfo{ 3416 {0, 239}, // AX CX DX BX BP SI DI 3417 }, 3418 outputs: []outputInfo{ 3419 {0, 239}, // AX CX DX BX BP SI DI 3420 }, 3421 }, 3422 }, 3423 { 3424 name: "BSRL", 3425 argLen: 1, 3426 clobberFlags: true, 3427 asm: x86.ABSRL, 3428 reg: regInfo{ 3429 inputs: []inputInfo{ 3430 {0, 239}, // AX CX DX BX BP SI DI 3431 }, 3432 outputs: []outputInfo{ 3433 {0, 239}, // AX CX DX BX BP SI DI 3434 }, 3435 }, 3436 }, 3437 { 3438 name: "BSRW", 3439 argLen: 1, 3440 clobberFlags: true, 3441 asm: x86.ABSRW, 3442 reg: regInfo{ 3443 inputs: []inputInfo{ 3444 {0, 239}, // AX CX DX BX BP SI DI 3445 }, 3446 outputs: []outputInfo{ 3447 {0, 239}, // AX CX DX BX BP SI DI 3448 }, 3449 }, 3450 }, 3451 { 3452 name: "BSWAPL", 3453 argLen: 1, 3454 resultInArg0: true, 3455 clobberFlags: true, 3456 asm: x86.ABSWAPL, 3457 reg: regInfo{ 3458 inputs: []inputInfo{ 3459 {0, 239}, // AX CX DX BX BP SI DI 3460 }, 3461 outputs: []outputInfo{ 3462 {0, 239}, // AX CX DX BX BP SI DI 3463 }, 3464 }, 3465 }, 3466 { 3467 name: "SQRTSD", 3468 argLen: 1, 3469 asm: x86.ASQRTSD, 3470 reg: regInfo{ 3471 inputs: []inputInfo{ 3472 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3473 }, 3474 outputs: []outputInfo{ 3475 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3476 }, 3477 }, 3478 }, 3479 { 3480 name: "SBBLcarrymask", 3481 argLen: 1, 3482 asm: x86.ASBBL, 3483 reg: regInfo{ 3484 outputs: []outputInfo{ 3485 {0, 239}, // AX CX DX BX BP SI DI 3486 }, 3487 }, 3488 }, 3489 { 3490 name: "SETEQ", 3491 argLen: 1, 3492 asm: x86.ASETEQ, 3493 reg: regInfo{ 3494 outputs: []outputInfo{ 3495 {0, 239}, // AX CX DX BX BP SI DI 3496 }, 3497 }, 3498 }, 3499 { 3500 name: "SETNE", 3501 argLen: 1, 3502 asm: x86.ASETNE, 3503 reg: regInfo{ 3504 outputs: []outputInfo{ 3505 {0, 239}, // AX CX DX BX BP SI DI 3506 }, 3507 }, 3508 }, 3509 { 3510 name: "SETL", 3511 argLen: 1, 3512 asm: x86.ASETLT, 3513 reg: regInfo{ 3514 outputs: []outputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "SETLE", 3521 argLen: 1, 3522 asm: x86.ASETLE, 3523 reg: regInfo{ 3524 outputs: []outputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 }, 3528 }, 3529 { 3530 name: "SETG", 3531 argLen: 1, 3532 asm: x86.ASETGT, 3533 reg: regInfo{ 3534 outputs: []outputInfo{ 3535 {0, 239}, // AX CX DX BX BP SI DI 3536 }, 3537 }, 3538 }, 3539 { 3540 name: "SETGE", 3541 argLen: 1, 3542 asm: x86.ASETGE, 3543 reg: regInfo{ 3544 outputs: []outputInfo{ 3545 {0, 239}, // AX CX DX BX BP SI DI 3546 }, 3547 }, 3548 }, 3549 { 3550 name: "SETB", 3551 argLen: 1, 3552 asm: x86.ASETCS, 3553 reg: regInfo{ 3554 outputs: []outputInfo{ 3555 {0, 239}, // AX CX DX BX BP SI DI 3556 }, 3557 }, 3558 }, 3559 { 3560 name: "SETBE", 3561 argLen: 1, 3562 asm: x86.ASETLS, 3563 reg: regInfo{ 3564 outputs: []outputInfo{ 3565 {0, 239}, // AX CX DX BX BP SI DI 3566 }, 3567 }, 3568 }, 3569 { 3570 name: "SETA", 3571 argLen: 1, 3572 asm: x86.ASETHI, 3573 reg: regInfo{ 3574 outputs: []outputInfo{ 3575 {0, 239}, // AX CX DX BX BP SI DI 3576 }, 3577 }, 3578 }, 3579 { 3580 name: "SETAE", 3581 argLen: 1, 3582 asm: x86.ASETCC, 3583 reg: regInfo{ 3584 outputs: []outputInfo{ 3585 {0, 239}, // AX CX DX BX BP SI DI 3586 }, 3587 }, 3588 }, 3589 { 3590 name: "SETEQF", 3591 argLen: 1, 3592 clobberFlags: true, 3593 asm: x86.ASETEQ, 3594 reg: regInfo{ 3595 clobbers: 1, // AX 3596 outputs: []outputInfo{ 3597 {0, 238}, // CX DX BX BP SI DI 3598 }, 3599 }, 3600 }, 3601 { 3602 name: "SETNEF", 3603 argLen: 1, 3604 clobberFlags: true, 3605 asm: x86.ASETNE, 3606 reg: regInfo{ 3607 clobbers: 1, // AX 3608 outputs: []outputInfo{ 3609 {0, 238}, // CX DX BX BP SI DI 3610 }, 3611 }, 3612 }, 3613 { 3614 name: "SETORD", 3615 argLen: 1, 3616 asm: x86.ASETPC, 3617 reg: regInfo{ 3618 outputs: []outputInfo{ 3619 {0, 239}, // AX CX DX BX BP SI DI 3620 }, 3621 }, 3622 }, 3623 { 3624 name: "SETNAN", 3625 argLen: 1, 3626 asm: x86.ASETPS, 3627 reg: regInfo{ 3628 outputs: []outputInfo{ 3629 {0, 239}, // AX CX DX BX BP SI DI 3630 }, 3631 }, 3632 }, 3633 { 3634 name: "SETGF", 3635 argLen: 1, 3636 asm: x86.ASETHI, 3637 reg: regInfo{ 3638 outputs: []outputInfo{ 3639 {0, 239}, // AX CX DX BX BP SI DI 3640 }, 3641 }, 3642 }, 3643 { 3644 name: "SETGEF", 3645 argLen: 1, 3646 asm: x86.ASETCC, 3647 reg: regInfo{ 3648 outputs: []outputInfo{ 3649 {0, 239}, // AX CX DX BX BP SI DI 3650 }, 3651 }, 3652 }, 3653 { 3654 name: "MOVBLSX", 3655 argLen: 1, 3656 asm: x86.AMOVBLSX, 3657 reg: regInfo{ 3658 inputs: []inputInfo{ 3659 {0, 239}, // AX CX DX BX BP SI DI 3660 }, 3661 outputs: []outputInfo{ 3662 {0, 239}, // AX CX DX BX BP SI DI 3663 }, 3664 }, 3665 }, 3666 { 3667 name: "MOVBLZX", 3668 argLen: 1, 3669 asm: x86.AMOVBLZX, 3670 reg: regInfo{ 3671 inputs: []inputInfo{ 3672 {0, 239}, // AX CX DX BX BP SI DI 3673 }, 3674 outputs: []outputInfo{ 3675 {0, 239}, // AX CX DX BX BP SI DI 3676 }, 3677 }, 3678 }, 3679 { 3680 name: "MOVWLSX", 3681 argLen: 1, 3682 asm: x86.AMOVWLSX, 3683 reg: regInfo{ 3684 inputs: []inputInfo{ 3685 {0, 239}, // AX CX DX BX BP SI DI 3686 }, 3687 outputs: []outputInfo{ 3688 {0, 239}, // AX CX DX BX BP SI DI 3689 }, 3690 }, 3691 }, 3692 { 3693 name: "MOVWLZX", 3694 argLen: 1, 3695 asm: x86.AMOVWLZX, 3696 reg: regInfo{ 3697 inputs: []inputInfo{ 3698 {0, 239}, // AX CX DX BX BP SI DI 3699 }, 3700 outputs: []outputInfo{ 3701 {0, 239}, // AX CX DX BX BP SI DI 3702 }, 3703 }, 3704 }, 3705 { 3706 name: "MOVLconst", 3707 auxType: auxInt32, 3708 argLen: 0, 3709 rematerializeable: true, 3710 asm: x86.AMOVL, 3711 reg: regInfo{ 3712 outputs: []outputInfo{ 3713 {0, 239}, // AX CX DX BX BP SI DI 3714 }, 3715 }, 3716 }, 3717 { 3718 name: "CVTTSD2SL", 3719 argLen: 1, 3720 usesScratch: true, 3721 asm: x86.ACVTTSD2SL, 3722 reg: regInfo{ 3723 inputs: []inputInfo{ 3724 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3725 }, 3726 outputs: []outputInfo{ 3727 {0, 239}, // AX CX DX BX BP SI DI 3728 }, 3729 }, 3730 }, 3731 { 3732 name: "CVTTSS2SL", 3733 argLen: 1, 3734 usesScratch: true, 3735 asm: x86.ACVTTSS2SL, 3736 reg: regInfo{ 3737 inputs: []inputInfo{ 3738 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3739 }, 3740 outputs: []outputInfo{ 3741 {0, 239}, // AX CX DX BX BP SI DI 3742 }, 3743 }, 3744 }, 3745 { 3746 name: "CVTSL2SS", 3747 argLen: 1, 3748 usesScratch: true, 3749 asm: x86.ACVTSL2SS, 3750 reg: regInfo{ 3751 inputs: []inputInfo{ 3752 {0, 239}, // AX CX DX BX BP SI DI 3753 }, 3754 outputs: []outputInfo{ 3755 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3756 }, 3757 }, 3758 }, 3759 { 3760 name: "CVTSL2SD", 3761 argLen: 1, 3762 usesScratch: true, 3763 asm: x86.ACVTSL2SD, 3764 reg: regInfo{ 3765 inputs: []inputInfo{ 3766 {0, 239}, // AX CX DX BX BP SI DI 3767 }, 3768 outputs: []outputInfo{ 3769 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3770 }, 3771 }, 3772 }, 3773 { 3774 name: "CVTSD2SS", 3775 argLen: 1, 3776 usesScratch: true, 3777 asm: x86.ACVTSD2SS, 3778 reg: regInfo{ 3779 inputs: []inputInfo{ 3780 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3781 }, 3782 outputs: []outputInfo{ 3783 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3784 }, 3785 }, 3786 }, 3787 { 3788 name: "CVTSS2SD", 3789 argLen: 1, 3790 asm: x86.ACVTSS2SD, 3791 reg: regInfo{ 3792 inputs: []inputInfo{ 3793 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3794 }, 3795 outputs: []outputInfo{ 3796 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3797 }, 3798 }, 3799 }, 3800 { 3801 name: "PXOR", 3802 argLen: 2, 3803 commutative: true, 3804 resultInArg0: true, 3805 asm: x86.APXOR, 3806 reg: regInfo{ 3807 inputs: []inputInfo{ 3808 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3809 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3810 }, 3811 outputs: []outputInfo{ 3812 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3813 }, 3814 }, 3815 }, 3816 { 3817 name: "LEAL", 3818 auxType: auxSymOff, 3819 argLen: 1, 3820 rematerializeable: true, 3821 symEffect: SymAddr, 3822 reg: regInfo{ 3823 inputs: []inputInfo{ 3824 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3825 }, 3826 outputs: []outputInfo{ 3827 {0, 239}, // AX CX DX BX BP SI DI 3828 }, 3829 }, 3830 }, 3831 { 3832 name: "LEAL1", 3833 auxType: auxSymOff, 3834 argLen: 2, 3835 commutative: true, 3836 symEffect: SymAddr, 3837 reg: regInfo{ 3838 inputs: []inputInfo{ 3839 {1, 255}, // AX CX DX BX SP BP SI DI 3840 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3841 }, 3842 outputs: []outputInfo{ 3843 {0, 239}, // AX CX DX BX BP SI DI 3844 }, 3845 }, 3846 }, 3847 { 3848 name: "LEAL2", 3849 auxType: auxSymOff, 3850 argLen: 2, 3851 symEffect: SymAddr, 3852 reg: regInfo{ 3853 inputs: []inputInfo{ 3854 {1, 255}, // AX CX DX BX SP BP SI DI 3855 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3856 }, 3857 outputs: []outputInfo{ 3858 {0, 239}, // AX CX DX BX BP SI DI 3859 }, 3860 }, 3861 }, 3862 { 3863 name: "LEAL4", 3864 auxType: auxSymOff, 3865 argLen: 2, 3866 symEffect: SymAddr, 3867 reg: regInfo{ 3868 inputs: []inputInfo{ 3869 {1, 255}, // AX CX DX BX SP BP SI DI 3870 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3871 }, 3872 outputs: []outputInfo{ 3873 {0, 239}, // AX CX DX BX BP SI DI 3874 }, 3875 }, 3876 }, 3877 { 3878 name: "LEAL8", 3879 auxType: auxSymOff, 3880 argLen: 2, 3881 symEffect: SymAddr, 3882 reg: regInfo{ 3883 inputs: []inputInfo{ 3884 {1, 255}, // AX CX DX BX SP BP SI DI 3885 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3886 }, 3887 outputs: []outputInfo{ 3888 {0, 239}, // AX CX DX BX BP SI DI 3889 }, 3890 }, 3891 }, 3892 { 3893 name: "MOVBload", 3894 auxType: auxSymOff, 3895 argLen: 2, 3896 faultOnNilArg0: true, 3897 symEffect: SymRead, 3898 asm: x86.AMOVBLZX, 3899 reg: regInfo{ 3900 inputs: []inputInfo{ 3901 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3902 }, 3903 outputs: []outputInfo{ 3904 {0, 239}, // AX CX DX BX BP SI DI 3905 }, 3906 }, 3907 }, 3908 { 3909 name: "MOVBLSXload", 3910 auxType: auxSymOff, 3911 argLen: 2, 3912 faultOnNilArg0: true, 3913 symEffect: SymRead, 3914 asm: x86.AMOVBLSX, 3915 reg: regInfo{ 3916 inputs: []inputInfo{ 3917 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3918 }, 3919 outputs: []outputInfo{ 3920 {0, 239}, // AX CX DX BX BP SI DI 3921 }, 3922 }, 3923 }, 3924 { 3925 name: "MOVWload", 3926 auxType: auxSymOff, 3927 argLen: 2, 3928 faultOnNilArg0: true, 3929 symEffect: SymRead, 3930 asm: x86.AMOVWLZX, 3931 reg: regInfo{ 3932 inputs: []inputInfo{ 3933 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3934 }, 3935 outputs: []outputInfo{ 3936 {0, 239}, // AX CX DX BX BP SI DI 3937 }, 3938 }, 3939 }, 3940 { 3941 name: "MOVWLSXload", 3942 auxType: auxSymOff, 3943 argLen: 2, 3944 faultOnNilArg0: true, 3945 symEffect: SymRead, 3946 asm: x86.AMOVWLSX, 3947 reg: regInfo{ 3948 inputs: []inputInfo{ 3949 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3950 }, 3951 outputs: []outputInfo{ 3952 {0, 239}, // AX CX DX BX BP SI DI 3953 }, 3954 }, 3955 }, 3956 { 3957 name: "MOVLload", 3958 auxType: auxSymOff, 3959 argLen: 2, 3960 faultOnNilArg0: true, 3961 symEffect: SymRead, 3962 asm: x86.AMOVL, 3963 reg: regInfo{ 3964 inputs: []inputInfo{ 3965 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3966 }, 3967 outputs: []outputInfo{ 3968 {0, 239}, // AX CX DX BX BP SI DI 3969 }, 3970 }, 3971 }, 3972 { 3973 name: "MOVBstore", 3974 auxType: auxSymOff, 3975 argLen: 3, 3976 faultOnNilArg0: true, 3977 symEffect: SymWrite, 3978 asm: x86.AMOVB, 3979 reg: regInfo{ 3980 inputs: []inputInfo{ 3981 {1, 255}, // AX CX DX BX SP BP SI DI 3982 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3983 }, 3984 }, 3985 }, 3986 { 3987 name: "MOVWstore", 3988 auxType: auxSymOff, 3989 argLen: 3, 3990 faultOnNilArg0: true, 3991 symEffect: SymWrite, 3992 asm: x86.AMOVW, 3993 reg: regInfo{ 3994 inputs: []inputInfo{ 3995 {1, 255}, // AX CX DX BX SP BP SI DI 3996 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3997 }, 3998 }, 3999 }, 4000 { 4001 name: "MOVLstore", 4002 auxType: auxSymOff, 4003 argLen: 3, 4004 faultOnNilArg0: true, 4005 symEffect: SymWrite, 4006 asm: x86.AMOVL, 4007 reg: regInfo{ 4008 inputs: []inputInfo{ 4009 {1, 255}, // AX CX DX BX SP BP SI DI 4010 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4011 }, 4012 }, 4013 }, 4014 { 4015 name: "MOVBloadidx1", 4016 auxType: auxSymOff, 4017 argLen: 3, 4018 commutative: true, 4019 symEffect: SymRead, 4020 asm: x86.AMOVBLZX, 4021 reg: regInfo{ 4022 inputs: []inputInfo{ 4023 {1, 255}, // AX CX DX BX SP BP SI DI 4024 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4025 }, 4026 outputs: []outputInfo{ 4027 {0, 239}, // AX CX DX BX BP SI DI 4028 }, 4029 }, 4030 }, 4031 { 4032 name: "MOVWloadidx1", 4033 auxType: auxSymOff, 4034 argLen: 3, 4035 commutative: true, 4036 symEffect: SymRead, 4037 asm: x86.AMOVWLZX, 4038 reg: regInfo{ 4039 inputs: []inputInfo{ 4040 {1, 255}, // AX CX DX BX SP BP SI DI 4041 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4042 }, 4043 outputs: []outputInfo{ 4044 {0, 239}, // AX CX DX BX BP SI DI 4045 }, 4046 }, 4047 }, 4048 { 4049 name: "MOVWloadidx2", 4050 auxType: auxSymOff, 4051 argLen: 3, 4052 symEffect: SymRead, 4053 asm: x86.AMOVWLZX, 4054 reg: regInfo{ 4055 inputs: []inputInfo{ 4056 {1, 255}, // AX CX DX BX SP BP SI DI 4057 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4058 }, 4059 outputs: []outputInfo{ 4060 {0, 239}, // AX CX DX BX BP SI DI 4061 }, 4062 }, 4063 }, 4064 { 4065 name: "MOVLloadidx1", 4066 auxType: auxSymOff, 4067 argLen: 3, 4068 commutative: true, 4069 symEffect: SymRead, 4070 asm: x86.AMOVL, 4071 reg: regInfo{ 4072 inputs: []inputInfo{ 4073 {1, 255}, // AX CX DX BX SP BP SI DI 4074 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4075 }, 4076 outputs: []outputInfo{ 4077 {0, 239}, // AX CX DX BX BP SI DI 4078 }, 4079 }, 4080 }, 4081 { 4082 name: "MOVLloadidx4", 4083 auxType: auxSymOff, 4084 argLen: 3, 4085 symEffect: SymRead, 4086 asm: x86.AMOVL, 4087 reg: regInfo{ 4088 inputs: []inputInfo{ 4089 {1, 255}, // AX CX DX BX SP BP SI DI 4090 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4091 }, 4092 outputs: []outputInfo{ 4093 {0, 239}, // AX CX DX BX BP SI DI 4094 }, 4095 }, 4096 }, 4097 { 4098 name: "MOVBstoreidx1", 4099 auxType: auxSymOff, 4100 argLen: 4, 4101 commutative: true, 4102 symEffect: SymWrite, 4103 asm: x86.AMOVB, 4104 reg: regInfo{ 4105 inputs: []inputInfo{ 4106 {1, 255}, // AX CX DX BX SP BP SI DI 4107 {2, 255}, // AX CX DX BX SP BP SI DI 4108 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4109 }, 4110 }, 4111 }, 4112 { 4113 name: "MOVWstoreidx1", 4114 auxType: auxSymOff, 4115 argLen: 4, 4116 commutative: true, 4117 symEffect: SymWrite, 4118 asm: x86.AMOVW, 4119 reg: regInfo{ 4120 inputs: []inputInfo{ 4121 {1, 255}, // AX CX DX BX SP BP SI DI 4122 {2, 255}, // AX CX DX BX SP BP SI DI 4123 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4124 }, 4125 }, 4126 }, 4127 { 4128 name: "MOVWstoreidx2", 4129 auxType: auxSymOff, 4130 argLen: 4, 4131 symEffect: SymWrite, 4132 asm: x86.AMOVW, 4133 reg: regInfo{ 4134 inputs: []inputInfo{ 4135 {1, 255}, // AX CX DX BX SP BP SI DI 4136 {2, 255}, // AX CX DX BX SP BP SI DI 4137 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4138 }, 4139 }, 4140 }, 4141 { 4142 name: "MOVLstoreidx1", 4143 auxType: auxSymOff, 4144 argLen: 4, 4145 commutative: true, 4146 symEffect: SymWrite, 4147 asm: x86.AMOVL, 4148 reg: regInfo{ 4149 inputs: []inputInfo{ 4150 {1, 255}, // AX CX DX BX SP BP SI DI 4151 {2, 255}, // AX CX DX BX SP BP SI DI 4152 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4153 }, 4154 }, 4155 }, 4156 { 4157 name: "MOVLstoreidx4", 4158 auxType: auxSymOff, 4159 argLen: 4, 4160 symEffect: SymWrite, 4161 asm: x86.AMOVL, 4162 reg: regInfo{ 4163 inputs: []inputInfo{ 4164 {1, 255}, // AX CX DX BX SP BP SI DI 4165 {2, 255}, // AX CX DX BX SP BP SI DI 4166 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4167 }, 4168 }, 4169 }, 4170 { 4171 name: "MOVBstoreconst", 4172 auxType: auxSymValAndOff, 4173 argLen: 2, 4174 faultOnNilArg0: true, 4175 symEffect: SymWrite, 4176 asm: x86.AMOVB, 4177 reg: regInfo{ 4178 inputs: []inputInfo{ 4179 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4180 }, 4181 }, 4182 }, 4183 { 4184 name: "MOVWstoreconst", 4185 auxType: auxSymValAndOff, 4186 argLen: 2, 4187 faultOnNilArg0: true, 4188 symEffect: SymWrite, 4189 asm: x86.AMOVW, 4190 reg: regInfo{ 4191 inputs: []inputInfo{ 4192 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4193 }, 4194 }, 4195 }, 4196 { 4197 name: "MOVLstoreconst", 4198 auxType: auxSymValAndOff, 4199 argLen: 2, 4200 faultOnNilArg0: true, 4201 symEffect: SymWrite, 4202 asm: x86.AMOVL, 4203 reg: regInfo{ 4204 inputs: []inputInfo{ 4205 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4206 }, 4207 }, 4208 }, 4209 { 4210 name: "MOVBstoreconstidx1", 4211 auxType: auxSymValAndOff, 4212 argLen: 3, 4213 symEffect: SymWrite, 4214 asm: x86.AMOVB, 4215 reg: regInfo{ 4216 inputs: []inputInfo{ 4217 {1, 255}, // AX CX DX BX SP BP SI DI 4218 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4219 }, 4220 }, 4221 }, 4222 { 4223 name: "MOVWstoreconstidx1", 4224 auxType: auxSymValAndOff, 4225 argLen: 3, 4226 symEffect: SymWrite, 4227 asm: x86.AMOVW, 4228 reg: regInfo{ 4229 inputs: []inputInfo{ 4230 {1, 255}, // AX CX DX BX SP BP SI DI 4231 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4232 }, 4233 }, 4234 }, 4235 { 4236 name: "MOVWstoreconstidx2", 4237 auxType: auxSymValAndOff, 4238 argLen: 3, 4239 symEffect: SymWrite, 4240 asm: x86.AMOVW, 4241 reg: regInfo{ 4242 inputs: []inputInfo{ 4243 {1, 255}, // AX CX DX BX SP BP SI DI 4244 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4245 }, 4246 }, 4247 }, 4248 { 4249 name: "MOVLstoreconstidx1", 4250 auxType: auxSymValAndOff, 4251 argLen: 3, 4252 symEffect: SymWrite, 4253 asm: x86.AMOVL, 4254 reg: regInfo{ 4255 inputs: []inputInfo{ 4256 {1, 255}, // AX CX DX BX SP BP SI DI 4257 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4258 }, 4259 }, 4260 }, 4261 { 4262 name: "MOVLstoreconstidx4", 4263 auxType: auxSymValAndOff, 4264 argLen: 3, 4265 symEffect: SymWrite, 4266 asm: x86.AMOVL, 4267 reg: regInfo{ 4268 inputs: []inputInfo{ 4269 {1, 255}, // AX CX DX BX SP BP SI DI 4270 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4271 }, 4272 }, 4273 }, 4274 { 4275 name: "DUFFZERO", 4276 auxType: auxInt64, 4277 argLen: 3, 4278 faultOnNilArg0: true, 4279 reg: regInfo{ 4280 inputs: []inputInfo{ 4281 {0, 128}, // DI 4282 {1, 1}, // AX 4283 }, 4284 clobbers: 130, // CX DI 4285 }, 4286 }, 4287 { 4288 name: "REPSTOSL", 4289 argLen: 4, 4290 faultOnNilArg0: true, 4291 reg: regInfo{ 4292 inputs: []inputInfo{ 4293 {0, 128}, // DI 4294 {1, 2}, // CX 4295 {2, 1}, // AX 4296 }, 4297 clobbers: 130, // CX DI 4298 }, 4299 }, 4300 { 4301 name: "CALLstatic", 4302 auxType: auxSymOff, 4303 argLen: 1, 4304 clobberFlags: true, 4305 call: true, 4306 symEffect: SymNone, 4307 reg: regInfo{ 4308 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4309 }, 4310 }, 4311 { 4312 name: "CALLclosure", 4313 auxType: auxInt64, 4314 argLen: 3, 4315 clobberFlags: true, 4316 call: true, 4317 reg: regInfo{ 4318 inputs: []inputInfo{ 4319 {1, 4}, // DX 4320 {0, 255}, // AX CX DX BX SP BP SI DI 4321 }, 4322 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4323 }, 4324 }, 4325 { 4326 name: "CALLinter", 4327 auxType: auxInt64, 4328 argLen: 2, 4329 clobberFlags: true, 4330 call: true, 4331 reg: regInfo{ 4332 inputs: []inputInfo{ 4333 {0, 239}, // AX CX DX BX BP SI DI 4334 }, 4335 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4336 }, 4337 }, 4338 { 4339 name: "DUFFCOPY", 4340 auxType: auxInt64, 4341 argLen: 3, 4342 clobberFlags: true, 4343 faultOnNilArg0: true, 4344 faultOnNilArg1: true, 4345 reg: regInfo{ 4346 inputs: []inputInfo{ 4347 {0, 128}, // DI 4348 {1, 64}, // SI 4349 }, 4350 clobbers: 194, // CX SI DI 4351 }, 4352 }, 4353 { 4354 name: "REPMOVSL", 4355 argLen: 4, 4356 faultOnNilArg0: true, 4357 faultOnNilArg1: true, 4358 reg: regInfo{ 4359 inputs: []inputInfo{ 4360 {0, 128}, // DI 4361 {1, 64}, // SI 4362 {2, 2}, // CX 4363 }, 4364 clobbers: 194, // CX SI DI 4365 }, 4366 }, 4367 { 4368 name: "InvertFlags", 4369 argLen: 1, 4370 reg: regInfo{}, 4371 }, 4372 { 4373 name: "LoweredGetG", 4374 argLen: 1, 4375 reg: regInfo{ 4376 outputs: []outputInfo{ 4377 {0, 239}, // AX CX DX BX BP SI DI 4378 }, 4379 }, 4380 }, 4381 { 4382 name: "LoweredGetClosurePtr", 4383 argLen: 0, 4384 reg: regInfo{ 4385 outputs: []outputInfo{ 4386 {0, 4}, // DX 4387 }, 4388 }, 4389 }, 4390 { 4391 name: "LoweredGetCallerPC", 4392 argLen: 0, 4393 rematerializeable: true, 4394 reg: regInfo{ 4395 outputs: []outputInfo{ 4396 {0, 239}, // AX CX DX BX BP SI DI 4397 }, 4398 }, 4399 }, 4400 { 4401 name: "LoweredGetCallerSP", 4402 argLen: 0, 4403 rematerializeable: true, 4404 reg: regInfo{ 4405 outputs: []outputInfo{ 4406 {0, 239}, // AX CX DX BX BP SI DI 4407 }, 4408 }, 4409 }, 4410 { 4411 name: "LoweredNilCheck", 4412 argLen: 2, 4413 clobberFlags: true, 4414 nilCheck: true, 4415 faultOnNilArg0: true, 4416 reg: regInfo{ 4417 inputs: []inputInfo{ 4418 {0, 255}, // AX CX DX BX SP BP SI DI 4419 }, 4420 }, 4421 }, 4422 { 4423 name: "LoweredWB", 4424 auxType: auxSym, 4425 argLen: 3, 4426 clobberFlags: true, 4427 symEffect: SymNone, 4428 reg: regInfo{ 4429 inputs: []inputInfo{ 4430 {0, 128}, // DI 4431 {1, 1}, // AX 4432 }, 4433 clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7 4434 }, 4435 }, 4436 { 4437 name: "MOVLconvert", 4438 argLen: 2, 4439 resultInArg0: true, 4440 asm: x86.AMOVL, 4441 reg: regInfo{ 4442 inputs: []inputInfo{ 4443 {0, 239}, // AX CX DX BX BP SI DI 4444 }, 4445 outputs: []outputInfo{ 4446 {0, 239}, // AX CX DX BX BP SI DI 4447 }, 4448 }, 4449 }, 4450 { 4451 name: "FlagEQ", 4452 argLen: 0, 4453 reg: regInfo{}, 4454 }, 4455 { 4456 name: "FlagLT_ULT", 4457 argLen: 0, 4458 reg: regInfo{}, 4459 }, 4460 { 4461 name: "FlagLT_UGT", 4462 argLen: 0, 4463 reg: regInfo{}, 4464 }, 4465 { 4466 name: "FlagGT_UGT", 4467 argLen: 0, 4468 reg: regInfo{}, 4469 }, 4470 { 4471 name: "FlagGT_ULT", 4472 argLen: 0, 4473 reg: regInfo{}, 4474 }, 4475 { 4476 name: "FCHS", 4477 argLen: 1, 4478 reg: regInfo{ 4479 inputs: []inputInfo{ 4480 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4481 }, 4482 outputs: []outputInfo{ 4483 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4484 }, 4485 }, 4486 }, 4487 { 4488 name: "MOVSSconst1", 4489 auxType: auxFloat32, 4490 argLen: 0, 4491 reg: regInfo{ 4492 outputs: []outputInfo{ 4493 {0, 239}, // AX CX DX BX BP SI DI 4494 }, 4495 }, 4496 }, 4497 { 4498 name: "MOVSDconst1", 4499 auxType: auxFloat64, 4500 argLen: 0, 4501 reg: regInfo{ 4502 outputs: []outputInfo{ 4503 {0, 239}, // AX CX DX BX BP SI DI 4504 }, 4505 }, 4506 }, 4507 { 4508 name: "MOVSSconst2", 4509 argLen: 1, 4510 asm: x86.AMOVSS, 4511 reg: regInfo{ 4512 inputs: []inputInfo{ 4513 {0, 239}, // AX CX DX BX BP SI DI 4514 }, 4515 outputs: []outputInfo{ 4516 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4517 }, 4518 }, 4519 }, 4520 { 4521 name: "MOVSDconst2", 4522 argLen: 1, 4523 asm: x86.AMOVSD, 4524 reg: regInfo{ 4525 inputs: []inputInfo{ 4526 {0, 239}, // AX CX DX BX BP SI DI 4527 }, 4528 outputs: []outputInfo{ 4529 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4530 }, 4531 }, 4532 }, 4533 4534 { 4535 name: "ADDSS", 4536 argLen: 2, 4537 commutative: true, 4538 resultInArg0: true, 4539 asm: x86.AADDSS, 4540 reg: regInfo{ 4541 inputs: []inputInfo{ 4542 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4543 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4544 }, 4545 outputs: []outputInfo{ 4546 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4547 }, 4548 }, 4549 }, 4550 { 4551 name: "ADDSD", 4552 argLen: 2, 4553 commutative: true, 4554 resultInArg0: true, 4555 asm: x86.AADDSD, 4556 reg: regInfo{ 4557 inputs: []inputInfo{ 4558 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4559 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4560 }, 4561 outputs: []outputInfo{ 4562 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4563 }, 4564 }, 4565 }, 4566 { 4567 name: "SUBSS", 4568 argLen: 2, 4569 resultInArg0: true, 4570 asm: x86.ASUBSS, 4571 reg: regInfo{ 4572 inputs: []inputInfo{ 4573 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4574 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4575 }, 4576 outputs: []outputInfo{ 4577 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4578 }, 4579 }, 4580 }, 4581 { 4582 name: "SUBSD", 4583 argLen: 2, 4584 resultInArg0: true, 4585 asm: x86.ASUBSD, 4586 reg: regInfo{ 4587 inputs: []inputInfo{ 4588 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4589 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4590 }, 4591 outputs: []outputInfo{ 4592 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4593 }, 4594 }, 4595 }, 4596 { 4597 name: "MULSS", 4598 argLen: 2, 4599 commutative: true, 4600 resultInArg0: true, 4601 asm: x86.AMULSS, 4602 reg: regInfo{ 4603 inputs: []inputInfo{ 4604 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4605 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4606 }, 4607 outputs: []outputInfo{ 4608 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4609 }, 4610 }, 4611 }, 4612 { 4613 name: "MULSD", 4614 argLen: 2, 4615 commutative: true, 4616 resultInArg0: true, 4617 asm: x86.AMULSD, 4618 reg: regInfo{ 4619 inputs: []inputInfo{ 4620 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4621 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4622 }, 4623 outputs: []outputInfo{ 4624 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4625 }, 4626 }, 4627 }, 4628 { 4629 name: "DIVSS", 4630 argLen: 2, 4631 resultInArg0: true, 4632 asm: x86.ADIVSS, 4633 reg: regInfo{ 4634 inputs: []inputInfo{ 4635 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4636 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4637 }, 4638 outputs: []outputInfo{ 4639 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4640 }, 4641 }, 4642 }, 4643 { 4644 name: "DIVSD", 4645 argLen: 2, 4646 resultInArg0: true, 4647 asm: x86.ADIVSD, 4648 reg: regInfo{ 4649 inputs: []inputInfo{ 4650 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4651 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4652 }, 4653 outputs: []outputInfo{ 4654 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4655 }, 4656 }, 4657 }, 4658 { 4659 name: "MOVSSload", 4660 auxType: auxSymOff, 4661 argLen: 2, 4662 faultOnNilArg0: true, 4663 symEffect: SymRead, 4664 asm: x86.AMOVSS, 4665 reg: regInfo{ 4666 inputs: []inputInfo{ 4667 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4668 }, 4669 outputs: []outputInfo{ 4670 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4671 }, 4672 }, 4673 }, 4674 { 4675 name: "MOVSDload", 4676 auxType: auxSymOff, 4677 argLen: 2, 4678 faultOnNilArg0: true, 4679 symEffect: SymRead, 4680 asm: x86.AMOVSD, 4681 reg: regInfo{ 4682 inputs: []inputInfo{ 4683 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4684 }, 4685 outputs: []outputInfo{ 4686 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4687 }, 4688 }, 4689 }, 4690 { 4691 name: "MOVSSconst", 4692 auxType: auxFloat32, 4693 argLen: 0, 4694 rematerializeable: true, 4695 asm: x86.AMOVSS, 4696 reg: regInfo{ 4697 outputs: []outputInfo{ 4698 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4699 }, 4700 }, 4701 }, 4702 { 4703 name: "MOVSDconst", 4704 auxType: auxFloat64, 4705 argLen: 0, 4706 rematerializeable: true, 4707 asm: x86.AMOVSD, 4708 reg: regInfo{ 4709 outputs: []outputInfo{ 4710 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4711 }, 4712 }, 4713 }, 4714 { 4715 name: "MOVSSloadidx1", 4716 auxType: auxSymOff, 4717 argLen: 3, 4718 symEffect: SymRead, 4719 asm: x86.AMOVSS, 4720 reg: regInfo{ 4721 inputs: []inputInfo{ 4722 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4723 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4724 }, 4725 outputs: []outputInfo{ 4726 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4727 }, 4728 }, 4729 }, 4730 { 4731 name: "MOVSSloadidx4", 4732 auxType: auxSymOff, 4733 argLen: 3, 4734 symEffect: SymRead, 4735 asm: x86.AMOVSS, 4736 reg: regInfo{ 4737 inputs: []inputInfo{ 4738 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4739 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4740 }, 4741 outputs: []outputInfo{ 4742 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4743 }, 4744 }, 4745 }, 4746 { 4747 name: "MOVSDloadidx1", 4748 auxType: auxSymOff, 4749 argLen: 3, 4750 symEffect: SymRead, 4751 asm: x86.AMOVSD, 4752 reg: regInfo{ 4753 inputs: []inputInfo{ 4754 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4755 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4756 }, 4757 outputs: []outputInfo{ 4758 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4759 }, 4760 }, 4761 }, 4762 { 4763 name: "MOVSDloadidx8", 4764 auxType: auxSymOff, 4765 argLen: 3, 4766 symEffect: SymRead, 4767 asm: x86.AMOVSD, 4768 reg: regInfo{ 4769 inputs: []inputInfo{ 4770 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4771 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4772 }, 4773 outputs: []outputInfo{ 4774 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4775 }, 4776 }, 4777 }, 4778 { 4779 name: "MOVSSstore", 4780 auxType: auxSymOff, 4781 argLen: 3, 4782 faultOnNilArg0: true, 4783 symEffect: SymWrite, 4784 asm: x86.AMOVSS, 4785 reg: regInfo{ 4786 inputs: []inputInfo{ 4787 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4788 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4789 }, 4790 }, 4791 }, 4792 { 4793 name: "MOVSDstore", 4794 auxType: auxSymOff, 4795 argLen: 3, 4796 faultOnNilArg0: true, 4797 symEffect: SymWrite, 4798 asm: x86.AMOVSD, 4799 reg: regInfo{ 4800 inputs: []inputInfo{ 4801 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4802 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4803 }, 4804 }, 4805 }, 4806 { 4807 name: "MOVSSstoreidx1", 4808 auxType: auxSymOff, 4809 argLen: 4, 4810 symEffect: SymWrite, 4811 asm: x86.AMOVSS, 4812 reg: regInfo{ 4813 inputs: []inputInfo{ 4814 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4815 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4816 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4817 }, 4818 }, 4819 }, 4820 { 4821 name: "MOVSSstoreidx4", 4822 auxType: auxSymOff, 4823 argLen: 4, 4824 symEffect: SymWrite, 4825 asm: x86.AMOVSS, 4826 reg: regInfo{ 4827 inputs: []inputInfo{ 4828 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4829 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4830 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4831 }, 4832 }, 4833 }, 4834 { 4835 name: "MOVSDstoreidx1", 4836 auxType: auxSymOff, 4837 argLen: 4, 4838 symEffect: SymWrite, 4839 asm: x86.AMOVSD, 4840 reg: regInfo{ 4841 inputs: []inputInfo{ 4842 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4843 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4844 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4845 }, 4846 }, 4847 }, 4848 { 4849 name: "MOVSDstoreidx8", 4850 auxType: auxSymOff, 4851 argLen: 4, 4852 symEffect: SymWrite, 4853 asm: x86.AMOVSD, 4854 reg: regInfo{ 4855 inputs: []inputInfo{ 4856 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4857 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4858 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4859 }, 4860 }, 4861 }, 4862 { 4863 name: "ADDSSmem", 4864 auxType: auxSymOff, 4865 argLen: 3, 4866 resultInArg0: true, 4867 faultOnNilArg1: true, 4868 symEffect: SymRead, 4869 asm: x86.AADDSS, 4870 reg: regInfo{ 4871 inputs: []inputInfo{ 4872 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4873 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4874 }, 4875 outputs: []outputInfo{ 4876 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4877 }, 4878 }, 4879 }, 4880 { 4881 name: "ADDSDmem", 4882 auxType: auxSymOff, 4883 argLen: 3, 4884 resultInArg0: true, 4885 faultOnNilArg1: true, 4886 symEffect: SymRead, 4887 asm: x86.AADDSD, 4888 reg: regInfo{ 4889 inputs: []inputInfo{ 4890 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4891 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4892 }, 4893 outputs: []outputInfo{ 4894 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4895 }, 4896 }, 4897 }, 4898 { 4899 name: "SUBSSmem", 4900 auxType: auxSymOff, 4901 argLen: 3, 4902 resultInArg0: true, 4903 faultOnNilArg1: true, 4904 symEffect: SymRead, 4905 asm: x86.ASUBSS, 4906 reg: regInfo{ 4907 inputs: []inputInfo{ 4908 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4909 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4910 }, 4911 outputs: []outputInfo{ 4912 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4913 }, 4914 }, 4915 }, 4916 { 4917 name: "SUBSDmem", 4918 auxType: auxSymOff, 4919 argLen: 3, 4920 resultInArg0: true, 4921 faultOnNilArg1: true, 4922 symEffect: SymRead, 4923 asm: x86.ASUBSD, 4924 reg: regInfo{ 4925 inputs: []inputInfo{ 4926 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4927 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4928 }, 4929 outputs: []outputInfo{ 4930 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4931 }, 4932 }, 4933 }, 4934 { 4935 name: "MULSSmem", 4936 auxType: auxSymOff, 4937 argLen: 3, 4938 resultInArg0: true, 4939 faultOnNilArg1: true, 4940 symEffect: SymRead, 4941 asm: x86.AMULSS, 4942 reg: regInfo{ 4943 inputs: []inputInfo{ 4944 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4945 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4946 }, 4947 outputs: []outputInfo{ 4948 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4949 }, 4950 }, 4951 }, 4952 { 4953 name: "MULSDmem", 4954 auxType: auxSymOff, 4955 argLen: 3, 4956 resultInArg0: true, 4957 faultOnNilArg1: true, 4958 symEffect: SymRead, 4959 asm: x86.AMULSD, 4960 reg: regInfo{ 4961 inputs: []inputInfo{ 4962 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4963 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4964 }, 4965 outputs: []outputInfo{ 4966 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4967 }, 4968 }, 4969 }, 4970 { 4971 name: "ADDQ", 4972 argLen: 2, 4973 commutative: true, 4974 clobberFlags: true, 4975 asm: x86.AADDQ, 4976 reg: regInfo{ 4977 inputs: []inputInfo{ 4978 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4979 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4980 }, 4981 outputs: []outputInfo{ 4982 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4983 }, 4984 }, 4985 }, 4986 { 4987 name: "ADDL", 4988 argLen: 2, 4989 commutative: true, 4990 clobberFlags: true, 4991 asm: x86.AADDL, 4992 reg: regInfo{ 4993 inputs: []inputInfo{ 4994 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4995 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4996 }, 4997 outputs: []outputInfo{ 4998 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4999 }, 5000 }, 5001 }, 5002 { 5003 name: "ADDQconst", 5004 auxType: auxInt32, 5005 argLen: 1, 5006 clobberFlags: true, 5007 asm: x86.AADDQ, 5008 reg: regInfo{ 5009 inputs: []inputInfo{ 5010 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5011 }, 5012 outputs: []outputInfo{ 5013 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5014 }, 5015 }, 5016 }, 5017 { 5018 name: "ADDLconst", 5019 auxType: auxInt32, 5020 argLen: 1, 5021 clobberFlags: true, 5022 asm: x86.AADDL, 5023 reg: regInfo{ 5024 inputs: []inputInfo{ 5025 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5026 }, 5027 outputs: []outputInfo{ 5028 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5029 }, 5030 }, 5031 }, 5032 { 5033 name: "ADDQconstmem", 5034 auxType: auxSymValAndOff, 5035 argLen: 2, 5036 clobberFlags: true, 5037 faultOnNilArg0: true, 5038 symEffect: SymWrite, 5039 asm: x86.AADDQ, 5040 reg: regInfo{ 5041 inputs: []inputInfo{ 5042 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5043 }, 5044 }, 5045 }, 5046 { 5047 name: "ADDLconstmem", 5048 auxType: auxSymValAndOff, 5049 argLen: 2, 5050 clobberFlags: true, 5051 faultOnNilArg0: true, 5052 symEffect: SymWrite, 5053 asm: x86.AADDL, 5054 reg: regInfo{ 5055 inputs: []inputInfo{ 5056 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5057 }, 5058 }, 5059 }, 5060 { 5061 name: "SUBQ", 5062 argLen: 2, 5063 resultInArg0: true, 5064 clobberFlags: true, 5065 asm: x86.ASUBQ, 5066 reg: regInfo{ 5067 inputs: []inputInfo{ 5068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5069 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5070 }, 5071 outputs: []outputInfo{ 5072 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5073 }, 5074 }, 5075 }, 5076 { 5077 name: "SUBL", 5078 argLen: 2, 5079 resultInArg0: true, 5080 clobberFlags: true, 5081 asm: x86.ASUBL, 5082 reg: regInfo{ 5083 inputs: []inputInfo{ 5084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5085 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5086 }, 5087 outputs: []outputInfo{ 5088 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5089 }, 5090 }, 5091 }, 5092 { 5093 name: "SUBQconst", 5094 auxType: auxInt32, 5095 argLen: 1, 5096 resultInArg0: true, 5097 clobberFlags: true, 5098 asm: x86.ASUBQ, 5099 reg: regInfo{ 5100 inputs: []inputInfo{ 5101 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5102 }, 5103 outputs: []outputInfo{ 5104 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5105 }, 5106 }, 5107 }, 5108 { 5109 name: "SUBLconst", 5110 auxType: auxInt32, 5111 argLen: 1, 5112 resultInArg0: true, 5113 clobberFlags: true, 5114 asm: x86.ASUBL, 5115 reg: regInfo{ 5116 inputs: []inputInfo{ 5117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5118 }, 5119 outputs: []outputInfo{ 5120 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5121 }, 5122 }, 5123 }, 5124 { 5125 name: "MULQ", 5126 argLen: 2, 5127 commutative: true, 5128 resultInArg0: true, 5129 clobberFlags: true, 5130 asm: x86.AIMULQ, 5131 reg: regInfo{ 5132 inputs: []inputInfo{ 5133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5134 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5135 }, 5136 outputs: []outputInfo{ 5137 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5138 }, 5139 }, 5140 }, 5141 { 5142 name: "MULL", 5143 argLen: 2, 5144 commutative: true, 5145 resultInArg0: true, 5146 clobberFlags: true, 5147 asm: x86.AIMULL, 5148 reg: regInfo{ 5149 inputs: []inputInfo{ 5150 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5151 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5152 }, 5153 outputs: []outputInfo{ 5154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5155 }, 5156 }, 5157 }, 5158 { 5159 name: "MULQconst", 5160 auxType: auxInt32, 5161 argLen: 1, 5162 resultInArg0: true, 5163 clobberFlags: true, 5164 asm: x86.AIMULQ, 5165 reg: regInfo{ 5166 inputs: []inputInfo{ 5167 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5168 }, 5169 outputs: []outputInfo{ 5170 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5171 }, 5172 }, 5173 }, 5174 { 5175 name: "MULLconst", 5176 auxType: auxInt32, 5177 argLen: 1, 5178 resultInArg0: true, 5179 clobberFlags: true, 5180 asm: x86.AIMULL, 5181 reg: regInfo{ 5182 inputs: []inputInfo{ 5183 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5184 }, 5185 outputs: []outputInfo{ 5186 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5187 }, 5188 }, 5189 }, 5190 { 5191 name: "HMULQ", 5192 argLen: 2, 5193 commutative: true, 5194 clobberFlags: true, 5195 asm: x86.AIMULQ, 5196 reg: regInfo{ 5197 inputs: []inputInfo{ 5198 {0, 1}, // AX 5199 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5200 }, 5201 clobbers: 1, // AX 5202 outputs: []outputInfo{ 5203 {0, 4}, // DX 5204 }, 5205 }, 5206 }, 5207 { 5208 name: "HMULL", 5209 argLen: 2, 5210 commutative: true, 5211 clobberFlags: true, 5212 asm: x86.AIMULL, 5213 reg: regInfo{ 5214 inputs: []inputInfo{ 5215 {0, 1}, // AX 5216 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5217 }, 5218 clobbers: 1, // AX 5219 outputs: []outputInfo{ 5220 {0, 4}, // DX 5221 }, 5222 }, 5223 }, 5224 { 5225 name: "HMULQU", 5226 argLen: 2, 5227 commutative: true, 5228 clobberFlags: true, 5229 asm: x86.AMULQ, 5230 reg: regInfo{ 5231 inputs: []inputInfo{ 5232 {0, 1}, // AX 5233 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5234 }, 5235 clobbers: 1, // AX 5236 outputs: []outputInfo{ 5237 {0, 4}, // DX 5238 }, 5239 }, 5240 }, 5241 { 5242 name: "HMULLU", 5243 argLen: 2, 5244 commutative: true, 5245 clobberFlags: true, 5246 asm: x86.AMULL, 5247 reg: regInfo{ 5248 inputs: []inputInfo{ 5249 {0, 1}, // AX 5250 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5251 }, 5252 clobbers: 1, // AX 5253 outputs: []outputInfo{ 5254 {0, 4}, // DX 5255 }, 5256 }, 5257 }, 5258 { 5259 name: "AVGQU", 5260 argLen: 2, 5261 commutative: true, 5262 resultInArg0: true, 5263 clobberFlags: true, 5264 reg: regInfo{ 5265 inputs: []inputInfo{ 5266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5267 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5268 }, 5269 outputs: []outputInfo{ 5270 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5271 }, 5272 }, 5273 }, 5274 { 5275 name: "DIVQ", 5276 argLen: 2, 5277 clobberFlags: true, 5278 asm: x86.AIDIVQ, 5279 reg: regInfo{ 5280 inputs: []inputInfo{ 5281 {0, 1}, // AX 5282 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5283 }, 5284 outputs: []outputInfo{ 5285 {0, 1}, // AX 5286 {1, 4}, // DX 5287 }, 5288 }, 5289 }, 5290 { 5291 name: "DIVL", 5292 argLen: 2, 5293 clobberFlags: true, 5294 asm: x86.AIDIVL, 5295 reg: regInfo{ 5296 inputs: []inputInfo{ 5297 {0, 1}, // AX 5298 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5299 }, 5300 outputs: []outputInfo{ 5301 {0, 1}, // AX 5302 {1, 4}, // DX 5303 }, 5304 }, 5305 }, 5306 { 5307 name: "DIVW", 5308 argLen: 2, 5309 clobberFlags: true, 5310 asm: x86.AIDIVW, 5311 reg: regInfo{ 5312 inputs: []inputInfo{ 5313 {0, 1}, // AX 5314 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5315 }, 5316 outputs: []outputInfo{ 5317 {0, 1}, // AX 5318 {1, 4}, // DX 5319 }, 5320 }, 5321 }, 5322 { 5323 name: "DIVQU", 5324 argLen: 2, 5325 clobberFlags: true, 5326 asm: x86.ADIVQ, 5327 reg: regInfo{ 5328 inputs: []inputInfo{ 5329 {0, 1}, // AX 5330 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5331 }, 5332 outputs: []outputInfo{ 5333 {0, 1}, // AX 5334 {1, 4}, // DX 5335 }, 5336 }, 5337 }, 5338 { 5339 name: "DIVLU", 5340 argLen: 2, 5341 clobberFlags: true, 5342 asm: x86.ADIVL, 5343 reg: regInfo{ 5344 inputs: []inputInfo{ 5345 {0, 1}, // AX 5346 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5347 }, 5348 outputs: []outputInfo{ 5349 {0, 1}, // AX 5350 {1, 4}, // DX 5351 }, 5352 }, 5353 }, 5354 { 5355 name: "DIVWU", 5356 argLen: 2, 5357 clobberFlags: true, 5358 asm: x86.ADIVW, 5359 reg: regInfo{ 5360 inputs: []inputInfo{ 5361 {0, 1}, // AX 5362 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5363 }, 5364 outputs: []outputInfo{ 5365 {0, 1}, // AX 5366 {1, 4}, // DX 5367 }, 5368 }, 5369 }, 5370 { 5371 name: "MULQU2", 5372 argLen: 2, 5373 commutative: true, 5374 clobberFlags: true, 5375 asm: x86.AMULQ, 5376 reg: regInfo{ 5377 inputs: []inputInfo{ 5378 {0, 1}, // AX 5379 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5380 }, 5381 outputs: []outputInfo{ 5382 {0, 4}, // DX 5383 {1, 1}, // AX 5384 }, 5385 }, 5386 }, 5387 { 5388 name: "DIVQU2", 5389 argLen: 3, 5390 clobberFlags: true, 5391 asm: x86.ADIVQ, 5392 reg: regInfo{ 5393 inputs: []inputInfo{ 5394 {0, 4}, // DX 5395 {1, 1}, // AX 5396 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5397 }, 5398 outputs: []outputInfo{ 5399 {0, 1}, // AX 5400 {1, 4}, // DX 5401 }, 5402 }, 5403 }, 5404 { 5405 name: "ANDQ", 5406 argLen: 2, 5407 commutative: true, 5408 resultInArg0: true, 5409 clobberFlags: true, 5410 asm: x86.AANDQ, 5411 reg: regInfo{ 5412 inputs: []inputInfo{ 5413 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5414 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5415 }, 5416 outputs: []outputInfo{ 5417 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5418 }, 5419 }, 5420 }, 5421 { 5422 name: "ANDL", 5423 argLen: 2, 5424 commutative: true, 5425 resultInArg0: true, 5426 clobberFlags: true, 5427 asm: x86.AANDL, 5428 reg: regInfo{ 5429 inputs: []inputInfo{ 5430 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5431 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5432 }, 5433 outputs: []outputInfo{ 5434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5435 }, 5436 }, 5437 }, 5438 { 5439 name: "ANDQconst", 5440 auxType: auxInt32, 5441 argLen: 1, 5442 resultInArg0: true, 5443 clobberFlags: true, 5444 asm: x86.AANDQ, 5445 reg: regInfo{ 5446 inputs: []inputInfo{ 5447 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5448 }, 5449 outputs: []outputInfo{ 5450 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5451 }, 5452 }, 5453 }, 5454 { 5455 name: "ANDLconst", 5456 auxType: auxInt32, 5457 argLen: 1, 5458 resultInArg0: true, 5459 clobberFlags: true, 5460 asm: x86.AANDL, 5461 reg: regInfo{ 5462 inputs: []inputInfo{ 5463 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5464 }, 5465 outputs: []outputInfo{ 5466 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5467 }, 5468 }, 5469 }, 5470 { 5471 name: "ORQ", 5472 argLen: 2, 5473 commutative: true, 5474 resultInArg0: true, 5475 clobberFlags: true, 5476 asm: x86.AORQ, 5477 reg: regInfo{ 5478 inputs: []inputInfo{ 5479 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5480 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5481 }, 5482 outputs: []outputInfo{ 5483 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5484 }, 5485 }, 5486 }, 5487 { 5488 name: "ORL", 5489 argLen: 2, 5490 commutative: true, 5491 resultInArg0: true, 5492 clobberFlags: true, 5493 asm: x86.AORL, 5494 reg: regInfo{ 5495 inputs: []inputInfo{ 5496 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5497 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5498 }, 5499 outputs: []outputInfo{ 5500 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5501 }, 5502 }, 5503 }, 5504 { 5505 name: "ORQconst", 5506 auxType: auxInt32, 5507 argLen: 1, 5508 resultInArg0: true, 5509 clobberFlags: true, 5510 asm: x86.AORQ, 5511 reg: regInfo{ 5512 inputs: []inputInfo{ 5513 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5514 }, 5515 outputs: []outputInfo{ 5516 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5517 }, 5518 }, 5519 }, 5520 { 5521 name: "ORLconst", 5522 auxType: auxInt32, 5523 argLen: 1, 5524 resultInArg0: true, 5525 clobberFlags: true, 5526 asm: x86.AORL, 5527 reg: regInfo{ 5528 inputs: []inputInfo{ 5529 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5530 }, 5531 outputs: []outputInfo{ 5532 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5533 }, 5534 }, 5535 }, 5536 { 5537 name: "XORQ", 5538 argLen: 2, 5539 commutative: true, 5540 resultInArg0: true, 5541 clobberFlags: true, 5542 asm: x86.AXORQ, 5543 reg: regInfo{ 5544 inputs: []inputInfo{ 5545 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5546 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5547 }, 5548 outputs: []outputInfo{ 5549 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5550 }, 5551 }, 5552 }, 5553 { 5554 name: "XORL", 5555 argLen: 2, 5556 commutative: true, 5557 resultInArg0: true, 5558 clobberFlags: true, 5559 asm: x86.AXORL, 5560 reg: regInfo{ 5561 inputs: []inputInfo{ 5562 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5563 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5564 }, 5565 outputs: []outputInfo{ 5566 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5567 }, 5568 }, 5569 }, 5570 { 5571 name: "XORQconst", 5572 auxType: auxInt32, 5573 argLen: 1, 5574 resultInArg0: true, 5575 clobberFlags: true, 5576 asm: x86.AXORQ, 5577 reg: regInfo{ 5578 inputs: []inputInfo{ 5579 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5580 }, 5581 outputs: []outputInfo{ 5582 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5583 }, 5584 }, 5585 }, 5586 { 5587 name: "XORLconst", 5588 auxType: auxInt32, 5589 argLen: 1, 5590 resultInArg0: true, 5591 clobberFlags: true, 5592 asm: x86.AXORL, 5593 reg: regInfo{ 5594 inputs: []inputInfo{ 5595 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5596 }, 5597 outputs: []outputInfo{ 5598 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5599 }, 5600 }, 5601 }, 5602 { 5603 name: "CMPQ", 5604 argLen: 2, 5605 asm: x86.ACMPQ, 5606 reg: regInfo{ 5607 inputs: []inputInfo{ 5608 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5609 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5610 }, 5611 }, 5612 }, 5613 { 5614 name: "CMPL", 5615 argLen: 2, 5616 asm: x86.ACMPL, 5617 reg: regInfo{ 5618 inputs: []inputInfo{ 5619 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5620 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5621 }, 5622 }, 5623 }, 5624 { 5625 name: "CMPW", 5626 argLen: 2, 5627 asm: x86.ACMPW, 5628 reg: regInfo{ 5629 inputs: []inputInfo{ 5630 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5631 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5632 }, 5633 }, 5634 }, 5635 { 5636 name: "CMPB", 5637 argLen: 2, 5638 asm: x86.ACMPB, 5639 reg: regInfo{ 5640 inputs: []inputInfo{ 5641 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5642 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5643 }, 5644 }, 5645 }, 5646 { 5647 name: "CMPQconst", 5648 auxType: auxInt32, 5649 argLen: 1, 5650 asm: x86.ACMPQ, 5651 reg: regInfo{ 5652 inputs: []inputInfo{ 5653 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5654 }, 5655 }, 5656 }, 5657 { 5658 name: "CMPLconst", 5659 auxType: auxInt32, 5660 argLen: 1, 5661 asm: x86.ACMPL, 5662 reg: regInfo{ 5663 inputs: []inputInfo{ 5664 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5665 }, 5666 }, 5667 }, 5668 { 5669 name: "CMPWconst", 5670 auxType: auxInt16, 5671 argLen: 1, 5672 asm: x86.ACMPW, 5673 reg: regInfo{ 5674 inputs: []inputInfo{ 5675 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5676 }, 5677 }, 5678 }, 5679 { 5680 name: "CMPBconst", 5681 auxType: auxInt8, 5682 argLen: 1, 5683 asm: x86.ACMPB, 5684 reg: regInfo{ 5685 inputs: []inputInfo{ 5686 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5687 }, 5688 }, 5689 }, 5690 { 5691 name: "UCOMISS", 5692 argLen: 2, 5693 asm: x86.AUCOMISS, 5694 reg: regInfo{ 5695 inputs: []inputInfo{ 5696 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5697 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5698 }, 5699 }, 5700 }, 5701 { 5702 name: "UCOMISD", 5703 argLen: 2, 5704 asm: x86.AUCOMISD, 5705 reg: regInfo{ 5706 inputs: []inputInfo{ 5707 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5708 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5709 }, 5710 }, 5711 }, 5712 { 5713 name: "BTL", 5714 argLen: 2, 5715 asm: x86.ABTL, 5716 reg: regInfo{ 5717 inputs: []inputInfo{ 5718 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5719 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 }, 5721 }, 5722 }, 5723 { 5724 name: "BTQ", 5725 argLen: 2, 5726 asm: x86.ABTQ, 5727 reg: regInfo{ 5728 inputs: []inputInfo{ 5729 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5730 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5731 }, 5732 }, 5733 }, 5734 { 5735 name: "BTLconst", 5736 auxType: auxInt8, 5737 argLen: 1, 5738 asm: x86.ABTL, 5739 reg: regInfo{ 5740 inputs: []inputInfo{ 5741 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5742 }, 5743 }, 5744 }, 5745 { 5746 name: "BTQconst", 5747 auxType: auxInt8, 5748 argLen: 1, 5749 asm: x86.ABTQ, 5750 reg: regInfo{ 5751 inputs: []inputInfo{ 5752 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5753 }, 5754 }, 5755 }, 5756 { 5757 name: "TESTQ", 5758 argLen: 2, 5759 commutative: true, 5760 asm: x86.ATESTQ, 5761 reg: regInfo{ 5762 inputs: []inputInfo{ 5763 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5764 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5765 }, 5766 }, 5767 }, 5768 { 5769 name: "TESTL", 5770 argLen: 2, 5771 commutative: true, 5772 asm: x86.ATESTL, 5773 reg: regInfo{ 5774 inputs: []inputInfo{ 5775 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5776 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5777 }, 5778 }, 5779 }, 5780 { 5781 name: "TESTW", 5782 argLen: 2, 5783 commutative: true, 5784 asm: x86.ATESTW, 5785 reg: regInfo{ 5786 inputs: []inputInfo{ 5787 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5788 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5789 }, 5790 }, 5791 }, 5792 { 5793 name: "TESTB", 5794 argLen: 2, 5795 commutative: true, 5796 asm: x86.ATESTB, 5797 reg: regInfo{ 5798 inputs: []inputInfo{ 5799 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5800 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5801 }, 5802 }, 5803 }, 5804 { 5805 name: "TESTQconst", 5806 auxType: auxInt32, 5807 argLen: 1, 5808 asm: x86.ATESTQ, 5809 reg: regInfo{ 5810 inputs: []inputInfo{ 5811 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5812 }, 5813 }, 5814 }, 5815 { 5816 name: "TESTLconst", 5817 auxType: auxInt32, 5818 argLen: 1, 5819 asm: x86.ATESTL, 5820 reg: regInfo{ 5821 inputs: []inputInfo{ 5822 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5823 }, 5824 }, 5825 }, 5826 { 5827 name: "TESTWconst", 5828 auxType: auxInt16, 5829 argLen: 1, 5830 asm: x86.ATESTW, 5831 reg: regInfo{ 5832 inputs: []inputInfo{ 5833 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5834 }, 5835 }, 5836 }, 5837 { 5838 name: "TESTBconst", 5839 auxType: auxInt8, 5840 argLen: 1, 5841 asm: x86.ATESTB, 5842 reg: regInfo{ 5843 inputs: []inputInfo{ 5844 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5845 }, 5846 }, 5847 }, 5848 { 5849 name: "SHLQ", 5850 argLen: 2, 5851 resultInArg0: true, 5852 clobberFlags: true, 5853 asm: x86.ASHLQ, 5854 reg: regInfo{ 5855 inputs: []inputInfo{ 5856 {1, 2}, // CX 5857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5858 }, 5859 outputs: []outputInfo{ 5860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5861 }, 5862 }, 5863 }, 5864 { 5865 name: "SHLL", 5866 argLen: 2, 5867 resultInArg0: true, 5868 clobberFlags: true, 5869 asm: x86.ASHLL, 5870 reg: regInfo{ 5871 inputs: []inputInfo{ 5872 {1, 2}, // CX 5873 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5874 }, 5875 outputs: []outputInfo{ 5876 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5877 }, 5878 }, 5879 }, 5880 { 5881 name: "SHLQconst", 5882 auxType: auxInt8, 5883 argLen: 1, 5884 resultInArg0: true, 5885 clobberFlags: true, 5886 asm: x86.ASHLQ, 5887 reg: regInfo{ 5888 inputs: []inputInfo{ 5889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5890 }, 5891 outputs: []outputInfo{ 5892 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5893 }, 5894 }, 5895 }, 5896 { 5897 name: "SHLLconst", 5898 auxType: auxInt8, 5899 argLen: 1, 5900 resultInArg0: true, 5901 clobberFlags: true, 5902 asm: x86.ASHLL, 5903 reg: regInfo{ 5904 inputs: []inputInfo{ 5905 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5906 }, 5907 outputs: []outputInfo{ 5908 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5909 }, 5910 }, 5911 }, 5912 { 5913 name: "SHRQ", 5914 argLen: 2, 5915 resultInArg0: true, 5916 clobberFlags: true, 5917 asm: x86.ASHRQ, 5918 reg: regInfo{ 5919 inputs: []inputInfo{ 5920 {1, 2}, // CX 5921 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5922 }, 5923 outputs: []outputInfo{ 5924 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5925 }, 5926 }, 5927 }, 5928 { 5929 name: "SHRL", 5930 argLen: 2, 5931 resultInArg0: true, 5932 clobberFlags: true, 5933 asm: x86.ASHRL, 5934 reg: regInfo{ 5935 inputs: []inputInfo{ 5936 {1, 2}, // CX 5937 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5938 }, 5939 outputs: []outputInfo{ 5940 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5941 }, 5942 }, 5943 }, 5944 { 5945 name: "SHRW", 5946 argLen: 2, 5947 resultInArg0: true, 5948 clobberFlags: true, 5949 asm: x86.ASHRW, 5950 reg: regInfo{ 5951 inputs: []inputInfo{ 5952 {1, 2}, // CX 5953 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5954 }, 5955 outputs: []outputInfo{ 5956 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5957 }, 5958 }, 5959 }, 5960 { 5961 name: "SHRB", 5962 argLen: 2, 5963 resultInArg0: true, 5964 clobberFlags: true, 5965 asm: x86.ASHRB, 5966 reg: regInfo{ 5967 inputs: []inputInfo{ 5968 {1, 2}, // CX 5969 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5970 }, 5971 outputs: []outputInfo{ 5972 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5973 }, 5974 }, 5975 }, 5976 { 5977 name: "SHRQconst", 5978 auxType: auxInt8, 5979 argLen: 1, 5980 resultInArg0: true, 5981 clobberFlags: true, 5982 asm: x86.ASHRQ, 5983 reg: regInfo{ 5984 inputs: []inputInfo{ 5985 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5986 }, 5987 outputs: []outputInfo{ 5988 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5989 }, 5990 }, 5991 }, 5992 { 5993 name: "SHRLconst", 5994 auxType: auxInt8, 5995 argLen: 1, 5996 resultInArg0: true, 5997 clobberFlags: true, 5998 asm: x86.ASHRL, 5999 reg: regInfo{ 6000 inputs: []inputInfo{ 6001 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6002 }, 6003 outputs: []outputInfo{ 6004 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6005 }, 6006 }, 6007 }, 6008 { 6009 name: "SHRWconst", 6010 auxType: auxInt8, 6011 argLen: 1, 6012 resultInArg0: true, 6013 clobberFlags: true, 6014 asm: x86.ASHRW, 6015 reg: regInfo{ 6016 inputs: []inputInfo{ 6017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6018 }, 6019 outputs: []outputInfo{ 6020 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6021 }, 6022 }, 6023 }, 6024 { 6025 name: "SHRBconst", 6026 auxType: auxInt8, 6027 argLen: 1, 6028 resultInArg0: true, 6029 clobberFlags: true, 6030 asm: x86.ASHRB, 6031 reg: regInfo{ 6032 inputs: []inputInfo{ 6033 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6034 }, 6035 outputs: []outputInfo{ 6036 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6037 }, 6038 }, 6039 }, 6040 { 6041 name: "SARQ", 6042 argLen: 2, 6043 resultInArg0: true, 6044 clobberFlags: true, 6045 asm: x86.ASARQ, 6046 reg: regInfo{ 6047 inputs: []inputInfo{ 6048 {1, 2}, // CX 6049 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6050 }, 6051 outputs: []outputInfo{ 6052 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6053 }, 6054 }, 6055 }, 6056 { 6057 name: "SARL", 6058 argLen: 2, 6059 resultInArg0: true, 6060 clobberFlags: true, 6061 asm: x86.ASARL, 6062 reg: regInfo{ 6063 inputs: []inputInfo{ 6064 {1, 2}, // CX 6065 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6066 }, 6067 outputs: []outputInfo{ 6068 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6069 }, 6070 }, 6071 }, 6072 { 6073 name: "SARW", 6074 argLen: 2, 6075 resultInArg0: true, 6076 clobberFlags: true, 6077 asm: x86.ASARW, 6078 reg: regInfo{ 6079 inputs: []inputInfo{ 6080 {1, 2}, // CX 6081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6082 }, 6083 outputs: []outputInfo{ 6084 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6085 }, 6086 }, 6087 }, 6088 { 6089 name: "SARB", 6090 argLen: 2, 6091 resultInArg0: true, 6092 clobberFlags: true, 6093 asm: x86.ASARB, 6094 reg: regInfo{ 6095 inputs: []inputInfo{ 6096 {1, 2}, // CX 6097 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6098 }, 6099 outputs: []outputInfo{ 6100 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6101 }, 6102 }, 6103 }, 6104 { 6105 name: "SARQconst", 6106 auxType: auxInt8, 6107 argLen: 1, 6108 resultInArg0: true, 6109 clobberFlags: true, 6110 asm: x86.ASARQ, 6111 reg: regInfo{ 6112 inputs: []inputInfo{ 6113 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6114 }, 6115 outputs: []outputInfo{ 6116 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6117 }, 6118 }, 6119 }, 6120 { 6121 name: "SARLconst", 6122 auxType: auxInt8, 6123 argLen: 1, 6124 resultInArg0: true, 6125 clobberFlags: true, 6126 asm: x86.ASARL, 6127 reg: regInfo{ 6128 inputs: []inputInfo{ 6129 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6130 }, 6131 outputs: []outputInfo{ 6132 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6133 }, 6134 }, 6135 }, 6136 { 6137 name: "SARWconst", 6138 auxType: auxInt8, 6139 argLen: 1, 6140 resultInArg0: true, 6141 clobberFlags: true, 6142 asm: x86.ASARW, 6143 reg: regInfo{ 6144 inputs: []inputInfo{ 6145 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6146 }, 6147 outputs: []outputInfo{ 6148 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6149 }, 6150 }, 6151 }, 6152 { 6153 name: "SARBconst", 6154 auxType: auxInt8, 6155 argLen: 1, 6156 resultInArg0: true, 6157 clobberFlags: true, 6158 asm: x86.ASARB, 6159 reg: regInfo{ 6160 inputs: []inputInfo{ 6161 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6162 }, 6163 outputs: []outputInfo{ 6164 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6165 }, 6166 }, 6167 }, 6168 { 6169 name: "ROLQ", 6170 argLen: 2, 6171 resultInArg0: true, 6172 clobberFlags: true, 6173 asm: x86.AROLQ, 6174 reg: regInfo{ 6175 inputs: []inputInfo{ 6176 {1, 2}, // CX 6177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6178 }, 6179 outputs: []outputInfo{ 6180 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6181 }, 6182 }, 6183 }, 6184 { 6185 name: "ROLL", 6186 argLen: 2, 6187 resultInArg0: true, 6188 clobberFlags: true, 6189 asm: x86.AROLL, 6190 reg: regInfo{ 6191 inputs: []inputInfo{ 6192 {1, 2}, // CX 6193 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6194 }, 6195 outputs: []outputInfo{ 6196 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6197 }, 6198 }, 6199 }, 6200 { 6201 name: "ROLW", 6202 argLen: 2, 6203 resultInArg0: true, 6204 clobberFlags: true, 6205 asm: x86.AROLW, 6206 reg: regInfo{ 6207 inputs: []inputInfo{ 6208 {1, 2}, // CX 6209 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6210 }, 6211 outputs: []outputInfo{ 6212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6213 }, 6214 }, 6215 }, 6216 { 6217 name: "ROLB", 6218 argLen: 2, 6219 resultInArg0: true, 6220 clobberFlags: true, 6221 asm: x86.AROLB, 6222 reg: regInfo{ 6223 inputs: []inputInfo{ 6224 {1, 2}, // CX 6225 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6226 }, 6227 outputs: []outputInfo{ 6228 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6229 }, 6230 }, 6231 }, 6232 { 6233 name: "RORQ", 6234 argLen: 2, 6235 resultInArg0: true, 6236 clobberFlags: true, 6237 asm: x86.ARORQ, 6238 reg: regInfo{ 6239 inputs: []inputInfo{ 6240 {1, 2}, // CX 6241 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6242 }, 6243 outputs: []outputInfo{ 6244 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6245 }, 6246 }, 6247 }, 6248 { 6249 name: "RORL", 6250 argLen: 2, 6251 resultInArg0: true, 6252 clobberFlags: true, 6253 asm: x86.ARORL, 6254 reg: regInfo{ 6255 inputs: []inputInfo{ 6256 {1, 2}, // CX 6257 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6258 }, 6259 outputs: []outputInfo{ 6260 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6261 }, 6262 }, 6263 }, 6264 { 6265 name: "RORW", 6266 argLen: 2, 6267 resultInArg0: true, 6268 clobberFlags: true, 6269 asm: x86.ARORW, 6270 reg: regInfo{ 6271 inputs: []inputInfo{ 6272 {1, 2}, // CX 6273 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6274 }, 6275 outputs: []outputInfo{ 6276 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6277 }, 6278 }, 6279 }, 6280 { 6281 name: "RORB", 6282 argLen: 2, 6283 resultInArg0: true, 6284 clobberFlags: true, 6285 asm: x86.ARORB, 6286 reg: regInfo{ 6287 inputs: []inputInfo{ 6288 {1, 2}, // CX 6289 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6290 }, 6291 outputs: []outputInfo{ 6292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6293 }, 6294 }, 6295 }, 6296 { 6297 name: "ROLQconst", 6298 auxType: auxInt8, 6299 argLen: 1, 6300 resultInArg0: true, 6301 clobberFlags: true, 6302 asm: x86.AROLQ, 6303 reg: regInfo{ 6304 inputs: []inputInfo{ 6305 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6306 }, 6307 outputs: []outputInfo{ 6308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6309 }, 6310 }, 6311 }, 6312 { 6313 name: "ROLLconst", 6314 auxType: auxInt8, 6315 argLen: 1, 6316 resultInArg0: true, 6317 clobberFlags: true, 6318 asm: x86.AROLL, 6319 reg: regInfo{ 6320 inputs: []inputInfo{ 6321 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6322 }, 6323 outputs: []outputInfo{ 6324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6325 }, 6326 }, 6327 }, 6328 { 6329 name: "ROLWconst", 6330 auxType: auxInt8, 6331 argLen: 1, 6332 resultInArg0: true, 6333 clobberFlags: true, 6334 asm: x86.AROLW, 6335 reg: regInfo{ 6336 inputs: []inputInfo{ 6337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6338 }, 6339 outputs: []outputInfo{ 6340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6341 }, 6342 }, 6343 }, 6344 { 6345 name: "ROLBconst", 6346 auxType: auxInt8, 6347 argLen: 1, 6348 resultInArg0: true, 6349 clobberFlags: true, 6350 asm: x86.AROLB, 6351 reg: regInfo{ 6352 inputs: []inputInfo{ 6353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6354 }, 6355 outputs: []outputInfo{ 6356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6357 }, 6358 }, 6359 }, 6360 { 6361 name: "ADDLmem", 6362 auxType: auxSymOff, 6363 argLen: 3, 6364 resultInArg0: true, 6365 clobberFlags: true, 6366 faultOnNilArg1: true, 6367 symEffect: SymRead, 6368 asm: x86.AADDL, 6369 reg: regInfo{ 6370 inputs: []inputInfo{ 6371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6372 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6373 }, 6374 outputs: []outputInfo{ 6375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6376 }, 6377 }, 6378 }, 6379 { 6380 name: "ADDQmem", 6381 auxType: auxSymOff, 6382 argLen: 3, 6383 resultInArg0: true, 6384 clobberFlags: true, 6385 faultOnNilArg1: true, 6386 symEffect: SymRead, 6387 asm: x86.AADDQ, 6388 reg: regInfo{ 6389 inputs: []inputInfo{ 6390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6391 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6392 }, 6393 outputs: []outputInfo{ 6394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6395 }, 6396 }, 6397 }, 6398 { 6399 name: "SUBQmem", 6400 auxType: auxSymOff, 6401 argLen: 3, 6402 resultInArg0: true, 6403 clobberFlags: true, 6404 faultOnNilArg1: true, 6405 symEffect: SymRead, 6406 asm: x86.ASUBQ, 6407 reg: regInfo{ 6408 inputs: []inputInfo{ 6409 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6410 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6411 }, 6412 outputs: []outputInfo{ 6413 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6414 }, 6415 }, 6416 }, 6417 { 6418 name: "SUBLmem", 6419 auxType: auxSymOff, 6420 argLen: 3, 6421 resultInArg0: true, 6422 clobberFlags: true, 6423 faultOnNilArg1: true, 6424 symEffect: SymRead, 6425 asm: x86.ASUBL, 6426 reg: regInfo{ 6427 inputs: []inputInfo{ 6428 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6429 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6430 }, 6431 outputs: []outputInfo{ 6432 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6433 }, 6434 }, 6435 }, 6436 { 6437 name: "ANDLmem", 6438 auxType: auxSymOff, 6439 argLen: 3, 6440 resultInArg0: true, 6441 clobberFlags: true, 6442 faultOnNilArg1: true, 6443 symEffect: SymRead, 6444 asm: x86.AANDL, 6445 reg: regInfo{ 6446 inputs: []inputInfo{ 6447 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6448 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6449 }, 6450 outputs: []outputInfo{ 6451 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6452 }, 6453 }, 6454 }, 6455 { 6456 name: "ANDQmem", 6457 auxType: auxSymOff, 6458 argLen: 3, 6459 resultInArg0: true, 6460 clobberFlags: true, 6461 faultOnNilArg1: true, 6462 symEffect: SymRead, 6463 asm: x86.AANDQ, 6464 reg: regInfo{ 6465 inputs: []inputInfo{ 6466 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6467 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6468 }, 6469 outputs: []outputInfo{ 6470 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6471 }, 6472 }, 6473 }, 6474 { 6475 name: "ORQmem", 6476 auxType: auxSymOff, 6477 argLen: 3, 6478 resultInArg0: true, 6479 clobberFlags: true, 6480 faultOnNilArg1: true, 6481 symEffect: SymRead, 6482 asm: x86.AORQ, 6483 reg: regInfo{ 6484 inputs: []inputInfo{ 6485 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6486 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6487 }, 6488 outputs: []outputInfo{ 6489 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6490 }, 6491 }, 6492 }, 6493 { 6494 name: "ORLmem", 6495 auxType: auxSymOff, 6496 argLen: 3, 6497 resultInArg0: true, 6498 clobberFlags: true, 6499 faultOnNilArg1: true, 6500 symEffect: SymRead, 6501 asm: x86.AORL, 6502 reg: regInfo{ 6503 inputs: []inputInfo{ 6504 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6505 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6506 }, 6507 outputs: []outputInfo{ 6508 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6509 }, 6510 }, 6511 }, 6512 { 6513 name: "XORQmem", 6514 auxType: auxSymOff, 6515 argLen: 3, 6516 resultInArg0: true, 6517 clobberFlags: true, 6518 faultOnNilArg1: true, 6519 symEffect: SymRead, 6520 asm: x86.AXORQ, 6521 reg: regInfo{ 6522 inputs: []inputInfo{ 6523 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6524 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6525 }, 6526 outputs: []outputInfo{ 6527 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6528 }, 6529 }, 6530 }, 6531 { 6532 name: "XORLmem", 6533 auxType: auxSymOff, 6534 argLen: 3, 6535 resultInArg0: true, 6536 clobberFlags: true, 6537 faultOnNilArg1: true, 6538 symEffect: SymRead, 6539 asm: x86.AXORL, 6540 reg: regInfo{ 6541 inputs: []inputInfo{ 6542 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6543 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6544 }, 6545 outputs: []outputInfo{ 6546 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6547 }, 6548 }, 6549 }, 6550 { 6551 name: "NEGQ", 6552 argLen: 1, 6553 resultInArg0: true, 6554 clobberFlags: true, 6555 asm: x86.ANEGQ, 6556 reg: regInfo{ 6557 inputs: []inputInfo{ 6558 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6559 }, 6560 outputs: []outputInfo{ 6561 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6562 }, 6563 }, 6564 }, 6565 { 6566 name: "NEGL", 6567 argLen: 1, 6568 resultInArg0: true, 6569 clobberFlags: true, 6570 asm: x86.ANEGL, 6571 reg: regInfo{ 6572 inputs: []inputInfo{ 6573 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6574 }, 6575 outputs: []outputInfo{ 6576 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6577 }, 6578 }, 6579 }, 6580 { 6581 name: "NOTQ", 6582 argLen: 1, 6583 resultInArg0: true, 6584 clobberFlags: true, 6585 asm: x86.ANOTQ, 6586 reg: regInfo{ 6587 inputs: []inputInfo{ 6588 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6589 }, 6590 outputs: []outputInfo{ 6591 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6592 }, 6593 }, 6594 }, 6595 { 6596 name: "NOTL", 6597 argLen: 1, 6598 resultInArg0: true, 6599 clobberFlags: true, 6600 asm: x86.ANOTL, 6601 reg: regInfo{ 6602 inputs: []inputInfo{ 6603 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6604 }, 6605 outputs: []outputInfo{ 6606 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6607 }, 6608 }, 6609 }, 6610 { 6611 name: "BSFQ", 6612 argLen: 1, 6613 asm: x86.ABSFQ, 6614 reg: regInfo{ 6615 inputs: []inputInfo{ 6616 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6617 }, 6618 outputs: []outputInfo{ 6619 {1, 0}, 6620 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6621 }, 6622 }, 6623 }, 6624 { 6625 name: "BSFL", 6626 argLen: 1, 6627 asm: x86.ABSFL, 6628 reg: regInfo{ 6629 inputs: []inputInfo{ 6630 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6631 }, 6632 outputs: []outputInfo{ 6633 {1, 0}, 6634 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6635 }, 6636 }, 6637 }, 6638 { 6639 name: "BSRQ", 6640 argLen: 1, 6641 asm: x86.ABSRQ, 6642 reg: regInfo{ 6643 inputs: []inputInfo{ 6644 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6645 }, 6646 outputs: []outputInfo{ 6647 {1, 0}, 6648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6649 }, 6650 }, 6651 }, 6652 { 6653 name: "BSRL", 6654 argLen: 1, 6655 asm: x86.ABSRL, 6656 reg: regInfo{ 6657 inputs: []inputInfo{ 6658 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6659 }, 6660 outputs: []outputInfo{ 6661 {1, 0}, 6662 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6663 }, 6664 }, 6665 }, 6666 { 6667 name: "CMOVQEQ", 6668 argLen: 3, 6669 resultInArg0: true, 6670 asm: x86.ACMOVQEQ, 6671 reg: regInfo{ 6672 inputs: []inputInfo{ 6673 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6674 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6675 }, 6676 outputs: []outputInfo{ 6677 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6678 }, 6679 }, 6680 }, 6681 { 6682 name: "CMOVLEQ", 6683 argLen: 3, 6684 resultInArg0: true, 6685 asm: x86.ACMOVLEQ, 6686 reg: regInfo{ 6687 inputs: []inputInfo{ 6688 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6689 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6690 }, 6691 outputs: []outputInfo{ 6692 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6693 }, 6694 }, 6695 }, 6696 { 6697 name: "BSWAPQ", 6698 argLen: 1, 6699 resultInArg0: true, 6700 clobberFlags: true, 6701 asm: x86.ABSWAPQ, 6702 reg: regInfo{ 6703 inputs: []inputInfo{ 6704 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6705 }, 6706 outputs: []outputInfo{ 6707 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6708 }, 6709 }, 6710 }, 6711 { 6712 name: "BSWAPL", 6713 argLen: 1, 6714 resultInArg0: true, 6715 clobberFlags: true, 6716 asm: x86.ABSWAPL, 6717 reg: regInfo{ 6718 inputs: []inputInfo{ 6719 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6720 }, 6721 outputs: []outputInfo{ 6722 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6723 }, 6724 }, 6725 }, 6726 { 6727 name: "POPCNTQ", 6728 argLen: 1, 6729 clobberFlags: true, 6730 asm: x86.APOPCNTQ, 6731 reg: regInfo{ 6732 inputs: []inputInfo{ 6733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6734 }, 6735 outputs: []outputInfo{ 6736 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6737 }, 6738 }, 6739 }, 6740 { 6741 name: "POPCNTL", 6742 argLen: 1, 6743 clobberFlags: true, 6744 asm: x86.APOPCNTL, 6745 reg: regInfo{ 6746 inputs: []inputInfo{ 6747 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6748 }, 6749 outputs: []outputInfo{ 6750 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6751 }, 6752 }, 6753 }, 6754 { 6755 name: "SQRTSD", 6756 argLen: 1, 6757 asm: x86.ASQRTSD, 6758 reg: regInfo{ 6759 inputs: []inputInfo{ 6760 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6761 }, 6762 outputs: []outputInfo{ 6763 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6764 }, 6765 }, 6766 }, 6767 { 6768 name: "ROUNDSD", 6769 auxType: auxInt8, 6770 argLen: 1, 6771 asm: x86.AROUNDSD, 6772 reg: regInfo{ 6773 inputs: []inputInfo{ 6774 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6775 }, 6776 outputs: []outputInfo{ 6777 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6778 }, 6779 }, 6780 }, 6781 { 6782 name: "SBBQcarrymask", 6783 argLen: 1, 6784 asm: x86.ASBBQ, 6785 reg: regInfo{ 6786 outputs: []outputInfo{ 6787 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6788 }, 6789 }, 6790 }, 6791 { 6792 name: "SBBLcarrymask", 6793 argLen: 1, 6794 asm: x86.ASBBL, 6795 reg: regInfo{ 6796 outputs: []outputInfo{ 6797 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6798 }, 6799 }, 6800 }, 6801 { 6802 name: "SETEQ", 6803 argLen: 1, 6804 asm: x86.ASETEQ, 6805 reg: regInfo{ 6806 outputs: []outputInfo{ 6807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6808 }, 6809 }, 6810 }, 6811 { 6812 name: "SETNE", 6813 argLen: 1, 6814 asm: x86.ASETNE, 6815 reg: regInfo{ 6816 outputs: []outputInfo{ 6817 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6818 }, 6819 }, 6820 }, 6821 { 6822 name: "SETL", 6823 argLen: 1, 6824 asm: x86.ASETLT, 6825 reg: regInfo{ 6826 outputs: []outputInfo{ 6827 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6828 }, 6829 }, 6830 }, 6831 { 6832 name: "SETLE", 6833 argLen: 1, 6834 asm: x86.ASETLE, 6835 reg: regInfo{ 6836 outputs: []outputInfo{ 6837 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6838 }, 6839 }, 6840 }, 6841 { 6842 name: "SETG", 6843 argLen: 1, 6844 asm: x86.ASETGT, 6845 reg: regInfo{ 6846 outputs: []outputInfo{ 6847 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6848 }, 6849 }, 6850 }, 6851 { 6852 name: "SETGE", 6853 argLen: 1, 6854 asm: x86.ASETGE, 6855 reg: regInfo{ 6856 outputs: []outputInfo{ 6857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6858 }, 6859 }, 6860 }, 6861 { 6862 name: "SETB", 6863 argLen: 1, 6864 asm: x86.ASETCS, 6865 reg: regInfo{ 6866 outputs: []outputInfo{ 6867 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6868 }, 6869 }, 6870 }, 6871 { 6872 name: "SETBE", 6873 argLen: 1, 6874 asm: x86.ASETLS, 6875 reg: regInfo{ 6876 outputs: []outputInfo{ 6877 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6878 }, 6879 }, 6880 }, 6881 { 6882 name: "SETA", 6883 argLen: 1, 6884 asm: x86.ASETHI, 6885 reg: regInfo{ 6886 outputs: []outputInfo{ 6887 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6888 }, 6889 }, 6890 }, 6891 { 6892 name: "SETAE", 6893 argLen: 1, 6894 asm: x86.ASETCC, 6895 reg: regInfo{ 6896 outputs: []outputInfo{ 6897 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6898 }, 6899 }, 6900 }, 6901 { 6902 name: "SETEQmem", 6903 auxType: auxSymOff, 6904 argLen: 3, 6905 faultOnNilArg0: true, 6906 symEffect: SymWrite, 6907 asm: x86.ASETEQ, 6908 reg: regInfo{ 6909 inputs: []inputInfo{ 6910 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6911 }, 6912 }, 6913 }, 6914 { 6915 name: "SETNEmem", 6916 auxType: auxSymOff, 6917 argLen: 3, 6918 faultOnNilArg0: true, 6919 symEffect: SymWrite, 6920 asm: x86.ASETNE, 6921 reg: regInfo{ 6922 inputs: []inputInfo{ 6923 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6924 }, 6925 }, 6926 }, 6927 { 6928 name: "SETLmem", 6929 auxType: auxSymOff, 6930 argLen: 3, 6931 faultOnNilArg0: true, 6932 symEffect: SymWrite, 6933 asm: x86.ASETLT, 6934 reg: regInfo{ 6935 inputs: []inputInfo{ 6936 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6937 }, 6938 }, 6939 }, 6940 { 6941 name: "SETLEmem", 6942 auxType: auxSymOff, 6943 argLen: 3, 6944 faultOnNilArg0: true, 6945 symEffect: SymWrite, 6946 asm: x86.ASETLE, 6947 reg: regInfo{ 6948 inputs: []inputInfo{ 6949 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6950 }, 6951 }, 6952 }, 6953 { 6954 name: "SETGmem", 6955 auxType: auxSymOff, 6956 argLen: 3, 6957 faultOnNilArg0: true, 6958 symEffect: SymWrite, 6959 asm: x86.ASETGT, 6960 reg: regInfo{ 6961 inputs: []inputInfo{ 6962 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6963 }, 6964 }, 6965 }, 6966 { 6967 name: "SETGEmem", 6968 auxType: auxSymOff, 6969 argLen: 3, 6970 faultOnNilArg0: true, 6971 symEffect: SymWrite, 6972 asm: x86.ASETGE, 6973 reg: regInfo{ 6974 inputs: []inputInfo{ 6975 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6976 }, 6977 }, 6978 }, 6979 { 6980 name: "SETBmem", 6981 auxType: auxSymOff, 6982 argLen: 3, 6983 faultOnNilArg0: true, 6984 symEffect: SymWrite, 6985 asm: x86.ASETCS, 6986 reg: regInfo{ 6987 inputs: []inputInfo{ 6988 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6989 }, 6990 }, 6991 }, 6992 { 6993 name: "SETBEmem", 6994 auxType: auxSymOff, 6995 argLen: 3, 6996 faultOnNilArg0: true, 6997 symEffect: SymWrite, 6998 asm: x86.ASETLS, 6999 reg: regInfo{ 7000 inputs: []inputInfo{ 7001 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7002 }, 7003 }, 7004 }, 7005 { 7006 name: "SETAmem", 7007 auxType: auxSymOff, 7008 argLen: 3, 7009 faultOnNilArg0: true, 7010 symEffect: SymWrite, 7011 asm: x86.ASETHI, 7012 reg: regInfo{ 7013 inputs: []inputInfo{ 7014 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7015 }, 7016 }, 7017 }, 7018 { 7019 name: "SETAEmem", 7020 auxType: auxSymOff, 7021 argLen: 3, 7022 faultOnNilArg0: true, 7023 symEffect: SymWrite, 7024 asm: x86.ASETCC, 7025 reg: regInfo{ 7026 inputs: []inputInfo{ 7027 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7028 }, 7029 }, 7030 }, 7031 { 7032 name: "SETEQF", 7033 argLen: 1, 7034 clobberFlags: true, 7035 asm: x86.ASETEQ, 7036 reg: regInfo{ 7037 clobbers: 1, // AX 7038 outputs: []outputInfo{ 7039 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7040 }, 7041 }, 7042 }, 7043 { 7044 name: "SETNEF", 7045 argLen: 1, 7046 clobberFlags: true, 7047 asm: x86.ASETNE, 7048 reg: regInfo{ 7049 clobbers: 1, // AX 7050 outputs: []outputInfo{ 7051 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7052 }, 7053 }, 7054 }, 7055 { 7056 name: "SETORD", 7057 argLen: 1, 7058 asm: x86.ASETPC, 7059 reg: regInfo{ 7060 outputs: []outputInfo{ 7061 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7062 }, 7063 }, 7064 }, 7065 { 7066 name: "SETNAN", 7067 argLen: 1, 7068 asm: x86.ASETPS, 7069 reg: regInfo{ 7070 outputs: []outputInfo{ 7071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7072 }, 7073 }, 7074 }, 7075 { 7076 name: "SETGF", 7077 argLen: 1, 7078 asm: x86.ASETHI, 7079 reg: regInfo{ 7080 outputs: []outputInfo{ 7081 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7082 }, 7083 }, 7084 }, 7085 { 7086 name: "SETGEF", 7087 argLen: 1, 7088 asm: x86.ASETCC, 7089 reg: regInfo{ 7090 outputs: []outputInfo{ 7091 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7092 }, 7093 }, 7094 }, 7095 { 7096 name: "MOVBQSX", 7097 argLen: 1, 7098 asm: x86.AMOVBQSX, 7099 reg: regInfo{ 7100 inputs: []inputInfo{ 7101 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7102 }, 7103 outputs: []outputInfo{ 7104 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7105 }, 7106 }, 7107 }, 7108 { 7109 name: "MOVBQZX", 7110 argLen: 1, 7111 asm: x86.AMOVBLZX, 7112 reg: regInfo{ 7113 inputs: []inputInfo{ 7114 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7115 }, 7116 outputs: []outputInfo{ 7117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7118 }, 7119 }, 7120 }, 7121 { 7122 name: "MOVWQSX", 7123 argLen: 1, 7124 asm: x86.AMOVWQSX, 7125 reg: regInfo{ 7126 inputs: []inputInfo{ 7127 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7128 }, 7129 outputs: []outputInfo{ 7130 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7131 }, 7132 }, 7133 }, 7134 { 7135 name: "MOVWQZX", 7136 argLen: 1, 7137 asm: x86.AMOVWLZX, 7138 reg: regInfo{ 7139 inputs: []inputInfo{ 7140 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7141 }, 7142 outputs: []outputInfo{ 7143 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7144 }, 7145 }, 7146 }, 7147 { 7148 name: "MOVLQSX", 7149 argLen: 1, 7150 asm: x86.AMOVLQSX, 7151 reg: regInfo{ 7152 inputs: []inputInfo{ 7153 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7154 }, 7155 outputs: []outputInfo{ 7156 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7157 }, 7158 }, 7159 }, 7160 { 7161 name: "MOVLQZX", 7162 argLen: 1, 7163 asm: x86.AMOVL, 7164 reg: regInfo{ 7165 inputs: []inputInfo{ 7166 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7167 }, 7168 outputs: []outputInfo{ 7169 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7170 }, 7171 }, 7172 }, 7173 { 7174 name: "MOVLconst", 7175 auxType: auxInt32, 7176 argLen: 0, 7177 rematerializeable: true, 7178 asm: x86.AMOVL, 7179 reg: regInfo{ 7180 outputs: []outputInfo{ 7181 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7182 }, 7183 }, 7184 }, 7185 { 7186 name: "MOVQconst", 7187 auxType: auxInt64, 7188 argLen: 0, 7189 rematerializeable: true, 7190 asm: x86.AMOVQ, 7191 reg: regInfo{ 7192 outputs: []outputInfo{ 7193 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7194 }, 7195 }, 7196 }, 7197 { 7198 name: "CVTTSD2SL", 7199 argLen: 1, 7200 asm: x86.ACVTTSD2SL, 7201 reg: regInfo{ 7202 inputs: []inputInfo{ 7203 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7204 }, 7205 outputs: []outputInfo{ 7206 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7207 }, 7208 }, 7209 }, 7210 { 7211 name: "CVTTSD2SQ", 7212 argLen: 1, 7213 asm: x86.ACVTTSD2SQ, 7214 reg: regInfo{ 7215 inputs: []inputInfo{ 7216 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7217 }, 7218 outputs: []outputInfo{ 7219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7220 }, 7221 }, 7222 }, 7223 { 7224 name: "CVTTSS2SL", 7225 argLen: 1, 7226 asm: x86.ACVTTSS2SL, 7227 reg: regInfo{ 7228 inputs: []inputInfo{ 7229 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7230 }, 7231 outputs: []outputInfo{ 7232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7233 }, 7234 }, 7235 }, 7236 { 7237 name: "CVTTSS2SQ", 7238 argLen: 1, 7239 asm: x86.ACVTTSS2SQ, 7240 reg: regInfo{ 7241 inputs: []inputInfo{ 7242 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7243 }, 7244 outputs: []outputInfo{ 7245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7246 }, 7247 }, 7248 }, 7249 { 7250 name: "CVTSL2SS", 7251 argLen: 1, 7252 asm: x86.ACVTSL2SS, 7253 reg: regInfo{ 7254 inputs: []inputInfo{ 7255 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7256 }, 7257 outputs: []outputInfo{ 7258 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7259 }, 7260 }, 7261 }, 7262 { 7263 name: "CVTSL2SD", 7264 argLen: 1, 7265 asm: x86.ACVTSL2SD, 7266 reg: regInfo{ 7267 inputs: []inputInfo{ 7268 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7269 }, 7270 outputs: []outputInfo{ 7271 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7272 }, 7273 }, 7274 }, 7275 { 7276 name: "CVTSQ2SS", 7277 argLen: 1, 7278 asm: x86.ACVTSQ2SS, 7279 reg: regInfo{ 7280 inputs: []inputInfo{ 7281 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7282 }, 7283 outputs: []outputInfo{ 7284 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7285 }, 7286 }, 7287 }, 7288 { 7289 name: "CVTSQ2SD", 7290 argLen: 1, 7291 asm: x86.ACVTSQ2SD, 7292 reg: regInfo{ 7293 inputs: []inputInfo{ 7294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7295 }, 7296 outputs: []outputInfo{ 7297 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7298 }, 7299 }, 7300 }, 7301 { 7302 name: "CVTSD2SS", 7303 argLen: 1, 7304 asm: x86.ACVTSD2SS, 7305 reg: regInfo{ 7306 inputs: []inputInfo{ 7307 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7308 }, 7309 outputs: []outputInfo{ 7310 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7311 }, 7312 }, 7313 }, 7314 { 7315 name: "CVTSS2SD", 7316 argLen: 1, 7317 asm: x86.ACVTSS2SD, 7318 reg: regInfo{ 7319 inputs: []inputInfo{ 7320 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7321 }, 7322 outputs: []outputInfo{ 7323 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7324 }, 7325 }, 7326 }, 7327 { 7328 name: "MOVQi2f", 7329 argLen: 1, 7330 reg: regInfo{ 7331 inputs: []inputInfo{ 7332 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7333 }, 7334 outputs: []outputInfo{ 7335 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7336 }, 7337 }, 7338 }, 7339 { 7340 name: "MOVQf2i", 7341 argLen: 1, 7342 reg: regInfo{ 7343 inputs: []inputInfo{ 7344 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7345 }, 7346 outputs: []outputInfo{ 7347 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7348 }, 7349 }, 7350 }, 7351 { 7352 name: "MOVLi2f", 7353 argLen: 1, 7354 reg: regInfo{ 7355 inputs: []inputInfo{ 7356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7357 }, 7358 outputs: []outputInfo{ 7359 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7360 }, 7361 }, 7362 }, 7363 { 7364 name: "MOVLf2i", 7365 argLen: 1, 7366 reg: regInfo{ 7367 inputs: []inputInfo{ 7368 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7369 }, 7370 outputs: []outputInfo{ 7371 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7372 }, 7373 }, 7374 }, 7375 { 7376 name: "PXOR", 7377 argLen: 2, 7378 commutative: true, 7379 resultInArg0: true, 7380 asm: x86.APXOR, 7381 reg: regInfo{ 7382 inputs: []inputInfo{ 7383 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7384 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7385 }, 7386 outputs: []outputInfo{ 7387 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7388 }, 7389 }, 7390 }, 7391 { 7392 name: "LEAQ", 7393 auxType: auxSymOff, 7394 argLen: 1, 7395 rematerializeable: true, 7396 symEffect: SymAddr, 7397 asm: x86.ALEAQ, 7398 reg: regInfo{ 7399 inputs: []inputInfo{ 7400 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7401 }, 7402 outputs: []outputInfo{ 7403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7404 }, 7405 }, 7406 }, 7407 { 7408 name: "LEAQ1", 7409 auxType: auxSymOff, 7410 argLen: 2, 7411 commutative: true, 7412 symEffect: SymAddr, 7413 reg: regInfo{ 7414 inputs: []inputInfo{ 7415 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7416 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7417 }, 7418 outputs: []outputInfo{ 7419 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7420 }, 7421 }, 7422 }, 7423 { 7424 name: "LEAQ2", 7425 auxType: auxSymOff, 7426 argLen: 2, 7427 symEffect: SymAddr, 7428 reg: regInfo{ 7429 inputs: []inputInfo{ 7430 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7431 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7432 }, 7433 outputs: []outputInfo{ 7434 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7435 }, 7436 }, 7437 }, 7438 { 7439 name: "LEAQ4", 7440 auxType: auxSymOff, 7441 argLen: 2, 7442 symEffect: SymAddr, 7443 reg: regInfo{ 7444 inputs: []inputInfo{ 7445 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7446 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7447 }, 7448 outputs: []outputInfo{ 7449 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7450 }, 7451 }, 7452 }, 7453 { 7454 name: "LEAQ8", 7455 auxType: auxSymOff, 7456 argLen: 2, 7457 symEffect: SymAddr, 7458 reg: regInfo{ 7459 inputs: []inputInfo{ 7460 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7461 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7462 }, 7463 outputs: []outputInfo{ 7464 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7465 }, 7466 }, 7467 }, 7468 { 7469 name: "LEAL", 7470 auxType: auxSymOff, 7471 argLen: 1, 7472 rematerializeable: true, 7473 symEffect: SymAddr, 7474 asm: x86.ALEAL, 7475 reg: regInfo{ 7476 inputs: []inputInfo{ 7477 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7478 }, 7479 outputs: []outputInfo{ 7480 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7481 }, 7482 }, 7483 }, 7484 { 7485 name: "MOVBload", 7486 auxType: auxSymOff, 7487 argLen: 2, 7488 faultOnNilArg0: true, 7489 symEffect: SymRead, 7490 asm: x86.AMOVBLZX, 7491 reg: regInfo{ 7492 inputs: []inputInfo{ 7493 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7494 }, 7495 outputs: []outputInfo{ 7496 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7497 }, 7498 }, 7499 }, 7500 { 7501 name: "MOVBQSXload", 7502 auxType: auxSymOff, 7503 argLen: 2, 7504 faultOnNilArg0: true, 7505 symEffect: SymRead, 7506 asm: x86.AMOVBQSX, 7507 reg: regInfo{ 7508 inputs: []inputInfo{ 7509 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7510 }, 7511 outputs: []outputInfo{ 7512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7513 }, 7514 }, 7515 }, 7516 { 7517 name: "MOVWload", 7518 auxType: auxSymOff, 7519 argLen: 2, 7520 faultOnNilArg0: true, 7521 symEffect: SymRead, 7522 asm: x86.AMOVWLZX, 7523 reg: regInfo{ 7524 inputs: []inputInfo{ 7525 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7526 }, 7527 outputs: []outputInfo{ 7528 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7529 }, 7530 }, 7531 }, 7532 { 7533 name: "MOVWQSXload", 7534 auxType: auxSymOff, 7535 argLen: 2, 7536 faultOnNilArg0: true, 7537 symEffect: SymRead, 7538 asm: x86.AMOVWQSX, 7539 reg: regInfo{ 7540 inputs: []inputInfo{ 7541 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7542 }, 7543 outputs: []outputInfo{ 7544 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7545 }, 7546 }, 7547 }, 7548 { 7549 name: "MOVLload", 7550 auxType: auxSymOff, 7551 argLen: 2, 7552 faultOnNilArg0: true, 7553 symEffect: SymRead, 7554 asm: x86.AMOVL, 7555 reg: regInfo{ 7556 inputs: []inputInfo{ 7557 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7558 }, 7559 outputs: []outputInfo{ 7560 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7561 }, 7562 }, 7563 }, 7564 { 7565 name: "MOVLQSXload", 7566 auxType: auxSymOff, 7567 argLen: 2, 7568 faultOnNilArg0: true, 7569 symEffect: SymRead, 7570 asm: x86.AMOVLQSX, 7571 reg: regInfo{ 7572 inputs: []inputInfo{ 7573 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7574 }, 7575 outputs: []outputInfo{ 7576 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7577 }, 7578 }, 7579 }, 7580 { 7581 name: "MOVQload", 7582 auxType: auxSymOff, 7583 argLen: 2, 7584 faultOnNilArg0: true, 7585 symEffect: SymRead, 7586 asm: x86.AMOVQ, 7587 reg: regInfo{ 7588 inputs: []inputInfo{ 7589 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7590 }, 7591 outputs: []outputInfo{ 7592 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7593 }, 7594 }, 7595 }, 7596 { 7597 name: "MOVBstore", 7598 auxType: auxSymOff, 7599 argLen: 3, 7600 faultOnNilArg0: true, 7601 symEffect: SymWrite, 7602 asm: x86.AMOVB, 7603 reg: regInfo{ 7604 inputs: []inputInfo{ 7605 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7606 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7607 }, 7608 }, 7609 }, 7610 { 7611 name: "MOVWstore", 7612 auxType: auxSymOff, 7613 argLen: 3, 7614 faultOnNilArg0: true, 7615 symEffect: SymWrite, 7616 asm: x86.AMOVW, 7617 reg: regInfo{ 7618 inputs: []inputInfo{ 7619 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7620 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7621 }, 7622 }, 7623 }, 7624 { 7625 name: "MOVLstore", 7626 auxType: auxSymOff, 7627 argLen: 3, 7628 faultOnNilArg0: true, 7629 symEffect: SymWrite, 7630 asm: x86.AMOVL, 7631 reg: regInfo{ 7632 inputs: []inputInfo{ 7633 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7634 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7635 }, 7636 }, 7637 }, 7638 { 7639 name: "MOVQstore", 7640 auxType: auxSymOff, 7641 argLen: 3, 7642 faultOnNilArg0: true, 7643 symEffect: SymWrite, 7644 asm: x86.AMOVQ, 7645 reg: regInfo{ 7646 inputs: []inputInfo{ 7647 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7648 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7649 }, 7650 }, 7651 }, 7652 { 7653 name: "MOVOload", 7654 auxType: auxSymOff, 7655 argLen: 2, 7656 faultOnNilArg0: true, 7657 symEffect: SymRead, 7658 asm: x86.AMOVUPS, 7659 reg: regInfo{ 7660 inputs: []inputInfo{ 7661 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7662 }, 7663 outputs: []outputInfo{ 7664 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7665 }, 7666 }, 7667 }, 7668 { 7669 name: "MOVOstore", 7670 auxType: auxSymOff, 7671 argLen: 3, 7672 faultOnNilArg0: true, 7673 symEffect: SymWrite, 7674 asm: x86.AMOVUPS, 7675 reg: regInfo{ 7676 inputs: []inputInfo{ 7677 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7678 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7679 }, 7680 }, 7681 }, 7682 { 7683 name: "MOVBloadidx1", 7684 auxType: auxSymOff, 7685 argLen: 3, 7686 commutative: true, 7687 symEffect: SymRead, 7688 asm: x86.AMOVBLZX, 7689 reg: regInfo{ 7690 inputs: []inputInfo{ 7691 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7692 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7693 }, 7694 outputs: []outputInfo{ 7695 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7696 }, 7697 }, 7698 }, 7699 { 7700 name: "MOVWloadidx1", 7701 auxType: auxSymOff, 7702 argLen: 3, 7703 commutative: true, 7704 symEffect: SymRead, 7705 asm: x86.AMOVWLZX, 7706 reg: regInfo{ 7707 inputs: []inputInfo{ 7708 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7709 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7710 }, 7711 outputs: []outputInfo{ 7712 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7713 }, 7714 }, 7715 }, 7716 { 7717 name: "MOVWloadidx2", 7718 auxType: auxSymOff, 7719 argLen: 3, 7720 symEffect: SymRead, 7721 asm: x86.AMOVWLZX, 7722 reg: regInfo{ 7723 inputs: []inputInfo{ 7724 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7725 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7726 }, 7727 outputs: []outputInfo{ 7728 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7729 }, 7730 }, 7731 }, 7732 { 7733 name: "MOVLloadidx1", 7734 auxType: auxSymOff, 7735 argLen: 3, 7736 commutative: true, 7737 symEffect: SymRead, 7738 asm: x86.AMOVL, 7739 reg: regInfo{ 7740 inputs: []inputInfo{ 7741 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7742 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7743 }, 7744 outputs: []outputInfo{ 7745 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7746 }, 7747 }, 7748 }, 7749 { 7750 name: "MOVLloadidx4", 7751 auxType: auxSymOff, 7752 argLen: 3, 7753 symEffect: SymRead, 7754 asm: x86.AMOVL, 7755 reg: regInfo{ 7756 inputs: []inputInfo{ 7757 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7758 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7759 }, 7760 outputs: []outputInfo{ 7761 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7762 }, 7763 }, 7764 }, 7765 { 7766 name: "MOVLloadidx8", 7767 auxType: auxSymOff, 7768 argLen: 3, 7769 symEffect: SymRead, 7770 asm: x86.AMOVL, 7771 reg: regInfo{ 7772 inputs: []inputInfo{ 7773 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7774 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7775 }, 7776 outputs: []outputInfo{ 7777 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7778 }, 7779 }, 7780 }, 7781 { 7782 name: "MOVQloadidx1", 7783 auxType: auxSymOff, 7784 argLen: 3, 7785 commutative: true, 7786 symEffect: SymRead, 7787 asm: x86.AMOVQ, 7788 reg: regInfo{ 7789 inputs: []inputInfo{ 7790 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7791 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7792 }, 7793 outputs: []outputInfo{ 7794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7795 }, 7796 }, 7797 }, 7798 { 7799 name: "MOVQloadidx8", 7800 auxType: auxSymOff, 7801 argLen: 3, 7802 symEffect: SymRead, 7803 asm: x86.AMOVQ, 7804 reg: regInfo{ 7805 inputs: []inputInfo{ 7806 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7807 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7808 }, 7809 outputs: []outputInfo{ 7810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7811 }, 7812 }, 7813 }, 7814 { 7815 name: "MOVBstoreidx1", 7816 auxType: auxSymOff, 7817 argLen: 4, 7818 symEffect: SymWrite, 7819 asm: x86.AMOVB, 7820 reg: regInfo{ 7821 inputs: []inputInfo{ 7822 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7823 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7824 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7825 }, 7826 }, 7827 }, 7828 { 7829 name: "MOVWstoreidx1", 7830 auxType: auxSymOff, 7831 argLen: 4, 7832 symEffect: SymWrite, 7833 asm: x86.AMOVW, 7834 reg: regInfo{ 7835 inputs: []inputInfo{ 7836 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7837 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7838 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7839 }, 7840 }, 7841 }, 7842 { 7843 name: "MOVWstoreidx2", 7844 auxType: auxSymOff, 7845 argLen: 4, 7846 symEffect: SymWrite, 7847 asm: x86.AMOVW, 7848 reg: regInfo{ 7849 inputs: []inputInfo{ 7850 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7851 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7852 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7853 }, 7854 }, 7855 }, 7856 { 7857 name: "MOVLstoreidx1", 7858 auxType: auxSymOff, 7859 argLen: 4, 7860 symEffect: SymWrite, 7861 asm: x86.AMOVL, 7862 reg: regInfo{ 7863 inputs: []inputInfo{ 7864 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7865 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7866 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7867 }, 7868 }, 7869 }, 7870 { 7871 name: "MOVLstoreidx4", 7872 auxType: auxSymOff, 7873 argLen: 4, 7874 symEffect: SymWrite, 7875 asm: x86.AMOVL, 7876 reg: regInfo{ 7877 inputs: []inputInfo{ 7878 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7879 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7880 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7881 }, 7882 }, 7883 }, 7884 { 7885 name: "MOVLstoreidx8", 7886 auxType: auxSymOff, 7887 argLen: 4, 7888 symEffect: SymWrite, 7889 asm: x86.AMOVL, 7890 reg: regInfo{ 7891 inputs: []inputInfo{ 7892 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7893 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7894 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7895 }, 7896 }, 7897 }, 7898 { 7899 name: "MOVQstoreidx1", 7900 auxType: auxSymOff, 7901 argLen: 4, 7902 symEffect: SymWrite, 7903 asm: x86.AMOVQ, 7904 reg: regInfo{ 7905 inputs: []inputInfo{ 7906 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7907 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7908 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7909 }, 7910 }, 7911 }, 7912 { 7913 name: "MOVQstoreidx8", 7914 auxType: auxSymOff, 7915 argLen: 4, 7916 symEffect: SymWrite, 7917 asm: x86.AMOVQ, 7918 reg: regInfo{ 7919 inputs: []inputInfo{ 7920 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7921 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7922 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7923 }, 7924 }, 7925 }, 7926 { 7927 name: "MOVBstoreconst", 7928 auxType: auxSymValAndOff, 7929 argLen: 2, 7930 faultOnNilArg0: true, 7931 symEffect: SymWrite, 7932 asm: x86.AMOVB, 7933 reg: regInfo{ 7934 inputs: []inputInfo{ 7935 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7936 }, 7937 }, 7938 }, 7939 { 7940 name: "MOVWstoreconst", 7941 auxType: auxSymValAndOff, 7942 argLen: 2, 7943 faultOnNilArg0: true, 7944 symEffect: SymWrite, 7945 asm: x86.AMOVW, 7946 reg: regInfo{ 7947 inputs: []inputInfo{ 7948 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7949 }, 7950 }, 7951 }, 7952 { 7953 name: "MOVLstoreconst", 7954 auxType: auxSymValAndOff, 7955 argLen: 2, 7956 faultOnNilArg0: true, 7957 symEffect: SymWrite, 7958 asm: x86.AMOVL, 7959 reg: regInfo{ 7960 inputs: []inputInfo{ 7961 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7962 }, 7963 }, 7964 }, 7965 { 7966 name: "MOVQstoreconst", 7967 auxType: auxSymValAndOff, 7968 argLen: 2, 7969 faultOnNilArg0: true, 7970 symEffect: SymWrite, 7971 asm: x86.AMOVQ, 7972 reg: regInfo{ 7973 inputs: []inputInfo{ 7974 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7975 }, 7976 }, 7977 }, 7978 { 7979 name: "MOVBstoreconstidx1", 7980 auxType: auxSymValAndOff, 7981 argLen: 3, 7982 symEffect: SymWrite, 7983 asm: x86.AMOVB, 7984 reg: regInfo{ 7985 inputs: []inputInfo{ 7986 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7987 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7988 }, 7989 }, 7990 }, 7991 { 7992 name: "MOVWstoreconstidx1", 7993 auxType: auxSymValAndOff, 7994 argLen: 3, 7995 symEffect: SymWrite, 7996 asm: x86.AMOVW, 7997 reg: regInfo{ 7998 inputs: []inputInfo{ 7999 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8000 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8001 }, 8002 }, 8003 }, 8004 { 8005 name: "MOVWstoreconstidx2", 8006 auxType: auxSymValAndOff, 8007 argLen: 3, 8008 symEffect: SymWrite, 8009 asm: x86.AMOVW, 8010 reg: regInfo{ 8011 inputs: []inputInfo{ 8012 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8013 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8014 }, 8015 }, 8016 }, 8017 { 8018 name: "MOVLstoreconstidx1", 8019 auxType: auxSymValAndOff, 8020 argLen: 3, 8021 symEffect: SymWrite, 8022 asm: x86.AMOVL, 8023 reg: regInfo{ 8024 inputs: []inputInfo{ 8025 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8026 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8027 }, 8028 }, 8029 }, 8030 { 8031 name: "MOVLstoreconstidx4", 8032 auxType: auxSymValAndOff, 8033 argLen: 3, 8034 symEffect: SymWrite, 8035 asm: x86.AMOVL, 8036 reg: regInfo{ 8037 inputs: []inputInfo{ 8038 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8039 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8040 }, 8041 }, 8042 }, 8043 { 8044 name: "MOVQstoreconstidx1", 8045 auxType: auxSymValAndOff, 8046 argLen: 3, 8047 symEffect: SymWrite, 8048 asm: x86.AMOVQ, 8049 reg: regInfo{ 8050 inputs: []inputInfo{ 8051 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8052 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8053 }, 8054 }, 8055 }, 8056 { 8057 name: "MOVQstoreconstidx8", 8058 auxType: auxSymValAndOff, 8059 argLen: 3, 8060 symEffect: SymWrite, 8061 asm: x86.AMOVQ, 8062 reg: regInfo{ 8063 inputs: []inputInfo{ 8064 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8065 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8066 }, 8067 }, 8068 }, 8069 { 8070 name: "DUFFZERO", 8071 auxType: auxInt64, 8072 argLen: 3, 8073 faultOnNilArg0: true, 8074 reg: regInfo{ 8075 inputs: []inputInfo{ 8076 {0, 128}, // DI 8077 {1, 65536}, // X0 8078 }, 8079 clobbers: 128, // DI 8080 }, 8081 }, 8082 { 8083 name: "MOVOconst", 8084 auxType: auxInt128, 8085 argLen: 0, 8086 rematerializeable: true, 8087 reg: regInfo{ 8088 outputs: []outputInfo{ 8089 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8090 }, 8091 }, 8092 }, 8093 { 8094 name: "REPSTOSQ", 8095 argLen: 4, 8096 faultOnNilArg0: true, 8097 reg: regInfo{ 8098 inputs: []inputInfo{ 8099 {0, 128}, // DI 8100 {1, 2}, // CX 8101 {2, 1}, // AX 8102 }, 8103 clobbers: 130, // CX DI 8104 }, 8105 }, 8106 { 8107 name: "CALLstatic", 8108 auxType: auxSymOff, 8109 argLen: 1, 8110 clobberFlags: true, 8111 call: true, 8112 symEffect: SymNone, 8113 reg: regInfo{ 8114 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8115 }, 8116 }, 8117 { 8118 name: "CALLclosure", 8119 auxType: auxInt64, 8120 argLen: 3, 8121 clobberFlags: true, 8122 call: true, 8123 reg: regInfo{ 8124 inputs: []inputInfo{ 8125 {1, 4}, // DX 8126 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8127 }, 8128 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8129 }, 8130 }, 8131 { 8132 name: "CALLinter", 8133 auxType: auxInt64, 8134 argLen: 2, 8135 clobberFlags: true, 8136 call: true, 8137 reg: regInfo{ 8138 inputs: []inputInfo{ 8139 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8140 }, 8141 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8142 }, 8143 }, 8144 { 8145 name: "DUFFCOPY", 8146 auxType: auxInt64, 8147 argLen: 3, 8148 clobberFlags: true, 8149 faultOnNilArg0: true, 8150 faultOnNilArg1: true, 8151 reg: regInfo{ 8152 inputs: []inputInfo{ 8153 {0, 128}, // DI 8154 {1, 64}, // SI 8155 }, 8156 clobbers: 65728, // SI DI X0 8157 }, 8158 }, 8159 { 8160 name: "REPMOVSQ", 8161 argLen: 4, 8162 faultOnNilArg0: true, 8163 faultOnNilArg1: true, 8164 reg: regInfo{ 8165 inputs: []inputInfo{ 8166 {0, 128}, // DI 8167 {1, 64}, // SI 8168 {2, 2}, // CX 8169 }, 8170 clobbers: 194, // CX SI DI 8171 }, 8172 }, 8173 { 8174 name: "InvertFlags", 8175 argLen: 1, 8176 reg: regInfo{}, 8177 }, 8178 { 8179 name: "LoweredGetG", 8180 argLen: 1, 8181 reg: regInfo{ 8182 outputs: []outputInfo{ 8183 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8184 }, 8185 }, 8186 }, 8187 { 8188 name: "LoweredGetClosurePtr", 8189 argLen: 0, 8190 reg: regInfo{ 8191 outputs: []outputInfo{ 8192 {0, 4}, // DX 8193 }, 8194 }, 8195 }, 8196 { 8197 name: "LoweredGetCallerPC", 8198 argLen: 0, 8199 rematerializeable: true, 8200 reg: regInfo{ 8201 outputs: []outputInfo{ 8202 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8203 }, 8204 }, 8205 }, 8206 { 8207 name: "LoweredGetCallerSP", 8208 argLen: 0, 8209 rematerializeable: true, 8210 reg: regInfo{ 8211 outputs: []outputInfo{ 8212 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8213 }, 8214 }, 8215 }, 8216 { 8217 name: "LoweredNilCheck", 8218 argLen: 2, 8219 clobberFlags: true, 8220 nilCheck: true, 8221 faultOnNilArg0: true, 8222 reg: regInfo{ 8223 inputs: []inputInfo{ 8224 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8225 }, 8226 }, 8227 }, 8228 { 8229 name: "LoweredWB", 8230 auxType: auxSym, 8231 argLen: 3, 8232 clobberFlags: true, 8233 symEffect: SymNone, 8234 reg: regInfo{ 8235 inputs: []inputInfo{ 8236 {0, 128}, // DI 8237 {1, 1}, // AX 8238 }, 8239 clobbers: 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8240 }, 8241 }, 8242 { 8243 name: "MOVQconvert", 8244 argLen: 2, 8245 resultInArg0: true, 8246 asm: x86.AMOVQ, 8247 reg: regInfo{ 8248 inputs: []inputInfo{ 8249 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8250 }, 8251 outputs: []outputInfo{ 8252 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8253 }, 8254 }, 8255 }, 8256 { 8257 name: "MOVLconvert", 8258 argLen: 2, 8259 resultInArg0: true, 8260 asm: x86.AMOVL, 8261 reg: regInfo{ 8262 inputs: []inputInfo{ 8263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8264 }, 8265 outputs: []outputInfo{ 8266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8267 }, 8268 }, 8269 }, 8270 { 8271 name: "FlagEQ", 8272 argLen: 0, 8273 reg: regInfo{}, 8274 }, 8275 { 8276 name: "FlagLT_ULT", 8277 argLen: 0, 8278 reg: regInfo{}, 8279 }, 8280 { 8281 name: "FlagLT_UGT", 8282 argLen: 0, 8283 reg: regInfo{}, 8284 }, 8285 { 8286 name: "FlagGT_UGT", 8287 argLen: 0, 8288 reg: regInfo{}, 8289 }, 8290 { 8291 name: "FlagGT_ULT", 8292 argLen: 0, 8293 reg: regInfo{}, 8294 }, 8295 { 8296 name: "MOVLatomicload", 8297 auxType: auxSymOff, 8298 argLen: 2, 8299 faultOnNilArg0: true, 8300 symEffect: SymRead, 8301 asm: x86.AMOVL, 8302 reg: regInfo{ 8303 inputs: []inputInfo{ 8304 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8305 }, 8306 outputs: []outputInfo{ 8307 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8308 }, 8309 }, 8310 }, 8311 { 8312 name: "MOVQatomicload", 8313 auxType: auxSymOff, 8314 argLen: 2, 8315 faultOnNilArg0: true, 8316 symEffect: SymRead, 8317 asm: x86.AMOVQ, 8318 reg: regInfo{ 8319 inputs: []inputInfo{ 8320 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8321 }, 8322 outputs: []outputInfo{ 8323 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8324 }, 8325 }, 8326 }, 8327 { 8328 name: "XCHGL", 8329 auxType: auxSymOff, 8330 argLen: 3, 8331 resultInArg0: true, 8332 faultOnNilArg1: true, 8333 hasSideEffects: true, 8334 symEffect: SymRdWr, 8335 asm: x86.AXCHGL, 8336 reg: regInfo{ 8337 inputs: []inputInfo{ 8338 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8339 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8340 }, 8341 outputs: []outputInfo{ 8342 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8343 }, 8344 }, 8345 }, 8346 { 8347 name: "XCHGQ", 8348 auxType: auxSymOff, 8349 argLen: 3, 8350 resultInArg0: true, 8351 faultOnNilArg1: true, 8352 hasSideEffects: true, 8353 symEffect: SymRdWr, 8354 asm: x86.AXCHGQ, 8355 reg: regInfo{ 8356 inputs: []inputInfo{ 8357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8358 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8359 }, 8360 outputs: []outputInfo{ 8361 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8362 }, 8363 }, 8364 }, 8365 { 8366 name: "XADDLlock", 8367 auxType: auxSymOff, 8368 argLen: 3, 8369 resultInArg0: true, 8370 clobberFlags: true, 8371 faultOnNilArg1: true, 8372 hasSideEffects: true, 8373 symEffect: SymRdWr, 8374 asm: x86.AXADDL, 8375 reg: regInfo{ 8376 inputs: []inputInfo{ 8377 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8378 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8379 }, 8380 outputs: []outputInfo{ 8381 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8382 }, 8383 }, 8384 }, 8385 { 8386 name: "XADDQlock", 8387 auxType: auxSymOff, 8388 argLen: 3, 8389 resultInArg0: true, 8390 clobberFlags: true, 8391 faultOnNilArg1: true, 8392 hasSideEffects: true, 8393 symEffect: SymRdWr, 8394 asm: x86.AXADDQ, 8395 reg: regInfo{ 8396 inputs: []inputInfo{ 8397 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8398 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8399 }, 8400 outputs: []outputInfo{ 8401 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8402 }, 8403 }, 8404 }, 8405 { 8406 name: "AddTupleFirst32", 8407 argLen: 2, 8408 reg: regInfo{}, 8409 }, 8410 { 8411 name: "AddTupleFirst64", 8412 argLen: 2, 8413 reg: regInfo{}, 8414 }, 8415 { 8416 name: "CMPXCHGLlock", 8417 auxType: auxSymOff, 8418 argLen: 4, 8419 clobberFlags: true, 8420 faultOnNilArg0: true, 8421 hasSideEffects: true, 8422 symEffect: SymRdWr, 8423 asm: x86.ACMPXCHGL, 8424 reg: regInfo{ 8425 inputs: []inputInfo{ 8426 {1, 1}, // AX 8427 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8428 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8429 }, 8430 clobbers: 1, // AX 8431 outputs: []outputInfo{ 8432 {1, 0}, 8433 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8434 }, 8435 }, 8436 }, 8437 { 8438 name: "CMPXCHGQlock", 8439 auxType: auxSymOff, 8440 argLen: 4, 8441 clobberFlags: true, 8442 faultOnNilArg0: true, 8443 hasSideEffects: true, 8444 symEffect: SymRdWr, 8445 asm: x86.ACMPXCHGQ, 8446 reg: regInfo{ 8447 inputs: []inputInfo{ 8448 {1, 1}, // AX 8449 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8450 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8451 }, 8452 clobbers: 1, // AX 8453 outputs: []outputInfo{ 8454 {1, 0}, 8455 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8456 }, 8457 }, 8458 }, 8459 { 8460 name: "ANDBlock", 8461 auxType: auxSymOff, 8462 argLen: 3, 8463 clobberFlags: true, 8464 faultOnNilArg0: true, 8465 hasSideEffects: true, 8466 symEffect: SymRdWr, 8467 asm: x86.AANDB, 8468 reg: regInfo{ 8469 inputs: []inputInfo{ 8470 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8471 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8472 }, 8473 }, 8474 }, 8475 { 8476 name: "ORBlock", 8477 auxType: auxSymOff, 8478 argLen: 3, 8479 clobberFlags: true, 8480 faultOnNilArg0: true, 8481 hasSideEffects: true, 8482 symEffect: SymRdWr, 8483 asm: x86.AORB, 8484 reg: regInfo{ 8485 inputs: []inputInfo{ 8486 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8487 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8488 }, 8489 }, 8490 }, 8491 8492 { 8493 name: "ADD", 8494 argLen: 2, 8495 commutative: true, 8496 asm: arm.AADD, 8497 reg: regInfo{ 8498 inputs: []inputInfo{ 8499 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8500 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8501 }, 8502 outputs: []outputInfo{ 8503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8504 }, 8505 }, 8506 }, 8507 { 8508 name: "ADDconst", 8509 auxType: auxInt32, 8510 argLen: 1, 8511 asm: arm.AADD, 8512 reg: regInfo{ 8513 inputs: []inputInfo{ 8514 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8515 }, 8516 outputs: []outputInfo{ 8517 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8518 }, 8519 }, 8520 }, 8521 { 8522 name: "SUB", 8523 argLen: 2, 8524 asm: arm.ASUB, 8525 reg: regInfo{ 8526 inputs: []inputInfo{ 8527 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8528 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8529 }, 8530 outputs: []outputInfo{ 8531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8532 }, 8533 }, 8534 }, 8535 { 8536 name: "SUBconst", 8537 auxType: auxInt32, 8538 argLen: 1, 8539 asm: arm.ASUB, 8540 reg: regInfo{ 8541 inputs: []inputInfo{ 8542 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8543 }, 8544 outputs: []outputInfo{ 8545 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8546 }, 8547 }, 8548 }, 8549 { 8550 name: "RSB", 8551 argLen: 2, 8552 asm: arm.ARSB, 8553 reg: regInfo{ 8554 inputs: []inputInfo{ 8555 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8556 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8557 }, 8558 outputs: []outputInfo{ 8559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8560 }, 8561 }, 8562 }, 8563 { 8564 name: "RSBconst", 8565 auxType: auxInt32, 8566 argLen: 1, 8567 asm: arm.ARSB, 8568 reg: regInfo{ 8569 inputs: []inputInfo{ 8570 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8571 }, 8572 outputs: []outputInfo{ 8573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8574 }, 8575 }, 8576 }, 8577 { 8578 name: "MUL", 8579 argLen: 2, 8580 commutative: true, 8581 asm: arm.AMUL, 8582 reg: regInfo{ 8583 inputs: []inputInfo{ 8584 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8585 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8586 }, 8587 outputs: []outputInfo{ 8588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8589 }, 8590 }, 8591 }, 8592 { 8593 name: "HMUL", 8594 argLen: 2, 8595 commutative: true, 8596 asm: arm.AMULL, 8597 reg: regInfo{ 8598 inputs: []inputInfo{ 8599 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8600 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8601 }, 8602 outputs: []outputInfo{ 8603 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8604 }, 8605 }, 8606 }, 8607 { 8608 name: "HMULU", 8609 argLen: 2, 8610 commutative: true, 8611 asm: arm.AMULLU, 8612 reg: regInfo{ 8613 inputs: []inputInfo{ 8614 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8615 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8616 }, 8617 outputs: []outputInfo{ 8618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8619 }, 8620 }, 8621 }, 8622 { 8623 name: "CALLudiv", 8624 argLen: 2, 8625 clobberFlags: true, 8626 reg: regInfo{ 8627 inputs: []inputInfo{ 8628 {0, 2}, // R1 8629 {1, 1}, // R0 8630 }, 8631 clobbers: 16396, // R2 R3 R14 8632 outputs: []outputInfo{ 8633 {0, 1}, // R0 8634 {1, 2}, // R1 8635 }, 8636 }, 8637 }, 8638 { 8639 name: "ADDS", 8640 argLen: 2, 8641 commutative: true, 8642 asm: arm.AADD, 8643 reg: regInfo{ 8644 inputs: []inputInfo{ 8645 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8646 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8647 }, 8648 outputs: []outputInfo{ 8649 {1, 0}, 8650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8651 }, 8652 }, 8653 }, 8654 { 8655 name: "ADDSconst", 8656 auxType: auxInt32, 8657 argLen: 1, 8658 asm: arm.AADD, 8659 reg: regInfo{ 8660 inputs: []inputInfo{ 8661 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8662 }, 8663 outputs: []outputInfo{ 8664 {1, 0}, 8665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8666 }, 8667 }, 8668 }, 8669 { 8670 name: "ADC", 8671 argLen: 3, 8672 commutative: true, 8673 asm: arm.AADC, 8674 reg: regInfo{ 8675 inputs: []inputInfo{ 8676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8677 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8678 }, 8679 outputs: []outputInfo{ 8680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8681 }, 8682 }, 8683 }, 8684 { 8685 name: "ADCconst", 8686 auxType: auxInt32, 8687 argLen: 2, 8688 asm: arm.AADC, 8689 reg: regInfo{ 8690 inputs: []inputInfo{ 8691 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8692 }, 8693 outputs: []outputInfo{ 8694 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8695 }, 8696 }, 8697 }, 8698 { 8699 name: "SUBS", 8700 argLen: 2, 8701 asm: arm.ASUB, 8702 reg: regInfo{ 8703 inputs: []inputInfo{ 8704 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8705 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8706 }, 8707 outputs: []outputInfo{ 8708 {1, 0}, 8709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8710 }, 8711 }, 8712 }, 8713 { 8714 name: "SUBSconst", 8715 auxType: auxInt32, 8716 argLen: 1, 8717 asm: arm.ASUB, 8718 reg: regInfo{ 8719 inputs: []inputInfo{ 8720 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8721 }, 8722 outputs: []outputInfo{ 8723 {1, 0}, 8724 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8725 }, 8726 }, 8727 }, 8728 { 8729 name: "RSBSconst", 8730 auxType: auxInt32, 8731 argLen: 1, 8732 asm: arm.ARSB, 8733 reg: regInfo{ 8734 inputs: []inputInfo{ 8735 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8736 }, 8737 outputs: []outputInfo{ 8738 {1, 0}, 8739 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8740 }, 8741 }, 8742 }, 8743 { 8744 name: "SBC", 8745 argLen: 3, 8746 asm: arm.ASBC, 8747 reg: regInfo{ 8748 inputs: []inputInfo{ 8749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8750 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8751 }, 8752 outputs: []outputInfo{ 8753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8754 }, 8755 }, 8756 }, 8757 { 8758 name: "SBCconst", 8759 auxType: auxInt32, 8760 argLen: 2, 8761 asm: arm.ASBC, 8762 reg: regInfo{ 8763 inputs: []inputInfo{ 8764 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8765 }, 8766 outputs: []outputInfo{ 8767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8768 }, 8769 }, 8770 }, 8771 { 8772 name: "RSCconst", 8773 auxType: auxInt32, 8774 argLen: 2, 8775 asm: arm.ARSC, 8776 reg: regInfo{ 8777 inputs: []inputInfo{ 8778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8779 }, 8780 outputs: []outputInfo{ 8781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8782 }, 8783 }, 8784 }, 8785 { 8786 name: "MULLU", 8787 argLen: 2, 8788 commutative: true, 8789 asm: arm.AMULLU, 8790 reg: regInfo{ 8791 inputs: []inputInfo{ 8792 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8793 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8794 }, 8795 outputs: []outputInfo{ 8796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8797 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8798 }, 8799 }, 8800 }, 8801 { 8802 name: "MULA", 8803 argLen: 3, 8804 asm: arm.AMULA, 8805 reg: regInfo{ 8806 inputs: []inputInfo{ 8807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8808 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8809 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8810 }, 8811 outputs: []outputInfo{ 8812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8813 }, 8814 }, 8815 }, 8816 { 8817 name: "MULS", 8818 argLen: 3, 8819 asm: arm.AMULS, 8820 reg: regInfo{ 8821 inputs: []inputInfo{ 8822 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8823 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8824 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8825 }, 8826 outputs: []outputInfo{ 8827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8828 }, 8829 }, 8830 }, 8831 { 8832 name: "ADDF", 8833 argLen: 2, 8834 commutative: true, 8835 asm: arm.AADDF, 8836 reg: regInfo{ 8837 inputs: []inputInfo{ 8838 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8839 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8840 }, 8841 outputs: []outputInfo{ 8842 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8843 }, 8844 }, 8845 }, 8846 { 8847 name: "ADDD", 8848 argLen: 2, 8849 commutative: true, 8850 asm: arm.AADDD, 8851 reg: regInfo{ 8852 inputs: []inputInfo{ 8853 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8854 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8855 }, 8856 outputs: []outputInfo{ 8857 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8858 }, 8859 }, 8860 }, 8861 { 8862 name: "SUBF", 8863 argLen: 2, 8864 asm: arm.ASUBF, 8865 reg: regInfo{ 8866 inputs: []inputInfo{ 8867 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8868 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8869 }, 8870 outputs: []outputInfo{ 8871 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8872 }, 8873 }, 8874 }, 8875 { 8876 name: "SUBD", 8877 argLen: 2, 8878 asm: arm.ASUBD, 8879 reg: regInfo{ 8880 inputs: []inputInfo{ 8881 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8882 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8883 }, 8884 outputs: []outputInfo{ 8885 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8886 }, 8887 }, 8888 }, 8889 { 8890 name: "MULF", 8891 argLen: 2, 8892 commutative: true, 8893 asm: arm.AMULF, 8894 reg: regInfo{ 8895 inputs: []inputInfo{ 8896 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8897 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8898 }, 8899 outputs: []outputInfo{ 8900 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8901 }, 8902 }, 8903 }, 8904 { 8905 name: "MULD", 8906 argLen: 2, 8907 commutative: true, 8908 asm: arm.AMULD, 8909 reg: regInfo{ 8910 inputs: []inputInfo{ 8911 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8912 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8913 }, 8914 outputs: []outputInfo{ 8915 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8916 }, 8917 }, 8918 }, 8919 { 8920 name: "NMULF", 8921 argLen: 2, 8922 commutative: true, 8923 asm: arm.ANMULF, 8924 reg: regInfo{ 8925 inputs: []inputInfo{ 8926 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8927 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8928 }, 8929 outputs: []outputInfo{ 8930 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8931 }, 8932 }, 8933 }, 8934 { 8935 name: "NMULD", 8936 argLen: 2, 8937 commutative: true, 8938 asm: arm.ANMULD, 8939 reg: regInfo{ 8940 inputs: []inputInfo{ 8941 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8942 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8943 }, 8944 outputs: []outputInfo{ 8945 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8946 }, 8947 }, 8948 }, 8949 { 8950 name: "DIVF", 8951 argLen: 2, 8952 asm: arm.ADIVF, 8953 reg: regInfo{ 8954 inputs: []inputInfo{ 8955 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8956 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8957 }, 8958 outputs: []outputInfo{ 8959 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8960 }, 8961 }, 8962 }, 8963 { 8964 name: "DIVD", 8965 argLen: 2, 8966 asm: arm.ADIVD, 8967 reg: regInfo{ 8968 inputs: []inputInfo{ 8969 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8970 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8971 }, 8972 outputs: []outputInfo{ 8973 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8974 }, 8975 }, 8976 }, 8977 { 8978 name: "MULAF", 8979 argLen: 3, 8980 resultInArg0: true, 8981 asm: arm.AMULAF, 8982 reg: regInfo{ 8983 inputs: []inputInfo{ 8984 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8985 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8986 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8987 }, 8988 outputs: []outputInfo{ 8989 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8990 }, 8991 }, 8992 }, 8993 { 8994 name: "MULAD", 8995 argLen: 3, 8996 resultInArg0: true, 8997 asm: arm.AMULAD, 8998 reg: regInfo{ 8999 inputs: []inputInfo{ 9000 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9001 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9002 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9003 }, 9004 outputs: []outputInfo{ 9005 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9006 }, 9007 }, 9008 }, 9009 { 9010 name: "MULSF", 9011 argLen: 3, 9012 resultInArg0: true, 9013 asm: arm.AMULSF, 9014 reg: regInfo{ 9015 inputs: []inputInfo{ 9016 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9017 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9018 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9019 }, 9020 outputs: []outputInfo{ 9021 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9022 }, 9023 }, 9024 }, 9025 { 9026 name: "MULSD", 9027 argLen: 3, 9028 resultInArg0: true, 9029 asm: arm.AMULSD, 9030 reg: regInfo{ 9031 inputs: []inputInfo{ 9032 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9033 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9034 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9035 }, 9036 outputs: []outputInfo{ 9037 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9038 }, 9039 }, 9040 }, 9041 { 9042 name: "AND", 9043 argLen: 2, 9044 commutative: true, 9045 asm: arm.AAND, 9046 reg: regInfo{ 9047 inputs: []inputInfo{ 9048 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9049 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9050 }, 9051 outputs: []outputInfo{ 9052 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9053 }, 9054 }, 9055 }, 9056 { 9057 name: "ANDconst", 9058 auxType: auxInt32, 9059 argLen: 1, 9060 asm: arm.AAND, 9061 reg: regInfo{ 9062 inputs: []inputInfo{ 9063 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9064 }, 9065 outputs: []outputInfo{ 9066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9067 }, 9068 }, 9069 }, 9070 { 9071 name: "OR", 9072 argLen: 2, 9073 commutative: true, 9074 asm: arm.AORR, 9075 reg: regInfo{ 9076 inputs: []inputInfo{ 9077 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9078 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9079 }, 9080 outputs: []outputInfo{ 9081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9082 }, 9083 }, 9084 }, 9085 { 9086 name: "ORconst", 9087 auxType: auxInt32, 9088 argLen: 1, 9089 asm: arm.AORR, 9090 reg: regInfo{ 9091 inputs: []inputInfo{ 9092 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9093 }, 9094 outputs: []outputInfo{ 9095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9096 }, 9097 }, 9098 }, 9099 { 9100 name: "XOR", 9101 argLen: 2, 9102 commutative: true, 9103 asm: arm.AEOR, 9104 reg: regInfo{ 9105 inputs: []inputInfo{ 9106 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9107 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9108 }, 9109 outputs: []outputInfo{ 9110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9111 }, 9112 }, 9113 }, 9114 { 9115 name: "XORconst", 9116 auxType: auxInt32, 9117 argLen: 1, 9118 asm: arm.AEOR, 9119 reg: regInfo{ 9120 inputs: []inputInfo{ 9121 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9122 }, 9123 outputs: []outputInfo{ 9124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9125 }, 9126 }, 9127 }, 9128 { 9129 name: "BIC", 9130 argLen: 2, 9131 asm: arm.ABIC, 9132 reg: regInfo{ 9133 inputs: []inputInfo{ 9134 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9135 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9136 }, 9137 outputs: []outputInfo{ 9138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9139 }, 9140 }, 9141 }, 9142 { 9143 name: "BICconst", 9144 auxType: auxInt32, 9145 argLen: 1, 9146 asm: arm.ABIC, 9147 reg: regInfo{ 9148 inputs: []inputInfo{ 9149 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9150 }, 9151 outputs: []outputInfo{ 9152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9153 }, 9154 }, 9155 }, 9156 { 9157 name: "BFX", 9158 auxType: auxInt32, 9159 argLen: 1, 9160 asm: arm.ABFX, 9161 reg: regInfo{ 9162 inputs: []inputInfo{ 9163 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9164 }, 9165 outputs: []outputInfo{ 9166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9167 }, 9168 }, 9169 }, 9170 { 9171 name: "BFXU", 9172 auxType: auxInt32, 9173 argLen: 1, 9174 asm: arm.ABFXU, 9175 reg: regInfo{ 9176 inputs: []inputInfo{ 9177 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9178 }, 9179 outputs: []outputInfo{ 9180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9181 }, 9182 }, 9183 }, 9184 { 9185 name: "MVN", 9186 argLen: 1, 9187 asm: arm.AMVN, 9188 reg: regInfo{ 9189 inputs: []inputInfo{ 9190 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9191 }, 9192 outputs: []outputInfo{ 9193 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9194 }, 9195 }, 9196 }, 9197 { 9198 name: "NEGF", 9199 argLen: 1, 9200 asm: arm.ANEGF, 9201 reg: regInfo{ 9202 inputs: []inputInfo{ 9203 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9204 }, 9205 outputs: []outputInfo{ 9206 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9207 }, 9208 }, 9209 }, 9210 { 9211 name: "NEGD", 9212 argLen: 1, 9213 asm: arm.ANEGD, 9214 reg: regInfo{ 9215 inputs: []inputInfo{ 9216 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9217 }, 9218 outputs: []outputInfo{ 9219 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9220 }, 9221 }, 9222 }, 9223 { 9224 name: "SQRTD", 9225 argLen: 1, 9226 asm: arm.ASQRTD, 9227 reg: regInfo{ 9228 inputs: []inputInfo{ 9229 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9230 }, 9231 outputs: []outputInfo{ 9232 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9233 }, 9234 }, 9235 }, 9236 { 9237 name: "CLZ", 9238 argLen: 1, 9239 asm: arm.ACLZ, 9240 reg: regInfo{ 9241 inputs: []inputInfo{ 9242 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9243 }, 9244 outputs: []outputInfo{ 9245 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9246 }, 9247 }, 9248 }, 9249 { 9250 name: "REV", 9251 argLen: 1, 9252 asm: arm.AREV, 9253 reg: regInfo{ 9254 inputs: []inputInfo{ 9255 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9256 }, 9257 outputs: []outputInfo{ 9258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9259 }, 9260 }, 9261 }, 9262 { 9263 name: "RBIT", 9264 argLen: 1, 9265 asm: arm.ARBIT, 9266 reg: regInfo{ 9267 inputs: []inputInfo{ 9268 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9269 }, 9270 outputs: []outputInfo{ 9271 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9272 }, 9273 }, 9274 }, 9275 { 9276 name: "SLL", 9277 argLen: 2, 9278 asm: arm.ASLL, 9279 reg: regInfo{ 9280 inputs: []inputInfo{ 9281 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9282 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9283 }, 9284 outputs: []outputInfo{ 9285 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9286 }, 9287 }, 9288 }, 9289 { 9290 name: "SLLconst", 9291 auxType: auxInt32, 9292 argLen: 1, 9293 asm: arm.ASLL, 9294 reg: regInfo{ 9295 inputs: []inputInfo{ 9296 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9297 }, 9298 outputs: []outputInfo{ 9299 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9300 }, 9301 }, 9302 }, 9303 { 9304 name: "SRL", 9305 argLen: 2, 9306 asm: arm.ASRL, 9307 reg: regInfo{ 9308 inputs: []inputInfo{ 9309 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9310 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9311 }, 9312 outputs: []outputInfo{ 9313 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9314 }, 9315 }, 9316 }, 9317 { 9318 name: "SRLconst", 9319 auxType: auxInt32, 9320 argLen: 1, 9321 asm: arm.ASRL, 9322 reg: regInfo{ 9323 inputs: []inputInfo{ 9324 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9325 }, 9326 outputs: []outputInfo{ 9327 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9328 }, 9329 }, 9330 }, 9331 { 9332 name: "SRA", 9333 argLen: 2, 9334 asm: arm.ASRA, 9335 reg: regInfo{ 9336 inputs: []inputInfo{ 9337 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9338 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9339 }, 9340 outputs: []outputInfo{ 9341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9342 }, 9343 }, 9344 }, 9345 { 9346 name: "SRAconst", 9347 auxType: auxInt32, 9348 argLen: 1, 9349 asm: arm.ASRA, 9350 reg: regInfo{ 9351 inputs: []inputInfo{ 9352 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9353 }, 9354 outputs: []outputInfo{ 9355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9356 }, 9357 }, 9358 }, 9359 { 9360 name: "SRRconst", 9361 auxType: auxInt32, 9362 argLen: 1, 9363 reg: regInfo{ 9364 inputs: []inputInfo{ 9365 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9366 }, 9367 outputs: []outputInfo{ 9368 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9369 }, 9370 }, 9371 }, 9372 { 9373 name: "ADDshiftLL", 9374 auxType: auxInt32, 9375 argLen: 2, 9376 asm: arm.AADD, 9377 reg: regInfo{ 9378 inputs: []inputInfo{ 9379 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9380 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9381 }, 9382 outputs: []outputInfo{ 9383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9384 }, 9385 }, 9386 }, 9387 { 9388 name: "ADDshiftRL", 9389 auxType: auxInt32, 9390 argLen: 2, 9391 asm: arm.AADD, 9392 reg: regInfo{ 9393 inputs: []inputInfo{ 9394 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9395 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9396 }, 9397 outputs: []outputInfo{ 9398 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9399 }, 9400 }, 9401 }, 9402 { 9403 name: "ADDshiftRA", 9404 auxType: auxInt32, 9405 argLen: 2, 9406 asm: arm.AADD, 9407 reg: regInfo{ 9408 inputs: []inputInfo{ 9409 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9410 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9411 }, 9412 outputs: []outputInfo{ 9413 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9414 }, 9415 }, 9416 }, 9417 { 9418 name: "SUBshiftLL", 9419 auxType: auxInt32, 9420 argLen: 2, 9421 asm: arm.ASUB, 9422 reg: regInfo{ 9423 inputs: []inputInfo{ 9424 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9425 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9426 }, 9427 outputs: []outputInfo{ 9428 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9429 }, 9430 }, 9431 }, 9432 { 9433 name: "SUBshiftRL", 9434 auxType: auxInt32, 9435 argLen: 2, 9436 asm: arm.ASUB, 9437 reg: regInfo{ 9438 inputs: []inputInfo{ 9439 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9440 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9441 }, 9442 outputs: []outputInfo{ 9443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9444 }, 9445 }, 9446 }, 9447 { 9448 name: "SUBshiftRA", 9449 auxType: auxInt32, 9450 argLen: 2, 9451 asm: arm.ASUB, 9452 reg: regInfo{ 9453 inputs: []inputInfo{ 9454 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9455 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9456 }, 9457 outputs: []outputInfo{ 9458 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9459 }, 9460 }, 9461 }, 9462 { 9463 name: "RSBshiftLL", 9464 auxType: auxInt32, 9465 argLen: 2, 9466 asm: arm.ARSB, 9467 reg: regInfo{ 9468 inputs: []inputInfo{ 9469 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9470 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9471 }, 9472 outputs: []outputInfo{ 9473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9474 }, 9475 }, 9476 }, 9477 { 9478 name: "RSBshiftRL", 9479 auxType: auxInt32, 9480 argLen: 2, 9481 asm: arm.ARSB, 9482 reg: regInfo{ 9483 inputs: []inputInfo{ 9484 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9485 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9486 }, 9487 outputs: []outputInfo{ 9488 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9489 }, 9490 }, 9491 }, 9492 { 9493 name: "RSBshiftRA", 9494 auxType: auxInt32, 9495 argLen: 2, 9496 asm: arm.ARSB, 9497 reg: regInfo{ 9498 inputs: []inputInfo{ 9499 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9500 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9501 }, 9502 outputs: []outputInfo{ 9503 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9504 }, 9505 }, 9506 }, 9507 { 9508 name: "ANDshiftLL", 9509 auxType: auxInt32, 9510 argLen: 2, 9511 asm: arm.AAND, 9512 reg: regInfo{ 9513 inputs: []inputInfo{ 9514 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9515 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9516 }, 9517 outputs: []outputInfo{ 9518 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9519 }, 9520 }, 9521 }, 9522 { 9523 name: "ANDshiftRL", 9524 auxType: auxInt32, 9525 argLen: 2, 9526 asm: arm.AAND, 9527 reg: regInfo{ 9528 inputs: []inputInfo{ 9529 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9530 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9531 }, 9532 outputs: []outputInfo{ 9533 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9534 }, 9535 }, 9536 }, 9537 { 9538 name: "ANDshiftRA", 9539 auxType: auxInt32, 9540 argLen: 2, 9541 asm: arm.AAND, 9542 reg: regInfo{ 9543 inputs: []inputInfo{ 9544 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9545 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9546 }, 9547 outputs: []outputInfo{ 9548 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9549 }, 9550 }, 9551 }, 9552 { 9553 name: "ORshiftLL", 9554 auxType: auxInt32, 9555 argLen: 2, 9556 asm: arm.AORR, 9557 reg: regInfo{ 9558 inputs: []inputInfo{ 9559 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9560 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9561 }, 9562 outputs: []outputInfo{ 9563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9564 }, 9565 }, 9566 }, 9567 { 9568 name: "ORshiftRL", 9569 auxType: auxInt32, 9570 argLen: 2, 9571 asm: arm.AORR, 9572 reg: regInfo{ 9573 inputs: []inputInfo{ 9574 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9575 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9576 }, 9577 outputs: []outputInfo{ 9578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9579 }, 9580 }, 9581 }, 9582 { 9583 name: "ORshiftRA", 9584 auxType: auxInt32, 9585 argLen: 2, 9586 asm: arm.AORR, 9587 reg: regInfo{ 9588 inputs: []inputInfo{ 9589 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9590 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9591 }, 9592 outputs: []outputInfo{ 9593 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9594 }, 9595 }, 9596 }, 9597 { 9598 name: "XORshiftLL", 9599 auxType: auxInt32, 9600 argLen: 2, 9601 asm: arm.AEOR, 9602 reg: regInfo{ 9603 inputs: []inputInfo{ 9604 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9605 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9606 }, 9607 outputs: []outputInfo{ 9608 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9609 }, 9610 }, 9611 }, 9612 { 9613 name: "XORshiftRL", 9614 auxType: auxInt32, 9615 argLen: 2, 9616 asm: arm.AEOR, 9617 reg: regInfo{ 9618 inputs: []inputInfo{ 9619 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9620 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9621 }, 9622 outputs: []outputInfo{ 9623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9624 }, 9625 }, 9626 }, 9627 { 9628 name: "XORshiftRA", 9629 auxType: auxInt32, 9630 argLen: 2, 9631 asm: arm.AEOR, 9632 reg: regInfo{ 9633 inputs: []inputInfo{ 9634 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9635 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9636 }, 9637 outputs: []outputInfo{ 9638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9639 }, 9640 }, 9641 }, 9642 { 9643 name: "XORshiftRR", 9644 auxType: auxInt32, 9645 argLen: 2, 9646 asm: arm.AEOR, 9647 reg: regInfo{ 9648 inputs: []inputInfo{ 9649 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9650 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9651 }, 9652 outputs: []outputInfo{ 9653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9654 }, 9655 }, 9656 }, 9657 { 9658 name: "BICshiftLL", 9659 auxType: auxInt32, 9660 argLen: 2, 9661 asm: arm.ABIC, 9662 reg: regInfo{ 9663 inputs: []inputInfo{ 9664 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9665 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9666 }, 9667 outputs: []outputInfo{ 9668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9669 }, 9670 }, 9671 }, 9672 { 9673 name: "BICshiftRL", 9674 auxType: auxInt32, 9675 argLen: 2, 9676 asm: arm.ABIC, 9677 reg: regInfo{ 9678 inputs: []inputInfo{ 9679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9680 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9681 }, 9682 outputs: []outputInfo{ 9683 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9684 }, 9685 }, 9686 }, 9687 { 9688 name: "BICshiftRA", 9689 auxType: auxInt32, 9690 argLen: 2, 9691 asm: arm.ABIC, 9692 reg: regInfo{ 9693 inputs: []inputInfo{ 9694 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9695 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9696 }, 9697 outputs: []outputInfo{ 9698 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9699 }, 9700 }, 9701 }, 9702 { 9703 name: "MVNshiftLL", 9704 auxType: auxInt32, 9705 argLen: 1, 9706 asm: arm.AMVN, 9707 reg: regInfo{ 9708 inputs: []inputInfo{ 9709 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9710 }, 9711 outputs: []outputInfo{ 9712 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9713 }, 9714 }, 9715 }, 9716 { 9717 name: "MVNshiftRL", 9718 auxType: auxInt32, 9719 argLen: 1, 9720 asm: arm.AMVN, 9721 reg: regInfo{ 9722 inputs: []inputInfo{ 9723 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9724 }, 9725 outputs: []outputInfo{ 9726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9727 }, 9728 }, 9729 }, 9730 { 9731 name: "MVNshiftRA", 9732 auxType: auxInt32, 9733 argLen: 1, 9734 asm: arm.AMVN, 9735 reg: regInfo{ 9736 inputs: []inputInfo{ 9737 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9738 }, 9739 outputs: []outputInfo{ 9740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9741 }, 9742 }, 9743 }, 9744 { 9745 name: "ADCshiftLL", 9746 auxType: auxInt32, 9747 argLen: 3, 9748 asm: arm.AADC, 9749 reg: regInfo{ 9750 inputs: []inputInfo{ 9751 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9752 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9753 }, 9754 outputs: []outputInfo{ 9755 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9756 }, 9757 }, 9758 }, 9759 { 9760 name: "ADCshiftRL", 9761 auxType: auxInt32, 9762 argLen: 3, 9763 asm: arm.AADC, 9764 reg: regInfo{ 9765 inputs: []inputInfo{ 9766 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9767 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9768 }, 9769 outputs: []outputInfo{ 9770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9771 }, 9772 }, 9773 }, 9774 { 9775 name: "ADCshiftRA", 9776 auxType: auxInt32, 9777 argLen: 3, 9778 asm: arm.AADC, 9779 reg: regInfo{ 9780 inputs: []inputInfo{ 9781 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9782 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9783 }, 9784 outputs: []outputInfo{ 9785 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9786 }, 9787 }, 9788 }, 9789 { 9790 name: "SBCshiftLL", 9791 auxType: auxInt32, 9792 argLen: 3, 9793 asm: arm.ASBC, 9794 reg: regInfo{ 9795 inputs: []inputInfo{ 9796 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9797 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9798 }, 9799 outputs: []outputInfo{ 9800 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9801 }, 9802 }, 9803 }, 9804 { 9805 name: "SBCshiftRL", 9806 auxType: auxInt32, 9807 argLen: 3, 9808 asm: arm.ASBC, 9809 reg: regInfo{ 9810 inputs: []inputInfo{ 9811 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9812 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9813 }, 9814 outputs: []outputInfo{ 9815 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9816 }, 9817 }, 9818 }, 9819 { 9820 name: "SBCshiftRA", 9821 auxType: auxInt32, 9822 argLen: 3, 9823 asm: arm.ASBC, 9824 reg: regInfo{ 9825 inputs: []inputInfo{ 9826 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9827 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9828 }, 9829 outputs: []outputInfo{ 9830 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9831 }, 9832 }, 9833 }, 9834 { 9835 name: "RSCshiftLL", 9836 auxType: auxInt32, 9837 argLen: 3, 9838 asm: arm.ARSC, 9839 reg: regInfo{ 9840 inputs: []inputInfo{ 9841 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9842 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9843 }, 9844 outputs: []outputInfo{ 9845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9846 }, 9847 }, 9848 }, 9849 { 9850 name: "RSCshiftRL", 9851 auxType: auxInt32, 9852 argLen: 3, 9853 asm: arm.ARSC, 9854 reg: regInfo{ 9855 inputs: []inputInfo{ 9856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9857 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9858 }, 9859 outputs: []outputInfo{ 9860 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9861 }, 9862 }, 9863 }, 9864 { 9865 name: "RSCshiftRA", 9866 auxType: auxInt32, 9867 argLen: 3, 9868 asm: arm.ARSC, 9869 reg: regInfo{ 9870 inputs: []inputInfo{ 9871 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9872 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9873 }, 9874 outputs: []outputInfo{ 9875 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9876 }, 9877 }, 9878 }, 9879 { 9880 name: "ADDSshiftLL", 9881 auxType: auxInt32, 9882 argLen: 2, 9883 asm: arm.AADD, 9884 reg: regInfo{ 9885 inputs: []inputInfo{ 9886 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9887 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9888 }, 9889 outputs: []outputInfo{ 9890 {1, 0}, 9891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9892 }, 9893 }, 9894 }, 9895 { 9896 name: "ADDSshiftRL", 9897 auxType: auxInt32, 9898 argLen: 2, 9899 asm: arm.AADD, 9900 reg: regInfo{ 9901 inputs: []inputInfo{ 9902 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9903 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9904 }, 9905 outputs: []outputInfo{ 9906 {1, 0}, 9907 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9908 }, 9909 }, 9910 }, 9911 { 9912 name: "ADDSshiftRA", 9913 auxType: auxInt32, 9914 argLen: 2, 9915 asm: arm.AADD, 9916 reg: regInfo{ 9917 inputs: []inputInfo{ 9918 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9919 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9920 }, 9921 outputs: []outputInfo{ 9922 {1, 0}, 9923 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9924 }, 9925 }, 9926 }, 9927 { 9928 name: "SUBSshiftLL", 9929 auxType: auxInt32, 9930 argLen: 2, 9931 asm: arm.ASUB, 9932 reg: regInfo{ 9933 inputs: []inputInfo{ 9934 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9935 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9936 }, 9937 outputs: []outputInfo{ 9938 {1, 0}, 9939 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9940 }, 9941 }, 9942 }, 9943 { 9944 name: "SUBSshiftRL", 9945 auxType: auxInt32, 9946 argLen: 2, 9947 asm: arm.ASUB, 9948 reg: regInfo{ 9949 inputs: []inputInfo{ 9950 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9951 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9952 }, 9953 outputs: []outputInfo{ 9954 {1, 0}, 9955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9956 }, 9957 }, 9958 }, 9959 { 9960 name: "SUBSshiftRA", 9961 auxType: auxInt32, 9962 argLen: 2, 9963 asm: arm.ASUB, 9964 reg: regInfo{ 9965 inputs: []inputInfo{ 9966 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9967 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9968 }, 9969 outputs: []outputInfo{ 9970 {1, 0}, 9971 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9972 }, 9973 }, 9974 }, 9975 { 9976 name: "RSBSshiftLL", 9977 auxType: auxInt32, 9978 argLen: 2, 9979 asm: arm.ARSB, 9980 reg: regInfo{ 9981 inputs: []inputInfo{ 9982 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9983 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9984 }, 9985 outputs: []outputInfo{ 9986 {1, 0}, 9987 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9988 }, 9989 }, 9990 }, 9991 { 9992 name: "RSBSshiftRL", 9993 auxType: auxInt32, 9994 argLen: 2, 9995 asm: arm.ARSB, 9996 reg: regInfo{ 9997 inputs: []inputInfo{ 9998 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9999 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10000 }, 10001 outputs: []outputInfo{ 10002 {1, 0}, 10003 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10004 }, 10005 }, 10006 }, 10007 { 10008 name: "RSBSshiftRA", 10009 auxType: auxInt32, 10010 argLen: 2, 10011 asm: arm.ARSB, 10012 reg: regInfo{ 10013 inputs: []inputInfo{ 10014 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10015 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10016 }, 10017 outputs: []outputInfo{ 10018 {1, 0}, 10019 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10020 }, 10021 }, 10022 }, 10023 { 10024 name: "ADDshiftLLreg", 10025 argLen: 3, 10026 asm: arm.AADD, 10027 reg: regInfo{ 10028 inputs: []inputInfo{ 10029 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10030 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10032 }, 10033 outputs: []outputInfo{ 10034 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10035 }, 10036 }, 10037 }, 10038 { 10039 name: "ADDshiftRLreg", 10040 argLen: 3, 10041 asm: arm.AADD, 10042 reg: regInfo{ 10043 inputs: []inputInfo{ 10044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10045 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10047 }, 10048 outputs: []outputInfo{ 10049 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10050 }, 10051 }, 10052 }, 10053 { 10054 name: "ADDshiftRAreg", 10055 argLen: 3, 10056 asm: arm.AADD, 10057 reg: regInfo{ 10058 inputs: []inputInfo{ 10059 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10060 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10061 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 }, 10063 outputs: []outputInfo{ 10064 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10065 }, 10066 }, 10067 }, 10068 { 10069 name: "SUBshiftLLreg", 10070 argLen: 3, 10071 asm: arm.ASUB, 10072 reg: regInfo{ 10073 inputs: []inputInfo{ 10074 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10075 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10076 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10077 }, 10078 outputs: []outputInfo{ 10079 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10080 }, 10081 }, 10082 }, 10083 { 10084 name: "SUBshiftRLreg", 10085 argLen: 3, 10086 asm: arm.ASUB, 10087 reg: regInfo{ 10088 inputs: []inputInfo{ 10089 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10090 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10091 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10092 }, 10093 outputs: []outputInfo{ 10094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10095 }, 10096 }, 10097 }, 10098 { 10099 name: "SUBshiftRAreg", 10100 argLen: 3, 10101 asm: arm.ASUB, 10102 reg: regInfo{ 10103 inputs: []inputInfo{ 10104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10105 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10106 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10107 }, 10108 outputs: []outputInfo{ 10109 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10110 }, 10111 }, 10112 }, 10113 { 10114 name: "RSBshiftLLreg", 10115 argLen: 3, 10116 asm: arm.ARSB, 10117 reg: regInfo{ 10118 inputs: []inputInfo{ 10119 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10120 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10121 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10122 }, 10123 outputs: []outputInfo{ 10124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10125 }, 10126 }, 10127 }, 10128 { 10129 name: "RSBshiftRLreg", 10130 argLen: 3, 10131 asm: arm.ARSB, 10132 reg: regInfo{ 10133 inputs: []inputInfo{ 10134 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10135 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10136 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10137 }, 10138 outputs: []outputInfo{ 10139 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10140 }, 10141 }, 10142 }, 10143 { 10144 name: "RSBshiftRAreg", 10145 argLen: 3, 10146 asm: arm.ARSB, 10147 reg: regInfo{ 10148 inputs: []inputInfo{ 10149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10150 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10151 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10152 }, 10153 outputs: []outputInfo{ 10154 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10155 }, 10156 }, 10157 }, 10158 { 10159 name: "ANDshiftLLreg", 10160 argLen: 3, 10161 asm: arm.AAND, 10162 reg: regInfo{ 10163 inputs: []inputInfo{ 10164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10165 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10166 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10167 }, 10168 outputs: []outputInfo{ 10169 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10170 }, 10171 }, 10172 }, 10173 { 10174 name: "ANDshiftRLreg", 10175 argLen: 3, 10176 asm: arm.AAND, 10177 reg: regInfo{ 10178 inputs: []inputInfo{ 10179 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10180 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10181 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10182 }, 10183 outputs: []outputInfo{ 10184 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10185 }, 10186 }, 10187 }, 10188 { 10189 name: "ANDshiftRAreg", 10190 argLen: 3, 10191 asm: arm.AAND, 10192 reg: regInfo{ 10193 inputs: []inputInfo{ 10194 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10195 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10196 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10197 }, 10198 outputs: []outputInfo{ 10199 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10200 }, 10201 }, 10202 }, 10203 { 10204 name: "ORshiftLLreg", 10205 argLen: 3, 10206 asm: arm.AORR, 10207 reg: regInfo{ 10208 inputs: []inputInfo{ 10209 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10210 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10211 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10212 }, 10213 outputs: []outputInfo{ 10214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10215 }, 10216 }, 10217 }, 10218 { 10219 name: "ORshiftRLreg", 10220 argLen: 3, 10221 asm: arm.AORR, 10222 reg: regInfo{ 10223 inputs: []inputInfo{ 10224 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10225 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10226 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10227 }, 10228 outputs: []outputInfo{ 10229 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10230 }, 10231 }, 10232 }, 10233 { 10234 name: "ORshiftRAreg", 10235 argLen: 3, 10236 asm: arm.AORR, 10237 reg: regInfo{ 10238 inputs: []inputInfo{ 10239 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10240 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10241 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10242 }, 10243 outputs: []outputInfo{ 10244 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10245 }, 10246 }, 10247 }, 10248 { 10249 name: "XORshiftLLreg", 10250 argLen: 3, 10251 asm: arm.AEOR, 10252 reg: regInfo{ 10253 inputs: []inputInfo{ 10254 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10255 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10256 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10257 }, 10258 outputs: []outputInfo{ 10259 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10260 }, 10261 }, 10262 }, 10263 { 10264 name: "XORshiftRLreg", 10265 argLen: 3, 10266 asm: arm.AEOR, 10267 reg: regInfo{ 10268 inputs: []inputInfo{ 10269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10270 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10271 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10272 }, 10273 outputs: []outputInfo{ 10274 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10275 }, 10276 }, 10277 }, 10278 { 10279 name: "XORshiftRAreg", 10280 argLen: 3, 10281 asm: arm.AEOR, 10282 reg: regInfo{ 10283 inputs: []inputInfo{ 10284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10285 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10286 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10287 }, 10288 outputs: []outputInfo{ 10289 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10290 }, 10291 }, 10292 }, 10293 { 10294 name: "BICshiftLLreg", 10295 argLen: 3, 10296 asm: arm.ABIC, 10297 reg: regInfo{ 10298 inputs: []inputInfo{ 10299 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10300 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10301 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10302 }, 10303 outputs: []outputInfo{ 10304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10305 }, 10306 }, 10307 }, 10308 { 10309 name: "BICshiftRLreg", 10310 argLen: 3, 10311 asm: arm.ABIC, 10312 reg: regInfo{ 10313 inputs: []inputInfo{ 10314 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10315 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10316 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10317 }, 10318 outputs: []outputInfo{ 10319 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10320 }, 10321 }, 10322 }, 10323 { 10324 name: "BICshiftRAreg", 10325 argLen: 3, 10326 asm: arm.ABIC, 10327 reg: regInfo{ 10328 inputs: []inputInfo{ 10329 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10330 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10331 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10332 }, 10333 outputs: []outputInfo{ 10334 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10335 }, 10336 }, 10337 }, 10338 { 10339 name: "MVNshiftLLreg", 10340 argLen: 2, 10341 asm: arm.AMVN, 10342 reg: regInfo{ 10343 inputs: []inputInfo{ 10344 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10345 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10346 }, 10347 outputs: []outputInfo{ 10348 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10349 }, 10350 }, 10351 }, 10352 { 10353 name: "MVNshiftRLreg", 10354 argLen: 2, 10355 asm: arm.AMVN, 10356 reg: regInfo{ 10357 inputs: []inputInfo{ 10358 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10359 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10360 }, 10361 outputs: []outputInfo{ 10362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10363 }, 10364 }, 10365 }, 10366 { 10367 name: "MVNshiftRAreg", 10368 argLen: 2, 10369 asm: arm.AMVN, 10370 reg: regInfo{ 10371 inputs: []inputInfo{ 10372 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10373 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10374 }, 10375 outputs: []outputInfo{ 10376 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10377 }, 10378 }, 10379 }, 10380 { 10381 name: "ADCshiftLLreg", 10382 argLen: 4, 10383 asm: arm.AADC, 10384 reg: regInfo{ 10385 inputs: []inputInfo{ 10386 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10387 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10388 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10389 }, 10390 outputs: []outputInfo{ 10391 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10392 }, 10393 }, 10394 }, 10395 { 10396 name: "ADCshiftRLreg", 10397 argLen: 4, 10398 asm: arm.AADC, 10399 reg: regInfo{ 10400 inputs: []inputInfo{ 10401 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10402 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10403 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10404 }, 10405 outputs: []outputInfo{ 10406 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10407 }, 10408 }, 10409 }, 10410 { 10411 name: "ADCshiftRAreg", 10412 argLen: 4, 10413 asm: arm.AADC, 10414 reg: regInfo{ 10415 inputs: []inputInfo{ 10416 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10417 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10418 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10419 }, 10420 outputs: []outputInfo{ 10421 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10422 }, 10423 }, 10424 }, 10425 { 10426 name: "SBCshiftLLreg", 10427 argLen: 4, 10428 asm: arm.ASBC, 10429 reg: regInfo{ 10430 inputs: []inputInfo{ 10431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10432 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10433 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10434 }, 10435 outputs: []outputInfo{ 10436 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10437 }, 10438 }, 10439 }, 10440 { 10441 name: "SBCshiftRLreg", 10442 argLen: 4, 10443 asm: arm.ASBC, 10444 reg: regInfo{ 10445 inputs: []inputInfo{ 10446 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10447 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10448 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10449 }, 10450 outputs: []outputInfo{ 10451 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10452 }, 10453 }, 10454 }, 10455 { 10456 name: "SBCshiftRAreg", 10457 argLen: 4, 10458 asm: arm.ASBC, 10459 reg: regInfo{ 10460 inputs: []inputInfo{ 10461 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10462 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10463 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10464 }, 10465 outputs: []outputInfo{ 10466 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10467 }, 10468 }, 10469 }, 10470 { 10471 name: "RSCshiftLLreg", 10472 argLen: 4, 10473 asm: arm.ARSC, 10474 reg: regInfo{ 10475 inputs: []inputInfo{ 10476 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10477 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10478 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10479 }, 10480 outputs: []outputInfo{ 10481 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10482 }, 10483 }, 10484 }, 10485 { 10486 name: "RSCshiftRLreg", 10487 argLen: 4, 10488 asm: arm.ARSC, 10489 reg: regInfo{ 10490 inputs: []inputInfo{ 10491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10492 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10493 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10494 }, 10495 outputs: []outputInfo{ 10496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10497 }, 10498 }, 10499 }, 10500 { 10501 name: "RSCshiftRAreg", 10502 argLen: 4, 10503 asm: arm.ARSC, 10504 reg: regInfo{ 10505 inputs: []inputInfo{ 10506 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10507 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10508 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10509 }, 10510 outputs: []outputInfo{ 10511 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10512 }, 10513 }, 10514 }, 10515 { 10516 name: "ADDSshiftLLreg", 10517 argLen: 3, 10518 asm: arm.AADD, 10519 reg: regInfo{ 10520 inputs: []inputInfo{ 10521 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10522 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10523 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10524 }, 10525 outputs: []outputInfo{ 10526 {1, 0}, 10527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10528 }, 10529 }, 10530 }, 10531 { 10532 name: "ADDSshiftRLreg", 10533 argLen: 3, 10534 asm: arm.AADD, 10535 reg: regInfo{ 10536 inputs: []inputInfo{ 10537 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10538 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10539 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10540 }, 10541 outputs: []outputInfo{ 10542 {1, 0}, 10543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10544 }, 10545 }, 10546 }, 10547 { 10548 name: "ADDSshiftRAreg", 10549 argLen: 3, 10550 asm: arm.AADD, 10551 reg: regInfo{ 10552 inputs: []inputInfo{ 10553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10554 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10555 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10556 }, 10557 outputs: []outputInfo{ 10558 {1, 0}, 10559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10560 }, 10561 }, 10562 }, 10563 { 10564 name: "SUBSshiftLLreg", 10565 argLen: 3, 10566 asm: arm.ASUB, 10567 reg: regInfo{ 10568 inputs: []inputInfo{ 10569 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10570 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10571 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10572 }, 10573 outputs: []outputInfo{ 10574 {1, 0}, 10575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10576 }, 10577 }, 10578 }, 10579 { 10580 name: "SUBSshiftRLreg", 10581 argLen: 3, 10582 asm: arm.ASUB, 10583 reg: regInfo{ 10584 inputs: []inputInfo{ 10585 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10586 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10587 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10588 }, 10589 outputs: []outputInfo{ 10590 {1, 0}, 10591 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10592 }, 10593 }, 10594 }, 10595 { 10596 name: "SUBSshiftRAreg", 10597 argLen: 3, 10598 asm: arm.ASUB, 10599 reg: regInfo{ 10600 inputs: []inputInfo{ 10601 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10602 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10603 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10604 }, 10605 outputs: []outputInfo{ 10606 {1, 0}, 10607 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10608 }, 10609 }, 10610 }, 10611 { 10612 name: "RSBSshiftLLreg", 10613 argLen: 3, 10614 asm: arm.ARSB, 10615 reg: regInfo{ 10616 inputs: []inputInfo{ 10617 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10618 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10619 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10620 }, 10621 outputs: []outputInfo{ 10622 {1, 0}, 10623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10624 }, 10625 }, 10626 }, 10627 { 10628 name: "RSBSshiftRLreg", 10629 argLen: 3, 10630 asm: arm.ARSB, 10631 reg: regInfo{ 10632 inputs: []inputInfo{ 10633 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10635 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10636 }, 10637 outputs: []outputInfo{ 10638 {1, 0}, 10639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10640 }, 10641 }, 10642 }, 10643 { 10644 name: "RSBSshiftRAreg", 10645 argLen: 3, 10646 asm: arm.ARSB, 10647 reg: regInfo{ 10648 inputs: []inputInfo{ 10649 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10650 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10651 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10652 }, 10653 outputs: []outputInfo{ 10654 {1, 0}, 10655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10656 }, 10657 }, 10658 }, 10659 { 10660 name: "CMP", 10661 argLen: 2, 10662 asm: arm.ACMP, 10663 reg: regInfo{ 10664 inputs: []inputInfo{ 10665 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10666 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10667 }, 10668 }, 10669 }, 10670 { 10671 name: "CMPconst", 10672 auxType: auxInt32, 10673 argLen: 1, 10674 asm: arm.ACMP, 10675 reg: regInfo{ 10676 inputs: []inputInfo{ 10677 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10678 }, 10679 }, 10680 }, 10681 { 10682 name: "CMN", 10683 argLen: 2, 10684 commutative: true, 10685 asm: arm.ACMN, 10686 reg: regInfo{ 10687 inputs: []inputInfo{ 10688 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10689 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10690 }, 10691 }, 10692 }, 10693 { 10694 name: "CMNconst", 10695 auxType: auxInt32, 10696 argLen: 1, 10697 asm: arm.ACMN, 10698 reg: regInfo{ 10699 inputs: []inputInfo{ 10700 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10701 }, 10702 }, 10703 }, 10704 { 10705 name: "TST", 10706 argLen: 2, 10707 commutative: true, 10708 asm: arm.ATST, 10709 reg: regInfo{ 10710 inputs: []inputInfo{ 10711 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10712 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10713 }, 10714 }, 10715 }, 10716 { 10717 name: "TSTconst", 10718 auxType: auxInt32, 10719 argLen: 1, 10720 asm: arm.ATST, 10721 reg: regInfo{ 10722 inputs: []inputInfo{ 10723 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10724 }, 10725 }, 10726 }, 10727 { 10728 name: "TEQ", 10729 argLen: 2, 10730 commutative: true, 10731 asm: arm.ATEQ, 10732 reg: regInfo{ 10733 inputs: []inputInfo{ 10734 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10735 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10736 }, 10737 }, 10738 }, 10739 { 10740 name: "TEQconst", 10741 auxType: auxInt32, 10742 argLen: 1, 10743 asm: arm.ATEQ, 10744 reg: regInfo{ 10745 inputs: []inputInfo{ 10746 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10747 }, 10748 }, 10749 }, 10750 { 10751 name: "CMPF", 10752 argLen: 2, 10753 asm: arm.ACMPF, 10754 reg: regInfo{ 10755 inputs: []inputInfo{ 10756 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10757 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10758 }, 10759 }, 10760 }, 10761 { 10762 name: "CMPD", 10763 argLen: 2, 10764 asm: arm.ACMPD, 10765 reg: regInfo{ 10766 inputs: []inputInfo{ 10767 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10768 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10769 }, 10770 }, 10771 }, 10772 { 10773 name: "CMPshiftLL", 10774 auxType: auxInt32, 10775 argLen: 2, 10776 asm: arm.ACMP, 10777 reg: regInfo{ 10778 inputs: []inputInfo{ 10779 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10780 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10781 }, 10782 }, 10783 }, 10784 { 10785 name: "CMPshiftRL", 10786 auxType: auxInt32, 10787 argLen: 2, 10788 asm: arm.ACMP, 10789 reg: regInfo{ 10790 inputs: []inputInfo{ 10791 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10792 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10793 }, 10794 }, 10795 }, 10796 { 10797 name: "CMPshiftRA", 10798 auxType: auxInt32, 10799 argLen: 2, 10800 asm: arm.ACMP, 10801 reg: regInfo{ 10802 inputs: []inputInfo{ 10803 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10804 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10805 }, 10806 }, 10807 }, 10808 { 10809 name: "CMNshiftLL", 10810 auxType: auxInt32, 10811 argLen: 2, 10812 asm: arm.ACMN, 10813 reg: regInfo{ 10814 inputs: []inputInfo{ 10815 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10816 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10817 }, 10818 }, 10819 }, 10820 { 10821 name: "CMNshiftRL", 10822 auxType: auxInt32, 10823 argLen: 2, 10824 asm: arm.ACMN, 10825 reg: regInfo{ 10826 inputs: []inputInfo{ 10827 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10828 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10829 }, 10830 }, 10831 }, 10832 { 10833 name: "CMNshiftRA", 10834 auxType: auxInt32, 10835 argLen: 2, 10836 asm: arm.ACMN, 10837 reg: regInfo{ 10838 inputs: []inputInfo{ 10839 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10840 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10841 }, 10842 }, 10843 }, 10844 { 10845 name: "TSTshiftLL", 10846 auxType: auxInt32, 10847 argLen: 2, 10848 asm: arm.ATST, 10849 reg: regInfo{ 10850 inputs: []inputInfo{ 10851 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10852 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10853 }, 10854 }, 10855 }, 10856 { 10857 name: "TSTshiftRL", 10858 auxType: auxInt32, 10859 argLen: 2, 10860 asm: arm.ATST, 10861 reg: regInfo{ 10862 inputs: []inputInfo{ 10863 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10864 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10865 }, 10866 }, 10867 }, 10868 { 10869 name: "TSTshiftRA", 10870 auxType: auxInt32, 10871 argLen: 2, 10872 asm: arm.ATST, 10873 reg: regInfo{ 10874 inputs: []inputInfo{ 10875 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10876 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10877 }, 10878 }, 10879 }, 10880 { 10881 name: "TEQshiftLL", 10882 auxType: auxInt32, 10883 argLen: 2, 10884 asm: arm.ATEQ, 10885 reg: regInfo{ 10886 inputs: []inputInfo{ 10887 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10888 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10889 }, 10890 }, 10891 }, 10892 { 10893 name: "TEQshiftRL", 10894 auxType: auxInt32, 10895 argLen: 2, 10896 asm: arm.ATEQ, 10897 reg: regInfo{ 10898 inputs: []inputInfo{ 10899 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10900 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10901 }, 10902 }, 10903 }, 10904 { 10905 name: "TEQshiftRA", 10906 auxType: auxInt32, 10907 argLen: 2, 10908 asm: arm.ATEQ, 10909 reg: regInfo{ 10910 inputs: []inputInfo{ 10911 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10912 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10913 }, 10914 }, 10915 }, 10916 { 10917 name: "CMPshiftLLreg", 10918 argLen: 3, 10919 asm: arm.ACMP, 10920 reg: regInfo{ 10921 inputs: []inputInfo{ 10922 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10923 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10924 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10925 }, 10926 }, 10927 }, 10928 { 10929 name: "CMPshiftRLreg", 10930 argLen: 3, 10931 asm: arm.ACMP, 10932 reg: regInfo{ 10933 inputs: []inputInfo{ 10934 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10935 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10936 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10937 }, 10938 }, 10939 }, 10940 { 10941 name: "CMPshiftRAreg", 10942 argLen: 3, 10943 asm: arm.ACMP, 10944 reg: regInfo{ 10945 inputs: []inputInfo{ 10946 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10947 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10948 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10949 }, 10950 }, 10951 }, 10952 { 10953 name: "CMNshiftLLreg", 10954 argLen: 3, 10955 asm: arm.ACMN, 10956 reg: regInfo{ 10957 inputs: []inputInfo{ 10958 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10959 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10960 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10961 }, 10962 }, 10963 }, 10964 { 10965 name: "CMNshiftRLreg", 10966 argLen: 3, 10967 asm: arm.ACMN, 10968 reg: regInfo{ 10969 inputs: []inputInfo{ 10970 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10971 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10972 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10973 }, 10974 }, 10975 }, 10976 { 10977 name: "CMNshiftRAreg", 10978 argLen: 3, 10979 asm: arm.ACMN, 10980 reg: regInfo{ 10981 inputs: []inputInfo{ 10982 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10983 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10984 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10985 }, 10986 }, 10987 }, 10988 { 10989 name: "TSTshiftLLreg", 10990 argLen: 3, 10991 asm: arm.ATST, 10992 reg: regInfo{ 10993 inputs: []inputInfo{ 10994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10995 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10996 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10997 }, 10998 }, 10999 }, 11000 { 11001 name: "TSTshiftRLreg", 11002 argLen: 3, 11003 asm: arm.ATST, 11004 reg: regInfo{ 11005 inputs: []inputInfo{ 11006 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11007 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11008 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11009 }, 11010 }, 11011 }, 11012 { 11013 name: "TSTshiftRAreg", 11014 argLen: 3, 11015 asm: arm.ATST, 11016 reg: regInfo{ 11017 inputs: []inputInfo{ 11018 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11019 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11020 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11021 }, 11022 }, 11023 }, 11024 { 11025 name: "TEQshiftLLreg", 11026 argLen: 3, 11027 asm: arm.ATEQ, 11028 reg: regInfo{ 11029 inputs: []inputInfo{ 11030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11031 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11032 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11033 }, 11034 }, 11035 }, 11036 { 11037 name: "TEQshiftRLreg", 11038 argLen: 3, 11039 asm: arm.ATEQ, 11040 reg: regInfo{ 11041 inputs: []inputInfo{ 11042 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11043 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11044 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11045 }, 11046 }, 11047 }, 11048 { 11049 name: "TEQshiftRAreg", 11050 argLen: 3, 11051 asm: arm.ATEQ, 11052 reg: regInfo{ 11053 inputs: []inputInfo{ 11054 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11055 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11056 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11057 }, 11058 }, 11059 }, 11060 { 11061 name: "CMPF0", 11062 argLen: 1, 11063 asm: arm.ACMPF, 11064 reg: regInfo{ 11065 inputs: []inputInfo{ 11066 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11067 }, 11068 }, 11069 }, 11070 { 11071 name: "CMPD0", 11072 argLen: 1, 11073 asm: arm.ACMPD, 11074 reg: regInfo{ 11075 inputs: []inputInfo{ 11076 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11077 }, 11078 }, 11079 }, 11080 { 11081 name: "MOVWconst", 11082 auxType: auxInt32, 11083 argLen: 0, 11084 rematerializeable: true, 11085 asm: arm.AMOVW, 11086 reg: regInfo{ 11087 outputs: []outputInfo{ 11088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11089 }, 11090 }, 11091 }, 11092 { 11093 name: "MOVFconst", 11094 auxType: auxFloat64, 11095 argLen: 0, 11096 rematerializeable: true, 11097 asm: arm.AMOVF, 11098 reg: regInfo{ 11099 outputs: []outputInfo{ 11100 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11101 }, 11102 }, 11103 }, 11104 { 11105 name: "MOVDconst", 11106 auxType: auxFloat64, 11107 argLen: 0, 11108 rematerializeable: true, 11109 asm: arm.AMOVD, 11110 reg: regInfo{ 11111 outputs: []outputInfo{ 11112 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11113 }, 11114 }, 11115 }, 11116 { 11117 name: "MOVWaddr", 11118 auxType: auxSymOff, 11119 argLen: 1, 11120 rematerializeable: true, 11121 symEffect: SymAddr, 11122 asm: arm.AMOVW, 11123 reg: regInfo{ 11124 inputs: []inputInfo{ 11125 {0, 4294975488}, // SP SB 11126 }, 11127 outputs: []outputInfo{ 11128 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11129 }, 11130 }, 11131 }, 11132 { 11133 name: "MOVBload", 11134 auxType: auxSymOff, 11135 argLen: 2, 11136 faultOnNilArg0: true, 11137 symEffect: SymRead, 11138 asm: arm.AMOVB, 11139 reg: regInfo{ 11140 inputs: []inputInfo{ 11141 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11142 }, 11143 outputs: []outputInfo{ 11144 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11145 }, 11146 }, 11147 }, 11148 { 11149 name: "MOVBUload", 11150 auxType: auxSymOff, 11151 argLen: 2, 11152 faultOnNilArg0: true, 11153 symEffect: SymRead, 11154 asm: arm.AMOVBU, 11155 reg: regInfo{ 11156 inputs: []inputInfo{ 11157 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11158 }, 11159 outputs: []outputInfo{ 11160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11161 }, 11162 }, 11163 }, 11164 { 11165 name: "MOVHload", 11166 auxType: auxSymOff, 11167 argLen: 2, 11168 faultOnNilArg0: true, 11169 symEffect: SymRead, 11170 asm: arm.AMOVH, 11171 reg: regInfo{ 11172 inputs: []inputInfo{ 11173 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11174 }, 11175 outputs: []outputInfo{ 11176 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11177 }, 11178 }, 11179 }, 11180 { 11181 name: "MOVHUload", 11182 auxType: auxSymOff, 11183 argLen: 2, 11184 faultOnNilArg0: true, 11185 symEffect: SymRead, 11186 asm: arm.AMOVHU, 11187 reg: regInfo{ 11188 inputs: []inputInfo{ 11189 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11190 }, 11191 outputs: []outputInfo{ 11192 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11193 }, 11194 }, 11195 }, 11196 { 11197 name: "MOVWload", 11198 auxType: auxSymOff, 11199 argLen: 2, 11200 faultOnNilArg0: true, 11201 symEffect: SymRead, 11202 asm: arm.AMOVW, 11203 reg: regInfo{ 11204 inputs: []inputInfo{ 11205 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11206 }, 11207 outputs: []outputInfo{ 11208 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11209 }, 11210 }, 11211 }, 11212 { 11213 name: "MOVFload", 11214 auxType: auxSymOff, 11215 argLen: 2, 11216 faultOnNilArg0: true, 11217 symEffect: SymRead, 11218 asm: arm.AMOVF, 11219 reg: regInfo{ 11220 inputs: []inputInfo{ 11221 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11222 }, 11223 outputs: []outputInfo{ 11224 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11225 }, 11226 }, 11227 }, 11228 { 11229 name: "MOVDload", 11230 auxType: auxSymOff, 11231 argLen: 2, 11232 faultOnNilArg0: true, 11233 symEffect: SymRead, 11234 asm: arm.AMOVD, 11235 reg: regInfo{ 11236 inputs: []inputInfo{ 11237 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11238 }, 11239 outputs: []outputInfo{ 11240 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11241 }, 11242 }, 11243 }, 11244 { 11245 name: "MOVBstore", 11246 auxType: auxSymOff, 11247 argLen: 3, 11248 faultOnNilArg0: true, 11249 symEffect: SymWrite, 11250 asm: arm.AMOVB, 11251 reg: regInfo{ 11252 inputs: []inputInfo{ 11253 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11254 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11255 }, 11256 }, 11257 }, 11258 { 11259 name: "MOVHstore", 11260 auxType: auxSymOff, 11261 argLen: 3, 11262 faultOnNilArg0: true, 11263 symEffect: SymWrite, 11264 asm: arm.AMOVH, 11265 reg: regInfo{ 11266 inputs: []inputInfo{ 11267 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11268 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11269 }, 11270 }, 11271 }, 11272 { 11273 name: "MOVWstore", 11274 auxType: auxSymOff, 11275 argLen: 3, 11276 faultOnNilArg0: true, 11277 symEffect: SymWrite, 11278 asm: arm.AMOVW, 11279 reg: regInfo{ 11280 inputs: []inputInfo{ 11281 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11282 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11283 }, 11284 }, 11285 }, 11286 { 11287 name: "MOVFstore", 11288 auxType: auxSymOff, 11289 argLen: 3, 11290 faultOnNilArg0: true, 11291 symEffect: SymWrite, 11292 asm: arm.AMOVF, 11293 reg: regInfo{ 11294 inputs: []inputInfo{ 11295 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11296 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11297 }, 11298 }, 11299 }, 11300 { 11301 name: "MOVDstore", 11302 auxType: auxSymOff, 11303 argLen: 3, 11304 faultOnNilArg0: true, 11305 symEffect: SymWrite, 11306 asm: arm.AMOVD, 11307 reg: regInfo{ 11308 inputs: []inputInfo{ 11309 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11310 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11311 }, 11312 }, 11313 }, 11314 { 11315 name: "MOVWloadidx", 11316 argLen: 3, 11317 asm: arm.AMOVW, 11318 reg: regInfo{ 11319 inputs: []inputInfo{ 11320 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11321 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11322 }, 11323 outputs: []outputInfo{ 11324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11325 }, 11326 }, 11327 }, 11328 { 11329 name: "MOVWloadshiftLL", 11330 auxType: auxInt32, 11331 argLen: 3, 11332 asm: arm.AMOVW, 11333 reg: regInfo{ 11334 inputs: []inputInfo{ 11335 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11336 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11337 }, 11338 outputs: []outputInfo{ 11339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11340 }, 11341 }, 11342 }, 11343 { 11344 name: "MOVWloadshiftRL", 11345 auxType: auxInt32, 11346 argLen: 3, 11347 asm: arm.AMOVW, 11348 reg: regInfo{ 11349 inputs: []inputInfo{ 11350 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11351 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11352 }, 11353 outputs: []outputInfo{ 11354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11355 }, 11356 }, 11357 }, 11358 { 11359 name: "MOVWloadshiftRA", 11360 auxType: auxInt32, 11361 argLen: 3, 11362 asm: arm.AMOVW, 11363 reg: regInfo{ 11364 inputs: []inputInfo{ 11365 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11366 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11367 }, 11368 outputs: []outputInfo{ 11369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11370 }, 11371 }, 11372 }, 11373 { 11374 name: "MOVBUloadidx", 11375 argLen: 3, 11376 asm: arm.AMOVBU, 11377 reg: regInfo{ 11378 inputs: []inputInfo{ 11379 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11380 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11381 }, 11382 outputs: []outputInfo{ 11383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11384 }, 11385 }, 11386 }, 11387 { 11388 name: "MOVBloadidx", 11389 argLen: 3, 11390 asm: arm.AMOVB, 11391 reg: regInfo{ 11392 inputs: []inputInfo{ 11393 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11394 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11395 }, 11396 outputs: []outputInfo{ 11397 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11398 }, 11399 }, 11400 }, 11401 { 11402 name: "MOVHUloadidx", 11403 argLen: 3, 11404 asm: arm.AMOVHU, 11405 reg: regInfo{ 11406 inputs: []inputInfo{ 11407 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11408 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11409 }, 11410 outputs: []outputInfo{ 11411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11412 }, 11413 }, 11414 }, 11415 { 11416 name: "MOVHloadidx", 11417 argLen: 3, 11418 asm: arm.AMOVH, 11419 reg: regInfo{ 11420 inputs: []inputInfo{ 11421 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11422 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11423 }, 11424 outputs: []outputInfo{ 11425 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11426 }, 11427 }, 11428 }, 11429 { 11430 name: "MOVWstoreidx", 11431 argLen: 4, 11432 asm: arm.AMOVW, 11433 reg: regInfo{ 11434 inputs: []inputInfo{ 11435 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11436 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11437 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11438 }, 11439 }, 11440 }, 11441 { 11442 name: "MOVWstoreshiftLL", 11443 auxType: auxInt32, 11444 argLen: 4, 11445 asm: arm.AMOVW, 11446 reg: regInfo{ 11447 inputs: []inputInfo{ 11448 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11449 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11450 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11451 }, 11452 }, 11453 }, 11454 { 11455 name: "MOVWstoreshiftRL", 11456 auxType: auxInt32, 11457 argLen: 4, 11458 asm: arm.AMOVW, 11459 reg: regInfo{ 11460 inputs: []inputInfo{ 11461 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11462 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11463 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11464 }, 11465 }, 11466 }, 11467 { 11468 name: "MOVWstoreshiftRA", 11469 auxType: auxInt32, 11470 argLen: 4, 11471 asm: arm.AMOVW, 11472 reg: regInfo{ 11473 inputs: []inputInfo{ 11474 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11475 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11476 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11477 }, 11478 }, 11479 }, 11480 { 11481 name: "MOVBstoreidx", 11482 argLen: 4, 11483 asm: arm.AMOVB, 11484 reg: regInfo{ 11485 inputs: []inputInfo{ 11486 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11487 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11488 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11489 }, 11490 }, 11491 }, 11492 { 11493 name: "MOVHstoreidx", 11494 argLen: 4, 11495 asm: arm.AMOVH, 11496 reg: regInfo{ 11497 inputs: []inputInfo{ 11498 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11499 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11500 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11501 }, 11502 }, 11503 }, 11504 { 11505 name: "MOVBreg", 11506 argLen: 1, 11507 asm: arm.AMOVBS, 11508 reg: regInfo{ 11509 inputs: []inputInfo{ 11510 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11511 }, 11512 outputs: []outputInfo{ 11513 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11514 }, 11515 }, 11516 }, 11517 { 11518 name: "MOVBUreg", 11519 argLen: 1, 11520 asm: arm.AMOVBU, 11521 reg: regInfo{ 11522 inputs: []inputInfo{ 11523 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11524 }, 11525 outputs: []outputInfo{ 11526 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11527 }, 11528 }, 11529 }, 11530 { 11531 name: "MOVHreg", 11532 argLen: 1, 11533 asm: arm.AMOVHS, 11534 reg: regInfo{ 11535 inputs: []inputInfo{ 11536 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11537 }, 11538 outputs: []outputInfo{ 11539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11540 }, 11541 }, 11542 }, 11543 { 11544 name: "MOVHUreg", 11545 argLen: 1, 11546 asm: arm.AMOVHU, 11547 reg: regInfo{ 11548 inputs: []inputInfo{ 11549 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11550 }, 11551 outputs: []outputInfo{ 11552 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11553 }, 11554 }, 11555 }, 11556 { 11557 name: "MOVWreg", 11558 argLen: 1, 11559 asm: arm.AMOVW, 11560 reg: regInfo{ 11561 inputs: []inputInfo{ 11562 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11563 }, 11564 outputs: []outputInfo{ 11565 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11566 }, 11567 }, 11568 }, 11569 { 11570 name: "MOVWnop", 11571 argLen: 1, 11572 resultInArg0: true, 11573 reg: regInfo{ 11574 inputs: []inputInfo{ 11575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11576 }, 11577 outputs: []outputInfo{ 11578 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11579 }, 11580 }, 11581 }, 11582 { 11583 name: "MOVWF", 11584 argLen: 1, 11585 asm: arm.AMOVWF, 11586 reg: regInfo{ 11587 inputs: []inputInfo{ 11588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11589 }, 11590 clobbers: 2147483648, // F15 11591 outputs: []outputInfo{ 11592 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11593 }, 11594 }, 11595 }, 11596 { 11597 name: "MOVWD", 11598 argLen: 1, 11599 asm: arm.AMOVWD, 11600 reg: regInfo{ 11601 inputs: []inputInfo{ 11602 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11603 }, 11604 clobbers: 2147483648, // F15 11605 outputs: []outputInfo{ 11606 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11607 }, 11608 }, 11609 }, 11610 { 11611 name: "MOVWUF", 11612 argLen: 1, 11613 asm: arm.AMOVWF, 11614 reg: regInfo{ 11615 inputs: []inputInfo{ 11616 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11617 }, 11618 clobbers: 2147483648, // F15 11619 outputs: []outputInfo{ 11620 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11621 }, 11622 }, 11623 }, 11624 { 11625 name: "MOVWUD", 11626 argLen: 1, 11627 asm: arm.AMOVWD, 11628 reg: regInfo{ 11629 inputs: []inputInfo{ 11630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11631 }, 11632 clobbers: 2147483648, // F15 11633 outputs: []outputInfo{ 11634 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11635 }, 11636 }, 11637 }, 11638 { 11639 name: "MOVFW", 11640 argLen: 1, 11641 asm: arm.AMOVFW, 11642 reg: regInfo{ 11643 inputs: []inputInfo{ 11644 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11645 }, 11646 clobbers: 2147483648, // F15 11647 outputs: []outputInfo{ 11648 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11649 }, 11650 }, 11651 }, 11652 { 11653 name: "MOVDW", 11654 argLen: 1, 11655 asm: arm.AMOVDW, 11656 reg: regInfo{ 11657 inputs: []inputInfo{ 11658 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11659 }, 11660 clobbers: 2147483648, // F15 11661 outputs: []outputInfo{ 11662 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11663 }, 11664 }, 11665 }, 11666 { 11667 name: "MOVFWU", 11668 argLen: 1, 11669 asm: arm.AMOVFW, 11670 reg: regInfo{ 11671 inputs: []inputInfo{ 11672 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11673 }, 11674 clobbers: 2147483648, // F15 11675 outputs: []outputInfo{ 11676 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11677 }, 11678 }, 11679 }, 11680 { 11681 name: "MOVDWU", 11682 argLen: 1, 11683 asm: arm.AMOVDW, 11684 reg: regInfo{ 11685 inputs: []inputInfo{ 11686 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11687 }, 11688 clobbers: 2147483648, // F15 11689 outputs: []outputInfo{ 11690 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11691 }, 11692 }, 11693 }, 11694 { 11695 name: "MOVFD", 11696 argLen: 1, 11697 asm: arm.AMOVFD, 11698 reg: regInfo{ 11699 inputs: []inputInfo{ 11700 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11701 }, 11702 outputs: []outputInfo{ 11703 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11704 }, 11705 }, 11706 }, 11707 { 11708 name: "MOVDF", 11709 argLen: 1, 11710 asm: arm.AMOVDF, 11711 reg: regInfo{ 11712 inputs: []inputInfo{ 11713 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "CMOVWHSconst", 11722 auxType: auxInt32, 11723 argLen: 2, 11724 resultInArg0: true, 11725 asm: arm.AMOVW, 11726 reg: regInfo{ 11727 inputs: []inputInfo{ 11728 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11729 }, 11730 outputs: []outputInfo{ 11731 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11732 }, 11733 }, 11734 }, 11735 { 11736 name: "CMOVWLSconst", 11737 auxType: auxInt32, 11738 argLen: 2, 11739 resultInArg0: true, 11740 asm: arm.AMOVW, 11741 reg: regInfo{ 11742 inputs: []inputInfo{ 11743 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11744 }, 11745 outputs: []outputInfo{ 11746 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11747 }, 11748 }, 11749 }, 11750 { 11751 name: "SRAcond", 11752 argLen: 3, 11753 asm: arm.ASRA, 11754 reg: regInfo{ 11755 inputs: []inputInfo{ 11756 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11757 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11758 }, 11759 outputs: []outputInfo{ 11760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11761 }, 11762 }, 11763 }, 11764 { 11765 name: "CALLstatic", 11766 auxType: auxSymOff, 11767 argLen: 1, 11768 clobberFlags: true, 11769 call: true, 11770 symEffect: SymNone, 11771 reg: regInfo{ 11772 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11773 }, 11774 }, 11775 { 11776 name: "CALLclosure", 11777 auxType: auxInt64, 11778 argLen: 3, 11779 clobberFlags: true, 11780 call: true, 11781 reg: regInfo{ 11782 inputs: []inputInfo{ 11783 {1, 128}, // R7 11784 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 11785 }, 11786 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11787 }, 11788 }, 11789 { 11790 name: "CALLinter", 11791 auxType: auxInt64, 11792 argLen: 2, 11793 clobberFlags: true, 11794 call: true, 11795 reg: regInfo{ 11796 inputs: []inputInfo{ 11797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11798 }, 11799 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11800 }, 11801 }, 11802 { 11803 name: "LoweredNilCheck", 11804 argLen: 2, 11805 nilCheck: true, 11806 faultOnNilArg0: true, 11807 reg: regInfo{ 11808 inputs: []inputInfo{ 11809 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11810 }, 11811 }, 11812 }, 11813 { 11814 name: "Equal", 11815 argLen: 1, 11816 reg: regInfo{ 11817 outputs: []outputInfo{ 11818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11819 }, 11820 }, 11821 }, 11822 { 11823 name: "NotEqual", 11824 argLen: 1, 11825 reg: regInfo{ 11826 outputs: []outputInfo{ 11827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11828 }, 11829 }, 11830 }, 11831 { 11832 name: "LessThan", 11833 argLen: 1, 11834 reg: regInfo{ 11835 outputs: []outputInfo{ 11836 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11837 }, 11838 }, 11839 }, 11840 { 11841 name: "LessEqual", 11842 argLen: 1, 11843 reg: regInfo{ 11844 outputs: []outputInfo{ 11845 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11846 }, 11847 }, 11848 }, 11849 { 11850 name: "GreaterThan", 11851 argLen: 1, 11852 reg: regInfo{ 11853 outputs: []outputInfo{ 11854 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11855 }, 11856 }, 11857 }, 11858 { 11859 name: "GreaterEqual", 11860 argLen: 1, 11861 reg: regInfo{ 11862 outputs: []outputInfo{ 11863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11864 }, 11865 }, 11866 }, 11867 { 11868 name: "LessThanU", 11869 argLen: 1, 11870 reg: regInfo{ 11871 outputs: []outputInfo{ 11872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11873 }, 11874 }, 11875 }, 11876 { 11877 name: "LessEqualU", 11878 argLen: 1, 11879 reg: regInfo{ 11880 outputs: []outputInfo{ 11881 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11882 }, 11883 }, 11884 }, 11885 { 11886 name: "GreaterThanU", 11887 argLen: 1, 11888 reg: regInfo{ 11889 outputs: []outputInfo{ 11890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11891 }, 11892 }, 11893 }, 11894 { 11895 name: "GreaterEqualU", 11896 argLen: 1, 11897 reg: regInfo{ 11898 outputs: []outputInfo{ 11899 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11900 }, 11901 }, 11902 }, 11903 { 11904 name: "DUFFZERO", 11905 auxType: auxInt64, 11906 argLen: 3, 11907 faultOnNilArg0: true, 11908 reg: regInfo{ 11909 inputs: []inputInfo{ 11910 {0, 2}, // R1 11911 {1, 1}, // R0 11912 }, 11913 clobbers: 16386, // R1 R14 11914 }, 11915 }, 11916 { 11917 name: "DUFFCOPY", 11918 auxType: auxInt64, 11919 argLen: 3, 11920 faultOnNilArg0: true, 11921 faultOnNilArg1: true, 11922 reg: regInfo{ 11923 inputs: []inputInfo{ 11924 {0, 4}, // R2 11925 {1, 2}, // R1 11926 }, 11927 clobbers: 16391, // R0 R1 R2 R14 11928 }, 11929 }, 11930 { 11931 name: "LoweredZero", 11932 auxType: auxInt64, 11933 argLen: 4, 11934 clobberFlags: true, 11935 faultOnNilArg0: true, 11936 reg: regInfo{ 11937 inputs: []inputInfo{ 11938 {0, 2}, // R1 11939 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11940 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11941 }, 11942 clobbers: 2, // R1 11943 }, 11944 }, 11945 { 11946 name: "LoweredMove", 11947 auxType: auxInt64, 11948 argLen: 4, 11949 clobberFlags: true, 11950 faultOnNilArg0: true, 11951 faultOnNilArg1: true, 11952 reg: regInfo{ 11953 inputs: []inputInfo{ 11954 {0, 4}, // R2 11955 {1, 2}, // R1 11956 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11957 }, 11958 clobbers: 6, // R1 R2 11959 }, 11960 }, 11961 { 11962 name: "LoweredGetClosurePtr", 11963 argLen: 0, 11964 reg: regInfo{ 11965 outputs: []outputInfo{ 11966 {0, 128}, // R7 11967 }, 11968 }, 11969 }, 11970 { 11971 name: "LoweredGetCallerSP", 11972 argLen: 0, 11973 rematerializeable: true, 11974 reg: regInfo{ 11975 outputs: []outputInfo{ 11976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11977 }, 11978 }, 11979 }, 11980 { 11981 name: "MOVWconvert", 11982 argLen: 2, 11983 asm: arm.AMOVW, 11984 reg: regInfo{ 11985 inputs: []inputInfo{ 11986 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11987 }, 11988 outputs: []outputInfo{ 11989 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11990 }, 11991 }, 11992 }, 11993 { 11994 name: "FlagEQ", 11995 argLen: 0, 11996 reg: regInfo{}, 11997 }, 11998 { 11999 name: "FlagLT_ULT", 12000 argLen: 0, 12001 reg: regInfo{}, 12002 }, 12003 { 12004 name: "FlagLT_UGT", 12005 argLen: 0, 12006 reg: regInfo{}, 12007 }, 12008 { 12009 name: "FlagGT_UGT", 12010 argLen: 0, 12011 reg: regInfo{}, 12012 }, 12013 { 12014 name: "FlagGT_ULT", 12015 argLen: 0, 12016 reg: regInfo{}, 12017 }, 12018 { 12019 name: "InvertFlags", 12020 argLen: 1, 12021 reg: regInfo{}, 12022 }, 12023 { 12024 name: "LoweredWB", 12025 auxType: auxSym, 12026 argLen: 3, 12027 clobberFlags: true, 12028 symEffect: SymNone, 12029 reg: regInfo{ 12030 inputs: []inputInfo{ 12031 {0, 4}, // R2 12032 {1, 8}, // R3 12033 }, 12034 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 12035 }, 12036 }, 12037 12038 { 12039 name: "ADD", 12040 argLen: 2, 12041 commutative: true, 12042 asm: arm64.AADD, 12043 reg: regInfo{ 12044 inputs: []inputInfo{ 12045 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12046 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12047 }, 12048 outputs: []outputInfo{ 12049 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12050 }, 12051 }, 12052 }, 12053 { 12054 name: "ADDconst", 12055 auxType: auxInt64, 12056 argLen: 1, 12057 asm: arm64.AADD, 12058 reg: regInfo{ 12059 inputs: []inputInfo{ 12060 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 12061 }, 12062 outputs: []outputInfo{ 12063 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12064 }, 12065 }, 12066 }, 12067 { 12068 name: "SUB", 12069 argLen: 2, 12070 asm: arm64.ASUB, 12071 reg: regInfo{ 12072 inputs: []inputInfo{ 12073 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12074 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12075 }, 12076 outputs: []outputInfo{ 12077 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12078 }, 12079 }, 12080 }, 12081 { 12082 name: "SUBconst", 12083 auxType: auxInt64, 12084 argLen: 1, 12085 asm: arm64.ASUB, 12086 reg: regInfo{ 12087 inputs: []inputInfo{ 12088 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12089 }, 12090 outputs: []outputInfo{ 12091 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12092 }, 12093 }, 12094 }, 12095 { 12096 name: "MUL", 12097 argLen: 2, 12098 commutative: true, 12099 asm: arm64.AMUL, 12100 reg: regInfo{ 12101 inputs: []inputInfo{ 12102 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12103 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12104 }, 12105 outputs: []outputInfo{ 12106 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12107 }, 12108 }, 12109 }, 12110 { 12111 name: "MULW", 12112 argLen: 2, 12113 commutative: true, 12114 asm: arm64.AMULW, 12115 reg: regInfo{ 12116 inputs: []inputInfo{ 12117 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12118 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12119 }, 12120 outputs: []outputInfo{ 12121 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12122 }, 12123 }, 12124 }, 12125 { 12126 name: "MNEG", 12127 argLen: 2, 12128 commutative: true, 12129 asm: arm64.AMNEG, 12130 reg: regInfo{ 12131 inputs: []inputInfo{ 12132 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12133 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12134 }, 12135 outputs: []outputInfo{ 12136 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12137 }, 12138 }, 12139 }, 12140 { 12141 name: "MNEGW", 12142 argLen: 2, 12143 commutative: true, 12144 asm: arm64.AMNEGW, 12145 reg: regInfo{ 12146 inputs: []inputInfo{ 12147 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12148 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12149 }, 12150 outputs: []outputInfo{ 12151 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12152 }, 12153 }, 12154 }, 12155 { 12156 name: "MULH", 12157 argLen: 2, 12158 commutative: true, 12159 asm: arm64.ASMULH, 12160 reg: regInfo{ 12161 inputs: []inputInfo{ 12162 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12163 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12164 }, 12165 outputs: []outputInfo{ 12166 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12167 }, 12168 }, 12169 }, 12170 { 12171 name: "UMULH", 12172 argLen: 2, 12173 commutative: true, 12174 asm: arm64.AUMULH, 12175 reg: regInfo{ 12176 inputs: []inputInfo{ 12177 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12178 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12179 }, 12180 outputs: []outputInfo{ 12181 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12182 }, 12183 }, 12184 }, 12185 { 12186 name: "MULL", 12187 argLen: 2, 12188 commutative: true, 12189 asm: arm64.ASMULL, 12190 reg: regInfo{ 12191 inputs: []inputInfo{ 12192 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12193 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12194 }, 12195 outputs: []outputInfo{ 12196 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12197 }, 12198 }, 12199 }, 12200 { 12201 name: "UMULL", 12202 argLen: 2, 12203 commutative: true, 12204 asm: arm64.AUMULL, 12205 reg: regInfo{ 12206 inputs: []inputInfo{ 12207 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12208 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12209 }, 12210 outputs: []outputInfo{ 12211 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12212 }, 12213 }, 12214 }, 12215 { 12216 name: "DIV", 12217 argLen: 2, 12218 asm: arm64.ASDIV, 12219 reg: regInfo{ 12220 inputs: []inputInfo{ 12221 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12222 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12223 }, 12224 outputs: []outputInfo{ 12225 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12226 }, 12227 }, 12228 }, 12229 { 12230 name: "UDIV", 12231 argLen: 2, 12232 asm: arm64.AUDIV, 12233 reg: regInfo{ 12234 inputs: []inputInfo{ 12235 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12236 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12237 }, 12238 outputs: []outputInfo{ 12239 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12240 }, 12241 }, 12242 }, 12243 { 12244 name: "DIVW", 12245 argLen: 2, 12246 asm: arm64.ASDIVW, 12247 reg: regInfo{ 12248 inputs: []inputInfo{ 12249 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12250 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12251 }, 12252 outputs: []outputInfo{ 12253 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12254 }, 12255 }, 12256 }, 12257 { 12258 name: "UDIVW", 12259 argLen: 2, 12260 asm: arm64.AUDIVW, 12261 reg: regInfo{ 12262 inputs: []inputInfo{ 12263 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12264 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12265 }, 12266 outputs: []outputInfo{ 12267 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12268 }, 12269 }, 12270 }, 12271 { 12272 name: "MOD", 12273 argLen: 2, 12274 asm: arm64.AREM, 12275 reg: regInfo{ 12276 inputs: []inputInfo{ 12277 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12278 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12279 }, 12280 outputs: []outputInfo{ 12281 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12282 }, 12283 }, 12284 }, 12285 { 12286 name: "UMOD", 12287 argLen: 2, 12288 asm: arm64.AUREM, 12289 reg: regInfo{ 12290 inputs: []inputInfo{ 12291 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12292 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12293 }, 12294 outputs: []outputInfo{ 12295 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12296 }, 12297 }, 12298 }, 12299 { 12300 name: "MODW", 12301 argLen: 2, 12302 asm: arm64.AREMW, 12303 reg: regInfo{ 12304 inputs: []inputInfo{ 12305 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12306 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12307 }, 12308 outputs: []outputInfo{ 12309 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12310 }, 12311 }, 12312 }, 12313 { 12314 name: "UMODW", 12315 argLen: 2, 12316 asm: arm64.AUREMW, 12317 reg: regInfo{ 12318 inputs: []inputInfo{ 12319 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12320 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12321 }, 12322 outputs: []outputInfo{ 12323 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12324 }, 12325 }, 12326 }, 12327 { 12328 name: "FADDS", 12329 argLen: 2, 12330 commutative: true, 12331 asm: arm64.AFADDS, 12332 reg: regInfo{ 12333 inputs: []inputInfo{ 12334 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12335 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12336 }, 12337 outputs: []outputInfo{ 12338 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12339 }, 12340 }, 12341 }, 12342 { 12343 name: "FADDD", 12344 argLen: 2, 12345 commutative: true, 12346 asm: arm64.AFADDD, 12347 reg: regInfo{ 12348 inputs: []inputInfo{ 12349 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12350 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12351 }, 12352 outputs: []outputInfo{ 12353 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12354 }, 12355 }, 12356 }, 12357 { 12358 name: "FSUBS", 12359 argLen: 2, 12360 asm: arm64.AFSUBS, 12361 reg: regInfo{ 12362 inputs: []inputInfo{ 12363 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12364 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12365 }, 12366 outputs: []outputInfo{ 12367 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12368 }, 12369 }, 12370 }, 12371 { 12372 name: "FSUBD", 12373 argLen: 2, 12374 asm: arm64.AFSUBD, 12375 reg: regInfo{ 12376 inputs: []inputInfo{ 12377 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12378 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12379 }, 12380 outputs: []outputInfo{ 12381 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12382 }, 12383 }, 12384 }, 12385 { 12386 name: "FMULS", 12387 argLen: 2, 12388 commutative: true, 12389 asm: arm64.AFMULS, 12390 reg: regInfo{ 12391 inputs: []inputInfo{ 12392 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12393 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12394 }, 12395 outputs: []outputInfo{ 12396 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12397 }, 12398 }, 12399 }, 12400 { 12401 name: "FMULD", 12402 argLen: 2, 12403 commutative: true, 12404 asm: arm64.AFMULD, 12405 reg: regInfo{ 12406 inputs: []inputInfo{ 12407 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12408 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12409 }, 12410 outputs: []outputInfo{ 12411 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12412 }, 12413 }, 12414 }, 12415 { 12416 name: "FNMULS", 12417 argLen: 2, 12418 commutative: true, 12419 asm: arm64.AFNMULS, 12420 reg: regInfo{ 12421 inputs: []inputInfo{ 12422 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12423 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12424 }, 12425 outputs: []outputInfo{ 12426 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12427 }, 12428 }, 12429 }, 12430 { 12431 name: "FNMULD", 12432 argLen: 2, 12433 commutative: true, 12434 asm: arm64.AFNMULD, 12435 reg: regInfo{ 12436 inputs: []inputInfo{ 12437 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12438 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12439 }, 12440 outputs: []outputInfo{ 12441 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12442 }, 12443 }, 12444 }, 12445 { 12446 name: "FDIVS", 12447 argLen: 2, 12448 asm: arm64.AFDIVS, 12449 reg: regInfo{ 12450 inputs: []inputInfo{ 12451 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12452 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12453 }, 12454 outputs: []outputInfo{ 12455 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12456 }, 12457 }, 12458 }, 12459 { 12460 name: "FDIVD", 12461 argLen: 2, 12462 asm: arm64.AFDIVD, 12463 reg: regInfo{ 12464 inputs: []inputInfo{ 12465 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12466 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12467 }, 12468 outputs: []outputInfo{ 12469 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12470 }, 12471 }, 12472 }, 12473 { 12474 name: "AND", 12475 argLen: 2, 12476 commutative: true, 12477 asm: arm64.AAND, 12478 reg: regInfo{ 12479 inputs: []inputInfo{ 12480 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12481 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12482 }, 12483 outputs: []outputInfo{ 12484 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12485 }, 12486 }, 12487 }, 12488 { 12489 name: "ANDconst", 12490 auxType: auxInt64, 12491 argLen: 1, 12492 asm: arm64.AAND, 12493 reg: regInfo{ 12494 inputs: []inputInfo{ 12495 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12496 }, 12497 outputs: []outputInfo{ 12498 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12499 }, 12500 }, 12501 }, 12502 { 12503 name: "OR", 12504 argLen: 2, 12505 commutative: true, 12506 asm: arm64.AORR, 12507 reg: regInfo{ 12508 inputs: []inputInfo{ 12509 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12510 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12511 }, 12512 outputs: []outputInfo{ 12513 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12514 }, 12515 }, 12516 }, 12517 { 12518 name: "ORconst", 12519 auxType: auxInt64, 12520 argLen: 1, 12521 asm: arm64.AORR, 12522 reg: regInfo{ 12523 inputs: []inputInfo{ 12524 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12525 }, 12526 outputs: []outputInfo{ 12527 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12528 }, 12529 }, 12530 }, 12531 { 12532 name: "XOR", 12533 argLen: 2, 12534 commutative: true, 12535 asm: arm64.AEOR, 12536 reg: regInfo{ 12537 inputs: []inputInfo{ 12538 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12539 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12540 }, 12541 outputs: []outputInfo{ 12542 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12543 }, 12544 }, 12545 }, 12546 { 12547 name: "XORconst", 12548 auxType: auxInt64, 12549 argLen: 1, 12550 asm: arm64.AEOR, 12551 reg: regInfo{ 12552 inputs: []inputInfo{ 12553 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12554 }, 12555 outputs: []outputInfo{ 12556 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12557 }, 12558 }, 12559 }, 12560 { 12561 name: "BIC", 12562 argLen: 2, 12563 asm: arm64.ABIC, 12564 reg: regInfo{ 12565 inputs: []inputInfo{ 12566 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12567 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12568 }, 12569 outputs: []outputInfo{ 12570 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12571 }, 12572 }, 12573 }, 12574 { 12575 name: "BICconst", 12576 auxType: auxInt64, 12577 argLen: 1, 12578 asm: arm64.ABIC, 12579 reg: regInfo{ 12580 inputs: []inputInfo{ 12581 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12582 }, 12583 outputs: []outputInfo{ 12584 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12585 }, 12586 }, 12587 }, 12588 { 12589 name: "MVN", 12590 argLen: 1, 12591 asm: arm64.AMVN, 12592 reg: regInfo{ 12593 inputs: []inputInfo{ 12594 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12595 }, 12596 outputs: []outputInfo{ 12597 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12598 }, 12599 }, 12600 }, 12601 { 12602 name: "NEG", 12603 argLen: 1, 12604 asm: arm64.ANEG, 12605 reg: regInfo{ 12606 inputs: []inputInfo{ 12607 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12608 }, 12609 outputs: []outputInfo{ 12610 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12611 }, 12612 }, 12613 }, 12614 { 12615 name: "FNEGS", 12616 argLen: 1, 12617 asm: arm64.AFNEGS, 12618 reg: regInfo{ 12619 inputs: []inputInfo{ 12620 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12621 }, 12622 outputs: []outputInfo{ 12623 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12624 }, 12625 }, 12626 }, 12627 { 12628 name: "FNEGD", 12629 argLen: 1, 12630 asm: arm64.AFNEGD, 12631 reg: regInfo{ 12632 inputs: []inputInfo{ 12633 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12634 }, 12635 outputs: []outputInfo{ 12636 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12637 }, 12638 }, 12639 }, 12640 { 12641 name: "FSQRTD", 12642 argLen: 1, 12643 asm: arm64.AFSQRTD, 12644 reg: regInfo{ 12645 inputs: []inputInfo{ 12646 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12647 }, 12648 outputs: []outputInfo{ 12649 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12650 }, 12651 }, 12652 }, 12653 { 12654 name: "REV", 12655 argLen: 1, 12656 asm: arm64.AREV, 12657 reg: regInfo{ 12658 inputs: []inputInfo{ 12659 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12660 }, 12661 outputs: []outputInfo{ 12662 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12663 }, 12664 }, 12665 }, 12666 { 12667 name: "REVW", 12668 argLen: 1, 12669 asm: arm64.AREVW, 12670 reg: regInfo{ 12671 inputs: []inputInfo{ 12672 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12673 }, 12674 outputs: []outputInfo{ 12675 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12676 }, 12677 }, 12678 }, 12679 { 12680 name: "REV16W", 12681 argLen: 1, 12682 asm: arm64.AREV16W, 12683 reg: regInfo{ 12684 inputs: []inputInfo{ 12685 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12686 }, 12687 outputs: []outputInfo{ 12688 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12689 }, 12690 }, 12691 }, 12692 { 12693 name: "RBIT", 12694 argLen: 1, 12695 asm: arm64.ARBIT, 12696 reg: regInfo{ 12697 inputs: []inputInfo{ 12698 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12699 }, 12700 outputs: []outputInfo{ 12701 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12702 }, 12703 }, 12704 }, 12705 { 12706 name: "RBITW", 12707 argLen: 1, 12708 asm: arm64.ARBITW, 12709 reg: regInfo{ 12710 inputs: []inputInfo{ 12711 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12712 }, 12713 outputs: []outputInfo{ 12714 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12715 }, 12716 }, 12717 }, 12718 { 12719 name: "CLZ", 12720 argLen: 1, 12721 asm: arm64.ACLZ, 12722 reg: regInfo{ 12723 inputs: []inputInfo{ 12724 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12725 }, 12726 outputs: []outputInfo{ 12727 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12728 }, 12729 }, 12730 }, 12731 { 12732 name: "CLZW", 12733 argLen: 1, 12734 asm: arm64.ACLZW, 12735 reg: regInfo{ 12736 inputs: []inputInfo{ 12737 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12738 }, 12739 outputs: []outputInfo{ 12740 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12741 }, 12742 }, 12743 }, 12744 { 12745 name: "VCNT", 12746 argLen: 1, 12747 asm: arm64.AVCNT, 12748 reg: regInfo{ 12749 inputs: []inputInfo{ 12750 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12751 }, 12752 outputs: []outputInfo{ 12753 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12754 }, 12755 }, 12756 }, 12757 { 12758 name: "VUADDLV", 12759 argLen: 1, 12760 asm: arm64.AVUADDLV, 12761 reg: regInfo{ 12762 inputs: []inputInfo{ 12763 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12764 }, 12765 outputs: []outputInfo{ 12766 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12767 }, 12768 }, 12769 }, 12770 { 12771 name: "LoweredRound32F", 12772 argLen: 1, 12773 resultInArg0: true, 12774 reg: regInfo{ 12775 inputs: []inputInfo{ 12776 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12777 }, 12778 outputs: []outputInfo{ 12779 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12780 }, 12781 }, 12782 }, 12783 { 12784 name: "LoweredRound64F", 12785 argLen: 1, 12786 resultInArg0: true, 12787 reg: regInfo{ 12788 inputs: []inputInfo{ 12789 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12790 }, 12791 outputs: []outputInfo{ 12792 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12793 }, 12794 }, 12795 }, 12796 { 12797 name: "FMADDS", 12798 argLen: 3, 12799 asm: arm64.AFMADDS, 12800 reg: regInfo{ 12801 inputs: []inputInfo{ 12802 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12803 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12804 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12805 }, 12806 outputs: []outputInfo{ 12807 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12808 }, 12809 }, 12810 }, 12811 { 12812 name: "FMADDD", 12813 argLen: 3, 12814 asm: arm64.AFMADDD, 12815 reg: regInfo{ 12816 inputs: []inputInfo{ 12817 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12818 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12819 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12820 }, 12821 outputs: []outputInfo{ 12822 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12823 }, 12824 }, 12825 }, 12826 { 12827 name: "FNMADDS", 12828 argLen: 3, 12829 asm: arm64.AFNMADDS, 12830 reg: regInfo{ 12831 inputs: []inputInfo{ 12832 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12833 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12834 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12835 }, 12836 outputs: []outputInfo{ 12837 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12838 }, 12839 }, 12840 }, 12841 { 12842 name: "FNMADDD", 12843 argLen: 3, 12844 asm: arm64.AFNMADDD, 12845 reg: regInfo{ 12846 inputs: []inputInfo{ 12847 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12848 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12849 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12850 }, 12851 outputs: []outputInfo{ 12852 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12853 }, 12854 }, 12855 }, 12856 { 12857 name: "FMSUBS", 12858 argLen: 3, 12859 asm: arm64.AFMSUBS, 12860 reg: regInfo{ 12861 inputs: []inputInfo{ 12862 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12863 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12864 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12865 }, 12866 outputs: []outputInfo{ 12867 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12868 }, 12869 }, 12870 }, 12871 { 12872 name: "FMSUBD", 12873 argLen: 3, 12874 asm: arm64.AFMSUBD, 12875 reg: regInfo{ 12876 inputs: []inputInfo{ 12877 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12878 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12879 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12880 }, 12881 outputs: []outputInfo{ 12882 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12883 }, 12884 }, 12885 }, 12886 { 12887 name: "FNMSUBS", 12888 argLen: 3, 12889 asm: arm64.AFNMSUBS, 12890 reg: regInfo{ 12891 inputs: []inputInfo{ 12892 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12893 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12894 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12895 }, 12896 outputs: []outputInfo{ 12897 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12898 }, 12899 }, 12900 }, 12901 { 12902 name: "FNMSUBD", 12903 argLen: 3, 12904 asm: arm64.AFNMSUBD, 12905 reg: regInfo{ 12906 inputs: []inputInfo{ 12907 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12908 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12909 {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12910 }, 12911 outputs: []outputInfo{ 12912 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12913 }, 12914 }, 12915 }, 12916 { 12917 name: "SLL", 12918 argLen: 2, 12919 asm: arm64.ALSL, 12920 reg: regInfo{ 12921 inputs: []inputInfo{ 12922 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12923 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12924 }, 12925 outputs: []outputInfo{ 12926 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12927 }, 12928 }, 12929 }, 12930 { 12931 name: "SLLconst", 12932 auxType: auxInt64, 12933 argLen: 1, 12934 asm: arm64.ALSL, 12935 reg: regInfo{ 12936 inputs: []inputInfo{ 12937 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12938 }, 12939 outputs: []outputInfo{ 12940 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12941 }, 12942 }, 12943 }, 12944 { 12945 name: "SRL", 12946 argLen: 2, 12947 asm: arm64.ALSR, 12948 reg: regInfo{ 12949 inputs: []inputInfo{ 12950 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12951 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12952 }, 12953 outputs: []outputInfo{ 12954 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12955 }, 12956 }, 12957 }, 12958 { 12959 name: "SRLconst", 12960 auxType: auxInt64, 12961 argLen: 1, 12962 asm: arm64.ALSR, 12963 reg: regInfo{ 12964 inputs: []inputInfo{ 12965 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12966 }, 12967 outputs: []outputInfo{ 12968 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12969 }, 12970 }, 12971 }, 12972 { 12973 name: "SRA", 12974 argLen: 2, 12975 asm: arm64.AASR, 12976 reg: regInfo{ 12977 inputs: []inputInfo{ 12978 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12979 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12980 }, 12981 outputs: []outputInfo{ 12982 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12983 }, 12984 }, 12985 }, 12986 { 12987 name: "SRAconst", 12988 auxType: auxInt64, 12989 argLen: 1, 12990 asm: arm64.AASR, 12991 reg: regInfo{ 12992 inputs: []inputInfo{ 12993 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12994 }, 12995 outputs: []outputInfo{ 12996 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12997 }, 12998 }, 12999 }, 13000 { 13001 name: "RORconst", 13002 auxType: auxInt64, 13003 argLen: 1, 13004 asm: arm64.AROR, 13005 reg: regInfo{ 13006 inputs: []inputInfo{ 13007 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13008 }, 13009 outputs: []outputInfo{ 13010 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13011 }, 13012 }, 13013 }, 13014 { 13015 name: "RORWconst", 13016 auxType: auxInt64, 13017 argLen: 1, 13018 asm: arm64.ARORW, 13019 reg: regInfo{ 13020 inputs: []inputInfo{ 13021 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13022 }, 13023 outputs: []outputInfo{ 13024 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13025 }, 13026 }, 13027 }, 13028 { 13029 name: "CMP", 13030 argLen: 2, 13031 asm: arm64.ACMP, 13032 reg: regInfo{ 13033 inputs: []inputInfo{ 13034 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13035 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13036 }, 13037 }, 13038 }, 13039 { 13040 name: "CMPconst", 13041 auxType: auxInt64, 13042 argLen: 1, 13043 asm: arm64.ACMP, 13044 reg: regInfo{ 13045 inputs: []inputInfo{ 13046 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13047 }, 13048 }, 13049 }, 13050 { 13051 name: "CMPW", 13052 argLen: 2, 13053 asm: arm64.ACMPW, 13054 reg: regInfo{ 13055 inputs: []inputInfo{ 13056 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13057 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13058 }, 13059 }, 13060 }, 13061 { 13062 name: "CMPWconst", 13063 auxType: auxInt32, 13064 argLen: 1, 13065 asm: arm64.ACMPW, 13066 reg: regInfo{ 13067 inputs: []inputInfo{ 13068 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13069 }, 13070 }, 13071 }, 13072 { 13073 name: "CMN", 13074 argLen: 2, 13075 asm: arm64.ACMN, 13076 reg: regInfo{ 13077 inputs: []inputInfo{ 13078 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13079 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13080 }, 13081 }, 13082 }, 13083 { 13084 name: "CMNconst", 13085 auxType: auxInt64, 13086 argLen: 1, 13087 asm: arm64.ACMN, 13088 reg: regInfo{ 13089 inputs: []inputInfo{ 13090 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13091 }, 13092 }, 13093 }, 13094 { 13095 name: "CMNW", 13096 argLen: 2, 13097 asm: arm64.ACMNW, 13098 reg: regInfo{ 13099 inputs: []inputInfo{ 13100 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13101 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13102 }, 13103 }, 13104 }, 13105 { 13106 name: "CMNWconst", 13107 auxType: auxInt32, 13108 argLen: 1, 13109 asm: arm64.ACMNW, 13110 reg: regInfo{ 13111 inputs: []inputInfo{ 13112 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13113 }, 13114 }, 13115 }, 13116 { 13117 name: "FCMPS", 13118 argLen: 2, 13119 asm: arm64.AFCMPS, 13120 reg: regInfo{ 13121 inputs: []inputInfo{ 13122 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13123 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13124 }, 13125 }, 13126 }, 13127 { 13128 name: "FCMPD", 13129 argLen: 2, 13130 asm: arm64.AFCMPD, 13131 reg: regInfo{ 13132 inputs: []inputInfo{ 13133 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13134 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13135 }, 13136 }, 13137 }, 13138 { 13139 name: "ADDshiftLL", 13140 auxType: auxInt64, 13141 argLen: 2, 13142 asm: arm64.AADD, 13143 reg: regInfo{ 13144 inputs: []inputInfo{ 13145 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13146 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13147 }, 13148 outputs: []outputInfo{ 13149 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13150 }, 13151 }, 13152 }, 13153 { 13154 name: "ADDshiftRL", 13155 auxType: auxInt64, 13156 argLen: 2, 13157 asm: arm64.AADD, 13158 reg: regInfo{ 13159 inputs: []inputInfo{ 13160 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13161 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13162 }, 13163 outputs: []outputInfo{ 13164 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13165 }, 13166 }, 13167 }, 13168 { 13169 name: "ADDshiftRA", 13170 auxType: auxInt64, 13171 argLen: 2, 13172 asm: arm64.AADD, 13173 reg: regInfo{ 13174 inputs: []inputInfo{ 13175 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13176 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13177 }, 13178 outputs: []outputInfo{ 13179 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13180 }, 13181 }, 13182 }, 13183 { 13184 name: "SUBshiftLL", 13185 auxType: auxInt64, 13186 argLen: 2, 13187 asm: arm64.ASUB, 13188 reg: regInfo{ 13189 inputs: []inputInfo{ 13190 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13191 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13192 }, 13193 outputs: []outputInfo{ 13194 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13195 }, 13196 }, 13197 }, 13198 { 13199 name: "SUBshiftRL", 13200 auxType: auxInt64, 13201 argLen: 2, 13202 asm: arm64.ASUB, 13203 reg: regInfo{ 13204 inputs: []inputInfo{ 13205 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13206 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13207 }, 13208 outputs: []outputInfo{ 13209 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13210 }, 13211 }, 13212 }, 13213 { 13214 name: "SUBshiftRA", 13215 auxType: auxInt64, 13216 argLen: 2, 13217 asm: arm64.ASUB, 13218 reg: regInfo{ 13219 inputs: []inputInfo{ 13220 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13221 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13222 }, 13223 outputs: []outputInfo{ 13224 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13225 }, 13226 }, 13227 }, 13228 { 13229 name: "ANDshiftLL", 13230 auxType: auxInt64, 13231 argLen: 2, 13232 asm: arm64.AAND, 13233 reg: regInfo{ 13234 inputs: []inputInfo{ 13235 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13236 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13237 }, 13238 outputs: []outputInfo{ 13239 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13240 }, 13241 }, 13242 }, 13243 { 13244 name: "ANDshiftRL", 13245 auxType: auxInt64, 13246 argLen: 2, 13247 asm: arm64.AAND, 13248 reg: regInfo{ 13249 inputs: []inputInfo{ 13250 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13251 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13252 }, 13253 outputs: []outputInfo{ 13254 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13255 }, 13256 }, 13257 }, 13258 { 13259 name: "ANDshiftRA", 13260 auxType: auxInt64, 13261 argLen: 2, 13262 asm: arm64.AAND, 13263 reg: regInfo{ 13264 inputs: []inputInfo{ 13265 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13266 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13267 }, 13268 outputs: []outputInfo{ 13269 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13270 }, 13271 }, 13272 }, 13273 { 13274 name: "ORshiftLL", 13275 auxType: auxInt64, 13276 argLen: 2, 13277 asm: arm64.AORR, 13278 reg: regInfo{ 13279 inputs: []inputInfo{ 13280 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13281 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13282 }, 13283 outputs: []outputInfo{ 13284 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13285 }, 13286 }, 13287 }, 13288 { 13289 name: "ORshiftRL", 13290 auxType: auxInt64, 13291 argLen: 2, 13292 asm: arm64.AORR, 13293 reg: regInfo{ 13294 inputs: []inputInfo{ 13295 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13297 }, 13298 outputs: []outputInfo{ 13299 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13300 }, 13301 }, 13302 }, 13303 { 13304 name: "ORshiftRA", 13305 auxType: auxInt64, 13306 argLen: 2, 13307 asm: arm64.AORR, 13308 reg: regInfo{ 13309 inputs: []inputInfo{ 13310 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13311 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13312 }, 13313 outputs: []outputInfo{ 13314 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13315 }, 13316 }, 13317 }, 13318 { 13319 name: "XORshiftLL", 13320 auxType: auxInt64, 13321 argLen: 2, 13322 asm: arm64.AEOR, 13323 reg: regInfo{ 13324 inputs: []inputInfo{ 13325 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13326 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13327 }, 13328 outputs: []outputInfo{ 13329 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13330 }, 13331 }, 13332 }, 13333 { 13334 name: "XORshiftRL", 13335 auxType: auxInt64, 13336 argLen: 2, 13337 asm: arm64.AEOR, 13338 reg: regInfo{ 13339 inputs: []inputInfo{ 13340 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13341 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13342 }, 13343 outputs: []outputInfo{ 13344 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13345 }, 13346 }, 13347 }, 13348 { 13349 name: "XORshiftRA", 13350 auxType: auxInt64, 13351 argLen: 2, 13352 asm: arm64.AEOR, 13353 reg: regInfo{ 13354 inputs: []inputInfo{ 13355 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13356 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13357 }, 13358 outputs: []outputInfo{ 13359 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13360 }, 13361 }, 13362 }, 13363 { 13364 name: "BICshiftLL", 13365 auxType: auxInt64, 13366 argLen: 2, 13367 asm: arm64.ABIC, 13368 reg: regInfo{ 13369 inputs: []inputInfo{ 13370 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13371 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13372 }, 13373 outputs: []outputInfo{ 13374 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13375 }, 13376 }, 13377 }, 13378 { 13379 name: "BICshiftRL", 13380 auxType: auxInt64, 13381 argLen: 2, 13382 asm: arm64.ABIC, 13383 reg: regInfo{ 13384 inputs: []inputInfo{ 13385 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13386 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13387 }, 13388 outputs: []outputInfo{ 13389 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13390 }, 13391 }, 13392 }, 13393 { 13394 name: "BICshiftRA", 13395 auxType: auxInt64, 13396 argLen: 2, 13397 asm: arm64.ABIC, 13398 reg: regInfo{ 13399 inputs: []inputInfo{ 13400 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13401 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13402 }, 13403 outputs: []outputInfo{ 13404 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13405 }, 13406 }, 13407 }, 13408 { 13409 name: "CMPshiftLL", 13410 auxType: auxInt64, 13411 argLen: 2, 13412 asm: arm64.ACMP, 13413 reg: regInfo{ 13414 inputs: []inputInfo{ 13415 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13416 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13417 }, 13418 }, 13419 }, 13420 { 13421 name: "CMPshiftRL", 13422 auxType: auxInt64, 13423 argLen: 2, 13424 asm: arm64.ACMP, 13425 reg: regInfo{ 13426 inputs: []inputInfo{ 13427 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13428 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13429 }, 13430 }, 13431 }, 13432 { 13433 name: "CMPshiftRA", 13434 auxType: auxInt64, 13435 argLen: 2, 13436 asm: arm64.ACMP, 13437 reg: regInfo{ 13438 inputs: []inputInfo{ 13439 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13440 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13441 }, 13442 }, 13443 }, 13444 { 13445 name: "MOVDconst", 13446 auxType: auxInt64, 13447 argLen: 0, 13448 rematerializeable: true, 13449 asm: arm64.AMOVD, 13450 reg: regInfo{ 13451 outputs: []outputInfo{ 13452 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13453 }, 13454 }, 13455 }, 13456 { 13457 name: "FMOVSconst", 13458 auxType: auxFloat64, 13459 argLen: 0, 13460 rematerializeable: true, 13461 asm: arm64.AFMOVS, 13462 reg: regInfo{ 13463 outputs: []outputInfo{ 13464 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13465 }, 13466 }, 13467 }, 13468 { 13469 name: "FMOVDconst", 13470 auxType: auxFloat64, 13471 argLen: 0, 13472 rematerializeable: true, 13473 asm: arm64.AFMOVD, 13474 reg: regInfo{ 13475 outputs: []outputInfo{ 13476 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13477 }, 13478 }, 13479 }, 13480 { 13481 name: "MOVDaddr", 13482 auxType: auxSymOff, 13483 argLen: 1, 13484 rematerializeable: true, 13485 symEffect: SymAddr, 13486 asm: arm64.AMOVD, 13487 reg: regInfo{ 13488 inputs: []inputInfo{ 13489 {0, 9223372037928517632}, // SP SB 13490 }, 13491 outputs: []outputInfo{ 13492 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13493 }, 13494 }, 13495 }, 13496 { 13497 name: "MOVBload", 13498 auxType: auxSymOff, 13499 argLen: 2, 13500 faultOnNilArg0: true, 13501 symEffect: SymRead, 13502 asm: arm64.AMOVB, 13503 reg: regInfo{ 13504 inputs: []inputInfo{ 13505 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13506 }, 13507 outputs: []outputInfo{ 13508 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13509 }, 13510 }, 13511 }, 13512 { 13513 name: "MOVBUload", 13514 auxType: auxSymOff, 13515 argLen: 2, 13516 faultOnNilArg0: true, 13517 symEffect: SymRead, 13518 asm: arm64.AMOVBU, 13519 reg: regInfo{ 13520 inputs: []inputInfo{ 13521 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13522 }, 13523 outputs: []outputInfo{ 13524 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13525 }, 13526 }, 13527 }, 13528 { 13529 name: "MOVHload", 13530 auxType: auxSymOff, 13531 argLen: 2, 13532 faultOnNilArg0: true, 13533 symEffect: SymRead, 13534 asm: arm64.AMOVH, 13535 reg: regInfo{ 13536 inputs: []inputInfo{ 13537 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13538 }, 13539 outputs: []outputInfo{ 13540 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13541 }, 13542 }, 13543 }, 13544 { 13545 name: "MOVHUload", 13546 auxType: auxSymOff, 13547 argLen: 2, 13548 faultOnNilArg0: true, 13549 symEffect: SymRead, 13550 asm: arm64.AMOVHU, 13551 reg: regInfo{ 13552 inputs: []inputInfo{ 13553 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13554 }, 13555 outputs: []outputInfo{ 13556 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13557 }, 13558 }, 13559 }, 13560 { 13561 name: "MOVWload", 13562 auxType: auxSymOff, 13563 argLen: 2, 13564 faultOnNilArg0: true, 13565 symEffect: SymRead, 13566 asm: arm64.AMOVW, 13567 reg: regInfo{ 13568 inputs: []inputInfo{ 13569 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13570 }, 13571 outputs: []outputInfo{ 13572 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13573 }, 13574 }, 13575 }, 13576 { 13577 name: "MOVWUload", 13578 auxType: auxSymOff, 13579 argLen: 2, 13580 faultOnNilArg0: true, 13581 symEffect: SymRead, 13582 asm: arm64.AMOVWU, 13583 reg: regInfo{ 13584 inputs: []inputInfo{ 13585 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13586 }, 13587 outputs: []outputInfo{ 13588 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13589 }, 13590 }, 13591 }, 13592 { 13593 name: "MOVDload", 13594 auxType: auxSymOff, 13595 argLen: 2, 13596 faultOnNilArg0: true, 13597 symEffect: SymRead, 13598 asm: arm64.AMOVD, 13599 reg: regInfo{ 13600 inputs: []inputInfo{ 13601 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13602 }, 13603 outputs: []outputInfo{ 13604 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13605 }, 13606 }, 13607 }, 13608 { 13609 name: "FMOVSload", 13610 auxType: auxSymOff, 13611 argLen: 2, 13612 faultOnNilArg0: true, 13613 symEffect: SymRead, 13614 asm: arm64.AFMOVS, 13615 reg: regInfo{ 13616 inputs: []inputInfo{ 13617 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13618 }, 13619 outputs: []outputInfo{ 13620 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13621 }, 13622 }, 13623 }, 13624 { 13625 name: "FMOVDload", 13626 auxType: auxSymOff, 13627 argLen: 2, 13628 faultOnNilArg0: true, 13629 symEffect: SymRead, 13630 asm: arm64.AFMOVD, 13631 reg: regInfo{ 13632 inputs: []inputInfo{ 13633 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13634 }, 13635 outputs: []outputInfo{ 13636 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13637 }, 13638 }, 13639 }, 13640 { 13641 name: "MOVBstore", 13642 auxType: auxSymOff, 13643 argLen: 3, 13644 faultOnNilArg0: true, 13645 symEffect: SymWrite, 13646 asm: arm64.AMOVB, 13647 reg: regInfo{ 13648 inputs: []inputInfo{ 13649 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13650 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13651 }, 13652 }, 13653 }, 13654 { 13655 name: "MOVHstore", 13656 auxType: auxSymOff, 13657 argLen: 3, 13658 faultOnNilArg0: true, 13659 symEffect: SymWrite, 13660 asm: arm64.AMOVH, 13661 reg: regInfo{ 13662 inputs: []inputInfo{ 13663 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13664 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13665 }, 13666 }, 13667 }, 13668 { 13669 name: "MOVWstore", 13670 auxType: auxSymOff, 13671 argLen: 3, 13672 faultOnNilArg0: true, 13673 symEffect: SymWrite, 13674 asm: arm64.AMOVW, 13675 reg: regInfo{ 13676 inputs: []inputInfo{ 13677 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13678 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13679 }, 13680 }, 13681 }, 13682 { 13683 name: "MOVDstore", 13684 auxType: auxSymOff, 13685 argLen: 3, 13686 faultOnNilArg0: true, 13687 symEffect: SymWrite, 13688 asm: arm64.AMOVD, 13689 reg: regInfo{ 13690 inputs: []inputInfo{ 13691 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13692 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13693 }, 13694 }, 13695 }, 13696 { 13697 name: "STP", 13698 auxType: auxSymOff, 13699 argLen: 4, 13700 faultOnNilArg0: true, 13701 symEffect: SymWrite, 13702 asm: arm64.ASTP, 13703 reg: regInfo{ 13704 inputs: []inputInfo{ 13705 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13706 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13707 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13708 }, 13709 }, 13710 }, 13711 { 13712 name: "FMOVSstore", 13713 auxType: auxSymOff, 13714 argLen: 3, 13715 faultOnNilArg0: true, 13716 symEffect: SymWrite, 13717 asm: arm64.AFMOVS, 13718 reg: regInfo{ 13719 inputs: []inputInfo{ 13720 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13721 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13722 }, 13723 }, 13724 }, 13725 { 13726 name: "FMOVDstore", 13727 auxType: auxSymOff, 13728 argLen: 3, 13729 faultOnNilArg0: true, 13730 symEffect: SymWrite, 13731 asm: arm64.AFMOVD, 13732 reg: regInfo{ 13733 inputs: []inputInfo{ 13734 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13735 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13736 }, 13737 }, 13738 }, 13739 { 13740 name: "MOVBstorezero", 13741 auxType: auxSymOff, 13742 argLen: 2, 13743 faultOnNilArg0: true, 13744 symEffect: SymWrite, 13745 asm: arm64.AMOVB, 13746 reg: regInfo{ 13747 inputs: []inputInfo{ 13748 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13749 }, 13750 }, 13751 }, 13752 { 13753 name: "MOVHstorezero", 13754 auxType: auxSymOff, 13755 argLen: 2, 13756 faultOnNilArg0: true, 13757 symEffect: SymWrite, 13758 asm: arm64.AMOVH, 13759 reg: regInfo{ 13760 inputs: []inputInfo{ 13761 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13762 }, 13763 }, 13764 }, 13765 { 13766 name: "MOVWstorezero", 13767 auxType: auxSymOff, 13768 argLen: 2, 13769 faultOnNilArg0: true, 13770 symEffect: SymWrite, 13771 asm: arm64.AMOVW, 13772 reg: regInfo{ 13773 inputs: []inputInfo{ 13774 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13775 }, 13776 }, 13777 }, 13778 { 13779 name: "MOVDstorezero", 13780 auxType: auxSymOff, 13781 argLen: 2, 13782 faultOnNilArg0: true, 13783 symEffect: SymWrite, 13784 asm: arm64.AMOVD, 13785 reg: regInfo{ 13786 inputs: []inputInfo{ 13787 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13788 }, 13789 }, 13790 }, 13791 { 13792 name: "MOVQstorezero", 13793 auxType: auxSymOff, 13794 argLen: 2, 13795 faultOnNilArg0: true, 13796 symEffect: SymWrite, 13797 asm: arm64.ASTP, 13798 reg: regInfo{ 13799 inputs: []inputInfo{ 13800 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13801 }, 13802 }, 13803 }, 13804 { 13805 name: "FMOVDgpfp", 13806 argLen: 1, 13807 asm: arm64.AFMOVD, 13808 reg: regInfo{ 13809 inputs: []inputInfo{ 13810 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13811 }, 13812 outputs: []outputInfo{ 13813 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13814 }, 13815 }, 13816 }, 13817 { 13818 name: "FMOVDfpgp", 13819 argLen: 1, 13820 asm: arm64.AFMOVD, 13821 reg: regInfo{ 13822 inputs: []inputInfo{ 13823 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13824 }, 13825 outputs: []outputInfo{ 13826 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13827 }, 13828 }, 13829 }, 13830 { 13831 name: "MOVBreg", 13832 argLen: 1, 13833 asm: arm64.AMOVB, 13834 reg: regInfo{ 13835 inputs: []inputInfo{ 13836 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13837 }, 13838 outputs: []outputInfo{ 13839 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13840 }, 13841 }, 13842 }, 13843 { 13844 name: "MOVBUreg", 13845 argLen: 1, 13846 asm: arm64.AMOVBU, 13847 reg: regInfo{ 13848 inputs: []inputInfo{ 13849 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13850 }, 13851 outputs: []outputInfo{ 13852 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13853 }, 13854 }, 13855 }, 13856 { 13857 name: "MOVHreg", 13858 argLen: 1, 13859 asm: arm64.AMOVH, 13860 reg: regInfo{ 13861 inputs: []inputInfo{ 13862 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13863 }, 13864 outputs: []outputInfo{ 13865 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13866 }, 13867 }, 13868 }, 13869 { 13870 name: "MOVHUreg", 13871 argLen: 1, 13872 asm: arm64.AMOVHU, 13873 reg: regInfo{ 13874 inputs: []inputInfo{ 13875 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13876 }, 13877 outputs: []outputInfo{ 13878 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13879 }, 13880 }, 13881 }, 13882 { 13883 name: "MOVWreg", 13884 argLen: 1, 13885 asm: arm64.AMOVW, 13886 reg: regInfo{ 13887 inputs: []inputInfo{ 13888 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13889 }, 13890 outputs: []outputInfo{ 13891 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13892 }, 13893 }, 13894 }, 13895 { 13896 name: "MOVWUreg", 13897 argLen: 1, 13898 asm: arm64.AMOVWU, 13899 reg: regInfo{ 13900 inputs: []inputInfo{ 13901 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13902 }, 13903 outputs: []outputInfo{ 13904 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13905 }, 13906 }, 13907 }, 13908 { 13909 name: "MOVDreg", 13910 argLen: 1, 13911 asm: arm64.AMOVD, 13912 reg: regInfo{ 13913 inputs: []inputInfo{ 13914 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13915 }, 13916 outputs: []outputInfo{ 13917 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13918 }, 13919 }, 13920 }, 13921 { 13922 name: "MOVDnop", 13923 argLen: 1, 13924 resultInArg0: true, 13925 reg: regInfo{ 13926 inputs: []inputInfo{ 13927 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13928 }, 13929 outputs: []outputInfo{ 13930 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13931 }, 13932 }, 13933 }, 13934 { 13935 name: "SCVTFWS", 13936 argLen: 1, 13937 asm: arm64.ASCVTFWS, 13938 reg: regInfo{ 13939 inputs: []inputInfo{ 13940 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13941 }, 13942 outputs: []outputInfo{ 13943 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13944 }, 13945 }, 13946 }, 13947 { 13948 name: "SCVTFWD", 13949 argLen: 1, 13950 asm: arm64.ASCVTFWD, 13951 reg: regInfo{ 13952 inputs: []inputInfo{ 13953 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13954 }, 13955 outputs: []outputInfo{ 13956 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13957 }, 13958 }, 13959 }, 13960 { 13961 name: "UCVTFWS", 13962 argLen: 1, 13963 asm: arm64.AUCVTFWS, 13964 reg: regInfo{ 13965 inputs: []inputInfo{ 13966 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13967 }, 13968 outputs: []outputInfo{ 13969 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13970 }, 13971 }, 13972 }, 13973 { 13974 name: "UCVTFWD", 13975 argLen: 1, 13976 asm: arm64.AUCVTFWD, 13977 reg: regInfo{ 13978 inputs: []inputInfo{ 13979 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13980 }, 13981 outputs: []outputInfo{ 13982 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13983 }, 13984 }, 13985 }, 13986 { 13987 name: "SCVTFS", 13988 argLen: 1, 13989 asm: arm64.ASCVTFS, 13990 reg: regInfo{ 13991 inputs: []inputInfo{ 13992 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13993 }, 13994 outputs: []outputInfo{ 13995 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13996 }, 13997 }, 13998 }, 13999 { 14000 name: "SCVTFD", 14001 argLen: 1, 14002 asm: arm64.ASCVTFD, 14003 reg: regInfo{ 14004 inputs: []inputInfo{ 14005 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14006 }, 14007 outputs: []outputInfo{ 14008 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14009 }, 14010 }, 14011 }, 14012 { 14013 name: "UCVTFS", 14014 argLen: 1, 14015 asm: arm64.AUCVTFS, 14016 reg: regInfo{ 14017 inputs: []inputInfo{ 14018 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14019 }, 14020 outputs: []outputInfo{ 14021 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14022 }, 14023 }, 14024 }, 14025 { 14026 name: "UCVTFD", 14027 argLen: 1, 14028 asm: arm64.AUCVTFD, 14029 reg: regInfo{ 14030 inputs: []inputInfo{ 14031 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14032 }, 14033 outputs: []outputInfo{ 14034 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14035 }, 14036 }, 14037 }, 14038 { 14039 name: "FCVTZSSW", 14040 argLen: 1, 14041 asm: arm64.AFCVTZSSW, 14042 reg: regInfo{ 14043 inputs: []inputInfo{ 14044 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14045 }, 14046 outputs: []outputInfo{ 14047 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14048 }, 14049 }, 14050 }, 14051 { 14052 name: "FCVTZSDW", 14053 argLen: 1, 14054 asm: arm64.AFCVTZSDW, 14055 reg: regInfo{ 14056 inputs: []inputInfo{ 14057 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14058 }, 14059 outputs: []outputInfo{ 14060 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14061 }, 14062 }, 14063 }, 14064 { 14065 name: "FCVTZUSW", 14066 argLen: 1, 14067 asm: arm64.AFCVTZUSW, 14068 reg: regInfo{ 14069 inputs: []inputInfo{ 14070 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14071 }, 14072 outputs: []outputInfo{ 14073 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14074 }, 14075 }, 14076 }, 14077 { 14078 name: "FCVTZUDW", 14079 argLen: 1, 14080 asm: arm64.AFCVTZUDW, 14081 reg: regInfo{ 14082 inputs: []inputInfo{ 14083 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14084 }, 14085 outputs: []outputInfo{ 14086 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14087 }, 14088 }, 14089 }, 14090 { 14091 name: "FCVTZSS", 14092 argLen: 1, 14093 asm: arm64.AFCVTZSS, 14094 reg: regInfo{ 14095 inputs: []inputInfo{ 14096 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14097 }, 14098 outputs: []outputInfo{ 14099 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14100 }, 14101 }, 14102 }, 14103 { 14104 name: "FCVTZSD", 14105 argLen: 1, 14106 asm: arm64.AFCVTZSD, 14107 reg: regInfo{ 14108 inputs: []inputInfo{ 14109 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14110 }, 14111 outputs: []outputInfo{ 14112 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14113 }, 14114 }, 14115 }, 14116 { 14117 name: "FCVTZUS", 14118 argLen: 1, 14119 asm: arm64.AFCVTZUS, 14120 reg: regInfo{ 14121 inputs: []inputInfo{ 14122 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14123 }, 14124 outputs: []outputInfo{ 14125 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14126 }, 14127 }, 14128 }, 14129 { 14130 name: "FCVTZUD", 14131 argLen: 1, 14132 asm: arm64.AFCVTZUD, 14133 reg: regInfo{ 14134 inputs: []inputInfo{ 14135 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14136 }, 14137 outputs: []outputInfo{ 14138 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14139 }, 14140 }, 14141 }, 14142 { 14143 name: "FCVTSD", 14144 argLen: 1, 14145 asm: arm64.AFCVTSD, 14146 reg: regInfo{ 14147 inputs: []inputInfo{ 14148 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14149 }, 14150 outputs: []outputInfo{ 14151 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14152 }, 14153 }, 14154 }, 14155 { 14156 name: "FCVTDS", 14157 argLen: 1, 14158 asm: arm64.AFCVTDS, 14159 reg: regInfo{ 14160 inputs: []inputInfo{ 14161 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14162 }, 14163 outputs: []outputInfo{ 14164 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14165 }, 14166 }, 14167 }, 14168 { 14169 name: "FRINTAD", 14170 argLen: 1, 14171 asm: arm64.AFRINTAD, 14172 reg: regInfo{ 14173 inputs: []inputInfo{ 14174 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14175 }, 14176 outputs: []outputInfo{ 14177 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14178 }, 14179 }, 14180 }, 14181 { 14182 name: "FRINTMD", 14183 argLen: 1, 14184 asm: arm64.AFRINTMD, 14185 reg: regInfo{ 14186 inputs: []inputInfo{ 14187 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14188 }, 14189 outputs: []outputInfo{ 14190 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14191 }, 14192 }, 14193 }, 14194 { 14195 name: "FRINTPD", 14196 argLen: 1, 14197 asm: arm64.AFRINTPD, 14198 reg: regInfo{ 14199 inputs: []inputInfo{ 14200 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14201 }, 14202 outputs: []outputInfo{ 14203 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14204 }, 14205 }, 14206 }, 14207 { 14208 name: "FRINTZD", 14209 argLen: 1, 14210 asm: arm64.AFRINTZD, 14211 reg: regInfo{ 14212 inputs: []inputInfo{ 14213 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14214 }, 14215 outputs: []outputInfo{ 14216 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14217 }, 14218 }, 14219 }, 14220 { 14221 name: "CSEL", 14222 auxType: auxCCop, 14223 argLen: 3, 14224 asm: arm64.ACSEL, 14225 reg: regInfo{ 14226 inputs: []inputInfo{ 14227 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14228 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14229 }, 14230 outputs: []outputInfo{ 14231 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14232 }, 14233 }, 14234 }, 14235 { 14236 name: "CSEL0", 14237 auxType: auxCCop, 14238 argLen: 2, 14239 asm: arm64.ACSEL, 14240 reg: regInfo{ 14241 inputs: []inputInfo{ 14242 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14243 }, 14244 outputs: []outputInfo{ 14245 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14246 }, 14247 }, 14248 }, 14249 { 14250 name: "CALLstatic", 14251 auxType: auxSymOff, 14252 argLen: 1, 14253 clobberFlags: true, 14254 call: true, 14255 symEffect: SymNone, 14256 reg: regInfo{ 14257 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14258 }, 14259 }, 14260 { 14261 name: "CALLclosure", 14262 auxType: auxInt64, 14263 argLen: 3, 14264 clobberFlags: true, 14265 call: true, 14266 reg: regInfo{ 14267 inputs: []inputInfo{ 14268 {1, 67108864}, // R26 14269 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 14270 }, 14271 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14272 }, 14273 }, 14274 { 14275 name: "CALLinter", 14276 auxType: auxInt64, 14277 argLen: 2, 14278 clobberFlags: true, 14279 call: true, 14280 reg: regInfo{ 14281 inputs: []inputInfo{ 14282 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14283 }, 14284 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14285 }, 14286 }, 14287 { 14288 name: "LoweredNilCheck", 14289 argLen: 2, 14290 nilCheck: true, 14291 faultOnNilArg0: true, 14292 reg: regInfo{ 14293 inputs: []inputInfo{ 14294 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14295 }, 14296 }, 14297 }, 14298 { 14299 name: "Equal", 14300 argLen: 1, 14301 reg: regInfo{ 14302 outputs: []outputInfo{ 14303 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14304 }, 14305 }, 14306 }, 14307 { 14308 name: "NotEqual", 14309 argLen: 1, 14310 reg: regInfo{ 14311 outputs: []outputInfo{ 14312 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14313 }, 14314 }, 14315 }, 14316 { 14317 name: "LessThan", 14318 argLen: 1, 14319 reg: regInfo{ 14320 outputs: []outputInfo{ 14321 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14322 }, 14323 }, 14324 }, 14325 { 14326 name: "LessEqual", 14327 argLen: 1, 14328 reg: regInfo{ 14329 outputs: []outputInfo{ 14330 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14331 }, 14332 }, 14333 }, 14334 { 14335 name: "GreaterThan", 14336 argLen: 1, 14337 reg: regInfo{ 14338 outputs: []outputInfo{ 14339 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14340 }, 14341 }, 14342 }, 14343 { 14344 name: "GreaterEqual", 14345 argLen: 1, 14346 reg: regInfo{ 14347 outputs: []outputInfo{ 14348 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14349 }, 14350 }, 14351 }, 14352 { 14353 name: "LessThanU", 14354 argLen: 1, 14355 reg: regInfo{ 14356 outputs: []outputInfo{ 14357 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14358 }, 14359 }, 14360 }, 14361 { 14362 name: "LessEqualU", 14363 argLen: 1, 14364 reg: regInfo{ 14365 outputs: []outputInfo{ 14366 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14367 }, 14368 }, 14369 }, 14370 { 14371 name: "GreaterThanU", 14372 argLen: 1, 14373 reg: regInfo{ 14374 outputs: []outputInfo{ 14375 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14376 }, 14377 }, 14378 }, 14379 { 14380 name: "GreaterEqualU", 14381 argLen: 1, 14382 reg: regInfo{ 14383 outputs: []outputInfo{ 14384 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14385 }, 14386 }, 14387 }, 14388 { 14389 name: "DUFFZERO", 14390 auxType: auxInt64, 14391 argLen: 2, 14392 faultOnNilArg0: true, 14393 reg: regInfo{ 14394 inputs: []inputInfo{ 14395 {0, 65536}, // R16 14396 }, 14397 clobbers: 536936448, // R16 R30 14398 }, 14399 }, 14400 { 14401 name: "LoweredZero", 14402 argLen: 3, 14403 clobberFlags: true, 14404 faultOnNilArg0: true, 14405 reg: regInfo{ 14406 inputs: []inputInfo{ 14407 {0, 65536}, // R16 14408 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14409 }, 14410 clobbers: 65536, // R16 14411 }, 14412 }, 14413 { 14414 name: "DUFFCOPY", 14415 auxType: auxInt64, 14416 argLen: 3, 14417 faultOnNilArg0: true, 14418 faultOnNilArg1: true, 14419 reg: regInfo{ 14420 inputs: []inputInfo{ 14421 {0, 131072}, // R17 14422 {1, 65536}, // R16 14423 }, 14424 clobbers: 537067520, // R16 R17 R30 14425 }, 14426 }, 14427 { 14428 name: "LoweredMove", 14429 argLen: 4, 14430 clobberFlags: true, 14431 faultOnNilArg0: true, 14432 faultOnNilArg1: true, 14433 reg: regInfo{ 14434 inputs: []inputInfo{ 14435 {0, 131072}, // R17 14436 {1, 65536}, // R16 14437 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14438 }, 14439 clobbers: 196608, // R16 R17 14440 }, 14441 }, 14442 { 14443 name: "LoweredGetClosurePtr", 14444 argLen: 0, 14445 reg: regInfo{ 14446 outputs: []outputInfo{ 14447 {0, 67108864}, // R26 14448 }, 14449 }, 14450 }, 14451 { 14452 name: "LoweredGetCallerSP", 14453 argLen: 0, 14454 rematerializeable: true, 14455 reg: regInfo{ 14456 outputs: []outputInfo{ 14457 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14458 }, 14459 }, 14460 }, 14461 { 14462 name: "MOVDconvert", 14463 argLen: 2, 14464 asm: arm64.AMOVD, 14465 reg: regInfo{ 14466 inputs: []inputInfo{ 14467 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14468 }, 14469 outputs: []outputInfo{ 14470 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14471 }, 14472 }, 14473 }, 14474 { 14475 name: "FlagEQ", 14476 argLen: 0, 14477 reg: regInfo{}, 14478 }, 14479 { 14480 name: "FlagLT_ULT", 14481 argLen: 0, 14482 reg: regInfo{}, 14483 }, 14484 { 14485 name: "FlagLT_UGT", 14486 argLen: 0, 14487 reg: regInfo{}, 14488 }, 14489 { 14490 name: "FlagGT_UGT", 14491 argLen: 0, 14492 reg: regInfo{}, 14493 }, 14494 { 14495 name: "FlagGT_ULT", 14496 argLen: 0, 14497 reg: regInfo{}, 14498 }, 14499 { 14500 name: "InvertFlags", 14501 argLen: 1, 14502 reg: regInfo{}, 14503 }, 14504 { 14505 name: "LDAR", 14506 argLen: 2, 14507 faultOnNilArg0: true, 14508 asm: arm64.ALDAR, 14509 reg: regInfo{ 14510 inputs: []inputInfo{ 14511 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14512 }, 14513 outputs: []outputInfo{ 14514 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14515 }, 14516 }, 14517 }, 14518 { 14519 name: "LDARW", 14520 argLen: 2, 14521 faultOnNilArg0: true, 14522 asm: arm64.ALDARW, 14523 reg: regInfo{ 14524 inputs: []inputInfo{ 14525 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14526 }, 14527 outputs: []outputInfo{ 14528 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14529 }, 14530 }, 14531 }, 14532 { 14533 name: "STLR", 14534 argLen: 3, 14535 faultOnNilArg0: true, 14536 hasSideEffects: true, 14537 asm: arm64.ASTLR, 14538 reg: regInfo{ 14539 inputs: []inputInfo{ 14540 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14541 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14542 }, 14543 }, 14544 }, 14545 { 14546 name: "STLRW", 14547 argLen: 3, 14548 faultOnNilArg0: true, 14549 hasSideEffects: true, 14550 asm: arm64.ASTLRW, 14551 reg: regInfo{ 14552 inputs: []inputInfo{ 14553 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14554 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14555 }, 14556 }, 14557 }, 14558 { 14559 name: "LoweredAtomicExchange64", 14560 argLen: 3, 14561 resultNotInArgs: true, 14562 faultOnNilArg0: true, 14563 hasSideEffects: true, 14564 reg: regInfo{ 14565 inputs: []inputInfo{ 14566 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14567 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14568 }, 14569 outputs: []outputInfo{ 14570 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14571 }, 14572 }, 14573 }, 14574 { 14575 name: "LoweredAtomicExchange32", 14576 argLen: 3, 14577 resultNotInArgs: true, 14578 faultOnNilArg0: true, 14579 hasSideEffects: true, 14580 reg: regInfo{ 14581 inputs: []inputInfo{ 14582 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14583 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14584 }, 14585 outputs: []outputInfo{ 14586 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14587 }, 14588 }, 14589 }, 14590 { 14591 name: "LoweredAtomicAdd64", 14592 argLen: 3, 14593 resultNotInArgs: true, 14594 faultOnNilArg0: true, 14595 hasSideEffects: true, 14596 reg: regInfo{ 14597 inputs: []inputInfo{ 14598 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14599 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14600 }, 14601 outputs: []outputInfo{ 14602 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14603 }, 14604 }, 14605 }, 14606 { 14607 name: "LoweredAtomicAdd32", 14608 argLen: 3, 14609 resultNotInArgs: true, 14610 faultOnNilArg0: true, 14611 hasSideEffects: true, 14612 reg: regInfo{ 14613 inputs: []inputInfo{ 14614 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14615 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14616 }, 14617 outputs: []outputInfo{ 14618 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14619 }, 14620 }, 14621 }, 14622 { 14623 name: "LoweredAtomicCas64", 14624 argLen: 4, 14625 resultNotInArgs: true, 14626 clobberFlags: true, 14627 faultOnNilArg0: true, 14628 hasSideEffects: true, 14629 reg: regInfo{ 14630 inputs: []inputInfo{ 14631 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14632 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14633 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14634 }, 14635 outputs: []outputInfo{ 14636 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14637 }, 14638 }, 14639 }, 14640 { 14641 name: "LoweredAtomicCas32", 14642 argLen: 4, 14643 resultNotInArgs: true, 14644 clobberFlags: true, 14645 faultOnNilArg0: true, 14646 hasSideEffects: true, 14647 reg: regInfo{ 14648 inputs: []inputInfo{ 14649 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14650 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14651 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14652 }, 14653 outputs: []outputInfo{ 14654 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14655 }, 14656 }, 14657 }, 14658 { 14659 name: "LoweredAtomicAnd8", 14660 argLen: 3, 14661 faultOnNilArg0: true, 14662 hasSideEffects: true, 14663 asm: arm64.AAND, 14664 reg: regInfo{ 14665 inputs: []inputInfo{ 14666 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14667 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14668 }, 14669 }, 14670 }, 14671 { 14672 name: "LoweredAtomicOr8", 14673 argLen: 3, 14674 faultOnNilArg0: true, 14675 hasSideEffects: true, 14676 asm: arm64.AORR, 14677 reg: regInfo{ 14678 inputs: []inputInfo{ 14679 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14680 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14681 }, 14682 }, 14683 }, 14684 { 14685 name: "LoweredWB", 14686 auxType: auxSym, 14687 argLen: 3, 14688 clobberFlags: true, 14689 symEffect: SymNone, 14690 reg: regInfo{ 14691 inputs: []inputInfo{ 14692 {0, 4}, // R2 14693 {1, 8}, // R3 14694 }, 14695 clobbers: 9223372035244163072, // R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 14696 }, 14697 }, 14698 14699 { 14700 name: "ADD", 14701 argLen: 2, 14702 commutative: true, 14703 asm: mips.AADDU, 14704 reg: regInfo{ 14705 inputs: []inputInfo{ 14706 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14707 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14708 }, 14709 outputs: []outputInfo{ 14710 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14711 }, 14712 }, 14713 }, 14714 { 14715 name: "ADDconst", 14716 auxType: auxInt32, 14717 argLen: 1, 14718 asm: mips.AADDU, 14719 reg: regInfo{ 14720 inputs: []inputInfo{ 14721 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 14722 }, 14723 outputs: []outputInfo{ 14724 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14725 }, 14726 }, 14727 }, 14728 { 14729 name: "SUB", 14730 argLen: 2, 14731 asm: mips.ASUBU, 14732 reg: regInfo{ 14733 inputs: []inputInfo{ 14734 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14735 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14736 }, 14737 outputs: []outputInfo{ 14738 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14739 }, 14740 }, 14741 }, 14742 { 14743 name: "SUBconst", 14744 auxType: auxInt32, 14745 argLen: 1, 14746 asm: mips.ASUBU, 14747 reg: regInfo{ 14748 inputs: []inputInfo{ 14749 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14750 }, 14751 outputs: []outputInfo{ 14752 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14753 }, 14754 }, 14755 }, 14756 { 14757 name: "MUL", 14758 argLen: 2, 14759 commutative: true, 14760 asm: mips.AMUL, 14761 reg: regInfo{ 14762 inputs: []inputInfo{ 14763 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14764 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14765 }, 14766 clobbers: 105553116266496, // HI LO 14767 outputs: []outputInfo{ 14768 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14769 }, 14770 }, 14771 }, 14772 { 14773 name: "MULT", 14774 argLen: 2, 14775 commutative: true, 14776 asm: mips.AMUL, 14777 reg: regInfo{ 14778 inputs: []inputInfo{ 14779 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14780 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14781 }, 14782 outputs: []outputInfo{ 14783 {0, 35184372088832}, // HI 14784 {1, 70368744177664}, // LO 14785 }, 14786 }, 14787 }, 14788 { 14789 name: "MULTU", 14790 argLen: 2, 14791 commutative: true, 14792 asm: mips.AMULU, 14793 reg: regInfo{ 14794 inputs: []inputInfo{ 14795 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14796 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14797 }, 14798 outputs: []outputInfo{ 14799 {0, 35184372088832}, // HI 14800 {1, 70368744177664}, // LO 14801 }, 14802 }, 14803 }, 14804 { 14805 name: "DIV", 14806 argLen: 2, 14807 asm: mips.ADIV, 14808 reg: regInfo{ 14809 inputs: []inputInfo{ 14810 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14811 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14812 }, 14813 outputs: []outputInfo{ 14814 {0, 35184372088832}, // HI 14815 {1, 70368744177664}, // LO 14816 }, 14817 }, 14818 }, 14819 { 14820 name: "DIVU", 14821 argLen: 2, 14822 asm: mips.ADIVU, 14823 reg: regInfo{ 14824 inputs: []inputInfo{ 14825 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14826 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14827 }, 14828 outputs: []outputInfo{ 14829 {0, 35184372088832}, // HI 14830 {1, 70368744177664}, // LO 14831 }, 14832 }, 14833 }, 14834 { 14835 name: "ADDF", 14836 argLen: 2, 14837 commutative: true, 14838 asm: mips.AADDF, 14839 reg: regInfo{ 14840 inputs: []inputInfo{ 14841 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14842 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14843 }, 14844 outputs: []outputInfo{ 14845 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14846 }, 14847 }, 14848 }, 14849 { 14850 name: "ADDD", 14851 argLen: 2, 14852 commutative: true, 14853 asm: mips.AADDD, 14854 reg: regInfo{ 14855 inputs: []inputInfo{ 14856 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14857 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14858 }, 14859 outputs: []outputInfo{ 14860 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14861 }, 14862 }, 14863 }, 14864 { 14865 name: "SUBF", 14866 argLen: 2, 14867 asm: mips.ASUBF, 14868 reg: regInfo{ 14869 inputs: []inputInfo{ 14870 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14871 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14872 }, 14873 outputs: []outputInfo{ 14874 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14875 }, 14876 }, 14877 }, 14878 { 14879 name: "SUBD", 14880 argLen: 2, 14881 asm: mips.ASUBD, 14882 reg: regInfo{ 14883 inputs: []inputInfo{ 14884 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14885 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14886 }, 14887 outputs: []outputInfo{ 14888 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14889 }, 14890 }, 14891 }, 14892 { 14893 name: "MULF", 14894 argLen: 2, 14895 commutative: true, 14896 asm: mips.AMULF, 14897 reg: regInfo{ 14898 inputs: []inputInfo{ 14899 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14900 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14901 }, 14902 outputs: []outputInfo{ 14903 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14904 }, 14905 }, 14906 }, 14907 { 14908 name: "MULD", 14909 argLen: 2, 14910 commutative: true, 14911 asm: mips.AMULD, 14912 reg: regInfo{ 14913 inputs: []inputInfo{ 14914 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14915 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14916 }, 14917 outputs: []outputInfo{ 14918 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14919 }, 14920 }, 14921 }, 14922 { 14923 name: "DIVF", 14924 argLen: 2, 14925 asm: mips.ADIVF, 14926 reg: regInfo{ 14927 inputs: []inputInfo{ 14928 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14929 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14930 }, 14931 outputs: []outputInfo{ 14932 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14933 }, 14934 }, 14935 }, 14936 { 14937 name: "DIVD", 14938 argLen: 2, 14939 asm: mips.ADIVD, 14940 reg: regInfo{ 14941 inputs: []inputInfo{ 14942 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14943 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14944 }, 14945 outputs: []outputInfo{ 14946 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14947 }, 14948 }, 14949 }, 14950 { 14951 name: "AND", 14952 argLen: 2, 14953 commutative: true, 14954 asm: mips.AAND, 14955 reg: regInfo{ 14956 inputs: []inputInfo{ 14957 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14958 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14959 }, 14960 outputs: []outputInfo{ 14961 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14962 }, 14963 }, 14964 }, 14965 { 14966 name: "ANDconst", 14967 auxType: auxInt32, 14968 argLen: 1, 14969 asm: mips.AAND, 14970 reg: regInfo{ 14971 inputs: []inputInfo{ 14972 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14973 }, 14974 outputs: []outputInfo{ 14975 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14976 }, 14977 }, 14978 }, 14979 { 14980 name: "OR", 14981 argLen: 2, 14982 commutative: true, 14983 asm: mips.AOR, 14984 reg: regInfo{ 14985 inputs: []inputInfo{ 14986 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14987 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14988 }, 14989 outputs: []outputInfo{ 14990 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14991 }, 14992 }, 14993 }, 14994 { 14995 name: "ORconst", 14996 auxType: auxInt32, 14997 argLen: 1, 14998 asm: mips.AOR, 14999 reg: regInfo{ 15000 inputs: []inputInfo{ 15001 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15002 }, 15003 outputs: []outputInfo{ 15004 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15005 }, 15006 }, 15007 }, 15008 { 15009 name: "XOR", 15010 argLen: 2, 15011 commutative: true, 15012 asm: mips.AXOR, 15013 reg: regInfo{ 15014 inputs: []inputInfo{ 15015 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15016 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15017 }, 15018 outputs: []outputInfo{ 15019 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15020 }, 15021 }, 15022 }, 15023 { 15024 name: "XORconst", 15025 auxType: auxInt32, 15026 argLen: 1, 15027 asm: mips.AXOR, 15028 reg: regInfo{ 15029 inputs: []inputInfo{ 15030 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15031 }, 15032 outputs: []outputInfo{ 15033 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15034 }, 15035 }, 15036 }, 15037 { 15038 name: "NOR", 15039 argLen: 2, 15040 commutative: true, 15041 asm: mips.ANOR, 15042 reg: regInfo{ 15043 inputs: []inputInfo{ 15044 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15045 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15046 }, 15047 outputs: []outputInfo{ 15048 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15049 }, 15050 }, 15051 }, 15052 { 15053 name: "NORconst", 15054 auxType: auxInt32, 15055 argLen: 1, 15056 asm: mips.ANOR, 15057 reg: regInfo{ 15058 inputs: []inputInfo{ 15059 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15060 }, 15061 outputs: []outputInfo{ 15062 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15063 }, 15064 }, 15065 }, 15066 { 15067 name: "NEG", 15068 argLen: 1, 15069 reg: regInfo{ 15070 inputs: []inputInfo{ 15071 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15072 }, 15073 outputs: []outputInfo{ 15074 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15075 }, 15076 }, 15077 }, 15078 { 15079 name: "NEGF", 15080 argLen: 1, 15081 asm: mips.ANEGF, 15082 reg: regInfo{ 15083 inputs: []inputInfo{ 15084 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15085 }, 15086 outputs: []outputInfo{ 15087 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15088 }, 15089 }, 15090 }, 15091 { 15092 name: "NEGD", 15093 argLen: 1, 15094 asm: mips.ANEGD, 15095 reg: regInfo{ 15096 inputs: []inputInfo{ 15097 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15098 }, 15099 outputs: []outputInfo{ 15100 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15101 }, 15102 }, 15103 }, 15104 { 15105 name: "SQRTD", 15106 argLen: 1, 15107 asm: mips.ASQRTD, 15108 reg: regInfo{ 15109 inputs: []inputInfo{ 15110 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15111 }, 15112 outputs: []outputInfo{ 15113 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15114 }, 15115 }, 15116 }, 15117 { 15118 name: "SLL", 15119 argLen: 2, 15120 asm: mips.ASLL, 15121 reg: regInfo{ 15122 inputs: []inputInfo{ 15123 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15124 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15125 }, 15126 outputs: []outputInfo{ 15127 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15128 }, 15129 }, 15130 }, 15131 { 15132 name: "SLLconst", 15133 auxType: auxInt32, 15134 argLen: 1, 15135 asm: mips.ASLL, 15136 reg: regInfo{ 15137 inputs: []inputInfo{ 15138 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15139 }, 15140 outputs: []outputInfo{ 15141 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15142 }, 15143 }, 15144 }, 15145 { 15146 name: "SRL", 15147 argLen: 2, 15148 asm: mips.ASRL, 15149 reg: regInfo{ 15150 inputs: []inputInfo{ 15151 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15152 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15153 }, 15154 outputs: []outputInfo{ 15155 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15156 }, 15157 }, 15158 }, 15159 { 15160 name: "SRLconst", 15161 auxType: auxInt32, 15162 argLen: 1, 15163 asm: mips.ASRL, 15164 reg: regInfo{ 15165 inputs: []inputInfo{ 15166 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15167 }, 15168 outputs: []outputInfo{ 15169 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15170 }, 15171 }, 15172 }, 15173 { 15174 name: "SRA", 15175 argLen: 2, 15176 asm: mips.ASRA, 15177 reg: regInfo{ 15178 inputs: []inputInfo{ 15179 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15180 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15181 }, 15182 outputs: []outputInfo{ 15183 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15184 }, 15185 }, 15186 }, 15187 { 15188 name: "SRAconst", 15189 auxType: auxInt32, 15190 argLen: 1, 15191 asm: mips.ASRA, 15192 reg: regInfo{ 15193 inputs: []inputInfo{ 15194 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15195 }, 15196 outputs: []outputInfo{ 15197 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15198 }, 15199 }, 15200 }, 15201 { 15202 name: "CLZ", 15203 argLen: 1, 15204 asm: mips.ACLZ, 15205 reg: regInfo{ 15206 inputs: []inputInfo{ 15207 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15208 }, 15209 outputs: []outputInfo{ 15210 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15211 }, 15212 }, 15213 }, 15214 { 15215 name: "SGT", 15216 argLen: 2, 15217 asm: mips.ASGT, 15218 reg: regInfo{ 15219 inputs: []inputInfo{ 15220 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15221 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15222 }, 15223 outputs: []outputInfo{ 15224 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15225 }, 15226 }, 15227 }, 15228 { 15229 name: "SGTconst", 15230 auxType: auxInt32, 15231 argLen: 1, 15232 asm: mips.ASGT, 15233 reg: regInfo{ 15234 inputs: []inputInfo{ 15235 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15236 }, 15237 outputs: []outputInfo{ 15238 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15239 }, 15240 }, 15241 }, 15242 { 15243 name: "SGTzero", 15244 argLen: 1, 15245 asm: mips.ASGT, 15246 reg: regInfo{ 15247 inputs: []inputInfo{ 15248 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15249 }, 15250 outputs: []outputInfo{ 15251 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15252 }, 15253 }, 15254 }, 15255 { 15256 name: "SGTU", 15257 argLen: 2, 15258 asm: mips.ASGTU, 15259 reg: regInfo{ 15260 inputs: []inputInfo{ 15261 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15262 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15263 }, 15264 outputs: []outputInfo{ 15265 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15266 }, 15267 }, 15268 }, 15269 { 15270 name: "SGTUconst", 15271 auxType: auxInt32, 15272 argLen: 1, 15273 asm: mips.ASGTU, 15274 reg: regInfo{ 15275 inputs: []inputInfo{ 15276 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15277 }, 15278 outputs: []outputInfo{ 15279 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15280 }, 15281 }, 15282 }, 15283 { 15284 name: "SGTUzero", 15285 argLen: 1, 15286 asm: mips.ASGTU, 15287 reg: regInfo{ 15288 inputs: []inputInfo{ 15289 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15290 }, 15291 outputs: []outputInfo{ 15292 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15293 }, 15294 }, 15295 }, 15296 { 15297 name: "CMPEQF", 15298 argLen: 2, 15299 asm: mips.ACMPEQF, 15300 reg: regInfo{ 15301 inputs: []inputInfo{ 15302 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15303 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15304 }, 15305 }, 15306 }, 15307 { 15308 name: "CMPEQD", 15309 argLen: 2, 15310 asm: mips.ACMPEQD, 15311 reg: regInfo{ 15312 inputs: []inputInfo{ 15313 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15314 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15315 }, 15316 }, 15317 }, 15318 { 15319 name: "CMPGEF", 15320 argLen: 2, 15321 asm: mips.ACMPGEF, 15322 reg: regInfo{ 15323 inputs: []inputInfo{ 15324 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15325 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15326 }, 15327 }, 15328 }, 15329 { 15330 name: "CMPGED", 15331 argLen: 2, 15332 asm: mips.ACMPGED, 15333 reg: regInfo{ 15334 inputs: []inputInfo{ 15335 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15336 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15337 }, 15338 }, 15339 }, 15340 { 15341 name: "CMPGTF", 15342 argLen: 2, 15343 asm: mips.ACMPGTF, 15344 reg: regInfo{ 15345 inputs: []inputInfo{ 15346 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15347 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15348 }, 15349 }, 15350 }, 15351 { 15352 name: "CMPGTD", 15353 argLen: 2, 15354 asm: mips.ACMPGTD, 15355 reg: regInfo{ 15356 inputs: []inputInfo{ 15357 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15358 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15359 }, 15360 }, 15361 }, 15362 { 15363 name: "MOVWconst", 15364 auxType: auxInt32, 15365 argLen: 0, 15366 rematerializeable: true, 15367 asm: mips.AMOVW, 15368 reg: regInfo{ 15369 outputs: []outputInfo{ 15370 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15371 }, 15372 }, 15373 }, 15374 { 15375 name: "MOVFconst", 15376 auxType: auxFloat32, 15377 argLen: 0, 15378 rematerializeable: true, 15379 asm: mips.AMOVF, 15380 reg: regInfo{ 15381 outputs: []outputInfo{ 15382 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15383 }, 15384 }, 15385 }, 15386 { 15387 name: "MOVDconst", 15388 auxType: auxFloat64, 15389 argLen: 0, 15390 rematerializeable: true, 15391 asm: mips.AMOVD, 15392 reg: regInfo{ 15393 outputs: []outputInfo{ 15394 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15395 }, 15396 }, 15397 }, 15398 { 15399 name: "MOVWaddr", 15400 auxType: auxSymOff, 15401 argLen: 1, 15402 rematerializeable: true, 15403 symEffect: SymAddr, 15404 asm: mips.AMOVW, 15405 reg: regInfo{ 15406 inputs: []inputInfo{ 15407 {0, 140737555464192}, // SP SB 15408 }, 15409 outputs: []outputInfo{ 15410 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15411 }, 15412 }, 15413 }, 15414 { 15415 name: "MOVBload", 15416 auxType: auxSymOff, 15417 argLen: 2, 15418 faultOnNilArg0: true, 15419 symEffect: SymRead, 15420 asm: mips.AMOVB, 15421 reg: regInfo{ 15422 inputs: []inputInfo{ 15423 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15424 }, 15425 outputs: []outputInfo{ 15426 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15427 }, 15428 }, 15429 }, 15430 { 15431 name: "MOVBUload", 15432 auxType: auxSymOff, 15433 argLen: 2, 15434 faultOnNilArg0: true, 15435 symEffect: SymRead, 15436 asm: mips.AMOVBU, 15437 reg: regInfo{ 15438 inputs: []inputInfo{ 15439 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15440 }, 15441 outputs: []outputInfo{ 15442 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15443 }, 15444 }, 15445 }, 15446 { 15447 name: "MOVHload", 15448 auxType: auxSymOff, 15449 argLen: 2, 15450 faultOnNilArg0: true, 15451 symEffect: SymRead, 15452 asm: mips.AMOVH, 15453 reg: regInfo{ 15454 inputs: []inputInfo{ 15455 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15456 }, 15457 outputs: []outputInfo{ 15458 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15459 }, 15460 }, 15461 }, 15462 { 15463 name: "MOVHUload", 15464 auxType: auxSymOff, 15465 argLen: 2, 15466 faultOnNilArg0: true, 15467 symEffect: SymRead, 15468 asm: mips.AMOVHU, 15469 reg: regInfo{ 15470 inputs: []inputInfo{ 15471 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15472 }, 15473 outputs: []outputInfo{ 15474 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15475 }, 15476 }, 15477 }, 15478 { 15479 name: "MOVWload", 15480 auxType: auxSymOff, 15481 argLen: 2, 15482 faultOnNilArg0: true, 15483 symEffect: SymRead, 15484 asm: mips.AMOVW, 15485 reg: regInfo{ 15486 inputs: []inputInfo{ 15487 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15488 }, 15489 outputs: []outputInfo{ 15490 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15491 }, 15492 }, 15493 }, 15494 { 15495 name: "MOVFload", 15496 auxType: auxSymOff, 15497 argLen: 2, 15498 faultOnNilArg0: true, 15499 symEffect: SymRead, 15500 asm: mips.AMOVF, 15501 reg: regInfo{ 15502 inputs: []inputInfo{ 15503 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15504 }, 15505 outputs: []outputInfo{ 15506 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15507 }, 15508 }, 15509 }, 15510 { 15511 name: "MOVDload", 15512 auxType: auxSymOff, 15513 argLen: 2, 15514 faultOnNilArg0: true, 15515 symEffect: SymRead, 15516 asm: mips.AMOVD, 15517 reg: regInfo{ 15518 inputs: []inputInfo{ 15519 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15520 }, 15521 outputs: []outputInfo{ 15522 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15523 }, 15524 }, 15525 }, 15526 { 15527 name: "MOVBstore", 15528 auxType: auxSymOff, 15529 argLen: 3, 15530 faultOnNilArg0: true, 15531 symEffect: SymWrite, 15532 asm: mips.AMOVB, 15533 reg: regInfo{ 15534 inputs: []inputInfo{ 15535 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15536 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15537 }, 15538 }, 15539 }, 15540 { 15541 name: "MOVHstore", 15542 auxType: auxSymOff, 15543 argLen: 3, 15544 faultOnNilArg0: true, 15545 symEffect: SymWrite, 15546 asm: mips.AMOVH, 15547 reg: regInfo{ 15548 inputs: []inputInfo{ 15549 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15550 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15551 }, 15552 }, 15553 }, 15554 { 15555 name: "MOVWstore", 15556 auxType: auxSymOff, 15557 argLen: 3, 15558 faultOnNilArg0: true, 15559 symEffect: SymWrite, 15560 asm: mips.AMOVW, 15561 reg: regInfo{ 15562 inputs: []inputInfo{ 15563 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15564 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15565 }, 15566 }, 15567 }, 15568 { 15569 name: "MOVFstore", 15570 auxType: auxSymOff, 15571 argLen: 3, 15572 faultOnNilArg0: true, 15573 symEffect: SymWrite, 15574 asm: mips.AMOVF, 15575 reg: regInfo{ 15576 inputs: []inputInfo{ 15577 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15578 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15579 }, 15580 }, 15581 }, 15582 { 15583 name: "MOVDstore", 15584 auxType: auxSymOff, 15585 argLen: 3, 15586 faultOnNilArg0: true, 15587 symEffect: SymWrite, 15588 asm: mips.AMOVD, 15589 reg: regInfo{ 15590 inputs: []inputInfo{ 15591 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15592 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15593 }, 15594 }, 15595 }, 15596 { 15597 name: "MOVBstorezero", 15598 auxType: auxSymOff, 15599 argLen: 2, 15600 faultOnNilArg0: true, 15601 symEffect: SymWrite, 15602 asm: mips.AMOVB, 15603 reg: regInfo{ 15604 inputs: []inputInfo{ 15605 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15606 }, 15607 }, 15608 }, 15609 { 15610 name: "MOVHstorezero", 15611 auxType: auxSymOff, 15612 argLen: 2, 15613 faultOnNilArg0: true, 15614 symEffect: SymWrite, 15615 asm: mips.AMOVH, 15616 reg: regInfo{ 15617 inputs: []inputInfo{ 15618 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15619 }, 15620 }, 15621 }, 15622 { 15623 name: "MOVWstorezero", 15624 auxType: auxSymOff, 15625 argLen: 2, 15626 faultOnNilArg0: true, 15627 symEffect: SymWrite, 15628 asm: mips.AMOVW, 15629 reg: regInfo{ 15630 inputs: []inputInfo{ 15631 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15632 }, 15633 }, 15634 }, 15635 { 15636 name: "MOVBreg", 15637 argLen: 1, 15638 asm: mips.AMOVB, 15639 reg: regInfo{ 15640 inputs: []inputInfo{ 15641 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15642 }, 15643 outputs: []outputInfo{ 15644 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15645 }, 15646 }, 15647 }, 15648 { 15649 name: "MOVBUreg", 15650 argLen: 1, 15651 asm: mips.AMOVBU, 15652 reg: regInfo{ 15653 inputs: []inputInfo{ 15654 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15655 }, 15656 outputs: []outputInfo{ 15657 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15658 }, 15659 }, 15660 }, 15661 { 15662 name: "MOVHreg", 15663 argLen: 1, 15664 asm: mips.AMOVH, 15665 reg: regInfo{ 15666 inputs: []inputInfo{ 15667 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15668 }, 15669 outputs: []outputInfo{ 15670 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15671 }, 15672 }, 15673 }, 15674 { 15675 name: "MOVHUreg", 15676 argLen: 1, 15677 asm: mips.AMOVHU, 15678 reg: regInfo{ 15679 inputs: []inputInfo{ 15680 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15681 }, 15682 outputs: []outputInfo{ 15683 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15684 }, 15685 }, 15686 }, 15687 { 15688 name: "MOVWreg", 15689 argLen: 1, 15690 asm: mips.AMOVW, 15691 reg: regInfo{ 15692 inputs: []inputInfo{ 15693 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15694 }, 15695 outputs: []outputInfo{ 15696 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15697 }, 15698 }, 15699 }, 15700 { 15701 name: "MOVWnop", 15702 argLen: 1, 15703 resultInArg0: true, 15704 reg: regInfo{ 15705 inputs: []inputInfo{ 15706 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15707 }, 15708 outputs: []outputInfo{ 15709 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15710 }, 15711 }, 15712 }, 15713 { 15714 name: "CMOVZ", 15715 argLen: 3, 15716 resultInArg0: true, 15717 asm: mips.ACMOVZ, 15718 reg: regInfo{ 15719 inputs: []inputInfo{ 15720 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15721 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15722 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15723 }, 15724 outputs: []outputInfo{ 15725 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15726 }, 15727 }, 15728 }, 15729 { 15730 name: "CMOVZzero", 15731 argLen: 2, 15732 resultInArg0: true, 15733 asm: mips.ACMOVZ, 15734 reg: regInfo{ 15735 inputs: []inputInfo{ 15736 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15737 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15738 }, 15739 outputs: []outputInfo{ 15740 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15741 }, 15742 }, 15743 }, 15744 { 15745 name: "MOVWF", 15746 argLen: 1, 15747 asm: mips.AMOVWF, 15748 reg: regInfo{ 15749 inputs: []inputInfo{ 15750 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15751 }, 15752 outputs: []outputInfo{ 15753 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15754 }, 15755 }, 15756 }, 15757 { 15758 name: "MOVWD", 15759 argLen: 1, 15760 asm: mips.AMOVWD, 15761 reg: regInfo{ 15762 inputs: []inputInfo{ 15763 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15764 }, 15765 outputs: []outputInfo{ 15766 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15767 }, 15768 }, 15769 }, 15770 { 15771 name: "TRUNCFW", 15772 argLen: 1, 15773 asm: mips.ATRUNCFW, 15774 reg: regInfo{ 15775 inputs: []inputInfo{ 15776 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15777 }, 15778 outputs: []outputInfo{ 15779 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15780 }, 15781 }, 15782 }, 15783 { 15784 name: "TRUNCDW", 15785 argLen: 1, 15786 asm: mips.ATRUNCDW, 15787 reg: regInfo{ 15788 inputs: []inputInfo{ 15789 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15790 }, 15791 outputs: []outputInfo{ 15792 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15793 }, 15794 }, 15795 }, 15796 { 15797 name: "MOVFD", 15798 argLen: 1, 15799 asm: mips.AMOVFD, 15800 reg: regInfo{ 15801 inputs: []inputInfo{ 15802 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15803 }, 15804 outputs: []outputInfo{ 15805 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15806 }, 15807 }, 15808 }, 15809 { 15810 name: "MOVDF", 15811 argLen: 1, 15812 asm: mips.AMOVDF, 15813 reg: regInfo{ 15814 inputs: []inputInfo{ 15815 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15816 }, 15817 outputs: []outputInfo{ 15818 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15819 }, 15820 }, 15821 }, 15822 { 15823 name: "CALLstatic", 15824 auxType: auxSymOff, 15825 argLen: 1, 15826 clobberFlags: true, 15827 call: true, 15828 symEffect: SymNone, 15829 reg: regInfo{ 15830 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15831 }, 15832 }, 15833 { 15834 name: "CALLclosure", 15835 auxType: auxInt64, 15836 argLen: 3, 15837 clobberFlags: true, 15838 call: true, 15839 reg: regInfo{ 15840 inputs: []inputInfo{ 15841 {1, 4194304}, // R22 15842 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 15843 }, 15844 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15845 }, 15846 }, 15847 { 15848 name: "CALLinter", 15849 auxType: auxInt64, 15850 argLen: 2, 15851 clobberFlags: true, 15852 call: true, 15853 reg: regInfo{ 15854 inputs: []inputInfo{ 15855 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15856 }, 15857 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15858 }, 15859 }, 15860 { 15861 name: "LoweredAtomicLoad", 15862 argLen: 2, 15863 faultOnNilArg0: true, 15864 reg: regInfo{ 15865 inputs: []inputInfo{ 15866 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15867 }, 15868 outputs: []outputInfo{ 15869 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15870 }, 15871 }, 15872 }, 15873 { 15874 name: "LoweredAtomicStore", 15875 argLen: 3, 15876 faultOnNilArg0: true, 15877 hasSideEffects: true, 15878 reg: regInfo{ 15879 inputs: []inputInfo{ 15880 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15881 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15882 }, 15883 }, 15884 }, 15885 { 15886 name: "LoweredAtomicStorezero", 15887 argLen: 2, 15888 faultOnNilArg0: true, 15889 hasSideEffects: true, 15890 reg: regInfo{ 15891 inputs: []inputInfo{ 15892 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15893 }, 15894 }, 15895 }, 15896 { 15897 name: "LoweredAtomicExchange", 15898 argLen: 3, 15899 resultNotInArgs: true, 15900 faultOnNilArg0: true, 15901 hasSideEffects: true, 15902 reg: regInfo{ 15903 inputs: []inputInfo{ 15904 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15905 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15906 }, 15907 outputs: []outputInfo{ 15908 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15909 }, 15910 }, 15911 }, 15912 { 15913 name: "LoweredAtomicAdd", 15914 argLen: 3, 15915 resultNotInArgs: true, 15916 faultOnNilArg0: true, 15917 hasSideEffects: true, 15918 reg: regInfo{ 15919 inputs: []inputInfo{ 15920 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15921 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15922 }, 15923 outputs: []outputInfo{ 15924 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15925 }, 15926 }, 15927 }, 15928 { 15929 name: "LoweredAtomicAddconst", 15930 auxType: auxInt32, 15931 argLen: 2, 15932 resultNotInArgs: true, 15933 faultOnNilArg0: true, 15934 hasSideEffects: true, 15935 reg: regInfo{ 15936 inputs: []inputInfo{ 15937 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15938 }, 15939 outputs: []outputInfo{ 15940 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15941 }, 15942 }, 15943 }, 15944 { 15945 name: "LoweredAtomicCas", 15946 argLen: 4, 15947 resultNotInArgs: true, 15948 faultOnNilArg0: true, 15949 hasSideEffects: true, 15950 reg: regInfo{ 15951 inputs: []inputInfo{ 15952 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15953 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15954 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15955 }, 15956 outputs: []outputInfo{ 15957 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15958 }, 15959 }, 15960 }, 15961 { 15962 name: "LoweredAtomicAnd", 15963 argLen: 3, 15964 faultOnNilArg0: true, 15965 hasSideEffects: true, 15966 asm: mips.AAND, 15967 reg: regInfo{ 15968 inputs: []inputInfo{ 15969 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15970 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15971 }, 15972 }, 15973 }, 15974 { 15975 name: "LoweredAtomicOr", 15976 argLen: 3, 15977 faultOnNilArg0: true, 15978 hasSideEffects: true, 15979 asm: mips.AOR, 15980 reg: regInfo{ 15981 inputs: []inputInfo{ 15982 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15983 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15984 }, 15985 }, 15986 }, 15987 { 15988 name: "LoweredZero", 15989 auxType: auxInt32, 15990 argLen: 3, 15991 faultOnNilArg0: true, 15992 reg: regInfo{ 15993 inputs: []inputInfo{ 15994 {0, 2}, // R1 15995 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15996 }, 15997 clobbers: 2, // R1 15998 }, 15999 }, 16000 { 16001 name: "LoweredMove", 16002 auxType: auxInt32, 16003 argLen: 4, 16004 faultOnNilArg0: true, 16005 faultOnNilArg1: true, 16006 reg: regInfo{ 16007 inputs: []inputInfo{ 16008 {0, 4}, // R2 16009 {1, 2}, // R1 16010 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 16011 }, 16012 clobbers: 6, // R1 R2 16013 }, 16014 }, 16015 { 16016 name: "LoweredNilCheck", 16017 argLen: 2, 16018 nilCheck: true, 16019 faultOnNilArg0: true, 16020 reg: regInfo{ 16021 inputs: []inputInfo{ 16022 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 16023 }, 16024 }, 16025 }, 16026 { 16027 name: "FPFlagTrue", 16028 argLen: 1, 16029 reg: regInfo{ 16030 outputs: []outputInfo{ 16031 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 16032 }, 16033 }, 16034 }, 16035 { 16036 name: "FPFlagFalse", 16037 argLen: 1, 16038 reg: regInfo{ 16039 outputs: []outputInfo{ 16040 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 16041 }, 16042 }, 16043 }, 16044 { 16045 name: "LoweredGetClosurePtr", 16046 argLen: 0, 16047 reg: regInfo{ 16048 outputs: []outputInfo{ 16049 {0, 4194304}, // R22 16050 }, 16051 }, 16052 }, 16053 { 16054 name: "LoweredGetCallerSP", 16055 argLen: 0, 16056 rematerializeable: true, 16057 reg: regInfo{ 16058 outputs: []outputInfo{ 16059 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 16060 }, 16061 }, 16062 }, 16063 { 16064 name: "LoweredWB", 16065 auxType: auxSym, 16066 argLen: 3, 16067 clobberFlags: true, 16068 symEffect: SymNone, 16069 reg: regInfo{ 16070 inputs: []inputInfo{ 16071 {0, 1048576}, // R20 16072 {1, 2097152}, // R21 16073 }, 16074 clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 16075 }, 16076 }, 16077 { 16078 name: "MOVWconvert", 16079 argLen: 2, 16080 asm: mips.AMOVW, 16081 reg: regInfo{ 16082 inputs: []inputInfo{ 16083 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 16084 }, 16085 outputs: []outputInfo{ 16086 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 16087 }, 16088 }, 16089 }, 16090 16091 { 16092 name: "ADDV", 16093 argLen: 2, 16094 commutative: true, 16095 asm: mips.AADDVU, 16096 reg: regInfo{ 16097 inputs: []inputInfo{ 16098 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16099 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16100 }, 16101 outputs: []outputInfo{ 16102 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16103 }, 16104 }, 16105 }, 16106 { 16107 name: "ADDVconst", 16108 auxType: auxInt64, 16109 argLen: 1, 16110 asm: mips.AADDVU, 16111 reg: regInfo{ 16112 inputs: []inputInfo{ 16113 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 16114 }, 16115 outputs: []outputInfo{ 16116 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16117 }, 16118 }, 16119 }, 16120 { 16121 name: "SUBV", 16122 argLen: 2, 16123 asm: mips.ASUBVU, 16124 reg: regInfo{ 16125 inputs: []inputInfo{ 16126 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16127 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16128 }, 16129 outputs: []outputInfo{ 16130 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16131 }, 16132 }, 16133 }, 16134 { 16135 name: "SUBVconst", 16136 auxType: auxInt64, 16137 argLen: 1, 16138 asm: mips.ASUBVU, 16139 reg: regInfo{ 16140 inputs: []inputInfo{ 16141 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16142 }, 16143 outputs: []outputInfo{ 16144 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16145 }, 16146 }, 16147 }, 16148 { 16149 name: "MULV", 16150 argLen: 2, 16151 commutative: true, 16152 asm: mips.AMULV, 16153 reg: regInfo{ 16154 inputs: []inputInfo{ 16155 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16156 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16157 }, 16158 outputs: []outputInfo{ 16159 {0, 1152921504606846976}, // HI 16160 {1, 2305843009213693952}, // LO 16161 }, 16162 }, 16163 }, 16164 { 16165 name: "MULVU", 16166 argLen: 2, 16167 commutative: true, 16168 asm: mips.AMULVU, 16169 reg: regInfo{ 16170 inputs: []inputInfo{ 16171 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16172 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16173 }, 16174 outputs: []outputInfo{ 16175 {0, 1152921504606846976}, // HI 16176 {1, 2305843009213693952}, // LO 16177 }, 16178 }, 16179 }, 16180 { 16181 name: "DIVV", 16182 argLen: 2, 16183 asm: mips.ADIVV, 16184 reg: regInfo{ 16185 inputs: []inputInfo{ 16186 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16187 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16188 }, 16189 outputs: []outputInfo{ 16190 {0, 1152921504606846976}, // HI 16191 {1, 2305843009213693952}, // LO 16192 }, 16193 }, 16194 }, 16195 { 16196 name: "DIVVU", 16197 argLen: 2, 16198 asm: mips.ADIVVU, 16199 reg: regInfo{ 16200 inputs: []inputInfo{ 16201 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16202 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16203 }, 16204 outputs: []outputInfo{ 16205 {0, 1152921504606846976}, // HI 16206 {1, 2305843009213693952}, // LO 16207 }, 16208 }, 16209 }, 16210 { 16211 name: "ADDF", 16212 argLen: 2, 16213 commutative: true, 16214 asm: mips.AADDF, 16215 reg: regInfo{ 16216 inputs: []inputInfo{ 16217 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16218 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16219 }, 16220 outputs: []outputInfo{ 16221 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16222 }, 16223 }, 16224 }, 16225 { 16226 name: "ADDD", 16227 argLen: 2, 16228 commutative: true, 16229 asm: mips.AADDD, 16230 reg: regInfo{ 16231 inputs: []inputInfo{ 16232 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16233 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16234 }, 16235 outputs: []outputInfo{ 16236 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16237 }, 16238 }, 16239 }, 16240 { 16241 name: "SUBF", 16242 argLen: 2, 16243 asm: mips.ASUBF, 16244 reg: regInfo{ 16245 inputs: []inputInfo{ 16246 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16247 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16248 }, 16249 outputs: []outputInfo{ 16250 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16251 }, 16252 }, 16253 }, 16254 { 16255 name: "SUBD", 16256 argLen: 2, 16257 asm: mips.ASUBD, 16258 reg: regInfo{ 16259 inputs: []inputInfo{ 16260 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16261 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16262 }, 16263 outputs: []outputInfo{ 16264 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16265 }, 16266 }, 16267 }, 16268 { 16269 name: "MULF", 16270 argLen: 2, 16271 commutative: true, 16272 asm: mips.AMULF, 16273 reg: regInfo{ 16274 inputs: []inputInfo{ 16275 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16276 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16277 }, 16278 outputs: []outputInfo{ 16279 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16280 }, 16281 }, 16282 }, 16283 { 16284 name: "MULD", 16285 argLen: 2, 16286 commutative: true, 16287 asm: mips.AMULD, 16288 reg: regInfo{ 16289 inputs: []inputInfo{ 16290 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16291 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16292 }, 16293 outputs: []outputInfo{ 16294 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16295 }, 16296 }, 16297 }, 16298 { 16299 name: "DIVF", 16300 argLen: 2, 16301 asm: mips.ADIVF, 16302 reg: regInfo{ 16303 inputs: []inputInfo{ 16304 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16305 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16306 }, 16307 outputs: []outputInfo{ 16308 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16309 }, 16310 }, 16311 }, 16312 { 16313 name: "DIVD", 16314 argLen: 2, 16315 asm: mips.ADIVD, 16316 reg: regInfo{ 16317 inputs: []inputInfo{ 16318 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16319 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16320 }, 16321 outputs: []outputInfo{ 16322 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16323 }, 16324 }, 16325 }, 16326 { 16327 name: "AND", 16328 argLen: 2, 16329 commutative: true, 16330 asm: mips.AAND, 16331 reg: regInfo{ 16332 inputs: []inputInfo{ 16333 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16334 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16335 }, 16336 outputs: []outputInfo{ 16337 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16338 }, 16339 }, 16340 }, 16341 { 16342 name: "ANDconst", 16343 auxType: auxInt64, 16344 argLen: 1, 16345 asm: mips.AAND, 16346 reg: regInfo{ 16347 inputs: []inputInfo{ 16348 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16349 }, 16350 outputs: []outputInfo{ 16351 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16352 }, 16353 }, 16354 }, 16355 { 16356 name: "OR", 16357 argLen: 2, 16358 commutative: true, 16359 asm: mips.AOR, 16360 reg: regInfo{ 16361 inputs: []inputInfo{ 16362 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16363 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16364 }, 16365 outputs: []outputInfo{ 16366 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16367 }, 16368 }, 16369 }, 16370 { 16371 name: "ORconst", 16372 auxType: auxInt64, 16373 argLen: 1, 16374 asm: mips.AOR, 16375 reg: regInfo{ 16376 inputs: []inputInfo{ 16377 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16378 }, 16379 outputs: []outputInfo{ 16380 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16381 }, 16382 }, 16383 }, 16384 { 16385 name: "XOR", 16386 argLen: 2, 16387 commutative: true, 16388 asm: mips.AXOR, 16389 reg: regInfo{ 16390 inputs: []inputInfo{ 16391 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16392 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16393 }, 16394 outputs: []outputInfo{ 16395 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16396 }, 16397 }, 16398 }, 16399 { 16400 name: "XORconst", 16401 auxType: auxInt64, 16402 argLen: 1, 16403 asm: mips.AXOR, 16404 reg: regInfo{ 16405 inputs: []inputInfo{ 16406 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16407 }, 16408 outputs: []outputInfo{ 16409 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16410 }, 16411 }, 16412 }, 16413 { 16414 name: "NOR", 16415 argLen: 2, 16416 commutative: true, 16417 asm: mips.ANOR, 16418 reg: regInfo{ 16419 inputs: []inputInfo{ 16420 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16421 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16422 }, 16423 outputs: []outputInfo{ 16424 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16425 }, 16426 }, 16427 }, 16428 { 16429 name: "NORconst", 16430 auxType: auxInt64, 16431 argLen: 1, 16432 asm: mips.ANOR, 16433 reg: regInfo{ 16434 inputs: []inputInfo{ 16435 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16436 }, 16437 outputs: []outputInfo{ 16438 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16439 }, 16440 }, 16441 }, 16442 { 16443 name: "NEGV", 16444 argLen: 1, 16445 reg: regInfo{ 16446 inputs: []inputInfo{ 16447 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16448 }, 16449 outputs: []outputInfo{ 16450 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16451 }, 16452 }, 16453 }, 16454 { 16455 name: "NEGF", 16456 argLen: 1, 16457 asm: mips.ANEGF, 16458 reg: regInfo{ 16459 inputs: []inputInfo{ 16460 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16461 }, 16462 outputs: []outputInfo{ 16463 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16464 }, 16465 }, 16466 }, 16467 { 16468 name: "NEGD", 16469 argLen: 1, 16470 asm: mips.ANEGD, 16471 reg: regInfo{ 16472 inputs: []inputInfo{ 16473 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16474 }, 16475 outputs: []outputInfo{ 16476 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16477 }, 16478 }, 16479 }, 16480 { 16481 name: "SQRTD", 16482 argLen: 1, 16483 asm: mips.ASQRTD, 16484 reg: regInfo{ 16485 inputs: []inputInfo{ 16486 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16487 }, 16488 outputs: []outputInfo{ 16489 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16490 }, 16491 }, 16492 }, 16493 { 16494 name: "SLLV", 16495 argLen: 2, 16496 asm: mips.ASLLV, 16497 reg: regInfo{ 16498 inputs: []inputInfo{ 16499 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16500 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16501 }, 16502 outputs: []outputInfo{ 16503 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16504 }, 16505 }, 16506 }, 16507 { 16508 name: "SLLVconst", 16509 auxType: auxInt64, 16510 argLen: 1, 16511 asm: mips.ASLLV, 16512 reg: regInfo{ 16513 inputs: []inputInfo{ 16514 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16515 }, 16516 outputs: []outputInfo{ 16517 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16518 }, 16519 }, 16520 }, 16521 { 16522 name: "SRLV", 16523 argLen: 2, 16524 asm: mips.ASRLV, 16525 reg: regInfo{ 16526 inputs: []inputInfo{ 16527 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16528 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16529 }, 16530 outputs: []outputInfo{ 16531 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16532 }, 16533 }, 16534 }, 16535 { 16536 name: "SRLVconst", 16537 auxType: auxInt64, 16538 argLen: 1, 16539 asm: mips.ASRLV, 16540 reg: regInfo{ 16541 inputs: []inputInfo{ 16542 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16543 }, 16544 outputs: []outputInfo{ 16545 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16546 }, 16547 }, 16548 }, 16549 { 16550 name: "SRAV", 16551 argLen: 2, 16552 asm: mips.ASRAV, 16553 reg: regInfo{ 16554 inputs: []inputInfo{ 16555 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16556 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16557 }, 16558 outputs: []outputInfo{ 16559 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16560 }, 16561 }, 16562 }, 16563 { 16564 name: "SRAVconst", 16565 auxType: auxInt64, 16566 argLen: 1, 16567 asm: mips.ASRAV, 16568 reg: regInfo{ 16569 inputs: []inputInfo{ 16570 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16571 }, 16572 outputs: []outputInfo{ 16573 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16574 }, 16575 }, 16576 }, 16577 { 16578 name: "SGT", 16579 argLen: 2, 16580 asm: mips.ASGT, 16581 reg: regInfo{ 16582 inputs: []inputInfo{ 16583 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16584 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16585 }, 16586 outputs: []outputInfo{ 16587 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16588 }, 16589 }, 16590 }, 16591 { 16592 name: "SGTconst", 16593 auxType: auxInt64, 16594 argLen: 1, 16595 asm: mips.ASGT, 16596 reg: regInfo{ 16597 inputs: []inputInfo{ 16598 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16599 }, 16600 outputs: []outputInfo{ 16601 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16602 }, 16603 }, 16604 }, 16605 { 16606 name: "SGTU", 16607 argLen: 2, 16608 asm: mips.ASGTU, 16609 reg: regInfo{ 16610 inputs: []inputInfo{ 16611 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16612 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16613 }, 16614 outputs: []outputInfo{ 16615 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16616 }, 16617 }, 16618 }, 16619 { 16620 name: "SGTUconst", 16621 auxType: auxInt64, 16622 argLen: 1, 16623 asm: mips.ASGTU, 16624 reg: regInfo{ 16625 inputs: []inputInfo{ 16626 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16627 }, 16628 outputs: []outputInfo{ 16629 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16630 }, 16631 }, 16632 }, 16633 { 16634 name: "CMPEQF", 16635 argLen: 2, 16636 asm: mips.ACMPEQF, 16637 reg: regInfo{ 16638 inputs: []inputInfo{ 16639 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16640 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16641 }, 16642 }, 16643 }, 16644 { 16645 name: "CMPEQD", 16646 argLen: 2, 16647 asm: mips.ACMPEQD, 16648 reg: regInfo{ 16649 inputs: []inputInfo{ 16650 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16651 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16652 }, 16653 }, 16654 }, 16655 { 16656 name: "CMPGEF", 16657 argLen: 2, 16658 asm: mips.ACMPGEF, 16659 reg: regInfo{ 16660 inputs: []inputInfo{ 16661 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16662 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16663 }, 16664 }, 16665 }, 16666 { 16667 name: "CMPGED", 16668 argLen: 2, 16669 asm: mips.ACMPGED, 16670 reg: regInfo{ 16671 inputs: []inputInfo{ 16672 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16673 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16674 }, 16675 }, 16676 }, 16677 { 16678 name: "CMPGTF", 16679 argLen: 2, 16680 asm: mips.ACMPGTF, 16681 reg: regInfo{ 16682 inputs: []inputInfo{ 16683 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16684 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16685 }, 16686 }, 16687 }, 16688 { 16689 name: "CMPGTD", 16690 argLen: 2, 16691 asm: mips.ACMPGTD, 16692 reg: regInfo{ 16693 inputs: []inputInfo{ 16694 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16695 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16696 }, 16697 }, 16698 }, 16699 { 16700 name: "MOVVconst", 16701 auxType: auxInt64, 16702 argLen: 0, 16703 rematerializeable: true, 16704 asm: mips.AMOVV, 16705 reg: regInfo{ 16706 outputs: []outputInfo{ 16707 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16708 }, 16709 }, 16710 }, 16711 { 16712 name: "MOVFconst", 16713 auxType: auxFloat64, 16714 argLen: 0, 16715 rematerializeable: true, 16716 asm: mips.AMOVF, 16717 reg: regInfo{ 16718 outputs: []outputInfo{ 16719 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16720 }, 16721 }, 16722 }, 16723 { 16724 name: "MOVDconst", 16725 auxType: auxFloat64, 16726 argLen: 0, 16727 rematerializeable: true, 16728 asm: mips.AMOVD, 16729 reg: regInfo{ 16730 outputs: []outputInfo{ 16731 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16732 }, 16733 }, 16734 }, 16735 { 16736 name: "MOVVaddr", 16737 auxType: auxSymOff, 16738 argLen: 1, 16739 rematerializeable: true, 16740 symEffect: SymAddr, 16741 asm: mips.AMOVV, 16742 reg: regInfo{ 16743 inputs: []inputInfo{ 16744 {0, 4611686018460942336}, // SP SB 16745 }, 16746 outputs: []outputInfo{ 16747 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16748 }, 16749 }, 16750 }, 16751 { 16752 name: "MOVBload", 16753 auxType: auxSymOff, 16754 argLen: 2, 16755 faultOnNilArg0: true, 16756 symEffect: SymRead, 16757 asm: mips.AMOVB, 16758 reg: regInfo{ 16759 inputs: []inputInfo{ 16760 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16761 }, 16762 outputs: []outputInfo{ 16763 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16764 }, 16765 }, 16766 }, 16767 { 16768 name: "MOVBUload", 16769 auxType: auxSymOff, 16770 argLen: 2, 16771 faultOnNilArg0: true, 16772 symEffect: SymRead, 16773 asm: mips.AMOVBU, 16774 reg: regInfo{ 16775 inputs: []inputInfo{ 16776 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16777 }, 16778 outputs: []outputInfo{ 16779 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16780 }, 16781 }, 16782 }, 16783 { 16784 name: "MOVHload", 16785 auxType: auxSymOff, 16786 argLen: 2, 16787 faultOnNilArg0: true, 16788 symEffect: SymRead, 16789 asm: mips.AMOVH, 16790 reg: regInfo{ 16791 inputs: []inputInfo{ 16792 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16793 }, 16794 outputs: []outputInfo{ 16795 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16796 }, 16797 }, 16798 }, 16799 { 16800 name: "MOVHUload", 16801 auxType: auxSymOff, 16802 argLen: 2, 16803 faultOnNilArg0: true, 16804 symEffect: SymRead, 16805 asm: mips.AMOVHU, 16806 reg: regInfo{ 16807 inputs: []inputInfo{ 16808 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16809 }, 16810 outputs: []outputInfo{ 16811 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16812 }, 16813 }, 16814 }, 16815 { 16816 name: "MOVWload", 16817 auxType: auxSymOff, 16818 argLen: 2, 16819 faultOnNilArg0: true, 16820 symEffect: SymRead, 16821 asm: mips.AMOVW, 16822 reg: regInfo{ 16823 inputs: []inputInfo{ 16824 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16825 }, 16826 outputs: []outputInfo{ 16827 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16828 }, 16829 }, 16830 }, 16831 { 16832 name: "MOVWUload", 16833 auxType: auxSymOff, 16834 argLen: 2, 16835 faultOnNilArg0: true, 16836 symEffect: SymRead, 16837 asm: mips.AMOVWU, 16838 reg: regInfo{ 16839 inputs: []inputInfo{ 16840 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16841 }, 16842 outputs: []outputInfo{ 16843 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16844 }, 16845 }, 16846 }, 16847 { 16848 name: "MOVVload", 16849 auxType: auxSymOff, 16850 argLen: 2, 16851 faultOnNilArg0: true, 16852 symEffect: SymRead, 16853 asm: mips.AMOVV, 16854 reg: regInfo{ 16855 inputs: []inputInfo{ 16856 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16857 }, 16858 outputs: []outputInfo{ 16859 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16860 }, 16861 }, 16862 }, 16863 { 16864 name: "MOVFload", 16865 auxType: auxSymOff, 16866 argLen: 2, 16867 faultOnNilArg0: true, 16868 symEffect: SymRead, 16869 asm: mips.AMOVF, 16870 reg: regInfo{ 16871 inputs: []inputInfo{ 16872 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16873 }, 16874 outputs: []outputInfo{ 16875 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16876 }, 16877 }, 16878 }, 16879 { 16880 name: "MOVDload", 16881 auxType: auxSymOff, 16882 argLen: 2, 16883 faultOnNilArg0: true, 16884 symEffect: SymRead, 16885 asm: mips.AMOVD, 16886 reg: regInfo{ 16887 inputs: []inputInfo{ 16888 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16889 }, 16890 outputs: []outputInfo{ 16891 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16892 }, 16893 }, 16894 }, 16895 { 16896 name: "MOVBstore", 16897 auxType: auxSymOff, 16898 argLen: 3, 16899 faultOnNilArg0: true, 16900 symEffect: SymWrite, 16901 asm: mips.AMOVB, 16902 reg: regInfo{ 16903 inputs: []inputInfo{ 16904 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16905 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16906 }, 16907 }, 16908 }, 16909 { 16910 name: "MOVHstore", 16911 auxType: auxSymOff, 16912 argLen: 3, 16913 faultOnNilArg0: true, 16914 symEffect: SymWrite, 16915 asm: mips.AMOVH, 16916 reg: regInfo{ 16917 inputs: []inputInfo{ 16918 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16919 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16920 }, 16921 }, 16922 }, 16923 { 16924 name: "MOVWstore", 16925 auxType: auxSymOff, 16926 argLen: 3, 16927 faultOnNilArg0: true, 16928 symEffect: SymWrite, 16929 asm: mips.AMOVW, 16930 reg: regInfo{ 16931 inputs: []inputInfo{ 16932 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16933 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16934 }, 16935 }, 16936 }, 16937 { 16938 name: "MOVVstore", 16939 auxType: auxSymOff, 16940 argLen: 3, 16941 faultOnNilArg0: true, 16942 symEffect: SymWrite, 16943 asm: mips.AMOVV, 16944 reg: regInfo{ 16945 inputs: []inputInfo{ 16946 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16947 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16948 }, 16949 }, 16950 }, 16951 { 16952 name: "MOVFstore", 16953 auxType: auxSymOff, 16954 argLen: 3, 16955 faultOnNilArg0: true, 16956 symEffect: SymWrite, 16957 asm: mips.AMOVF, 16958 reg: regInfo{ 16959 inputs: []inputInfo{ 16960 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16961 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16962 }, 16963 }, 16964 }, 16965 { 16966 name: "MOVDstore", 16967 auxType: auxSymOff, 16968 argLen: 3, 16969 faultOnNilArg0: true, 16970 symEffect: SymWrite, 16971 asm: mips.AMOVD, 16972 reg: regInfo{ 16973 inputs: []inputInfo{ 16974 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16975 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16976 }, 16977 }, 16978 }, 16979 { 16980 name: "MOVBstorezero", 16981 auxType: auxSymOff, 16982 argLen: 2, 16983 faultOnNilArg0: true, 16984 symEffect: SymWrite, 16985 asm: mips.AMOVB, 16986 reg: regInfo{ 16987 inputs: []inputInfo{ 16988 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16989 }, 16990 }, 16991 }, 16992 { 16993 name: "MOVHstorezero", 16994 auxType: auxSymOff, 16995 argLen: 2, 16996 faultOnNilArg0: true, 16997 symEffect: SymWrite, 16998 asm: mips.AMOVH, 16999 reg: regInfo{ 17000 inputs: []inputInfo{ 17001 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17002 }, 17003 }, 17004 }, 17005 { 17006 name: "MOVWstorezero", 17007 auxType: auxSymOff, 17008 argLen: 2, 17009 faultOnNilArg0: true, 17010 symEffect: SymWrite, 17011 asm: mips.AMOVW, 17012 reg: regInfo{ 17013 inputs: []inputInfo{ 17014 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17015 }, 17016 }, 17017 }, 17018 { 17019 name: "MOVVstorezero", 17020 auxType: auxSymOff, 17021 argLen: 2, 17022 faultOnNilArg0: true, 17023 symEffect: SymWrite, 17024 asm: mips.AMOVV, 17025 reg: regInfo{ 17026 inputs: []inputInfo{ 17027 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17028 }, 17029 }, 17030 }, 17031 { 17032 name: "MOVBreg", 17033 argLen: 1, 17034 asm: mips.AMOVB, 17035 reg: regInfo{ 17036 inputs: []inputInfo{ 17037 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17038 }, 17039 outputs: []outputInfo{ 17040 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17041 }, 17042 }, 17043 }, 17044 { 17045 name: "MOVBUreg", 17046 argLen: 1, 17047 asm: mips.AMOVBU, 17048 reg: regInfo{ 17049 inputs: []inputInfo{ 17050 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17051 }, 17052 outputs: []outputInfo{ 17053 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17054 }, 17055 }, 17056 }, 17057 { 17058 name: "MOVHreg", 17059 argLen: 1, 17060 asm: mips.AMOVH, 17061 reg: regInfo{ 17062 inputs: []inputInfo{ 17063 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17064 }, 17065 outputs: []outputInfo{ 17066 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17067 }, 17068 }, 17069 }, 17070 { 17071 name: "MOVHUreg", 17072 argLen: 1, 17073 asm: mips.AMOVHU, 17074 reg: regInfo{ 17075 inputs: []inputInfo{ 17076 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17077 }, 17078 outputs: []outputInfo{ 17079 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17080 }, 17081 }, 17082 }, 17083 { 17084 name: "MOVWreg", 17085 argLen: 1, 17086 asm: mips.AMOVW, 17087 reg: regInfo{ 17088 inputs: []inputInfo{ 17089 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17090 }, 17091 outputs: []outputInfo{ 17092 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17093 }, 17094 }, 17095 }, 17096 { 17097 name: "MOVWUreg", 17098 argLen: 1, 17099 asm: mips.AMOVWU, 17100 reg: regInfo{ 17101 inputs: []inputInfo{ 17102 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17103 }, 17104 outputs: []outputInfo{ 17105 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17106 }, 17107 }, 17108 }, 17109 { 17110 name: "MOVVreg", 17111 argLen: 1, 17112 asm: mips.AMOVV, 17113 reg: regInfo{ 17114 inputs: []inputInfo{ 17115 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17116 }, 17117 outputs: []outputInfo{ 17118 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17119 }, 17120 }, 17121 }, 17122 { 17123 name: "MOVVnop", 17124 argLen: 1, 17125 resultInArg0: true, 17126 reg: regInfo{ 17127 inputs: []inputInfo{ 17128 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17129 }, 17130 outputs: []outputInfo{ 17131 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17132 }, 17133 }, 17134 }, 17135 { 17136 name: "MOVWF", 17137 argLen: 1, 17138 asm: mips.AMOVWF, 17139 reg: regInfo{ 17140 inputs: []inputInfo{ 17141 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17142 }, 17143 outputs: []outputInfo{ 17144 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17145 }, 17146 }, 17147 }, 17148 { 17149 name: "MOVWD", 17150 argLen: 1, 17151 asm: mips.AMOVWD, 17152 reg: regInfo{ 17153 inputs: []inputInfo{ 17154 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17155 }, 17156 outputs: []outputInfo{ 17157 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17158 }, 17159 }, 17160 }, 17161 { 17162 name: "MOVVF", 17163 argLen: 1, 17164 asm: mips.AMOVVF, 17165 reg: regInfo{ 17166 inputs: []inputInfo{ 17167 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17168 }, 17169 outputs: []outputInfo{ 17170 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17171 }, 17172 }, 17173 }, 17174 { 17175 name: "MOVVD", 17176 argLen: 1, 17177 asm: mips.AMOVVD, 17178 reg: regInfo{ 17179 inputs: []inputInfo{ 17180 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17181 }, 17182 outputs: []outputInfo{ 17183 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17184 }, 17185 }, 17186 }, 17187 { 17188 name: "TRUNCFW", 17189 argLen: 1, 17190 asm: mips.ATRUNCFW, 17191 reg: regInfo{ 17192 inputs: []inputInfo{ 17193 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17194 }, 17195 outputs: []outputInfo{ 17196 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17197 }, 17198 }, 17199 }, 17200 { 17201 name: "TRUNCDW", 17202 argLen: 1, 17203 asm: mips.ATRUNCDW, 17204 reg: regInfo{ 17205 inputs: []inputInfo{ 17206 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17207 }, 17208 outputs: []outputInfo{ 17209 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17210 }, 17211 }, 17212 }, 17213 { 17214 name: "TRUNCFV", 17215 argLen: 1, 17216 asm: mips.ATRUNCFV, 17217 reg: regInfo{ 17218 inputs: []inputInfo{ 17219 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17220 }, 17221 outputs: []outputInfo{ 17222 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17223 }, 17224 }, 17225 }, 17226 { 17227 name: "TRUNCDV", 17228 argLen: 1, 17229 asm: mips.ATRUNCDV, 17230 reg: regInfo{ 17231 inputs: []inputInfo{ 17232 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17233 }, 17234 outputs: []outputInfo{ 17235 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17236 }, 17237 }, 17238 }, 17239 { 17240 name: "MOVFD", 17241 argLen: 1, 17242 asm: mips.AMOVFD, 17243 reg: regInfo{ 17244 inputs: []inputInfo{ 17245 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17246 }, 17247 outputs: []outputInfo{ 17248 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17249 }, 17250 }, 17251 }, 17252 { 17253 name: "MOVDF", 17254 argLen: 1, 17255 asm: mips.AMOVDF, 17256 reg: regInfo{ 17257 inputs: []inputInfo{ 17258 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17259 }, 17260 outputs: []outputInfo{ 17261 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 17262 }, 17263 }, 17264 }, 17265 { 17266 name: "CALLstatic", 17267 auxType: auxSymOff, 17268 argLen: 1, 17269 clobberFlags: true, 17270 call: true, 17271 symEffect: SymNone, 17272 reg: regInfo{ 17273 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 17274 }, 17275 }, 17276 { 17277 name: "CALLclosure", 17278 auxType: auxInt64, 17279 argLen: 3, 17280 clobberFlags: true, 17281 call: true, 17282 reg: regInfo{ 17283 inputs: []inputInfo{ 17284 {1, 4194304}, // R22 17285 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 17286 }, 17287 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 17288 }, 17289 }, 17290 { 17291 name: "CALLinter", 17292 auxType: auxInt64, 17293 argLen: 2, 17294 clobberFlags: true, 17295 call: true, 17296 reg: regInfo{ 17297 inputs: []inputInfo{ 17298 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17299 }, 17300 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 17301 }, 17302 }, 17303 { 17304 name: "DUFFZERO", 17305 auxType: auxInt64, 17306 argLen: 2, 17307 faultOnNilArg0: true, 17308 reg: regInfo{ 17309 inputs: []inputInfo{ 17310 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17311 }, 17312 clobbers: 134217730, // R1 R31 17313 }, 17314 }, 17315 { 17316 name: "LoweredZero", 17317 auxType: auxInt64, 17318 argLen: 3, 17319 clobberFlags: true, 17320 faultOnNilArg0: true, 17321 reg: regInfo{ 17322 inputs: []inputInfo{ 17323 {0, 2}, // R1 17324 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17325 }, 17326 clobbers: 2, // R1 17327 }, 17328 }, 17329 { 17330 name: "LoweredMove", 17331 auxType: auxInt64, 17332 argLen: 4, 17333 clobberFlags: true, 17334 faultOnNilArg0: true, 17335 faultOnNilArg1: true, 17336 reg: regInfo{ 17337 inputs: []inputInfo{ 17338 {0, 4}, // R2 17339 {1, 2}, // R1 17340 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17341 }, 17342 clobbers: 6, // R1 R2 17343 }, 17344 }, 17345 { 17346 name: "LoweredAtomicLoad32", 17347 argLen: 2, 17348 faultOnNilArg0: true, 17349 reg: regInfo{ 17350 inputs: []inputInfo{ 17351 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17352 }, 17353 outputs: []outputInfo{ 17354 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17355 }, 17356 }, 17357 }, 17358 { 17359 name: "LoweredAtomicLoad64", 17360 argLen: 2, 17361 faultOnNilArg0: true, 17362 reg: regInfo{ 17363 inputs: []inputInfo{ 17364 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17365 }, 17366 outputs: []outputInfo{ 17367 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17368 }, 17369 }, 17370 }, 17371 { 17372 name: "LoweredAtomicStore32", 17373 argLen: 3, 17374 faultOnNilArg0: true, 17375 hasSideEffects: true, 17376 reg: regInfo{ 17377 inputs: []inputInfo{ 17378 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17379 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17380 }, 17381 }, 17382 }, 17383 { 17384 name: "LoweredAtomicStore64", 17385 argLen: 3, 17386 faultOnNilArg0: true, 17387 hasSideEffects: true, 17388 reg: regInfo{ 17389 inputs: []inputInfo{ 17390 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17391 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17392 }, 17393 }, 17394 }, 17395 { 17396 name: "LoweredAtomicStorezero32", 17397 argLen: 2, 17398 faultOnNilArg0: true, 17399 hasSideEffects: true, 17400 reg: regInfo{ 17401 inputs: []inputInfo{ 17402 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17403 }, 17404 }, 17405 }, 17406 { 17407 name: "LoweredAtomicStorezero64", 17408 argLen: 2, 17409 faultOnNilArg0: true, 17410 hasSideEffects: true, 17411 reg: regInfo{ 17412 inputs: []inputInfo{ 17413 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17414 }, 17415 }, 17416 }, 17417 { 17418 name: "LoweredAtomicExchange32", 17419 argLen: 3, 17420 resultNotInArgs: true, 17421 faultOnNilArg0: true, 17422 hasSideEffects: true, 17423 reg: regInfo{ 17424 inputs: []inputInfo{ 17425 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17426 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17427 }, 17428 outputs: []outputInfo{ 17429 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17430 }, 17431 }, 17432 }, 17433 { 17434 name: "LoweredAtomicExchange64", 17435 argLen: 3, 17436 resultNotInArgs: true, 17437 faultOnNilArg0: true, 17438 hasSideEffects: true, 17439 reg: regInfo{ 17440 inputs: []inputInfo{ 17441 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17442 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17443 }, 17444 outputs: []outputInfo{ 17445 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17446 }, 17447 }, 17448 }, 17449 { 17450 name: "LoweredAtomicAdd32", 17451 argLen: 3, 17452 resultNotInArgs: true, 17453 faultOnNilArg0: true, 17454 hasSideEffects: true, 17455 reg: regInfo{ 17456 inputs: []inputInfo{ 17457 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17458 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17459 }, 17460 outputs: []outputInfo{ 17461 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17462 }, 17463 }, 17464 }, 17465 { 17466 name: "LoweredAtomicAdd64", 17467 argLen: 3, 17468 resultNotInArgs: true, 17469 faultOnNilArg0: true, 17470 hasSideEffects: true, 17471 reg: regInfo{ 17472 inputs: []inputInfo{ 17473 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17474 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17475 }, 17476 outputs: []outputInfo{ 17477 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17478 }, 17479 }, 17480 }, 17481 { 17482 name: "LoweredAtomicAddconst32", 17483 auxType: auxInt32, 17484 argLen: 2, 17485 resultNotInArgs: true, 17486 faultOnNilArg0: true, 17487 hasSideEffects: true, 17488 reg: regInfo{ 17489 inputs: []inputInfo{ 17490 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17491 }, 17492 outputs: []outputInfo{ 17493 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17494 }, 17495 }, 17496 }, 17497 { 17498 name: "LoweredAtomicAddconst64", 17499 auxType: auxInt64, 17500 argLen: 2, 17501 resultNotInArgs: true, 17502 faultOnNilArg0: true, 17503 hasSideEffects: true, 17504 reg: regInfo{ 17505 inputs: []inputInfo{ 17506 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17507 }, 17508 outputs: []outputInfo{ 17509 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17510 }, 17511 }, 17512 }, 17513 { 17514 name: "LoweredAtomicCas32", 17515 argLen: 4, 17516 resultNotInArgs: true, 17517 faultOnNilArg0: true, 17518 hasSideEffects: true, 17519 reg: regInfo{ 17520 inputs: []inputInfo{ 17521 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17522 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17523 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17524 }, 17525 outputs: []outputInfo{ 17526 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17527 }, 17528 }, 17529 }, 17530 { 17531 name: "LoweredAtomicCas64", 17532 argLen: 4, 17533 resultNotInArgs: true, 17534 faultOnNilArg0: true, 17535 hasSideEffects: true, 17536 reg: regInfo{ 17537 inputs: []inputInfo{ 17538 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17539 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17540 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17541 }, 17542 outputs: []outputInfo{ 17543 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17544 }, 17545 }, 17546 }, 17547 { 17548 name: "LoweredNilCheck", 17549 argLen: 2, 17550 nilCheck: true, 17551 faultOnNilArg0: true, 17552 reg: regInfo{ 17553 inputs: []inputInfo{ 17554 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17555 }, 17556 }, 17557 }, 17558 { 17559 name: "FPFlagTrue", 17560 argLen: 1, 17561 reg: regInfo{ 17562 outputs: []outputInfo{ 17563 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17564 }, 17565 }, 17566 }, 17567 { 17568 name: "FPFlagFalse", 17569 argLen: 1, 17570 reg: regInfo{ 17571 outputs: []outputInfo{ 17572 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17573 }, 17574 }, 17575 }, 17576 { 17577 name: "LoweredGetClosurePtr", 17578 argLen: 0, 17579 reg: regInfo{ 17580 outputs: []outputInfo{ 17581 {0, 4194304}, // R22 17582 }, 17583 }, 17584 }, 17585 { 17586 name: "LoweredGetCallerSP", 17587 argLen: 0, 17588 rematerializeable: true, 17589 reg: regInfo{ 17590 outputs: []outputInfo{ 17591 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17592 }, 17593 }, 17594 }, 17595 { 17596 name: "LoweredWB", 17597 auxType: auxSym, 17598 argLen: 3, 17599 clobberFlags: true, 17600 symEffect: SymNone, 17601 reg: regInfo{ 17602 inputs: []inputInfo{ 17603 {0, 1048576}, // R20 17604 {1, 2097152}, // R21 17605 }, 17606 clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 17607 }, 17608 }, 17609 { 17610 name: "MOVVconvert", 17611 argLen: 2, 17612 asm: mips.AMOVV, 17613 reg: regInfo{ 17614 inputs: []inputInfo{ 17615 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17616 }, 17617 outputs: []outputInfo{ 17618 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17619 }, 17620 }, 17621 }, 17622 17623 { 17624 name: "ADD", 17625 argLen: 2, 17626 commutative: true, 17627 asm: ppc64.AADD, 17628 reg: regInfo{ 17629 inputs: []inputInfo{ 17630 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17631 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17632 }, 17633 outputs: []outputInfo{ 17634 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17635 }, 17636 }, 17637 }, 17638 { 17639 name: "ADDconst", 17640 auxType: auxInt64, 17641 argLen: 1, 17642 asm: ppc64.AADD, 17643 reg: regInfo{ 17644 inputs: []inputInfo{ 17645 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17646 }, 17647 outputs: []outputInfo{ 17648 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17649 }, 17650 }, 17651 }, 17652 { 17653 name: "FADD", 17654 argLen: 2, 17655 commutative: true, 17656 asm: ppc64.AFADD, 17657 reg: regInfo{ 17658 inputs: []inputInfo{ 17659 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17660 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17661 }, 17662 outputs: []outputInfo{ 17663 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17664 }, 17665 }, 17666 }, 17667 { 17668 name: "FADDS", 17669 argLen: 2, 17670 commutative: true, 17671 asm: ppc64.AFADDS, 17672 reg: regInfo{ 17673 inputs: []inputInfo{ 17674 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17675 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17676 }, 17677 outputs: []outputInfo{ 17678 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17679 }, 17680 }, 17681 }, 17682 { 17683 name: "SUB", 17684 argLen: 2, 17685 asm: ppc64.ASUB, 17686 reg: regInfo{ 17687 inputs: []inputInfo{ 17688 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17689 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17690 }, 17691 outputs: []outputInfo{ 17692 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17693 }, 17694 }, 17695 }, 17696 { 17697 name: "FSUB", 17698 argLen: 2, 17699 asm: ppc64.AFSUB, 17700 reg: regInfo{ 17701 inputs: []inputInfo{ 17702 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17703 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17704 }, 17705 outputs: []outputInfo{ 17706 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17707 }, 17708 }, 17709 }, 17710 { 17711 name: "FSUBS", 17712 argLen: 2, 17713 asm: ppc64.AFSUBS, 17714 reg: regInfo{ 17715 inputs: []inputInfo{ 17716 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17717 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17718 }, 17719 outputs: []outputInfo{ 17720 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17721 }, 17722 }, 17723 }, 17724 { 17725 name: "MULLD", 17726 argLen: 2, 17727 commutative: true, 17728 asm: ppc64.AMULLD, 17729 reg: regInfo{ 17730 inputs: []inputInfo{ 17731 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17732 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17733 }, 17734 outputs: []outputInfo{ 17735 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17736 }, 17737 }, 17738 }, 17739 { 17740 name: "MULLW", 17741 argLen: 2, 17742 commutative: true, 17743 asm: ppc64.AMULLW, 17744 reg: regInfo{ 17745 inputs: []inputInfo{ 17746 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17747 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17748 }, 17749 outputs: []outputInfo{ 17750 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17751 }, 17752 }, 17753 }, 17754 { 17755 name: "MULHD", 17756 argLen: 2, 17757 commutative: true, 17758 asm: ppc64.AMULHD, 17759 reg: regInfo{ 17760 inputs: []inputInfo{ 17761 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17762 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17763 }, 17764 outputs: []outputInfo{ 17765 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17766 }, 17767 }, 17768 }, 17769 { 17770 name: "MULHW", 17771 argLen: 2, 17772 commutative: true, 17773 asm: ppc64.AMULHW, 17774 reg: regInfo{ 17775 inputs: []inputInfo{ 17776 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17777 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17778 }, 17779 outputs: []outputInfo{ 17780 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17781 }, 17782 }, 17783 }, 17784 { 17785 name: "MULHDU", 17786 argLen: 2, 17787 commutative: true, 17788 asm: ppc64.AMULHDU, 17789 reg: regInfo{ 17790 inputs: []inputInfo{ 17791 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17792 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17793 }, 17794 outputs: []outputInfo{ 17795 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17796 }, 17797 }, 17798 }, 17799 { 17800 name: "MULHWU", 17801 argLen: 2, 17802 commutative: true, 17803 asm: ppc64.AMULHWU, 17804 reg: regInfo{ 17805 inputs: []inputInfo{ 17806 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17807 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17808 }, 17809 outputs: []outputInfo{ 17810 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17811 }, 17812 }, 17813 }, 17814 { 17815 name: "FMUL", 17816 argLen: 2, 17817 commutative: true, 17818 asm: ppc64.AFMUL, 17819 reg: regInfo{ 17820 inputs: []inputInfo{ 17821 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17822 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17823 }, 17824 outputs: []outputInfo{ 17825 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17826 }, 17827 }, 17828 }, 17829 { 17830 name: "FMULS", 17831 argLen: 2, 17832 commutative: true, 17833 asm: ppc64.AFMULS, 17834 reg: regInfo{ 17835 inputs: []inputInfo{ 17836 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17837 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17838 }, 17839 outputs: []outputInfo{ 17840 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17841 }, 17842 }, 17843 }, 17844 { 17845 name: "FMADD", 17846 argLen: 3, 17847 asm: ppc64.AFMADD, 17848 reg: regInfo{ 17849 inputs: []inputInfo{ 17850 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17851 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17852 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17853 }, 17854 outputs: []outputInfo{ 17855 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17856 }, 17857 }, 17858 }, 17859 { 17860 name: "FMADDS", 17861 argLen: 3, 17862 asm: ppc64.AFMADDS, 17863 reg: regInfo{ 17864 inputs: []inputInfo{ 17865 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17866 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17867 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17868 }, 17869 outputs: []outputInfo{ 17870 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17871 }, 17872 }, 17873 }, 17874 { 17875 name: "FMSUB", 17876 argLen: 3, 17877 asm: ppc64.AFMSUB, 17878 reg: regInfo{ 17879 inputs: []inputInfo{ 17880 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17881 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17882 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17883 }, 17884 outputs: []outputInfo{ 17885 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17886 }, 17887 }, 17888 }, 17889 { 17890 name: "FMSUBS", 17891 argLen: 3, 17892 asm: ppc64.AFMSUBS, 17893 reg: regInfo{ 17894 inputs: []inputInfo{ 17895 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17896 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17897 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17898 }, 17899 outputs: []outputInfo{ 17900 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17901 }, 17902 }, 17903 }, 17904 { 17905 name: "SRAD", 17906 argLen: 2, 17907 asm: ppc64.ASRAD, 17908 reg: regInfo{ 17909 inputs: []inputInfo{ 17910 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17911 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17912 }, 17913 outputs: []outputInfo{ 17914 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17915 }, 17916 }, 17917 }, 17918 { 17919 name: "SRAW", 17920 argLen: 2, 17921 asm: ppc64.ASRAW, 17922 reg: regInfo{ 17923 inputs: []inputInfo{ 17924 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17925 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17926 }, 17927 outputs: []outputInfo{ 17928 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17929 }, 17930 }, 17931 }, 17932 { 17933 name: "SRD", 17934 argLen: 2, 17935 asm: ppc64.ASRD, 17936 reg: regInfo{ 17937 inputs: []inputInfo{ 17938 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17939 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17940 }, 17941 outputs: []outputInfo{ 17942 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17943 }, 17944 }, 17945 }, 17946 { 17947 name: "SRW", 17948 argLen: 2, 17949 asm: ppc64.ASRW, 17950 reg: regInfo{ 17951 inputs: []inputInfo{ 17952 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17953 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17954 }, 17955 outputs: []outputInfo{ 17956 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17957 }, 17958 }, 17959 }, 17960 { 17961 name: "SLD", 17962 argLen: 2, 17963 asm: ppc64.ASLD, 17964 reg: regInfo{ 17965 inputs: []inputInfo{ 17966 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17967 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17968 }, 17969 outputs: []outputInfo{ 17970 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17971 }, 17972 }, 17973 }, 17974 { 17975 name: "SLW", 17976 argLen: 2, 17977 asm: ppc64.ASLW, 17978 reg: regInfo{ 17979 inputs: []inputInfo{ 17980 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17981 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17982 }, 17983 outputs: []outputInfo{ 17984 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17985 }, 17986 }, 17987 }, 17988 { 17989 name: "ROTL", 17990 argLen: 2, 17991 asm: ppc64.AROTL, 17992 reg: regInfo{ 17993 inputs: []inputInfo{ 17994 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17995 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17996 }, 17997 outputs: []outputInfo{ 17998 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17999 }, 18000 }, 18001 }, 18002 { 18003 name: "ROTLW", 18004 argLen: 2, 18005 asm: ppc64.AROTLW, 18006 reg: regInfo{ 18007 inputs: []inputInfo{ 18008 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18009 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18010 }, 18011 outputs: []outputInfo{ 18012 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18013 }, 18014 }, 18015 }, 18016 { 18017 name: "ADDconstForCarry", 18018 auxType: auxInt16, 18019 argLen: 1, 18020 asm: ppc64.AADDC, 18021 reg: regInfo{ 18022 inputs: []inputInfo{ 18023 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18024 }, 18025 clobbers: 2147483648, // R31 18026 }, 18027 }, 18028 { 18029 name: "MaskIfNotCarry", 18030 argLen: 1, 18031 asm: ppc64.AADDME, 18032 reg: regInfo{ 18033 outputs: []outputInfo{ 18034 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18035 }, 18036 }, 18037 }, 18038 { 18039 name: "SRADconst", 18040 auxType: auxInt64, 18041 argLen: 1, 18042 asm: ppc64.ASRAD, 18043 reg: regInfo{ 18044 inputs: []inputInfo{ 18045 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18046 }, 18047 outputs: []outputInfo{ 18048 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18049 }, 18050 }, 18051 }, 18052 { 18053 name: "SRAWconst", 18054 auxType: auxInt64, 18055 argLen: 1, 18056 asm: ppc64.ASRAW, 18057 reg: regInfo{ 18058 inputs: []inputInfo{ 18059 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18060 }, 18061 outputs: []outputInfo{ 18062 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18063 }, 18064 }, 18065 }, 18066 { 18067 name: "SRDconst", 18068 auxType: auxInt64, 18069 argLen: 1, 18070 asm: ppc64.ASRD, 18071 reg: regInfo{ 18072 inputs: []inputInfo{ 18073 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18074 }, 18075 outputs: []outputInfo{ 18076 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18077 }, 18078 }, 18079 }, 18080 { 18081 name: "SRWconst", 18082 auxType: auxInt64, 18083 argLen: 1, 18084 asm: ppc64.ASRW, 18085 reg: regInfo{ 18086 inputs: []inputInfo{ 18087 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18088 }, 18089 outputs: []outputInfo{ 18090 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18091 }, 18092 }, 18093 }, 18094 { 18095 name: "SLDconst", 18096 auxType: auxInt64, 18097 argLen: 1, 18098 asm: ppc64.ASLD, 18099 reg: regInfo{ 18100 inputs: []inputInfo{ 18101 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18102 }, 18103 outputs: []outputInfo{ 18104 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18105 }, 18106 }, 18107 }, 18108 { 18109 name: "SLWconst", 18110 auxType: auxInt64, 18111 argLen: 1, 18112 asm: ppc64.ASLW, 18113 reg: regInfo{ 18114 inputs: []inputInfo{ 18115 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18116 }, 18117 outputs: []outputInfo{ 18118 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18119 }, 18120 }, 18121 }, 18122 { 18123 name: "ROTLconst", 18124 auxType: auxInt64, 18125 argLen: 1, 18126 asm: ppc64.AROTL, 18127 reg: regInfo{ 18128 inputs: []inputInfo{ 18129 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18130 }, 18131 outputs: []outputInfo{ 18132 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18133 }, 18134 }, 18135 }, 18136 { 18137 name: "ROTLWconst", 18138 auxType: auxInt64, 18139 argLen: 1, 18140 asm: ppc64.AROTLW, 18141 reg: regInfo{ 18142 inputs: []inputInfo{ 18143 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18144 }, 18145 outputs: []outputInfo{ 18146 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18147 }, 18148 }, 18149 }, 18150 { 18151 name: "CNTLZD", 18152 argLen: 1, 18153 clobberFlags: true, 18154 asm: ppc64.ACNTLZD, 18155 reg: regInfo{ 18156 inputs: []inputInfo{ 18157 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18158 }, 18159 outputs: []outputInfo{ 18160 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18161 }, 18162 }, 18163 }, 18164 { 18165 name: "CNTLZW", 18166 argLen: 1, 18167 clobberFlags: true, 18168 asm: ppc64.ACNTLZW, 18169 reg: regInfo{ 18170 inputs: []inputInfo{ 18171 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18172 }, 18173 outputs: []outputInfo{ 18174 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18175 }, 18176 }, 18177 }, 18178 { 18179 name: "POPCNTD", 18180 argLen: 1, 18181 asm: ppc64.APOPCNTD, 18182 reg: regInfo{ 18183 inputs: []inputInfo{ 18184 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18185 }, 18186 outputs: []outputInfo{ 18187 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18188 }, 18189 }, 18190 }, 18191 { 18192 name: "POPCNTW", 18193 argLen: 1, 18194 asm: ppc64.APOPCNTW, 18195 reg: regInfo{ 18196 inputs: []inputInfo{ 18197 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18198 }, 18199 outputs: []outputInfo{ 18200 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18201 }, 18202 }, 18203 }, 18204 { 18205 name: "POPCNTB", 18206 argLen: 1, 18207 asm: ppc64.APOPCNTB, 18208 reg: regInfo{ 18209 inputs: []inputInfo{ 18210 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18211 }, 18212 outputs: []outputInfo{ 18213 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18214 }, 18215 }, 18216 }, 18217 { 18218 name: "FDIV", 18219 argLen: 2, 18220 asm: ppc64.AFDIV, 18221 reg: regInfo{ 18222 inputs: []inputInfo{ 18223 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18224 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18225 }, 18226 outputs: []outputInfo{ 18227 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18228 }, 18229 }, 18230 }, 18231 { 18232 name: "FDIVS", 18233 argLen: 2, 18234 asm: ppc64.AFDIVS, 18235 reg: regInfo{ 18236 inputs: []inputInfo{ 18237 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18238 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18239 }, 18240 outputs: []outputInfo{ 18241 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18242 }, 18243 }, 18244 }, 18245 { 18246 name: "DIVD", 18247 argLen: 2, 18248 asm: ppc64.ADIVD, 18249 reg: regInfo{ 18250 inputs: []inputInfo{ 18251 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18252 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18253 }, 18254 outputs: []outputInfo{ 18255 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18256 }, 18257 }, 18258 }, 18259 { 18260 name: "DIVW", 18261 argLen: 2, 18262 asm: ppc64.ADIVW, 18263 reg: regInfo{ 18264 inputs: []inputInfo{ 18265 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18266 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18267 }, 18268 outputs: []outputInfo{ 18269 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18270 }, 18271 }, 18272 }, 18273 { 18274 name: "DIVDU", 18275 argLen: 2, 18276 asm: ppc64.ADIVDU, 18277 reg: regInfo{ 18278 inputs: []inputInfo{ 18279 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18280 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18281 }, 18282 outputs: []outputInfo{ 18283 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18284 }, 18285 }, 18286 }, 18287 { 18288 name: "DIVWU", 18289 argLen: 2, 18290 asm: ppc64.ADIVWU, 18291 reg: regInfo{ 18292 inputs: []inputInfo{ 18293 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18294 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18295 }, 18296 outputs: []outputInfo{ 18297 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18298 }, 18299 }, 18300 }, 18301 { 18302 name: "FCTIDZ", 18303 argLen: 1, 18304 asm: ppc64.AFCTIDZ, 18305 reg: regInfo{ 18306 inputs: []inputInfo{ 18307 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18308 }, 18309 outputs: []outputInfo{ 18310 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18311 }, 18312 }, 18313 }, 18314 { 18315 name: "FCTIWZ", 18316 argLen: 1, 18317 asm: ppc64.AFCTIWZ, 18318 reg: regInfo{ 18319 inputs: []inputInfo{ 18320 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18321 }, 18322 outputs: []outputInfo{ 18323 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18324 }, 18325 }, 18326 }, 18327 { 18328 name: "FCFID", 18329 argLen: 1, 18330 asm: ppc64.AFCFID, 18331 reg: regInfo{ 18332 inputs: []inputInfo{ 18333 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18334 }, 18335 outputs: []outputInfo{ 18336 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18337 }, 18338 }, 18339 }, 18340 { 18341 name: "FCFIDS", 18342 argLen: 1, 18343 asm: ppc64.AFCFIDS, 18344 reg: regInfo{ 18345 inputs: []inputInfo{ 18346 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18347 }, 18348 outputs: []outputInfo{ 18349 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18350 }, 18351 }, 18352 }, 18353 { 18354 name: "FRSP", 18355 argLen: 1, 18356 asm: ppc64.AFRSP, 18357 reg: regInfo{ 18358 inputs: []inputInfo{ 18359 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18360 }, 18361 outputs: []outputInfo{ 18362 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18363 }, 18364 }, 18365 }, 18366 { 18367 name: "MFVSRD", 18368 argLen: 1, 18369 asm: ppc64.AMFVSRD, 18370 reg: regInfo{ 18371 inputs: []inputInfo{ 18372 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18373 }, 18374 outputs: []outputInfo{ 18375 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18376 }, 18377 }, 18378 }, 18379 { 18380 name: "MTVSRD", 18381 argLen: 1, 18382 asm: ppc64.AMTVSRD, 18383 reg: regInfo{ 18384 inputs: []inputInfo{ 18385 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18386 }, 18387 outputs: []outputInfo{ 18388 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18389 }, 18390 }, 18391 }, 18392 { 18393 name: "AND", 18394 argLen: 2, 18395 commutative: true, 18396 asm: ppc64.AAND, 18397 reg: regInfo{ 18398 inputs: []inputInfo{ 18399 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18400 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18401 }, 18402 outputs: []outputInfo{ 18403 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18404 }, 18405 }, 18406 }, 18407 { 18408 name: "ANDN", 18409 argLen: 2, 18410 asm: ppc64.AANDN, 18411 reg: regInfo{ 18412 inputs: []inputInfo{ 18413 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18414 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18415 }, 18416 outputs: []outputInfo{ 18417 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18418 }, 18419 }, 18420 }, 18421 { 18422 name: "OR", 18423 argLen: 2, 18424 commutative: true, 18425 asm: ppc64.AOR, 18426 reg: regInfo{ 18427 inputs: []inputInfo{ 18428 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18429 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18430 }, 18431 outputs: []outputInfo{ 18432 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18433 }, 18434 }, 18435 }, 18436 { 18437 name: "ORN", 18438 argLen: 2, 18439 asm: ppc64.AORN, 18440 reg: regInfo{ 18441 inputs: []inputInfo{ 18442 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18443 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18444 }, 18445 outputs: []outputInfo{ 18446 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18447 }, 18448 }, 18449 }, 18450 { 18451 name: "NOR", 18452 argLen: 2, 18453 commutative: true, 18454 asm: ppc64.ANOR, 18455 reg: regInfo{ 18456 inputs: []inputInfo{ 18457 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18458 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18459 }, 18460 outputs: []outputInfo{ 18461 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18462 }, 18463 }, 18464 }, 18465 { 18466 name: "XOR", 18467 argLen: 2, 18468 commutative: true, 18469 asm: ppc64.AXOR, 18470 reg: regInfo{ 18471 inputs: []inputInfo{ 18472 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18473 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18474 }, 18475 outputs: []outputInfo{ 18476 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18477 }, 18478 }, 18479 }, 18480 { 18481 name: "EQV", 18482 argLen: 2, 18483 commutative: true, 18484 asm: ppc64.AEQV, 18485 reg: regInfo{ 18486 inputs: []inputInfo{ 18487 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18488 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18489 }, 18490 outputs: []outputInfo{ 18491 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18492 }, 18493 }, 18494 }, 18495 { 18496 name: "NEG", 18497 argLen: 1, 18498 asm: ppc64.ANEG, 18499 reg: regInfo{ 18500 inputs: []inputInfo{ 18501 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18502 }, 18503 outputs: []outputInfo{ 18504 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18505 }, 18506 }, 18507 }, 18508 { 18509 name: "FNEG", 18510 argLen: 1, 18511 asm: ppc64.AFNEG, 18512 reg: regInfo{ 18513 inputs: []inputInfo{ 18514 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18515 }, 18516 outputs: []outputInfo{ 18517 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18518 }, 18519 }, 18520 }, 18521 { 18522 name: "FSQRT", 18523 argLen: 1, 18524 asm: ppc64.AFSQRT, 18525 reg: regInfo{ 18526 inputs: []inputInfo{ 18527 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18528 }, 18529 outputs: []outputInfo{ 18530 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18531 }, 18532 }, 18533 }, 18534 { 18535 name: "FSQRTS", 18536 argLen: 1, 18537 asm: ppc64.AFSQRTS, 18538 reg: regInfo{ 18539 inputs: []inputInfo{ 18540 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18541 }, 18542 outputs: []outputInfo{ 18543 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18544 }, 18545 }, 18546 }, 18547 { 18548 name: "FFLOOR", 18549 argLen: 1, 18550 asm: ppc64.AFRIM, 18551 reg: regInfo{ 18552 inputs: []inputInfo{ 18553 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18554 }, 18555 outputs: []outputInfo{ 18556 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18557 }, 18558 }, 18559 }, 18560 { 18561 name: "FCEIL", 18562 argLen: 1, 18563 asm: ppc64.AFRIP, 18564 reg: regInfo{ 18565 inputs: []inputInfo{ 18566 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18567 }, 18568 outputs: []outputInfo{ 18569 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18570 }, 18571 }, 18572 }, 18573 { 18574 name: "FTRUNC", 18575 argLen: 1, 18576 asm: ppc64.AFRIZ, 18577 reg: regInfo{ 18578 inputs: []inputInfo{ 18579 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18580 }, 18581 outputs: []outputInfo{ 18582 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18583 }, 18584 }, 18585 }, 18586 { 18587 name: "FABS", 18588 argLen: 1, 18589 asm: ppc64.AFABS, 18590 reg: regInfo{ 18591 inputs: []inputInfo{ 18592 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18593 }, 18594 outputs: []outputInfo{ 18595 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18596 }, 18597 }, 18598 }, 18599 { 18600 name: "FNABS", 18601 argLen: 1, 18602 asm: ppc64.AFNABS, 18603 reg: regInfo{ 18604 inputs: []inputInfo{ 18605 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18606 }, 18607 outputs: []outputInfo{ 18608 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18609 }, 18610 }, 18611 }, 18612 { 18613 name: "FCPSGN", 18614 argLen: 2, 18615 asm: ppc64.AFCPSGN, 18616 reg: regInfo{ 18617 inputs: []inputInfo{ 18618 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18619 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18620 }, 18621 outputs: []outputInfo{ 18622 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18623 }, 18624 }, 18625 }, 18626 { 18627 name: "ORconst", 18628 auxType: auxInt64, 18629 argLen: 1, 18630 asm: ppc64.AOR, 18631 reg: regInfo{ 18632 inputs: []inputInfo{ 18633 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18634 }, 18635 outputs: []outputInfo{ 18636 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18637 }, 18638 }, 18639 }, 18640 { 18641 name: "XORconst", 18642 auxType: auxInt64, 18643 argLen: 1, 18644 asm: ppc64.AXOR, 18645 reg: regInfo{ 18646 inputs: []inputInfo{ 18647 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18648 }, 18649 outputs: []outputInfo{ 18650 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18651 }, 18652 }, 18653 }, 18654 { 18655 name: "ANDconst", 18656 auxType: auxInt64, 18657 argLen: 1, 18658 clobberFlags: true, 18659 asm: ppc64.AANDCC, 18660 reg: regInfo{ 18661 inputs: []inputInfo{ 18662 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18663 }, 18664 outputs: []outputInfo{ 18665 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18666 }, 18667 }, 18668 }, 18669 { 18670 name: "ANDCCconst", 18671 auxType: auxInt64, 18672 argLen: 1, 18673 asm: ppc64.AANDCC, 18674 reg: regInfo{ 18675 inputs: []inputInfo{ 18676 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18677 }, 18678 }, 18679 }, 18680 { 18681 name: "MOVBreg", 18682 argLen: 1, 18683 asm: ppc64.AMOVB, 18684 reg: regInfo{ 18685 inputs: []inputInfo{ 18686 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18687 }, 18688 outputs: []outputInfo{ 18689 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18690 }, 18691 }, 18692 }, 18693 { 18694 name: "MOVBZreg", 18695 argLen: 1, 18696 asm: ppc64.AMOVBZ, 18697 reg: regInfo{ 18698 inputs: []inputInfo{ 18699 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18700 }, 18701 outputs: []outputInfo{ 18702 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18703 }, 18704 }, 18705 }, 18706 { 18707 name: "MOVHreg", 18708 argLen: 1, 18709 asm: ppc64.AMOVH, 18710 reg: regInfo{ 18711 inputs: []inputInfo{ 18712 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18713 }, 18714 outputs: []outputInfo{ 18715 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18716 }, 18717 }, 18718 }, 18719 { 18720 name: "MOVHZreg", 18721 argLen: 1, 18722 asm: ppc64.AMOVHZ, 18723 reg: regInfo{ 18724 inputs: []inputInfo{ 18725 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18726 }, 18727 outputs: []outputInfo{ 18728 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18729 }, 18730 }, 18731 }, 18732 { 18733 name: "MOVWreg", 18734 argLen: 1, 18735 asm: ppc64.AMOVW, 18736 reg: regInfo{ 18737 inputs: []inputInfo{ 18738 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18739 }, 18740 outputs: []outputInfo{ 18741 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18742 }, 18743 }, 18744 }, 18745 { 18746 name: "MOVWZreg", 18747 argLen: 1, 18748 asm: ppc64.AMOVWZ, 18749 reg: regInfo{ 18750 inputs: []inputInfo{ 18751 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18752 }, 18753 outputs: []outputInfo{ 18754 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18755 }, 18756 }, 18757 }, 18758 { 18759 name: "MOVBZload", 18760 auxType: auxSymOff, 18761 argLen: 2, 18762 faultOnNilArg0: true, 18763 symEffect: SymRead, 18764 asm: ppc64.AMOVBZ, 18765 reg: regInfo{ 18766 inputs: []inputInfo{ 18767 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18768 }, 18769 outputs: []outputInfo{ 18770 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18771 }, 18772 }, 18773 }, 18774 { 18775 name: "MOVHload", 18776 auxType: auxSymOff, 18777 argLen: 2, 18778 faultOnNilArg0: true, 18779 symEffect: SymRead, 18780 asm: ppc64.AMOVH, 18781 reg: regInfo{ 18782 inputs: []inputInfo{ 18783 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18784 }, 18785 outputs: []outputInfo{ 18786 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18787 }, 18788 }, 18789 }, 18790 { 18791 name: "MOVHZload", 18792 auxType: auxSymOff, 18793 argLen: 2, 18794 faultOnNilArg0: true, 18795 symEffect: SymRead, 18796 asm: ppc64.AMOVHZ, 18797 reg: regInfo{ 18798 inputs: []inputInfo{ 18799 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18800 }, 18801 outputs: []outputInfo{ 18802 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18803 }, 18804 }, 18805 }, 18806 { 18807 name: "MOVWload", 18808 auxType: auxSymOff, 18809 argLen: 2, 18810 faultOnNilArg0: true, 18811 symEffect: SymRead, 18812 asm: ppc64.AMOVW, 18813 reg: regInfo{ 18814 inputs: []inputInfo{ 18815 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18816 }, 18817 outputs: []outputInfo{ 18818 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18819 }, 18820 }, 18821 }, 18822 { 18823 name: "MOVWZload", 18824 auxType: auxSymOff, 18825 argLen: 2, 18826 faultOnNilArg0: true, 18827 symEffect: SymRead, 18828 asm: ppc64.AMOVWZ, 18829 reg: regInfo{ 18830 inputs: []inputInfo{ 18831 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18832 }, 18833 outputs: []outputInfo{ 18834 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18835 }, 18836 }, 18837 }, 18838 { 18839 name: "MOVDload", 18840 auxType: auxSymOff, 18841 argLen: 2, 18842 faultOnNilArg0: true, 18843 symEffect: SymRead, 18844 asm: ppc64.AMOVD, 18845 reg: regInfo{ 18846 inputs: []inputInfo{ 18847 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18848 }, 18849 outputs: []outputInfo{ 18850 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18851 }, 18852 }, 18853 }, 18854 { 18855 name: "FMOVDload", 18856 auxType: auxSymOff, 18857 argLen: 2, 18858 faultOnNilArg0: true, 18859 symEffect: SymRead, 18860 asm: ppc64.AFMOVD, 18861 reg: regInfo{ 18862 inputs: []inputInfo{ 18863 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18864 }, 18865 outputs: []outputInfo{ 18866 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18867 }, 18868 }, 18869 }, 18870 { 18871 name: "FMOVSload", 18872 auxType: auxSymOff, 18873 argLen: 2, 18874 faultOnNilArg0: true, 18875 symEffect: SymRead, 18876 asm: ppc64.AFMOVS, 18877 reg: regInfo{ 18878 inputs: []inputInfo{ 18879 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18880 }, 18881 outputs: []outputInfo{ 18882 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18883 }, 18884 }, 18885 }, 18886 { 18887 name: "MOVBstore", 18888 auxType: auxSymOff, 18889 argLen: 3, 18890 faultOnNilArg0: true, 18891 symEffect: SymWrite, 18892 asm: ppc64.AMOVB, 18893 reg: regInfo{ 18894 inputs: []inputInfo{ 18895 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18896 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18897 }, 18898 }, 18899 }, 18900 { 18901 name: "MOVHstore", 18902 auxType: auxSymOff, 18903 argLen: 3, 18904 faultOnNilArg0: true, 18905 symEffect: SymWrite, 18906 asm: ppc64.AMOVH, 18907 reg: regInfo{ 18908 inputs: []inputInfo{ 18909 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18910 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18911 }, 18912 }, 18913 }, 18914 { 18915 name: "MOVWstore", 18916 auxType: auxSymOff, 18917 argLen: 3, 18918 faultOnNilArg0: true, 18919 symEffect: SymWrite, 18920 asm: ppc64.AMOVW, 18921 reg: regInfo{ 18922 inputs: []inputInfo{ 18923 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18924 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18925 }, 18926 }, 18927 }, 18928 { 18929 name: "MOVDstore", 18930 auxType: auxSymOff, 18931 argLen: 3, 18932 faultOnNilArg0: true, 18933 symEffect: SymWrite, 18934 asm: ppc64.AMOVD, 18935 reg: regInfo{ 18936 inputs: []inputInfo{ 18937 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18938 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18939 }, 18940 }, 18941 }, 18942 { 18943 name: "FMOVDstore", 18944 auxType: auxSymOff, 18945 argLen: 3, 18946 faultOnNilArg0: true, 18947 symEffect: SymWrite, 18948 asm: ppc64.AFMOVD, 18949 reg: regInfo{ 18950 inputs: []inputInfo{ 18951 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18952 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18953 }, 18954 }, 18955 }, 18956 { 18957 name: "FMOVSstore", 18958 auxType: auxSymOff, 18959 argLen: 3, 18960 faultOnNilArg0: true, 18961 symEffect: SymWrite, 18962 asm: ppc64.AFMOVS, 18963 reg: regInfo{ 18964 inputs: []inputInfo{ 18965 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18966 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18967 }, 18968 }, 18969 }, 18970 { 18971 name: "MOVBstorezero", 18972 auxType: auxSymOff, 18973 argLen: 2, 18974 faultOnNilArg0: true, 18975 symEffect: SymWrite, 18976 asm: ppc64.AMOVB, 18977 reg: regInfo{ 18978 inputs: []inputInfo{ 18979 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18980 }, 18981 }, 18982 }, 18983 { 18984 name: "MOVHstorezero", 18985 auxType: auxSymOff, 18986 argLen: 2, 18987 faultOnNilArg0: true, 18988 symEffect: SymWrite, 18989 asm: ppc64.AMOVH, 18990 reg: regInfo{ 18991 inputs: []inputInfo{ 18992 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18993 }, 18994 }, 18995 }, 18996 { 18997 name: "MOVWstorezero", 18998 auxType: auxSymOff, 18999 argLen: 2, 19000 faultOnNilArg0: true, 19001 symEffect: SymWrite, 19002 asm: ppc64.AMOVW, 19003 reg: regInfo{ 19004 inputs: []inputInfo{ 19005 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19006 }, 19007 }, 19008 }, 19009 { 19010 name: "MOVDstorezero", 19011 auxType: auxSymOff, 19012 argLen: 2, 19013 faultOnNilArg0: true, 19014 symEffect: SymWrite, 19015 asm: ppc64.AMOVD, 19016 reg: regInfo{ 19017 inputs: []inputInfo{ 19018 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19019 }, 19020 }, 19021 }, 19022 { 19023 name: "MOVDaddr", 19024 auxType: auxSymOff, 19025 argLen: 1, 19026 rematerializeable: true, 19027 symEffect: SymAddr, 19028 asm: ppc64.AMOVD, 19029 reg: regInfo{ 19030 inputs: []inputInfo{ 19031 {0, 6}, // SP SB 19032 }, 19033 outputs: []outputInfo{ 19034 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19035 }, 19036 }, 19037 }, 19038 { 19039 name: "MOVDconst", 19040 auxType: auxInt64, 19041 argLen: 0, 19042 rematerializeable: true, 19043 asm: ppc64.AMOVD, 19044 reg: regInfo{ 19045 outputs: []outputInfo{ 19046 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19047 }, 19048 }, 19049 }, 19050 { 19051 name: "FMOVDconst", 19052 auxType: auxFloat64, 19053 argLen: 0, 19054 rematerializeable: true, 19055 asm: ppc64.AFMOVD, 19056 reg: regInfo{ 19057 outputs: []outputInfo{ 19058 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19059 }, 19060 }, 19061 }, 19062 { 19063 name: "FMOVSconst", 19064 auxType: auxFloat32, 19065 argLen: 0, 19066 rematerializeable: true, 19067 asm: ppc64.AFMOVS, 19068 reg: regInfo{ 19069 outputs: []outputInfo{ 19070 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19071 }, 19072 }, 19073 }, 19074 { 19075 name: "FCMPU", 19076 argLen: 2, 19077 asm: ppc64.AFCMPU, 19078 reg: regInfo{ 19079 inputs: []inputInfo{ 19080 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19081 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19082 }, 19083 }, 19084 }, 19085 { 19086 name: "CMP", 19087 argLen: 2, 19088 asm: ppc64.ACMP, 19089 reg: regInfo{ 19090 inputs: []inputInfo{ 19091 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19092 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19093 }, 19094 }, 19095 }, 19096 { 19097 name: "CMPU", 19098 argLen: 2, 19099 asm: ppc64.ACMPU, 19100 reg: regInfo{ 19101 inputs: []inputInfo{ 19102 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19103 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19104 }, 19105 }, 19106 }, 19107 { 19108 name: "CMPW", 19109 argLen: 2, 19110 asm: ppc64.ACMPW, 19111 reg: regInfo{ 19112 inputs: []inputInfo{ 19113 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19114 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19115 }, 19116 }, 19117 }, 19118 { 19119 name: "CMPWU", 19120 argLen: 2, 19121 asm: ppc64.ACMPWU, 19122 reg: regInfo{ 19123 inputs: []inputInfo{ 19124 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19125 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19126 }, 19127 }, 19128 }, 19129 { 19130 name: "CMPconst", 19131 auxType: auxInt64, 19132 argLen: 1, 19133 asm: ppc64.ACMP, 19134 reg: regInfo{ 19135 inputs: []inputInfo{ 19136 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19137 }, 19138 }, 19139 }, 19140 { 19141 name: "CMPUconst", 19142 auxType: auxInt64, 19143 argLen: 1, 19144 asm: ppc64.ACMPU, 19145 reg: regInfo{ 19146 inputs: []inputInfo{ 19147 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19148 }, 19149 }, 19150 }, 19151 { 19152 name: "CMPWconst", 19153 auxType: auxInt32, 19154 argLen: 1, 19155 asm: ppc64.ACMPW, 19156 reg: regInfo{ 19157 inputs: []inputInfo{ 19158 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19159 }, 19160 }, 19161 }, 19162 { 19163 name: "CMPWUconst", 19164 auxType: auxInt32, 19165 argLen: 1, 19166 asm: ppc64.ACMPWU, 19167 reg: regInfo{ 19168 inputs: []inputInfo{ 19169 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19170 }, 19171 }, 19172 }, 19173 { 19174 name: "Equal", 19175 argLen: 1, 19176 reg: regInfo{ 19177 outputs: []outputInfo{ 19178 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19179 }, 19180 }, 19181 }, 19182 { 19183 name: "NotEqual", 19184 argLen: 1, 19185 reg: regInfo{ 19186 outputs: []outputInfo{ 19187 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19188 }, 19189 }, 19190 }, 19191 { 19192 name: "LessThan", 19193 argLen: 1, 19194 reg: regInfo{ 19195 outputs: []outputInfo{ 19196 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19197 }, 19198 }, 19199 }, 19200 { 19201 name: "FLessThan", 19202 argLen: 1, 19203 reg: regInfo{ 19204 outputs: []outputInfo{ 19205 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19206 }, 19207 }, 19208 }, 19209 { 19210 name: "LessEqual", 19211 argLen: 1, 19212 reg: regInfo{ 19213 outputs: []outputInfo{ 19214 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19215 }, 19216 }, 19217 }, 19218 { 19219 name: "FLessEqual", 19220 argLen: 1, 19221 reg: regInfo{ 19222 outputs: []outputInfo{ 19223 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19224 }, 19225 }, 19226 }, 19227 { 19228 name: "GreaterThan", 19229 argLen: 1, 19230 reg: regInfo{ 19231 outputs: []outputInfo{ 19232 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19233 }, 19234 }, 19235 }, 19236 { 19237 name: "FGreaterThan", 19238 argLen: 1, 19239 reg: regInfo{ 19240 outputs: []outputInfo{ 19241 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19242 }, 19243 }, 19244 }, 19245 { 19246 name: "GreaterEqual", 19247 argLen: 1, 19248 reg: regInfo{ 19249 outputs: []outputInfo{ 19250 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19251 }, 19252 }, 19253 }, 19254 { 19255 name: "FGreaterEqual", 19256 argLen: 1, 19257 reg: regInfo{ 19258 outputs: []outputInfo{ 19259 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19260 }, 19261 }, 19262 }, 19263 { 19264 name: "LoweredGetClosurePtr", 19265 argLen: 0, 19266 reg: regInfo{ 19267 outputs: []outputInfo{ 19268 {0, 2048}, // R11 19269 }, 19270 }, 19271 }, 19272 { 19273 name: "LoweredGetCallerSP", 19274 argLen: 0, 19275 rematerializeable: true, 19276 reg: regInfo{ 19277 outputs: []outputInfo{ 19278 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19279 }, 19280 }, 19281 }, 19282 { 19283 name: "LoweredNilCheck", 19284 argLen: 2, 19285 clobberFlags: true, 19286 nilCheck: true, 19287 faultOnNilArg0: true, 19288 reg: regInfo{ 19289 inputs: []inputInfo{ 19290 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19291 }, 19292 clobbers: 2147483648, // R31 19293 }, 19294 }, 19295 { 19296 name: "LoweredRound32F", 19297 argLen: 1, 19298 resultInArg0: true, 19299 reg: regInfo{ 19300 inputs: []inputInfo{ 19301 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19302 }, 19303 outputs: []outputInfo{ 19304 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19305 }, 19306 }, 19307 }, 19308 { 19309 name: "LoweredRound64F", 19310 argLen: 1, 19311 resultInArg0: true, 19312 reg: regInfo{ 19313 inputs: []inputInfo{ 19314 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19315 }, 19316 outputs: []outputInfo{ 19317 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19318 }, 19319 }, 19320 }, 19321 { 19322 name: "MOVDconvert", 19323 argLen: 2, 19324 asm: ppc64.AMOVD, 19325 reg: regInfo{ 19326 inputs: []inputInfo{ 19327 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19328 }, 19329 outputs: []outputInfo{ 19330 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19331 }, 19332 }, 19333 }, 19334 { 19335 name: "CALLstatic", 19336 auxType: auxSymOff, 19337 argLen: 1, 19338 clobberFlags: true, 19339 call: true, 19340 symEffect: SymNone, 19341 reg: regInfo{ 19342 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19343 }, 19344 }, 19345 { 19346 name: "CALLclosure", 19347 auxType: auxInt64, 19348 argLen: 3, 19349 clobberFlags: true, 19350 call: true, 19351 reg: regInfo{ 19352 inputs: []inputInfo{ 19353 {0, 4096}, // R12 19354 {1, 2048}, // R11 19355 }, 19356 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19357 }, 19358 }, 19359 { 19360 name: "CALLinter", 19361 auxType: auxInt64, 19362 argLen: 2, 19363 clobberFlags: true, 19364 call: true, 19365 reg: regInfo{ 19366 inputs: []inputInfo{ 19367 {0, 4096}, // R12 19368 }, 19369 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19370 }, 19371 }, 19372 { 19373 name: "LoweredZero", 19374 auxType: auxInt64, 19375 argLen: 2, 19376 clobberFlags: true, 19377 faultOnNilArg0: true, 19378 reg: regInfo{ 19379 inputs: []inputInfo{ 19380 {0, 8}, // R3 19381 }, 19382 clobbers: 8, // R3 19383 }, 19384 }, 19385 { 19386 name: "LoweredMove", 19387 auxType: auxInt64, 19388 argLen: 3, 19389 clobberFlags: true, 19390 faultOnNilArg0: true, 19391 faultOnNilArg1: true, 19392 reg: regInfo{ 19393 inputs: []inputInfo{ 19394 {0, 8}, // R3 19395 {1, 16}, // R4 19396 }, 19397 clobbers: 1944, // R3 R4 R7 R8 R9 R10 19398 }, 19399 }, 19400 { 19401 name: "LoweredAtomicStore32", 19402 argLen: 3, 19403 faultOnNilArg0: true, 19404 hasSideEffects: true, 19405 reg: regInfo{ 19406 inputs: []inputInfo{ 19407 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19408 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19409 }, 19410 }, 19411 }, 19412 { 19413 name: "LoweredAtomicStore64", 19414 argLen: 3, 19415 faultOnNilArg0: true, 19416 hasSideEffects: true, 19417 reg: regInfo{ 19418 inputs: []inputInfo{ 19419 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19420 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19421 }, 19422 }, 19423 }, 19424 { 19425 name: "LoweredAtomicLoad32", 19426 argLen: 2, 19427 clobberFlags: true, 19428 faultOnNilArg0: true, 19429 reg: regInfo{ 19430 inputs: []inputInfo{ 19431 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19432 }, 19433 outputs: []outputInfo{ 19434 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19435 }, 19436 }, 19437 }, 19438 { 19439 name: "LoweredAtomicLoad64", 19440 argLen: 2, 19441 clobberFlags: true, 19442 faultOnNilArg0: true, 19443 reg: regInfo{ 19444 inputs: []inputInfo{ 19445 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19446 }, 19447 outputs: []outputInfo{ 19448 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19449 }, 19450 }, 19451 }, 19452 { 19453 name: "LoweredAtomicLoadPtr", 19454 argLen: 2, 19455 clobberFlags: true, 19456 faultOnNilArg0: true, 19457 reg: regInfo{ 19458 inputs: []inputInfo{ 19459 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19460 }, 19461 outputs: []outputInfo{ 19462 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19463 }, 19464 }, 19465 }, 19466 { 19467 name: "LoweredAtomicAdd32", 19468 argLen: 3, 19469 resultNotInArgs: true, 19470 clobberFlags: true, 19471 faultOnNilArg0: true, 19472 hasSideEffects: true, 19473 reg: regInfo{ 19474 inputs: []inputInfo{ 19475 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19476 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19477 }, 19478 outputs: []outputInfo{ 19479 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19480 }, 19481 }, 19482 }, 19483 { 19484 name: "LoweredAtomicAdd64", 19485 argLen: 3, 19486 resultNotInArgs: true, 19487 clobberFlags: true, 19488 faultOnNilArg0: true, 19489 hasSideEffects: true, 19490 reg: regInfo{ 19491 inputs: []inputInfo{ 19492 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19493 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19494 }, 19495 outputs: []outputInfo{ 19496 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19497 }, 19498 }, 19499 }, 19500 { 19501 name: "LoweredAtomicExchange32", 19502 argLen: 3, 19503 resultNotInArgs: true, 19504 clobberFlags: true, 19505 faultOnNilArg0: true, 19506 hasSideEffects: true, 19507 reg: regInfo{ 19508 inputs: []inputInfo{ 19509 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19510 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19511 }, 19512 outputs: []outputInfo{ 19513 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19514 }, 19515 }, 19516 }, 19517 { 19518 name: "LoweredAtomicExchange64", 19519 argLen: 3, 19520 resultNotInArgs: true, 19521 clobberFlags: true, 19522 faultOnNilArg0: true, 19523 hasSideEffects: true, 19524 reg: regInfo{ 19525 inputs: []inputInfo{ 19526 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19528 }, 19529 outputs: []outputInfo{ 19530 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19531 }, 19532 }, 19533 }, 19534 { 19535 name: "LoweredAtomicCas64", 19536 argLen: 4, 19537 resultNotInArgs: true, 19538 clobberFlags: true, 19539 faultOnNilArg0: true, 19540 hasSideEffects: true, 19541 reg: regInfo{ 19542 inputs: []inputInfo{ 19543 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19544 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19545 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19546 }, 19547 outputs: []outputInfo{ 19548 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19549 }, 19550 }, 19551 }, 19552 { 19553 name: "LoweredAtomicCas32", 19554 argLen: 4, 19555 resultNotInArgs: true, 19556 clobberFlags: true, 19557 faultOnNilArg0: true, 19558 hasSideEffects: true, 19559 reg: regInfo{ 19560 inputs: []inputInfo{ 19561 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19562 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19563 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19564 }, 19565 outputs: []outputInfo{ 19566 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19567 }, 19568 }, 19569 }, 19570 { 19571 name: "LoweredAtomicAnd8", 19572 argLen: 3, 19573 faultOnNilArg0: true, 19574 hasSideEffects: true, 19575 asm: ppc64.AAND, 19576 reg: regInfo{ 19577 inputs: []inputInfo{ 19578 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19579 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19580 }, 19581 }, 19582 }, 19583 { 19584 name: "LoweredAtomicOr8", 19585 argLen: 3, 19586 faultOnNilArg0: true, 19587 hasSideEffects: true, 19588 asm: ppc64.AOR, 19589 reg: regInfo{ 19590 inputs: []inputInfo{ 19591 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19592 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19593 }, 19594 }, 19595 }, 19596 { 19597 name: "LoweredWB", 19598 auxType: auxSym, 19599 argLen: 3, 19600 clobberFlags: true, 19601 symEffect: SymNone, 19602 reg: regInfo{ 19603 inputs: []inputInfo{ 19604 {0, 1048576}, // R20 19605 {1, 2097152}, // R21 19606 }, 19607 clobbers: 576460746931503104, // R16 R17 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 19608 }, 19609 }, 19610 { 19611 name: "InvertFlags", 19612 argLen: 1, 19613 reg: regInfo{}, 19614 }, 19615 { 19616 name: "FlagEQ", 19617 argLen: 0, 19618 reg: regInfo{}, 19619 }, 19620 { 19621 name: "FlagLT", 19622 argLen: 0, 19623 reg: regInfo{}, 19624 }, 19625 { 19626 name: "FlagGT", 19627 argLen: 0, 19628 reg: regInfo{}, 19629 }, 19630 19631 { 19632 name: "FADDS", 19633 argLen: 2, 19634 commutative: true, 19635 resultInArg0: true, 19636 clobberFlags: true, 19637 asm: s390x.AFADDS, 19638 reg: regInfo{ 19639 inputs: []inputInfo{ 19640 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19641 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19642 }, 19643 outputs: []outputInfo{ 19644 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19645 }, 19646 }, 19647 }, 19648 { 19649 name: "FADD", 19650 argLen: 2, 19651 commutative: true, 19652 resultInArg0: true, 19653 clobberFlags: true, 19654 asm: s390x.AFADD, 19655 reg: regInfo{ 19656 inputs: []inputInfo{ 19657 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19658 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19659 }, 19660 outputs: []outputInfo{ 19661 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19662 }, 19663 }, 19664 }, 19665 { 19666 name: "FSUBS", 19667 argLen: 2, 19668 resultInArg0: true, 19669 clobberFlags: true, 19670 asm: s390x.AFSUBS, 19671 reg: regInfo{ 19672 inputs: []inputInfo{ 19673 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19674 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19675 }, 19676 outputs: []outputInfo{ 19677 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19678 }, 19679 }, 19680 }, 19681 { 19682 name: "FSUB", 19683 argLen: 2, 19684 resultInArg0: true, 19685 clobberFlags: true, 19686 asm: s390x.AFSUB, 19687 reg: regInfo{ 19688 inputs: []inputInfo{ 19689 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19690 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19691 }, 19692 outputs: []outputInfo{ 19693 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19694 }, 19695 }, 19696 }, 19697 { 19698 name: "FMULS", 19699 argLen: 2, 19700 commutative: true, 19701 resultInArg0: true, 19702 asm: s390x.AFMULS, 19703 reg: regInfo{ 19704 inputs: []inputInfo{ 19705 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19706 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19707 }, 19708 outputs: []outputInfo{ 19709 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19710 }, 19711 }, 19712 }, 19713 { 19714 name: "FMUL", 19715 argLen: 2, 19716 commutative: true, 19717 resultInArg0: true, 19718 asm: s390x.AFMUL, 19719 reg: regInfo{ 19720 inputs: []inputInfo{ 19721 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19722 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19723 }, 19724 outputs: []outputInfo{ 19725 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19726 }, 19727 }, 19728 }, 19729 { 19730 name: "FDIVS", 19731 argLen: 2, 19732 resultInArg0: true, 19733 asm: s390x.AFDIVS, 19734 reg: regInfo{ 19735 inputs: []inputInfo{ 19736 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19737 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19738 }, 19739 outputs: []outputInfo{ 19740 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19741 }, 19742 }, 19743 }, 19744 { 19745 name: "FDIV", 19746 argLen: 2, 19747 resultInArg0: true, 19748 asm: s390x.AFDIV, 19749 reg: regInfo{ 19750 inputs: []inputInfo{ 19751 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19752 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19753 }, 19754 outputs: []outputInfo{ 19755 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19756 }, 19757 }, 19758 }, 19759 { 19760 name: "FNEGS", 19761 argLen: 1, 19762 clobberFlags: true, 19763 asm: s390x.AFNEGS, 19764 reg: regInfo{ 19765 inputs: []inputInfo{ 19766 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19767 }, 19768 outputs: []outputInfo{ 19769 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19770 }, 19771 }, 19772 }, 19773 { 19774 name: "FNEG", 19775 argLen: 1, 19776 clobberFlags: true, 19777 asm: s390x.AFNEG, 19778 reg: regInfo{ 19779 inputs: []inputInfo{ 19780 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19781 }, 19782 outputs: []outputInfo{ 19783 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19784 }, 19785 }, 19786 }, 19787 { 19788 name: "FMADDS", 19789 argLen: 3, 19790 resultInArg0: true, 19791 asm: s390x.AFMADDS, 19792 reg: regInfo{ 19793 inputs: []inputInfo{ 19794 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19795 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19796 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19797 }, 19798 outputs: []outputInfo{ 19799 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19800 }, 19801 }, 19802 }, 19803 { 19804 name: "FMADD", 19805 argLen: 3, 19806 resultInArg0: true, 19807 asm: s390x.AFMADD, 19808 reg: regInfo{ 19809 inputs: []inputInfo{ 19810 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19811 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19812 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19813 }, 19814 outputs: []outputInfo{ 19815 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19816 }, 19817 }, 19818 }, 19819 { 19820 name: "FMSUBS", 19821 argLen: 3, 19822 resultInArg0: true, 19823 asm: s390x.AFMSUBS, 19824 reg: regInfo{ 19825 inputs: []inputInfo{ 19826 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19827 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19828 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19829 }, 19830 outputs: []outputInfo{ 19831 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19832 }, 19833 }, 19834 }, 19835 { 19836 name: "FMSUB", 19837 argLen: 3, 19838 resultInArg0: true, 19839 asm: s390x.AFMSUB, 19840 reg: regInfo{ 19841 inputs: []inputInfo{ 19842 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19843 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19844 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19845 }, 19846 outputs: []outputInfo{ 19847 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19848 }, 19849 }, 19850 }, 19851 { 19852 name: "LPDFR", 19853 argLen: 1, 19854 asm: s390x.ALPDFR, 19855 reg: regInfo{ 19856 inputs: []inputInfo{ 19857 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19858 }, 19859 outputs: []outputInfo{ 19860 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19861 }, 19862 }, 19863 }, 19864 { 19865 name: "LNDFR", 19866 argLen: 1, 19867 asm: s390x.ALNDFR, 19868 reg: regInfo{ 19869 inputs: []inputInfo{ 19870 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19871 }, 19872 outputs: []outputInfo{ 19873 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19874 }, 19875 }, 19876 }, 19877 { 19878 name: "CPSDR", 19879 argLen: 2, 19880 asm: s390x.ACPSDR, 19881 reg: regInfo{ 19882 inputs: []inputInfo{ 19883 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19884 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19885 }, 19886 outputs: []outputInfo{ 19887 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19888 }, 19889 }, 19890 }, 19891 { 19892 name: "FIDBR", 19893 auxType: auxInt8, 19894 argLen: 1, 19895 asm: s390x.AFIDBR, 19896 reg: regInfo{ 19897 inputs: []inputInfo{ 19898 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19899 }, 19900 outputs: []outputInfo{ 19901 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19902 }, 19903 }, 19904 }, 19905 { 19906 name: "FMOVSload", 19907 auxType: auxSymOff, 19908 argLen: 2, 19909 faultOnNilArg0: true, 19910 symEffect: SymRead, 19911 asm: s390x.AFMOVS, 19912 reg: regInfo{ 19913 inputs: []inputInfo{ 19914 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19915 }, 19916 outputs: []outputInfo{ 19917 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19918 }, 19919 }, 19920 }, 19921 { 19922 name: "FMOVDload", 19923 auxType: auxSymOff, 19924 argLen: 2, 19925 faultOnNilArg0: true, 19926 symEffect: SymRead, 19927 asm: s390x.AFMOVD, 19928 reg: regInfo{ 19929 inputs: []inputInfo{ 19930 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19931 }, 19932 outputs: []outputInfo{ 19933 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19934 }, 19935 }, 19936 }, 19937 { 19938 name: "FMOVSconst", 19939 auxType: auxFloat32, 19940 argLen: 0, 19941 rematerializeable: true, 19942 asm: s390x.AFMOVS, 19943 reg: regInfo{ 19944 outputs: []outputInfo{ 19945 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19946 }, 19947 }, 19948 }, 19949 { 19950 name: "FMOVDconst", 19951 auxType: auxFloat64, 19952 argLen: 0, 19953 rematerializeable: true, 19954 asm: s390x.AFMOVD, 19955 reg: regInfo{ 19956 outputs: []outputInfo{ 19957 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19958 }, 19959 }, 19960 }, 19961 { 19962 name: "FMOVSloadidx", 19963 auxType: auxSymOff, 19964 argLen: 3, 19965 symEffect: SymRead, 19966 asm: s390x.AFMOVS, 19967 reg: regInfo{ 19968 inputs: []inputInfo{ 19969 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19970 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19971 }, 19972 outputs: []outputInfo{ 19973 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19974 }, 19975 }, 19976 }, 19977 { 19978 name: "FMOVDloadidx", 19979 auxType: auxSymOff, 19980 argLen: 3, 19981 symEffect: SymRead, 19982 asm: s390x.AFMOVD, 19983 reg: regInfo{ 19984 inputs: []inputInfo{ 19985 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19986 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19987 }, 19988 outputs: []outputInfo{ 19989 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19990 }, 19991 }, 19992 }, 19993 { 19994 name: "FMOVSstore", 19995 auxType: auxSymOff, 19996 argLen: 3, 19997 faultOnNilArg0: true, 19998 symEffect: SymWrite, 19999 asm: s390x.AFMOVS, 20000 reg: regInfo{ 20001 inputs: []inputInfo{ 20002 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20003 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20004 }, 20005 }, 20006 }, 20007 { 20008 name: "FMOVDstore", 20009 auxType: auxSymOff, 20010 argLen: 3, 20011 faultOnNilArg0: true, 20012 symEffect: SymWrite, 20013 asm: s390x.AFMOVD, 20014 reg: regInfo{ 20015 inputs: []inputInfo{ 20016 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 20017 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20018 }, 20019 }, 20020 }, 20021 { 20022 name: "FMOVSstoreidx", 20023 auxType: auxSymOff, 20024 argLen: 4, 20025 symEffect: SymWrite, 20026 asm: s390x.AFMOVS, 20027 reg: regInfo{ 20028 inputs: []inputInfo{ 20029 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20030 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20031 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20032 }, 20033 }, 20034 }, 20035 { 20036 name: "FMOVDstoreidx", 20037 auxType: auxSymOff, 20038 argLen: 4, 20039 symEffect: SymWrite, 20040 asm: s390x.AFMOVD, 20041 reg: regInfo{ 20042 inputs: []inputInfo{ 20043 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20044 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20045 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20046 }, 20047 }, 20048 }, 20049 { 20050 name: "ADD", 20051 argLen: 2, 20052 commutative: true, 20053 clobberFlags: true, 20054 asm: s390x.AADD, 20055 reg: regInfo{ 20056 inputs: []inputInfo{ 20057 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20058 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20059 }, 20060 outputs: []outputInfo{ 20061 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20062 }, 20063 }, 20064 }, 20065 { 20066 name: "ADDW", 20067 argLen: 2, 20068 commutative: true, 20069 clobberFlags: true, 20070 asm: s390x.AADDW, 20071 reg: regInfo{ 20072 inputs: []inputInfo{ 20073 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20074 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20075 }, 20076 outputs: []outputInfo{ 20077 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20078 }, 20079 }, 20080 }, 20081 { 20082 name: "ADDconst", 20083 auxType: auxInt32, 20084 argLen: 1, 20085 clobberFlags: true, 20086 asm: s390x.AADD, 20087 reg: regInfo{ 20088 inputs: []inputInfo{ 20089 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20090 }, 20091 outputs: []outputInfo{ 20092 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20093 }, 20094 }, 20095 }, 20096 { 20097 name: "ADDWconst", 20098 auxType: auxInt32, 20099 argLen: 1, 20100 clobberFlags: true, 20101 asm: s390x.AADDW, 20102 reg: regInfo{ 20103 inputs: []inputInfo{ 20104 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20105 }, 20106 outputs: []outputInfo{ 20107 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20108 }, 20109 }, 20110 }, 20111 { 20112 name: "ADDload", 20113 auxType: auxSymOff, 20114 argLen: 3, 20115 resultInArg0: true, 20116 clobberFlags: true, 20117 faultOnNilArg1: true, 20118 symEffect: SymRead, 20119 asm: s390x.AADD, 20120 reg: regInfo{ 20121 inputs: []inputInfo{ 20122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20123 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20124 }, 20125 outputs: []outputInfo{ 20126 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20127 }, 20128 }, 20129 }, 20130 { 20131 name: "ADDWload", 20132 auxType: auxSymOff, 20133 argLen: 3, 20134 resultInArg0: true, 20135 clobberFlags: true, 20136 faultOnNilArg1: true, 20137 symEffect: SymRead, 20138 asm: s390x.AADDW, 20139 reg: regInfo{ 20140 inputs: []inputInfo{ 20141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20142 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20143 }, 20144 outputs: []outputInfo{ 20145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20146 }, 20147 }, 20148 }, 20149 { 20150 name: "SUB", 20151 argLen: 2, 20152 clobberFlags: true, 20153 asm: s390x.ASUB, 20154 reg: regInfo{ 20155 inputs: []inputInfo{ 20156 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20157 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20158 }, 20159 outputs: []outputInfo{ 20160 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20161 }, 20162 }, 20163 }, 20164 { 20165 name: "SUBW", 20166 argLen: 2, 20167 clobberFlags: true, 20168 asm: s390x.ASUBW, 20169 reg: regInfo{ 20170 inputs: []inputInfo{ 20171 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20172 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20173 }, 20174 outputs: []outputInfo{ 20175 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20176 }, 20177 }, 20178 }, 20179 { 20180 name: "SUBconst", 20181 auxType: auxInt32, 20182 argLen: 1, 20183 resultInArg0: true, 20184 clobberFlags: true, 20185 asm: s390x.ASUB, 20186 reg: regInfo{ 20187 inputs: []inputInfo{ 20188 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20189 }, 20190 outputs: []outputInfo{ 20191 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20192 }, 20193 }, 20194 }, 20195 { 20196 name: "SUBWconst", 20197 auxType: auxInt32, 20198 argLen: 1, 20199 resultInArg0: true, 20200 clobberFlags: true, 20201 asm: s390x.ASUBW, 20202 reg: regInfo{ 20203 inputs: []inputInfo{ 20204 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20205 }, 20206 outputs: []outputInfo{ 20207 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20208 }, 20209 }, 20210 }, 20211 { 20212 name: "SUBload", 20213 auxType: auxSymOff, 20214 argLen: 3, 20215 resultInArg0: true, 20216 clobberFlags: true, 20217 faultOnNilArg1: true, 20218 symEffect: SymRead, 20219 asm: s390x.ASUB, 20220 reg: regInfo{ 20221 inputs: []inputInfo{ 20222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20223 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20224 }, 20225 outputs: []outputInfo{ 20226 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20227 }, 20228 }, 20229 }, 20230 { 20231 name: "SUBWload", 20232 auxType: auxSymOff, 20233 argLen: 3, 20234 resultInArg0: true, 20235 clobberFlags: true, 20236 faultOnNilArg1: true, 20237 symEffect: SymRead, 20238 asm: s390x.ASUBW, 20239 reg: regInfo{ 20240 inputs: []inputInfo{ 20241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20242 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20243 }, 20244 outputs: []outputInfo{ 20245 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20246 }, 20247 }, 20248 }, 20249 { 20250 name: "MULLD", 20251 argLen: 2, 20252 commutative: true, 20253 resultInArg0: true, 20254 clobberFlags: true, 20255 asm: s390x.AMULLD, 20256 reg: regInfo{ 20257 inputs: []inputInfo{ 20258 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20259 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20260 }, 20261 outputs: []outputInfo{ 20262 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20263 }, 20264 }, 20265 }, 20266 { 20267 name: "MULLW", 20268 argLen: 2, 20269 commutative: true, 20270 resultInArg0: true, 20271 clobberFlags: true, 20272 asm: s390x.AMULLW, 20273 reg: regInfo{ 20274 inputs: []inputInfo{ 20275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20276 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20277 }, 20278 outputs: []outputInfo{ 20279 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20280 }, 20281 }, 20282 }, 20283 { 20284 name: "MULLDconst", 20285 auxType: auxInt32, 20286 argLen: 1, 20287 resultInArg0: true, 20288 clobberFlags: true, 20289 asm: s390x.AMULLD, 20290 reg: regInfo{ 20291 inputs: []inputInfo{ 20292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20293 }, 20294 outputs: []outputInfo{ 20295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20296 }, 20297 }, 20298 }, 20299 { 20300 name: "MULLWconst", 20301 auxType: auxInt32, 20302 argLen: 1, 20303 resultInArg0: true, 20304 clobberFlags: true, 20305 asm: s390x.AMULLW, 20306 reg: regInfo{ 20307 inputs: []inputInfo{ 20308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20309 }, 20310 outputs: []outputInfo{ 20311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20312 }, 20313 }, 20314 }, 20315 { 20316 name: "MULLDload", 20317 auxType: auxSymOff, 20318 argLen: 3, 20319 resultInArg0: true, 20320 clobberFlags: true, 20321 faultOnNilArg1: true, 20322 symEffect: SymRead, 20323 asm: s390x.AMULLD, 20324 reg: regInfo{ 20325 inputs: []inputInfo{ 20326 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20327 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20328 }, 20329 outputs: []outputInfo{ 20330 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20331 }, 20332 }, 20333 }, 20334 { 20335 name: "MULLWload", 20336 auxType: auxSymOff, 20337 argLen: 3, 20338 resultInArg0: true, 20339 clobberFlags: true, 20340 faultOnNilArg1: true, 20341 symEffect: SymRead, 20342 asm: s390x.AMULLW, 20343 reg: regInfo{ 20344 inputs: []inputInfo{ 20345 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20346 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20347 }, 20348 outputs: []outputInfo{ 20349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20350 }, 20351 }, 20352 }, 20353 { 20354 name: "MULHD", 20355 argLen: 2, 20356 commutative: true, 20357 resultInArg0: true, 20358 clobberFlags: true, 20359 asm: s390x.AMULHD, 20360 reg: regInfo{ 20361 inputs: []inputInfo{ 20362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20363 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20364 }, 20365 outputs: []outputInfo{ 20366 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20367 }, 20368 }, 20369 }, 20370 { 20371 name: "MULHDU", 20372 argLen: 2, 20373 commutative: true, 20374 resultInArg0: true, 20375 clobberFlags: true, 20376 asm: s390x.AMULHDU, 20377 reg: regInfo{ 20378 inputs: []inputInfo{ 20379 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20380 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20381 }, 20382 outputs: []outputInfo{ 20383 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20384 }, 20385 }, 20386 }, 20387 { 20388 name: "DIVD", 20389 argLen: 2, 20390 resultInArg0: true, 20391 clobberFlags: true, 20392 asm: s390x.ADIVD, 20393 reg: regInfo{ 20394 inputs: []inputInfo{ 20395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20396 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20397 }, 20398 outputs: []outputInfo{ 20399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20400 }, 20401 }, 20402 }, 20403 { 20404 name: "DIVW", 20405 argLen: 2, 20406 resultInArg0: true, 20407 clobberFlags: true, 20408 asm: s390x.ADIVW, 20409 reg: regInfo{ 20410 inputs: []inputInfo{ 20411 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20412 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20413 }, 20414 outputs: []outputInfo{ 20415 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20416 }, 20417 }, 20418 }, 20419 { 20420 name: "DIVDU", 20421 argLen: 2, 20422 resultInArg0: true, 20423 clobberFlags: true, 20424 asm: s390x.ADIVDU, 20425 reg: regInfo{ 20426 inputs: []inputInfo{ 20427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20428 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20429 }, 20430 outputs: []outputInfo{ 20431 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20432 }, 20433 }, 20434 }, 20435 { 20436 name: "DIVWU", 20437 argLen: 2, 20438 resultInArg0: true, 20439 clobberFlags: true, 20440 asm: s390x.ADIVWU, 20441 reg: regInfo{ 20442 inputs: []inputInfo{ 20443 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20444 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20445 }, 20446 outputs: []outputInfo{ 20447 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20448 }, 20449 }, 20450 }, 20451 { 20452 name: "MODD", 20453 argLen: 2, 20454 resultInArg0: true, 20455 clobberFlags: true, 20456 asm: s390x.AMODD, 20457 reg: regInfo{ 20458 inputs: []inputInfo{ 20459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20460 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20461 }, 20462 outputs: []outputInfo{ 20463 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20464 }, 20465 }, 20466 }, 20467 { 20468 name: "MODW", 20469 argLen: 2, 20470 resultInArg0: true, 20471 clobberFlags: true, 20472 asm: s390x.AMODW, 20473 reg: regInfo{ 20474 inputs: []inputInfo{ 20475 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20476 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20477 }, 20478 outputs: []outputInfo{ 20479 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20480 }, 20481 }, 20482 }, 20483 { 20484 name: "MODDU", 20485 argLen: 2, 20486 resultInArg0: true, 20487 clobberFlags: true, 20488 asm: s390x.AMODDU, 20489 reg: regInfo{ 20490 inputs: []inputInfo{ 20491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20492 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20493 }, 20494 outputs: []outputInfo{ 20495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20496 }, 20497 }, 20498 }, 20499 { 20500 name: "MODWU", 20501 argLen: 2, 20502 resultInArg0: true, 20503 clobberFlags: true, 20504 asm: s390x.AMODWU, 20505 reg: regInfo{ 20506 inputs: []inputInfo{ 20507 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20508 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20509 }, 20510 outputs: []outputInfo{ 20511 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20512 }, 20513 }, 20514 }, 20515 { 20516 name: "AND", 20517 argLen: 2, 20518 commutative: true, 20519 clobberFlags: true, 20520 asm: s390x.AAND, 20521 reg: regInfo{ 20522 inputs: []inputInfo{ 20523 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20524 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20525 }, 20526 outputs: []outputInfo{ 20527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20528 }, 20529 }, 20530 }, 20531 { 20532 name: "ANDW", 20533 argLen: 2, 20534 commutative: true, 20535 clobberFlags: true, 20536 asm: s390x.AANDW, 20537 reg: regInfo{ 20538 inputs: []inputInfo{ 20539 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20540 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20541 }, 20542 outputs: []outputInfo{ 20543 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20544 }, 20545 }, 20546 }, 20547 { 20548 name: "ANDconst", 20549 auxType: auxInt64, 20550 argLen: 1, 20551 resultInArg0: true, 20552 clobberFlags: true, 20553 asm: s390x.AAND, 20554 reg: regInfo{ 20555 inputs: []inputInfo{ 20556 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20557 }, 20558 outputs: []outputInfo{ 20559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20560 }, 20561 }, 20562 }, 20563 { 20564 name: "ANDWconst", 20565 auxType: auxInt32, 20566 argLen: 1, 20567 resultInArg0: true, 20568 clobberFlags: true, 20569 asm: s390x.AANDW, 20570 reg: regInfo{ 20571 inputs: []inputInfo{ 20572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20573 }, 20574 outputs: []outputInfo{ 20575 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20576 }, 20577 }, 20578 }, 20579 { 20580 name: "ANDload", 20581 auxType: auxSymOff, 20582 argLen: 3, 20583 resultInArg0: true, 20584 clobberFlags: true, 20585 faultOnNilArg1: true, 20586 symEffect: SymRead, 20587 asm: s390x.AAND, 20588 reg: regInfo{ 20589 inputs: []inputInfo{ 20590 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20591 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20592 }, 20593 outputs: []outputInfo{ 20594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20595 }, 20596 }, 20597 }, 20598 { 20599 name: "ANDWload", 20600 auxType: auxSymOff, 20601 argLen: 3, 20602 resultInArg0: true, 20603 clobberFlags: true, 20604 faultOnNilArg1: true, 20605 symEffect: SymRead, 20606 asm: s390x.AANDW, 20607 reg: regInfo{ 20608 inputs: []inputInfo{ 20609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20610 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20611 }, 20612 outputs: []outputInfo{ 20613 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20614 }, 20615 }, 20616 }, 20617 { 20618 name: "OR", 20619 argLen: 2, 20620 commutative: true, 20621 clobberFlags: true, 20622 asm: s390x.AOR, 20623 reg: regInfo{ 20624 inputs: []inputInfo{ 20625 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20626 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20627 }, 20628 outputs: []outputInfo{ 20629 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20630 }, 20631 }, 20632 }, 20633 { 20634 name: "ORW", 20635 argLen: 2, 20636 commutative: true, 20637 clobberFlags: true, 20638 asm: s390x.AORW, 20639 reg: regInfo{ 20640 inputs: []inputInfo{ 20641 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20642 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20643 }, 20644 outputs: []outputInfo{ 20645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20646 }, 20647 }, 20648 }, 20649 { 20650 name: "ORconst", 20651 auxType: auxInt64, 20652 argLen: 1, 20653 resultInArg0: true, 20654 clobberFlags: true, 20655 asm: s390x.AOR, 20656 reg: regInfo{ 20657 inputs: []inputInfo{ 20658 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20659 }, 20660 outputs: []outputInfo{ 20661 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20662 }, 20663 }, 20664 }, 20665 { 20666 name: "ORWconst", 20667 auxType: auxInt32, 20668 argLen: 1, 20669 resultInArg0: true, 20670 clobberFlags: true, 20671 asm: s390x.AORW, 20672 reg: regInfo{ 20673 inputs: []inputInfo{ 20674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20675 }, 20676 outputs: []outputInfo{ 20677 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20678 }, 20679 }, 20680 }, 20681 { 20682 name: "ORload", 20683 auxType: auxSymOff, 20684 argLen: 3, 20685 resultInArg0: true, 20686 clobberFlags: true, 20687 faultOnNilArg1: true, 20688 symEffect: SymRead, 20689 asm: s390x.AOR, 20690 reg: regInfo{ 20691 inputs: []inputInfo{ 20692 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20693 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20694 }, 20695 outputs: []outputInfo{ 20696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20697 }, 20698 }, 20699 }, 20700 { 20701 name: "ORWload", 20702 auxType: auxSymOff, 20703 argLen: 3, 20704 resultInArg0: true, 20705 clobberFlags: true, 20706 faultOnNilArg1: true, 20707 symEffect: SymRead, 20708 asm: s390x.AORW, 20709 reg: regInfo{ 20710 inputs: []inputInfo{ 20711 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20712 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20713 }, 20714 outputs: []outputInfo{ 20715 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20716 }, 20717 }, 20718 }, 20719 { 20720 name: "XOR", 20721 argLen: 2, 20722 commutative: true, 20723 clobberFlags: true, 20724 asm: s390x.AXOR, 20725 reg: regInfo{ 20726 inputs: []inputInfo{ 20727 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20728 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20729 }, 20730 outputs: []outputInfo{ 20731 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20732 }, 20733 }, 20734 }, 20735 { 20736 name: "XORW", 20737 argLen: 2, 20738 commutative: true, 20739 clobberFlags: true, 20740 asm: s390x.AXORW, 20741 reg: regInfo{ 20742 inputs: []inputInfo{ 20743 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20744 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20745 }, 20746 outputs: []outputInfo{ 20747 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20748 }, 20749 }, 20750 }, 20751 { 20752 name: "XORconst", 20753 auxType: auxInt64, 20754 argLen: 1, 20755 resultInArg0: true, 20756 clobberFlags: true, 20757 asm: s390x.AXOR, 20758 reg: regInfo{ 20759 inputs: []inputInfo{ 20760 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20761 }, 20762 outputs: []outputInfo{ 20763 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20764 }, 20765 }, 20766 }, 20767 { 20768 name: "XORWconst", 20769 auxType: auxInt32, 20770 argLen: 1, 20771 resultInArg0: true, 20772 clobberFlags: true, 20773 asm: s390x.AXORW, 20774 reg: regInfo{ 20775 inputs: []inputInfo{ 20776 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20777 }, 20778 outputs: []outputInfo{ 20779 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20780 }, 20781 }, 20782 }, 20783 { 20784 name: "XORload", 20785 auxType: auxSymOff, 20786 argLen: 3, 20787 resultInArg0: true, 20788 clobberFlags: true, 20789 faultOnNilArg1: true, 20790 symEffect: SymRead, 20791 asm: s390x.AXOR, 20792 reg: regInfo{ 20793 inputs: []inputInfo{ 20794 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20795 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20796 }, 20797 outputs: []outputInfo{ 20798 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20799 }, 20800 }, 20801 }, 20802 { 20803 name: "XORWload", 20804 auxType: auxSymOff, 20805 argLen: 3, 20806 resultInArg0: true, 20807 clobberFlags: true, 20808 faultOnNilArg1: true, 20809 symEffect: SymRead, 20810 asm: s390x.AXORW, 20811 reg: regInfo{ 20812 inputs: []inputInfo{ 20813 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20814 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20815 }, 20816 outputs: []outputInfo{ 20817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20818 }, 20819 }, 20820 }, 20821 { 20822 name: "CMP", 20823 argLen: 2, 20824 asm: s390x.ACMP, 20825 reg: regInfo{ 20826 inputs: []inputInfo{ 20827 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20828 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20829 }, 20830 }, 20831 }, 20832 { 20833 name: "CMPW", 20834 argLen: 2, 20835 asm: s390x.ACMPW, 20836 reg: regInfo{ 20837 inputs: []inputInfo{ 20838 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20839 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20840 }, 20841 }, 20842 }, 20843 { 20844 name: "CMPU", 20845 argLen: 2, 20846 asm: s390x.ACMPU, 20847 reg: regInfo{ 20848 inputs: []inputInfo{ 20849 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20850 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20851 }, 20852 }, 20853 }, 20854 { 20855 name: "CMPWU", 20856 argLen: 2, 20857 asm: s390x.ACMPWU, 20858 reg: regInfo{ 20859 inputs: []inputInfo{ 20860 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20861 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20862 }, 20863 }, 20864 }, 20865 { 20866 name: "CMPconst", 20867 auxType: auxInt32, 20868 argLen: 1, 20869 asm: s390x.ACMP, 20870 reg: regInfo{ 20871 inputs: []inputInfo{ 20872 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20873 }, 20874 }, 20875 }, 20876 { 20877 name: "CMPWconst", 20878 auxType: auxInt32, 20879 argLen: 1, 20880 asm: s390x.ACMPW, 20881 reg: regInfo{ 20882 inputs: []inputInfo{ 20883 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20884 }, 20885 }, 20886 }, 20887 { 20888 name: "CMPUconst", 20889 auxType: auxInt32, 20890 argLen: 1, 20891 asm: s390x.ACMPU, 20892 reg: regInfo{ 20893 inputs: []inputInfo{ 20894 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20895 }, 20896 }, 20897 }, 20898 { 20899 name: "CMPWUconst", 20900 auxType: auxInt32, 20901 argLen: 1, 20902 asm: s390x.ACMPWU, 20903 reg: regInfo{ 20904 inputs: []inputInfo{ 20905 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20906 }, 20907 }, 20908 }, 20909 { 20910 name: "FCMPS", 20911 argLen: 2, 20912 asm: s390x.ACEBR, 20913 reg: regInfo{ 20914 inputs: []inputInfo{ 20915 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20916 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20917 }, 20918 }, 20919 }, 20920 { 20921 name: "FCMP", 20922 argLen: 2, 20923 asm: s390x.AFCMPU, 20924 reg: regInfo{ 20925 inputs: []inputInfo{ 20926 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20927 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20928 }, 20929 }, 20930 }, 20931 { 20932 name: "SLD", 20933 argLen: 2, 20934 asm: s390x.ASLD, 20935 reg: regInfo{ 20936 inputs: []inputInfo{ 20937 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20939 }, 20940 outputs: []outputInfo{ 20941 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20942 }, 20943 }, 20944 }, 20945 { 20946 name: "SLW", 20947 argLen: 2, 20948 asm: s390x.ASLW, 20949 reg: regInfo{ 20950 inputs: []inputInfo{ 20951 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20952 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20953 }, 20954 outputs: []outputInfo{ 20955 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20956 }, 20957 }, 20958 }, 20959 { 20960 name: "SLDconst", 20961 auxType: auxInt8, 20962 argLen: 1, 20963 asm: s390x.ASLD, 20964 reg: regInfo{ 20965 inputs: []inputInfo{ 20966 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20967 }, 20968 outputs: []outputInfo{ 20969 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20970 }, 20971 }, 20972 }, 20973 { 20974 name: "SLWconst", 20975 auxType: auxInt8, 20976 argLen: 1, 20977 asm: s390x.ASLW, 20978 reg: regInfo{ 20979 inputs: []inputInfo{ 20980 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20981 }, 20982 outputs: []outputInfo{ 20983 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20984 }, 20985 }, 20986 }, 20987 { 20988 name: "SRD", 20989 argLen: 2, 20990 asm: s390x.ASRD, 20991 reg: regInfo{ 20992 inputs: []inputInfo{ 20993 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20994 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20995 }, 20996 outputs: []outputInfo{ 20997 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20998 }, 20999 }, 21000 }, 21001 { 21002 name: "SRW", 21003 argLen: 2, 21004 asm: s390x.ASRW, 21005 reg: regInfo{ 21006 inputs: []inputInfo{ 21007 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21009 }, 21010 outputs: []outputInfo{ 21011 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21012 }, 21013 }, 21014 }, 21015 { 21016 name: "SRDconst", 21017 auxType: auxInt8, 21018 argLen: 1, 21019 asm: s390x.ASRD, 21020 reg: regInfo{ 21021 inputs: []inputInfo{ 21022 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21023 }, 21024 outputs: []outputInfo{ 21025 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21026 }, 21027 }, 21028 }, 21029 { 21030 name: "SRWconst", 21031 auxType: auxInt8, 21032 argLen: 1, 21033 asm: s390x.ASRW, 21034 reg: regInfo{ 21035 inputs: []inputInfo{ 21036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21037 }, 21038 outputs: []outputInfo{ 21039 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21040 }, 21041 }, 21042 }, 21043 { 21044 name: "SRAD", 21045 argLen: 2, 21046 clobberFlags: true, 21047 asm: s390x.ASRAD, 21048 reg: regInfo{ 21049 inputs: []inputInfo{ 21050 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21052 }, 21053 outputs: []outputInfo{ 21054 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21055 }, 21056 }, 21057 }, 21058 { 21059 name: "SRAW", 21060 argLen: 2, 21061 clobberFlags: true, 21062 asm: s390x.ASRAW, 21063 reg: regInfo{ 21064 inputs: []inputInfo{ 21065 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21067 }, 21068 outputs: []outputInfo{ 21069 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21070 }, 21071 }, 21072 }, 21073 { 21074 name: "SRADconst", 21075 auxType: auxInt8, 21076 argLen: 1, 21077 clobberFlags: true, 21078 asm: s390x.ASRAD, 21079 reg: regInfo{ 21080 inputs: []inputInfo{ 21081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21082 }, 21083 outputs: []outputInfo{ 21084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21085 }, 21086 }, 21087 }, 21088 { 21089 name: "SRAWconst", 21090 auxType: auxInt8, 21091 argLen: 1, 21092 clobberFlags: true, 21093 asm: s390x.ASRAW, 21094 reg: regInfo{ 21095 inputs: []inputInfo{ 21096 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21097 }, 21098 outputs: []outputInfo{ 21099 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21100 }, 21101 }, 21102 }, 21103 { 21104 name: "RLLGconst", 21105 auxType: auxInt8, 21106 argLen: 1, 21107 asm: s390x.ARLLG, 21108 reg: regInfo{ 21109 inputs: []inputInfo{ 21110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21111 }, 21112 outputs: []outputInfo{ 21113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21114 }, 21115 }, 21116 }, 21117 { 21118 name: "RLLconst", 21119 auxType: auxInt8, 21120 argLen: 1, 21121 asm: s390x.ARLL, 21122 reg: regInfo{ 21123 inputs: []inputInfo{ 21124 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21125 }, 21126 outputs: []outputInfo{ 21127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21128 }, 21129 }, 21130 }, 21131 { 21132 name: "NEG", 21133 argLen: 1, 21134 clobberFlags: true, 21135 asm: s390x.ANEG, 21136 reg: regInfo{ 21137 inputs: []inputInfo{ 21138 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21139 }, 21140 outputs: []outputInfo{ 21141 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21142 }, 21143 }, 21144 }, 21145 { 21146 name: "NEGW", 21147 argLen: 1, 21148 clobberFlags: true, 21149 asm: s390x.ANEGW, 21150 reg: regInfo{ 21151 inputs: []inputInfo{ 21152 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21153 }, 21154 outputs: []outputInfo{ 21155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21156 }, 21157 }, 21158 }, 21159 { 21160 name: "NOT", 21161 argLen: 1, 21162 resultInArg0: true, 21163 clobberFlags: true, 21164 reg: regInfo{ 21165 inputs: []inputInfo{ 21166 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21167 }, 21168 outputs: []outputInfo{ 21169 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21170 }, 21171 }, 21172 }, 21173 { 21174 name: "NOTW", 21175 argLen: 1, 21176 resultInArg0: true, 21177 clobberFlags: true, 21178 reg: regInfo{ 21179 inputs: []inputInfo{ 21180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21181 }, 21182 outputs: []outputInfo{ 21183 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21184 }, 21185 }, 21186 }, 21187 { 21188 name: "FSQRT", 21189 argLen: 1, 21190 asm: s390x.AFSQRT, 21191 reg: regInfo{ 21192 inputs: []inputInfo{ 21193 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21194 }, 21195 outputs: []outputInfo{ 21196 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21197 }, 21198 }, 21199 }, 21200 { 21201 name: "SUBEcarrymask", 21202 argLen: 1, 21203 asm: s390x.ASUBE, 21204 reg: regInfo{ 21205 outputs: []outputInfo{ 21206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21207 }, 21208 }, 21209 }, 21210 { 21211 name: "SUBEWcarrymask", 21212 argLen: 1, 21213 asm: s390x.ASUBE, 21214 reg: regInfo{ 21215 outputs: []outputInfo{ 21216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21217 }, 21218 }, 21219 }, 21220 { 21221 name: "MOVDEQ", 21222 argLen: 3, 21223 resultInArg0: true, 21224 asm: s390x.AMOVDEQ, 21225 reg: regInfo{ 21226 inputs: []inputInfo{ 21227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21228 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21229 }, 21230 outputs: []outputInfo{ 21231 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21232 }, 21233 }, 21234 }, 21235 { 21236 name: "MOVDNE", 21237 argLen: 3, 21238 resultInArg0: true, 21239 asm: s390x.AMOVDNE, 21240 reg: regInfo{ 21241 inputs: []inputInfo{ 21242 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21243 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21244 }, 21245 outputs: []outputInfo{ 21246 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21247 }, 21248 }, 21249 }, 21250 { 21251 name: "MOVDLT", 21252 argLen: 3, 21253 resultInArg0: true, 21254 asm: s390x.AMOVDLT, 21255 reg: regInfo{ 21256 inputs: []inputInfo{ 21257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21258 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21259 }, 21260 outputs: []outputInfo{ 21261 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21262 }, 21263 }, 21264 }, 21265 { 21266 name: "MOVDLE", 21267 argLen: 3, 21268 resultInArg0: true, 21269 asm: s390x.AMOVDLE, 21270 reg: regInfo{ 21271 inputs: []inputInfo{ 21272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21273 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21274 }, 21275 outputs: []outputInfo{ 21276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21277 }, 21278 }, 21279 }, 21280 { 21281 name: "MOVDGT", 21282 argLen: 3, 21283 resultInArg0: true, 21284 asm: s390x.AMOVDGT, 21285 reg: regInfo{ 21286 inputs: []inputInfo{ 21287 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21288 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21289 }, 21290 outputs: []outputInfo{ 21291 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21292 }, 21293 }, 21294 }, 21295 { 21296 name: "MOVDGE", 21297 argLen: 3, 21298 resultInArg0: true, 21299 asm: s390x.AMOVDGE, 21300 reg: regInfo{ 21301 inputs: []inputInfo{ 21302 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21303 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21304 }, 21305 outputs: []outputInfo{ 21306 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21307 }, 21308 }, 21309 }, 21310 { 21311 name: "MOVDGTnoinv", 21312 argLen: 3, 21313 resultInArg0: true, 21314 asm: s390x.AMOVDGT, 21315 reg: regInfo{ 21316 inputs: []inputInfo{ 21317 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21318 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21319 }, 21320 outputs: []outputInfo{ 21321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21322 }, 21323 }, 21324 }, 21325 { 21326 name: "MOVDGEnoinv", 21327 argLen: 3, 21328 resultInArg0: true, 21329 asm: s390x.AMOVDGE, 21330 reg: regInfo{ 21331 inputs: []inputInfo{ 21332 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21333 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21334 }, 21335 outputs: []outputInfo{ 21336 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21337 }, 21338 }, 21339 }, 21340 { 21341 name: "MOVBreg", 21342 argLen: 1, 21343 asm: s390x.AMOVB, 21344 reg: regInfo{ 21345 inputs: []inputInfo{ 21346 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21347 }, 21348 outputs: []outputInfo{ 21349 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21350 }, 21351 }, 21352 }, 21353 { 21354 name: "MOVBZreg", 21355 argLen: 1, 21356 asm: s390x.AMOVBZ, 21357 reg: regInfo{ 21358 inputs: []inputInfo{ 21359 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21360 }, 21361 outputs: []outputInfo{ 21362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21363 }, 21364 }, 21365 }, 21366 { 21367 name: "MOVHreg", 21368 argLen: 1, 21369 asm: s390x.AMOVH, 21370 reg: regInfo{ 21371 inputs: []inputInfo{ 21372 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21373 }, 21374 outputs: []outputInfo{ 21375 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21376 }, 21377 }, 21378 }, 21379 { 21380 name: "MOVHZreg", 21381 argLen: 1, 21382 asm: s390x.AMOVHZ, 21383 reg: regInfo{ 21384 inputs: []inputInfo{ 21385 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21386 }, 21387 outputs: []outputInfo{ 21388 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21389 }, 21390 }, 21391 }, 21392 { 21393 name: "MOVWreg", 21394 argLen: 1, 21395 asm: s390x.AMOVW, 21396 reg: regInfo{ 21397 inputs: []inputInfo{ 21398 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21399 }, 21400 outputs: []outputInfo{ 21401 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21402 }, 21403 }, 21404 }, 21405 { 21406 name: "MOVWZreg", 21407 argLen: 1, 21408 asm: s390x.AMOVWZ, 21409 reg: regInfo{ 21410 inputs: []inputInfo{ 21411 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21412 }, 21413 outputs: []outputInfo{ 21414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21415 }, 21416 }, 21417 }, 21418 { 21419 name: "MOVDreg", 21420 argLen: 1, 21421 asm: s390x.AMOVD, 21422 reg: regInfo{ 21423 inputs: []inputInfo{ 21424 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21425 }, 21426 outputs: []outputInfo{ 21427 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21428 }, 21429 }, 21430 }, 21431 { 21432 name: "MOVDnop", 21433 argLen: 1, 21434 resultInArg0: true, 21435 reg: regInfo{ 21436 inputs: []inputInfo{ 21437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21438 }, 21439 outputs: []outputInfo{ 21440 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21441 }, 21442 }, 21443 }, 21444 { 21445 name: "MOVDconst", 21446 auxType: auxInt64, 21447 argLen: 0, 21448 rematerializeable: true, 21449 asm: s390x.AMOVD, 21450 reg: regInfo{ 21451 outputs: []outputInfo{ 21452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21453 }, 21454 }, 21455 }, 21456 { 21457 name: "LDGR", 21458 argLen: 1, 21459 asm: s390x.ALDGR, 21460 reg: regInfo{ 21461 inputs: []inputInfo{ 21462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21463 }, 21464 outputs: []outputInfo{ 21465 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21466 }, 21467 }, 21468 }, 21469 { 21470 name: "LGDR", 21471 argLen: 1, 21472 asm: s390x.ALGDR, 21473 reg: regInfo{ 21474 inputs: []inputInfo{ 21475 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21476 }, 21477 outputs: []outputInfo{ 21478 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21479 }, 21480 }, 21481 }, 21482 { 21483 name: "CFDBRA", 21484 argLen: 1, 21485 asm: s390x.ACFDBRA, 21486 reg: regInfo{ 21487 inputs: []inputInfo{ 21488 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21489 }, 21490 outputs: []outputInfo{ 21491 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21492 }, 21493 }, 21494 }, 21495 { 21496 name: "CGDBRA", 21497 argLen: 1, 21498 asm: s390x.ACGDBRA, 21499 reg: regInfo{ 21500 inputs: []inputInfo{ 21501 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21502 }, 21503 outputs: []outputInfo{ 21504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21505 }, 21506 }, 21507 }, 21508 { 21509 name: "CFEBRA", 21510 argLen: 1, 21511 asm: s390x.ACFEBRA, 21512 reg: regInfo{ 21513 inputs: []inputInfo{ 21514 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21515 }, 21516 outputs: []outputInfo{ 21517 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21518 }, 21519 }, 21520 }, 21521 { 21522 name: "CGEBRA", 21523 argLen: 1, 21524 asm: s390x.ACGEBRA, 21525 reg: regInfo{ 21526 inputs: []inputInfo{ 21527 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21528 }, 21529 outputs: []outputInfo{ 21530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21531 }, 21532 }, 21533 }, 21534 { 21535 name: "CEFBRA", 21536 argLen: 1, 21537 asm: s390x.ACEFBRA, 21538 reg: regInfo{ 21539 inputs: []inputInfo{ 21540 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21541 }, 21542 outputs: []outputInfo{ 21543 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21544 }, 21545 }, 21546 }, 21547 { 21548 name: "CDFBRA", 21549 argLen: 1, 21550 asm: s390x.ACDFBRA, 21551 reg: regInfo{ 21552 inputs: []inputInfo{ 21553 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21554 }, 21555 outputs: []outputInfo{ 21556 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21557 }, 21558 }, 21559 }, 21560 { 21561 name: "CEGBRA", 21562 argLen: 1, 21563 asm: s390x.ACEGBRA, 21564 reg: regInfo{ 21565 inputs: []inputInfo{ 21566 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21567 }, 21568 outputs: []outputInfo{ 21569 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21570 }, 21571 }, 21572 }, 21573 { 21574 name: "CDGBRA", 21575 argLen: 1, 21576 asm: s390x.ACDGBRA, 21577 reg: regInfo{ 21578 inputs: []inputInfo{ 21579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21580 }, 21581 outputs: []outputInfo{ 21582 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21583 }, 21584 }, 21585 }, 21586 { 21587 name: "LEDBR", 21588 argLen: 1, 21589 asm: s390x.ALEDBR, 21590 reg: regInfo{ 21591 inputs: []inputInfo{ 21592 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21593 }, 21594 outputs: []outputInfo{ 21595 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21596 }, 21597 }, 21598 }, 21599 { 21600 name: "LDEBR", 21601 argLen: 1, 21602 asm: s390x.ALDEBR, 21603 reg: regInfo{ 21604 inputs: []inputInfo{ 21605 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21606 }, 21607 outputs: []outputInfo{ 21608 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21609 }, 21610 }, 21611 }, 21612 { 21613 name: "MOVDaddr", 21614 auxType: auxSymOff, 21615 argLen: 1, 21616 rematerializeable: true, 21617 symEffect: SymRead, 21618 reg: regInfo{ 21619 inputs: []inputInfo{ 21620 {0, 4295000064}, // SP SB 21621 }, 21622 outputs: []outputInfo{ 21623 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21624 }, 21625 }, 21626 }, 21627 { 21628 name: "MOVDaddridx", 21629 auxType: auxSymOff, 21630 argLen: 2, 21631 symEffect: SymRead, 21632 reg: regInfo{ 21633 inputs: []inputInfo{ 21634 {0, 4295000064}, // SP SB 21635 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21636 }, 21637 outputs: []outputInfo{ 21638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21639 }, 21640 }, 21641 }, 21642 { 21643 name: "MOVBZload", 21644 auxType: auxSymOff, 21645 argLen: 2, 21646 clobberFlags: true, 21647 faultOnNilArg0: true, 21648 symEffect: SymRead, 21649 asm: s390x.AMOVBZ, 21650 reg: regInfo{ 21651 inputs: []inputInfo{ 21652 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21653 }, 21654 outputs: []outputInfo{ 21655 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21656 }, 21657 }, 21658 }, 21659 { 21660 name: "MOVBload", 21661 auxType: auxSymOff, 21662 argLen: 2, 21663 clobberFlags: true, 21664 faultOnNilArg0: true, 21665 symEffect: SymRead, 21666 asm: s390x.AMOVB, 21667 reg: regInfo{ 21668 inputs: []inputInfo{ 21669 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21670 }, 21671 outputs: []outputInfo{ 21672 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21673 }, 21674 }, 21675 }, 21676 { 21677 name: "MOVHZload", 21678 auxType: auxSymOff, 21679 argLen: 2, 21680 clobberFlags: true, 21681 faultOnNilArg0: true, 21682 symEffect: SymRead, 21683 asm: s390x.AMOVHZ, 21684 reg: regInfo{ 21685 inputs: []inputInfo{ 21686 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21687 }, 21688 outputs: []outputInfo{ 21689 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21690 }, 21691 }, 21692 }, 21693 { 21694 name: "MOVHload", 21695 auxType: auxSymOff, 21696 argLen: 2, 21697 clobberFlags: true, 21698 faultOnNilArg0: true, 21699 symEffect: SymRead, 21700 asm: s390x.AMOVH, 21701 reg: regInfo{ 21702 inputs: []inputInfo{ 21703 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21704 }, 21705 outputs: []outputInfo{ 21706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21707 }, 21708 }, 21709 }, 21710 { 21711 name: "MOVWZload", 21712 auxType: auxSymOff, 21713 argLen: 2, 21714 clobberFlags: true, 21715 faultOnNilArg0: true, 21716 symEffect: SymRead, 21717 asm: s390x.AMOVWZ, 21718 reg: regInfo{ 21719 inputs: []inputInfo{ 21720 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21721 }, 21722 outputs: []outputInfo{ 21723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21724 }, 21725 }, 21726 }, 21727 { 21728 name: "MOVWload", 21729 auxType: auxSymOff, 21730 argLen: 2, 21731 clobberFlags: true, 21732 faultOnNilArg0: true, 21733 symEffect: SymRead, 21734 asm: s390x.AMOVW, 21735 reg: regInfo{ 21736 inputs: []inputInfo{ 21737 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21738 }, 21739 outputs: []outputInfo{ 21740 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21741 }, 21742 }, 21743 }, 21744 { 21745 name: "MOVDload", 21746 auxType: auxSymOff, 21747 argLen: 2, 21748 clobberFlags: true, 21749 faultOnNilArg0: true, 21750 symEffect: SymRead, 21751 asm: s390x.AMOVD, 21752 reg: regInfo{ 21753 inputs: []inputInfo{ 21754 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21755 }, 21756 outputs: []outputInfo{ 21757 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21758 }, 21759 }, 21760 }, 21761 { 21762 name: "MOVWBR", 21763 argLen: 1, 21764 asm: s390x.AMOVWBR, 21765 reg: regInfo{ 21766 inputs: []inputInfo{ 21767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21768 }, 21769 outputs: []outputInfo{ 21770 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21771 }, 21772 }, 21773 }, 21774 { 21775 name: "MOVDBR", 21776 argLen: 1, 21777 asm: s390x.AMOVDBR, 21778 reg: regInfo{ 21779 inputs: []inputInfo{ 21780 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21781 }, 21782 outputs: []outputInfo{ 21783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21784 }, 21785 }, 21786 }, 21787 { 21788 name: "MOVHBRload", 21789 auxType: auxSymOff, 21790 argLen: 2, 21791 clobberFlags: true, 21792 faultOnNilArg0: true, 21793 symEffect: SymRead, 21794 asm: s390x.AMOVHBR, 21795 reg: regInfo{ 21796 inputs: []inputInfo{ 21797 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21798 }, 21799 outputs: []outputInfo{ 21800 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21801 }, 21802 }, 21803 }, 21804 { 21805 name: "MOVWBRload", 21806 auxType: auxSymOff, 21807 argLen: 2, 21808 clobberFlags: true, 21809 faultOnNilArg0: true, 21810 symEffect: SymRead, 21811 asm: s390x.AMOVWBR, 21812 reg: regInfo{ 21813 inputs: []inputInfo{ 21814 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21815 }, 21816 outputs: []outputInfo{ 21817 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21818 }, 21819 }, 21820 }, 21821 { 21822 name: "MOVDBRload", 21823 auxType: auxSymOff, 21824 argLen: 2, 21825 clobberFlags: true, 21826 faultOnNilArg0: true, 21827 symEffect: SymRead, 21828 asm: s390x.AMOVDBR, 21829 reg: regInfo{ 21830 inputs: []inputInfo{ 21831 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21832 }, 21833 outputs: []outputInfo{ 21834 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21835 }, 21836 }, 21837 }, 21838 { 21839 name: "MOVBstore", 21840 auxType: auxSymOff, 21841 argLen: 3, 21842 clobberFlags: true, 21843 faultOnNilArg0: true, 21844 symEffect: SymWrite, 21845 asm: s390x.AMOVB, 21846 reg: regInfo{ 21847 inputs: []inputInfo{ 21848 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21849 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21850 }, 21851 }, 21852 }, 21853 { 21854 name: "MOVHstore", 21855 auxType: auxSymOff, 21856 argLen: 3, 21857 clobberFlags: true, 21858 faultOnNilArg0: true, 21859 symEffect: SymWrite, 21860 asm: s390x.AMOVH, 21861 reg: regInfo{ 21862 inputs: []inputInfo{ 21863 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21864 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21865 }, 21866 }, 21867 }, 21868 { 21869 name: "MOVWstore", 21870 auxType: auxSymOff, 21871 argLen: 3, 21872 clobberFlags: true, 21873 faultOnNilArg0: true, 21874 symEffect: SymWrite, 21875 asm: s390x.AMOVW, 21876 reg: regInfo{ 21877 inputs: []inputInfo{ 21878 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21879 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21880 }, 21881 }, 21882 }, 21883 { 21884 name: "MOVDstore", 21885 auxType: auxSymOff, 21886 argLen: 3, 21887 clobberFlags: true, 21888 faultOnNilArg0: true, 21889 symEffect: SymWrite, 21890 asm: s390x.AMOVD, 21891 reg: regInfo{ 21892 inputs: []inputInfo{ 21893 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21894 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21895 }, 21896 }, 21897 }, 21898 { 21899 name: "MOVHBRstore", 21900 auxType: auxSymOff, 21901 argLen: 3, 21902 clobberFlags: true, 21903 faultOnNilArg0: true, 21904 symEffect: SymWrite, 21905 asm: s390x.AMOVHBR, 21906 reg: regInfo{ 21907 inputs: []inputInfo{ 21908 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21909 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21910 }, 21911 }, 21912 }, 21913 { 21914 name: "MOVWBRstore", 21915 auxType: auxSymOff, 21916 argLen: 3, 21917 clobberFlags: true, 21918 faultOnNilArg0: true, 21919 symEffect: SymWrite, 21920 asm: s390x.AMOVWBR, 21921 reg: regInfo{ 21922 inputs: []inputInfo{ 21923 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21924 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21925 }, 21926 }, 21927 }, 21928 { 21929 name: "MOVDBRstore", 21930 auxType: auxSymOff, 21931 argLen: 3, 21932 clobberFlags: true, 21933 faultOnNilArg0: true, 21934 symEffect: SymWrite, 21935 asm: s390x.AMOVDBR, 21936 reg: regInfo{ 21937 inputs: []inputInfo{ 21938 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21939 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21940 }, 21941 }, 21942 }, 21943 { 21944 name: "MVC", 21945 auxType: auxSymValAndOff, 21946 argLen: 3, 21947 clobberFlags: true, 21948 faultOnNilArg0: true, 21949 faultOnNilArg1: true, 21950 symEffect: SymNone, 21951 asm: s390x.AMVC, 21952 reg: regInfo{ 21953 inputs: []inputInfo{ 21954 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21955 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21956 }, 21957 }, 21958 }, 21959 { 21960 name: "MOVBZloadidx", 21961 auxType: auxSymOff, 21962 argLen: 3, 21963 commutative: true, 21964 clobberFlags: true, 21965 symEffect: SymRead, 21966 asm: s390x.AMOVBZ, 21967 reg: regInfo{ 21968 inputs: []inputInfo{ 21969 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21970 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21971 }, 21972 outputs: []outputInfo{ 21973 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21974 }, 21975 }, 21976 }, 21977 { 21978 name: "MOVBloadidx", 21979 auxType: auxSymOff, 21980 argLen: 3, 21981 commutative: true, 21982 clobberFlags: true, 21983 symEffect: SymRead, 21984 asm: s390x.AMOVB, 21985 reg: regInfo{ 21986 inputs: []inputInfo{ 21987 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21988 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21989 }, 21990 outputs: []outputInfo{ 21991 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21992 }, 21993 }, 21994 }, 21995 { 21996 name: "MOVHZloadidx", 21997 auxType: auxSymOff, 21998 argLen: 3, 21999 commutative: true, 22000 clobberFlags: true, 22001 symEffect: SymRead, 22002 asm: s390x.AMOVHZ, 22003 reg: regInfo{ 22004 inputs: []inputInfo{ 22005 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22006 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22007 }, 22008 outputs: []outputInfo{ 22009 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22010 }, 22011 }, 22012 }, 22013 { 22014 name: "MOVHloadidx", 22015 auxType: auxSymOff, 22016 argLen: 3, 22017 commutative: true, 22018 clobberFlags: true, 22019 symEffect: SymRead, 22020 asm: s390x.AMOVH, 22021 reg: regInfo{ 22022 inputs: []inputInfo{ 22023 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22024 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22025 }, 22026 outputs: []outputInfo{ 22027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22028 }, 22029 }, 22030 }, 22031 { 22032 name: "MOVWZloadidx", 22033 auxType: auxSymOff, 22034 argLen: 3, 22035 commutative: true, 22036 clobberFlags: true, 22037 symEffect: SymRead, 22038 asm: s390x.AMOVWZ, 22039 reg: regInfo{ 22040 inputs: []inputInfo{ 22041 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22042 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22043 }, 22044 outputs: []outputInfo{ 22045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22046 }, 22047 }, 22048 }, 22049 { 22050 name: "MOVWloadidx", 22051 auxType: auxSymOff, 22052 argLen: 3, 22053 commutative: true, 22054 clobberFlags: true, 22055 symEffect: SymRead, 22056 asm: s390x.AMOVW, 22057 reg: regInfo{ 22058 inputs: []inputInfo{ 22059 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22060 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22061 }, 22062 outputs: []outputInfo{ 22063 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22064 }, 22065 }, 22066 }, 22067 { 22068 name: "MOVDloadidx", 22069 auxType: auxSymOff, 22070 argLen: 3, 22071 commutative: true, 22072 clobberFlags: true, 22073 symEffect: SymRead, 22074 asm: s390x.AMOVD, 22075 reg: regInfo{ 22076 inputs: []inputInfo{ 22077 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22078 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22079 }, 22080 outputs: []outputInfo{ 22081 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22082 }, 22083 }, 22084 }, 22085 { 22086 name: "MOVHBRloadidx", 22087 auxType: auxSymOff, 22088 argLen: 3, 22089 commutative: true, 22090 clobberFlags: true, 22091 symEffect: SymRead, 22092 asm: s390x.AMOVHBR, 22093 reg: regInfo{ 22094 inputs: []inputInfo{ 22095 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22096 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22097 }, 22098 outputs: []outputInfo{ 22099 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22100 }, 22101 }, 22102 }, 22103 { 22104 name: "MOVWBRloadidx", 22105 auxType: auxSymOff, 22106 argLen: 3, 22107 commutative: true, 22108 clobberFlags: true, 22109 symEffect: SymRead, 22110 asm: s390x.AMOVWBR, 22111 reg: regInfo{ 22112 inputs: []inputInfo{ 22113 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22114 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22115 }, 22116 outputs: []outputInfo{ 22117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22118 }, 22119 }, 22120 }, 22121 { 22122 name: "MOVDBRloadidx", 22123 auxType: auxSymOff, 22124 argLen: 3, 22125 commutative: true, 22126 clobberFlags: true, 22127 symEffect: SymRead, 22128 asm: s390x.AMOVDBR, 22129 reg: regInfo{ 22130 inputs: []inputInfo{ 22131 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22132 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22133 }, 22134 outputs: []outputInfo{ 22135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22136 }, 22137 }, 22138 }, 22139 { 22140 name: "MOVBstoreidx", 22141 auxType: auxSymOff, 22142 argLen: 4, 22143 commutative: true, 22144 clobberFlags: true, 22145 symEffect: SymWrite, 22146 asm: s390x.AMOVB, 22147 reg: regInfo{ 22148 inputs: []inputInfo{ 22149 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22150 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22151 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22152 }, 22153 }, 22154 }, 22155 { 22156 name: "MOVHstoreidx", 22157 auxType: auxSymOff, 22158 argLen: 4, 22159 commutative: true, 22160 clobberFlags: true, 22161 symEffect: SymWrite, 22162 asm: s390x.AMOVH, 22163 reg: regInfo{ 22164 inputs: []inputInfo{ 22165 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22166 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22167 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22168 }, 22169 }, 22170 }, 22171 { 22172 name: "MOVWstoreidx", 22173 auxType: auxSymOff, 22174 argLen: 4, 22175 commutative: true, 22176 clobberFlags: true, 22177 symEffect: SymWrite, 22178 asm: s390x.AMOVW, 22179 reg: regInfo{ 22180 inputs: []inputInfo{ 22181 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22182 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22183 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22184 }, 22185 }, 22186 }, 22187 { 22188 name: "MOVDstoreidx", 22189 auxType: auxSymOff, 22190 argLen: 4, 22191 commutative: true, 22192 clobberFlags: true, 22193 symEffect: SymWrite, 22194 asm: s390x.AMOVD, 22195 reg: regInfo{ 22196 inputs: []inputInfo{ 22197 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22198 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22199 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22200 }, 22201 }, 22202 }, 22203 { 22204 name: "MOVHBRstoreidx", 22205 auxType: auxSymOff, 22206 argLen: 4, 22207 commutative: true, 22208 clobberFlags: true, 22209 symEffect: SymWrite, 22210 asm: s390x.AMOVHBR, 22211 reg: regInfo{ 22212 inputs: []inputInfo{ 22213 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22214 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22215 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22216 }, 22217 }, 22218 }, 22219 { 22220 name: "MOVWBRstoreidx", 22221 auxType: auxSymOff, 22222 argLen: 4, 22223 commutative: true, 22224 clobberFlags: true, 22225 symEffect: SymWrite, 22226 asm: s390x.AMOVWBR, 22227 reg: regInfo{ 22228 inputs: []inputInfo{ 22229 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22230 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22231 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22232 }, 22233 }, 22234 }, 22235 { 22236 name: "MOVDBRstoreidx", 22237 auxType: auxSymOff, 22238 argLen: 4, 22239 commutative: true, 22240 clobberFlags: true, 22241 symEffect: SymWrite, 22242 asm: s390x.AMOVDBR, 22243 reg: regInfo{ 22244 inputs: []inputInfo{ 22245 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22246 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22247 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22248 }, 22249 }, 22250 }, 22251 { 22252 name: "MOVBstoreconst", 22253 auxType: auxSymValAndOff, 22254 argLen: 2, 22255 faultOnNilArg0: true, 22256 symEffect: SymWrite, 22257 asm: s390x.AMOVB, 22258 reg: regInfo{ 22259 inputs: []inputInfo{ 22260 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22261 }, 22262 }, 22263 }, 22264 { 22265 name: "MOVHstoreconst", 22266 auxType: auxSymValAndOff, 22267 argLen: 2, 22268 faultOnNilArg0: true, 22269 symEffect: SymWrite, 22270 asm: s390x.AMOVH, 22271 reg: regInfo{ 22272 inputs: []inputInfo{ 22273 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22274 }, 22275 }, 22276 }, 22277 { 22278 name: "MOVWstoreconst", 22279 auxType: auxSymValAndOff, 22280 argLen: 2, 22281 faultOnNilArg0: true, 22282 symEffect: SymWrite, 22283 asm: s390x.AMOVW, 22284 reg: regInfo{ 22285 inputs: []inputInfo{ 22286 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22287 }, 22288 }, 22289 }, 22290 { 22291 name: "MOVDstoreconst", 22292 auxType: auxSymValAndOff, 22293 argLen: 2, 22294 faultOnNilArg0: true, 22295 symEffect: SymWrite, 22296 asm: s390x.AMOVD, 22297 reg: regInfo{ 22298 inputs: []inputInfo{ 22299 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22300 }, 22301 }, 22302 }, 22303 { 22304 name: "CLEAR", 22305 auxType: auxSymValAndOff, 22306 argLen: 2, 22307 clobberFlags: true, 22308 faultOnNilArg0: true, 22309 symEffect: SymWrite, 22310 asm: s390x.ACLEAR, 22311 reg: regInfo{ 22312 inputs: []inputInfo{ 22313 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22314 }, 22315 }, 22316 }, 22317 { 22318 name: "CALLstatic", 22319 auxType: auxSymOff, 22320 argLen: 1, 22321 clobberFlags: true, 22322 call: true, 22323 symEffect: SymNone, 22324 reg: regInfo{ 22325 clobbers: 4294931455, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22326 }, 22327 }, 22328 { 22329 name: "CALLclosure", 22330 auxType: auxInt64, 22331 argLen: 3, 22332 clobberFlags: true, 22333 call: true, 22334 reg: regInfo{ 22335 inputs: []inputInfo{ 22336 {1, 4096}, // R12 22337 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22338 }, 22339 clobbers: 4294931455, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22340 }, 22341 }, 22342 { 22343 name: "CALLinter", 22344 auxType: auxInt64, 22345 argLen: 2, 22346 clobberFlags: true, 22347 call: true, 22348 reg: regInfo{ 22349 inputs: []inputInfo{ 22350 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22351 }, 22352 clobbers: 4294931455, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22353 }, 22354 }, 22355 { 22356 name: "InvertFlags", 22357 argLen: 1, 22358 reg: regInfo{}, 22359 }, 22360 { 22361 name: "LoweredGetG", 22362 argLen: 1, 22363 reg: regInfo{ 22364 outputs: []outputInfo{ 22365 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22366 }, 22367 }, 22368 }, 22369 { 22370 name: "LoweredGetClosurePtr", 22371 argLen: 0, 22372 reg: regInfo{ 22373 outputs: []outputInfo{ 22374 {0, 4096}, // R12 22375 }, 22376 }, 22377 }, 22378 { 22379 name: "LoweredGetCallerSP", 22380 argLen: 0, 22381 rematerializeable: true, 22382 reg: regInfo{ 22383 outputs: []outputInfo{ 22384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22385 }, 22386 }, 22387 }, 22388 { 22389 name: "LoweredNilCheck", 22390 argLen: 2, 22391 clobberFlags: true, 22392 nilCheck: true, 22393 faultOnNilArg0: true, 22394 reg: regInfo{ 22395 inputs: []inputInfo{ 22396 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22397 }, 22398 }, 22399 }, 22400 { 22401 name: "LoweredRound32F", 22402 argLen: 1, 22403 resultInArg0: true, 22404 reg: regInfo{ 22405 inputs: []inputInfo{ 22406 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22407 }, 22408 outputs: []outputInfo{ 22409 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22410 }, 22411 }, 22412 }, 22413 { 22414 name: "LoweredRound64F", 22415 argLen: 1, 22416 resultInArg0: true, 22417 reg: regInfo{ 22418 inputs: []inputInfo{ 22419 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22420 }, 22421 outputs: []outputInfo{ 22422 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22423 }, 22424 }, 22425 }, 22426 { 22427 name: "LoweredWB", 22428 auxType: auxSym, 22429 argLen: 3, 22430 clobberFlags: true, 22431 symEffect: SymNone, 22432 reg: regInfo{ 22433 inputs: []inputInfo{ 22434 {0, 4}, // R2 22435 {1, 8}, // R3 22436 }, 22437 clobbers: 4294918144, // R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 22438 }, 22439 }, 22440 { 22441 name: "MOVDconvert", 22442 argLen: 2, 22443 asm: s390x.AMOVD, 22444 reg: regInfo{ 22445 inputs: []inputInfo{ 22446 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22447 }, 22448 outputs: []outputInfo{ 22449 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22450 }, 22451 }, 22452 }, 22453 { 22454 name: "FlagEQ", 22455 argLen: 0, 22456 reg: regInfo{}, 22457 }, 22458 { 22459 name: "FlagLT", 22460 argLen: 0, 22461 reg: regInfo{}, 22462 }, 22463 { 22464 name: "FlagGT", 22465 argLen: 0, 22466 reg: regInfo{}, 22467 }, 22468 { 22469 name: "MOVWZatomicload", 22470 auxType: auxSymOff, 22471 argLen: 2, 22472 faultOnNilArg0: true, 22473 symEffect: SymRead, 22474 asm: s390x.AMOVWZ, 22475 reg: regInfo{ 22476 inputs: []inputInfo{ 22477 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22478 }, 22479 outputs: []outputInfo{ 22480 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22481 }, 22482 }, 22483 }, 22484 { 22485 name: "MOVDatomicload", 22486 auxType: auxSymOff, 22487 argLen: 2, 22488 faultOnNilArg0: true, 22489 symEffect: SymRead, 22490 asm: s390x.AMOVD, 22491 reg: regInfo{ 22492 inputs: []inputInfo{ 22493 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22494 }, 22495 outputs: []outputInfo{ 22496 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22497 }, 22498 }, 22499 }, 22500 { 22501 name: "MOVWatomicstore", 22502 auxType: auxSymOff, 22503 argLen: 3, 22504 clobberFlags: true, 22505 faultOnNilArg0: true, 22506 hasSideEffects: true, 22507 symEffect: SymWrite, 22508 asm: s390x.AMOVW, 22509 reg: regInfo{ 22510 inputs: []inputInfo{ 22511 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22512 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22513 }, 22514 }, 22515 }, 22516 { 22517 name: "MOVDatomicstore", 22518 auxType: auxSymOff, 22519 argLen: 3, 22520 clobberFlags: true, 22521 faultOnNilArg0: true, 22522 hasSideEffects: true, 22523 symEffect: SymWrite, 22524 asm: s390x.AMOVD, 22525 reg: regInfo{ 22526 inputs: []inputInfo{ 22527 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22528 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22529 }, 22530 }, 22531 }, 22532 { 22533 name: "LAA", 22534 auxType: auxSymOff, 22535 argLen: 3, 22536 faultOnNilArg0: true, 22537 hasSideEffects: true, 22538 symEffect: SymRdWr, 22539 asm: s390x.ALAA, 22540 reg: regInfo{ 22541 inputs: []inputInfo{ 22542 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22543 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22544 }, 22545 outputs: []outputInfo{ 22546 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22547 }, 22548 }, 22549 }, 22550 { 22551 name: "LAAG", 22552 auxType: auxSymOff, 22553 argLen: 3, 22554 faultOnNilArg0: true, 22555 hasSideEffects: true, 22556 symEffect: SymRdWr, 22557 asm: s390x.ALAAG, 22558 reg: regInfo{ 22559 inputs: []inputInfo{ 22560 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22561 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22562 }, 22563 outputs: []outputInfo{ 22564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22565 }, 22566 }, 22567 }, 22568 { 22569 name: "AddTupleFirst32", 22570 argLen: 2, 22571 reg: regInfo{}, 22572 }, 22573 { 22574 name: "AddTupleFirst64", 22575 argLen: 2, 22576 reg: regInfo{}, 22577 }, 22578 { 22579 name: "LoweredAtomicCas32", 22580 auxType: auxSymOff, 22581 argLen: 4, 22582 clobberFlags: true, 22583 faultOnNilArg0: true, 22584 hasSideEffects: true, 22585 symEffect: SymRdWr, 22586 asm: s390x.ACS, 22587 reg: regInfo{ 22588 inputs: []inputInfo{ 22589 {1, 1}, // R0 22590 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22591 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22592 }, 22593 clobbers: 1, // R0 22594 outputs: []outputInfo{ 22595 {1, 0}, 22596 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22597 }, 22598 }, 22599 }, 22600 { 22601 name: "LoweredAtomicCas64", 22602 auxType: auxSymOff, 22603 argLen: 4, 22604 clobberFlags: true, 22605 faultOnNilArg0: true, 22606 hasSideEffects: true, 22607 symEffect: SymRdWr, 22608 asm: s390x.ACSG, 22609 reg: regInfo{ 22610 inputs: []inputInfo{ 22611 {1, 1}, // R0 22612 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22613 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22614 }, 22615 clobbers: 1, // R0 22616 outputs: []outputInfo{ 22617 {1, 0}, 22618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22619 }, 22620 }, 22621 }, 22622 { 22623 name: "LoweredAtomicExchange32", 22624 auxType: auxSymOff, 22625 argLen: 3, 22626 clobberFlags: true, 22627 faultOnNilArg0: true, 22628 hasSideEffects: true, 22629 symEffect: SymRdWr, 22630 asm: s390x.ACS, 22631 reg: regInfo{ 22632 inputs: []inputInfo{ 22633 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22634 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22635 }, 22636 outputs: []outputInfo{ 22637 {1, 0}, 22638 {0, 1}, // R0 22639 }, 22640 }, 22641 }, 22642 { 22643 name: "LoweredAtomicExchange64", 22644 auxType: auxSymOff, 22645 argLen: 3, 22646 clobberFlags: true, 22647 faultOnNilArg0: true, 22648 hasSideEffects: true, 22649 symEffect: SymRdWr, 22650 asm: s390x.ACSG, 22651 reg: regInfo{ 22652 inputs: []inputInfo{ 22653 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22654 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22655 }, 22656 outputs: []outputInfo{ 22657 {1, 0}, 22658 {0, 1}, // R0 22659 }, 22660 }, 22661 }, 22662 { 22663 name: "FLOGR", 22664 argLen: 1, 22665 clobberFlags: true, 22666 asm: s390x.AFLOGR, 22667 reg: regInfo{ 22668 inputs: []inputInfo{ 22669 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22670 }, 22671 clobbers: 2, // R1 22672 outputs: []outputInfo{ 22673 {0, 1}, // R0 22674 }, 22675 }, 22676 }, 22677 { 22678 name: "STMG2", 22679 auxType: auxSymOff, 22680 argLen: 4, 22681 faultOnNilArg0: true, 22682 symEffect: SymWrite, 22683 asm: s390x.ASTMG, 22684 reg: regInfo{ 22685 inputs: []inputInfo{ 22686 {1, 2}, // R1 22687 {2, 4}, // R2 22688 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22689 }, 22690 }, 22691 }, 22692 { 22693 name: "STMG3", 22694 auxType: auxSymOff, 22695 argLen: 5, 22696 faultOnNilArg0: true, 22697 symEffect: SymWrite, 22698 asm: s390x.ASTMG, 22699 reg: regInfo{ 22700 inputs: []inputInfo{ 22701 {1, 2}, // R1 22702 {2, 4}, // R2 22703 {3, 8}, // R3 22704 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22705 }, 22706 }, 22707 }, 22708 { 22709 name: "STMG4", 22710 auxType: auxSymOff, 22711 argLen: 6, 22712 faultOnNilArg0: true, 22713 symEffect: SymWrite, 22714 asm: s390x.ASTMG, 22715 reg: regInfo{ 22716 inputs: []inputInfo{ 22717 {1, 2}, // R1 22718 {2, 4}, // R2 22719 {3, 8}, // R3 22720 {4, 16}, // R4 22721 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22722 }, 22723 }, 22724 }, 22725 { 22726 name: "STM2", 22727 auxType: auxSymOff, 22728 argLen: 4, 22729 faultOnNilArg0: true, 22730 symEffect: SymWrite, 22731 asm: s390x.ASTMY, 22732 reg: regInfo{ 22733 inputs: []inputInfo{ 22734 {1, 2}, // R1 22735 {2, 4}, // R2 22736 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22737 }, 22738 }, 22739 }, 22740 { 22741 name: "STM3", 22742 auxType: auxSymOff, 22743 argLen: 5, 22744 faultOnNilArg0: true, 22745 symEffect: SymWrite, 22746 asm: s390x.ASTMY, 22747 reg: regInfo{ 22748 inputs: []inputInfo{ 22749 {1, 2}, // R1 22750 {2, 4}, // R2 22751 {3, 8}, // R3 22752 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22753 }, 22754 }, 22755 }, 22756 { 22757 name: "STM4", 22758 auxType: auxSymOff, 22759 argLen: 6, 22760 faultOnNilArg0: true, 22761 symEffect: SymWrite, 22762 asm: s390x.ASTMY, 22763 reg: regInfo{ 22764 inputs: []inputInfo{ 22765 {1, 2}, // R1 22766 {2, 4}, // R2 22767 {3, 8}, // R3 22768 {4, 16}, // R4 22769 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22770 }, 22771 }, 22772 }, 22773 { 22774 name: "LoweredMove", 22775 auxType: auxInt64, 22776 argLen: 4, 22777 clobberFlags: true, 22778 faultOnNilArg0: true, 22779 faultOnNilArg1: true, 22780 reg: regInfo{ 22781 inputs: []inputInfo{ 22782 {0, 2}, // R1 22783 {1, 4}, // R2 22784 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22785 }, 22786 clobbers: 6, // R1 R2 22787 }, 22788 }, 22789 { 22790 name: "LoweredZero", 22791 auxType: auxInt64, 22792 argLen: 3, 22793 clobberFlags: true, 22794 faultOnNilArg0: true, 22795 reg: regInfo{ 22796 inputs: []inputInfo{ 22797 {0, 2}, // R1 22798 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22799 }, 22800 clobbers: 2, // R1 22801 }, 22802 }, 22803 22804 { 22805 name: "Add8", 22806 argLen: 2, 22807 commutative: true, 22808 generic: true, 22809 }, 22810 { 22811 name: "Add16", 22812 argLen: 2, 22813 commutative: true, 22814 generic: true, 22815 }, 22816 { 22817 name: "Add32", 22818 argLen: 2, 22819 commutative: true, 22820 generic: true, 22821 }, 22822 { 22823 name: "Add64", 22824 argLen: 2, 22825 commutative: true, 22826 generic: true, 22827 }, 22828 { 22829 name: "AddPtr", 22830 argLen: 2, 22831 generic: true, 22832 }, 22833 { 22834 name: "Add32F", 22835 argLen: 2, 22836 commutative: true, 22837 generic: true, 22838 }, 22839 { 22840 name: "Add64F", 22841 argLen: 2, 22842 commutative: true, 22843 generic: true, 22844 }, 22845 { 22846 name: "Sub8", 22847 argLen: 2, 22848 generic: true, 22849 }, 22850 { 22851 name: "Sub16", 22852 argLen: 2, 22853 generic: true, 22854 }, 22855 { 22856 name: "Sub32", 22857 argLen: 2, 22858 generic: true, 22859 }, 22860 { 22861 name: "Sub64", 22862 argLen: 2, 22863 generic: true, 22864 }, 22865 { 22866 name: "SubPtr", 22867 argLen: 2, 22868 generic: true, 22869 }, 22870 { 22871 name: "Sub32F", 22872 argLen: 2, 22873 generic: true, 22874 }, 22875 { 22876 name: "Sub64F", 22877 argLen: 2, 22878 generic: true, 22879 }, 22880 { 22881 name: "Mul8", 22882 argLen: 2, 22883 commutative: true, 22884 generic: true, 22885 }, 22886 { 22887 name: "Mul16", 22888 argLen: 2, 22889 commutative: true, 22890 generic: true, 22891 }, 22892 { 22893 name: "Mul32", 22894 argLen: 2, 22895 commutative: true, 22896 generic: true, 22897 }, 22898 { 22899 name: "Mul64", 22900 argLen: 2, 22901 commutative: true, 22902 generic: true, 22903 }, 22904 { 22905 name: "Mul32F", 22906 argLen: 2, 22907 commutative: true, 22908 generic: true, 22909 }, 22910 { 22911 name: "Mul64F", 22912 argLen: 2, 22913 commutative: true, 22914 generic: true, 22915 }, 22916 { 22917 name: "Div32F", 22918 argLen: 2, 22919 generic: true, 22920 }, 22921 { 22922 name: "Div64F", 22923 argLen: 2, 22924 generic: true, 22925 }, 22926 { 22927 name: "Hmul32", 22928 argLen: 2, 22929 commutative: true, 22930 generic: true, 22931 }, 22932 { 22933 name: "Hmul32u", 22934 argLen: 2, 22935 commutative: true, 22936 generic: true, 22937 }, 22938 { 22939 name: "Hmul64", 22940 argLen: 2, 22941 commutative: true, 22942 generic: true, 22943 }, 22944 { 22945 name: "Hmul64u", 22946 argLen: 2, 22947 commutative: true, 22948 generic: true, 22949 }, 22950 { 22951 name: "Mul32uhilo", 22952 argLen: 2, 22953 commutative: true, 22954 generic: true, 22955 }, 22956 { 22957 name: "Mul64uhilo", 22958 argLen: 2, 22959 commutative: true, 22960 generic: true, 22961 }, 22962 { 22963 name: "Avg32u", 22964 argLen: 2, 22965 generic: true, 22966 }, 22967 { 22968 name: "Avg64u", 22969 argLen: 2, 22970 generic: true, 22971 }, 22972 { 22973 name: "Div8", 22974 argLen: 2, 22975 generic: true, 22976 }, 22977 { 22978 name: "Div8u", 22979 argLen: 2, 22980 generic: true, 22981 }, 22982 { 22983 name: "Div16", 22984 argLen: 2, 22985 generic: true, 22986 }, 22987 { 22988 name: "Div16u", 22989 argLen: 2, 22990 generic: true, 22991 }, 22992 { 22993 name: "Div32", 22994 argLen: 2, 22995 generic: true, 22996 }, 22997 { 22998 name: "Div32u", 22999 argLen: 2, 23000 generic: true, 23001 }, 23002 { 23003 name: "Div64", 23004 argLen: 2, 23005 generic: true, 23006 }, 23007 { 23008 name: "Div64u", 23009 argLen: 2, 23010 generic: true, 23011 }, 23012 { 23013 name: "Div128u", 23014 argLen: 3, 23015 generic: true, 23016 }, 23017 { 23018 name: "Mod8", 23019 argLen: 2, 23020 generic: true, 23021 }, 23022 { 23023 name: "Mod8u", 23024 argLen: 2, 23025 generic: true, 23026 }, 23027 { 23028 name: "Mod16", 23029 argLen: 2, 23030 generic: true, 23031 }, 23032 { 23033 name: "Mod16u", 23034 argLen: 2, 23035 generic: true, 23036 }, 23037 { 23038 name: "Mod32", 23039 argLen: 2, 23040 generic: true, 23041 }, 23042 { 23043 name: "Mod32u", 23044 argLen: 2, 23045 generic: true, 23046 }, 23047 { 23048 name: "Mod64", 23049 argLen: 2, 23050 generic: true, 23051 }, 23052 { 23053 name: "Mod64u", 23054 argLen: 2, 23055 generic: true, 23056 }, 23057 { 23058 name: "And8", 23059 argLen: 2, 23060 commutative: true, 23061 generic: true, 23062 }, 23063 { 23064 name: "And16", 23065 argLen: 2, 23066 commutative: true, 23067 generic: true, 23068 }, 23069 { 23070 name: "And32", 23071 argLen: 2, 23072 commutative: true, 23073 generic: true, 23074 }, 23075 { 23076 name: "And64", 23077 argLen: 2, 23078 commutative: true, 23079 generic: true, 23080 }, 23081 { 23082 name: "Or8", 23083 argLen: 2, 23084 commutative: true, 23085 generic: true, 23086 }, 23087 { 23088 name: "Or16", 23089 argLen: 2, 23090 commutative: true, 23091 generic: true, 23092 }, 23093 { 23094 name: "Or32", 23095 argLen: 2, 23096 commutative: true, 23097 generic: true, 23098 }, 23099 { 23100 name: "Or64", 23101 argLen: 2, 23102 commutative: true, 23103 generic: true, 23104 }, 23105 { 23106 name: "Xor8", 23107 argLen: 2, 23108 commutative: true, 23109 generic: true, 23110 }, 23111 { 23112 name: "Xor16", 23113 argLen: 2, 23114 commutative: true, 23115 generic: true, 23116 }, 23117 { 23118 name: "Xor32", 23119 argLen: 2, 23120 commutative: true, 23121 generic: true, 23122 }, 23123 { 23124 name: "Xor64", 23125 argLen: 2, 23126 commutative: true, 23127 generic: true, 23128 }, 23129 { 23130 name: "Lsh8x8", 23131 argLen: 2, 23132 generic: true, 23133 }, 23134 { 23135 name: "Lsh8x16", 23136 argLen: 2, 23137 generic: true, 23138 }, 23139 { 23140 name: "Lsh8x32", 23141 argLen: 2, 23142 generic: true, 23143 }, 23144 { 23145 name: "Lsh8x64", 23146 argLen: 2, 23147 generic: true, 23148 }, 23149 { 23150 name: "Lsh16x8", 23151 argLen: 2, 23152 generic: true, 23153 }, 23154 { 23155 name: "Lsh16x16", 23156 argLen: 2, 23157 generic: true, 23158 }, 23159 { 23160 name: "Lsh16x32", 23161 argLen: 2, 23162 generic: true, 23163 }, 23164 { 23165 name: "Lsh16x64", 23166 argLen: 2, 23167 generic: true, 23168 }, 23169 { 23170 name: "Lsh32x8", 23171 argLen: 2, 23172 generic: true, 23173 }, 23174 { 23175 name: "Lsh32x16", 23176 argLen: 2, 23177 generic: true, 23178 }, 23179 { 23180 name: "Lsh32x32", 23181 argLen: 2, 23182 generic: true, 23183 }, 23184 { 23185 name: "Lsh32x64", 23186 argLen: 2, 23187 generic: true, 23188 }, 23189 { 23190 name: "Lsh64x8", 23191 argLen: 2, 23192 generic: true, 23193 }, 23194 { 23195 name: "Lsh64x16", 23196 argLen: 2, 23197 generic: true, 23198 }, 23199 { 23200 name: "Lsh64x32", 23201 argLen: 2, 23202 generic: true, 23203 }, 23204 { 23205 name: "Lsh64x64", 23206 argLen: 2, 23207 generic: true, 23208 }, 23209 { 23210 name: "Rsh8x8", 23211 argLen: 2, 23212 generic: true, 23213 }, 23214 { 23215 name: "Rsh8x16", 23216 argLen: 2, 23217 generic: true, 23218 }, 23219 { 23220 name: "Rsh8x32", 23221 argLen: 2, 23222 generic: true, 23223 }, 23224 { 23225 name: "Rsh8x64", 23226 argLen: 2, 23227 generic: true, 23228 }, 23229 { 23230 name: "Rsh16x8", 23231 argLen: 2, 23232 generic: true, 23233 }, 23234 { 23235 name: "Rsh16x16", 23236 argLen: 2, 23237 generic: true, 23238 }, 23239 { 23240 name: "Rsh16x32", 23241 argLen: 2, 23242 generic: true, 23243 }, 23244 { 23245 name: "Rsh16x64", 23246 argLen: 2, 23247 generic: true, 23248 }, 23249 { 23250 name: "Rsh32x8", 23251 argLen: 2, 23252 generic: true, 23253 }, 23254 { 23255 name: "Rsh32x16", 23256 argLen: 2, 23257 generic: true, 23258 }, 23259 { 23260 name: "Rsh32x32", 23261 argLen: 2, 23262 generic: true, 23263 }, 23264 { 23265 name: "Rsh32x64", 23266 argLen: 2, 23267 generic: true, 23268 }, 23269 { 23270 name: "Rsh64x8", 23271 argLen: 2, 23272 generic: true, 23273 }, 23274 { 23275 name: "Rsh64x16", 23276 argLen: 2, 23277 generic: true, 23278 }, 23279 { 23280 name: "Rsh64x32", 23281 argLen: 2, 23282 generic: true, 23283 }, 23284 { 23285 name: "Rsh64x64", 23286 argLen: 2, 23287 generic: true, 23288 }, 23289 { 23290 name: "Rsh8Ux8", 23291 argLen: 2, 23292 generic: true, 23293 }, 23294 { 23295 name: "Rsh8Ux16", 23296 argLen: 2, 23297 generic: true, 23298 }, 23299 { 23300 name: "Rsh8Ux32", 23301 argLen: 2, 23302 generic: true, 23303 }, 23304 { 23305 name: "Rsh8Ux64", 23306 argLen: 2, 23307 generic: true, 23308 }, 23309 { 23310 name: "Rsh16Ux8", 23311 argLen: 2, 23312 generic: true, 23313 }, 23314 { 23315 name: "Rsh16Ux16", 23316 argLen: 2, 23317 generic: true, 23318 }, 23319 { 23320 name: "Rsh16Ux32", 23321 argLen: 2, 23322 generic: true, 23323 }, 23324 { 23325 name: "Rsh16Ux64", 23326 argLen: 2, 23327 generic: true, 23328 }, 23329 { 23330 name: "Rsh32Ux8", 23331 argLen: 2, 23332 generic: true, 23333 }, 23334 { 23335 name: "Rsh32Ux16", 23336 argLen: 2, 23337 generic: true, 23338 }, 23339 { 23340 name: "Rsh32Ux32", 23341 argLen: 2, 23342 generic: true, 23343 }, 23344 { 23345 name: "Rsh32Ux64", 23346 argLen: 2, 23347 generic: true, 23348 }, 23349 { 23350 name: "Rsh64Ux8", 23351 argLen: 2, 23352 generic: true, 23353 }, 23354 { 23355 name: "Rsh64Ux16", 23356 argLen: 2, 23357 generic: true, 23358 }, 23359 { 23360 name: "Rsh64Ux32", 23361 argLen: 2, 23362 generic: true, 23363 }, 23364 { 23365 name: "Rsh64Ux64", 23366 argLen: 2, 23367 generic: true, 23368 }, 23369 { 23370 name: "Eq8", 23371 argLen: 2, 23372 commutative: true, 23373 generic: true, 23374 }, 23375 { 23376 name: "Eq16", 23377 argLen: 2, 23378 commutative: true, 23379 generic: true, 23380 }, 23381 { 23382 name: "Eq32", 23383 argLen: 2, 23384 commutative: true, 23385 generic: true, 23386 }, 23387 { 23388 name: "Eq64", 23389 argLen: 2, 23390 commutative: true, 23391 generic: true, 23392 }, 23393 { 23394 name: "EqPtr", 23395 argLen: 2, 23396 commutative: true, 23397 generic: true, 23398 }, 23399 { 23400 name: "EqInter", 23401 argLen: 2, 23402 generic: true, 23403 }, 23404 { 23405 name: "EqSlice", 23406 argLen: 2, 23407 generic: true, 23408 }, 23409 { 23410 name: "Eq32F", 23411 argLen: 2, 23412 commutative: true, 23413 generic: true, 23414 }, 23415 { 23416 name: "Eq64F", 23417 argLen: 2, 23418 commutative: true, 23419 generic: true, 23420 }, 23421 { 23422 name: "Neq8", 23423 argLen: 2, 23424 commutative: true, 23425 generic: true, 23426 }, 23427 { 23428 name: "Neq16", 23429 argLen: 2, 23430 commutative: true, 23431 generic: true, 23432 }, 23433 { 23434 name: "Neq32", 23435 argLen: 2, 23436 commutative: true, 23437 generic: true, 23438 }, 23439 { 23440 name: "Neq64", 23441 argLen: 2, 23442 commutative: true, 23443 generic: true, 23444 }, 23445 { 23446 name: "NeqPtr", 23447 argLen: 2, 23448 commutative: true, 23449 generic: true, 23450 }, 23451 { 23452 name: "NeqInter", 23453 argLen: 2, 23454 generic: true, 23455 }, 23456 { 23457 name: "NeqSlice", 23458 argLen: 2, 23459 generic: true, 23460 }, 23461 { 23462 name: "Neq32F", 23463 argLen: 2, 23464 commutative: true, 23465 generic: true, 23466 }, 23467 { 23468 name: "Neq64F", 23469 argLen: 2, 23470 commutative: true, 23471 generic: true, 23472 }, 23473 { 23474 name: "Less8", 23475 argLen: 2, 23476 generic: true, 23477 }, 23478 { 23479 name: "Less8U", 23480 argLen: 2, 23481 generic: true, 23482 }, 23483 { 23484 name: "Less16", 23485 argLen: 2, 23486 generic: true, 23487 }, 23488 { 23489 name: "Less16U", 23490 argLen: 2, 23491 generic: true, 23492 }, 23493 { 23494 name: "Less32", 23495 argLen: 2, 23496 generic: true, 23497 }, 23498 { 23499 name: "Less32U", 23500 argLen: 2, 23501 generic: true, 23502 }, 23503 { 23504 name: "Less64", 23505 argLen: 2, 23506 generic: true, 23507 }, 23508 { 23509 name: "Less64U", 23510 argLen: 2, 23511 generic: true, 23512 }, 23513 { 23514 name: "Less32F", 23515 argLen: 2, 23516 generic: true, 23517 }, 23518 { 23519 name: "Less64F", 23520 argLen: 2, 23521 generic: true, 23522 }, 23523 { 23524 name: "Leq8", 23525 argLen: 2, 23526 generic: true, 23527 }, 23528 { 23529 name: "Leq8U", 23530 argLen: 2, 23531 generic: true, 23532 }, 23533 { 23534 name: "Leq16", 23535 argLen: 2, 23536 generic: true, 23537 }, 23538 { 23539 name: "Leq16U", 23540 argLen: 2, 23541 generic: true, 23542 }, 23543 { 23544 name: "Leq32", 23545 argLen: 2, 23546 generic: true, 23547 }, 23548 { 23549 name: "Leq32U", 23550 argLen: 2, 23551 generic: true, 23552 }, 23553 { 23554 name: "Leq64", 23555 argLen: 2, 23556 generic: true, 23557 }, 23558 { 23559 name: "Leq64U", 23560 argLen: 2, 23561 generic: true, 23562 }, 23563 { 23564 name: "Leq32F", 23565 argLen: 2, 23566 generic: true, 23567 }, 23568 { 23569 name: "Leq64F", 23570 argLen: 2, 23571 generic: true, 23572 }, 23573 { 23574 name: "Greater8", 23575 argLen: 2, 23576 generic: true, 23577 }, 23578 { 23579 name: "Greater8U", 23580 argLen: 2, 23581 generic: true, 23582 }, 23583 { 23584 name: "Greater16", 23585 argLen: 2, 23586 generic: true, 23587 }, 23588 { 23589 name: "Greater16U", 23590 argLen: 2, 23591 generic: true, 23592 }, 23593 { 23594 name: "Greater32", 23595 argLen: 2, 23596 generic: true, 23597 }, 23598 { 23599 name: "Greater32U", 23600 argLen: 2, 23601 generic: true, 23602 }, 23603 { 23604 name: "Greater64", 23605 argLen: 2, 23606 generic: true, 23607 }, 23608 { 23609 name: "Greater64U", 23610 argLen: 2, 23611 generic: true, 23612 }, 23613 { 23614 name: "Greater32F", 23615 argLen: 2, 23616 generic: true, 23617 }, 23618 { 23619 name: "Greater64F", 23620 argLen: 2, 23621 generic: true, 23622 }, 23623 { 23624 name: "Geq8", 23625 argLen: 2, 23626 generic: true, 23627 }, 23628 { 23629 name: "Geq8U", 23630 argLen: 2, 23631 generic: true, 23632 }, 23633 { 23634 name: "Geq16", 23635 argLen: 2, 23636 generic: true, 23637 }, 23638 { 23639 name: "Geq16U", 23640 argLen: 2, 23641 generic: true, 23642 }, 23643 { 23644 name: "Geq32", 23645 argLen: 2, 23646 generic: true, 23647 }, 23648 { 23649 name: "Geq32U", 23650 argLen: 2, 23651 generic: true, 23652 }, 23653 { 23654 name: "Geq64", 23655 argLen: 2, 23656 generic: true, 23657 }, 23658 { 23659 name: "Geq64U", 23660 argLen: 2, 23661 generic: true, 23662 }, 23663 { 23664 name: "Geq32F", 23665 argLen: 2, 23666 generic: true, 23667 }, 23668 { 23669 name: "Geq64F", 23670 argLen: 2, 23671 generic: true, 23672 }, 23673 { 23674 name: "CondSelect", 23675 argLen: 3, 23676 generic: true, 23677 }, 23678 { 23679 name: "AndB", 23680 argLen: 2, 23681 commutative: true, 23682 generic: true, 23683 }, 23684 { 23685 name: "OrB", 23686 argLen: 2, 23687 commutative: true, 23688 generic: true, 23689 }, 23690 { 23691 name: "EqB", 23692 argLen: 2, 23693 commutative: true, 23694 generic: true, 23695 }, 23696 { 23697 name: "NeqB", 23698 argLen: 2, 23699 commutative: true, 23700 generic: true, 23701 }, 23702 { 23703 name: "Not", 23704 argLen: 1, 23705 generic: true, 23706 }, 23707 { 23708 name: "Neg8", 23709 argLen: 1, 23710 generic: true, 23711 }, 23712 { 23713 name: "Neg16", 23714 argLen: 1, 23715 generic: true, 23716 }, 23717 { 23718 name: "Neg32", 23719 argLen: 1, 23720 generic: true, 23721 }, 23722 { 23723 name: "Neg64", 23724 argLen: 1, 23725 generic: true, 23726 }, 23727 { 23728 name: "Neg32F", 23729 argLen: 1, 23730 generic: true, 23731 }, 23732 { 23733 name: "Neg64F", 23734 argLen: 1, 23735 generic: true, 23736 }, 23737 { 23738 name: "Com8", 23739 argLen: 1, 23740 generic: true, 23741 }, 23742 { 23743 name: "Com16", 23744 argLen: 1, 23745 generic: true, 23746 }, 23747 { 23748 name: "Com32", 23749 argLen: 1, 23750 generic: true, 23751 }, 23752 { 23753 name: "Com64", 23754 argLen: 1, 23755 generic: true, 23756 }, 23757 { 23758 name: "Ctz32", 23759 argLen: 1, 23760 generic: true, 23761 }, 23762 { 23763 name: "Ctz64", 23764 argLen: 1, 23765 generic: true, 23766 }, 23767 { 23768 name: "BitLen32", 23769 argLen: 1, 23770 generic: true, 23771 }, 23772 { 23773 name: "BitLen64", 23774 argLen: 1, 23775 generic: true, 23776 }, 23777 { 23778 name: "Bswap32", 23779 argLen: 1, 23780 generic: true, 23781 }, 23782 { 23783 name: "Bswap64", 23784 argLen: 1, 23785 generic: true, 23786 }, 23787 { 23788 name: "BitRev8", 23789 argLen: 1, 23790 generic: true, 23791 }, 23792 { 23793 name: "BitRev16", 23794 argLen: 1, 23795 generic: true, 23796 }, 23797 { 23798 name: "BitRev32", 23799 argLen: 1, 23800 generic: true, 23801 }, 23802 { 23803 name: "BitRev64", 23804 argLen: 1, 23805 generic: true, 23806 }, 23807 { 23808 name: "PopCount8", 23809 argLen: 1, 23810 generic: true, 23811 }, 23812 { 23813 name: "PopCount16", 23814 argLen: 1, 23815 generic: true, 23816 }, 23817 { 23818 name: "PopCount32", 23819 argLen: 1, 23820 generic: true, 23821 }, 23822 { 23823 name: "PopCount64", 23824 argLen: 1, 23825 generic: true, 23826 }, 23827 { 23828 name: "Sqrt", 23829 argLen: 1, 23830 generic: true, 23831 }, 23832 { 23833 name: "Floor", 23834 argLen: 1, 23835 generic: true, 23836 }, 23837 { 23838 name: "Ceil", 23839 argLen: 1, 23840 generic: true, 23841 }, 23842 { 23843 name: "Trunc", 23844 argLen: 1, 23845 generic: true, 23846 }, 23847 { 23848 name: "Round", 23849 argLen: 1, 23850 generic: true, 23851 }, 23852 { 23853 name: "RoundToEven", 23854 argLen: 1, 23855 generic: true, 23856 }, 23857 { 23858 name: "Abs", 23859 argLen: 1, 23860 generic: true, 23861 }, 23862 { 23863 name: "Copysign", 23864 argLen: 2, 23865 generic: true, 23866 }, 23867 { 23868 name: "Phi", 23869 argLen: -1, 23870 generic: true, 23871 }, 23872 { 23873 name: "Copy", 23874 argLen: 1, 23875 generic: true, 23876 }, 23877 { 23878 name: "Convert", 23879 argLen: 2, 23880 generic: true, 23881 }, 23882 { 23883 name: "ConstBool", 23884 auxType: auxBool, 23885 argLen: 0, 23886 generic: true, 23887 }, 23888 { 23889 name: "ConstString", 23890 auxType: auxString, 23891 argLen: 0, 23892 generic: true, 23893 }, 23894 { 23895 name: "ConstNil", 23896 argLen: 0, 23897 generic: true, 23898 }, 23899 { 23900 name: "Const8", 23901 auxType: auxInt8, 23902 argLen: 0, 23903 generic: true, 23904 }, 23905 { 23906 name: "Const16", 23907 auxType: auxInt16, 23908 argLen: 0, 23909 generic: true, 23910 }, 23911 { 23912 name: "Const32", 23913 auxType: auxInt32, 23914 argLen: 0, 23915 generic: true, 23916 }, 23917 { 23918 name: "Const64", 23919 auxType: auxInt64, 23920 argLen: 0, 23921 generic: true, 23922 }, 23923 { 23924 name: "Const32F", 23925 auxType: auxFloat32, 23926 argLen: 0, 23927 generic: true, 23928 }, 23929 { 23930 name: "Const64F", 23931 auxType: auxFloat64, 23932 argLen: 0, 23933 generic: true, 23934 }, 23935 { 23936 name: "ConstInterface", 23937 argLen: 0, 23938 generic: true, 23939 }, 23940 { 23941 name: "ConstSlice", 23942 argLen: 0, 23943 generic: true, 23944 }, 23945 { 23946 name: "InitMem", 23947 argLen: 0, 23948 generic: true, 23949 }, 23950 { 23951 name: "Arg", 23952 auxType: auxSymOff, 23953 argLen: 0, 23954 symEffect: SymRead, 23955 generic: true, 23956 }, 23957 { 23958 name: "Addr", 23959 auxType: auxSym, 23960 argLen: 1, 23961 symEffect: SymAddr, 23962 generic: true, 23963 }, 23964 { 23965 name: "SP", 23966 argLen: 0, 23967 generic: true, 23968 }, 23969 { 23970 name: "SB", 23971 argLen: 0, 23972 generic: true, 23973 }, 23974 { 23975 name: "Load", 23976 argLen: 2, 23977 generic: true, 23978 }, 23979 { 23980 name: "Store", 23981 auxType: auxTyp, 23982 argLen: 3, 23983 generic: true, 23984 }, 23985 { 23986 name: "Move", 23987 auxType: auxTypSize, 23988 argLen: 3, 23989 generic: true, 23990 }, 23991 { 23992 name: "Zero", 23993 auxType: auxTypSize, 23994 argLen: 2, 23995 generic: true, 23996 }, 23997 { 23998 name: "StoreWB", 23999 auxType: auxTyp, 24000 argLen: 3, 24001 generic: true, 24002 }, 24003 { 24004 name: "MoveWB", 24005 auxType: auxTypSize, 24006 argLen: 3, 24007 generic: true, 24008 }, 24009 { 24010 name: "ZeroWB", 24011 auxType: auxTypSize, 24012 argLen: 2, 24013 generic: true, 24014 }, 24015 { 24016 name: "WB", 24017 auxType: auxSym, 24018 argLen: 3, 24019 symEffect: SymNone, 24020 generic: true, 24021 }, 24022 { 24023 name: "ClosureCall", 24024 auxType: auxInt64, 24025 argLen: 3, 24026 call: true, 24027 generic: true, 24028 }, 24029 { 24030 name: "StaticCall", 24031 auxType: auxSymOff, 24032 argLen: 1, 24033 call: true, 24034 symEffect: SymNone, 24035 generic: true, 24036 }, 24037 { 24038 name: "InterCall", 24039 auxType: auxInt64, 24040 argLen: 2, 24041 call: true, 24042 generic: true, 24043 }, 24044 { 24045 name: "SignExt8to16", 24046 argLen: 1, 24047 generic: true, 24048 }, 24049 { 24050 name: "SignExt8to32", 24051 argLen: 1, 24052 generic: true, 24053 }, 24054 { 24055 name: "SignExt8to64", 24056 argLen: 1, 24057 generic: true, 24058 }, 24059 { 24060 name: "SignExt16to32", 24061 argLen: 1, 24062 generic: true, 24063 }, 24064 { 24065 name: "SignExt16to64", 24066 argLen: 1, 24067 generic: true, 24068 }, 24069 { 24070 name: "SignExt32to64", 24071 argLen: 1, 24072 generic: true, 24073 }, 24074 { 24075 name: "ZeroExt8to16", 24076 argLen: 1, 24077 generic: true, 24078 }, 24079 { 24080 name: "ZeroExt8to32", 24081 argLen: 1, 24082 generic: true, 24083 }, 24084 { 24085 name: "ZeroExt8to64", 24086 argLen: 1, 24087 generic: true, 24088 }, 24089 { 24090 name: "ZeroExt16to32", 24091 argLen: 1, 24092 generic: true, 24093 }, 24094 { 24095 name: "ZeroExt16to64", 24096 argLen: 1, 24097 generic: true, 24098 }, 24099 { 24100 name: "ZeroExt32to64", 24101 argLen: 1, 24102 generic: true, 24103 }, 24104 { 24105 name: "Trunc16to8", 24106 argLen: 1, 24107 generic: true, 24108 }, 24109 { 24110 name: "Trunc32to8", 24111 argLen: 1, 24112 generic: true, 24113 }, 24114 { 24115 name: "Trunc32to16", 24116 argLen: 1, 24117 generic: true, 24118 }, 24119 { 24120 name: "Trunc64to8", 24121 argLen: 1, 24122 generic: true, 24123 }, 24124 { 24125 name: "Trunc64to16", 24126 argLen: 1, 24127 generic: true, 24128 }, 24129 { 24130 name: "Trunc64to32", 24131 argLen: 1, 24132 generic: true, 24133 }, 24134 { 24135 name: "Cvt32to32F", 24136 argLen: 1, 24137 generic: true, 24138 }, 24139 { 24140 name: "Cvt32to64F", 24141 argLen: 1, 24142 generic: true, 24143 }, 24144 { 24145 name: "Cvt64to32F", 24146 argLen: 1, 24147 generic: true, 24148 }, 24149 { 24150 name: "Cvt64to64F", 24151 argLen: 1, 24152 generic: true, 24153 }, 24154 { 24155 name: "Cvt32Fto32", 24156 argLen: 1, 24157 generic: true, 24158 }, 24159 { 24160 name: "Cvt32Fto64", 24161 argLen: 1, 24162 generic: true, 24163 }, 24164 { 24165 name: "Cvt64Fto32", 24166 argLen: 1, 24167 generic: true, 24168 }, 24169 { 24170 name: "Cvt64Fto64", 24171 argLen: 1, 24172 generic: true, 24173 }, 24174 { 24175 name: "Cvt32Fto64F", 24176 argLen: 1, 24177 generic: true, 24178 }, 24179 { 24180 name: "Cvt64Fto32F", 24181 argLen: 1, 24182 generic: true, 24183 }, 24184 { 24185 name: "Round32F", 24186 argLen: 1, 24187 generic: true, 24188 }, 24189 { 24190 name: "Round64F", 24191 argLen: 1, 24192 generic: true, 24193 }, 24194 { 24195 name: "IsNonNil", 24196 argLen: 1, 24197 generic: true, 24198 }, 24199 { 24200 name: "IsInBounds", 24201 argLen: 2, 24202 generic: true, 24203 }, 24204 { 24205 name: "IsSliceInBounds", 24206 argLen: 2, 24207 generic: true, 24208 }, 24209 { 24210 name: "NilCheck", 24211 argLen: 2, 24212 generic: true, 24213 }, 24214 { 24215 name: "GetG", 24216 argLen: 1, 24217 generic: true, 24218 }, 24219 { 24220 name: "GetClosurePtr", 24221 argLen: 0, 24222 generic: true, 24223 }, 24224 { 24225 name: "GetCallerPC", 24226 argLen: 0, 24227 generic: true, 24228 }, 24229 { 24230 name: "GetCallerSP", 24231 argLen: 0, 24232 generic: true, 24233 }, 24234 { 24235 name: "PtrIndex", 24236 argLen: 2, 24237 generic: true, 24238 }, 24239 { 24240 name: "OffPtr", 24241 auxType: auxInt64, 24242 argLen: 1, 24243 generic: true, 24244 }, 24245 { 24246 name: "SliceMake", 24247 argLen: 3, 24248 generic: true, 24249 }, 24250 { 24251 name: "SlicePtr", 24252 argLen: 1, 24253 generic: true, 24254 }, 24255 { 24256 name: "SliceLen", 24257 argLen: 1, 24258 generic: true, 24259 }, 24260 { 24261 name: "SliceCap", 24262 argLen: 1, 24263 generic: true, 24264 }, 24265 { 24266 name: "ComplexMake", 24267 argLen: 2, 24268 generic: true, 24269 }, 24270 { 24271 name: "ComplexReal", 24272 argLen: 1, 24273 generic: true, 24274 }, 24275 { 24276 name: "ComplexImag", 24277 argLen: 1, 24278 generic: true, 24279 }, 24280 { 24281 name: "StringMake", 24282 argLen: 2, 24283 generic: true, 24284 }, 24285 { 24286 name: "StringPtr", 24287 argLen: 1, 24288 generic: true, 24289 }, 24290 { 24291 name: "StringLen", 24292 argLen: 1, 24293 generic: true, 24294 }, 24295 { 24296 name: "IMake", 24297 argLen: 2, 24298 generic: true, 24299 }, 24300 { 24301 name: "ITab", 24302 argLen: 1, 24303 generic: true, 24304 }, 24305 { 24306 name: "IData", 24307 argLen: 1, 24308 generic: true, 24309 }, 24310 { 24311 name: "StructMake0", 24312 argLen: 0, 24313 generic: true, 24314 }, 24315 { 24316 name: "StructMake1", 24317 argLen: 1, 24318 generic: true, 24319 }, 24320 { 24321 name: "StructMake2", 24322 argLen: 2, 24323 generic: true, 24324 }, 24325 { 24326 name: "StructMake3", 24327 argLen: 3, 24328 generic: true, 24329 }, 24330 { 24331 name: "StructMake4", 24332 argLen: 4, 24333 generic: true, 24334 }, 24335 { 24336 name: "StructSelect", 24337 auxType: auxInt64, 24338 argLen: 1, 24339 generic: true, 24340 }, 24341 { 24342 name: "ArrayMake0", 24343 argLen: 0, 24344 generic: true, 24345 }, 24346 { 24347 name: "ArrayMake1", 24348 argLen: 1, 24349 generic: true, 24350 }, 24351 { 24352 name: "ArraySelect", 24353 auxType: auxInt64, 24354 argLen: 1, 24355 generic: true, 24356 }, 24357 { 24358 name: "StoreReg", 24359 argLen: 1, 24360 generic: true, 24361 }, 24362 { 24363 name: "LoadReg", 24364 argLen: 1, 24365 generic: true, 24366 }, 24367 { 24368 name: "FwdRef", 24369 auxType: auxSym, 24370 argLen: 0, 24371 symEffect: SymNone, 24372 generic: true, 24373 }, 24374 { 24375 name: "Unknown", 24376 argLen: 0, 24377 generic: true, 24378 }, 24379 { 24380 name: "VarDef", 24381 auxType: auxSym, 24382 argLen: 1, 24383 symEffect: SymNone, 24384 generic: true, 24385 }, 24386 { 24387 name: "VarKill", 24388 auxType: auxSym, 24389 argLen: 1, 24390 symEffect: SymNone, 24391 generic: true, 24392 }, 24393 { 24394 name: "VarLive", 24395 auxType: auxSym, 24396 argLen: 1, 24397 symEffect: SymRead, 24398 generic: true, 24399 }, 24400 { 24401 name: "KeepAlive", 24402 argLen: 2, 24403 generic: true, 24404 }, 24405 { 24406 name: "Int64Make", 24407 argLen: 2, 24408 generic: true, 24409 }, 24410 { 24411 name: "Int64Hi", 24412 argLen: 1, 24413 generic: true, 24414 }, 24415 { 24416 name: "Int64Lo", 24417 argLen: 1, 24418 generic: true, 24419 }, 24420 { 24421 name: "Add32carry", 24422 argLen: 2, 24423 commutative: true, 24424 generic: true, 24425 }, 24426 { 24427 name: "Add32withcarry", 24428 argLen: 3, 24429 commutative: true, 24430 generic: true, 24431 }, 24432 { 24433 name: "Sub32carry", 24434 argLen: 2, 24435 generic: true, 24436 }, 24437 { 24438 name: "Sub32withcarry", 24439 argLen: 3, 24440 generic: true, 24441 }, 24442 { 24443 name: "Signmask", 24444 argLen: 1, 24445 generic: true, 24446 }, 24447 { 24448 name: "Zeromask", 24449 argLen: 1, 24450 generic: true, 24451 }, 24452 { 24453 name: "Slicemask", 24454 argLen: 1, 24455 generic: true, 24456 }, 24457 { 24458 name: "Cvt32Uto32F", 24459 argLen: 1, 24460 generic: true, 24461 }, 24462 { 24463 name: "Cvt32Uto64F", 24464 argLen: 1, 24465 generic: true, 24466 }, 24467 { 24468 name: "Cvt32Fto32U", 24469 argLen: 1, 24470 generic: true, 24471 }, 24472 { 24473 name: "Cvt64Fto32U", 24474 argLen: 1, 24475 generic: true, 24476 }, 24477 { 24478 name: "Cvt64Uto32F", 24479 argLen: 1, 24480 generic: true, 24481 }, 24482 { 24483 name: "Cvt64Uto64F", 24484 argLen: 1, 24485 generic: true, 24486 }, 24487 { 24488 name: "Cvt32Fto64U", 24489 argLen: 1, 24490 generic: true, 24491 }, 24492 { 24493 name: "Cvt64Fto64U", 24494 argLen: 1, 24495 generic: true, 24496 }, 24497 { 24498 name: "Select0", 24499 argLen: 1, 24500 generic: true, 24501 }, 24502 { 24503 name: "Select1", 24504 argLen: 1, 24505 generic: true, 24506 }, 24507 { 24508 name: "AtomicLoad32", 24509 argLen: 2, 24510 generic: true, 24511 }, 24512 { 24513 name: "AtomicLoad64", 24514 argLen: 2, 24515 generic: true, 24516 }, 24517 { 24518 name: "AtomicLoadPtr", 24519 argLen: 2, 24520 generic: true, 24521 }, 24522 { 24523 name: "AtomicStore32", 24524 argLen: 3, 24525 hasSideEffects: true, 24526 generic: true, 24527 }, 24528 { 24529 name: "AtomicStore64", 24530 argLen: 3, 24531 hasSideEffects: true, 24532 generic: true, 24533 }, 24534 { 24535 name: "AtomicStorePtrNoWB", 24536 argLen: 3, 24537 hasSideEffects: true, 24538 generic: true, 24539 }, 24540 { 24541 name: "AtomicExchange32", 24542 argLen: 3, 24543 hasSideEffects: true, 24544 generic: true, 24545 }, 24546 { 24547 name: "AtomicExchange64", 24548 argLen: 3, 24549 hasSideEffects: true, 24550 generic: true, 24551 }, 24552 { 24553 name: "AtomicAdd32", 24554 argLen: 3, 24555 hasSideEffects: true, 24556 generic: true, 24557 }, 24558 { 24559 name: "AtomicAdd64", 24560 argLen: 3, 24561 hasSideEffects: true, 24562 generic: true, 24563 }, 24564 { 24565 name: "AtomicCompareAndSwap32", 24566 argLen: 4, 24567 hasSideEffects: true, 24568 generic: true, 24569 }, 24570 { 24571 name: "AtomicCompareAndSwap64", 24572 argLen: 4, 24573 hasSideEffects: true, 24574 generic: true, 24575 }, 24576 { 24577 name: "AtomicAnd8", 24578 argLen: 3, 24579 hasSideEffects: true, 24580 generic: true, 24581 }, 24582 { 24583 name: "AtomicOr8", 24584 argLen: 3, 24585 hasSideEffects: true, 24586 generic: true, 24587 }, 24588 { 24589 name: "Clobber", 24590 auxType: auxSymOff, 24591 argLen: 0, 24592 symEffect: SymNone, 24593 generic: true, 24594 }, 24595 } 24596 24597 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 24598 func (o Op) String() string { return opcodeTable[o].name } 24599 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 24600 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 24601 func (o Op) IsCall() bool { return opcodeTable[o].call } 24602 24603 var registers386 = [...]Register{ 24604 {0, x86.REG_AX, "AX"}, 24605 {1, x86.REG_CX, "CX"}, 24606 {2, x86.REG_DX, "DX"}, 24607 {3, x86.REG_BX, "BX"}, 24608 {4, x86.REGSP, "SP"}, 24609 {5, x86.REG_BP, "BP"}, 24610 {6, x86.REG_SI, "SI"}, 24611 {7, x86.REG_DI, "DI"}, 24612 {8, x86.REG_X0, "X0"}, 24613 {9, x86.REG_X1, "X1"}, 24614 {10, x86.REG_X2, "X2"}, 24615 {11, x86.REG_X3, "X3"}, 24616 {12, x86.REG_X4, "X4"}, 24617 {13, x86.REG_X5, "X5"}, 24618 {14, x86.REG_X6, "X6"}, 24619 {15, x86.REG_X7, "X7"}, 24620 {16, 0, "SB"}, 24621 } 24622 var gpRegMask386 = regMask(239) 24623 var fpRegMask386 = regMask(65280) 24624 var specialRegMask386 = regMask(0) 24625 var framepointerReg386 = int8(5) 24626 var linkReg386 = int8(-1) 24627 var registersAMD64 = [...]Register{ 24628 {0, x86.REG_AX, "AX"}, 24629 {1, x86.REG_CX, "CX"}, 24630 {2, x86.REG_DX, "DX"}, 24631 {3, x86.REG_BX, "BX"}, 24632 {4, x86.REGSP, "SP"}, 24633 {5, x86.REG_BP, "BP"}, 24634 {6, x86.REG_SI, "SI"}, 24635 {7, x86.REG_DI, "DI"}, 24636 {8, x86.REG_R8, "R8"}, 24637 {9, x86.REG_R9, "R9"}, 24638 {10, x86.REG_R10, "R10"}, 24639 {11, x86.REG_R11, "R11"}, 24640 {12, x86.REG_R12, "R12"}, 24641 {13, x86.REG_R13, "R13"}, 24642 {14, x86.REG_R14, "R14"}, 24643 {15, x86.REG_R15, "R15"}, 24644 {16, x86.REG_X0, "X0"}, 24645 {17, x86.REG_X1, "X1"}, 24646 {18, x86.REG_X2, "X2"}, 24647 {19, x86.REG_X3, "X3"}, 24648 {20, x86.REG_X4, "X4"}, 24649 {21, x86.REG_X5, "X5"}, 24650 {22, x86.REG_X6, "X6"}, 24651 {23, x86.REG_X7, "X7"}, 24652 {24, x86.REG_X8, "X8"}, 24653 {25, x86.REG_X9, "X9"}, 24654 {26, x86.REG_X10, "X10"}, 24655 {27, x86.REG_X11, "X11"}, 24656 {28, x86.REG_X12, "X12"}, 24657 {29, x86.REG_X13, "X13"}, 24658 {30, x86.REG_X14, "X14"}, 24659 {31, x86.REG_X15, "X15"}, 24660 {32, 0, "SB"}, 24661 } 24662 var gpRegMaskAMD64 = regMask(65519) 24663 var fpRegMaskAMD64 = regMask(4294901760) 24664 var specialRegMaskAMD64 = regMask(0) 24665 var framepointerRegAMD64 = int8(5) 24666 var linkRegAMD64 = int8(-1) 24667 var registersARM = [...]Register{ 24668 {0, arm.REG_R0, "R0"}, 24669 {1, arm.REG_R1, "R1"}, 24670 {2, arm.REG_R2, "R2"}, 24671 {3, arm.REG_R3, "R3"}, 24672 {4, arm.REG_R4, "R4"}, 24673 {5, arm.REG_R5, "R5"}, 24674 {6, arm.REG_R6, "R6"}, 24675 {7, arm.REG_R7, "R7"}, 24676 {8, arm.REG_R8, "R8"}, 24677 {9, arm.REG_R9, "R9"}, 24678 {10, arm.REGG, "g"}, 24679 {11, arm.REG_R11, "R11"}, 24680 {12, arm.REG_R12, "R12"}, 24681 {13, arm.REGSP, "SP"}, 24682 {14, arm.REG_R14, "R14"}, 24683 {15, arm.REG_R15, "R15"}, 24684 {16, arm.REG_F0, "F0"}, 24685 {17, arm.REG_F1, "F1"}, 24686 {18, arm.REG_F2, "F2"}, 24687 {19, arm.REG_F3, "F3"}, 24688 {20, arm.REG_F4, "F4"}, 24689 {21, arm.REG_F5, "F5"}, 24690 {22, arm.REG_F6, "F6"}, 24691 {23, arm.REG_F7, "F7"}, 24692 {24, arm.REG_F8, "F8"}, 24693 {25, arm.REG_F9, "F9"}, 24694 {26, arm.REG_F10, "F10"}, 24695 {27, arm.REG_F11, "F11"}, 24696 {28, arm.REG_F12, "F12"}, 24697 {29, arm.REG_F13, "F13"}, 24698 {30, arm.REG_F14, "F14"}, 24699 {31, arm.REG_F15, "F15"}, 24700 {32, 0, "SB"}, 24701 } 24702 var gpRegMaskARM = regMask(21503) 24703 var fpRegMaskARM = regMask(4294901760) 24704 var specialRegMaskARM = regMask(0) 24705 var framepointerRegARM = int8(-1) 24706 var linkRegARM = int8(14) 24707 var registersARM64 = [...]Register{ 24708 {0, arm64.REG_R0, "R0"}, 24709 {1, arm64.REG_R1, "R1"}, 24710 {2, arm64.REG_R2, "R2"}, 24711 {3, arm64.REG_R3, "R3"}, 24712 {4, arm64.REG_R4, "R4"}, 24713 {5, arm64.REG_R5, "R5"}, 24714 {6, arm64.REG_R6, "R6"}, 24715 {7, arm64.REG_R7, "R7"}, 24716 {8, arm64.REG_R8, "R8"}, 24717 {9, arm64.REG_R9, "R9"}, 24718 {10, arm64.REG_R10, "R10"}, 24719 {11, arm64.REG_R11, "R11"}, 24720 {12, arm64.REG_R12, "R12"}, 24721 {13, arm64.REG_R13, "R13"}, 24722 {14, arm64.REG_R14, "R14"}, 24723 {15, arm64.REG_R15, "R15"}, 24724 {16, arm64.REG_R16, "R16"}, 24725 {17, arm64.REG_R17, "R17"}, 24726 {18, arm64.REG_R18, "R18"}, 24727 {19, arm64.REG_R19, "R19"}, 24728 {20, arm64.REG_R20, "R20"}, 24729 {21, arm64.REG_R21, "R21"}, 24730 {22, arm64.REG_R22, "R22"}, 24731 {23, arm64.REG_R23, "R23"}, 24732 {24, arm64.REG_R24, "R24"}, 24733 {25, arm64.REG_R25, "R25"}, 24734 {26, arm64.REG_R26, "R26"}, 24735 {27, arm64.REGG, "g"}, 24736 {28, arm64.REG_R29, "R29"}, 24737 {29, arm64.REG_R30, "R30"}, 24738 {30, arm64.REGSP, "SP"}, 24739 {31, arm64.REG_F0, "F0"}, 24740 {32, arm64.REG_F1, "F1"}, 24741 {33, arm64.REG_F2, "F2"}, 24742 {34, arm64.REG_F3, "F3"}, 24743 {35, arm64.REG_F4, "F4"}, 24744 {36, arm64.REG_F5, "F5"}, 24745 {37, arm64.REG_F6, "F6"}, 24746 {38, arm64.REG_F7, "F7"}, 24747 {39, arm64.REG_F8, "F8"}, 24748 {40, arm64.REG_F9, "F9"}, 24749 {41, arm64.REG_F10, "F10"}, 24750 {42, arm64.REG_F11, "F11"}, 24751 {43, arm64.REG_F12, "F12"}, 24752 {44, arm64.REG_F13, "F13"}, 24753 {45, arm64.REG_F14, "F14"}, 24754 {46, arm64.REG_F15, "F15"}, 24755 {47, arm64.REG_F16, "F16"}, 24756 {48, arm64.REG_F17, "F17"}, 24757 {49, arm64.REG_F18, "F18"}, 24758 {50, arm64.REG_F19, "F19"}, 24759 {51, arm64.REG_F20, "F20"}, 24760 {52, arm64.REG_F21, "F21"}, 24761 {53, arm64.REG_F22, "F22"}, 24762 {54, arm64.REG_F23, "F23"}, 24763 {55, arm64.REG_F24, "F24"}, 24764 {56, arm64.REG_F25, "F25"}, 24765 {57, arm64.REG_F26, "F26"}, 24766 {58, arm64.REG_F27, "F27"}, 24767 {59, arm64.REG_F28, "F28"}, 24768 {60, arm64.REG_F29, "F29"}, 24769 {61, arm64.REG_F30, "F30"}, 24770 {62, arm64.REG_F31, "F31"}, 24771 {63, 0, "SB"}, 24772 } 24773 var gpRegMaskARM64 = regMask(670826495) 24774 var fpRegMaskARM64 = regMask(9223372034707292160) 24775 var specialRegMaskARM64 = regMask(0) 24776 var framepointerRegARM64 = int8(-1) 24777 var linkRegARM64 = int8(29) 24778 var registersMIPS = [...]Register{ 24779 {0, mips.REG_R0, "R0"}, 24780 {1, mips.REG_R1, "R1"}, 24781 {2, mips.REG_R2, "R2"}, 24782 {3, mips.REG_R3, "R3"}, 24783 {4, mips.REG_R4, "R4"}, 24784 {5, mips.REG_R5, "R5"}, 24785 {6, mips.REG_R6, "R6"}, 24786 {7, mips.REG_R7, "R7"}, 24787 {8, mips.REG_R8, "R8"}, 24788 {9, mips.REG_R9, "R9"}, 24789 {10, mips.REG_R10, "R10"}, 24790 {11, mips.REG_R11, "R11"}, 24791 {12, mips.REG_R12, "R12"}, 24792 {13, mips.REG_R13, "R13"}, 24793 {14, mips.REG_R14, "R14"}, 24794 {15, mips.REG_R15, "R15"}, 24795 {16, mips.REG_R16, "R16"}, 24796 {17, mips.REG_R17, "R17"}, 24797 {18, mips.REG_R18, "R18"}, 24798 {19, mips.REG_R19, "R19"}, 24799 {20, mips.REG_R20, "R20"}, 24800 {21, mips.REG_R21, "R21"}, 24801 {22, mips.REG_R22, "R22"}, 24802 {23, mips.REG_R24, "R24"}, 24803 {24, mips.REG_R25, "R25"}, 24804 {25, mips.REG_R28, "R28"}, 24805 {26, mips.REGSP, "SP"}, 24806 {27, mips.REGG, "g"}, 24807 {28, mips.REG_R31, "R31"}, 24808 {29, mips.REG_F0, "F0"}, 24809 {30, mips.REG_F2, "F2"}, 24810 {31, mips.REG_F4, "F4"}, 24811 {32, mips.REG_F6, "F6"}, 24812 {33, mips.REG_F8, "F8"}, 24813 {34, mips.REG_F10, "F10"}, 24814 {35, mips.REG_F12, "F12"}, 24815 {36, mips.REG_F14, "F14"}, 24816 {37, mips.REG_F16, "F16"}, 24817 {38, mips.REG_F18, "F18"}, 24818 {39, mips.REG_F20, "F20"}, 24819 {40, mips.REG_F22, "F22"}, 24820 {41, mips.REG_F24, "F24"}, 24821 {42, mips.REG_F26, "F26"}, 24822 {43, mips.REG_F28, "F28"}, 24823 {44, mips.REG_F30, "F30"}, 24824 {45, mips.REG_HI, "HI"}, 24825 {46, mips.REG_LO, "LO"}, 24826 {47, 0, "SB"}, 24827 } 24828 var gpRegMaskMIPS = regMask(335544318) 24829 var fpRegMaskMIPS = regMask(35183835217920) 24830 var specialRegMaskMIPS = regMask(105553116266496) 24831 var framepointerRegMIPS = int8(-1) 24832 var linkRegMIPS = int8(28) 24833 var registersMIPS64 = [...]Register{ 24834 {0, mips.REG_R0, "R0"}, 24835 {1, mips.REG_R1, "R1"}, 24836 {2, mips.REG_R2, "R2"}, 24837 {3, mips.REG_R3, "R3"}, 24838 {4, mips.REG_R4, "R4"}, 24839 {5, mips.REG_R5, "R5"}, 24840 {6, mips.REG_R6, "R6"}, 24841 {7, mips.REG_R7, "R7"}, 24842 {8, mips.REG_R8, "R8"}, 24843 {9, mips.REG_R9, "R9"}, 24844 {10, mips.REG_R10, "R10"}, 24845 {11, mips.REG_R11, "R11"}, 24846 {12, mips.REG_R12, "R12"}, 24847 {13, mips.REG_R13, "R13"}, 24848 {14, mips.REG_R14, "R14"}, 24849 {15, mips.REG_R15, "R15"}, 24850 {16, mips.REG_R16, "R16"}, 24851 {17, mips.REG_R17, "R17"}, 24852 {18, mips.REG_R18, "R18"}, 24853 {19, mips.REG_R19, "R19"}, 24854 {20, mips.REG_R20, "R20"}, 24855 {21, mips.REG_R21, "R21"}, 24856 {22, mips.REG_R22, "R22"}, 24857 {23, mips.REG_R24, "R24"}, 24858 {24, mips.REG_R25, "R25"}, 24859 {25, mips.REGSP, "SP"}, 24860 {26, mips.REGG, "g"}, 24861 {27, mips.REG_R31, "R31"}, 24862 {28, mips.REG_F0, "F0"}, 24863 {29, mips.REG_F1, "F1"}, 24864 {30, mips.REG_F2, "F2"}, 24865 {31, mips.REG_F3, "F3"}, 24866 {32, mips.REG_F4, "F4"}, 24867 {33, mips.REG_F5, "F5"}, 24868 {34, mips.REG_F6, "F6"}, 24869 {35, mips.REG_F7, "F7"}, 24870 {36, mips.REG_F8, "F8"}, 24871 {37, mips.REG_F9, "F9"}, 24872 {38, mips.REG_F10, "F10"}, 24873 {39, mips.REG_F11, "F11"}, 24874 {40, mips.REG_F12, "F12"}, 24875 {41, mips.REG_F13, "F13"}, 24876 {42, mips.REG_F14, "F14"}, 24877 {43, mips.REG_F15, "F15"}, 24878 {44, mips.REG_F16, "F16"}, 24879 {45, mips.REG_F17, "F17"}, 24880 {46, mips.REG_F18, "F18"}, 24881 {47, mips.REG_F19, "F19"}, 24882 {48, mips.REG_F20, "F20"}, 24883 {49, mips.REG_F21, "F21"}, 24884 {50, mips.REG_F22, "F22"}, 24885 {51, mips.REG_F23, "F23"}, 24886 {52, mips.REG_F24, "F24"}, 24887 {53, mips.REG_F25, "F25"}, 24888 {54, mips.REG_F26, "F26"}, 24889 {55, mips.REG_F27, "F27"}, 24890 {56, mips.REG_F28, "F28"}, 24891 {57, mips.REG_F29, "F29"}, 24892 {58, mips.REG_F30, "F30"}, 24893 {59, mips.REG_F31, "F31"}, 24894 {60, mips.REG_HI, "HI"}, 24895 {61, mips.REG_LO, "LO"}, 24896 {62, 0, "SB"}, 24897 } 24898 var gpRegMaskMIPS64 = regMask(167772158) 24899 var fpRegMaskMIPS64 = regMask(1152921504338411520) 24900 var specialRegMaskMIPS64 = regMask(3458764513820540928) 24901 var framepointerRegMIPS64 = int8(-1) 24902 var linkRegMIPS64 = int8(27) 24903 var registersPPC64 = [...]Register{ 24904 {0, ppc64.REG_R0, "R0"}, 24905 {1, ppc64.REGSP, "SP"}, 24906 {2, 0, "SB"}, 24907 {3, ppc64.REG_R3, "R3"}, 24908 {4, ppc64.REG_R4, "R4"}, 24909 {5, ppc64.REG_R5, "R5"}, 24910 {6, ppc64.REG_R6, "R6"}, 24911 {7, ppc64.REG_R7, "R7"}, 24912 {8, ppc64.REG_R8, "R8"}, 24913 {9, ppc64.REG_R9, "R9"}, 24914 {10, ppc64.REG_R10, "R10"}, 24915 {11, ppc64.REG_R11, "R11"}, 24916 {12, ppc64.REG_R12, "R12"}, 24917 {13, ppc64.REG_R13, "R13"}, 24918 {14, ppc64.REG_R14, "R14"}, 24919 {15, ppc64.REG_R15, "R15"}, 24920 {16, ppc64.REG_R16, "R16"}, 24921 {17, ppc64.REG_R17, "R17"}, 24922 {18, ppc64.REG_R18, "R18"}, 24923 {19, ppc64.REG_R19, "R19"}, 24924 {20, ppc64.REG_R20, "R20"}, 24925 {21, ppc64.REG_R21, "R21"}, 24926 {22, ppc64.REG_R22, "R22"}, 24927 {23, ppc64.REG_R23, "R23"}, 24928 {24, ppc64.REG_R24, "R24"}, 24929 {25, ppc64.REG_R25, "R25"}, 24930 {26, ppc64.REG_R26, "R26"}, 24931 {27, ppc64.REG_R27, "R27"}, 24932 {28, ppc64.REG_R28, "R28"}, 24933 {29, ppc64.REG_R29, "R29"}, 24934 {30, ppc64.REGG, "g"}, 24935 {31, ppc64.REG_R31, "R31"}, 24936 {32, ppc64.REG_F0, "F0"}, 24937 {33, ppc64.REG_F1, "F1"}, 24938 {34, ppc64.REG_F2, "F2"}, 24939 {35, ppc64.REG_F3, "F3"}, 24940 {36, ppc64.REG_F4, "F4"}, 24941 {37, ppc64.REG_F5, "F5"}, 24942 {38, ppc64.REG_F6, "F6"}, 24943 {39, ppc64.REG_F7, "F7"}, 24944 {40, ppc64.REG_F8, "F8"}, 24945 {41, ppc64.REG_F9, "F9"}, 24946 {42, ppc64.REG_F10, "F10"}, 24947 {43, ppc64.REG_F11, "F11"}, 24948 {44, ppc64.REG_F12, "F12"}, 24949 {45, ppc64.REG_F13, "F13"}, 24950 {46, ppc64.REG_F14, "F14"}, 24951 {47, ppc64.REG_F15, "F15"}, 24952 {48, ppc64.REG_F16, "F16"}, 24953 {49, ppc64.REG_F17, "F17"}, 24954 {50, ppc64.REG_F18, "F18"}, 24955 {51, ppc64.REG_F19, "F19"}, 24956 {52, ppc64.REG_F20, "F20"}, 24957 {53, ppc64.REG_F21, "F21"}, 24958 {54, ppc64.REG_F22, "F22"}, 24959 {55, ppc64.REG_F23, "F23"}, 24960 {56, ppc64.REG_F24, "F24"}, 24961 {57, ppc64.REG_F25, "F25"}, 24962 {58, ppc64.REG_F26, "F26"}, 24963 {59, ppc64.REG_F27, "F27"}, 24964 {60, ppc64.REG_F28, "F28"}, 24965 {61, ppc64.REG_F29, "F29"}, 24966 {62, ppc64.REG_F30, "F30"}, 24967 {63, ppc64.REG_F31, "F31"}, 24968 } 24969 var gpRegMaskPPC64 = regMask(1073733624) 24970 var fpRegMaskPPC64 = regMask(576460743713488896) 24971 var specialRegMaskPPC64 = regMask(0) 24972 var framepointerRegPPC64 = int8(1) 24973 var linkRegPPC64 = int8(-1) 24974 var registersS390X = [...]Register{ 24975 {0, s390x.REG_R0, "R0"}, 24976 {1, s390x.REG_R1, "R1"}, 24977 {2, s390x.REG_R2, "R2"}, 24978 {3, s390x.REG_R3, "R3"}, 24979 {4, s390x.REG_R4, "R4"}, 24980 {5, s390x.REG_R5, "R5"}, 24981 {6, s390x.REG_R6, "R6"}, 24982 {7, s390x.REG_R7, "R7"}, 24983 {8, s390x.REG_R8, "R8"}, 24984 {9, s390x.REG_R9, "R9"}, 24985 {10, s390x.REG_R10, "R10"}, 24986 {11, s390x.REG_R11, "R11"}, 24987 {12, s390x.REG_R12, "R12"}, 24988 {13, s390x.REGG, "g"}, 24989 {14, s390x.REG_R14, "R14"}, 24990 {15, s390x.REGSP, "SP"}, 24991 {16, s390x.REG_F0, "F0"}, 24992 {17, s390x.REG_F1, "F1"}, 24993 {18, s390x.REG_F2, "F2"}, 24994 {19, s390x.REG_F3, "F3"}, 24995 {20, s390x.REG_F4, "F4"}, 24996 {21, s390x.REG_F5, "F5"}, 24997 {22, s390x.REG_F6, "F6"}, 24998 {23, s390x.REG_F7, "F7"}, 24999 {24, s390x.REG_F8, "F8"}, 25000 {25, s390x.REG_F9, "F9"}, 25001 {26, s390x.REG_F10, "F10"}, 25002 {27, s390x.REG_F11, "F11"}, 25003 {28, s390x.REG_F12, "F12"}, 25004 {29, s390x.REG_F13, "F13"}, 25005 {30, s390x.REG_F14, "F14"}, 25006 {31, s390x.REG_F15, "F15"}, 25007 {32, 0, "SB"}, 25008 } 25009 var gpRegMaskS390X = regMask(21503) 25010 var fpRegMaskS390X = regMask(4294901760) 25011 var specialRegMaskS390X = regMask(0) 25012 var framepointerRegS390X = int8(-1) 25013 var linkRegS390X = int8(14)