github.com/dannin/go@v0.0.0-20161031215817-d35dfd405eaa/src/cmd/compile/internal/ssa/gen/S390X.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (Add64 x y) -> (ADD x y) 7 (AddPtr x y) -> (ADD x y) 8 (Add32 x y) -> (ADDW x y) 9 (Add16 x y) -> (ADDW x y) 10 (Add8 x y) -> (ADDW x y) 11 (Add32F x y) -> (FADDS x y) 12 (Add64F x y) -> (FADD x y) 13 14 (Sub64 x y) -> (SUB x y) 15 (SubPtr x y) -> (SUB x y) 16 (Sub32 x y) -> (SUBW x y) 17 (Sub16 x y) -> (SUBW x y) 18 (Sub8 x y) -> (SUBW x y) 19 (Sub32F x y) -> (FSUBS x y) 20 (Sub64F x y) -> (FSUB x y) 21 22 (Mul64 x y) -> (MULLD x y) 23 (Mul32 x y) -> (MULLW x y) 24 (Mul16 x y) -> (MULLW x y) 25 (Mul8 x y) -> (MULLW x y) 26 (Mul32F x y) -> (FMULS x y) 27 (Mul64F x y) -> (FMUL x y) 28 29 (Div32F x y) -> (FDIVS x y) 30 (Div64F x y) -> (FDIV x y) 31 32 (Div64 x y) -> (DIVD x y) 33 (Div64u x y) -> (DIVDU x y) 34 // DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor, 35 // so a sign/zero extension of the dividend is required. 36 (Div32 x y) -> (DIVW (MOVWreg x) y) 37 (Div32u x y) -> (DIVWU (MOVWZreg x) y) 38 (Div16 x y) -> (DIVW (MOVHreg x) (MOVHreg y)) 39 (Div16u x y) -> (DIVWU (MOVHZreg x) (MOVHZreg y)) 40 (Div8 x y) -> (DIVW (MOVBreg x) (MOVBreg y)) 41 (Div8u x y) -> (DIVWU (MOVBZreg x) (MOVBZreg y)) 42 43 (Hmul64 x y) -> (MULHD x y) 44 (Hmul64u x y) -> (MULHDU x y) 45 (Hmul32 x y) -> (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y))) 46 (Hmul32u x y) -> (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y))) 47 (Hmul16 x y) -> (SRDconst [16] (MULLW (MOVHreg x) (MOVHreg y))) 48 (Hmul16u x y) -> (SRDconst [16] (MULLW (MOVHZreg x) (MOVHZreg y))) 49 (Hmul8 x y) -> (SRDconst [8] (MULLW (MOVBreg x) (MOVBreg y))) 50 (Hmul8u x y) -> (SRDconst [8] (MULLW (MOVBZreg x) (MOVBZreg y))) 51 52 (Mod64 x y) -> (MODD x y) 53 (Mod64u x y) -> (MODDU x y) 54 // MODW/MODWU has a 64-bit dividend and a 32-bit divisor, 55 // so a sign/zero extension of the dividend is required. 56 (Mod32 x y) -> (MODW (MOVWreg x) y) 57 (Mod32u x y) -> (MODWU (MOVWZreg x) y) 58 (Mod16 x y) -> (MODW (MOVHreg x) (MOVHreg y)) 59 (Mod16u x y) -> (MODWU (MOVHZreg x) (MOVHZreg y)) 60 (Mod8 x y) -> (MODW (MOVBreg x) (MOVBreg y)) 61 (Mod8u x y) -> (MODWU (MOVBZreg x) (MOVBZreg y)) 62 63 (Avg64u <t> x y) -> (ADD (ADD <t> (SRDconst <t> x [1]) (SRDconst <t> y [1])) (ANDconst <t> (AND <t> x y) [1])) 64 65 (And64 x y) -> (AND x y) 66 (And32 x y) -> (ANDW x y) 67 (And16 x y) -> (ANDW x y) 68 (And8 x y) -> (ANDW x y) 69 70 (Or64 x y) -> (OR x y) 71 (Or32 x y) -> (ORW x y) 72 (Or16 x y) -> (ORW x y) 73 (Or8 x y) -> (ORW x y) 74 75 (Xor64 x y) -> (XOR x y) 76 (Xor32 x y) -> (XORW x y) 77 (Xor16 x y) -> (XORW x y) 78 (Xor8 x y) -> (XORW x y) 79 80 (Neg64 x) -> (NEG x) 81 (Neg32 x) -> (NEGW x) 82 (Neg16 x) -> (NEGW (MOVHreg x)) 83 (Neg8 x) -> (NEGW (MOVBreg x)) 84 (Neg32F x) -> (FNEGS x) 85 (Neg64F x) -> (FNEG x) 86 87 (Com64 x) -> (NOT x) 88 (Com32 x) -> (NOTW x) 89 (Com16 x) -> (NOTW x) 90 (Com8 x) -> (NOTW x) 91 (NOT x) && true -> (XOR (MOVDconst [-1]) x) 92 (NOTW x) && true -> (XORWconst [-1] x) 93 94 // Lowering boolean ops 95 (AndB x y) -> (ANDW x y) 96 (OrB x y) -> (ORW x y) 97 (Not x) -> (XORWconst [1] x) 98 99 // Lowering pointer arithmetic 100 (OffPtr [off] ptr:(SP)) -> (MOVDaddr [off] ptr) 101 (OffPtr [off] ptr) && is32Bit(off) -> (ADDconst [off] ptr) 102 (OffPtr [off] ptr) -> (ADD (MOVDconst [off]) ptr) 103 104 // Ctz(x) = 64 - findLeftmostOne((x-1)&^x) 105 (Ctz64 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (AND <t> (SUBconst <t> [1] x) (NOT <t> x)))) 106 (Ctz32 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (MOVWZreg (ANDW <t> (SUBWconst <t> [1] x) (NOTW <t> x))))) 107 108 (Bswap64 x) -> (MOVDBR x) 109 (Bswap32 x) -> (MOVWBR x) 110 111 (Sqrt x) -> (FSQRT x) 112 113 // Atomic loads. 114 (AtomicLoad32 ptr mem) -> (MOVWZatomicload ptr mem) 115 (AtomicLoad64 ptr mem) -> (MOVDatomicload ptr mem) 116 (AtomicLoadPtr ptr mem) -> (MOVDatomicload ptr mem) 117 118 // Atomic stores. 119 (AtomicStore32 ptr val mem) -> (MOVWatomicstore ptr val mem) 120 (AtomicStore64 ptr val mem) -> (MOVDatomicstore ptr val mem) 121 (AtomicStorePtrNoWB ptr val mem) -> (MOVDatomicstore ptr val mem) 122 123 // Atomic adds. 124 (AtomicAdd32 ptr val mem) -> (AddTupleFirst32 (LAA ptr val mem) val) 125 (AtomicAdd64 ptr val mem) -> (AddTupleFirst64 (LAAG ptr val mem) val) 126 (Select0 <t> (AddTupleFirst32 tuple val)) -> (ADDW val (Select0 <t> tuple)) 127 (Select1 (AddTupleFirst32 tuple _ )) -> (Select1 tuple) 128 (Select0 <t> (AddTupleFirst64 tuple val)) -> (ADD val (Select0 <t> tuple)) 129 (Select1 (AddTupleFirst64 tuple _ )) -> (Select1 tuple) 130 131 // Atomic exchanges. 132 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 133 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 134 135 // Atomic compare and swap. 136 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 137 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 138 139 // Lowering extension 140 // Note: we always extend to 64 bits even though some ops don't need that many result bits. 141 (SignExt8to16 x) -> (MOVBreg x) 142 (SignExt8to32 x) -> (MOVBreg x) 143 (SignExt8to64 x) -> (MOVBreg x) 144 (SignExt16to32 x) -> (MOVHreg x) 145 (SignExt16to64 x) -> (MOVHreg x) 146 (SignExt32to64 x) -> (MOVWreg x) 147 148 (ZeroExt8to16 x) -> (MOVBZreg x) 149 (ZeroExt8to32 x) -> (MOVBZreg x) 150 (ZeroExt8to64 x) -> (MOVBZreg x) 151 (ZeroExt16to32 x) -> (MOVHZreg x) 152 (ZeroExt16to64 x) -> (MOVHZreg x) 153 (ZeroExt32to64 x) -> (MOVWZreg x) 154 155 (Slicemask <t> x) -> (XOR (MOVDconst [-1]) (SRADconst <t> (SUBconst <t> x [1]) [63])) 156 157 // Lowering truncation 158 // Because we ignore high parts of registers, truncates are just copies. 159 (Trunc16to8 x) -> x 160 (Trunc32to8 x) -> x 161 (Trunc32to16 x) -> x 162 (Trunc64to8 x) -> x 163 (Trunc64to16 x) -> x 164 (Trunc64to32 x) -> x 165 166 // Lowering float <-> int 167 (Cvt32to32F x) -> (CEFBRA x) 168 (Cvt32to64F x) -> (CDFBRA x) 169 (Cvt64to32F x) -> (CEGBRA x) 170 (Cvt64to64F x) -> (CDGBRA x) 171 172 (Cvt32Fto32 x) -> (CFEBRA x) 173 (Cvt32Fto64 x) -> (CGEBRA x) 174 (Cvt64Fto32 x) -> (CFDBRA x) 175 (Cvt64Fto64 x) -> (CGDBRA x) 176 177 (Cvt32Fto64F x) -> (LDEBR x) 178 (Cvt64Fto32F x) -> (LEDBR x) 179 180 // Lowering shifts 181 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value. 182 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff) 183 (Lsh64x64 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 184 (Lsh64x32 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 185 (Lsh64x16 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 186 (Lsh64x8 <t> x y) -> (AND (SLD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 187 188 (Lsh32x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 189 (Lsh32x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 190 (Lsh32x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 191 (Lsh32x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 192 193 (Lsh16x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 194 (Lsh16x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 195 (Lsh16x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 196 (Lsh16x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 197 198 (Lsh8x64 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 199 (Lsh8x32 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 200 (Lsh8x16 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 201 (Lsh8x8 <t> x y) -> (ANDW (SLW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 202 203 (Lrot64 <t> x [c]) -> (RLLGconst <t> [c&63] x) 204 (Lrot32 <t> x [c]) -> (RLLconst <t> [c&31] x) 205 206 (Rsh64Ux64 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPUconst y [63]))) 207 (Rsh64Ux32 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst y [63]))) 208 (Rsh64Ux16 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVHZreg y) [63]))) 209 (Rsh64Ux8 <t> x y) -> (AND (SRD <t> x y) (SUBEcarrymask <t> (CMPWUconst (MOVBZreg y) [63]))) 210 211 (Rsh32Ux64 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPUconst y [31]))) 212 (Rsh32Ux32 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst y [31]))) 213 (Rsh32Ux16 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [31]))) 214 (Rsh32Ux8 <t> x y) -> (ANDW (SRW <t> x y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [31]))) 215 216 (Rsh16Ux64 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [15]))) 217 (Rsh16Ux32 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [15]))) 218 (Rsh16Ux16 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [15]))) 219 (Rsh16Ux8 <t> x y) -> (ANDW (SRW <t> (MOVHZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [15]))) 220 221 (Rsh8Ux64 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPUconst y [7]))) 222 (Rsh8Ux32 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst y [7]))) 223 (Rsh8Ux16 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVHZreg y) [7]))) 224 (Rsh8Ux8 <t> x y) -> (ANDW (SRW <t> (MOVBZreg x) y) (SUBEWcarrymask <t> (CMPWUconst (MOVBZreg y) [7]))) 225 226 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value. 227 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width. 228 (Rsh64x64 <t> x y) -> (SRAD <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [63]))))) 229 (Rsh64x32 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [63]))))) 230 (Rsh64x16 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [63]))))) 231 (Rsh64x8 <t> x y) -> (SRAD <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [63]))))) 232 233 (Rsh32x64 <t> x y) -> (SRAW <t> x (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [31]))))) 234 (Rsh32x32 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [31]))))) 235 (Rsh32x16 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [31]))))) 236 (Rsh32x8 <t> x y) -> (SRAW <t> x (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [31]))))) 237 238 (Rsh16x64 <t> x y) -> (SRAW <t> (MOVHreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [15]))))) 239 (Rsh16x32 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [15]))))) 240 (Rsh16x16 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [15]))))) 241 (Rsh16x8 <t> x y) -> (SRAW <t> (MOVHreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [15]))))) 242 243 (Rsh8x64 <t> x y) -> (SRAW <t> (MOVBreg x) (OR <y.Type> y (NOT <y.Type> (SUBEcarrymask <y.Type> (CMPUconst y [7]))))) 244 (Rsh8x32 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst y [7]))))) 245 (Rsh8x16 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVHZreg y) [7]))))) 246 (Rsh8x8 <t> x y) -> (SRAW <t> (MOVBreg x) (ORW <y.Type> y (NOTW <y.Type> (SUBEWcarrymask <y.Type> (CMPWUconst (MOVBZreg y) [7]))))) 247 248 // Lowering comparisons 249 (Less64 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 250 (Less32 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 251 (Less16 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 252 (Less8 x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 253 (Less64U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 254 (Less32U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 255 (Less16U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 256 (Less8U x y) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 257 // Use SETG with reversed operands to dodge NaN case. 258 (Less64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 259 (Less32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 260 261 (Leq64 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 262 (Leq32 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 263 (Leq16 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 264 (Leq8 x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 265 (Leq64U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 266 (Leq32U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 267 (Leq16U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 268 (Leq8U x y) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 269 // Use SETGE with reversed operands to dodge NaN case. 270 (Leq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP y x)) 271 (Leq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS y x)) 272 273 (Greater64 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 274 (Greater32 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 275 (Greater16 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 276 (Greater8 x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 277 (Greater64U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 278 (Greater32U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 279 (Greater16U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 280 (Greater8U x y) -> (MOVDGT (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 281 (Greater64F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 282 (Greater32F x y) -> (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 283 284 (Geq64 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 285 (Geq32 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 286 (Geq16 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 287 (Geq8 x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 288 (Geq64U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU x y)) 289 (Geq32U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y)) 290 (Geq16U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVHZreg x) (MOVHZreg y))) 291 (Geq8U x y) -> (MOVDGE (MOVDconst [0]) (MOVDconst [1]) (CMPU (MOVBZreg x) (MOVBZreg y))) 292 (Geq64F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 293 (Geq32F x y) -> (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 294 295 (Eq64 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 296 (Eq32 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 297 (Eq16 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 298 (Eq8 x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 299 (EqB x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 300 (EqPtr x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 301 (Eq64F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 302 (Eq32F x y) -> (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 303 304 (Neq64 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 305 (Neq32 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPW x y)) 306 (Neq16 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVHreg x) (MOVHreg y))) 307 (Neq8 x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 308 (NeqB x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP (MOVBreg x) (MOVBreg y))) 309 (NeqPtr x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMP x y)) 310 (Neq64F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMP x y)) 311 (Neq32F x y) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y)) 312 313 // Lowering loads 314 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVDload ptr mem) 315 (Load <t> ptr mem) && is32BitInt(t) -> (MOVWZload ptr mem) 316 (Load <t> ptr mem) && is16BitInt(t) -> (MOVHZload ptr mem) 317 (Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) -> (MOVBZload ptr mem) 318 (Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem) 319 (Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem) 320 321 // Lowering stores 322 // These more-specific FP versions of Store pattern should come first. 323 (Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem) 324 (Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem) 325 326 (Store [8] ptr val mem) -> (MOVDstore ptr val mem) 327 (Store [4] ptr val mem) -> (MOVWstore ptr val mem) 328 (Store [2] ptr val mem) -> (MOVHstore ptr val mem) 329 (Store [1] ptr val mem) -> (MOVBstore ptr val mem) 330 331 // Lowering moves 332 333 // Load and store for small copies. 334 (Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem 335 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBZload src mem) mem) 336 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstore dst (MOVHZload src mem) mem) 337 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstore dst (MOVWZload src mem) mem) 338 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstore dst (MOVDload src mem) mem) 339 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 -> 340 (MOVDstore [8] dst (MOVDload [8] src mem) 341 (MOVDstore dst (MOVDload src mem) mem)) 342 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 -> 343 (MOVDstore [16] dst (MOVDload [16] src mem) 344 (MOVDstore [8] dst (MOVDload [8] src mem) 345 (MOVDstore dst (MOVDload src mem) mem))) 346 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 -> 347 (MOVBstore [2] dst (MOVBZload [2] src mem) 348 (MOVHstore dst (MOVHZload src mem) mem)) 349 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 5 -> 350 (MOVBstore [4] dst (MOVBZload [4] src mem) 351 (MOVWstore dst (MOVWZload src mem) mem)) 352 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 -> 353 (MOVHstore [4] dst (MOVHZload [4] src mem) 354 (MOVWstore dst (MOVWZload src mem) mem)) 355 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 7 -> 356 (MOVBstore [6] dst (MOVBZload [6] src mem) 357 (MOVHstore [4] dst (MOVHZload [4] src mem) 358 (MOVWstore dst (MOVWZload src mem) mem))) 359 360 // MVC for other moves. Use up to 4 instructions (sizes up to 1024 bytes). 361 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 256 -> 362 (MVC [makeValAndOff(SizeAndAlign(s).Size(), 0)] dst src mem) 363 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 256 && SizeAndAlign(s).Size() <= 512 -> 364 (MVC [makeValAndOff(SizeAndAlign(s).Size()-256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)) 365 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 512 && SizeAndAlign(s).Size() <= 768 -> 366 (MVC [makeValAndOff(SizeAndAlign(s).Size()-512, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem))) 367 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 768 && SizeAndAlign(s).Size() <= 1024 -> 368 (MVC [makeValAndOff(SizeAndAlign(s).Size()-768, 768)] dst src (MVC [makeValAndOff(256, 512)] dst src (MVC [makeValAndOff(256, 256)] dst src (MVC [makeValAndOff(256, 0)] dst src mem)))) 369 370 // Move more than 1024 bytes using a loop. 371 (Move [s] dst src mem) && SizeAndAlign(s).Size() > 1024 -> 372 (LoweredMove [SizeAndAlign(s).Size()%256] dst src (ADDconst <src.Type> src [(SizeAndAlign(s).Size()/256)*256]) mem) 373 374 // Lowering Zero instructions 375 (Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem 376 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstoreconst [0] destptr mem) 377 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 2 -> (MOVHstoreconst [0] destptr mem) 378 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 4 -> (MOVWstoreconst [0] destptr mem) 379 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 8 -> (MOVDstoreconst [0] destptr mem) 380 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 3 -> 381 (MOVBstoreconst [makeValAndOff(0,2)] destptr 382 (MOVHstoreconst [0] destptr mem)) 383 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 5 -> 384 (MOVBstoreconst [makeValAndOff(0,4)] destptr 385 (MOVWstoreconst [0] destptr mem)) 386 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 6 -> 387 (MOVHstoreconst [makeValAndOff(0,4)] destptr 388 (MOVWstoreconst [0] destptr mem)) 389 (Zero [s] destptr mem) && SizeAndAlign(s).Size() == 7 -> 390 (MOVWstoreconst [makeValAndOff(0,3)] destptr 391 (MOVWstoreconst [0] destptr mem)) 392 393 (Zero [s] destptr mem) && SizeAndAlign(s).Size() > 0 && SizeAndAlign(s).Size() <= 1024 -> 394 (CLEAR [makeValAndOff(SizeAndAlign(s).Size(), 0)] destptr mem) 395 396 // Move more than 1024 bytes using a loop. 397 (Zero [s] destptr mem) && SizeAndAlign(s).Size() > 1024 -> 398 (LoweredZero [SizeAndAlign(s).Size()%256] destptr (ADDconst <destptr.Type> destptr [(SizeAndAlign(s).Size()/256)*256]) mem) 399 400 // Lowering constants 401 (Const8 [val]) -> (MOVDconst [val]) 402 (Const16 [val]) -> (MOVDconst [val]) 403 (Const32 [val]) -> (MOVDconst [val]) 404 (Const64 [val]) -> (MOVDconst [val]) 405 (Const32F [val]) -> (FMOVSconst [val]) 406 (Const64F [val]) -> (FMOVDconst [val]) 407 (ConstNil) -> (MOVDconst [0]) 408 (ConstBool [b]) -> (MOVDconst [b]) 409 410 // Lowering calls 411 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 412 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 413 (DeferCall [argwid] mem) -> (CALLdefer [argwid] mem) 414 (GoCall [argwid] mem) -> (CALLgo [argwid] mem) 415 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 416 417 // Miscellaneous 418 (Convert <t> x mem) -> (MOVDconvert <t> x mem) 419 (IsNonNil p) -> (MOVDNE (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0])) 420 (IsInBounds idx len) -> (MOVDLT (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 421 (IsSliceInBounds idx len) -> (MOVDLE (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len)) 422 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 423 (GetG mem) -> (LoweredGetG mem) 424 (GetClosurePtr) -> (LoweredGetClosurePtr) 425 (Addr {sym} base) -> (MOVDaddr {sym} base) 426 (ITab (Load ptr mem)) -> (MOVDload ptr mem) 427 428 // block rewrites 429 (If (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LT cmp yes no) 430 (If (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (LE cmp yes no) 431 (If (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GT cmp yes no) 432 (If (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GE cmp yes no) 433 (If (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (EQ cmp yes no) 434 (If (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (NE cmp yes no) 435 436 // Special case for floating point - LF/LEF not generated. 437 (If (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GTF cmp yes no) 438 (If (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp) yes no) -> (GEF cmp yes no) 439 440 (If cond yes no) -> (NE (CMPWconst [0] (MOVBZreg cond)) yes no) 441 442 // *************************** 443 // Above: lowering rules 444 // Below: optimizations 445 // *************************** 446 // TODO: Should the optimizations be a separate pass? 447 448 // Fold sign extensions into conditional moves of constants. 449 // Designed to remove the MOVBZreg inserted by the If lowering. 450 (MOVBZreg x:(MOVDLT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 451 (MOVBZreg x:(MOVDLE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 452 (MOVBZreg x:(MOVDGT (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 453 (MOVBZreg x:(MOVDGE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 454 (MOVBZreg x:(MOVDEQ (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 455 (MOVBZreg x:(MOVDNE (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 456 (MOVBZreg x:(MOVDGTnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 457 (MOVBZreg x:(MOVDGEnoinv (MOVDconst [c]) (MOVDconst [d]) _)) && int64(uint8(c)) == c && int64(uint8(d)) == d -> x 458 459 // Fold boolean tests into blocks. 460 (NE (CMPWconst [0] (MOVDLT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LT cmp yes no) 461 (NE (CMPWconst [0] (MOVDLE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (LE cmp yes no) 462 (NE (CMPWconst [0] (MOVDGT (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GT cmp yes no) 463 (NE (CMPWconst [0] (MOVDGE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GE cmp yes no) 464 (NE (CMPWconst [0] (MOVDEQ (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (EQ cmp yes no) 465 (NE (CMPWconst [0] (MOVDNE (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (NE cmp yes no) 466 (NE (CMPWconst [0] (MOVDGTnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GTF cmp yes no) 467 (NE (CMPWconst [0] (MOVDGEnoinv (MOVDconst [0]) (MOVDconst [1]) cmp)) yes no) -> (GEF cmp yes no) 468 469 // Fold constants into instructions. 470 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x) 471 (ADD (MOVDconst [c]) x) && is32Bit(c) -> (ADDconst [c] x) 472 (ADDW x (MOVDconst [c])) -> (ADDWconst [c] x) 473 (ADDW (MOVDconst [c]) x) -> (ADDWconst [c] x) 474 475 (SUB x (MOVDconst [c])) && is32Bit(c) -> (SUBconst x [c]) 476 (SUB (MOVDconst [c]) x) && is32Bit(c) -> (NEG (SUBconst <v.Type> x [c])) 477 (SUBW x (MOVDconst [c])) -> (SUBWconst x [c]) 478 (SUBW (MOVDconst [c]) x) -> (NEGW (SUBWconst <v.Type> x [c])) 479 480 (MULLD x (MOVDconst [c])) && is32Bit(c) -> (MULLDconst [c] x) 481 (MULLD (MOVDconst [c]) x) && is32Bit(c) -> (MULLDconst [c] x) 482 (MULLW x (MOVDconst [c])) -> (MULLWconst [c] x) 483 (MULLW (MOVDconst [c]) x) -> (MULLWconst [c] x) 484 485 // NILF instructions leave the high 32 bits unchanged which is 486 // equivalent to the leftmost 32 bits being set. 487 // TODO(mundaym): modify the assembler to accept 64-bit values 488 // and use isU32Bit(^c). 489 (AND x (MOVDconst [c])) && is32Bit(c) && c < 0 -> (ANDconst [c] x) 490 (AND (MOVDconst [c]) x) && is32Bit(c) && c < 0 -> (ANDconst [c] x) 491 (ANDW x (MOVDconst [c])) -> (ANDWconst [c] x) 492 (ANDW (MOVDconst [c]) x) -> (ANDWconst [c] x) 493 494 (ANDWconst [c] (ANDWconst [d] x)) -> (ANDWconst [c & d] x) 495 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c & d] x) 496 497 (OR x (MOVDconst [c])) && isU32Bit(c) -> (ORconst [c] x) 498 (OR (MOVDconst [c]) x) && isU32Bit(c) -> (ORconst [c] x) 499 (ORW x (MOVDconst [c])) -> (ORWconst [c] x) 500 (ORW (MOVDconst [c]) x) -> (ORWconst [c] x) 501 502 (XOR x (MOVDconst [c])) && isU32Bit(c) -> (XORconst [c] x) 503 (XOR (MOVDconst [c]) x) && isU32Bit(c) -> (XORconst [c] x) 504 (XORW x (MOVDconst [c])) -> (XORWconst [c] x) 505 (XORW (MOVDconst [c]) x) -> (XORWconst [c] x) 506 507 (SLD x (MOVDconst [c])) -> (SLDconst [c&63] x) 508 (SLW x (MOVDconst [c])) -> (SLWconst [c&63] x) 509 (SRD x (MOVDconst [c])) -> (SRDconst [c&63] x) 510 (SRW x (MOVDconst [c])) -> (SRWconst [c&63] x) 511 (SRAD x (MOVDconst [c])) -> (SRADconst [c&63] x) 512 (SRAW x (MOVDconst [c])) -> (SRAWconst [c&63] x) 513 514 (SRAW x (ANDWconst [63] y)) -> (SRAW x y) 515 (SRAD x (ANDconst [63] y)) -> (SRAD x y) 516 (SLW x (ANDWconst [63] y)) -> (SLW x y) 517 (SLD x (ANDconst [63] y)) -> (SLD x y) 518 (SRW x (ANDWconst [63] y)) -> (SRW x y) 519 (SRD x (ANDconst [63] y)) -> (SRD x y) 520 521 (CMP x (MOVDconst [c])) && is32Bit(c) -> (CMPconst x [c]) 522 (CMP (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPconst x [c])) 523 (CMPW x (MOVDconst [c])) -> (CMPWconst x [c]) 524 (CMPW (MOVDconst [c]) x) -> (InvertFlags (CMPWconst x [c])) 525 (CMPU x (MOVDconst [c])) && is32Bit(c) -> (CMPUconst x [int64(uint32(c))]) 526 (CMPU (MOVDconst [c]) x) && is32Bit(c) -> (InvertFlags (CMPUconst x [int64(uint32(c))])) 527 (CMPWU x (MOVDconst [c])) -> (CMPWUconst x [int64(uint32(c))]) 528 (CMPWU (MOVDconst [c]) x) -> (InvertFlags (CMPWUconst x [int64(uint32(c))])) 529 530 // Using MOV{W,H,B}Zreg instead of AND is cheaper. 531 (AND (MOVDconst [0xFF]) x) -> (MOVBZreg x) 532 (AND x (MOVDconst [0xFF])) -> (MOVBZreg x) 533 (AND (MOVDconst [0xFFFF]) x) -> (MOVHZreg x) 534 (AND x (MOVDconst [0xFFFF])) -> (MOVHZreg x) 535 (AND (MOVDconst [0xFFFFFFFF]) x) -> (MOVWZreg x) 536 (AND x (MOVDconst [0xFFFFFFFF])) -> (MOVWZreg x) 537 (ANDWconst [0xFF] x) -> (MOVBZreg x) 538 (ANDWconst [0xFFFF] x) -> (MOVHZreg x) 539 540 // strength reduction 541 (MULLDconst [-1] x) -> (NEG x) 542 (MULLDconst [0] _) -> (MOVDconst [0]) 543 (MULLDconst [1] x) -> x 544 (MULLDconst [c] x) && isPowerOfTwo(c) -> (SLDconst [log2(c)] x) 545 (MULLDconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUB (SLDconst <v.Type> [log2(c+1)] x) x) 546 (MULLDconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADD (SLDconst <v.Type> [log2(c-1)] x) x) 547 548 (MULLWconst [-1] x) -> (NEGW x) 549 (MULLWconst [0] _) -> (MOVDconst [0]) 550 (MULLWconst [1] x) -> x 551 (MULLWconst [c] x) && isPowerOfTwo(c) -> (SLWconst [log2(c)] x) 552 (MULLWconst [c] x) && isPowerOfTwo(c+1) && c >= 15 -> (SUBW (SLWconst <v.Type> [log2(c+1)] x) x) 553 (MULLWconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADDW (SLWconst <v.Type> [log2(c-1)] x) x) 554 555 // Fold ADD into MOVDaddr. Odd offsets from SB shouldn't be folded (LARL can't handle them). 556 (ADDconst [c] (MOVDaddr [d] {s} x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 557 (MOVDaddr [c] {s} (ADDconst [d] x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 558 (ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 559 (MOVDaddr [c] {s} (ADDconst [d] x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x) 560 (MOVDaddr [c] {s} (ADD x y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y) 561 (ADD x (MOVDaddr [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y) 562 (ADD (MOVDaddr [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y) 563 564 // fold ADDconst into MOVDaddrx 565 (ADDconst [c] (MOVDaddridx [d] {s} x y)) && is32Bit(c+d) -> (MOVDaddridx [c+d] {s} x y) 566 (MOVDaddridx [c] {s} (ADDconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 567 (MOVDaddridx [c] {s} x (ADDconst [d] y)) && is32Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y) 568 569 // reverse ordering of compare instruction 570 (MOVDLT x y (InvertFlags cmp)) -> (MOVDGT x y cmp) 571 (MOVDGT x y (InvertFlags cmp)) -> (MOVDLT x y cmp) 572 (MOVDLE x y (InvertFlags cmp)) -> (MOVDGE x y cmp) 573 (MOVDGE x y (InvertFlags cmp)) -> (MOVDLE x y cmp) 574 (MOVDEQ x y (InvertFlags cmp)) -> (MOVDEQ x y cmp) 575 (MOVDNE x y (InvertFlags cmp)) -> (MOVDNE x y cmp) 576 577 // don't extend after proper load 578 (MOVBreg x:(MOVBload _ _)) -> x 579 (MOVBZreg x:(MOVBZload _ _)) -> x 580 (MOVHreg x:(MOVBload _ _)) -> x 581 (MOVHreg x:(MOVBZload _ _)) -> x 582 (MOVHreg x:(MOVHload _ _)) -> x 583 (MOVHZreg x:(MOVBZload _ _)) -> x 584 (MOVHZreg x:(MOVHZload _ _)) -> x 585 (MOVWreg x:(MOVBload _ _)) -> x 586 (MOVWreg x:(MOVBZload _ _)) -> x 587 (MOVWreg x:(MOVHload _ _)) -> x 588 (MOVWreg x:(MOVHZload _ _)) -> x 589 (MOVWreg x:(MOVWload _ _)) -> x 590 (MOVWZreg x:(MOVBZload _ _)) -> x 591 (MOVWZreg x:(MOVHZload _ _)) -> x 592 (MOVWZreg x:(MOVWZload _ _)) -> x 593 594 // don't extend if argument is already extended 595 (MOVBreg x:(Arg <t>)) && is8BitInt(t) && isSigned(t) -> x 596 (MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !isSigned(t) -> x 597 (MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && isSigned(t) -> x 598 (MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) -> x 599 (MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) -> x 600 (MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) -> x 601 602 // fold double extensions 603 (MOVBreg x:(MOVBreg _)) -> x 604 (MOVBZreg x:(MOVBZreg _)) -> x 605 (MOVHreg x:(MOVBreg _)) -> x 606 (MOVHreg x:(MOVBZreg _)) -> x 607 (MOVHreg x:(MOVHreg _)) -> x 608 (MOVHZreg x:(MOVBZreg _)) -> x 609 (MOVHZreg x:(MOVHZreg _)) -> x 610 (MOVWreg x:(MOVBreg _)) -> x 611 (MOVWreg x:(MOVBZreg _)) -> x 612 (MOVWreg x:(MOVHreg _)) -> x 613 (MOVWreg x:(MOVHreg _)) -> x 614 (MOVWreg x:(MOVWreg _)) -> x 615 (MOVWZreg x:(MOVBZreg _)) -> x 616 (MOVWZreg x:(MOVHZreg _)) -> x 617 (MOVWZreg x:(MOVWZreg _)) -> x 618 619 // fold extensions into constants 620 (MOVBreg (MOVDconst [c])) -> (MOVDconst [int64(int8(c))]) 621 (MOVBZreg (MOVDconst [c])) -> (MOVDconst [int64(uint8(c))]) 622 (MOVHreg (MOVDconst [c])) -> (MOVDconst [int64(int16(c))]) 623 (MOVHZreg (MOVDconst [c])) -> (MOVDconst [int64(uint16(c))]) 624 (MOVWreg (MOVDconst [c])) -> (MOVDconst [int64(int32(c))]) 625 (MOVWZreg (MOVDconst [c])) -> (MOVDconst [int64(uint32(c))]) 626 627 // sign extended loads 628 // Note: The combined instruction must end up in the same block 629 // as the original load. If not, we end up making a value with 630 // memory type live in two different blocks, which can lead to 631 // multiple memory values alive simultaneously. 632 // Make sure we don't combine these ops if the load has another use. 633 // This prevents a single load from being split into multiple loads 634 // which then might return different values. See test/atomicload.go. 635 (MOVBreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem) 636 (MOVBZreg x:(MOVBZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZload <v.Type> [off] {sym} ptr mem) 637 (MOVHreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHload <v.Type> [off] {sym} ptr mem) 638 (MOVHZreg x:(MOVHZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZload <v.Type> [off] {sym} ptr mem) 639 (MOVWreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem) 640 (MOVWZreg x:(MOVWZload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZload <v.Type> [off] {sym} ptr mem) 641 642 (MOVBZreg x:(MOVBZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVBZloadidx <v.Type> [off] {sym} ptr idx mem) 643 (MOVHZreg x:(MOVHZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVHZloadidx <v.Type> [off] {sym} ptr idx mem) 644 (MOVWZreg x:(MOVWZloadidx [off] {sym} ptr idx mem)) && x.Uses == 1 && clobber(x) -> @x.Block (MOVWZloadidx <v.Type> [off] {sym} ptr idx mem) 645 646 // replace load from same location as preceding store with copy 647 (MOVBZload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 648 (MOVHZload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 649 (MOVWZload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 650 (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x 651 652 // Don't extend before storing 653 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 654 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 655 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 656 (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 657 (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 658 (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 659 660 // Fold constants into memory operations. 661 // Note that this is not always a good idea because if not all the uses of 662 // the ADDconst get eliminated, we still have to compute the ADDconst and we now 663 // have potentially two live values (ptr and (ADDconst [off] ptr)) instead of one. 664 // Nevertheless, let's do it! 665 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 666 (MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem) 667 (MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem) 668 (MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem) 669 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem) 670 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem) 671 672 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 673 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 674 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 675 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 676 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem) 677 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem) 678 679 // Fold constants into stores. 680 (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && validValAndOff(c,off) && int64(int16(c)) == c && ptr.Op != OpSB -> 681 (MOVDstoreconst [makeValAndOff(c,off)] {sym} ptr mem) 682 (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && int64(int16(c)) == c && ptr.Op != OpSB -> 683 (MOVWstoreconst [makeValAndOff(int64(int32(c)),off)] {sym} ptr mem) 684 (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && ptr.Op != OpSB -> 685 (MOVHstoreconst [makeValAndOff(int64(int16(c)),off)] {sym} ptr mem) 686 (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) && validOff(off) && ptr.Op != OpSB -> 687 (MOVBstoreconst [makeValAndOff(int64(int8(c)),off)] {sym} ptr mem) 688 689 // Fold address offsets into constant stores. 690 (MOVDstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 691 (MOVDstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 692 (MOVWstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 693 (MOVWstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 694 (MOVHstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 695 (MOVHstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 696 (MOVBstoreconst [sc] {s} (ADDconst [off] ptr) mem) && ValAndOff(sc).canAdd(off) -> 697 (MOVBstoreconst [ValAndOff(sc).add(off)] {s} ptr mem) 698 699 // We need to fold MOVDaddr into the MOVx ops so that the live variable analysis knows 700 // what variables are being read/written by the ops. 701 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 702 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 703 (MOVWZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 704 (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 705 (MOVHZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 706 (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 707 (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 708 (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} base mem) 709 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 710 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} base mem) 711 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 712 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} base mem) 713 714 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 715 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem) 716 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 717 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem) 718 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 719 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem) 720 721 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 722 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 723 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 724 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 725 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 726 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 727 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 728 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 729 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 730 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 731 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} base) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 732 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} base val mem) 733 734 (MOVDstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 735 (MOVDstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 736 (MOVWstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 737 (MOVWstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 738 (MOVHstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 739 (MOVHstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 740 (MOVBstoreconst [sc] {sym1} (MOVDaddr [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) -> 741 (MOVBstoreconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem) 742 743 // generating indexed loads and stores 744 (MOVBZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 745 (MOVBZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 746 (MOVHZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 747 (MOVHZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 748 (MOVWZload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 749 (MOVWZloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 750 (MOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 751 (MOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 752 (FMOVSload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 753 (FMOVSloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 754 (FMOVDload [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 755 (FMOVDloadidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx mem) 756 757 (MOVBstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 758 (MOVBstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 759 (MOVHstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 760 (MOVHstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 761 (MOVWstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 762 (MOVWstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 763 (MOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 764 (MOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 765 (FMOVSstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 766 (FMOVSstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 767 (FMOVDstore [off1] {sym1} (MOVDaddridx [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 768 (FMOVDstoreidx [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem) 769 770 (MOVBZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVBZloadidx [off] {sym} ptr idx mem) 771 (MOVHZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVHZloadidx [off] {sym} ptr idx mem) 772 (MOVWZload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVWZloadidx [off] {sym} ptr idx mem) 773 (MOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (MOVDloadidx [off] {sym} ptr idx mem) 774 (FMOVSload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVSloadidx [off] {sym} ptr idx mem) 775 (FMOVDload [off] {sym} (ADD ptr idx) mem) && ptr.Op != OpSB -> (FMOVDloadidx [off] {sym} ptr idx mem) 776 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVBstoreidx [off] {sym} ptr idx val mem) 777 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVHstoreidx [off] {sym} ptr idx val mem) 778 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVWstoreidx [off] {sym} ptr idx val mem) 779 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (MOVDstoreidx [off] {sym} ptr idx val mem) 780 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVSstoreidx [off] {sym} ptr idx val mem) 781 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && ptr.Op != OpSB -> (FMOVDstoreidx [off] {sym} ptr idx val mem) 782 783 // combine ADD into indexed loads and stores 784 (MOVBZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 785 (MOVHZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 786 (MOVWZloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 787 (MOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 788 (FMOVSloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 789 (FMOVDloadidx [c] {sym} (ADDconst [d] ptr) idx mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 790 791 (MOVBstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 792 (MOVHstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 793 (MOVWstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 794 (MOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 795 (FMOVSstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 796 (FMOVDstoreidx [c] {sym} (ADDconst [d] ptr) idx val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 797 798 (MOVBZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVBZloadidx [c+d] {sym} ptr idx mem) 799 (MOVHZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVHZloadidx [c+d] {sym} ptr idx mem) 800 (MOVWZloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVWZloadidx [c+d] {sym} ptr idx mem) 801 (MOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (MOVDloadidx [c+d] {sym} ptr idx mem) 802 (FMOVSloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVSloadidx [c+d] {sym} ptr idx mem) 803 (FMOVDloadidx [c] {sym} ptr (ADDconst [d] idx) mem) -> (FMOVDloadidx [c+d] {sym} ptr idx mem) 804 805 (MOVBstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVBstoreidx [c+d] {sym} ptr idx val mem) 806 (MOVHstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVHstoreidx [c+d] {sym} ptr idx val mem) 807 (MOVWstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVWstoreidx [c+d] {sym} ptr idx val mem) 808 (MOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (MOVDstoreidx [c+d] {sym} ptr idx val mem) 809 (FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem) 810 (FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem) 811 812 // fold MOVDaddrs together 813 (MOVDaddr [off1] {sym1} (MOVDaddr [off2] {sym2} x)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 814 (MOVDaddr [off1+off2] {mergeSym(sym1,sym2)} x) 815 816 // MOVDaddr into MOVDaddridx 817 (MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB -> 818 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 819 (MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB -> 820 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 821 822 // MOVDaddridx into MOVDaddr 823 (MOVDaddr [off1] {sym1} (MOVDaddridx [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) -> 824 (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y) 825 826 // Absorb InvertFlags into branches. 827 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 828 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 829 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 830 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 831 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 832 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 833 834 // Constant comparisons. 835 (CMPconst (MOVDconst [x]) [y]) && x==y -> (FlagEQ) 836 (CMPconst (MOVDconst [x]) [y]) && x<y -> (FlagLT) 837 (CMPconst (MOVDconst [x]) [y]) && x>y -> (FlagGT) 838 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)==uint64(y) -> (FlagEQ) 839 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) -> (FlagLT) 840 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) -> (FlagGT) 841 842 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 843 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) -> (FlagLT) 844 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) -> (FlagGT) 845 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)==uint32(y) -> (FlagEQ) 846 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) -> (FlagLT) 847 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) -> (FlagGT) 848 849 // Other known comparisons. 850 (CMPconst (MOVBZreg _) [c]) && 0xFF < c -> (FlagLT) 851 (CMPconst (MOVHZreg _) [c]) && 0xFFFF < c -> (FlagLT) 852 (CMPconst (MOVWZreg _) [c]) && 0xFFFFFFFF < c -> (FlagLT) 853 (CMPWconst (SRWconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) -> (FlagLT) 854 (CMPconst (SRDconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) -> (FlagLT) 855 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n -> (FlagLT) 856 (CMPWconst (ANDWconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT) 857 858 // Absorb flag constants into SBB ops. 859 (SUBEcarrymask (FlagEQ)) -> (MOVDconst [-1]) 860 (SUBEcarrymask (FlagLT)) -> (MOVDconst [-1]) 861 (SUBEcarrymask (FlagGT)) -> (MOVDconst [0]) 862 (SUBEWcarrymask (FlagEQ)) -> (MOVDconst [-1]) 863 (SUBEWcarrymask (FlagLT)) -> (MOVDconst [-1]) 864 (SUBEWcarrymask (FlagGT)) -> (MOVDconst [0]) 865 866 // Absorb flag constants into branches. 867 (EQ (FlagEQ) yes no) -> (First nil yes no) 868 (EQ (FlagLT) yes no) -> (First nil no yes) 869 (EQ (FlagGT) yes no) -> (First nil no yes) 870 871 (NE (FlagEQ) yes no) -> (First nil no yes) 872 (NE (FlagLT) yes no) -> (First nil yes no) 873 (NE (FlagGT) yes no) -> (First nil yes no) 874 875 (LT (FlagEQ) yes no) -> (First nil no yes) 876 (LT (FlagLT) yes no) -> (First nil yes no) 877 (LT (FlagGT) yes no) -> (First nil no yes) 878 879 (LE (FlagEQ) yes no) -> (First nil yes no) 880 (LE (FlagLT) yes no) -> (First nil yes no) 881 (LE (FlagGT) yes no) -> (First nil no yes) 882 883 (GT (FlagEQ) yes no) -> (First nil no yes) 884 (GT (FlagLT) yes no) -> (First nil no yes) 885 (GT (FlagGT) yes no) -> (First nil yes no) 886 887 (GE (FlagEQ) yes no) -> (First nil yes no) 888 (GE (FlagLT) yes no) -> (First nil no yes) 889 (GE (FlagGT) yes no) -> (First nil yes no) 890 891 // Absorb flag constants into SETxx ops. 892 (MOVDEQ _ x (FlagEQ)) -> x 893 (MOVDEQ y _ (FlagLT)) -> y 894 (MOVDEQ y _ (FlagGT)) -> y 895 896 (MOVDNE _ y (FlagEQ)) -> y 897 (MOVDNE x _ (FlagLT)) -> x 898 (MOVDNE x _ (FlagGT)) -> x 899 900 (MOVDLT y _ (FlagEQ)) -> y 901 (MOVDLT _ x (FlagLT)) -> x 902 (MOVDLT y _ (FlagGT)) -> y 903 904 (MOVDLE _ x (FlagEQ)) -> x 905 (MOVDLE _ x (FlagLT)) -> x 906 (MOVDLE y _ (FlagGT)) -> y 907 908 (MOVDGT y _ (FlagEQ)) -> y 909 (MOVDGT y _ (FlagLT)) -> y 910 (MOVDGT _ x (FlagGT)) -> x 911 912 (MOVDGE _ x (FlagEQ)) -> x 913 (MOVDGE y _ (FlagLT)) -> y 914 (MOVDGE _ x (FlagGT)) -> x 915 916 // Remove redundant *const ops 917 (ADDconst [0] x) -> x 918 (ADDWconst [c] x) && int32(c)==0 -> x 919 (SUBconst [0] x) -> x 920 (SUBWconst [c] x) && int32(c) == 0 -> x 921 (ANDconst [0] _) -> (MOVDconst [0]) 922 (ANDWconst [c] _) && int32(c)==0 -> (MOVDconst [0]) 923 (ANDconst [-1] x) -> x 924 (ANDWconst [c] x) && int32(c)==-1 -> x 925 (ORconst [0] x) -> x 926 (ORWconst [c] x) && int32(c)==0 -> x 927 (ORconst [-1] _) -> (MOVDconst [-1]) 928 (ORWconst [c] _) && int32(c)==-1 -> (MOVDconst [-1]) 929 (XORconst [0] x) -> x 930 (XORWconst [c] x) && int32(c)==0 -> x 931 932 // Convert constant subtracts to constant adds. 933 (SUBconst [c] x) && c != -(1<<31) -> (ADDconst [-c] x) 934 (SUBWconst [c] x) -> (ADDWconst [int64(int32(-c))] x) 935 936 // generic constant folding 937 // TODO: more of this 938 (ADDconst [c] (MOVDconst [d])) -> (MOVDconst [c+d]) 939 (ADDWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c+d))]) 940 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) -> (ADDconst [c+d] x) 941 (ADDWconst [c] (ADDWconst [d] x)) -> (ADDWconst [int64(int32(c+d))] x) 942 (SUBconst (MOVDconst [d]) [c]) -> (MOVDconst [d-c]) 943 (SUBconst (SUBconst x [d]) [c]) && is32Bit(-c-d) -> (ADDconst [-c-d] x) 944 (SRADconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 945 (SRAWconst [c] (MOVDconst [d])) -> (MOVDconst [d>>uint64(c)]) 946 (NEG (MOVDconst [c])) -> (MOVDconst [-c]) 947 (NEGW (MOVDconst [c])) -> (MOVDconst [int64(int32(-c))]) 948 (MULLDconst [c] (MOVDconst [d])) -> (MOVDconst [c*d]) 949 (MULLWconst [c] (MOVDconst [d])) -> (MOVDconst [int64(int32(c*d))]) 950 (AND (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c&d]) 951 (ANDconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 952 (ANDWconst [c] (MOVDconst [d])) -> (MOVDconst [c&d]) 953 (OR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c|d]) 954 (ORconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 955 (ORWconst [c] (MOVDconst [d])) -> (MOVDconst [c|d]) 956 (XOR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c^d]) 957 (XORconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 958 (XORWconst [c] (MOVDconst [d])) -> (MOVDconst [c^d]) 959 960 // generic simplifications 961 // TODO: more of this 962 (ADD x (NEG y)) -> (SUB x y) 963 (ADDW x (NEGW y)) -> (SUBW x y) 964 (SUB x x) -> (MOVDconst [0]) 965 (SUBW x x) -> (MOVDconst [0]) 966 (AND x x) -> x 967 (ANDW x x) -> x 968 (OR x x) -> x 969 (ORW x x) -> x 970 (XOR x x) -> (MOVDconst [0]) 971 (XORW x x) -> (MOVDconst [0]) 972 973 // Fold memory operations into operations. 974 // Exclude global data (SB) because these instructions cannot handle relative addresses. 975 // TODO(mundaym): use LARL in the assembler to handle SB? 976 // TODO(mundaym): indexed versions of these? 977 (ADD <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 978 -> (ADDload <t> [off] {sym} x ptr mem) 979 (ADD <t> g:(MOVDload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 980 -> (ADDload <t> [off] {sym} x ptr mem) 981 (ADDW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 982 -> (ADDWload <t> [off] {sym} x ptr mem) 983 (ADDW <t> g:(MOVWload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 984 -> (ADDWload <t> [off] {sym} x ptr mem) 985 (ADDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 986 -> (ADDWload <t> [off] {sym} x ptr mem) 987 (ADDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 988 -> (ADDWload <t> [off] {sym} x ptr mem) 989 (MULLD <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 990 -> (MULLDload <t> [off] {sym} x ptr mem) 991 (MULLD <t> g:(MOVDload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 992 -> (MULLDload <t> [off] {sym} x ptr mem) 993 (MULLW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 994 -> (MULLWload <t> [off] {sym} x ptr mem) 995 (MULLW <t> g:(MOVWload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 996 -> (MULLWload <t> [off] {sym} x ptr mem) 997 (MULLW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 998 -> (MULLWload <t> [off] {sym} x ptr mem) 999 (MULLW <t> g:(MOVWZload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1000 -> (MULLWload <t> [off] {sym} x ptr mem) 1001 (SUB <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1002 -> (SUBload <t> [off] {sym} x ptr mem) 1003 (SUBW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1004 -> (SUBWload <t> [off] {sym} x ptr mem) 1005 (SUBW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1006 -> (SUBWload <t> [off] {sym} x ptr mem) 1007 (AND <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1008 -> (ANDload <t> [off] {sym} x ptr mem) 1009 (AND <t> g:(MOVDload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1010 -> (ANDload <t> [off] {sym} x ptr mem) 1011 (ANDW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1012 -> (ANDWload <t> [off] {sym} x ptr mem) 1013 (ANDW <t> g:(MOVWload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1014 -> (ANDWload <t> [off] {sym} x ptr mem) 1015 (ANDW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1016 -> (ANDWload <t> [off] {sym} x ptr mem) 1017 (ANDW <t> g:(MOVWZload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1018 -> (ANDWload <t> [off] {sym} x ptr mem) 1019 (OR <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1020 -> (ORload <t> [off] {sym} x ptr mem) 1021 (OR <t> g:(MOVDload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1022 -> (ORload <t> [off] {sym} x ptr mem) 1023 (ORW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1024 -> (ORWload <t> [off] {sym} x ptr mem) 1025 (ORW <t> g:(MOVWload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1026 -> (ORWload <t> [off] {sym} x ptr mem) 1027 (ORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1028 -> (ORWload <t> [off] {sym} x ptr mem) 1029 (ORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1030 -> (ORWload <t> [off] {sym} x ptr mem) 1031 (XOR <t> x g:(MOVDload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1032 -> (XORload <t> [off] {sym} x ptr mem) 1033 (XOR <t> g:(MOVDload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1034 -> (XORload <t> [off] {sym} x ptr mem) 1035 (XORW <t> x g:(MOVWload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1036 -> (XORWload <t> [off] {sym} x ptr mem) 1037 (XORW <t> g:(MOVWload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1038 -> (XORWload <t> [off] {sym} x ptr mem) 1039 (XORW <t> x g:(MOVWZload [off] {sym} ptr mem)) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1040 -> (XORWload <t> [off] {sym} x ptr mem) 1041 (XORW <t> g:(MOVWZload [off] {sym} ptr mem) x) && g.Uses == 1 && ptr.Op != OpSB && is20Bit(off) && canMergeLoad(v, g) && clobber(g) 1042 -> (XORWload <t> [off] {sym} x ptr mem) 1043 1044 // Combine constant stores into larger (unaligned) stores. 1045 // It doesn't work to global data (based on SB), 1046 // because STGRL doesn't support unaligned address 1047 (MOVBstoreconst [c] {s} p x:(MOVBstoreconst [a] {s} p mem)) 1048 && p.Op != OpSB 1049 && x.Uses == 1 1050 && ValAndOff(a).Off() + 1 == ValAndOff(c).Off() 1051 && clobber(x) 1052 -> (MOVHstoreconst [makeValAndOff(ValAndOff(c).Val()&0xff | ValAndOff(a).Val()<<8, ValAndOff(a).Off())] {s} p mem) 1053 (MOVHstoreconst [c] {s} p x:(MOVHstoreconst [a] {s} p mem)) 1054 && p.Op != OpSB 1055 && x.Uses == 1 1056 && ValAndOff(a).Off() + 2 == ValAndOff(c).Off() 1057 && clobber(x) 1058 -> (MOVWstoreconst [makeValAndOff(ValAndOff(c).Val()&0xffff | ValAndOff(a).Val()<<16, ValAndOff(a).Off())] {s} p mem) 1059 (MOVWstoreconst [c] {s} p x:(MOVWstoreconst [a] {s} p mem)) 1060 && p.Op != OpSB 1061 && x.Uses == 1 1062 && ValAndOff(a).Off() + 4 == ValAndOff(c).Off() 1063 && clobber(x) 1064 -> (MOVDstore [ValAndOff(a).Off()] {s} p (MOVDconst [ValAndOff(c).Val()&0xffffffff | ValAndOff(a).Val()<<32]) mem) 1065 1066 // Combine stores into larger (unaligned) stores. 1067 // It doesn't work on global data (based on SB) because stores with relative addressing 1068 // require that the memory operand be aligned. 1069 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRDconst [8] w) mem)) 1070 && p.Op != OpSB 1071 && x.Uses == 1 1072 && clobber(x) 1073 -> (MOVHstore [i-1] {s} p w mem) 1074 (MOVBstore [i] {s} p w0:(SRDconst [j] w) x:(MOVBstore [i-1] {s} p (SRDconst [j+8] w) mem)) 1075 && p.Op != OpSB 1076 && x.Uses == 1 1077 && clobber(x) 1078 -> (MOVHstore [i-1] {s} p w0 mem) 1079 (MOVBstore [i] {s} p w x:(MOVBstore [i-1] {s} p (SRWconst [8] w) mem)) 1080 && p.Op != OpSB 1081 && x.Uses == 1 1082 && clobber(x) 1083 -> (MOVHstore [i-1] {s} p w mem) 1084 (MOVBstore [i] {s} p w0:(SRWconst [j] w) x:(MOVBstore [i-1] {s} p (SRWconst [j+8] w) mem)) 1085 && p.Op != OpSB 1086 && x.Uses == 1 1087 && clobber(x) 1088 -> (MOVHstore [i-1] {s} p w0 mem) 1089 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRDconst [16] w) mem)) 1090 && p.Op != OpSB 1091 && x.Uses == 1 1092 && clobber(x) 1093 -> (MOVWstore [i-2] {s} p w mem) 1094 (MOVHstore [i] {s} p w0:(SRDconst [j] w) x:(MOVHstore [i-2] {s} p (SRDconst [j+16] w) mem)) 1095 && p.Op != OpSB 1096 && x.Uses == 1 1097 && clobber(x) 1098 -> (MOVWstore [i-2] {s} p w0 mem) 1099 (MOVHstore [i] {s} p w x:(MOVHstore [i-2] {s} p (SRWconst [16] w) mem)) 1100 && p.Op != OpSB 1101 && x.Uses == 1 1102 && clobber(x) 1103 -> (MOVWstore [i-2] {s} p w mem) 1104 (MOVHstore [i] {s} p w0:(SRWconst [j] w) x:(MOVHstore [i-2] {s} p (SRWconst [j+16] w) mem)) 1105 && p.Op != OpSB 1106 && x.Uses == 1 1107 && clobber(x) 1108 -> (MOVWstore [i-2] {s} p w0 mem) 1109 (MOVWstore [i] {s} p (SRDconst [32] w) x:(MOVWstore [i-4] {s} p w mem)) 1110 && p.Op != OpSB 1111 && x.Uses == 1 1112 && clobber(x) 1113 -> (MOVDstore [i-4] {s} p w mem) 1114 (MOVWstore [i] {s} p w0:(SRDconst [j] w) x:(MOVWstore [i-4] {s} p (SRDconst [j+32] w) mem)) 1115 && p.Op != OpSB 1116 && x.Uses == 1 1117 && clobber(x) 1118 -> (MOVDstore [i-4] {s} p w0 mem) 1119 1120 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [8] w) mem)) 1121 && x.Uses == 1 1122 && clobber(x) 1123 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1124 (MOVBstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRDconst [j+8] w) mem)) 1125 && x.Uses == 1 1126 && clobber(x) 1127 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1128 (MOVBstoreidx [i] {s} p idx w x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [8] w) mem)) 1129 && x.Uses == 1 1130 && clobber(x) 1131 -> (MOVHstoreidx [i-1] {s} p idx w mem) 1132 (MOVBstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx (SRWconst [j+8] w) mem)) 1133 && x.Uses == 1 1134 && clobber(x) 1135 -> (MOVHstoreidx [i-1] {s} p idx w0 mem) 1136 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [16] w) mem)) 1137 && x.Uses == 1 1138 && clobber(x) 1139 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1140 (MOVHstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRDconst [j+16] w) mem)) 1141 && x.Uses == 1 1142 && clobber(x) 1143 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1144 (MOVHstoreidx [i] {s} p idx w x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [16] w) mem)) 1145 && x.Uses == 1 1146 && clobber(x) 1147 -> (MOVWstoreidx [i-2] {s} p idx w mem) 1148 (MOVHstoreidx [i] {s} p idx w0:(SRWconst [j] w) x:(MOVHstoreidx [i-2] {s} p idx (SRWconst [j+16] w) mem)) 1149 && x.Uses == 1 1150 && clobber(x) 1151 -> (MOVWstoreidx [i-2] {s} p idx w0 mem) 1152 (MOVWstoreidx [i] {s} p idx w x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [32] w) mem)) 1153 && x.Uses == 1 1154 && clobber(x) 1155 -> (MOVDstoreidx [i-4] {s} p idx w mem) 1156 (MOVWstoreidx [i] {s} p idx w0:(SRDconst [j] w) x:(MOVWstoreidx [i-4] {s} p idx (SRDconst [j+32] w) mem)) 1157 && x.Uses == 1 1158 && clobber(x) 1159 -> (MOVDstoreidx [i-4] {s} p idx w0 mem) 1160 1161 // Combine stores into larger (unaligned) stores with the bytes reversed (little endian). 1162 // Store-with-bytes-reversed instructions do not support relative memory addresses, 1163 // so these stores can't operate on global data (SB). 1164 (MOVBstore [i] {s} p (SRDconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1165 && p.Op != OpSB 1166 && x.Uses == 1 1167 && clobber(x) 1168 -> (MOVHBRstore [i-1] {s} p w mem) 1169 (MOVBstore [i] {s} p (SRDconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRDconst [j-8] w) mem)) 1170 && p.Op != OpSB 1171 && x.Uses == 1 1172 && clobber(x) 1173 -> (MOVHBRstore [i-1] {s} p w0 mem) 1174 (MOVBstore [i] {s} p (SRWconst [8] w) x:(MOVBstore [i-1] {s} p w mem)) 1175 && p.Op != OpSB 1176 && x.Uses == 1 1177 && clobber(x) 1178 -> (MOVHBRstore [i-1] {s} p w mem) 1179 (MOVBstore [i] {s} p (SRWconst [j] w) x:(MOVBstore [i-1] {s} p w0:(SRWconst [j-8] w) mem)) 1180 && p.Op != OpSB 1181 && x.Uses == 1 1182 && clobber(x) 1183 -> (MOVHBRstore [i-1] {s} p w0 mem) 1184 (MOVHBRstore [i] {s} p (SRDconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1185 && x.Uses == 1 1186 && clobber(x) 1187 -> (MOVWBRstore [i-2] {s} p w mem) 1188 (MOVHBRstore [i] {s} p (SRDconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRDconst [j-16] w) mem)) 1189 && x.Uses == 1 1190 && clobber(x) 1191 -> (MOVWBRstore [i-2] {s} p w0 mem) 1192 (MOVHBRstore [i] {s} p (SRWconst [16] w) x:(MOVHBRstore [i-2] {s} p w mem)) 1193 && x.Uses == 1 1194 && clobber(x) 1195 -> (MOVWBRstore [i-2] {s} p w mem) 1196 (MOVHBRstore [i] {s} p (SRWconst [j] w) x:(MOVHBRstore [i-2] {s} p w0:(SRWconst [j-16] w) mem)) 1197 && x.Uses == 1 1198 && clobber(x) 1199 -> (MOVWBRstore [i-2] {s} p w0 mem) 1200 (MOVWBRstore [i] {s} p (SRDconst [32] w) x:(MOVWBRstore [i-4] {s} p w mem)) 1201 && x.Uses == 1 1202 && clobber(x) 1203 -> (MOVDBRstore [i-4] {s} p w mem) 1204 (MOVWBRstore [i] {s} p (SRDconst [j] w) x:(MOVWBRstore [i-4] {s} p w0:(SRDconst [j-32] w) mem)) 1205 && x.Uses == 1 1206 && clobber(x) 1207 -> (MOVDBRstore [i-4] {s} p w0 mem) 1208 1209 (MOVBstoreidx [i] {s} p idx (SRDconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1210 && x.Uses == 1 1211 && clobber(x) 1212 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1213 (MOVBstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRDconst [j-8] w) mem)) 1214 && x.Uses == 1 1215 && clobber(x) 1216 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1217 (MOVBstoreidx [i] {s} p idx (SRWconst [8] w) x:(MOVBstoreidx [i-1] {s} p idx w mem)) 1218 && x.Uses == 1 1219 && clobber(x) 1220 -> (MOVHBRstoreidx [i-1] {s} p idx w mem) 1221 (MOVBstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVBstoreidx [i-1] {s} p idx w0:(SRWconst [j-8] w) mem)) 1222 && x.Uses == 1 1223 && clobber(x) 1224 -> (MOVHBRstoreidx [i-1] {s} p idx w0 mem) 1225 (MOVHBRstoreidx [i] {s} p idx (SRDconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1226 && x.Uses == 1 1227 && clobber(x) 1228 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1229 (MOVHBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRDconst [j-16] w) mem)) 1230 && x.Uses == 1 1231 && clobber(x) 1232 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1233 (MOVHBRstoreidx [i] {s} p idx (SRWconst [16] w) x:(MOVHBRstoreidx [i-2] {s} p idx w mem)) 1234 && x.Uses == 1 1235 && clobber(x) 1236 -> (MOVWBRstoreidx [i-2] {s} p idx w mem) 1237 (MOVHBRstoreidx [i] {s} p idx (SRWconst [j] w) x:(MOVHBRstoreidx [i-2] {s} p idx w0:(SRWconst [j-16] w) mem)) 1238 && x.Uses == 1 1239 && clobber(x) 1240 -> (MOVWBRstoreidx [i-2] {s} p idx w0 mem) 1241 (MOVWBRstoreidx [i] {s} p idx (SRDconst [32] w) x:(MOVWBRstoreidx [i-4] {s} p idx w mem)) 1242 && x.Uses == 1 1243 && clobber(x) 1244 -> (MOVDBRstoreidx [i-4] {s} p idx w mem) 1245 (MOVWBRstoreidx [i] {s} p idx (SRDconst [j] w) x:(MOVWBRstoreidx [i-4] {s} p idx w0:(SRDconst [j-32] w) mem)) 1246 && x.Uses == 1 1247 && clobber(x) 1248 -> (MOVDBRstoreidx [i-4] {s} p idx w0 mem) 1249 1250 // Combining byte loads into larger (unaligned) loads. 1251 1252 // Little endian loads. 1253 1254 // b[0] | b[1]<<8 -> load 16-bit, reverse bytes 1255 (ORW x0:(MOVBZload [i] {s} p mem) 1256 s0:(SLWconst [8] x1:(MOVBZload [i+1] {s} p mem))) 1257 && p.Op != OpSB 1258 && x0.Uses == 1 1259 && x1.Uses == 1 1260 && s0.Uses == 1 1261 && mergePoint(b,x0,x1) != nil 1262 && clobber(x0) 1263 && clobber(x1) 1264 && clobber(s0) 1265 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRload [i] {s} p mem)) 1266 1267 // b[0] | b[1]<<8 | b[2]<<16 | b[3]<<24 -> load 32-bit, reverse bytes 1268 (ORW o0:(ORW z0:(MOVHZreg x0:(MOVHBRload [i] {s} p mem)) 1269 s0:(SLWconst [16] x1:(MOVBZload [i+2] {s} p mem))) 1270 s1:(SLWconst [24] x2:(MOVBZload [i+3] {s} p mem))) 1271 && p.Op != OpSB 1272 && z0.Uses == 1 1273 && x0.Uses == 1 1274 && x1.Uses == 1 1275 && x2.Uses == 1 1276 && s0.Uses == 1 1277 && s1.Uses == 1 1278 && o0.Uses == 1 1279 && mergePoint(b,x0,x1,x2) != nil 1280 && clobber(z0) 1281 && clobber(x0) 1282 && clobber(x1) 1283 && clobber(x2) 1284 && clobber(s0) 1285 && clobber(s1) 1286 && clobber(o0) 1287 -> @mergePoint(b,x0,x1,x2) (MOVWBRload [i] {s} p mem) 1288 1289 // b[0] | b[1]<<8 | b[2]<<16 | b[3]<<24 | b[4]<<32 | b[5]<<40 | b[6]<<48 | b[7]<<56 -> load 64-bit, reverse bytes 1290 (OR o0:(OR o1:(OR o2:(OR o3:(OR o4:(OR o5:(OR 1291 x0:(MOVBZload [i] {s} p mem) 1292 s0:(SLDconst [8] x1:(MOVBZload [i+1] {s} p mem))) 1293 s1:(SLDconst [16] x2:(MOVBZload [i+2] {s} p mem))) 1294 s2:(SLDconst [24] x3:(MOVBZload [i+3] {s} p mem))) 1295 s3:(SLDconst [32] x4:(MOVBZload [i+4] {s} p mem))) 1296 s4:(SLDconst [40] x5:(MOVBZload [i+5] {s} p mem))) 1297 s5:(SLDconst [48] x6:(MOVBZload [i+6] {s} p mem))) 1298 s6:(SLDconst [56] x7:(MOVBZload [i+7] {s} p mem))) 1299 && p.Op != OpSB 1300 && x0.Uses == 1 1301 && x1.Uses == 1 1302 && x2.Uses == 1 1303 && x3.Uses == 1 1304 && x4.Uses == 1 1305 && x5.Uses == 1 1306 && x6.Uses == 1 1307 && x7.Uses == 1 1308 && s0.Uses == 1 1309 && s1.Uses == 1 1310 && s2.Uses == 1 1311 && s3.Uses == 1 1312 && s4.Uses == 1 1313 && s5.Uses == 1 1314 && s6.Uses == 1 1315 && o0.Uses == 1 1316 && o1.Uses == 1 1317 && o2.Uses == 1 1318 && o3.Uses == 1 1319 && o4.Uses == 1 1320 && o5.Uses == 1 1321 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1322 && clobber(x0) 1323 && clobber(x1) 1324 && clobber(x2) 1325 && clobber(x3) 1326 && clobber(x4) 1327 && clobber(x5) 1328 && clobber(x6) 1329 && clobber(x7) 1330 && clobber(s0) 1331 && clobber(s1) 1332 && clobber(s2) 1333 && clobber(s3) 1334 && clobber(s4) 1335 && clobber(s5) 1336 && clobber(s6) 1337 && clobber(o0) 1338 && clobber(o1) 1339 && clobber(o2) 1340 && clobber(o3) 1341 && clobber(o4) 1342 && clobber(o5) 1343 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDBRload [i] {s} p mem) 1344 1345 // b[0] | b[1]<<8 -> load 16-bit, reverse bytes 1346 (ORW x0:(MOVBZloadidx [i] {s} p idx mem) 1347 s0:(SLWconst [8] x1:(MOVBZloadidx [i+1] {s} p idx mem))) 1348 && x0.Uses == 1 1349 && x1.Uses == 1 1350 && s0.Uses == 1 1351 && mergePoint(b,x0,x1) != nil 1352 && clobber(x0) 1353 && clobber(x1) 1354 && clobber(s0) 1355 -> @mergePoint(b,x0,x1) (MOVHZreg (MOVHBRloadidx <v.Type> [i] {s} p idx mem)) 1356 1357 // b[0] | b[1]<<8 | b[2]<<16 | b[3]<<24 -> load 32-bit, reverse bytes 1358 (ORW o0:(ORW z0:(MOVHZreg x0:(MOVHBRloadidx [i] {s} p idx mem)) 1359 s0:(SLWconst [16] x1:(MOVBZloadidx [i+2] {s} p idx mem))) 1360 s1:(SLWconst [24] x2:(MOVBZloadidx [i+3] {s} p idx mem))) 1361 && z0.Uses == 1 1362 && x0.Uses == 1 1363 && x1.Uses == 1 1364 && x2.Uses == 1 1365 && s0.Uses == 1 1366 && s1.Uses == 1 1367 && o0.Uses == 1 1368 && mergePoint(b,x0,x1,x2) != nil 1369 && clobber(z0) 1370 && clobber(x0) 1371 && clobber(x1) 1372 && clobber(x2) 1373 && clobber(s0) 1374 && clobber(s1) 1375 && clobber(o0) 1376 -> @mergePoint(b,x0,x1,x2) (MOVWZreg (MOVWBRloadidx <v.Type> [i] {s} p idx mem)) 1377 1378 // b[0] | b[1]<<8 | b[2]<<16 | b[3]<<24 | b[4]<<32 | b[5]<<40 | b[6]<<48 | b[7]<<56 -> load 64-bit, reverse bytes 1379 (OR o0:(OR o1:(OR o2:(OR o3:(OR o4:(OR o5:(OR 1380 x0:(MOVBZloadidx [i] {s} p idx mem) 1381 s0:(SLDconst [8] x1:(MOVBZloadidx [i+1] {s} p idx mem))) 1382 s1:(SLDconst [16] x2:(MOVBZloadidx [i+2] {s} p idx mem))) 1383 s2:(SLDconst [24] x3:(MOVBZloadidx [i+3] {s} p idx mem))) 1384 s3:(SLDconst [32] x4:(MOVBZloadidx [i+4] {s} p idx mem))) 1385 s4:(SLDconst [40] x5:(MOVBZloadidx [i+5] {s} p idx mem))) 1386 s5:(SLDconst [48] x6:(MOVBZloadidx [i+6] {s} p idx mem))) 1387 s6:(SLDconst [56] x7:(MOVBZloadidx [i+7] {s} p idx mem))) 1388 && x0.Uses == 1 1389 && x1.Uses == 1 1390 && x2.Uses == 1 1391 && x3.Uses == 1 1392 && x4.Uses == 1 1393 && x5.Uses == 1 1394 && x6.Uses == 1 1395 && x7.Uses == 1 1396 && s0.Uses == 1 1397 && s1.Uses == 1 1398 && s2.Uses == 1 1399 && s3.Uses == 1 1400 && s4.Uses == 1 1401 && s5.Uses == 1 1402 && s6.Uses == 1 1403 && o0.Uses == 1 1404 && o1.Uses == 1 1405 && o2.Uses == 1 1406 && o3.Uses == 1 1407 && o4.Uses == 1 1408 && o5.Uses == 1 1409 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1410 && clobber(x0) 1411 && clobber(x1) 1412 && clobber(x2) 1413 && clobber(x3) 1414 && clobber(x4) 1415 && clobber(x5) 1416 && clobber(x6) 1417 && clobber(x7) 1418 && clobber(s0) 1419 && clobber(s1) 1420 && clobber(s2) 1421 && clobber(s3) 1422 && clobber(s4) 1423 && clobber(s5) 1424 && clobber(s6) 1425 && clobber(o0) 1426 && clobber(o1) 1427 && clobber(o2) 1428 && clobber(o3) 1429 && clobber(o4) 1430 && clobber(o5) 1431 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDBRloadidx <v.Type> [i] {s} p idx mem) 1432 1433 // Big endian loads. 1434 1435 // b[1] | b[0]<<8 -> load 16-bit 1436 (ORW x0:(MOVBZload [i] {s} p mem) 1437 s0:(SLWconst [8] x1:(MOVBZload [i-1] {s} p mem))) 1438 && p.Op != OpSB 1439 && x0.Uses == 1 1440 && x1.Uses == 1 1441 && s0.Uses == 1 1442 && mergePoint(b,x0,x1) != nil 1443 && clobber(x0) 1444 && clobber(x1) 1445 && clobber(s0) 1446 -> @mergePoint(b,x0,x1) (MOVHZload [i-1] {s} p mem) 1447 1448 // b[3] | b[2]<<8 | b[1]<<16 | b[0]<<24 -> load 32-bit 1449 (ORW o0:(ORW x0:(MOVHZload [i] {s} p mem) 1450 s0:(SLWconst [16] x1:(MOVBZload [i-1] {s} p mem))) 1451 s1:(SLWconst [24] x2:(MOVBZload [i-2] {s} p mem))) 1452 && p.Op != OpSB 1453 && x0.Uses == 1 1454 && x1.Uses == 1 1455 && x2.Uses == 1 1456 && s0.Uses == 1 1457 && s1.Uses == 1 1458 && o0.Uses == 1 1459 && mergePoint(b,x0,x1,x2) != nil 1460 && clobber(x0) 1461 && clobber(x1) 1462 && clobber(x2) 1463 && clobber(s0) 1464 && clobber(s1) 1465 && clobber(o0) 1466 -> @mergePoint(b,x0,x1,x2) (MOVWZload [i-2] {s} p mem) 1467 1468 // b[7] | b[6]<<8 | b[5]<<16 | b[4]<<24 | b[3]<<32 | b[2]<<40 | b[1]<<48 | b[0]<<56 -> load 64-bit 1469 (OR o0:(OR o1:(OR o2:(OR o3:(OR o4:(OR o5:(OR 1470 x0:(MOVBZload [i] {s} p mem) 1471 s0:(SLDconst [8] x1:(MOVBZload [i-1] {s} p mem))) 1472 s1:(SLDconst [16] x2:(MOVBZload [i-2] {s} p mem))) 1473 s2:(SLDconst [24] x3:(MOVBZload [i-3] {s} p mem))) 1474 s3:(SLDconst [32] x4:(MOVBZload [i-4] {s} p mem))) 1475 s4:(SLDconst [40] x5:(MOVBZload [i-5] {s} p mem))) 1476 s5:(SLDconst [48] x6:(MOVBZload [i-6] {s} p mem))) 1477 s6:(SLDconst [56] x7:(MOVBZload [i-7] {s} p mem))) 1478 && p.Op != OpSB 1479 && x0.Uses == 1 1480 && x1.Uses == 1 1481 && x2.Uses == 1 1482 && x3.Uses == 1 1483 && x4.Uses == 1 1484 && x5.Uses == 1 1485 && x6.Uses == 1 1486 && x7.Uses == 1 1487 && s0.Uses == 1 1488 && s1.Uses == 1 1489 && s2.Uses == 1 1490 && s3.Uses == 1 1491 && s4.Uses == 1 1492 && s5.Uses == 1 1493 && s6.Uses == 1 1494 && o0.Uses == 1 1495 && o1.Uses == 1 1496 && o2.Uses == 1 1497 && o3.Uses == 1 1498 && o4.Uses == 1 1499 && o5.Uses == 1 1500 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1501 && clobber(x0) 1502 && clobber(x1) 1503 && clobber(x2) 1504 && clobber(x3) 1505 && clobber(x4) 1506 && clobber(x5) 1507 && clobber(x6) 1508 && clobber(x7) 1509 && clobber(s0) 1510 && clobber(s1) 1511 && clobber(s2) 1512 && clobber(s3) 1513 && clobber(s4) 1514 && clobber(s5) 1515 && clobber(s6) 1516 && clobber(o0) 1517 && clobber(o1) 1518 && clobber(o2) 1519 && clobber(o3) 1520 && clobber(o4) 1521 && clobber(o5) 1522 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDload [i-7] {s} p mem) 1523 1524 // b[1] | b[0]<<8 -> load 16-bit 1525 (ORW x0:(MOVBZloadidx [i] {s} p idx mem) 1526 s0:(SLWconst [8] x1:(MOVBZloadidx [i-1] {s} p idx mem))) 1527 && x0.Uses == 1 1528 && x1.Uses == 1 1529 && s0.Uses == 1 1530 && mergePoint(b,x0,x1) != nil 1531 && clobber(x0) 1532 && clobber(x1) 1533 && clobber(s0) 1534 -> @mergePoint(b,x0,x1) (MOVHZloadidx <v.Type> [i-1] {s} p idx mem) 1535 1536 // b[3] | b[2]<<8 | b[1]<<16 | b[0]<<24 -> load 32-bit 1537 (ORW o0:(ORW x0:(MOVHZloadidx [i] {s} p idx mem) 1538 s0:(SLWconst [16] x1:(MOVBZloadidx [i-1] {s} p idx mem))) 1539 s1:(SLWconst [24] x2:(MOVBZloadidx [i-2] {s} p idx mem))) 1540 && x0.Uses == 1 1541 && x1.Uses == 1 1542 && x2.Uses == 1 1543 && s0.Uses == 1 1544 && s1.Uses == 1 1545 && o0.Uses == 1 1546 && mergePoint(b,x0,x1,x2) != nil 1547 && clobber(x0) 1548 && clobber(x1) 1549 && clobber(x2) 1550 && clobber(s0) 1551 && clobber(s1) 1552 && clobber(o0) 1553 -> @mergePoint(b,x0,x1,x2) (MOVWZloadidx <v.Type> [i-2] {s} p idx mem) 1554 1555 // b[7] | b[6]<<8 | b[5]<<16 | b[4]<<24 | b[3]<<32 | b[2]<<40 | b[1]<<48 | b[0]<<56 -> load 64-bit 1556 (OR o0:(OR o1:(OR o2:(OR o3:(OR o4:(OR o5:(OR 1557 x0:(MOVBZloadidx [i] {s} p idx mem) 1558 s0:(SLDconst [8] x1:(MOVBZloadidx [i-1] {s} p idx mem))) 1559 s1:(SLDconst [16] x2:(MOVBZloadidx [i-2] {s} p idx mem))) 1560 s2:(SLDconst [24] x3:(MOVBZloadidx [i-3] {s} p idx mem))) 1561 s3:(SLDconst [32] x4:(MOVBZloadidx [i-4] {s} p idx mem))) 1562 s4:(SLDconst [40] x5:(MOVBZloadidx [i-5] {s} p idx mem))) 1563 s5:(SLDconst [48] x6:(MOVBZloadidx [i-6] {s} p idx mem))) 1564 s6:(SLDconst [56] x7:(MOVBZloadidx [i-7] {s} p idx mem))) 1565 && x0.Uses == 1 1566 && x1.Uses == 1 1567 && x2.Uses == 1 1568 && x3.Uses == 1 1569 && x4.Uses == 1 1570 && x5.Uses == 1 1571 && x6.Uses == 1 1572 && x7.Uses == 1 1573 && s0.Uses == 1 1574 && s1.Uses == 1 1575 && s2.Uses == 1 1576 && s3.Uses == 1 1577 && s4.Uses == 1 1578 && s5.Uses == 1 1579 && s6.Uses == 1 1580 && o0.Uses == 1 1581 && o1.Uses == 1 1582 && o2.Uses == 1 1583 && o3.Uses == 1 1584 && o4.Uses == 1 1585 && o5.Uses == 1 1586 && mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) != nil 1587 && clobber(x0) 1588 && clobber(x1) 1589 && clobber(x2) 1590 && clobber(x3) 1591 && clobber(x4) 1592 && clobber(x5) 1593 && clobber(x6) 1594 && clobber(x7) 1595 && clobber(s0) 1596 && clobber(s1) 1597 && clobber(s2) 1598 && clobber(s3) 1599 && clobber(s4) 1600 && clobber(s5) 1601 && clobber(s6) 1602 && clobber(o0) 1603 && clobber(o1) 1604 && clobber(o2) 1605 && clobber(o3) 1606 && clobber(o4) 1607 && clobber(o5) 1608 -> @mergePoint(b,x0,x1,x2,x3,x4,x5,x6,x7) (MOVDloadidx <v.Type> [i-7] {s} p idx mem) 1609 1610 // Combine stores into store multiples. 1611 // 32-bit 1612 (MOVWstore [i] {s} p w1 x:(MOVWstore [i-4] {s} p w0 mem)) 1613 && p.Op != OpSB 1614 && x.Uses == 1 1615 && is20Bit(i-4) 1616 && clobber(x) 1617 -> (STM2 [i-4] {s} p w0 w1 mem) 1618 (MOVWstore [i] {s} p w2 x:(STM2 [i-8] {s} p w0 w1 mem)) 1619 && x.Uses == 1 1620 && is20Bit(i-8) 1621 && clobber(x) 1622 -> (STM3 [i-8] {s} p w0 w1 w2 mem) 1623 (MOVWstore [i] {s} p w3 x:(STM3 [i-12] {s} p w0 w1 w2 mem)) 1624 && x.Uses == 1 1625 && is20Bit(i-12) 1626 && clobber(x) 1627 -> (STM4 [i-12] {s} p w0 w1 w2 w3 mem) 1628 (STM2 [i] {s} p w2 w3 x:(STM2 [i-8] {s} p w0 w1 mem)) 1629 && x.Uses == 1 1630 && is20Bit(i-8) 1631 && clobber(x) 1632 -> (STM4 [i-8] {s} p w0 w1 w2 w3 mem) 1633 // 64-bit 1634 (MOVDstore [i] {s} p w1 x:(MOVDstore [i-8] {s} p w0 mem)) 1635 && p.Op != OpSB 1636 && x.Uses == 1 1637 && is20Bit(i-8) 1638 && clobber(x) 1639 -> (STMG2 [i-8] {s} p w0 w1 mem) 1640 (MOVDstore [i] {s} p w2 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1641 && x.Uses == 1 1642 && is20Bit(i-16) 1643 && clobber(x) 1644 -> (STMG3 [i-16] {s} p w0 w1 w2 mem) 1645 (MOVDstore [i] {s} p w3 x:(STMG3 [i-24] {s} p w0 w1 w2 mem)) 1646 && x.Uses == 1 1647 && is20Bit(i-24) 1648 && clobber(x) 1649 -> (STMG4 [i-24] {s} p w0 w1 w2 w3 mem) 1650 (STMG2 [i] {s} p w2 w3 x:(STMG2 [i-16] {s} p w0 w1 mem)) 1651 && x.Uses == 1 1652 && is20Bit(i-16) 1653 && clobber(x) 1654 -> (STMG4 [i-16] {s} p w0 w1 w2 w3 mem) 1655 1656 // Convert 32-bit store multiples into 64-bit stores. 1657 (STM2 [i] {s} p (SRDconst [32] x) x mem) -> (MOVDstore [i] {s} p x mem)