github.com/elliott5/community@v0.14.1-0.20160709191136-823126fb026a/app/public/codemirror/mode/verilog/index.html (about)

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    22      <li><a class=active href="#">Verilog/SystemVerilog</a>
    23    </ul>
    24  </div>
    25  
    26  <article>
    27  <h2>SystemVerilog mode</h2>
    28  
    29  <div><textarea id="code" name="code">
    30  // Literals
    31  1'b0
    32  1'bx
    33  1'bz
    34  16'hDC78
    35  'hdeadbeef
    36  'b0011xxzz
    37  1234
    38  32'd5678
    39  3.4e6
    40  -128.7
    41  
    42  // Macro definition
    43  `define BUS_WIDTH = 8;
    44  
    45  // Module definition
    46  module block(
    47    input                   clk,
    48    input                   rst_n,
    49    input  [`BUS_WIDTH-1:0] data_in,
    50    output [`BUS_WIDTH-1:0] data_out
    51  );
    52    
    53    always @(posedge clk or negedge rst_n) begin
    54  
    55      if (~rst_n) begin
    56        data_out <= 8'b0;
    57      end else begin
    58        data_out <= data_in;
    59      end
    60      
    61      if (~rst_n)
    62        data_out <= 8'b0;
    63      else
    64        data_out <= data_in;
    65      
    66      if (~rst_n)
    67        begin
    68          data_out <= 8'b0;
    69        end
    70      else
    71        begin
    72          data_out <= data_in;
    73        end
    74  
    75    end
    76    
    77  endmodule
    78  
    79  // Class definition
    80  class test;
    81  
    82    /**
    83     * Sum two integers
    84     */
    85    function int sum(int a, int b);
    86      int result = a + b;
    87      string msg = $sformatf("%d + %d = %d", a, b, result);
    88      $display(msg);
    89      return result;
    90    endfunction
    91    
    92    task delay(int num_cycles);
    93      repeat(num_cycles) #1;
    94    endtask
    95    
    96  endclass
    97  
    98  </textarea></div>
    99  
   100  <script>
   101    var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
   102      lineNumbers: true,
   103      matchBrackets: true,
   104      mode: {
   105        name: "verilog",
   106        noIndentKeywords: ["package"]
   107      }
   108    });
   109  </script>
   110  
   111  <p>
   112  Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).
   113  <h2>Configuration options:</h2>
   114    <ul>
   115      <li><strong>noIndentKeywords</strong> - List of keywords which should not cause identation to increase. E.g. ["package", "module"]. Default: None</li>
   116    </ul>
   117  </p>
   118  
   119  <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p>
   120  </article>