github.com/epfl-dcsl/gotee@v0.0.0-20200909122901-014b35f5e5e9/src/cmd/compile/internal/ssa/opGen.go (about) 1 // Code generated from gen/*Ops.go; DO NOT EDIT. 2 3 package ssa 4 5 import ( 6 "cmd/internal/obj" 7 "cmd/internal/obj/arm" 8 "cmd/internal/obj/arm64" 9 "cmd/internal/obj/mips" 10 "cmd/internal/obj/ppc64" 11 "cmd/internal/obj/s390x" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 BlockARM64Z 70 BlockARM64NZ 71 BlockARM64ZW 72 BlockARM64NZW 73 BlockARM64TBZ 74 BlockARM64TBNZ 75 76 BlockMIPSEQ 77 BlockMIPSNE 78 BlockMIPSLTZ 79 BlockMIPSLEZ 80 BlockMIPSGTZ 81 BlockMIPSGEZ 82 BlockMIPSFPT 83 BlockMIPSFPF 84 85 BlockMIPS64EQ 86 BlockMIPS64NE 87 BlockMIPS64LTZ 88 BlockMIPS64LEZ 89 BlockMIPS64GTZ 90 BlockMIPS64GEZ 91 BlockMIPS64FPT 92 BlockMIPS64FPF 93 94 BlockPPC64EQ 95 BlockPPC64NE 96 BlockPPC64LT 97 BlockPPC64LE 98 BlockPPC64GT 99 BlockPPC64GE 100 BlockPPC64FLT 101 BlockPPC64FLE 102 BlockPPC64FGT 103 BlockPPC64FGE 104 105 BlockS390XEQ 106 BlockS390XNE 107 BlockS390XLT 108 BlockS390XLE 109 BlockS390XGT 110 BlockS390XGE 111 BlockS390XGTF 112 BlockS390XGEF 113 114 BlockPlain 115 BlockIf 116 BlockDefer 117 BlockRet 118 BlockRetJmp 119 BlockExit 120 BlockFirst 121 ) 122 123 var blockString = [...]string{ 124 BlockInvalid: "BlockInvalid", 125 126 Block386EQ: "EQ", 127 Block386NE: "NE", 128 Block386LT: "LT", 129 Block386LE: "LE", 130 Block386GT: "GT", 131 Block386GE: "GE", 132 Block386ULT: "ULT", 133 Block386ULE: "ULE", 134 Block386UGT: "UGT", 135 Block386UGE: "UGE", 136 Block386EQF: "EQF", 137 Block386NEF: "NEF", 138 Block386ORD: "ORD", 139 Block386NAN: "NAN", 140 141 BlockAMD64EQ: "EQ", 142 BlockAMD64NE: "NE", 143 BlockAMD64LT: "LT", 144 BlockAMD64LE: "LE", 145 BlockAMD64GT: "GT", 146 BlockAMD64GE: "GE", 147 BlockAMD64ULT: "ULT", 148 BlockAMD64ULE: "ULE", 149 BlockAMD64UGT: "UGT", 150 BlockAMD64UGE: "UGE", 151 BlockAMD64EQF: "EQF", 152 BlockAMD64NEF: "NEF", 153 BlockAMD64ORD: "ORD", 154 BlockAMD64NAN: "NAN", 155 156 BlockARMEQ: "EQ", 157 BlockARMNE: "NE", 158 BlockARMLT: "LT", 159 BlockARMLE: "LE", 160 BlockARMGT: "GT", 161 BlockARMGE: "GE", 162 BlockARMULT: "ULT", 163 BlockARMULE: "ULE", 164 BlockARMUGT: "UGT", 165 BlockARMUGE: "UGE", 166 167 BlockARM64EQ: "EQ", 168 BlockARM64NE: "NE", 169 BlockARM64LT: "LT", 170 BlockARM64LE: "LE", 171 BlockARM64GT: "GT", 172 BlockARM64GE: "GE", 173 BlockARM64ULT: "ULT", 174 BlockARM64ULE: "ULE", 175 BlockARM64UGT: "UGT", 176 BlockARM64UGE: "UGE", 177 BlockARM64Z: "Z", 178 BlockARM64NZ: "NZ", 179 BlockARM64ZW: "ZW", 180 BlockARM64NZW: "NZW", 181 BlockARM64TBZ: "TBZ", 182 BlockARM64TBNZ: "TBNZ", 183 184 BlockMIPSEQ: "EQ", 185 BlockMIPSNE: "NE", 186 BlockMIPSLTZ: "LTZ", 187 BlockMIPSLEZ: "LEZ", 188 BlockMIPSGTZ: "GTZ", 189 BlockMIPSGEZ: "GEZ", 190 BlockMIPSFPT: "FPT", 191 BlockMIPSFPF: "FPF", 192 193 BlockMIPS64EQ: "EQ", 194 BlockMIPS64NE: "NE", 195 BlockMIPS64LTZ: "LTZ", 196 BlockMIPS64LEZ: "LEZ", 197 BlockMIPS64GTZ: "GTZ", 198 BlockMIPS64GEZ: "GEZ", 199 BlockMIPS64FPT: "FPT", 200 BlockMIPS64FPF: "FPF", 201 202 BlockPPC64EQ: "EQ", 203 BlockPPC64NE: "NE", 204 BlockPPC64LT: "LT", 205 BlockPPC64LE: "LE", 206 BlockPPC64GT: "GT", 207 BlockPPC64GE: "GE", 208 BlockPPC64FLT: "FLT", 209 BlockPPC64FLE: "FLE", 210 BlockPPC64FGT: "FGT", 211 BlockPPC64FGE: "FGE", 212 213 BlockS390XEQ: "EQ", 214 BlockS390XNE: "NE", 215 BlockS390XLT: "LT", 216 BlockS390XLE: "LE", 217 BlockS390XGT: "GT", 218 BlockS390XGE: "GE", 219 BlockS390XGTF: "GTF", 220 BlockS390XGEF: "GEF", 221 222 BlockPlain: "Plain", 223 BlockIf: "If", 224 BlockDefer: "Defer", 225 BlockRet: "Ret", 226 BlockRetJmp: "RetJmp", 227 BlockExit: "Exit", 228 BlockFirst: "First", 229 } 230 231 func (k BlockKind) String() string { return blockString[k] } 232 233 const ( 234 OpInvalid Op = iota 235 236 Op386ADDSS 237 Op386ADDSD 238 Op386SUBSS 239 Op386SUBSD 240 Op386MULSS 241 Op386MULSD 242 Op386DIVSS 243 Op386DIVSD 244 Op386MOVSSload 245 Op386MOVSDload 246 Op386MOVSSconst 247 Op386MOVSDconst 248 Op386MOVSSloadidx1 249 Op386MOVSSloadidx4 250 Op386MOVSDloadidx1 251 Op386MOVSDloadidx8 252 Op386MOVSSstore 253 Op386MOVSDstore 254 Op386MOVSSstoreidx1 255 Op386MOVSSstoreidx4 256 Op386MOVSDstoreidx1 257 Op386MOVSDstoreidx8 258 Op386ADDL 259 Op386ADDLconst 260 Op386ADDLcarry 261 Op386ADDLconstcarry 262 Op386ADCL 263 Op386ADCLconst 264 Op386SUBL 265 Op386SUBLconst 266 Op386SUBLcarry 267 Op386SUBLconstcarry 268 Op386SBBL 269 Op386SBBLconst 270 Op386MULL 271 Op386MULLconst 272 Op386HMULL 273 Op386HMULLU 274 Op386MULLQU 275 Op386AVGLU 276 Op386DIVL 277 Op386DIVW 278 Op386DIVLU 279 Op386DIVWU 280 Op386MODL 281 Op386MODW 282 Op386MODLU 283 Op386MODWU 284 Op386ANDL 285 Op386ANDLconst 286 Op386ORL 287 Op386ORLconst 288 Op386XORL 289 Op386XORLconst 290 Op386CMPL 291 Op386CMPW 292 Op386CMPB 293 Op386CMPLconst 294 Op386CMPWconst 295 Op386CMPBconst 296 Op386UCOMISS 297 Op386UCOMISD 298 Op386TESTL 299 Op386TESTW 300 Op386TESTB 301 Op386TESTLconst 302 Op386TESTWconst 303 Op386TESTBconst 304 Op386SHLL 305 Op386SHLLconst 306 Op386SHRL 307 Op386SHRW 308 Op386SHRB 309 Op386SHRLconst 310 Op386SHRWconst 311 Op386SHRBconst 312 Op386SARL 313 Op386SARW 314 Op386SARB 315 Op386SARLconst 316 Op386SARWconst 317 Op386SARBconst 318 Op386ROLLconst 319 Op386ROLWconst 320 Op386ROLBconst 321 Op386NEGL 322 Op386NOTL 323 Op386BSFL 324 Op386BSFW 325 Op386BSRL 326 Op386BSRW 327 Op386BSWAPL 328 Op386SQRTSD 329 Op386SBBLcarrymask 330 Op386SETEQ 331 Op386SETNE 332 Op386SETL 333 Op386SETLE 334 Op386SETG 335 Op386SETGE 336 Op386SETB 337 Op386SETBE 338 Op386SETA 339 Op386SETAE 340 Op386SETEQF 341 Op386SETNEF 342 Op386SETORD 343 Op386SETNAN 344 Op386SETGF 345 Op386SETGEF 346 Op386MOVBLSX 347 Op386MOVBLZX 348 Op386MOVWLSX 349 Op386MOVWLZX 350 Op386MOVLconst 351 Op386CVTTSD2SL 352 Op386CVTTSS2SL 353 Op386CVTSL2SS 354 Op386CVTSL2SD 355 Op386CVTSD2SS 356 Op386CVTSS2SD 357 Op386PXOR 358 Op386LEAL 359 Op386LEAL1 360 Op386LEAL2 361 Op386LEAL4 362 Op386LEAL8 363 Op386MOVBload 364 Op386MOVBLSXload 365 Op386MOVWload 366 Op386MOVWLSXload 367 Op386MOVLload 368 Op386MOVBstore 369 Op386MOVWstore 370 Op386MOVLstore 371 Op386MOVBloadidx1 372 Op386MOVWloadidx1 373 Op386MOVWloadidx2 374 Op386MOVLloadidx1 375 Op386MOVLloadidx4 376 Op386MOVBstoreidx1 377 Op386MOVWstoreidx1 378 Op386MOVWstoreidx2 379 Op386MOVLstoreidx1 380 Op386MOVLstoreidx4 381 Op386MOVBstoreconst 382 Op386MOVWstoreconst 383 Op386MOVLstoreconst 384 Op386MOVBstoreconstidx1 385 Op386MOVWstoreconstidx1 386 Op386MOVWstoreconstidx2 387 Op386MOVLstoreconstidx1 388 Op386MOVLstoreconstidx4 389 Op386DUFFZERO 390 Op386REPSTOSL 391 Op386CALLstatic 392 Op386CALLclosure 393 Op386CALLinter 394 Op386DUFFCOPY 395 Op386REPMOVSL 396 Op386InvertFlags 397 Op386LoweredGetG 398 Op386LoweredGetClosurePtr 399 Op386LoweredGetCallerPC 400 Op386LoweredGetCallerSP 401 Op386LoweredNilCheck 402 Op386MOVLconvert 403 Op386FlagEQ 404 Op386FlagLT_ULT 405 Op386FlagLT_UGT 406 Op386FlagGT_UGT 407 Op386FlagGT_ULT 408 Op386FCHS 409 Op386MOVSSconst1 410 Op386MOVSDconst1 411 Op386MOVSSconst2 412 Op386MOVSDconst2 413 414 OpAMD64ADDSS 415 OpAMD64ADDSD 416 OpAMD64SUBSS 417 OpAMD64SUBSD 418 OpAMD64MULSS 419 OpAMD64MULSD 420 OpAMD64DIVSS 421 OpAMD64DIVSD 422 OpAMD64MOVSSload 423 OpAMD64MOVSDload 424 OpAMD64MOVSSconst 425 OpAMD64MOVSDconst 426 OpAMD64MOVSSloadidx1 427 OpAMD64MOVSSloadidx4 428 OpAMD64MOVSDloadidx1 429 OpAMD64MOVSDloadidx8 430 OpAMD64MOVSSstore 431 OpAMD64MOVSDstore 432 OpAMD64MOVSSstoreidx1 433 OpAMD64MOVSSstoreidx4 434 OpAMD64MOVSDstoreidx1 435 OpAMD64MOVSDstoreidx8 436 OpAMD64ADDSSmem 437 OpAMD64ADDSDmem 438 OpAMD64SUBSSmem 439 OpAMD64SUBSDmem 440 OpAMD64MULSSmem 441 OpAMD64MULSDmem 442 OpAMD64ADDQ 443 OpAMD64ADDL 444 OpAMD64ADDQconst 445 OpAMD64ADDLconst 446 OpAMD64ADDQconstmem 447 OpAMD64ADDLconstmem 448 OpAMD64SUBQ 449 OpAMD64SUBL 450 OpAMD64SUBQconst 451 OpAMD64SUBLconst 452 OpAMD64MULQ 453 OpAMD64MULL 454 OpAMD64MULQconst 455 OpAMD64MULLconst 456 OpAMD64HMULQ 457 OpAMD64HMULL 458 OpAMD64HMULQU 459 OpAMD64HMULLU 460 OpAMD64AVGQU 461 OpAMD64DIVQ 462 OpAMD64DIVL 463 OpAMD64DIVW 464 OpAMD64DIVQU 465 OpAMD64DIVLU 466 OpAMD64DIVWU 467 OpAMD64MULQU2 468 OpAMD64DIVQU2 469 OpAMD64ANDQ 470 OpAMD64ANDL 471 OpAMD64ANDQconst 472 OpAMD64ANDLconst 473 OpAMD64ORQ 474 OpAMD64ORL 475 OpAMD64ORQconst 476 OpAMD64ORLconst 477 OpAMD64XORQ 478 OpAMD64XORL 479 OpAMD64XORQconst 480 OpAMD64XORLconst 481 OpAMD64CMPQ 482 OpAMD64CMPL 483 OpAMD64CMPW 484 OpAMD64CMPB 485 OpAMD64CMPQconst 486 OpAMD64CMPLconst 487 OpAMD64CMPWconst 488 OpAMD64CMPBconst 489 OpAMD64UCOMISS 490 OpAMD64UCOMISD 491 OpAMD64BTL 492 OpAMD64BTQ 493 OpAMD64BTLconst 494 OpAMD64BTQconst 495 OpAMD64TESTQ 496 OpAMD64TESTL 497 OpAMD64TESTW 498 OpAMD64TESTB 499 OpAMD64TESTQconst 500 OpAMD64TESTLconst 501 OpAMD64TESTWconst 502 OpAMD64TESTBconst 503 OpAMD64SHLQ 504 OpAMD64SHLL 505 OpAMD64SHLQconst 506 OpAMD64SHLLconst 507 OpAMD64SHRQ 508 OpAMD64SHRL 509 OpAMD64SHRW 510 OpAMD64SHRB 511 OpAMD64SHRQconst 512 OpAMD64SHRLconst 513 OpAMD64SHRWconst 514 OpAMD64SHRBconst 515 OpAMD64SARQ 516 OpAMD64SARL 517 OpAMD64SARW 518 OpAMD64SARB 519 OpAMD64SARQconst 520 OpAMD64SARLconst 521 OpAMD64SARWconst 522 OpAMD64SARBconst 523 OpAMD64ROLQ 524 OpAMD64ROLL 525 OpAMD64ROLW 526 OpAMD64ROLB 527 OpAMD64RORQ 528 OpAMD64RORL 529 OpAMD64RORW 530 OpAMD64RORB 531 OpAMD64ROLQconst 532 OpAMD64ROLLconst 533 OpAMD64ROLWconst 534 OpAMD64ROLBconst 535 OpAMD64ADDLmem 536 OpAMD64ADDQmem 537 OpAMD64SUBQmem 538 OpAMD64SUBLmem 539 OpAMD64ANDLmem 540 OpAMD64ANDQmem 541 OpAMD64ORQmem 542 OpAMD64ORLmem 543 OpAMD64XORQmem 544 OpAMD64XORLmem 545 OpAMD64NEGQ 546 OpAMD64NEGL 547 OpAMD64NOTQ 548 OpAMD64NOTL 549 OpAMD64BSFQ 550 OpAMD64BSFL 551 OpAMD64BSRQ 552 OpAMD64BSRL 553 OpAMD64CMOVQEQ 554 OpAMD64CMOVLEQ 555 OpAMD64BSWAPQ 556 OpAMD64BSWAPL 557 OpAMD64POPCNTQ 558 OpAMD64POPCNTL 559 OpAMD64SQRTSD 560 OpAMD64ROUNDSD 561 OpAMD64SBBQcarrymask 562 OpAMD64SBBLcarrymask 563 OpAMD64SETEQ 564 OpAMD64SETNE 565 OpAMD64SETL 566 OpAMD64SETLE 567 OpAMD64SETG 568 OpAMD64SETGE 569 OpAMD64SETB 570 OpAMD64SETBE 571 OpAMD64SETA 572 OpAMD64SETAE 573 OpAMD64SETEQmem 574 OpAMD64SETNEmem 575 OpAMD64SETLmem 576 OpAMD64SETLEmem 577 OpAMD64SETGmem 578 OpAMD64SETGEmem 579 OpAMD64SETBmem 580 OpAMD64SETBEmem 581 OpAMD64SETAmem 582 OpAMD64SETAEmem 583 OpAMD64SETEQF 584 OpAMD64SETNEF 585 OpAMD64SETORD 586 OpAMD64SETNAN 587 OpAMD64SETGF 588 OpAMD64SETGEF 589 OpAMD64MOVBQSX 590 OpAMD64MOVBQZX 591 OpAMD64MOVWQSX 592 OpAMD64MOVWQZX 593 OpAMD64MOVLQSX 594 OpAMD64MOVLQZX 595 OpAMD64MOVLconst 596 OpAMD64MOVQconst 597 OpAMD64CVTTSD2SL 598 OpAMD64CVTTSD2SQ 599 OpAMD64CVTTSS2SL 600 OpAMD64CVTTSS2SQ 601 OpAMD64CVTSL2SS 602 OpAMD64CVTSL2SD 603 OpAMD64CVTSQ2SS 604 OpAMD64CVTSQ2SD 605 OpAMD64CVTSD2SS 606 OpAMD64CVTSS2SD 607 OpAMD64MOVQi2f 608 OpAMD64MOVQf2i 609 OpAMD64MOVLi2f 610 OpAMD64MOVLf2i 611 OpAMD64PXOR 612 OpAMD64LEAQ 613 OpAMD64LEAQ1 614 OpAMD64LEAQ2 615 OpAMD64LEAQ4 616 OpAMD64LEAQ8 617 OpAMD64LEAL 618 OpAMD64MOVBload 619 OpAMD64MOVBQSXload 620 OpAMD64MOVWload 621 OpAMD64MOVWQSXload 622 OpAMD64MOVLload 623 OpAMD64MOVLQSXload 624 OpAMD64MOVQload 625 OpAMD64MOVBstore 626 OpAMD64MOVWstore 627 OpAMD64MOVLstore 628 OpAMD64MOVQstore 629 OpAMD64MOVOload 630 OpAMD64MOVOstore 631 OpAMD64MOVBloadidx1 632 OpAMD64MOVWloadidx1 633 OpAMD64MOVWloadidx2 634 OpAMD64MOVLloadidx1 635 OpAMD64MOVLloadidx4 636 OpAMD64MOVLloadidx8 637 OpAMD64MOVQloadidx1 638 OpAMD64MOVQloadidx8 639 OpAMD64MOVBstoreidx1 640 OpAMD64MOVWstoreidx1 641 OpAMD64MOVWstoreidx2 642 OpAMD64MOVLstoreidx1 643 OpAMD64MOVLstoreidx4 644 OpAMD64MOVLstoreidx8 645 OpAMD64MOVQstoreidx1 646 OpAMD64MOVQstoreidx8 647 OpAMD64MOVBstoreconst 648 OpAMD64MOVWstoreconst 649 OpAMD64MOVLstoreconst 650 OpAMD64MOVQstoreconst 651 OpAMD64MOVBstoreconstidx1 652 OpAMD64MOVWstoreconstidx1 653 OpAMD64MOVWstoreconstidx2 654 OpAMD64MOVLstoreconstidx1 655 OpAMD64MOVLstoreconstidx4 656 OpAMD64MOVQstoreconstidx1 657 OpAMD64MOVQstoreconstidx8 658 OpAMD64DUFFZERO 659 OpAMD64MOVOconst 660 OpAMD64REPSTOSQ 661 OpAMD64CALLstatic 662 OpAMD64CALLclosure 663 OpAMD64CALLinter 664 OpAMD64DUFFCOPY 665 OpAMD64REPMOVSQ 666 OpAMD64InvertFlags 667 OpAMD64LoweredGetG 668 OpAMD64LoweredGetClosurePtr 669 OpAMD64LoweredGetCallerPC 670 OpAMD64LoweredGetCallerSP 671 OpAMD64LoweredNilCheck 672 OpAMD64LoweredWB 673 OpAMD64MOVQconvert 674 OpAMD64MOVLconvert 675 OpAMD64FlagEQ 676 OpAMD64FlagLT_ULT 677 OpAMD64FlagLT_UGT 678 OpAMD64FlagGT_UGT 679 OpAMD64FlagGT_ULT 680 OpAMD64MOVLatomicload 681 OpAMD64MOVQatomicload 682 OpAMD64XCHGL 683 OpAMD64XCHGQ 684 OpAMD64XADDLlock 685 OpAMD64XADDQlock 686 OpAMD64AddTupleFirst32 687 OpAMD64AddTupleFirst64 688 OpAMD64CMPXCHGLlock 689 OpAMD64CMPXCHGQlock 690 OpAMD64ANDBlock 691 OpAMD64ORBlock 692 693 OpARMADD 694 OpARMADDconst 695 OpARMSUB 696 OpARMSUBconst 697 OpARMRSB 698 OpARMRSBconst 699 OpARMMUL 700 OpARMHMUL 701 OpARMHMULU 702 OpARMCALLudiv 703 OpARMADDS 704 OpARMADDSconst 705 OpARMADC 706 OpARMADCconst 707 OpARMSUBS 708 OpARMSUBSconst 709 OpARMRSBSconst 710 OpARMSBC 711 OpARMSBCconst 712 OpARMRSCconst 713 OpARMMULLU 714 OpARMMULA 715 OpARMMULS 716 OpARMADDF 717 OpARMADDD 718 OpARMSUBF 719 OpARMSUBD 720 OpARMMULF 721 OpARMMULD 722 OpARMNMULF 723 OpARMNMULD 724 OpARMDIVF 725 OpARMDIVD 726 OpARMMULAF 727 OpARMMULAD 728 OpARMMULSF 729 OpARMMULSD 730 OpARMAND 731 OpARMANDconst 732 OpARMOR 733 OpARMORconst 734 OpARMXOR 735 OpARMXORconst 736 OpARMBIC 737 OpARMBICconst 738 OpARMBFX 739 OpARMBFXU 740 OpARMMVN 741 OpARMNEGF 742 OpARMNEGD 743 OpARMSQRTD 744 OpARMCLZ 745 OpARMREV 746 OpARMRBIT 747 OpARMSLL 748 OpARMSLLconst 749 OpARMSRL 750 OpARMSRLconst 751 OpARMSRA 752 OpARMSRAconst 753 OpARMSRRconst 754 OpARMADDshiftLL 755 OpARMADDshiftRL 756 OpARMADDshiftRA 757 OpARMSUBshiftLL 758 OpARMSUBshiftRL 759 OpARMSUBshiftRA 760 OpARMRSBshiftLL 761 OpARMRSBshiftRL 762 OpARMRSBshiftRA 763 OpARMANDshiftLL 764 OpARMANDshiftRL 765 OpARMANDshiftRA 766 OpARMORshiftLL 767 OpARMORshiftRL 768 OpARMORshiftRA 769 OpARMXORshiftLL 770 OpARMXORshiftRL 771 OpARMXORshiftRA 772 OpARMXORshiftRR 773 OpARMBICshiftLL 774 OpARMBICshiftRL 775 OpARMBICshiftRA 776 OpARMMVNshiftLL 777 OpARMMVNshiftRL 778 OpARMMVNshiftRA 779 OpARMADCshiftLL 780 OpARMADCshiftRL 781 OpARMADCshiftRA 782 OpARMSBCshiftLL 783 OpARMSBCshiftRL 784 OpARMSBCshiftRA 785 OpARMRSCshiftLL 786 OpARMRSCshiftRL 787 OpARMRSCshiftRA 788 OpARMADDSshiftLL 789 OpARMADDSshiftRL 790 OpARMADDSshiftRA 791 OpARMSUBSshiftLL 792 OpARMSUBSshiftRL 793 OpARMSUBSshiftRA 794 OpARMRSBSshiftLL 795 OpARMRSBSshiftRL 796 OpARMRSBSshiftRA 797 OpARMADDshiftLLreg 798 OpARMADDshiftRLreg 799 OpARMADDshiftRAreg 800 OpARMSUBshiftLLreg 801 OpARMSUBshiftRLreg 802 OpARMSUBshiftRAreg 803 OpARMRSBshiftLLreg 804 OpARMRSBshiftRLreg 805 OpARMRSBshiftRAreg 806 OpARMANDshiftLLreg 807 OpARMANDshiftRLreg 808 OpARMANDshiftRAreg 809 OpARMORshiftLLreg 810 OpARMORshiftRLreg 811 OpARMORshiftRAreg 812 OpARMXORshiftLLreg 813 OpARMXORshiftRLreg 814 OpARMXORshiftRAreg 815 OpARMBICshiftLLreg 816 OpARMBICshiftRLreg 817 OpARMBICshiftRAreg 818 OpARMMVNshiftLLreg 819 OpARMMVNshiftRLreg 820 OpARMMVNshiftRAreg 821 OpARMADCshiftLLreg 822 OpARMADCshiftRLreg 823 OpARMADCshiftRAreg 824 OpARMSBCshiftLLreg 825 OpARMSBCshiftRLreg 826 OpARMSBCshiftRAreg 827 OpARMRSCshiftLLreg 828 OpARMRSCshiftRLreg 829 OpARMRSCshiftRAreg 830 OpARMADDSshiftLLreg 831 OpARMADDSshiftRLreg 832 OpARMADDSshiftRAreg 833 OpARMSUBSshiftLLreg 834 OpARMSUBSshiftRLreg 835 OpARMSUBSshiftRAreg 836 OpARMRSBSshiftLLreg 837 OpARMRSBSshiftRLreg 838 OpARMRSBSshiftRAreg 839 OpARMCMP 840 OpARMCMPconst 841 OpARMCMN 842 OpARMCMNconst 843 OpARMTST 844 OpARMTSTconst 845 OpARMTEQ 846 OpARMTEQconst 847 OpARMCMPF 848 OpARMCMPD 849 OpARMCMPshiftLL 850 OpARMCMPshiftRL 851 OpARMCMPshiftRA 852 OpARMCMNshiftLL 853 OpARMCMNshiftRL 854 OpARMCMNshiftRA 855 OpARMTSTshiftLL 856 OpARMTSTshiftRL 857 OpARMTSTshiftRA 858 OpARMTEQshiftLL 859 OpARMTEQshiftRL 860 OpARMTEQshiftRA 861 OpARMCMPshiftLLreg 862 OpARMCMPshiftRLreg 863 OpARMCMPshiftRAreg 864 OpARMCMNshiftLLreg 865 OpARMCMNshiftRLreg 866 OpARMCMNshiftRAreg 867 OpARMTSTshiftLLreg 868 OpARMTSTshiftRLreg 869 OpARMTSTshiftRAreg 870 OpARMTEQshiftLLreg 871 OpARMTEQshiftRLreg 872 OpARMTEQshiftRAreg 873 OpARMCMPF0 874 OpARMCMPD0 875 OpARMMOVWconst 876 OpARMMOVFconst 877 OpARMMOVDconst 878 OpARMMOVWaddr 879 OpARMMOVBload 880 OpARMMOVBUload 881 OpARMMOVHload 882 OpARMMOVHUload 883 OpARMMOVWload 884 OpARMMOVFload 885 OpARMMOVDload 886 OpARMMOVBstore 887 OpARMMOVHstore 888 OpARMMOVWstore 889 OpARMMOVFstore 890 OpARMMOVDstore 891 OpARMMOVWloadidx 892 OpARMMOVWloadshiftLL 893 OpARMMOVWloadshiftRL 894 OpARMMOVWloadshiftRA 895 OpARMMOVBUloadidx 896 OpARMMOVBloadidx 897 OpARMMOVHUloadidx 898 OpARMMOVHloadidx 899 OpARMMOVWstoreidx 900 OpARMMOVWstoreshiftLL 901 OpARMMOVWstoreshiftRL 902 OpARMMOVWstoreshiftRA 903 OpARMMOVBstoreidx 904 OpARMMOVHstoreidx 905 OpARMMOVBreg 906 OpARMMOVBUreg 907 OpARMMOVHreg 908 OpARMMOVHUreg 909 OpARMMOVWreg 910 OpARMMOVWnop 911 OpARMMOVWF 912 OpARMMOVWD 913 OpARMMOVWUF 914 OpARMMOVWUD 915 OpARMMOVFW 916 OpARMMOVDW 917 OpARMMOVFWU 918 OpARMMOVDWU 919 OpARMMOVFD 920 OpARMMOVDF 921 OpARMCMOVWHSconst 922 OpARMCMOVWLSconst 923 OpARMSRAcond 924 OpARMCALLstatic 925 OpARMCALLclosure 926 OpARMCALLinter 927 OpARMLoweredNilCheck 928 OpARMEqual 929 OpARMNotEqual 930 OpARMLessThan 931 OpARMLessEqual 932 OpARMGreaterThan 933 OpARMGreaterEqual 934 OpARMLessThanU 935 OpARMLessEqualU 936 OpARMGreaterThanU 937 OpARMGreaterEqualU 938 OpARMDUFFZERO 939 OpARMDUFFCOPY 940 OpARMLoweredZero 941 OpARMLoweredMove 942 OpARMLoweredGetClosurePtr 943 OpARMLoweredGetCallerSP 944 OpARMMOVWconvert 945 OpARMFlagEQ 946 OpARMFlagLT_ULT 947 OpARMFlagLT_UGT 948 OpARMFlagGT_UGT 949 OpARMFlagGT_ULT 950 OpARMInvertFlags 951 952 OpARM64ADD 953 OpARM64ADDconst 954 OpARM64SUB 955 OpARM64SUBconst 956 OpARM64MUL 957 OpARM64MULW 958 OpARM64MULH 959 OpARM64UMULH 960 OpARM64MULL 961 OpARM64UMULL 962 OpARM64DIV 963 OpARM64UDIV 964 OpARM64DIVW 965 OpARM64UDIVW 966 OpARM64MOD 967 OpARM64UMOD 968 OpARM64MODW 969 OpARM64UMODW 970 OpARM64FADDS 971 OpARM64FADDD 972 OpARM64FSUBS 973 OpARM64FSUBD 974 OpARM64FMULS 975 OpARM64FMULD 976 OpARM64FDIVS 977 OpARM64FDIVD 978 OpARM64AND 979 OpARM64ANDconst 980 OpARM64OR 981 OpARM64ORconst 982 OpARM64XOR 983 OpARM64XORconst 984 OpARM64BIC 985 OpARM64BICconst 986 OpARM64MVN 987 OpARM64NEG 988 OpARM64FNEGS 989 OpARM64FNEGD 990 OpARM64FSQRTD 991 OpARM64REV 992 OpARM64REVW 993 OpARM64REV16W 994 OpARM64RBIT 995 OpARM64RBITW 996 OpARM64CLZ 997 OpARM64CLZW 998 OpARM64SLL 999 OpARM64SLLconst 1000 OpARM64SRL 1001 OpARM64SRLconst 1002 OpARM64SRA 1003 OpARM64SRAconst 1004 OpARM64RORconst 1005 OpARM64RORWconst 1006 OpARM64CMP 1007 OpARM64CMPconst 1008 OpARM64CMPW 1009 OpARM64CMPWconst 1010 OpARM64CMN 1011 OpARM64CMNconst 1012 OpARM64CMNW 1013 OpARM64CMNWconst 1014 OpARM64FCMPS 1015 OpARM64FCMPD 1016 OpARM64ADDshiftLL 1017 OpARM64ADDshiftRL 1018 OpARM64ADDshiftRA 1019 OpARM64SUBshiftLL 1020 OpARM64SUBshiftRL 1021 OpARM64SUBshiftRA 1022 OpARM64ANDshiftLL 1023 OpARM64ANDshiftRL 1024 OpARM64ANDshiftRA 1025 OpARM64ORshiftLL 1026 OpARM64ORshiftRL 1027 OpARM64ORshiftRA 1028 OpARM64XORshiftLL 1029 OpARM64XORshiftRL 1030 OpARM64XORshiftRA 1031 OpARM64BICshiftLL 1032 OpARM64BICshiftRL 1033 OpARM64BICshiftRA 1034 OpARM64CMPshiftLL 1035 OpARM64CMPshiftRL 1036 OpARM64CMPshiftRA 1037 OpARM64MOVDconst 1038 OpARM64FMOVSconst 1039 OpARM64FMOVDconst 1040 OpARM64MOVDaddr 1041 OpARM64MOVBload 1042 OpARM64MOVBUload 1043 OpARM64MOVHload 1044 OpARM64MOVHUload 1045 OpARM64MOVWload 1046 OpARM64MOVWUload 1047 OpARM64MOVDload 1048 OpARM64FMOVSload 1049 OpARM64FMOVDload 1050 OpARM64MOVBstore 1051 OpARM64MOVHstore 1052 OpARM64MOVWstore 1053 OpARM64MOVDstore 1054 OpARM64STP 1055 OpARM64FMOVSstore 1056 OpARM64FMOVDstore 1057 OpARM64MOVBstorezero 1058 OpARM64MOVHstorezero 1059 OpARM64MOVWstorezero 1060 OpARM64MOVDstorezero 1061 OpARM64MOVQstorezero 1062 OpARM64MOVBreg 1063 OpARM64MOVBUreg 1064 OpARM64MOVHreg 1065 OpARM64MOVHUreg 1066 OpARM64MOVWreg 1067 OpARM64MOVWUreg 1068 OpARM64MOVDreg 1069 OpARM64MOVDnop 1070 OpARM64SCVTFWS 1071 OpARM64SCVTFWD 1072 OpARM64UCVTFWS 1073 OpARM64UCVTFWD 1074 OpARM64SCVTFS 1075 OpARM64SCVTFD 1076 OpARM64UCVTFS 1077 OpARM64UCVTFD 1078 OpARM64FCVTZSSW 1079 OpARM64FCVTZSDW 1080 OpARM64FCVTZUSW 1081 OpARM64FCVTZUDW 1082 OpARM64FCVTZSS 1083 OpARM64FCVTZSD 1084 OpARM64FCVTZUS 1085 OpARM64FCVTZUD 1086 OpARM64FCVTSD 1087 OpARM64FCVTDS 1088 OpARM64CSELULT 1089 OpARM64CSELULT0 1090 OpARM64CALLstatic 1091 OpARM64CALLclosure 1092 OpARM64CALLinter 1093 OpARM64LoweredNilCheck 1094 OpARM64Equal 1095 OpARM64NotEqual 1096 OpARM64LessThan 1097 OpARM64LessEqual 1098 OpARM64GreaterThan 1099 OpARM64GreaterEqual 1100 OpARM64LessThanU 1101 OpARM64LessEqualU 1102 OpARM64GreaterThanU 1103 OpARM64GreaterEqualU 1104 OpARM64DUFFZERO 1105 OpARM64LoweredZero 1106 OpARM64DUFFCOPY 1107 OpARM64LoweredMove 1108 OpARM64LoweredGetClosurePtr 1109 OpARM64LoweredGetCallerSP 1110 OpARM64MOVDconvert 1111 OpARM64FlagEQ 1112 OpARM64FlagLT_ULT 1113 OpARM64FlagLT_UGT 1114 OpARM64FlagGT_UGT 1115 OpARM64FlagGT_ULT 1116 OpARM64InvertFlags 1117 OpARM64LDAR 1118 OpARM64LDARW 1119 OpARM64STLR 1120 OpARM64STLRW 1121 OpARM64LoweredAtomicExchange64 1122 OpARM64LoweredAtomicExchange32 1123 OpARM64LoweredAtomicAdd64 1124 OpARM64LoweredAtomicAdd32 1125 OpARM64LoweredAtomicCas64 1126 OpARM64LoweredAtomicCas32 1127 OpARM64LoweredAtomicAnd8 1128 OpARM64LoweredAtomicOr8 1129 1130 OpMIPSADD 1131 OpMIPSADDconst 1132 OpMIPSSUB 1133 OpMIPSSUBconst 1134 OpMIPSMUL 1135 OpMIPSMULT 1136 OpMIPSMULTU 1137 OpMIPSDIV 1138 OpMIPSDIVU 1139 OpMIPSADDF 1140 OpMIPSADDD 1141 OpMIPSSUBF 1142 OpMIPSSUBD 1143 OpMIPSMULF 1144 OpMIPSMULD 1145 OpMIPSDIVF 1146 OpMIPSDIVD 1147 OpMIPSAND 1148 OpMIPSANDconst 1149 OpMIPSOR 1150 OpMIPSORconst 1151 OpMIPSXOR 1152 OpMIPSXORconst 1153 OpMIPSNOR 1154 OpMIPSNORconst 1155 OpMIPSNEG 1156 OpMIPSNEGF 1157 OpMIPSNEGD 1158 OpMIPSSQRTD 1159 OpMIPSSLL 1160 OpMIPSSLLconst 1161 OpMIPSSRL 1162 OpMIPSSRLconst 1163 OpMIPSSRA 1164 OpMIPSSRAconst 1165 OpMIPSCLZ 1166 OpMIPSSGT 1167 OpMIPSSGTconst 1168 OpMIPSSGTzero 1169 OpMIPSSGTU 1170 OpMIPSSGTUconst 1171 OpMIPSSGTUzero 1172 OpMIPSCMPEQF 1173 OpMIPSCMPEQD 1174 OpMIPSCMPGEF 1175 OpMIPSCMPGED 1176 OpMIPSCMPGTF 1177 OpMIPSCMPGTD 1178 OpMIPSMOVWconst 1179 OpMIPSMOVFconst 1180 OpMIPSMOVDconst 1181 OpMIPSMOVWaddr 1182 OpMIPSMOVBload 1183 OpMIPSMOVBUload 1184 OpMIPSMOVHload 1185 OpMIPSMOVHUload 1186 OpMIPSMOVWload 1187 OpMIPSMOVFload 1188 OpMIPSMOVDload 1189 OpMIPSMOVBstore 1190 OpMIPSMOVHstore 1191 OpMIPSMOVWstore 1192 OpMIPSMOVFstore 1193 OpMIPSMOVDstore 1194 OpMIPSMOVBstorezero 1195 OpMIPSMOVHstorezero 1196 OpMIPSMOVWstorezero 1197 OpMIPSMOVBreg 1198 OpMIPSMOVBUreg 1199 OpMIPSMOVHreg 1200 OpMIPSMOVHUreg 1201 OpMIPSMOVWreg 1202 OpMIPSMOVWnop 1203 OpMIPSCMOVZ 1204 OpMIPSCMOVZzero 1205 OpMIPSMOVWF 1206 OpMIPSMOVWD 1207 OpMIPSTRUNCFW 1208 OpMIPSTRUNCDW 1209 OpMIPSMOVFD 1210 OpMIPSMOVDF 1211 OpMIPSCALLstatic 1212 OpMIPSCALLclosure 1213 OpMIPSCALLinter 1214 OpMIPSLoweredAtomicLoad 1215 OpMIPSLoweredAtomicStore 1216 OpMIPSLoweredAtomicStorezero 1217 OpMIPSLoweredAtomicExchange 1218 OpMIPSLoweredAtomicAdd 1219 OpMIPSLoweredAtomicAddconst 1220 OpMIPSLoweredAtomicCas 1221 OpMIPSLoweredAtomicAnd 1222 OpMIPSLoweredAtomicOr 1223 OpMIPSLoweredZero 1224 OpMIPSLoweredMove 1225 OpMIPSLoweredNilCheck 1226 OpMIPSFPFlagTrue 1227 OpMIPSFPFlagFalse 1228 OpMIPSLoweredGetClosurePtr 1229 OpMIPSLoweredGetCallerSP 1230 OpMIPSMOVWconvert 1231 1232 OpMIPS64ADDV 1233 OpMIPS64ADDVconst 1234 OpMIPS64SUBV 1235 OpMIPS64SUBVconst 1236 OpMIPS64MULV 1237 OpMIPS64MULVU 1238 OpMIPS64DIVV 1239 OpMIPS64DIVVU 1240 OpMIPS64ADDF 1241 OpMIPS64ADDD 1242 OpMIPS64SUBF 1243 OpMIPS64SUBD 1244 OpMIPS64MULF 1245 OpMIPS64MULD 1246 OpMIPS64DIVF 1247 OpMIPS64DIVD 1248 OpMIPS64AND 1249 OpMIPS64ANDconst 1250 OpMIPS64OR 1251 OpMIPS64ORconst 1252 OpMIPS64XOR 1253 OpMIPS64XORconst 1254 OpMIPS64NOR 1255 OpMIPS64NORconst 1256 OpMIPS64NEGV 1257 OpMIPS64NEGF 1258 OpMIPS64NEGD 1259 OpMIPS64SLLV 1260 OpMIPS64SLLVconst 1261 OpMIPS64SRLV 1262 OpMIPS64SRLVconst 1263 OpMIPS64SRAV 1264 OpMIPS64SRAVconst 1265 OpMIPS64SGT 1266 OpMIPS64SGTconst 1267 OpMIPS64SGTU 1268 OpMIPS64SGTUconst 1269 OpMIPS64CMPEQF 1270 OpMIPS64CMPEQD 1271 OpMIPS64CMPGEF 1272 OpMIPS64CMPGED 1273 OpMIPS64CMPGTF 1274 OpMIPS64CMPGTD 1275 OpMIPS64MOVVconst 1276 OpMIPS64MOVFconst 1277 OpMIPS64MOVDconst 1278 OpMIPS64MOVVaddr 1279 OpMIPS64MOVBload 1280 OpMIPS64MOVBUload 1281 OpMIPS64MOVHload 1282 OpMIPS64MOVHUload 1283 OpMIPS64MOVWload 1284 OpMIPS64MOVWUload 1285 OpMIPS64MOVVload 1286 OpMIPS64MOVFload 1287 OpMIPS64MOVDload 1288 OpMIPS64MOVBstore 1289 OpMIPS64MOVHstore 1290 OpMIPS64MOVWstore 1291 OpMIPS64MOVVstore 1292 OpMIPS64MOVFstore 1293 OpMIPS64MOVDstore 1294 OpMIPS64MOVBstorezero 1295 OpMIPS64MOVHstorezero 1296 OpMIPS64MOVWstorezero 1297 OpMIPS64MOVVstorezero 1298 OpMIPS64MOVBreg 1299 OpMIPS64MOVBUreg 1300 OpMIPS64MOVHreg 1301 OpMIPS64MOVHUreg 1302 OpMIPS64MOVWreg 1303 OpMIPS64MOVWUreg 1304 OpMIPS64MOVVreg 1305 OpMIPS64MOVVnop 1306 OpMIPS64MOVWF 1307 OpMIPS64MOVWD 1308 OpMIPS64MOVVF 1309 OpMIPS64MOVVD 1310 OpMIPS64TRUNCFW 1311 OpMIPS64TRUNCDW 1312 OpMIPS64TRUNCFV 1313 OpMIPS64TRUNCDV 1314 OpMIPS64MOVFD 1315 OpMIPS64MOVDF 1316 OpMIPS64CALLstatic 1317 OpMIPS64CALLclosure 1318 OpMIPS64CALLinter 1319 OpMIPS64DUFFZERO 1320 OpMIPS64LoweredZero 1321 OpMIPS64LoweredMove 1322 OpMIPS64LoweredAtomicLoad32 1323 OpMIPS64LoweredAtomicLoad64 1324 OpMIPS64LoweredAtomicStore32 1325 OpMIPS64LoweredAtomicStore64 1326 OpMIPS64LoweredAtomicStorezero32 1327 OpMIPS64LoweredAtomicStorezero64 1328 OpMIPS64LoweredAtomicExchange32 1329 OpMIPS64LoweredAtomicExchange64 1330 OpMIPS64LoweredAtomicAdd32 1331 OpMIPS64LoweredAtomicAdd64 1332 OpMIPS64LoweredAtomicAddconst32 1333 OpMIPS64LoweredAtomicAddconst64 1334 OpMIPS64LoweredAtomicCas32 1335 OpMIPS64LoweredAtomicCas64 1336 OpMIPS64LoweredNilCheck 1337 OpMIPS64FPFlagTrue 1338 OpMIPS64FPFlagFalse 1339 OpMIPS64LoweredGetClosurePtr 1340 OpMIPS64LoweredGetCallerSP 1341 OpMIPS64MOVVconvert 1342 1343 OpPPC64ADD 1344 OpPPC64ADDconst 1345 OpPPC64FADD 1346 OpPPC64FADDS 1347 OpPPC64SUB 1348 OpPPC64FSUB 1349 OpPPC64FSUBS 1350 OpPPC64MULLD 1351 OpPPC64MULLW 1352 OpPPC64MULHD 1353 OpPPC64MULHW 1354 OpPPC64MULHDU 1355 OpPPC64MULHWU 1356 OpPPC64FMUL 1357 OpPPC64FMULS 1358 OpPPC64FMADD 1359 OpPPC64FMADDS 1360 OpPPC64FMSUB 1361 OpPPC64FMSUBS 1362 OpPPC64SRAD 1363 OpPPC64SRAW 1364 OpPPC64SRD 1365 OpPPC64SRW 1366 OpPPC64SLD 1367 OpPPC64SLW 1368 OpPPC64ROTL 1369 OpPPC64ROTLW 1370 OpPPC64ADDconstForCarry 1371 OpPPC64MaskIfNotCarry 1372 OpPPC64SRADconst 1373 OpPPC64SRAWconst 1374 OpPPC64SRDconst 1375 OpPPC64SRWconst 1376 OpPPC64SLDconst 1377 OpPPC64SLWconst 1378 OpPPC64ROTLconst 1379 OpPPC64ROTLWconst 1380 OpPPC64CNTLZD 1381 OpPPC64CNTLZW 1382 OpPPC64POPCNTD 1383 OpPPC64POPCNTW 1384 OpPPC64POPCNTB 1385 OpPPC64FDIV 1386 OpPPC64FDIVS 1387 OpPPC64DIVD 1388 OpPPC64DIVW 1389 OpPPC64DIVDU 1390 OpPPC64DIVWU 1391 OpPPC64FCTIDZ 1392 OpPPC64FCTIWZ 1393 OpPPC64FCFID 1394 OpPPC64FCFIDS 1395 OpPPC64FRSP 1396 OpPPC64MFVSRD 1397 OpPPC64MTVSRD 1398 OpPPC64AND 1399 OpPPC64ANDN 1400 OpPPC64OR 1401 OpPPC64ORN 1402 OpPPC64NOR 1403 OpPPC64XOR 1404 OpPPC64EQV 1405 OpPPC64NEG 1406 OpPPC64FNEG 1407 OpPPC64FSQRT 1408 OpPPC64FSQRTS 1409 OpPPC64FFLOOR 1410 OpPPC64FCEIL 1411 OpPPC64FTRUNC 1412 OpPPC64FABS 1413 OpPPC64FNABS 1414 OpPPC64FCPSGN 1415 OpPPC64ORconst 1416 OpPPC64XORconst 1417 OpPPC64ANDconst 1418 OpPPC64ANDCCconst 1419 OpPPC64MOVBreg 1420 OpPPC64MOVBZreg 1421 OpPPC64MOVHreg 1422 OpPPC64MOVHZreg 1423 OpPPC64MOVWreg 1424 OpPPC64MOVWZreg 1425 OpPPC64MOVBZload 1426 OpPPC64MOVHload 1427 OpPPC64MOVHZload 1428 OpPPC64MOVWload 1429 OpPPC64MOVWZload 1430 OpPPC64MOVDload 1431 OpPPC64FMOVDload 1432 OpPPC64FMOVSload 1433 OpPPC64MOVBstore 1434 OpPPC64MOVHstore 1435 OpPPC64MOVWstore 1436 OpPPC64MOVDstore 1437 OpPPC64FMOVDstore 1438 OpPPC64FMOVSstore 1439 OpPPC64MOVBstorezero 1440 OpPPC64MOVHstorezero 1441 OpPPC64MOVWstorezero 1442 OpPPC64MOVDstorezero 1443 OpPPC64MOVDaddr 1444 OpPPC64MOVDconst 1445 OpPPC64FMOVDconst 1446 OpPPC64FMOVSconst 1447 OpPPC64FCMPU 1448 OpPPC64CMP 1449 OpPPC64CMPU 1450 OpPPC64CMPW 1451 OpPPC64CMPWU 1452 OpPPC64CMPconst 1453 OpPPC64CMPUconst 1454 OpPPC64CMPWconst 1455 OpPPC64CMPWUconst 1456 OpPPC64Equal 1457 OpPPC64NotEqual 1458 OpPPC64LessThan 1459 OpPPC64FLessThan 1460 OpPPC64LessEqual 1461 OpPPC64FLessEqual 1462 OpPPC64GreaterThan 1463 OpPPC64FGreaterThan 1464 OpPPC64GreaterEqual 1465 OpPPC64FGreaterEqual 1466 OpPPC64LoweredGetClosurePtr 1467 OpPPC64LoweredGetCallerSP 1468 OpPPC64LoweredNilCheck 1469 OpPPC64LoweredRound32F 1470 OpPPC64LoweredRound64F 1471 OpPPC64MOVDconvert 1472 OpPPC64CALLstatic 1473 OpPPC64CALLclosure 1474 OpPPC64CALLinter 1475 OpPPC64LoweredZero 1476 OpPPC64LoweredMove 1477 OpPPC64LoweredAtomicStore32 1478 OpPPC64LoweredAtomicStore64 1479 OpPPC64LoweredAtomicLoad32 1480 OpPPC64LoweredAtomicLoad64 1481 OpPPC64LoweredAtomicLoadPtr 1482 OpPPC64LoweredAtomicAdd32 1483 OpPPC64LoweredAtomicAdd64 1484 OpPPC64LoweredAtomicExchange32 1485 OpPPC64LoweredAtomicExchange64 1486 OpPPC64LoweredAtomicCas64 1487 OpPPC64LoweredAtomicCas32 1488 OpPPC64LoweredAtomicAnd8 1489 OpPPC64LoweredAtomicOr8 1490 OpPPC64InvertFlags 1491 OpPPC64FlagEQ 1492 OpPPC64FlagLT 1493 OpPPC64FlagGT 1494 1495 OpS390XFADDS 1496 OpS390XFADD 1497 OpS390XFSUBS 1498 OpS390XFSUB 1499 OpS390XFMULS 1500 OpS390XFMUL 1501 OpS390XFDIVS 1502 OpS390XFDIV 1503 OpS390XFNEGS 1504 OpS390XFNEG 1505 OpS390XFMADDS 1506 OpS390XFMADD 1507 OpS390XFMSUBS 1508 OpS390XFMSUB 1509 OpS390XLPDFR 1510 OpS390XLNDFR 1511 OpS390XCPSDR 1512 OpS390XFIDBR 1513 OpS390XFMOVSload 1514 OpS390XFMOVDload 1515 OpS390XFMOVSconst 1516 OpS390XFMOVDconst 1517 OpS390XFMOVSloadidx 1518 OpS390XFMOVDloadidx 1519 OpS390XFMOVSstore 1520 OpS390XFMOVDstore 1521 OpS390XFMOVSstoreidx 1522 OpS390XFMOVDstoreidx 1523 OpS390XADD 1524 OpS390XADDW 1525 OpS390XADDconst 1526 OpS390XADDWconst 1527 OpS390XADDload 1528 OpS390XADDWload 1529 OpS390XSUB 1530 OpS390XSUBW 1531 OpS390XSUBconst 1532 OpS390XSUBWconst 1533 OpS390XSUBload 1534 OpS390XSUBWload 1535 OpS390XMULLD 1536 OpS390XMULLW 1537 OpS390XMULLDconst 1538 OpS390XMULLWconst 1539 OpS390XMULLDload 1540 OpS390XMULLWload 1541 OpS390XMULHD 1542 OpS390XMULHDU 1543 OpS390XDIVD 1544 OpS390XDIVW 1545 OpS390XDIVDU 1546 OpS390XDIVWU 1547 OpS390XMODD 1548 OpS390XMODW 1549 OpS390XMODDU 1550 OpS390XMODWU 1551 OpS390XAND 1552 OpS390XANDW 1553 OpS390XANDconst 1554 OpS390XANDWconst 1555 OpS390XANDload 1556 OpS390XANDWload 1557 OpS390XOR 1558 OpS390XORW 1559 OpS390XORconst 1560 OpS390XORWconst 1561 OpS390XORload 1562 OpS390XORWload 1563 OpS390XXOR 1564 OpS390XXORW 1565 OpS390XXORconst 1566 OpS390XXORWconst 1567 OpS390XXORload 1568 OpS390XXORWload 1569 OpS390XCMP 1570 OpS390XCMPW 1571 OpS390XCMPU 1572 OpS390XCMPWU 1573 OpS390XCMPconst 1574 OpS390XCMPWconst 1575 OpS390XCMPUconst 1576 OpS390XCMPWUconst 1577 OpS390XFCMPS 1578 OpS390XFCMP 1579 OpS390XSLD 1580 OpS390XSLW 1581 OpS390XSLDconst 1582 OpS390XSLWconst 1583 OpS390XSRD 1584 OpS390XSRW 1585 OpS390XSRDconst 1586 OpS390XSRWconst 1587 OpS390XSRAD 1588 OpS390XSRAW 1589 OpS390XSRADconst 1590 OpS390XSRAWconst 1591 OpS390XRLLGconst 1592 OpS390XRLLconst 1593 OpS390XNEG 1594 OpS390XNEGW 1595 OpS390XNOT 1596 OpS390XNOTW 1597 OpS390XFSQRT 1598 OpS390XSUBEcarrymask 1599 OpS390XSUBEWcarrymask 1600 OpS390XMOVDEQ 1601 OpS390XMOVDNE 1602 OpS390XMOVDLT 1603 OpS390XMOVDLE 1604 OpS390XMOVDGT 1605 OpS390XMOVDGE 1606 OpS390XMOVDGTnoinv 1607 OpS390XMOVDGEnoinv 1608 OpS390XMOVBreg 1609 OpS390XMOVBZreg 1610 OpS390XMOVHreg 1611 OpS390XMOVHZreg 1612 OpS390XMOVWreg 1613 OpS390XMOVWZreg 1614 OpS390XMOVDreg 1615 OpS390XMOVDnop 1616 OpS390XMOVDconst 1617 OpS390XLDGR 1618 OpS390XLGDR 1619 OpS390XCFDBRA 1620 OpS390XCGDBRA 1621 OpS390XCFEBRA 1622 OpS390XCGEBRA 1623 OpS390XCEFBRA 1624 OpS390XCDFBRA 1625 OpS390XCEGBRA 1626 OpS390XCDGBRA 1627 OpS390XLEDBR 1628 OpS390XLDEBR 1629 OpS390XMOVDaddr 1630 OpS390XMOVDaddridx 1631 OpS390XMOVBZload 1632 OpS390XMOVBload 1633 OpS390XMOVHZload 1634 OpS390XMOVHload 1635 OpS390XMOVWZload 1636 OpS390XMOVWload 1637 OpS390XMOVDload 1638 OpS390XMOVWBR 1639 OpS390XMOVDBR 1640 OpS390XMOVHBRload 1641 OpS390XMOVWBRload 1642 OpS390XMOVDBRload 1643 OpS390XMOVBstore 1644 OpS390XMOVHstore 1645 OpS390XMOVWstore 1646 OpS390XMOVDstore 1647 OpS390XMOVHBRstore 1648 OpS390XMOVWBRstore 1649 OpS390XMOVDBRstore 1650 OpS390XMVC 1651 OpS390XMOVBZloadidx 1652 OpS390XMOVBloadidx 1653 OpS390XMOVHZloadidx 1654 OpS390XMOVHloadidx 1655 OpS390XMOVWZloadidx 1656 OpS390XMOVWloadidx 1657 OpS390XMOVDloadidx 1658 OpS390XMOVHBRloadidx 1659 OpS390XMOVWBRloadidx 1660 OpS390XMOVDBRloadidx 1661 OpS390XMOVBstoreidx 1662 OpS390XMOVHstoreidx 1663 OpS390XMOVWstoreidx 1664 OpS390XMOVDstoreidx 1665 OpS390XMOVHBRstoreidx 1666 OpS390XMOVWBRstoreidx 1667 OpS390XMOVDBRstoreidx 1668 OpS390XMOVBstoreconst 1669 OpS390XMOVHstoreconst 1670 OpS390XMOVWstoreconst 1671 OpS390XMOVDstoreconst 1672 OpS390XCLEAR 1673 OpS390XCALLstatic 1674 OpS390XCALLclosure 1675 OpS390XCALLinter 1676 OpS390XInvertFlags 1677 OpS390XLoweredGetG 1678 OpS390XLoweredGetClosurePtr 1679 OpS390XLoweredGetCallerSP 1680 OpS390XLoweredNilCheck 1681 OpS390XLoweredRound32F 1682 OpS390XLoweredRound64F 1683 OpS390XMOVDconvert 1684 OpS390XFlagEQ 1685 OpS390XFlagLT 1686 OpS390XFlagGT 1687 OpS390XMOVWZatomicload 1688 OpS390XMOVDatomicload 1689 OpS390XMOVWatomicstore 1690 OpS390XMOVDatomicstore 1691 OpS390XLAA 1692 OpS390XLAAG 1693 OpS390XAddTupleFirst32 1694 OpS390XAddTupleFirst64 1695 OpS390XLoweredAtomicCas32 1696 OpS390XLoweredAtomicCas64 1697 OpS390XLoweredAtomicExchange32 1698 OpS390XLoweredAtomicExchange64 1699 OpS390XFLOGR 1700 OpS390XSTMG2 1701 OpS390XSTMG3 1702 OpS390XSTMG4 1703 OpS390XSTM2 1704 OpS390XSTM3 1705 OpS390XSTM4 1706 OpS390XLoweredMove 1707 OpS390XLoweredZero 1708 1709 OpAdd8 1710 OpAdd16 1711 OpAdd32 1712 OpAdd64 1713 OpAddPtr 1714 OpAdd32F 1715 OpAdd64F 1716 OpSub8 1717 OpSub16 1718 OpSub32 1719 OpSub64 1720 OpSubPtr 1721 OpSub32F 1722 OpSub64F 1723 OpMul8 1724 OpMul16 1725 OpMul32 1726 OpMul64 1727 OpMul32F 1728 OpMul64F 1729 OpDiv32F 1730 OpDiv64F 1731 OpHmul32 1732 OpHmul32u 1733 OpHmul64 1734 OpHmul64u 1735 OpMul32uhilo 1736 OpMul64uhilo 1737 OpAvg32u 1738 OpAvg64u 1739 OpDiv8 1740 OpDiv8u 1741 OpDiv16 1742 OpDiv16u 1743 OpDiv32 1744 OpDiv32u 1745 OpDiv64 1746 OpDiv64u 1747 OpDiv128u 1748 OpMod8 1749 OpMod8u 1750 OpMod16 1751 OpMod16u 1752 OpMod32 1753 OpMod32u 1754 OpMod64 1755 OpMod64u 1756 OpAnd8 1757 OpAnd16 1758 OpAnd32 1759 OpAnd64 1760 OpOr8 1761 OpOr16 1762 OpOr32 1763 OpOr64 1764 OpXor8 1765 OpXor16 1766 OpXor32 1767 OpXor64 1768 OpLsh8x8 1769 OpLsh8x16 1770 OpLsh8x32 1771 OpLsh8x64 1772 OpLsh16x8 1773 OpLsh16x16 1774 OpLsh16x32 1775 OpLsh16x64 1776 OpLsh32x8 1777 OpLsh32x16 1778 OpLsh32x32 1779 OpLsh32x64 1780 OpLsh64x8 1781 OpLsh64x16 1782 OpLsh64x32 1783 OpLsh64x64 1784 OpRsh8x8 1785 OpRsh8x16 1786 OpRsh8x32 1787 OpRsh8x64 1788 OpRsh16x8 1789 OpRsh16x16 1790 OpRsh16x32 1791 OpRsh16x64 1792 OpRsh32x8 1793 OpRsh32x16 1794 OpRsh32x32 1795 OpRsh32x64 1796 OpRsh64x8 1797 OpRsh64x16 1798 OpRsh64x32 1799 OpRsh64x64 1800 OpRsh8Ux8 1801 OpRsh8Ux16 1802 OpRsh8Ux32 1803 OpRsh8Ux64 1804 OpRsh16Ux8 1805 OpRsh16Ux16 1806 OpRsh16Ux32 1807 OpRsh16Ux64 1808 OpRsh32Ux8 1809 OpRsh32Ux16 1810 OpRsh32Ux32 1811 OpRsh32Ux64 1812 OpRsh64Ux8 1813 OpRsh64Ux16 1814 OpRsh64Ux32 1815 OpRsh64Ux64 1816 OpEq8 1817 OpEq16 1818 OpEq32 1819 OpEq64 1820 OpEqPtr 1821 OpEqInter 1822 OpEqSlice 1823 OpEq32F 1824 OpEq64F 1825 OpNeq8 1826 OpNeq16 1827 OpNeq32 1828 OpNeq64 1829 OpNeqPtr 1830 OpNeqInter 1831 OpNeqSlice 1832 OpNeq32F 1833 OpNeq64F 1834 OpLess8 1835 OpLess8U 1836 OpLess16 1837 OpLess16U 1838 OpLess32 1839 OpLess32U 1840 OpLess64 1841 OpLess64U 1842 OpLess32F 1843 OpLess64F 1844 OpLeq8 1845 OpLeq8U 1846 OpLeq16 1847 OpLeq16U 1848 OpLeq32 1849 OpLeq32U 1850 OpLeq64 1851 OpLeq64U 1852 OpLeq32F 1853 OpLeq64F 1854 OpGreater8 1855 OpGreater8U 1856 OpGreater16 1857 OpGreater16U 1858 OpGreater32 1859 OpGreater32U 1860 OpGreater64 1861 OpGreater64U 1862 OpGreater32F 1863 OpGreater64F 1864 OpGeq8 1865 OpGeq8U 1866 OpGeq16 1867 OpGeq16U 1868 OpGeq32 1869 OpGeq32U 1870 OpGeq64 1871 OpGeq64U 1872 OpGeq32F 1873 OpGeq64F 1874 OpAndB 1875 OpOrB 1876 OpEqB 1877 OpNeqB 1878 OpNot 1879 OpNeg8 1880 OpNeg16 1881 OpNeg32 1882 OpNeg64 1883 OpNeg32F 1884 OpNeg64F 1885 OpCom8 1886 OpCom16 1887 OpCom32 1888 OpCom64 1889 OpCtz32 1890 OpCtz64 1891 OpBitLen32 1892 OpBitLen64 1893 OpBswap32 1894 OpBswap64 1895 OpBitRev8 1896 OpBitRev16 1897 OpBitRev32 1898 OpBitRev64 1899 OpPopCount8 1900 OpPopCount16 1901 OpPopCount32 1902 OpPopCount64 1903 OpSqrt 1904 OpFloor 1905 OpCeil 1906 OpTrunc 1907 OpRound 1908 OpRoundToEven 1909 OpAbs 1910 OpCopysign 1911 OpPhi 1912 OpCopy 1913 OpConvert 1914 OpConstBool 1915 OpConstString 1916 OpConstNil 1917 OpConst8 1918 OpConst16 1919 OpConst32 1920 OpConst64 1921 OpConst32F 1922 OpConst64F 1923 OpConstInterface 1924 OpConstSlice 1925 OpInitMem 1926 OpArg 1927 OpAddr 1928 OpSP 1929 OpSB 1930 OpLoad 1931 OpStore 1932 OpMove 1933 OpZero 1934 OpStoreWB 1935 OpMoveWB 1936 OpZeroWB 1937 OpWB 1938 OpClosureCall 1939 OpStaticCall 1940 OpInterCall 1941 OpSignExt8to16 1942 OpSignExt8to32 1943 OpSignExt8to64 1944 OpSignExt16to32 1945 OpSignExt16to64 1946 OpSignExt32to64 1947 OpZeroExt8to16 1948 OpZeroExt8to32 1949 OpZeroExt8to64 1950 OpZeroExt16to32 1951 OpZeroExt16to64 1952 OpZeroExt32to64 1953 OpTrunc16to8 1954 OpTrunc32to8 1955 OpTrunc32to16 1956 OpTrunc64to8 1957 OpTrunc64to16 1958 OpTrunc64to32 1959 OpCvt32to32F 1960 OpCvt32to64F 1961 OpCvt64to32F 1962 OpCvt64to64F 1963 OpCvt32Fto32 1964 OpCvt32Fto64 1965 OpCvt64Fto32 1966 OpCvt64Fto64 1967 OpCvt32Fto64F 1968 OpCvt64Fto32F 1969 OpRound32F 1970 OpRound64F 1971 OpIsNonNil 1972 OpIsInBounds 1973 OpIsSliceInBounds 1974 OpNilCheck 1975 OpGetG 1976 OpGetClosurePtr 1977 OpGetCallerPC 1978 OpGetCallerSP 1979 OpPtrIndex 1980 OpOffPtr 1981 OpSliceMake 1982 OpSlicePtr 1983 OpSliceLen 1984 OpSliceCap 1985 OpComplexMake 1986 OpComplexReal 1987 OpComplexImag 1988 OpStringMake 1989 OpStringPtr 1990 OpStringLen 1991 OpIMake 1992 OpITab 1993 OpIData 1994 OpStructMake0 1995 OpStructMake1 1996 OpStructMake2 1997 OpStructMake3 1998 OpStructMake4 1999 OpStructSelect 2000 OpArrayMake0 2001 OpArrayMake1 2002 OpArraySelect 2003 OpStoreReg 2004 OpLoadReg 2005 OpFwdRef 2006 OpUnknown 2007 OpVarDef 2008 OpVarKill 2009 OpVarLive 2010 OpKeepAlive 2011 OpRegKill 2012 OpInt64Make 2013 OpInt64Hi 2014 OpInt64Lo 2015 OpAdd32carry 2016 OpAdd32withcarry 2017 OpSub32carry 2018 OpSub32withcarry 2019 OpSignmask 2020 OpZeromask 2021 OpSlicemask 2022 OpCvt32Uto32F 2023 OpCvt32Uto64F 2024 OpCvt32Fto32U 2025 OpCvt64Fto32U 2026 OpCvt64Uto32F 2027 OpCvt64Uto64F 2028 OpCvt32Fto64U 2029 OpCvt64Fto64U 2030 OpSelect0 2031 OpSelect1 2032 OpAtomicLoad32 2033 OpAtomicLoad64 2034 OpAtomicLoadPtr 2035 OpAtomicStore32 2036 OpAtomicStore64 2037 OpAtomicStorePtrNoWB 2038 OpAtomicExchange32 2039 OpAtomicExchange64 2040 OpAtomicAdd32 2041 OpAtomicAdd64 2042 OpAtomicCompareAndSwap32 2043 OpAtomicCompareAndSwap64 2044 OpAtomicAnd8 2045 OpAtomicOr8 2046 OpClobber 2047 ) 2048 2049 var opcodeTable = [...]opInfo{ 2050 {name: "OpInvalid"}, 2051 2052 { 2053 name: "ADDSS", 2054 argLen: 2, 2055 commutative: true, 2056 resultInArg0: true, 2057 usesScratch: true, 2058 asm: x86.AADDSS, 2059 reg: regInfo{ 2060 inputs: []inputInfo{ 2061 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2062 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2063 }, 2064 outputs: []outputInfo{ 2065 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2066 }, 2067 }, 2068 }, 2069 { 2070 name: "ADDSD", 2071 argLen: 2, 2072 commutative: true, 2073 resultInArg0: true, 2074 asm: x86.AADDSD, 2075 reg: regInfo{ 2076 inputs: []inputInfo{ 2077 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2078 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2079 }, 2080 outputs: []outputInfo{ 2081 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2082 }, 2083 }, 2084 }, 2085 { 2086 name: "SUBSS", 2087 argLen: 2, 2088 resultInArg0: true, 2089 usesScratch: true, 2090 asm: x86.ASUBSS, 2091 reg: regInfo{ 2092 inputs: []inputInfo{ 2093 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2094 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2095 }, 2096 outputs: []outputInfo{ 2097 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2098 }, 2099 }, 2100 }, 2101 { 2102 name: "SUBSD", 2103 argLen: 2, 2104 resultInArg0: true, 2105 asm: x86.ASUBSD, 2106 reg: regInfo{ 2107 inputs: []inputInfo{ 2108 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2109 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2110 }, 2111 outputs: []outputInfo{ 2112 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2113 }, 2114 }, 2115 }, 2116 { 2117 name: "MULSS", 2118 argLen: 2, 2119 commutative: true, 2120 resultInArg0: true, 2121 usesScratch: true, 2122 asm: x86.AMULSS, 2123 reg: regInfo{ 2124 inputs: []inputInfo{ 2125 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2126 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2127 }, 2128 outputs: []outputInfo{ 2129 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2130 }, 2131 }, 2132 }, 2133 { 2134 name: "MULSD", 2135 argLen: 2, 2136 commutative: true, 2137 resultInArg0: true, 2138 asm: x86.AMULSD, 2139 reg: regInfo{ 2140 inputs: []inputInfo{ 2141 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2142 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2143 }, 2144 outputs: []outputInfo{ 2145 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2146 }, 2147 }, 2148 }, 2149 { 2150 name: "DIVSS", 2151 argLen: 2, 2152 resultInArg0: true, 2153 usesScratch: true, 2154 asm: x86.ADIVSS, 2155 reg: regInfo{ 2156 inputs: []inputInfo{ 2157 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2158 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2159 }, 2160 outputs: []outputInfo{ 2161 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2162 }, 2163 }, 2164 }, 2165 { 2166 name: "DIVSD", 2167 argLen: 2, 2168 resultInArg0: true, 2169 asm: x86.ADIVSD, 2170 reg: regInfo{ 2171 inputs: []inputInfo{ 2172 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2173 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2174 }, 2175 outputs: []outputInfo{ 2176 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2177 }, 2178 }, 2179 }, 2180 { 2181 name: "MOVSSload", 2182 auxType: auxSymOff, 2183 argLen: 2, 2184 faultOnNilArg0: true, 2185 symEffect: SymRead, 2186 asm: x86.AMOVSS, 2187 reg: regInfo{ 2188 inputs: []inputInfo{ 2189 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2190 }, 2191 outputs: []outputInfo{ 2192 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2193 }, 2194 }, 2195 }, 2196 { 2197 name: "MOVSDload", 2198 auxType: auxSymOff, 2199 argLen: 2, 2200 faultOnNilArg0: true, 2201 symEffect: SymRead, 2202 asm: x86.AMOVSD, 2203 reg: regInfo{ 2204 inputs: []inputInfo{ 2205 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2206 }, 2207 outputs: []outputInfo{ 2208 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2209 }, 2210 }, 2211 }, 2212 { 2213 name: "MOVSSconst", 2214 auxType: auxFloat32, 2215 argLen: 0, 2216 rematerializeable: true, 2217 asm: x86.AMOVSS, 2218 reg: regInfo{ 2219 outputs: []outputInfo{ 2220 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2221 }, 2222 }, 2223 }, 2224 { 2225 name: "MOVSDconst", 2226 auxType: auxFloat64, 2227 argLen: 0, 2228 rematerializeable: true, 2229 asm: x86.AMOVSD, 2230 reg: regInfo{ 2231 outputs: []outputInfo{ 2232 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2233 }, 2234 }, 2235 }, 2236 { 2237 name: "MOVSSloadidx1", 2238 auxType: auxSymOff, 2239 argLen: 3, 2240 symEffect: SymRead, 2241 asm: x86.AMOVSS, 2242 reg: regInfo{ 2243 inputs: []inputInfo{ 2244 {1, 255}, // AX CX DX BX SP BP SI DI 2245 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2246 }, 2247 outputs: []outputInfo{ 2248 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2249 }, 2250 }, 2251 }, 2252 { 2253 name: "MOVSSloadidx4", 2254 auxType: auxSymOff, 2255 argLen: 3, 2256 symEffect: SymRead, 2257 asm: x86.AMOVSS, 2258 reg: regInfo{ 2259 inputs: []inputInfo{ 2260 {1, 255}, // AX CX DX BX SP BP SI DI 2261 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2262 }, 2263 outputs: []outputInfo{ 2264 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2265 }, 2266 }, 2267 }, 2268 { 2269 name: "MOVSDloadidx1", 2270 auxType: auxSymOff, 2271 argLen: 3, 2272 symEffect: SymRead, 2273 asm: x86.AMOVSD, 2274 reg: regInfo{ 2275 inputs: []inputInfo{ 2276 {1, 255}, // AX CX DX BX SP BP SI DI 2277 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2278 }, 2279 outputs: []outputInfo{ 2280 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2281 }, 2282 }, 2283 }, 2284 { 2285 name: "MOVSDloadidx8", 2286 auxType: auxSymOff, 2287 argLen: 3, 2288 symEffect: SymRead, 2289 asm: x86.AMOVSD, 2290 reg: regInfo{ 2291 inputs: []inputInfo{ 2292 {1, 255}, // AX CX DX BX SP BP SI DI 2293 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2294 }, 2295 outputs: []outputInfo{ 2296 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2297 }, 2298 }, 2299 }, 2300 { 2301 name: "MOVSSstore", 2302 auxType: auxSymOff, 2303 argLen: 3, 2304 faultOnNilArg0: true, 2305 symEffect: SymWrite, 2306 asm: x86.AMOVSS, 2307 reg: regInfo{ 2308 inputs: []inputInfo{ 2309 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2310 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2311 }, 2312 }, 2313 }, 2314 { 2315 name: "MOVSDstore", 2316 auxType: auxSymOff, 2317 argLen: 3, 2318 faultOnNilArg0: true, 2319 symEffect: SymWrite, 2320 asm: x86.AMOVSD, 2321 reg: regInfo{ 2322 inputs: []inputInfo{ 2323 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2324 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2325 }, 2326 }, 2327 }, 2328 { 2329 name: "MOVSSstoreidx1", 2330 auxType: auxSymOff, 2331 argLen: 4, 2332 symEffect: SymWrite, 2333 asm: x86.AMOVSS, 2334 reg: regInfo{ 2335 inputs: []inputInfo{ 2336 {1, 255}, // AX CX DX BX SP BP SI DI 2337 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2338 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2339 }, 2340 }, 2341 }, 2342 { 2343 name: "MOVSSstoreidx4", 2344 auxType: auxSymOff, 2345 argLen: 4, 2346 symEffect: SymWrite, 2347 asm: x86.AMOVSS, 2348 reg: regInfo{ 2349 inputs: []inputInfo{ 2350 {1, 255}, // AX CX DX BX SP BP SI DI 2351 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2352 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2353 }, 2354 }, 2355 }, 2356 { 2357 name: "MOVSDstoreidx1", 2358 auxType: auxSymOff, 2359 argLen: 4, 2360 symEffect: SymWrite, 2361 asm: x86.AMOVSD, 2362 reg: regInfo{ 2363 inputs: []inputInfo{ 2364 {1, 255}, // AX CX DX BX SP BP SI DI 2365 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2366 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2367 }, 2368 }, 2369 }, 2370 { 2371 name: "MOVSDstoreidx8", 2372 auxType: auxSymOff, 2373 argLen: 4, 2374 symEffect: SymWrite, 2375 asm: x86.AMOVSD, 2376 reg: regInfo{ 2377 inputs: []inputInfo{ 2378 {1, 255}, // AX CX DX BX SP BP SI DI 2379 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2380 {0, 65791}, // AX CX DX BX SP BP SI DI SB 2381 }, 2382 }, 2383 }, 2384 { 2385 name: "ADDL", 2386 argLen: 2, 2387 commutative: true, 2388 clobberFlags: true, 2389 asm: x86.AADDL, 2390 reg: regInfo{ 2391 inputs: []inputInfo{ 2392 {1, 239}, // AX CX DX BX BP SI DI 2393 {0, 255}, // AX CX DX BX SP BP SI DI 2394 }, 2395 outputs: []outputInfo{ 2396 {0, 239}, // AX CX DX BX BP SI DI 2397 }, 2398 }, 2399 }, 2400 { 2401 name: "ADDLconst", 2402 auxType: auxInt32, 2403 argLen: 1, 2404 clobberFlags: true, 2405 asm: x86.AADDL, 2406 reg: regInfo{ 2407 inputs: []inputInfo{ 2408 {0, 255}, // AX CX DX BX SP BP SI DI 2409 }, 2410 outputs: []outputInfo{ 2411 {0, 239}, // AX CX DX BX BP SI DI 2412 }, 2413 }, 2414 }, 2415 { 2416 name: "ADDLcarry", 2417 argLen: 2, 2418 commutative: true, 2419 resultInArg0: true, 2420 asm: x86.AADDL, 2421 reg: regInfo{ 2422 inputs: []inputInfo{ 2423 {0, 239}, // AX CX DX BX BP SI DI 2424 {1, 239}, // AX CX DX BX BP SI DI 2425 }, 2426 outputs: []outputInfo{ 2427 {1, 0}, 2428 {0, 239}, // AX CX DX BX BP SI DI 2429 }, 2430 }, 2431 }, 2432 { 2433 name: "ADDLconstcarry", 2434 auxType: auxInt32, 2435 argLen: 1, 2436 resultInArg0: true, 2437 asm: x86.AADDL, 2438 reg: regInfo{ 2439 inputs: []inputInfo{ 2440 {0, 239}, // AX CX DX BX BP SI DI 2441 }, 2442 outputs: []outputInfo{ 2443 {1, 0}, 2444 {0, 239}, // AX CX DX BX BP SI DI 2445 }, 2446 }, 2447 }, 2448 { 2449 name: "ADCL", 2450 argLen: 3, 2451 commutative: true, 2452 resultInArg0: true, 2453 clobberFlags: true, 2454 asm: x86.AADCL, 2455 reg: regInfo{ 2456 inputs: []inputInfo{ 2457 {0, 239}, // AX CX DX BX BP SI DI 2458 {1, 239}, // AX CX DX BX BP SI DI 2459 }, 2460 outputs: []outputInfo{ 2461 {0, 239}, // AX CX DX BX BP SI DI 2462 }, 2463 }, 2464 }, 2465 { 2466 name: "ADCLconst", 2467 auxType: auxInt32, 2468 argLen: 2, 2469 resultInArg0: true, 2470 clobberFlags: true, 2471 asm: x86.AADCL, 2472 reg: regInfo{ 2473 inputs: []inputInfo{ 2474 {0, 239}, // AX CX DX BX BP SI DI 2475 }, 2476 outputs: []outputInfo{ 2477 {0, 239}, // AX CX DX BX BP SI DI 2478 }, 2479 }, 2480 }, 2481 { 2482 name: "SUBL", 2483 argLen: 2, 2484 resultInArg0: true, 2485 clobberFlags: true, 2486 asm: x86.ASUBL, 2487 reg: regInfo{ 2488 inputs: []inputInfo{ 2489 {0, 239}, // AX CX DX BX BP SI DI 2490 {1, 239}, // AX CX DX BX BP SI DI 2491 }, 2492 outputs: []outputInfo{ 2493 {0, 239}, // AX CX DX BX BP SI DI 2494 }, 2495 }, 2496 }, 2497 { 2498 name: "SUBLconst", 2499 auxType: auxInt32, 2500 argLen: 1, 2501 resultInArg0: true, 2502 clobberFlags: true, 2503 asm: x86.ASUBL, 2504 reg: regInfo{ 2505 inputs: []inputInfo{ 2506 {0, 239}, // AX CX DX BX BP SI DI 2507 }, 2508 outputs: []outputInfo{ 2509 {0, 239}, // AX CX DX BX BP SI DI 2510 }, 2511 }, 2512 }, 2513 { 2514 name: "SUBLcarry", 2515 argLen: 2, 2516 resultInArg0: true, 2517 asm: x86.ASUBL, 2518 reg: regInfo{ 2519 inputs: []inputInfo{ 2520 {0, 239}, // AX CX DX BX BP SI DI 2521 {1, 239}, // AX CX DX BX BP SI DI 2522 }, 2523 outputs: []outputInfo{ 2524 {1, 0}, 2525 {0, 239}, // AX CX DX BX BP SI DI 2526 }, 2527 }, 2528 }, 2529 { 2530 name: "SUBLconstcarry", 2531 auxType: auxInt32, 2532 argLen: 1, 2533 resultInArg0: true, 2534 asm: x86.ASUBL, 2535 reg: regInfo{ 2536 inputs: []inputInfo{ 2537 {0, 239}, // AX CX DX BX BP SI DI 2538 }, 2539 outputs: []outputInfo{ 2540 {1, 0}, 2541 {0, 239}, // AX CX DX BX BP SI DI 2542 }, 2543 }, 2544 }, 2545 { 2546 name: "SBBL", 2547 argLen: 3, 2548 resultInArg0: true, 2549 clobberFlags: true, 2550 asm: x86.ASBBL, 2551 reg: regInfo{ 2552 inputs: []inputInfo{ 2553 {0, 239}, // AX CX DX BX BP SI DI 2554 {1, 239}, // AX CX DX BX BP SI DI 2555 }, 2556 outputs: []outputInfo{ 2557 {0, 239}, // AX CX DX BX BP SI DI 2558 }, 2559 }, 2560 }, 2561 { 2562 name: "SBBLconst", 2563 auxType: auxInt32, 2564 argLen: 2, 2565 resultInArg0: true, 2566 clobberFlags: true, 2567 asm: x86.ASBBL, 2568 reg: regInfo{ 2569 inputs: []inputInfo{ 2570 {0, 239}, // AX CX DX BX BP SI DI 2571 }, 2572 outputs: []outputInfo{ 2573 {0, 239}, // AX CX DX BX BP SI DI 2574 }, 2575 }, 2576 }, 2577 { 2578 name: "MULL", 2579 argLen: 2, 2580 commutative: true, 2581 resultInArg0: true, 2582 clobberFlags: true, 2583 asm: x86.AIMULL, 2584 reg: regInfo{ 2585 inputs: []inputInfo{ 2586 {0, 239}, // AX CX DX BX BP SI DI 2587 {1, 239}, // AX CX DX BX BP SI DI 2588 }, 2589 outputs: []outputInfo{ 2590 {0, 239}, // AX CX DX BX BP SI DI 2591 }, 2592 }, 2593 }, 2594 { 2595 name: "MULLconst", 2596 auxType: auxInt32, 2597 argLen: 1, 2598 resultInArg0: true, 2599 clobberFlags: true, 2600 asm: x86.AIMULL, 2601 reg: regInfo{ 2602 inputs: []inputInfo{ 2603 {0, 239}, // AX CX DX BX BP SI DI 2604 }, 2605 outputs: []outputInfo{ 2606 {0, 239}, // AX CX DX BX BP SI DI 2607 }, 2608 }, 2609 }, 2610 { 2611 name: "HMULL", 2612 argLen: 2, 2613 commutative: true, 2614 clobberFlags: true, 2615 asm: x86.AIMULL, 2616 reg: regInfo{ 2617 inputs: []inputInfo{ 2618 {0, 1}, // AX 2619 {1, 255}, // AX CX DX BX SP BP SI DI 2620 }, 2621 clobbers: 1, // AX 2622 outputs: []outputInfo{ 2623 {0, 4}, // DX 2624 }, 2625 }, 2626 }, 2627 { 2628 name: "HMULLU", 2629 argLen: 2, 2630 commutative: true, 2631 clobberFlags: true, 2632 asm: x86.AMULL, 2633 reg: regInfo{ 2634 inputs: []inputInfo{ 2635 {0, 1}, // AX 2636 {1, 255}, // AX CX DX BX SP BP SI DI 2637 }, 2638 clobbers: 1, // AX 2639 outputs: []outputInfo{ 2640 {0, 4}, // DX 2641 }, 2642 }, 2643 }, 2644 { 2645 name: "MULLQU", 2646 argLen: 2, 2647 commutative: true, 2648 clobberFlags: true, 2649 asm: x86.AMULL, 2650 reg: regInfo{ 2651 inputs: []inputInfo{ 2652 {0, 1}, // AX 2653 {1, 255}, // AX CX DX BX SP BP SI DI 2654 }, 2655 outputs: []outputInfo{ 2656 {0, 4}, // DX 2657 {1, 1}, // AX 2658 }, 2659 }, 2660 }, 2661 { 2662 name: "AVGLU", 2663 argLen: 2, 2664 commutative: true, 2665 resultInArg0: true, 2666 clobberFlags: true, 2667 reg: regInfo{ 2668 inputs: []inputInfo{ 2669 {0, 239}, // AX CX DX BX BP SI DI 2670 {1, 239}, // AX CX DX BX BP SI DI 2671 }, 2672 outputs: []outputInfo{ 2673 {0, 239}, // AX CX DX BX BP SI DI 2674 }, 2675 }, 2676 }, 2677 { 2678 name: "DIVL", 2679 argLen: 2, 2680 clobberFlags: true, 2681 asm: x86.AIDIVL, 2682 reg: regInfo{ 2683 inputs: []inputInfo{ 2684 {0, 1}, // AX 2685 {1, 251}, // AX CX BX SP BP SI DI 2686 }, 2687 clobbers: 4, // DX 2688 outputs: []outputInfo{ 2689 {0, 1}, // AX 2690 }, 2691 }, 2692 }, 2693 { 2694 name: "DIVW", 2695 argLen: 2, 2696 clobberFlags: true, 2697 asm: x86.AIDIVW, 2698 reg: regInfo{ 2699 inputs: []inputInfo{ 2700 {0, 1}, // AX 2701 {1, 251}, // AX CX BX SP BP SI DI 2702 }, 2703 clobbers: 4, // DX 2704 outputs: []outputInfo{ 2705 {0, 1}, // AX 2706 }, 2707 }, 2708 }, 2709 { 2710 name: "DIVLU", 2711 argLen: 2, 2712 clobberFlags: true, 2713 asm: x86.ADIVL, 2714 reg: regInfo{ 2715 inputs: []inputInfo{ 2716 {0, 1}, // AX 2717 {1, 251}, // AX CX BX SP BP SI DI 2718 }, 2719 clobbers: 4, // DX 2720 outputs: []outputInfo{ 2721 {0, 1}, // AX 2722 }, 2723 }, 2724 }, 2725 { 2726 name: "DIVWU", 2727 argLen: 2, 2728 clobberFlags: true, 2729 asm: x86.ADIVW, 2730 reg: regInfo{ 2731 inputs: []inputInfo{ 2732 {0, 1}, // AX 2733 {1, 251}, // AX CX BX SP BP SI DI 2734 }, 2735 clobbers: 4, // DX 2736 outputs: []outputInfo{ 2737 {0, 1}, // AX 2738 }, 2739 }, 2740 }, 2741 { 2742 name: "MODL", 2743 argLen: 2, 2744 clobberFlags: true, 2745 asm: x86.AIDIVL, 2746 reg: regInfo{ 2747 inputs: []inputInfo{ 2748 {0, 1}, // AX 2749 {1, 251}, // AX CX BX SP BP SI DI 2750 }, 2751 clobbers: 1, // AX 2752 outputs: []outputInfo{ 2753 {0, 4}, // DX 2754 }, 2755 }, 2756 }, 2757 { 2758 name: "MODW", 2759 argLen: 2, 2760 clobberFlags: true, 2761 asm: x86.AIDIVW, 2762 reg: regInfo{ 2763 inputs: []inputInfo{ 2764 {0, 1}, // AX 2765 {1, 251}, // AX CX BX SP BP SI DI 2766 }, 2767 clobbers: 1, // AX 2768 outputs: []outputInfo{ 2769 {0, 4}, // DX 2770 }, 2771 }, 2772 }, 2773 { 2774 name: "MODLU", 2775 argLen: 2, 2776 clobberFlags: true, 2777 asm: x86.ADIVL, 2778 reg: regInfo{ 2779 inputs: []inputInfo{ 2780 {0, 1}, // AX 2781 {1, 251}, // AX CX BX SP BP SI DI 2782 }, 2783 clobbers: 1, // AX 2784 outputs: []outputInfo{ 2785 {0, 4}, // DX 2786 }, 2787 }, 2788 }, 2789 { 2790 name: "MODWU", 2791 argLen: 2, 2792 clobberFlags: true, 2793 asm: x86.ADIVW, 2794 reg: regInfo{ 2795 inputs: []inputInfo{ 2796 {0, 1}, // AX 2797 {1, 251}, // AX CX BX SP BP SI DI 2798 }, 2799 clobbers: 1, // AX 2800 outputs: []outputInfo{ 2801 {0, 4}, // DX 2802 }, 2803 }, 2804 }, 2805 { 2806 name: "ANDL", 2807 argLen: 2, 2808 commutative: true, 2809 resultInArg0: true, 2810 clobberFlags: true, 2811 asm: x86.AANDL, 2812 reg: regInfo{ 2813 inputs: []inputInfo{ 2814 {0, 239}, // AX CX DX BX BP SI DI 2815 {1, 239}, // AX CX DX BX BP SI DI 2816 }, 2817 outputs: []outputInfo{ 2818 {0, 239}, // AX CX DX BX BP SI DI 2819 }, 2820 }, 2821 }, 2822 { 2823 name: "ANDLconst", 2824 auxType: auxInt32, 2825 argLen: 1, 2826 resultInArg0: true, 2827 clobberFlags: true, 2828 asm: x86.AANDL, 2829 reg: regInfo{ 2830 inputs: []inputInfo{ 2831 {0, 239}, // AX CX DX BX BP SI DI 2832 }, 2833 outputs: []outputInfo{ 2834 {0, 239}, // AX CX DX BX BP SI DI 2835 }, 2836 }, 2837 }, 2838 { 2839 name: "ORL", 2840 argLen: 2, 2841 commutative: true, 2842 resultInArg0: true, 2843 clobberFlags: true, 2844 asm: x86.AORL, 2845 reg: regInfo{ 2846 inputs: []inputInfo{ 2847 {0, 239}, // AX CX DX BX BP SI DI 2848 {1, 239}, // AX CX DX BX BP SI DI 2849 }, 2850 outputs: []outputInfo{ 2851 {0, 239}, // AX CX DX BX BP SI DI 2852 }, 2853 }, 2854 }, 2855 { 2856 name: "ORLconst", 2857 auxType: auxInt32, 2858 argLen: 1, 2859 resultInArg0: true, 2860 clobberFlags: true, 2861 asm: x86.AORL, 2862 reg: regInfo{ 2863 inputs: []inputInfo{ 2864 {0, 239}, // AX CX DX BX BP SI DI 2865 }, 2866 outputs: []outputInfo{ 2867 {0, 239}, // AX CX DX BX BP SI DI 2868 }, 2869 }, 2870 }, 2871 { 2872 name: "XORL", 2873 argLen: 2, 2874 commutative: true, 2875 resultInArg0: true, 2876 clobberFlags: true, 2877 asm: x86.AXORL, 2878 reg: regInfo{ 2879 inputs: []inputInfo{ 2880 {0, 239}, // AX CX DX BX BP SI DI 2881 {1, 239}, // AX CX DX BX BP SI DI 2882 }, 2883 outputs: []outputInfo{ 2884 {0, 239}, // AX CX DX BX BP SI DI 2885 }, 2886 }, 2887 }, 2888 { 2889 name: "XORLconst", 2890 auxType: auxInt32, 2891 argLen: 1, 2892 resultInArg0: true, 2893 clobberFlags: true, 2894 asm: x86.AXORL, 2895 reg: regInfo{ 2896 inputs: []inputInfo{ 2897 {0, 239}, // AX CX DX BX BP SI DI 2898 }, 2899 outputs: []outputInfo{ 2900 {0, 239}, // AX CX DX BX BP SI DI 2901 }, 2902 }, 2903 }, 2904 { 2905 name: "CMPL", 2906 argLen: 2, 2907 asm: x86.ACMPL, 2908 reg: regInfo{ 2909 inputs: []inputInfo{ 2910 {0, 255}, // AX CX DX BX SP BP SI DI 2911 {1, 255}, // AX CX DX BX SP BP SI DI 2912 }, 2913 }, 2914 }, 2915 { 2916 name: "CMPW", 2917 argLen: 2, 2918 asm: x86.ACMPW, 2919 reg: regInfo{ 2920 inputs: []inputInfo{ 2921 {0, 255}, // AX CX DX BX SP BP SI DI 2922 {1, 255}, // AX CX DX BX SP BP SI DI 2923 }, 2924 }, 2925 }, 2926 { 2927 name: "CMPB", 2928 argLen: 2, 2929 asm: x86.ACMPB, 2930 reg: regInfo{ 2931 inputs: []inputInfo{ 2932 {0, 255}, // AX CX DX BX SP BP SI DI 2933 {1, 255}, // AX CX DX BX SP BP SI DI 2934 }, 2935 }, 2936 }, 2937 { 2938 name: "CMPLconst", 2939 auxType: auxInt32, 2940 argLen: 1, 2941 asm: x86.ACMPL, 2942 reg: regInfo{ 2943 inputs: []inputInfo{ 2944 {0, 255}, // AX CX DX BX SP BP SI DI 2945 }, 2946 }, 2947 }, 2948 { 2949 name: "CMPWconst", 2950 auxType: auxInt16, 2951 argLen: 1, 2952 asm: x86.ACMPW, 2953 reg: regInfo{ 2954 inputs: []inputInfo{ 2955 {0, 255}, // AX CX DX BX SP BP SI DI 2956 }, 2957 }, 2958 }, 2959 { 2960 name: "CMPBconst", 2961 auxType: auxInt8, 2962 argLen: 1, 2963 asm: x86.ACMPB, 2964 reg: regInfo{ 2965 inputs: []inputInfo{ 2966 {0, 255}, // AX CX DX BX SP BP SI DI 2967 }, 2968 }, 2969 }, 2970 { 2971 name: "UCOMISS", 2972 argLen: 2, 2973 usesScratch: true, 2974 asm: x86.AUCOMISS, 2975 reg: regInfo{ 2976 inputs: []inputInfo{ 2977 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2978 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2979 }, 2980 }, 2981 }, 2982 { 2983 name: "UCOMISD", 2984 argLen: 2, 2985 usesScratch: true, 2986 asm: x86.AUCOMISD, 2987 reg: regInfo{ 2988 inputs: []inputInfo{ 2989 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2990 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2991 }, 2992 }, 2993 }, 2994 { 2995 name: "TESTL", 2996 argLen: 2, 2997 commutative: true, 2998 asm: x86.ATESTL, 2999 reg: regInfo{ 3000 inputs: []inputInfo{ 3001 {0, 255}, // AX CX DX BX SP BP SI DI 3002 {1, 255}, // AX CX DX BX SP BP SI DI 3003 }, 3004 }, 3005 }, 3006 { 3007 name: "TESTW", 3008 argLen: 2, 3009 commutative: true, 3010 asm: x86.ATESTW, 3011 reg: regInfo{ 3012 inputs: []inputInfo{ 3013 {0, 255}, // AX CX DX BX SP BP SI DI 3014 {1, 255}, // AX CX DX BX SP BP SI DI 3015 }, 3016 }, 3017 }, 3018 { 3019 name: "TESTB", 3020 argLen: 2, 3021 commutative: true, 3022 asm: x86.ATESTB, 3023 reg: regInfo{ 3024 inputs: []inputInfo{ 3025 {0, 255}, // AX CX DX BX SP BP SI DI 3026 {1, 255}, // AX CX DX BX SP BP SI DI 3027 }, 3028 }, 3029 }, 3030 { 3031 name: "TESTLconst", 3032 auxType: auxInt32, 3033 argLen: 1, 3034 asm: x86.ATESTL, 3035 reg: regInfo{ 3036 inputs: []inputInfo{ 3037 {0, 255}, // AX CX DX BX SP BP SI DI 3038 }, 3039 }, 3040 }, 3041 { 3042 name: "TESTWconst", 3043 auxType: auxInt16, 3044 argLen: 1, 3045 asm: x86.ATESTW, 3046 reg: regInfo{ 3047 inputs: []inputInfo{ 3048 {0, 255}, // AX CX DX BX SP BP SI DI 3049 }, 3050 }, 3051 }, 3052 { 3053 name: "TESTBconst", 3054 auxType: auxInt8, 3055 argLen: 1, 3056 asm: x86.ATESTB, 3057 reg: regInfo{ 3058 inputs: []inputInfo{ 3059 {0, 255}, // AX CX DX BX SP BP SI DI 3060 }, 3061 }, 3062 }, 3063 { 3064 name: "SHLL", 3065 argLen: 2, 3066 resultInArg0: true, 3067 clobberFlags: true, 3068 asm: x86.ASHLL, 3069 reg: regInfo{ 3070 inputs: []inputInfo{ 3071 {1, 2}, // CX 3072 {0, 239}, // AX CX DX BX BP SI DI 3073 }, 3074 outputs: []outputInfo{ 3075 {0, 239}, // AX CX DX BX BP SI DI 3076 }, 3077 }, 3078 }, 3079 { 3080 name: "SHLLconst", 3081 auxType: auxInt32, 3082 argLen: 1, 3083 resultInArg0: true, 3084 clobberFlags: true, 3085 asm: x86.ASHLL, 3086 reg: regInfo{ 3087 inputs: []inputInfo{ 3088 {0, 239}, // AX CX DX BX BP SI DI 3089 }, 3090 outputs: []outputInfo{ 3091 {0, 239}, // AX CX DX BX BP SI DI 3092 }, 3093 }, 3094 }, 3095 { 3096 name: "SHRL", 3097 argLen: 2, 3098 resultInArg0: true, 3099 clobberFlags: true, 3100 asm: x86.ASHRL, 3101 reg: regInfo{ 3102 inputs: []inputInfo{ 3103 {1, 2}, // CX 3104 {0, 239}, // AX CX DX BX BP SI DI 3105 }, 3106 outputs: []outputInfo{ 3107 {0, 239}, // AX CX DX BX BP SI DI 3108 }, 3109 }, 3110 }, 3111 { 3112 name: "SHRW", 3113 argLen: 2, 3114 resultInArg0: true, 3115 clobberFlags: true, 3116 asm: x86.ASHRW, 3117 reg: regInfo{ 3118 inputs: []inputInfo{ 3119 {1, 2}, // CX 3120 {0, 239}, // AX CX DX BX BP SI DI 3121 }, 3122 outputs: []outputInfo{ 3123 {0, 239}, // AX CX DX BX BP SI DI 3124 }, 3125 }, 3126 }, 3127 { 3128 name: "SHRB", 3129 argLen: 2, 3130 resultInArg0: true, 3131 clobberFlags: true, 3132 asm: x86.ASHRB, 3133 reg: regInfo{ 3134 inputs: []inputInfo{ 3135 {1, 2}, // CX 3136 {0, 239}, // AX CX DX BX BP SI DI 3137 }, 3138 outputs: []outputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 }, 3142 }, 3143 { 3144 name: "SHRLconst", 3145 auxType: auxInt32, 3146 argLen: 1, 3147 resultInArg0: true, 3148 clobberFlags: true, 3149 asm: x86.ASHRL, 3150 reg: regInfo{ 3151 inputs: []inputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 outputs: []outputInfo{ 3155 {0, 239}, // AX CX DX BX BP SI DI 3156 }, 3157 }, 3158 }, 3159 { 3160 name: "SHRWconst", 3161 auxType: auxInt16, 3162 argLen: 1, 3163 resultInArg0: true, 3164 clobberFlags: true, 3165 asm: x86.ASHRW, 3166 reg: regInfo{ 3167 inputs: []inputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 outputs: []outputInfo{ 3171 {0, 239}, // AX CX DX BX BP SI DI 3172 }, 3173 }, 3174 }, 3175 { 3176 name: "SHRBconst", 3177 auxType: auxInt8, 3178 argLen: 1, 3179 resultInArg0: true, 3180 clobberFlags: true, 3181 asm: x86.ASHRB, 3182 reg: regInfo{ 3183 inputs: []inputInfo{ 3184 {0, 239}, // AX CX DX BX BP SI DI 3185 }, 3186 outputs: []outputInfo{ 3187 {0, 239}, // AX CX DX BX BP SI DI 3188 }, 3189 }, 3190 }, 3191 { 3192 name: "SARL", 3193 argLen: 2, 3194 resultInArg0: true, 3195 clobberFlags: true, 3196 asm: x86.ASARL, 3197 reg: regInfo{ 3198 inputs: []inputInfo{ 3199 {1, 2}, // CX 3200 {0, 239}, // AX CX DX BX BP SI DI 3201 }, 3202 outputs: []outputInfo{ 3203 {0, 239}, // AX CX DX BX BP SI DI 3204 }, 3205 }, 3206 }, 3207 { 3208 name: "SARW", 3209 argLen: 2, 3210 resultInArg0: true, 3211 clobberFlags: true, 3212 asm: x86.ASARW, 3213 reg: regInfo{ 3214 inputs: []inputInfo{ 3215 {1, 2}, // CX 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 outputs: []outputInfo{ 3219 {0, 239}, // AX CX DX BX BP SI DI 3220 }, 3221 }, 3222 }, 3223 { 3224 name: "SARB", 3225 argLen: 2, 3226 resultInArg0: true, 3227 clobberFlags: true, 3228 asm: x86.ASARB, 3229 reg: regInfo{ 3230 inputs: []inputInfo{ 3231 {1, 2}, // CX 3232 {0, 239}, // AX CX DX BX BP SI DI 3233 }, 3234 outputs: []outputInfo{ 3235 {0, 239}, // AX CX DX BX BP SI DI 3236 }, 3237 }, 3238 }, 3239 { 3240 name: "SARLconst", 3241 auxType: auxInt32, 3242 argLen: 1, 3243 resultInArg0: true, 3244 clobberFlags: true, 3245 asm: x86.ASARL, 3246 reg: regInfo{ 3247 inputs: []inputInfo{ 3248 {0, 239}, // AX CX DX BX BP SI DI 3249 }, 3250 outputs: []outputInfo{ 3251 {0, 239}, // AX CX DX BX BP SI DI 3252 }, 3253 }, 3254 }, 3255 { 3256 name: "SARWconst", 3257 auxType: auxInt16, 3258 argLen: 1, 3259 resultInArg0: true, 3260 clobberFlags: true, 3261 asm: x86.ASARW, 3262 reg: regInfo{ 3263 inputs: []inputInfo{ 3264 {0, 239}, // AX CX DX BX BP SI DI 3265 }, 3266 outputs: []outputInfo{ 3267 {0, 239}, // AX CX DX BX BP SI DI 3268 }, 3269 }, 3270 }, 3271 { 3272 name: "SARBconst", 3273 auxType: auxInt8, 3274 argLen: 1, 3275 resultInArg0: true, 3276 clobberFlags: true, 3277 asm: x86.ASARB, 3278 reg: regInfo{ 3279 inputs: []inputInfo{ 3280 {0, 239}, // AX CX DX BX BP SI DI 3281 }, 3282 outputs: []outputInfo{ 3283 {0, 239}, // AX CX DX BX BP SI DI 3284 }, 3285 }, 3286 }, 3287 { 3288 name: "ROLLconst", 3289 auxType: auxInt32, 3290 argLen: 1, 3291 resultInArg0: true, 3292 clobberFlags: true, 3293 asm: x86.AROLL, 3294 reg: regInfo{ 3295 inputs: []inputInfo{ 3296 {0, 239}, // AX CX DX BX BP SI DI 3297 }, 3298 outputs: []outputInfo{ 3299 {0, 239}, // AX CX DX BX BP SI DI 3300 }, 3301 }, 3302 }, 3303 { 3304 name: "ROLWconst", 3305 auxType: auxInt16, 3306 argLen: 1, 3307 resultInArg0: true, 3308 clobberFlags: true, 3309 asm: x86.AROLW, 3310 reg: regInfo{ 3311 inputs: []inputInfo{ 3312 {0, 239}, // AX CX DX BX BP SI DI 3313 }, 3314 outputs: []outputInfo{ 3315 {0, 239}, // AX CX DX BX BP SI DI 3316 }, 3317 }, 3318 }, 3319 { 3320 name: "ROLBconst", 3321 auxType: auxInt8, 3322 argLen: 1, 3323 resultInArg0: true, 3324 clobberFlags: true, 3325 asm: x86.AROLB, 3326 reg: regInfo{ 3327 inputs: []inputInfo{ 3328 {0, 239}, // AX CX DX BX BP SI DI 3329 }, 3330 outputs: []outputInfo{ 3331 {0, 239}, // AX CX DX BX BP SI DI 3332 }, 3333 }, 3334 }, 3335 { 3336 name: "NEGL", 3337 argLen: 1, 3338 resultInArg0: true, 3339 clobberFlags: true, 3340 asm: x86.ANEGL, 3341 reg: regInfo{ 3342 inputs: []inputInfo{ 3343 {0, 239}, // AX CX DX BX BP SI DI 3344 }, 3345 outputs: []outputInfo{ 3346 {0, 239}, // AX CX DX BX BP SI DI 3347 }, 3348 }, 3349 }, 3350 { 3351 name: "NOTL", 3352 argLen: 1, 3353 resultInArg0: true, 3354 clobberFlags: true, 3355 asm: x86.ANOTL, 3356 reg: regInfo{ 3357 inputs: []inputInfo{ 3358 {0, 239}, // AX CX DX BX BP SI DI 3359 }, 3360 outputs: []outputInfo{ 3361 {0, 239}, // AX CX DX BX BP SI DI 3362 }, 3363 }, 3364 }, 3365 { 3366 name: "BSFL", 3367 argLen: 1, 3368 clobberFlags: true, 3369 asm: x86.ABSFL, 3370 reg: regInfo{ 3371 inputs: []inputInfo{ 3372 {0, 239}, // AX CX DX BX BP SI DI 3373 }, 3374 outputs: []outputInfo{ 3375 {0, 239}, // AX CX DX BX BP SI DI 3376 }, 3377 }, 3378 }, 3379 { 3380 name: "BSFW", 3381 argLen: 1, 3382 clobberFlags: true, 3383 asm: x86.ABSFW, 3384 reg: regInfo{ 3385 inputs: []inputInfo{ 3386 {0, 239}, // AX CX DX BX BP SI DI 3387 }, 3388 outputs: []outputInfo{ 3389 {0, 239}, // AX CX DX BX BP SI DI 3390 }, 3391 }, 3392 }, 3393 { 3394 name: "BSRL", 3395 argLen: 1, 3396 clobberFlags: true, 3397 asm: x86.ABSRL, 3398 reg: regInfo{ 3399 inputs: []inputInfo{ 3400 {0, 239}, // AX CX DX BX BP SI DI 3401 }, 3402 outputs: []outputInfo{ 3403 {0, 239}, // AX CX DX BX BP SI DI 3404 }, 3405 }, 3406 }, 3407 { 3408 name: "BSRW", 3409 argLen: 1, 3410 clobberFlags: true, 3411 asm: x86.ABSRW, 3412 reg: regInfo{ 3413 inputs: []inputInfo{ 3414 {0, 239}, // AX CX DX BX BP SI DI 3415 }, 3416 outputs: []outputInfo{ 3417 {0, 239}, // AX CX DX BX BP SI DI 3418 }, 3419 }, 3420 }, 3421 { 3422 name: "BSWAPL", 3423 argLen: 1, 3424 resultInArg0: true, 3425 clobberFlags: true, 3426 asm: x86.ABSWAPL, 3427 reg: regInfo{ 3428 inputs: []inputInfo{ 3429 {0, 239}, // AX CX DX BX BP SI DI 3430 }, 3431 outputs: []outputInfo{ 3432 {0, 239}, // AX CX DX BX BP SI DI 3433 }, 3434 }, 3435 }, 3436 { 3437 name: "SQRTSD", 3438 argLen: 1, 3439 asm: x86.ASQRTSD, 3440 reg: regInfo{ 3441 inputs: []inputInfo{ 3442 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3443 }, 3444 outputs: []outputInfo{ 3445 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3446 }, 3447 }, 3448 }, 3449 { 3450 name: "SBBLcarrymask", 3451 argLen: 1, 3452 asm: x86.ASBBL, 3453 reg: regInfo{ 3454 outputs: []outputInfo{ 3455 {0, 239}, // AX CX DX BX BP SI DI 3456 }, 3457 }, 3458 }, 3459 { 3460 name: "SETEQ", 3461 argLen: 1, 3462 asm: x86.ASETEQ, 3463 reg: regInfo{ 3464 outputs: []outputInfo{ 3465 {0, 239}, // AX CX DX BX BP SI DI 3466 }, 3467 }, 3468 }, 3469 { 3470 name: "SETNE", 3471 argLen: 1, 3472 asm: x86.ASETNE, 3473 reg: regInfo{ 3474 outputs: []outputInfo{ 3475 {0, 239}, // AX CX DX BX BP SI DI 3476 }, 3477 }, 3478 }, 3479 { 3480 name: "SETL", 3481 argLen: 1, 3482 asm: x86.ASETLT, 3483 reg: regInfo{ 3484 outputs: []outputInfo{ 3485 {0, 239}, // AX CX DX BX BP SI DI 3486 }, 3487 }, 3488 }, 3489 { 3490 name: "SETLE", 3491 argLen: 1, 3492 asm: x86.ASETLE, 3493 reg: regInfo{ 3494 outputs: []outputInfo{ 3495 {0, 239}, // AX CX DX BX BP SI DI 3496 }, 3497 }, 3498 }, 3499 { 3500 name: "SETG", 3501 argLen: 1, 3502 asm: x86.ASETGT, 3503 reg: regInfo{ 3504 outputs: []outputInfo{ 3505 {0, 239}, // AX CX DX BX BP SI DI 3506 }, 3507 }, 3508 }, 3509 { 3510 name: "SETGE", 3511 argLen: 1, 3512 asm: x86.ASETGE, 3513 reg: regInfo{ 3514 outputs: []outputInfo{ 3515 {0, 239}, // AX CX DX BX BP SI DI 3516 }, 3517 }, 3518 }, 3519 { 3520 name: "SETB", 3521 argLen: 1, 3522 asm: x86.ASETCS, 3523 reg: regInfo{ 3524 outputs: []outputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 }, 3528 }, 3529 { 3530 name: "SETBE", 3531 argLen: 1, 3532 asm: x86.ASETLS, 3533 reg: regInfo{ 3534 outputs: []outputInfo{ 3535 {0, 239}, // AX CX DX BX BP SI DI 3536 }, 3537 }, 3538 }, 3539 { 3540 name: "SETA", 3541 argLen: 1, 3542 asm: x86.ASETHI, 3543 reg: regInfo{ 3544 outputs: []outputInfo{ 3545 {0, 239}, // AX CX DX BX BP SI DI 3546 }, 3547 }, 3548 }, 3549 { 3550 name: "SETAE", 3551 argLen: 1, 3552 asm: x86.ASETCC, 3553 reg: regInfo{ 3554 outputs: []outputInfo{ 3555 {0, 239}, // AX CX DX BX BP SI DI 3556 }, 3557 }, 3558 }, 3559 { 3560 name: "SETEQF", 3561 argLen: 1, 3562 clobberFlags: true, 3563 asm: x86.ASETEQ, 3564 reg: regInfo{ 3565 clobbers: 1, // AX 3566 outputs: []outputInfo{ 3567 {0, 238}, // CX DX BX BP SI DI 3568 }, 3569 }, 3570 }, 3571 { 3572 name: "SETNEF", 3573 argLen: 1, 3574 clobberFlags: true, 3575 asm: x86.ASETNE, 3576 reg: regInfo{ 3577 clobbers: 1, // AX 3578 outputs: []outputInfo{ 3579 {0, 238}, // CX DX BX BP SI DI 3580 }, 3581 }, 3582 }, 3583 { 3584 name: "SETORD", 3585 argLen: 1, 3586 asm: x86.ASETPC, 3587 reg: regInfo{ 3588 outputs: []outputInfo{ 3589 {0, 239}, // AX CX DX BX BP SI DI 3590 }, 3591 }, 3592 }, 3593 { 3594 name: "SETNAN", 3595 argLen: 1, 3596 asm: x86.ASETPS, 3597 reg: regInfo{ 3598 outputs: []outputInfo{ 3599 {0, 239}, // AX CX DX BX BP SI DI 3600 }, 3601 }, 3602 }, 3603 { 3604 name: "SETGF", 3605 argLen: 1, 3606 asm: x86.ASETHI, 3607 reg: regInfo{ 3608 outputs: []outputInfo{ 3609 {0, 239}, // AX CX DX BX BP SI DI 3610 }, 3611 }, 3612 }, 3613 { 3614 name: "SETGEF", 3615 argLen: 1, 3616 asm: x86.ASETCC, 3617 reg: regInfo{ 3618 outputs: []outputInfo{ 3619 {0, 239}, // AX CX DX BX BP SI DI 3620 }, 3621 }, 3622 }, 3623 { 3624 name: "MOVBLSX", 3625 argLen: 1, 3626 asm: x86.AMOVBLSX, 3627 reg: regInfo{ 3628 inputs: []inputInfo{ 3629 {0, 239}, // AX CX DX BX BP SI DI 3630 }, 3631 outputs: []outputInfo{ 3632 {0, 239}, // AX CX DX BX BP SI DI 3633 }, 3634 }, 3635 }, 3636 { 3637 name: "MOVBLZX", 3638 argLen: 1, 3639 asm: x86.AMOVBLZX, 3640 reg: regInfo{ 3641 inputs: []inputInfo{ 3642 {0, 239}, // AX CX DX BX BP SI DI 3643 }, 3644 outputs: []outputInfo{ 3645 {0, 239}, // AX CX DX BX BP SI DI 3646 }, 3647 }, 3648 }, 3649 { 3650 name: "MOVWLSX", 3651 argLen: 1, 3652 asm: x86.AMOVWLSX, 3653 reg: regInfo{ 3654 inputs: []inputInfo{ 3655 {0, 239}, // AX CX DX BX BP SI DI 3656 }, 3657 outputs: []outputInfo{ 3658 {0, 239}, // AX CX DX BX BP SI DI 3659 }, 3660 }, 3661 }, 3662 { 3663 name: "MOVWLZX", 3664 argLen: 1, 3665 asm: x86.AMOVWLZX, 3666 reg: regInfo{ 3667 inputs: []inputInfo{ 3668 {0, 239}, // AX CX DX BX BP SI DI 3669 }, 3670 outputs: []outputInfo{ 3671 {0, 239}, // AX CX DX BX BP SI DI 3672 }, 3673 }, 3674 }, 3675 { 3676 name: "MOVLconst", 3677 auxType: auxInt32, 3678 argLen: 0, 3679 rematerializeable: true, 3680 asm: x86.AMOVL, 3681 reg: regInfo{ 3682 outputs: []outputInfo{ 3683 {0, 239}, // AX CX DX BX BP SI DI 3684 }, 3685 }, 3686 }, 3687 { 3688 name: "CVTTSD2SL", 3689 argLen: 1, 3690 usesScratch: true, 3691 asm: x86.ACVTTSD2SL, 3692 reg: regInfo{ 3693 inputs: []inputInfo{ 3694 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3695 }, 3696 outputs: []outputInfo{ 3697 {0, 239}, // AX CX DX BX BP SI DI 3698 }, 3699 }, 3700 }, 3701 { 3702 name: "CVTTSS2SL", 3703 argLen: 1, 3704 usesScratch: true, 3705 asm: x86.ACVTTSS2SL, 3706 reg: regInfo{ 3707 inputs: []inputInfo{ 3708 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3709 }, 3710 outputs: []outputInfo{ 3711 {0, 239}, // AX CX DX BX BP SI DI 3712 }, 3713 }, 3714 }, 3715 { 3716 name: "CVTSL2SS", 3717 argLen: 1, 3718 usesScratch: true, 3719 asm: x86.ACVTSL2SS, 3720 reg: regInfo{ 3721 inputs: []inputInfo{ 3722 {0, 239}, // AX CX DX BX BP SI DI 3723 }, 3724 outputs: []outputInfo{ 3725 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3726 }, 3727 }, 3728 }, 3729 { 3730 name: "CVTSL2SD", 3731 argLen: 1, 3732 usesScratch: true, 3733 asm: x86.ACVTSL2SD, 3734 reg: regInfo{ 3735 inputs: []inputInfo{ 3736 {0, 239}, // AX CX DX BX BP SI DI 3737 }, 3738 outputs: []outputInfo{ 3739 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3740 }, 3741 }, 3742 }, 3743 { 3744 name: "CVTSD2SS", 3745 argLen: 1, 3746 usesScratch: true, 3747 asm: x86.ACVTSD2SS, 3748 reg: regInfo{ 3749 inputs: []inputInfo{ 3750 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3751 }, 3752 outputs: []outputInfo{ 3753 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3754 }, 3755 }, 3756 }, 3757 { 3758 name: "CVTSS2SD", 3759 argLen: 1, 3760 asm: x86.ACVTSS2SD, 3761 reg: regInfo{ 3762 inputs: []inputInfo{ 3763 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3764 }, 3765 outputs: []outputInfo{ 3766 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3767 }, 3768 }, 3769 }, 3770 { 3771 name: "PXOR", 3772 argLen: 2, 3773 commutative: true, 3774 resultInArg0: true, 3775 asm: x86.APXOR, 3776 reg: regInfo{ 3777 inputs: []inputInfo{ 3778 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3779 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3780 }, 3781 outputs: []outputInfo{ 3782 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3783 }, 3784 }, 3785 }, 3786 { 3787 name: "LEAL", 3788 auxType: auxSymOff, 3789 argLen: 1, 3790 rematerializeable: true, 3791 symEffect: SymAddr, 3792 reg: regInfo{ 3793 inputs: []inputInfo{ 3794 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3795 }, 3796 outputs: []outputInfo{ 3797 {0, 239}, // AX CX DX BX BP SI DI 3798 }, 3799 }, 3800 }, 3801 { 3802 name: "LEAL1", 3803 auxType: auxSymOff, 3804 argLen: 2, 3805 commutative: true, 3806 symEffect: SymAddr, 3807 reg: regInfo{ 3808 inputs: []inputInfo{ 3809 {1, 255}, // AX CX DX BX SP BP SI DI 3810 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3811 }, 3812 outputs: []outputInfo{ 3813 {0, 239}, // AX CX DX BX BP SI DI 3814 }, 3815 }, 3816 }, 3817 { 3818 name: "LEAL2", 3819 auxType: auxSymOff, 3820 argLen: 2, 3821 symEffect: SymAddr, 3822 reg: regInfo{ 3823 inputs: []inputInfo{ 3824 {1, 255}, // AX CX DX BX SP BP SI DI 3825 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3826 }, 3827 outputs: []outputInfo{ 3828 {0, 239}, // AX CX DX BX BP SI DI 3829 }, 3830 }, 3831 }, 3832 { 3833 name: "LEAL4", 3834 auxType: auxSymOff, 3835 argLen: 2, 3836 symEffect: SymAddr, 3837 reg: regInfo{ 3838 inputs: []inputInfo{ 3839 {1, 255}, // AX CX DX BX SP BP SI DI 3840 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3841 }, 3842 outputs: []outputInfo{ 3843 {0, 239}, // AX CX DX BX BP SI DI 3844 }, 3845 }, 3846 }, 3847 { 3848 name: "LEAL8", 3849 auxType: auxSymOff, 3850 argLen: 2, 3851 symEffect: SymAddr, 3852 reg: regInfo{ 3853 inputs: []inputInfo{ 3854 {1, 255}, // AX CX DX BX SP BP SI DI 3855 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3856 }, 3857 outputs: []outputInfo{ 3858 {0, 239}, // AX CX DX BX BP SI DI 3859 }, 3860 }, 3861 }, 3862 { 3863 name: "MOVBload", 3864 auxType: auxSymOff, 3865 argLen: 2, 3866 faultOnNilArg0: true, 3867 symEffect: SymRead, 3868 asm: x86.AMOVBLZX, 3869 reg: regInfo{ 3870 inputs: []inputInfo{ 3871 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3872 }, 3873 outputs: []outputInfo{ 3874 {0, 239}, // AX CX DX BX BP SI DI 3875 }, 3876 }, 3877 }, 3878 { 3879 name: "MOVBLSXload", 3880 auxType: auxSymOff, 3881 argLen: 2, 3882 faultOnNilArg0: true, 3883 symEffect: SymRead, 3884 asm: x86.AMOVBLSX, 3885 reg: regInfo{ 3886 inputs: []inputInfo{ 3887 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3888 }, 3889 outputs: []outputInfo{ 3890 {0, 239}, // AX CX DX BX BP SI DI 3891 }, 3892 }, 3893 }, 3894 { 3895 name: "MOVWload", 3896 auxType: auxSymOff, 3897 argLen: 2, 3898 faultOnNilArg0: true, 3899 symEffect: SymRead, 3900 asm: x86.AMOVWLZX, 3901 reg: regInfo{ 3902 inputs: []inputInfo{ 3903 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3904 }, 3905 outputs: []outputInfo{ 3906 {0, 239}, // AX CX DX BX BP SI DI 3907 }, 3908 }, 3909 }, 3910 { 3911 name: "MOVWLSXload", 3912 auxType: auxSymOff, 3913 argLen: 2, 3914 faultOnNilArg0: true, 3915 symEffect: SymRead, 3916 asm: x86.AMOVWLSX, 3917 reg: regInfo{ 3918 inputs: []inputInfo{ 3919 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3920 }, 3921 outputs: []outputInfo{ 3922 {0, 239}, // AX CX DX BX BP SI DI 3923 }, 3924 }, 3925 }, 3926 { 3927 name: "MOVLload", 3928 auxType: auxSymOff, 3929 argLen: 2, 3930 faultOnNilArg0: true, 3931 symEffect: SymRead, 3932 asm: x86.AMOVL, 3933 reg: regInfo{ 3934 inputs: []inputInfo{ 3935 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3936 }, 3937 outputs: []outputInfo{ 3938 {0, 239}, // AX CX DX BX BP SI DI 3939 }, 3940 }, 3941 }, 3942 { 3943 name: "MOVBstore", 3944 auxType: auxSymOff, 3945 argLen: 3, 3946 faultOnNilArg0: true, 3947 symEffect: SymWrite, 3948 asm: x86.AMOVB, 3949 reg: regInfo{ 3950 inputs: []inputInfo{ 3951 {1, 255}, // AX CX DX BX SP BP SI DI 3952 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3953 }, 3954 }, 3955 }, 3956 { 3957 name: "MOVWstore", 3958 auxType: auxSymOff, 3959 argLen: 3, 3960 faultOnNilArg0: true, 3961 symEffect: SymWrite, 3962 asm: x86.AMOVW, 3963 reg: regInfo{ 3964 inputs: []inputInfo{ 3965 {1, 255}, // AX CX DX BX SP BP SI DI 3966 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3967 }, 3968 }, 3969 }, 3970 { 3971 name: "MOVLstore", 3972 auxType: auxSymOff, 3973 argLen: 3, 3974 faultOnNilArg0: true, 3975 symEffect: SymWrite, 3976 asm: x86.AMOVL, 3977 reg: regInfo{ 3978 inputs: []inputInfo{ 3979 {1, 255}, // AX CX DX BX SP BP SI DI 3980 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3981 }, 3982 }, 3983 }, 3984 { 3985 name: "MOVBloadidx1", 3986 auxType: auxSymOff, 3987 argLen: 3, 3988 commutative: true, 3989 symEffect: SymRead, 3990 asm: x86.AMOVBLZX, 3991 reg: regInfo{ 3992 inputs: []inputInfo{ 3993 {1, 255}, // AX CX DX BX SP BP SI DI 3994 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3995 }, 3996 outputs: []outputInfo{ 3997 {0, 239}, // AX CX DX BX BP SI DI 3998 }, 3999 }, 4000 }, 4001 { 4002 name: "MOVWloadidx1", 4003 auxType: auxSymOff, 4004 argLen: 3, 4005 commutative: true, 4006 symEffect: SymRead, 4007 asm: x86.AMOVWLZX, 4008 reg: regInfo{ 4009 inputs: []inputInfo{ 4010 {1, 255}, // AX CX DX BX SP BP SI DI 4011 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4012 }, 4013 outputs: []outputInfo{ 4014 {0, 239}, // AX CX DX BX BP SI DI 4015 }, 4016 }, 4017 }, 4018 { 4019 name: "MOVWloadidx2", 4020 auxType: auxSymOff, 4021 argLen: 3, 4022 symEffect: SymRead, 4023 asm: x86.AMOVWLZX, 4024 reg: regInfo{ 4025 inputs: []inputInfo{ 4026 {1, 255}, // AX CX DX BX SP BP SI DI 4027 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4028 }, 4029 outputs: []outputInfo{ 4030 {0, 239}, // AX CX DX BX BP SI DI 4031 }, 4032 }, 4033 }, 4034 { 4035 name: "MOVLloadidx1", 4036 auxType: auxSymOff, 4037 argLen: 3, 4038 commutative: true, 4039 symEffect: SymRead, 4040 asm: x86.AMOVL, 4041 reg: regInfo{ 4042 inputs: []inputInfo{ 4043 {1, 255}, // AX CX DX BX SP BP SI DI 4044 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4045 }, 4046 outputs: []outputInfo{ 4047 {0, 239}, // AX CX DX BX BP SI DI 4048 }, 4049 }, 4050 }, 4051 { 4052 name: "MOVLloadidx4", 4053 auxType: auxSymOff, 4054 argLen: 3, 4055 symEffect: SymRead, 4056 asm: x86.AMOVL, 4057 reg: regInfo{ 4058 inputs: []inputInfo{ 4059 {1, 255}, // AX CX DX BX SP BP SI DI 4060 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4061 }, 4062 outputs: []outputInfo{ 4063 {0, 239}, // AX CX DX BX BP SI DI 4064 }, 4065 }, 4066 }, 4067 { 4068 name: "MOVBstoreidx1", 4069 auxType: auxSymOff, 4070 argLen: 4, 4071 commutative: true, 4072 symEffect: SymWrite, 4073 asm: x86.AMOVB, 4074 reg: regInfo{ 4075 inputs: []inputInfo{ 4076 {1, 255}, // AX CX DX BX SP BP SI DI 4077 {2, 255}, // AX CX DX BX SP BP SI DI 4078 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4079 }, 4080 }, 4081 }, 4082 { 4083 name: "MOVWstoreidx1", 4084 auxType: auxSymOff, 4085 argLen: 4, 4086 commutative: true, 4087 symEffect: SymWrite, 4088 asm: x86.AMOVW, 4089 reg: regInfo{ 4090 inputs: []inputInfo{ 4091 {1, 255}, // AX CX DX BX SP BP SI DI 4092 {2, 255}, // AX CX DX BX SP BP SI DI 4093 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4094 }, 4095 }, 4096 }, 4097 { 4098 name: "MOVWstoreidx2", 4099 auxType: auxSymOff, 4100 argLen: 4, 4101 symEffect: SymWrite, 4102 asm: x86.AMOVW, 4103 reg: regInfo{ 4104 inputs: []inputInfo{ 4105 {1, 255}, // AX CX DX BX SP BP SI DI 4106 {2, 255}, // AX CX DX BX SP BP SI DI 4107 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4108 }, 4109 }, 4110 }, 4111 { 4112 name: "MOVLstoreidx1", 4113 auxType: auxSymOff, 4114 argLen: 4, 4115 commutative: true, 4116 symEffect: SymWrite, 4117 asm: x86.AMOVL, 4118 reg: regInfo{ 4119 inputs: []inputInfo{ 4120 {1, 255}, // AX CX DX BX SP BP SI DI 4121 {2, 255}, // AX CX DX BX SP BP SI DI 4122 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4123 }, 4124 }, 4125 }, 4126 { 4127 name: "MOVLstoreidx4", 4128 auxType: auxSymOff, 4129 argLen: 4, 4130 symEffect: SymWrite, 4131 asm: x86.AMOVL, 4132 reg: regInfo{ 4133 inputs: []inputInfo{ 4134 {1, 255}, // AX CX DX BX SP BP SI DI 4135 {2, 255}, // AX CX DX BX SP BP SI DI 4136 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4137 }, 4138 }, 4139 }, 4140 { 4141 name: "MOVBstoreconst", 4142 auxType: auxSymValAndOff, 4143 argLen: 2, 4144 faultOnNilArg0: true, 4145 symEffect: SymWrite, 4146 asm: x86.AMOVB, 4147 reg: regInfo{ 4148 inputs: []inputInfo{ 4149 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4150 }, 4151 }, 4152 }, 4153 { 4154 name: "MOVWstoreconst", 4155 auxType: auxSymValAndOff, 4156 argLen: 2, 4157 faultOnNilArg0: true, 4158 symEffect: SymWrite, 4159 asm: x86.AMOVW, 4160 reg: regInfo{ 4161 inputs: []inputInfo{ 4162 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4163 }, 4164 }, 4165 }, 4166 { 4167 name: "MOVLstoreconst", 4168 auxType: auxSymValAndOff, 4169 argLen: 2, 4170 faultOnNilArg0: true, 4171 symEffect: SymWrite, 4172 asm: x86.AMOVL, 4173 reg: regInfo{ 4174 inputs: []inputInfo{ 4175 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4176 }, 4177 }, 4178 }, 4179 { 4180 name: "MOVBstoreconstidx1", 4181 auxType: auxSymValAndOff, 4182 argLen: 3, 4183 symEffect: SymWrite, 4184 asm: x86.AMOVB, 4185 reg: regInfo{ 4186 inputs: []inputInfo{ 4187 {1, 255}, // AX CX DX BX SP BP SI DI 4188 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4189 }, 4190 }, 4191 }, 4192 { 4193 name: "MOVWstoreconstidx1", 4194 auxType: auxSymValAndOff, 4195 argLen: 3, 4196 symEffect: SymWrite, 4197 asm: x86.AMOVW, 4198 reg: regInfo{ 4199 inputs: []inputInfo{ 4200 {1, 255}, // AX CX DX BX SP BP SI DI 4201 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4202 }, 4203 }, 4204 }, 4205 { 4206 name: "MOVWstoreconstidx2", 4207 auxType: auxSymValAndOff, 4208 argLen: 3, 4209 symEffect: SymWrite, 4210 asm: x86.AMOVW, 4211 reg: regInfo{ 4212 inputs: []inputInfo{ 4213 {1, 255}, // AX CX DX BX SP BP SI DI 4214 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4215 }, 4216 }, 4217 }, 4218 { 4219 name: "MOVLstoreconstidx1", 4220 auxType: auxSymValAndOff, 4221 argLen: 3, 4222 symEffect: SymWrite, 4223 asm: x86.AMOVL, 4224 reg: regInfo{ 4225 inputs: []inputInfo{ 4226 {1, 255}, // AX CX DX BX SP BP SI DI 4227 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4228 }, 4229 }, 4230 }, 4231 { 4232 name: "MOVLstoreconstidx4", 4233 auxType: auxSymValAndOff, 4234 argLen: 3, 4235 symEffect: SymWrite, 4236 asm: x86.AMOVL, 4237 reg: regInfo{ 4238 inputs: []inputInfo{ 4239 {1, 255}, // AX CX DX BX SP BP SI DI 4240 {0, 65791}, // AX CX DX BX SP BP SI DI SB 4241 }, 4242 }, 4243 }, 4244 { 4245 name: "DUFFZERO", 4246 auxType: auxInt64, 4247 argLen: 3, 4248 faultOnNilArg0: true, 4249 reg: regInfo{ 4250 inputs: []inputInfo{ 4251 {0, 128}, // DI 4252 {1, 1}, // AX 4253 }, 4254 clobbers: 130, // CX DI 4255 }, 4256 }, 4257 { 4258 name: "REPSTOSL", 4259 argLen: 4, 4260 faultOnNilArg0: true, 4261 reg: regInfo{ 4262 inputs: []inputInfo{ 4263 {0, 128}, // DI 4264 {1, 2}, // CX 4265 {2, 1}, // AX 4266 }, 4267 clobbers: 130, // CX DI 4268 }, 4269 }, 4270 { 4271 name: "CALLstatic", 4272 auxType: auxSymOff, 4273 argLen: 1, 4274 clobberFlags: true, 4275 call: true, 4276 symEffect: SymNone, 4277 reg: regInfo{ 4278 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4279 }, 4280 }, 4281 { 4282 name: "CALLclosure", 4283 auxType: auxInt64, 4284 argLen: 3, 4285 clobberFlags: true, 4286 call: true, 4287 reg: regInfo{ 4288 inputs: []inputInfo{ 4289 {1, 4}, // DX 4290 {0, 255}, // AX CX DX BX SP BP SI DI 4291 }, 4292 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4293 }, 4294 }, 4295 { 4296 name: "CALLinter", 4297 auxType: auxInt64, 4298 argLen: 2, 4299 clobberFlags: true, 4300 call: true, 4301 reg: regInfo{ 4302 inputs: []inputInfo{ 4303 {0, 239}, // AX CX DX BX BP SI DI 4304 }, 4305 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 4306 }, 4307 }, 4308 { 4309 name: "DUFFCOPY", 4310 auxType: auxInt64, 4311 argLen: 3, 4312 clobberFlags: true, 4313 faultOnNilArg0: true, 4314 faultOnNilArg1: true, 4315 reg: regInfo{ 4316 inputs: []inputInfo{ 4317 {0, 128}, // DI 4318 {1, 64}, // SI 4319 }, 4320 clobbers: 194, // CX SI DI 4321 }, 4322 }, 4323 { 4324 name: "REPMOVSL", 4325 argLen: 4, 4326 faultOnNilArg0: true, 4327 faultOnNilArg1: true, 4328 reg: regInfo{ 4329 inputs: []inputInfo{ 4330 {0, 128}, // DI 4331 {1, 64}, // SI 4332 {2, 2}, // CX 4333 }, 4334 clobbers: 194, // CX SI DI 4335 }, 4336 }, 4337 { 4338 name: "InvertFlags", 4339 argLen: 1, 4340 reg: regInfo{}, 4341 }, 4342 { 4343 name: "LoweredGetG", 4344 argLen: 1, 4345 reg: regInfo{ 4346 outputs: []outputInfo{ 4347 {0, 239}, // AX CX DX BX BP SI DI 4348 }, 4349 }, 4350 }, 4351 { 4352 name: "LoweredGetClosurePtr", 4353 argLen: 0, 4354 reg: regInfo{ 4355 outputs: []outputInfo{ 4356 {0, 4}, // DX 4357 }, 4358 }, 4359 }, 4360 { 4361 name: "LoweredGetCallerPC", 4362 argLen: 0, 4363 rematerializeable: true, 4364 reg: regInfo{ 4365 outputs: []outputInfo{ 4366 {0, 239}, // AX CX DX BX BP SI DI 4367 }, 4368 }, 4369 }, 4370 { 4371 name: "LoweredGetCallerSP", 4372 argLen: 0, 4373 rematerializeable: true, 4374 reg: regInfo{ 4375 outputs: []outputInfo{ 4376 {0, 239}, // AX CX DX BX BP SI DI 4377 }, 4378 }, 4379 }, 4380 { 4381 name: "LoweredNilCheck", 4382 argLen: 2, 4383 clobberFlags: true, 4384 nilCheck: true, 4385 faultOnNilArg0: true, 4386 reg: regInfo{ 4387 inputs: []inputInfo{ 4388 {0, 255}, // AX CX DX BX SP BP SI DI 4389 }, 4390 }, 4391 }, 4392 { 4393 name: "MOVLconvert", 4394 argLen: 2, 4395 resultInArg0: true, 4396 asm: x86.AMOVL, 4397 reg: regInfo{ 4398 inputs: []inputInfo{ 4399 {0, 239}, // AX CX DX BX BP SI DI 4400 }, 4401 outputs: []outputInfo{ 4402 {0, 239}, // AX CX DX BX BP SI DI 4403 }, 4404 }, 4405 }, 4406 { 4407 name: "FlagEQ", 4408 argLen: 0, 4409 reg: regInfo{}, 4410 }, 4411 { 4412 name: "FlagLT_ULT", 4413 argLen: 0, 4414 reg: regInfo{}, 4415 }, 4416 { 4417 name: "FlagLT_UGT", 4418 argLen: 0, 4419 reg: regInfo{}, 4420 }, 4421 { 4422 name: "FlagGT_UGT", 4423 argLen: 0, 4424 reg: regInfo{}, 4425 }, 4426 { 4427 name: "FlagGT_ULT", 4428 argLen: 0, 4429 reg: regInfo{}, 4430 }, 4431 { 4432 name: "FCHS", 4433 argLen: 1, 4434 reg: regInfo{ 4435 inputs: []inputInfo{ 4436 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4437 }, 4438 outputs: []outputInfo{ 4439 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4440 }, 4441 }, 4442 }, 4443 { 4444 name: "MOVSSconst1", 4445 auxType: auxFloat32, 4446 argLen: 0, 4447 reg: regInfo{ 4448 outputs: []outputInfo{ 4449 {0, 239}, // AX CX DX BX BP SI DI 4450 }, 4451 }, 4452 }, 4453 { 4454 name: "MOVSDconst1", 4455 auxType: auxFloat64, 4456 argLen: 0, 4457 reg: regInfo{ 4458 outputs: []outputInfo{ 4459 {0, 239}, // AX CX DX BX BP SI DI 4460 }, 4461 }, 4462 }, 4463 { 4464 name: "MOVSSconst2", 4465 argLen: 1, 4466 asm: x86.AMOVSS, 4467 reg: regInfo{ 4468 inputs: []inputInfo{ 4469 {0, 239}, // AX CX DX BX BP SI DI 4470 }, 4471 outputs: []outputInfo{ 4472 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4473 }, 4474 }, 4475 }, 4476 { 4477 name: "MOVSDconst2", 4478 argLen: 1, 4479 asm: x86.AMOVSD, 4480 reg: regInfo{ 4481 inputs: []inputInfo{ 4482 {0, 239}, // AX CX DX BX BP SI DI 4483 }, 4484 outputs: []outputInfo{ 4485 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 4486 }, 4487 }, 4488 }, 4489 4490 { 4491 name: "ADDSS", 4492 argLen: 2, 4493 commutative: true, 4494 resultInArg0: true, 4495 asm: x86.AADDSS, 4496 reg: regInfo{ 4497 inputs: []inputInfo{ 4498 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4499 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4500 }, 4501 outputs: []outputInfo{ 4502 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4503 }, 4504 }, 4505 }, 4506 { 4507 name: "ADDSD", 4508 argLen: 2, 4509 commutative: true, 4510 resultInArg0: true, 4511 asm: x86.AADDSD, 4512 reg: regInfo{ 4513 inputs: []inputInfo{ 4514 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4515 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4516 }, 4517 outputs: []outputInfo{ 4518 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4519 }, 4520 }, 4521 }, 4522 { 4523 name: "SUBSS", 4524 argLen: 2, 4525 resultInArg0: true, 4526 asm: x86.ASUBSS, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4530 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4531 }, 4532 outputs: []outputInfo{ 4533 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4534 }, 4535 }, 4536 }, 4537 { 4538 name: "SUBSD", 4539 argLen: 2, 4540 resultInArg0: true, 4541 asm: x86.ASUBSD, 4542 reg: regInfo{ 4543 inputs: []inputInfo{ 4544 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4545 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4546 }, 4547 outputs: []outputInfo{ 4548 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4549 }, 4550 }, 4551 }, 4552 { 4553 name: "MULSS", 4554 argLen: 2, 4555 commutative: true, 4556 resultInArg0: true, 4557 asm: x86.AMULSS, 4558 reg: regInfo{ 4559 inputs: []inputInfo{ 4560 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4561 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4562 }, 4563 outputs: []outputInfo{ 4564 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4565 }, 4566 }, 4567 }, 4568 { 4569 name: "MULSD", 4570 argLen: 2, 4571 commutative: true, 4572 resultInArg0: true, 4573 asm: x86.AMULSD, 4574 reg: regInfo{ 4575 inputs: []inputInfo{ 4576 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4577 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4578 }, 4579 outputs: []outputInfo{ 4580 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4581 }, 4582 }, 4583 }, 4584 { 4585 name: "DIVSS", 4586 argLen: 2, 4587 resultInArg0: true, 4588 asm: x86.ADIVSS, 4589 reg: regInfo{ 4590 inputs: []inputInfo{ 4591 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4592 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4593 }, 4594 outputs: []outputInfo{ 4595 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4596 }, 4597 }, 4598 }, 4599 { 4600 name: "DIVSD", 4601 argLen: 2, 4602 resultInArg0: true, 4603 asm: x86.ADIVSD, 4604 reg: regInfo{ 4605 inputs: []inputInfo{ 4606 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4607 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4608 }, 4609 outputs: []outputInfo{ 4610 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4611 }, 4612 }, 4613 }, 4614 { 4615 name: "MOVSSload", 4616 auxType: auxSymOff, 4617 argLen: 2, 4618 faultOnNilArg0: true, 4619 symEffect: SymRead, 4620 asm: x86.AMOVSS, 4621 reg: regInfo{ 4622 inputs: []inputInfo{ 4623 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4624 }, 4625 outputs: []outputInfo{ 4626 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4627 }, 4628 }, 4629 }, 4630 { 4631 name: "MOVSDload", 4632 auxType: auxSymOff, 4633 argLen: 2, 4634 faultOnNilArg0: true, 4635 symEffect: SymRead, 4636 asm: x86.AMOVSD, 4637 reg: regInfo{ 4638 inputs: []inputInfo{ 4639 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4640 }, 4641 outputs: []outputInfo{ 4642 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4643 }, 4644 }, 4645 }, 4646 { 4647 name: "MOVSSconst", 4648 auxType: auxFloat32, 4649 argLen: 0, 4650 rematerializeable: true, 4651 asm: x86.AMOVSS, 4652 reg: regInfo{ 4653 outputs: []outputInfo{ 4654 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4655 }, 4656 }, 4657 }, 4658 { 4659 name: "MOVSDconst", 4660 auxType: auxFloat64, 4661 argLen: 0, 4662 rematerializeable: true, 4663 asm: x86.AMOVSD, 4664 reg: regInfo{ 4665 outputs: []outputInfo{ 4666 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4667 }, 4668 }, 4669 }, 4670 { 4671 name: "MOVSSloadidx1", 4672 auxType: auxSymOff, 4673 argLen: 3, 4674 symEffect: SymRead, 4675 asm: x86.AMOVSS, 4676 reg: regInfo{ 4677 inputs: []inputInfo{ 4678 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4679 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4680 }, 4681 outputs: []outputInfo{ 4682 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4683 }, 4684 }, 4685 }, 4686 { 4687 name: "MOVSSloadidx4", 4688 auxType: auxSymOff, 4689 argLen: 3, 4690 symEffect: SymRead, 4691 asm: x86.AMOVSS, 4692 reg: regInfo{ 4693 inputs: []inputInfo{ 4694 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4695 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4696 }, 4697 outputs: []outputInfo{ 4698 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4699 }, 4700 }, 4701 }, 4702 { 4703 name: "MOVSDloadidx1", 4704 auxType: auxSymOff, 4705 argLen: 3, 4706 symEffect: SymRead, 4707 asm: x86.AMOVSD, 4708 reg: regInfo{ 4709 inputs: []inputInfo{ 4710 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4711 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4712 }, 4713 outputs: []outputInfo{ 4714 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4715 }, 4716 }, 4717 }, 4718 { 4719 name: "MOVSDloadidx8", 4720 auxType: auxSymOff, 4721 argLen: 3, 4722 symEffect: SymRead, 4723 asm: x86.AMOVSD, 4724 reg: regInfo{ 4725 inputs: []inputInfo{ 4726 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4727 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4728 }, 4729 outputs: []outputInfo{ 4730 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4731 }, 4732 }, 4733 }, 4734 { 4735 name: "MOVSSstore", 4736 auxType: auxSymOff, 4737 argLen: 3, 4738 faultOnNilArg0: true, 4739 symEffect: SymWrite, 4740 asm: x86.AMOVSS, 4741 reg: regInfo{ 4742 inputs: []inputInfo{ 4743 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4744 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4745 }, 4746 }, 4747 }, 4748 { 4749 name: "MOVSDstore", 4750 auxType: auxSymOff, 4751 argLen: 3, 4752 faultOnNilArg0: true, 4753 symEffect: SymWrite, 4754 asm: x86.AMOVSD, 4755 reg: regInfo{ 4756 inputs: []inputInfo{ 4757 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4758 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4759 }, 4760 }, 4761 }, 4762 { 4763 name: "MOVSSstoreidx1", 4764 auxType: auxSymOff, 4765 argLen: 4, 4766 symEffect: SymWrite, 4767 asm: x86.AMOVSS, 4768 reg: regInfo{ 4769 inputs: []inputInfo{ 4770 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4771 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4772 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4773 }, 4774 }, 4775 }, 4776 { 4777 name: "MOVSSstoreidx4", 4778 auxType: auxSymOff, 4779 argLen: 4, 4780 symEffect: SymWrite, 4781 asm: x86.AMOVSS, 4782 reg: regInfo{ 4783 inputs: []inputInfo{ 4784 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4785 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4786 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4787 }, 4788 }, 4789 }, 4790 { 4791 name: "MOVSDstoreidx1", 4792 auxType: auxSymOff, 4793 argLen: 4, 4794 symEffect: SymWrite, 4795 asm: x86.AMOVSD, 4796 reg: regInfo{ 4797 inputs: []inputInfo{ 4798 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4799 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4800 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4801 }, 4802 }, 4803 }, 4804 { 4805 name: "MOVSDstoreidx8", 4806 auxType: auxSymOff, 4807 argLen: 4, 4808 symEffect: SymWrite, 4809 asm: x86.AMOVSD, 4810 reg: regInfo{ 4811 inputs: []inputInfo{ 4812 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4813 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4814 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4815 }, 4816 }, 4817 }, 4818 { 4819 name: "ADDSSmem", 4820 auxType: auxSymOff, 4821 argLen: 3, 4822 resultInArg0: true, 4823 faultOnNilArg1: true, 4824 symEffect: SymRead, 4825 asm: x86.AADDSS, 4826 reg: regInfo{ 4827 inputs: []inputInfo{ 4828 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4829 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4830 }, 4831 outputs: []outputInfo{ 4832 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4833 }, 4834 }, 4835 }, 4836 { 4837 name: "ADDSDmem", 4838 auxType: auxSymOff, 4839 argLen: 3, 4840 resultInArg0: true, 4841 faultOnNilArg1: true, 4842 symEffect: SymRead, 4843 asm: x86.AADDSD, 4844 reg: regInfo{ 4845 inputs: []inputInfo{ 4846 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4847 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4848 }, 4849 outputs: []outputInfo{ 4850 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4851 }, 4852 }, 4853 }, 4854 { 4855 name: "SUBSSmem", 4856 auxType: auxSymOff, 4857 argLen: 3, 4858 resultInArg0: true, 4859 faultOnNilArg1: true, 4860 symEffect: SymRead, 4861 asm: x86.ASUBSS, 4862 reg: regInfo{ 4863 inputs: []inputInfo{ 4864 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4865 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4866 }, 4867 outputs: []outputInfo{ 4868 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4869 }, 4870 }, 4871 }, 4872 { 4873 name: "SUBSDmem", 4874 auxType: auxSymOff, 4875 argLen: 3, 4876 resultInArg0: true, 4877 faultOnNilArg1: true, 4878 symEffect: SymRead, 4879 asm: x86.ASUBSD, 4880 reg: regInfo{ 4881 inputs: []inputInfo{ 4882 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4883 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4884 }, 4885 outputs: []outputInfo{ 4886 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4887 }, 4888 }, 4889 }, 4890 { 4891 name: "MULSSmem", 4892 auxType: auxSymOff, 4893 argLen: 3, 4894 resultInArg0: true, 4895 faultOnNilArg1: true, 4896 symEffect: SymRead, 4897 asm: x86.AMULSS, 4898 reg: regInfo{ 4899 inputs: []inputInfo{ 4900 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4901 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4902 }, 4903 outputs: []outputInfo{ 4904 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4905 }, 4906 }, 4907 }, 4908 { 4909 name: "MULSDmem", 4910 auxType: auxSymOff, 4911 argLen: 3, 4912 resultInArg0: true, 4913 faultOnNilArg1: true, 4914 symEffect: SymRead, 4915 asm: x86.AMULSD, 4916 reg: regInfo{ 4917 inputs: []inputInfo{ 4918 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4919 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4920 }, 4921 outputs: []outputInfo{ 4922 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4923 }, 4924 }, 4925 }, 4926 { 4927 name: "ADDQ", 4928 argLen: 2, 4929 commutative: true, 4930 clobberFlags: true, 4931 asm: x86.AADDQ, 4932 reg: regInfo{ 4933 inputs: []inputInfo{ 4934 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4935 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4936 }, 4937 outputs: []outputInfo{ 4938 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4939 }, 4940 }, 4941 }, 4942 { 4943 name: "ADDL", 4944 argLen: 2, 4945 commutative: true, 4946 clobberFlags: true, 4947 asm: x86.AADDL, 4948 reg: regInfo{ 4949 inputs: []inputInfo{ 4950 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4951 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4952 }, 4953 outputs: []outputInfo{ 4954 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4955 }, 4956 }, 4957 }, 4958 { 4959 name: "ADDQconst", 4960 auxType: auxInt32, 4961 argLen: 1, 4962 clobberFlags: true, 4963 asm: x86.AADDQ, 4964 reg: regInfo{ 4965 inputs: []inputInfo{ 4966 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4967 }, 4968 outputs: []outputInfo{ 4969 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4970 }, 4971 }, 4972 }, 4973 { 4974 name: "ADDLconst", 4975 auxType: auxInt32, 4976 argLen: 1, 4977 clobberFlags: true, 4978 asm: x86.AADDL, 4979 reg: regInfo{ 4980 inputs: []inputInfo{ 4981 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4982 }, 4983 outputs: []outputInfo{ 4984 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4985 }, 4986 }, 4987 }, 4988 { 4989 name: "ADDQconstmem", 4990 auxType: auxSymValAndOff, 4991 argLen: 2, 4992 clobberFlags: true, 4993 faultOnNilArg0: true, 4994 symEffect: SymWrite, 4995 asm: x86.AADDQ, 4996 reg: regInfo{ 4997 inputs: []inputInfo{ 4998 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4999 }, 5000 }, 5001 }, 5002 { 5003 name: "ADDLconstmem", 5004 auxType: auxSymValAndOff, 5005 argLen: 2, 5006 clobberFlags: true, 5007 faultOnNilArg0: true, 5008 symEffect: SymWrite, 5009 asm: x86.AADDL, 5010 reg: regInfo{ 5011 inputs: []inputInfo{ 5012 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 5013 }, 5014 }, 5015 }, 5016 { 5017 name: "SUBQ", 5018 argLen: 2, 5019 resultInArg0: true, 5020 clobberFlags: true, 5021 asm: x86.ASUBQ, 5022 reg: regInfo{ 5023 inputs: []inputInfo{ 5024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5025 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5026 }, 5027 outputs: []outputInfo{ 5028 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5029 }, 5030 }, 5031 }, 5032 { 5033 name: "SUBL", 5034 argLen: 2, 5035 resultInArg0: true, 5036 clobberFlags: true, 5037 asm: x86.ASUBL, 5038 reg: regInfo{ 5039 inputs: []inputInfo{ 5040 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5041 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5042 }, 5043 outputs: []outputInfo{ 5044 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5045 }, 5046 }, 5047 }, 5048 { 5049 name: "SUBQconst", 5050 auxType: auxInt32, 5051 argLen: 1, 5052 resultInArg0: true, 5053 clobberFlags: true, 5054 asm: x86.ASUBQ, 5055 reg: regInfo{ 5056 inputs: []inputInfo{ 5057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5058 }, 5059 outputs: []outputInfo{ 5060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5061 }, 5062 }, 5063 }, 5064 { 5065 name: "SUBLconst", 5066 auxType: auxInt32, 5067 argLen: 1, 5068 resultInArg0: true, 5069 clobberFlags: true, 5070 asm: x86.ASUBL, 5071 reg: regInfo{ 5072 inputs: []inputInfo{ 5073 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5074 }, 5075 outputs: []outputInfo{ 5076 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5077 }, 5078 }, 5079 }, 5080 { 5081 name: "MULQ", 5082 argLen: 2, 5083 commutative: true, 5084 resultInArg0: true, 5085 clobberFlags: true, 5086 asm: x86.AIMULQ, 5087 reg: regInfo{ 5088 inputs: []inputInfo{ 5089 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5090 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5091 }, 5092 outputs: []outputInfo{ 5093 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5094 }, 5095 }, 5096 }, 5097 { 5098 name: "MULL", 5099 argLen: 2, 5100 commutative: true, 5101 resultInArg0: true, 5102 clobberFlags: true, 5103 asm: x86.AIMULL, 5104 reg: regInfo{ 5105 inputs: []inputInfo{ 5106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5107 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5108 }, 5109 outputs: []outputInfo{ 5110 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5111 }, 5112 }, 5113 }, 5114 { 5115 name: "MULQconst", 5116 auxType: auxInt32, 5117 argLen: 1, 5118 resultInArg0: true, 5119 clobberFlags: true, 5120 asm: x86.AIMULQ, 5121 reg: regInfo{ 5122 inputs: []inputInfo{ 5123 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5124 }, 5125 outputs: []outputInfo{ 5126 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5127 }, 5128 }, 5129 }, 5130 { 5131 name: "MULLconst", 5132 auxType: auxInt32, 5133 argLen: 1, 5134 resultInArg0: true, 5135 clobberFlags: true, 5136 asm: x86.AIMULL, 5137 reg: regInfo{ 5138 inputs: []inputInfo{ 5139 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5140 }, 5141 outputs: []outputInfo{ 5142 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5143 }, 5144 }, 5145 }, 5146 { 5147 name: "HMULQ", 5148 argLen: 2, 5149 commutative: true, 5150 clobberFlags: true, 5151 asm: x86.AIMULQ, 5152 reg: regInfo{ 5153 inputs: []inputInfo{ 5154 {0, 1}, // AX 5155 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5156 }, 5157 clobbers: 1, // AX 5158 outputs: []outputInfo{ 5159 {0, 4}, // DX 5160 }, 5161 }, 5162 }, 5163 { 5164 name: "HMULL", 5165 argLen: 2, 5166 commutative: true, 5167 clobberFlags: true, 5168 asm: x86.AIMULL, 5169 reg: regInfo{ 5170 inputs: []inputInfo{ 5171 {0, 1}, // AX 5172 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5173 }, 5174 clobbers: 1, // AX 5175 outputs: []outputInfo{ 5176 {0, 4}, // DX 5177 }, 5178 }, 5179 }, 5180 { 5181 name: "HMULQU", 5182 argLen: 2, 5183 commutative: true, 5184 clobberFlags: true, 5185 asm: x86.AMULQ, 5186 reg: regInfo{ 5187 inputs: []inputInfo{ 5188 {0, 1}, // AX 5189 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5190 }, 5191 clobbers: 1, // AX 5192 outputs: []outputInfo{ 5193 {0, 4}, // DX 5194 }, 5195 }, 5196 }, 5197 { 5198 name: "HMULLU", 5199 argLen: 2, 5200 commutative: true, 5201 clobberFlags: true, 5202 asm: x86.AMULL, 5203 reg: regInfo{ 5204 inputs: []inputInfo{ 5205 {0, 1}, // AX 5206 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5207 }, 5208 clobbers: 1, // AX 5209 outputs: []outputInfo{ 5210 {0, 4}, // DX 5211 }, 5212 }, 5213 }, 5214 { 5215 name: "AVGQU", 5216 argLen: 2, 5217 commutative: true, 5218 resultInArg0: true, 5219 clobberFlags: true, 5220 reg: regInfo{ 5221 inputs: []inputInfo{ 5222 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5223 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5224 }, 5225 outputs: []outputInfo{ 5226 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5227 }, 5228 }, 5229 }, 5230 { 5231 name: "DIVQ", 5232 argLen: 2, 5233 clobberFlags: true, 5234 asm: x86.AIDIVQ, 5235 reg: regInfo{ 5236 inputs: []inputInfo{ 5237 {0, 1}, // AX 5238 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5239 }, 5240 outputs: []outputInfo{ 5241 {0, 1}, // AX 5242 {1, 4}, // DX 5243 }, 5244 }, 5245 }, 5246 { 5247 name: "DIVL", 5248 argLen: 2, 5249 clobberFlags: true, 5250 asm: x86.AIDIVL, 5251 reg: regInfo{ 5252 inputs: []inputInfo{ 5253 {0, 1}, // AX 5254 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5255 }, 5256 outputs: []outputInfo{ 5257 {0, 1}, // AX 5258 {1, 4}, // DX 5259 }, 5260 }, 5261 }, 5262 { 5263 name: "DIVW", 5264 argLen: 2, 5265 clobberFlags: true, 5266 asm: x86.AIDIVW, 5267 reg: regInfo{ 5268 inputs: []inputInfo{ 5269 {0, 1}, // AX 5270 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5271 }, 5272 outputs: []outputInfo{ 5273 {0, 1}, // AX 5274 {1, 4}, // DX 5275 }, 5276 }, 5277 }, 5278 { 5279 name: "DIVQU", 5280 argLen: 2, 5281 clobberFlags: true, 5282 asm: x86.ADIVQ, 5283 reg: regInfo{ 5284 inputs: []inputInfo{ 5285 {0, 1}, // AX 5286 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5287 }, 5288 outputs: []outputInfo{ 5289 {0, 1}, // AX 5290 {1, 4}, // DX 5291 }, 5292 }, 5293 }, 5294 { 5295 name: "DIVLU", 5296 argLen: 2, 5297 clobberFlags: true, 5298 asm: x86.ADIVL, 5299 reg: regInfo{ 5300 inputs: []inputInfo{ 5301 {0, 1}, // AX 5302 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5303 }, 5304 outputs: []outputInfo{ 5305 {0, 1}, // AX 5306 {1, 4}, // DX 5307 }, 5308 }, 5309 }, 5310 { 5311 name: "DIVWU", 5312 argLen: 2, 5313 clobberFlags: true, 5314 asm: x86.ADIVW, 5315 reg: regInfo{ 5316 inputs: []inputInfo{ 5317 {0, 1}, // AX 5318 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5319 }, 5320 outputs: []outputInfo{ 5321 {0, 1}, // AX 5322 {1, 4}, // DX 5323 }, 5324 }, 5325 }, 5326 { 5327 name: "MULQU2", 5328 argLen: 2, 5329 commutative: true, 5330 clobberFlags: true, 5331 asm: x86.AMULQ, 5332 reg: regInfo{ 5333 inputs: []inputInfo{ 5334 {0, 1}, // AX 5335 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5336 }, 5337 outputs: []outputInfo{ 5338 {0, 4}, // DX 5339 {1, 1}, // AX 5340 }, 5341 }, 5342 }, 5343 { 5344 name: "DIVQU2", 5345 argLen: 3, 5346 clobberFlags: true, 5347 asm: x86.ADIVQ, 5348 reg: regInfo{ 5349 inputs: []inputInfo{ 5350 {0, 4}, // DX 5351 {1, 1}, // AX 5352 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5353 }, 5354 outputs: []outputInfo{ 5355 {0, 1}, // AX 5356 {1, 4}, // DX 5357 }, 5358 }, 5359 }, 5360 { 5361 name: "ANDQ", 5362 argLen: 2, 5363 commutative: true, 5364 resultInArg0: true, 5365 clobberFlags: true, 5366 asm: x86.AANDQ, 5367 reg: regInfo{ 5368 inputs: []inputInfo{ 5369 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5370 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5371 }, 5372 outputs: []outputInfo{ 5373 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5374 }, 5375 }, 5376 }, 5377 { 5378 name: "ANDL", 5379 argLen: 2, 5380 commutative: true, 5381 resultInArg0: true, 5382 clobberFlags: true, 5383 asm: x86.AANDL, 5384 reg: regInfo{ 5385 inputs: []inputInfo{ 5386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5387 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5388 }, 5389 outputs: []outputInfo{ 5390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5391 }, 5392 }, 5393 }, 5394 { 5395 name: "ANDQconst", 5396 auxType: auxInt32, 5397 argLen: 1, 5398 resultInArg0: true, 5399 clobberFlags: true, 5400 asm: x86.AANDQ, 5401 reg: regInfo{ 5402 inputs: []inputInfo{ 5403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5404 }, 5405 outputs: []outputInfo{ 5406 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5407 }, 5408 }, 5409 }, 5410 { 5411 name: "ANDLconst", 5412 auxType: auxInt32, 5413 argLen: 1, 5414 resultInArg0: true, 5415 clobberFlags: true, 5416 asm: x86.AANDL, 5417 reg: regInfo{ 5418 inputs: []inputInfo{ 5419 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5420 }, 5421 outputs: []outputInfo{ 5422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5423 }, 5424 }, 5425 }, 5426 { 5427 name: "ORQ", 5428 argLen: 2, 5429 commutative: true, 5430 resultInArg0: true, 5431 clobberFlags: true, 5432 asm: x86.AORQ, 5433 reg: regInfo{ 5434 inputs: []inputInfo{ 5435 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5436 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5437 }, 5438 outputs: []outputInfo{ 5439 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5440 }, 5441 }, 5442 }, 5443 { 5444 name: "ORL", 5445 argLen: 2, 5446 commutative: true, 5447 resultInArg0: true, 5448 clobberFlags: true, 5449 asm: x86.AORL, 5450 reg: regInfo{ 5451 inputs: []inputInfo{ 5452 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5453 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5454 }, 5455 outputs: []outputInfo{ 5456 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5457 }, 5458 }, 5459 }, 5460 { 5461 name: "ORQconst", 5462 auxType: auxInt32, 5463 argLen: 1, 5464 resultInArg0: true, 5465 clobberFlags: true, 5466 asm: x86.AORQ, 5467 reg: regInfo{ 5468 inputs: []inputInfo{ 5469 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5470 }, 5471 outputs: []outputInfo{ 5472 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5473 }, 5474 }, 5475 }, 5476 { 5477 name: "ORLconst", 5478 auxType: auxInt32, 5479 argLen: 1, 5480 resultInArg0: true, 5481 clobberFlags: true, 5482 asm: x86.AORL, 5483 reg: regInfo{ 5484 inputs: []inputInfo{ 5485 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5486 }, 5487 outputs: []outputInfo{ 5488 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5489 }, 5490 }, 5491 }, 5492 { 5493 name: "XORQ", 5494 argLen: 2, 5495 commutative: true, 5496 resultInArg0: true, 5497 clobberFlags: true, 5498 asm: x86.AXORQ, 5499 reg: regInfo{ 5500 inputs: []inputInfo{ 5501 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5502 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5503 }, 5504 outputs: []outputInfo{ 5505 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5506 }, 5507 }, 5508 }, 5509 { 5510 name: "XORL", 5511 argLen: 2, 5512 commutative: true, 5513 resultInArg0: true, 5514 clobberFlags: true, 5515 asm: x86.AXORL, 5516 reg: regInfo{ 5517 inputs: []inputInfo{ 5518 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5519 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5520 }, 5521 outputs: []outputInfo{ 5522 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5523 }, 5524 }, 5525 }, 5526 { 5527 name: "XORQconst", 5528 auxType: auxInt32, 5529 argLen: 1, 5530 resultInArg0: true, 5531 clobberFlags: true, 5532 asm: x86.AXORQ, 5533 reg: regInfo{ 5534 inputs: []inputInfo{ 5535 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5536 }, 5537 outputs: []outputInfo{ 5538 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5539 }, 5540 }, 5541 }, 5542 { 5543 name: "XORLconst", 5544 auxType: auxInt32, 5545 argLen: 1, 5546 resultInArg0: true, 5547 clobberFlags: true, 5548 asm: x86.AXORL, 5549 reg: regInfo{ 5550 inputs: []inputInfo{ 5551 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5552 }, 5553 outputs: []outputInfo{ 5554 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5555 }, 5556 }, 5557 }, 5558 { 5559 name: "CMPQ", 5560 argLen: 2, 5561 asm: x86.ACMPQ, 5562 reg: regInfo{ 5563 inputs: []inputInfo{ 5564 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5565 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5566 }, 5567 }, 5568 }, 5569 { 5570 name: "CMPL", 5571 argLen: 2, 5572 asm: x86.ACMPL, 5573 reg: regInfo{ 5574 inputs: []inputInfo{ 5575 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5576 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5577 }, 5578 }, 5579 }, 5580 { 5581 name: "CMPW", 5582 argLen: 2, 5583 asm: x86.ACMPW, 5584 reg: regInfo{ 5585 inputs: []inputInfo{ 5586 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5587 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5588 }, 5589 }, 5590 }, 5591 { 5592 name: "CMPB", 5593 argLen: 2, 5594 asm: x86.ACMPB, 5595 reg: regInfo{ 5596 inputs: []inputInfo{ 5597 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5598 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5599 }, 5600 }, 5601 }, 5602 { 5603 name: "CMPQconst", 5604 auxType: auxInt32, 5605 argLen: 1, 5606 asm: x86.ACMPQ, 5607 reg: regInfo{ 5608 inputs: []inputInfo{ 5609 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5610 }, 5611 }, 5612 }, 5613 { 5614 name: "CMPLconst", 5615 auxType: auxInt32, 5616 argLen: 1, 5617 asm: x86.ACMPL, 5618 reg: regInfo{ 5619 inputs: []inputInfo{ 5620 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5621 }, 5622 }, 5623 }, 5624 { 5625 name: "CMPWconst", 5626 auxType: auxInt16, 5627 argLen: 1, 5628 asm: x86.ACMPW, 5629 reg: regInfo{ 5630 inputs: []inputInfo{ 5631 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5632 }, 5633 }, 5634 }, 5635 { 5636 name: "CMPBconst", 5637 auxType: auxInt8, 5638 argLen: 1, 5639 asm: x86.ACMPB, 5640 reg: regInfo{ 5641 inputs: []inputInfo{ 5642 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5643 }, 5644 }, 5645 }, 5646 { 5647 name: "UCOMISS", 5648 argLen: 2, 5649 asm: x86.AUCOMISS, 5650 reg: regInfo{ 5651 inputs: []inputInfo{ 5652 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5653 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5654 }, 5655 }, 5656 }, 5657 { 5658 name: "UCOMISD", 5659 argLen: 2, 5660 asm: x86.AUCOMISD, 5661 reg: regInfo{ 5662 inputs: []inputInfo{ 5663 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5664 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5665 }, 5666 }, 5667 }, 5668 { 5669 name: "BTL", 5670 argLen: 2, 5671 asm: x86.ABTL, 5672 reg: regInfo{ 5673 inputs: []inputInfo{ 5674 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5675 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5676 }, 5677 }, 5678 }, 5679 { 5680 name: "BTQ", 5681 argLen: 2, 5682 asm: x86.ABTQ, 5683 reg: regInfo{ 5684 inputs: []inputInfo{ 5685 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5686 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5687 }, 5688 }, 5689 }, 5690 { 5691 name: "BTLconst", 5692 auxType: auxInt8, 5693 argLen: 1, 5694 asm: x86.ABTL, 5695 reg: regInfo{ 5696 inputs: []inputInfo{ 5697 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5698 }, 5699 }, 5700 }, 5701 { 5702 name: "BTQconst", 5703 auxType: auxInt8, 5704 argLen: 1, 5705 asm: x86.ABTQ, 5706 reg: regInfo{ 5707 inputs: []inputInfo{ 5708 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5709 }, 5710 }, 5711 }, 5712 { 5713 name: "TESTQ", 5714 argLen: 2, 5715 commutative: true, 5716 asm: x86.ATESTQ, 5717 reg: regInfo{ 5718 inputs: []inputInfo{ 5719 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5720 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5721 }, 5722 }, 5723 }, 5724 { 5725 name: "TESTL", 5726 argLen: 2, 5727 commutative: true, 5728 asm: x86.ATESTL, 5729 reg: regInfo{ 5730 inputs: []inputInfo{ 5731 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5732 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5733 }, 5734 }, 5735 }, 5736 { 5737 name: "TESTW", 5738 argLen: 2, 5739 commutative: true, 5740 asm: x86.ATESTW, 5741 reg: regInfo{ 5742 inputs: []inputInfo{ 5743 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5744 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5745 }, 5746 }, 5747 }, 5748 { 5749 name: "TESTB", 5750 argLen: 2, 5751 commutative: true, 5752 asm: x86.ATESTB, 5753 reg: regInfo{ 5754 inputs: []inputInfo{ 5755 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5756 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5757 }, 5758 }, 5759 }, 5760 { 5761 name: "TESTQconst", 5762 auxType: auxInt32, 5763 argLen: 1, 5764 asm: x86.ATESTQ, 5765 reg: regInfo{ 5766 inputs: []inputInfo{ 5767 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5768 }, 5769 }, 5770 }, 5771 { 5772 name: "TESTLconst", 5773 auxType: auxInt32, 5774 argLen: 1, 5775 asm: x86.ATESTL, 5776 reg: regInfo{ 5777 inputs: []inputInfo{ 5778 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5779 }, 5780 }, 5781 }, 5782 { 5783 name: "TESTWconst", 5784 auxType: auxInt16, 5785 argLen: 1, 5786 asm: x86.ATESTW, 5787 reg: regInfo{ 5788 inputs: []inputInfo{ 5789 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5790 }, 5791 }, 5792 }, 5793 { 5794 name: "TESTBconst", 5795 auxType: auxInt8, 5796 argLen: 1, 5797 asm: x86.ATESTB, 5798 reg: regInfo{ 5799 inputs: []inputInfo{ 5800 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5801 }, 5802 }, 5803 }, 5804 { 5805 name: "SHLQ", 5806 argLen: 2, 5807 resultInArg0: true, 5808 clobberFlags: true, 5809 asm: x86.ASHLQ, 5810 reg: regInfo{ 5811 inputs: []inputInfo{ 5812 {1, 2}, // CX 5813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5814 }, 5815 outputs: []outputInfo{ 5816 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5817 }, 5818 }, 5819 }, 5820 { 5821 name: "SHLL", 5822 argLen: 2, 5823 resultInArg0: true, 5824 clobberFlags: true, 5825 asm: x86.ASHLL, 5826 reg: regInfo{ 5827 inputs: []inputInfo{ 5828 {1, 2}, // CX 5829 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5830 }, 5831 outputs: []outputInfo{ 5832 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5833 }, 5834 }, 5835 }, 5836 { 5837 name: "SHLQconst", 5838 auxType: auxInt8, 5839 argLen: 1, 5840 resultInArg0: true, 5841 clobberFlags: true, 5842 asm: x86.ASHLQ, 5843 reg: regInfo{ 5844 inputs: []inputInfo{ 5845 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5846 }, 5847 outputs: []outputInfo{ 5848 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5849 }, 5850 }, 5851 }, 5852 { 5853 name: "SHLLconst", 5854 auxType: auxInt8, 5855 argLen: 1, 5856 resultInArg0: true, 5857 clobberFlags: true, 5858 asm: x86.ASHLL, 5859 reg: regInfo{ 5860 inputs: []inputInfo{ 5861 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5862 }, 5863 outputs: []outputInfo{ 5864 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5865 }, 5866 }, 5867 }, 5868 { 5869 name: "SHRQ", 5870 argLen: 2, 5871 resultInArg0: true, 5872 clobberFlags: true, 5873 asm: x86.ASHRQ, 5874 reg: regInfo{ 5875 inputs: []inputInfo{ 5876 {1, 2}, // CX 5877 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5878 }, 5879 outputs: []outputInfo{ 5880 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5881 }, 5882 }, 5883 }, 5884 { 5885 name: "SHRL", 5886 argLen: 2, 5887 resultInArg0: true, 5888 clobberFlags: true, 5889 asm: x86.ASHRL, 5890 reg: regInfo{ 5891 inputs: []inputInfo{ 5892 {1, 2}, // CX 5893 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5894 }, 5895 outputs: []outputInfo{ 5896 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5897 }, 5898 }, 5899 }, 5900 { 5901 name: "SHRW", 5902 argLen: 2, 5903 resultInArg0: true, 5904 clobberFlags: true, 5905 asm: x86.ASHRW, 5906 reg: regInfo{ 5907 inputs: []inputInfo{ 5908 {1, 2}, // CX 5909 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5910 }, 5911 outputs: []outputInfo{ 5912 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5913 }, 5914 }, 5915 }, 5916 { 5917 name: "SHRB", 5918 argLen: 2, 5919 resultInArg0: true, 5920 clobberFlags: true, 5921 asm: x86.ASHRB, 5922 reg: regInfo{ 5923 inputs: []inputInfo{ 5924 {1, 2}, // CX 5925 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5926 }, 5927 outputs: []outputInfo{ 5928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5929 }, 5930 }, 5931 }, 5932 { 5933 name: "SHRQconst", 5934 auxType: auxInt8, 5935 argLen: 1, 5936 resultInArg0: true, 5937 clobberFlags: true, 5938 asm: x86.ASHRQ, 5939 reg: regInfo{ 5940 inputs: []inputInfo{ 5941 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5942 }, 5943 outputs: []outputInfo{ 5944 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5945 }, 5946 }, 5947 }, 5948 { 5949 name: "SHRLconst", 5950 auxType: auxInt8, 5951 argLen: 1, 5952 resultInArg0: true, 5953 clobberFlags: true, 5954 asm: x86.ASHRL, 5955 reg: regInfo{ 5956 inputs: []inputInfo{ 5957 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5958 }, 5959 outputs: []outputInfo{ 5960 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5961 }, 5962 }, 5963 }, 5964 { 5965 name: "SHRWconst", 5966 auxType: auxInt8, 5967 argLen: 1, 5968 resultInArg0: true, 5969 clobberFlags: true, 5970 asm: x86.ASHRW, 5971 reg: regInfo{ 5972 inputs: []inputInfo{ 5973 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5974 }, 5975 outputs: []outputInfo{ 5976 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5977 }, 5978 }, 5979 }, 5980 { 5981 name: "SHRBconst", 5982 auxType: auxInt8, 5983 argLen: 1, 5984 resultInArg0: true, 5985 clobberFlags: true, 5986 asm: x86.ASHRB, 5987 reg: regInfo{ 5988 inputs: []inputInfo{ 5989 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5990 }, 5991 outputs: []outputInfo{ 5992 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5993 }, 5994 }, 5995 }, 5996 { 5997 name: "SARQ", 5998 argLen: 2, 5999 resultInArg0: true, 6000 clobberFlags: true, 6001 asm: x86.ASARQ, 6002 reg: regInfo{ 6003 inputs: []inputInfo{ 6004 {1, 2}, // CX 6005 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6006 }, 6007 outputs: []outputInfo{ 6008 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6009 }, 6010 }, 6011 }, 6012 { 6013 name: "SARL", 6014 argLen: 2, 6015 resultInArg0: true, 6016 clobberFlags: true, 6017 asm: x86.ASARL, 6018 reg: regInfo{ 6019 inputs: []inputInfo{ 6020 {1, 2}, // CX 6021 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6022 }, 6023 outputs: []outputInfo{ 6024 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6025 }, 6026 }, 6027 }, 6028 { 6029 name: "SARW", 6030 argLen: 2, 6031 resultInArg0: true, 6032 clobberFlags: true, 6033 asm: x86.ASARW, 6034 reg: regInfo{ 6035 inputs: []inputInfo{ 6036 {1, 2}, // CX 6037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6038 }, 6039 outputs: []outputInfo{ 6040 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6041 }, 6042 }, 6043 }, 6044 { 6045 name: "SARB", 6046 argLen: 2, 6047 resultInArg0: true, 6048 clobberFlags: true, 6049 asm: x86.ASARB, 6050 reg: regInfo{ 6051 inputs: []inputInfo{ 6052 {1, 2}, // CX 6053 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6054 }, 6055 outputs: []outputInfo{ 6056 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6057 }, 6058 }, 6059 }, 6060 { 6061 name: "SARQconst", 6062 auxType: auxInt8, 6063 argLen: 1, 6064 resultInArg0: true, 6065 clobberFlags: true, 6066 asm: x86.ASARQ, 6067 reg: regInfo{ 6068 inputs: []inputInfo{ 6069 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6070 }, 6071 outputs: []outputInfo{ 6072 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6073 }, 6074 }, 6075 }, 6076 { 6077 name: "SARLconst", 6078 auxType: auxInt8, 6079 argLen: 1, 6080 resultInArg0: true, 6081 clobberFlags: true, 6082 asm: x86.ASARL, 6083 reg: regInfo{ 6084 inputs: []inputInfo{ 6085 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6086 }, 6087 outputs: []outputInfo{ 6088 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6089 }, 6090 }, 6091 }, 6092 { 6093 name: "SARWconst", 6094 auxType: auxInt8, 6095 argLen: 1, 6096 resultInArg0: true, 6097 clobberFlags: true, 6098 asm: x86.ASARW, 6099 reg: regInfo{ 6100 inputs: []inputInfo{ 6101 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6102 }, 6103 outputs: []outputInfo{ 6104 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6105 }, 6106 }, 6107 }, 6108 { 6109 name: "SARBconst", 6110 auxType: auxInt8, 6111 argLen: 1, 6112 resultInArg0: true, 6113 clobberFlags: true, 6114 asm: x86.ASARB, 6115 reg: regInfo{ 6116 inputs: []inputInfo{ 6117 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6118 }, 6119 outputs: []outputInfo{ 6120 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6121 }, 6122 }, 6123 }, 6124 { 6125 name: "ROLQ", 6126 argLen: 2, 6127 resultInArg0: true, 6128 clobberFlags: true, 6129 asm: x86.AROLQ, 6130 reg: regInfo{ 6131 inputs: []inputInfo{ 6132 {1, 2}, // CX 6133 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6134 }, 6135 outputs: []outputInfo{ 6136 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6137 }, 6138 }, 6139 }, 6140 { 6141 name: "ROLL", 6142 argLen: 2, 6143 resultInArg0: true, 6144 clobberFlags: true, 6145 asm: x86.AROLL, 6146 reg: regInfo{ 6147 inputs: []inputInfo{ 6148 {1, 2}, // CX 6149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6150 }, 6151 outputs: []outputInfo{ 6152 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6153 }, 6154 }, 6155 }, 6156 { 6157 name: "ROLW", 6158 argLen: 2, 6159 resultInArg0: true, 6160 clobberFlags: true, 6161 asm: x86.AROLW, 6162 reg: regInfo{ 6163 inputs: []inputInfo{ 6164 {1, 2}, // CX 6165 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6166 }, 6167 outputs: []outputInfo{ 6168 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6169 }, 6170 }, 6171 }, 6172 { 6173 name: "ROLB", 6174 argLen: 2, 6175 resultInArg0: true, 6176 clobberFlags: true, 6177 asm: x86.AROLB, 6178 reg: regInfo{ 6179 inputs: []inputInfo{ 6180 {1, 2}, // CX 6181 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6182 }, 6183 outputs: []outputInfo{ 6184 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6185 }, 6186 }, 6187 }, 6188 { 6189 name: "RORQ", 6190 argLen: 2, 6191 resultInArg0: true, 6192 clobberFlags: true, 6193 asm: x86.ARORQ, 6194 reg: regInfo{ 6195 inputs: []inputInfo{ 6196 {1, 2}, // CX 6197 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6198 }, 6199 outputs: []outputInfo{ 6200 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6201 }, 6202 }, 6203 }, 6204 { 6205 name: "RORL", 6206 argLen: 2, 6207 resultInArg0: true, 6208 clobberFlags: true, 6209 asm: x86.ARORL, 6210 reg: regInfo{ 6211 inputs: []inputInfo{ 6212 {1, 2}, // CX 6213 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6214 }, 6215 outputs: []outputInfo{ 6216 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6217 }, 6218 }, 6219 }, 6220 { 6221 name: "RORW", 6222 argLen: 2, 6223 resultInArg0: true, 6224 clobberFlags: true, 6225 asm: x86.ARORW, 6226 reg: regInfo{ 6227 inputs: []inputInfo{ 6228 {1, 2}, // CX 6229 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6230 }, 6231 outputs: []outputInfo{ 6232 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6233 }, 6234 }, 6235 }, 6236 { 6237 name: "RORB", 6238 argLen: 2, 6239 resultInArg0: true, 6240 clobberFlags: true, 6241 asm: x86.ARORB, 6242 reg: regInfo{ 6243 inputs: []inputInfo{ 6244 {1, 2}, // CX 6245 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6246 }, 6247 outputs: []outputInfo{ 6248 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6249 }, 6250 }, 6251 }, 6252 { 6253 name: "ROLQconst", 6254 auxType: auxInt8, 6255 argLen: 1, 6256 resultInArg0: true, 6257 clobberFlags: true, 6258 asm: x86.AROLQ, 6259 reg: regInfo{ 6260 inputs: []inputInfo{ 6261 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6262 }, 6263 outputs: []outputInfo{ 6264 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6265 }, 6266 }, 6267 }, 6268 { 6269 name: "ROLLconst", 6270 auxType: auxInt8, 6271 argLen: 1, 6272 resultInArg0: true, 6273 clobberFlags: true, 6274 asm: x86.AROLL, 6275 reg: regInfo{ 6276 inputs: []inputInfo{ 6277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6278 }, 6279 outputs: []outputInfo{ 6280 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6281 }, 6282 }, 6283 }, 6284 { 6285 name: "ROLWconst", 6286 auxType: auxInt8, 6287 argLen: 1, 6288 resultInArg0: true, 6289 clobberFlags: true, 6290 asm: x86.AROLW, 6291 reg: regInfo{ 6292 inputs: []inputInfo{ 6293 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6294 }, 6295 outputs: []outputInfo{ 6296 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6297 }, 6298 }, 6299 }, 6300 { 6301 name: "ROLBconst", 6302 auxType: auxInt8, 6303 argLen: 1, 6304 resultInArg0: true, 6305 clobberFlags: true, 6306 asm: x86.AROLB, 6307 reg: regInfo{ 6308 inputs: []inputInfo{ 6309 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6310 }, 6311 outputs: []outputInfo{ 6312 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6313 }, 6314 }, 6315 }, 6316 { 6317 name: "ADDLmem", 6318 auxType: auxSymOff, 6319 argLen: 3, 6320 resultInArg0: true, 6321 clobberFlags: true, 6322 faultOnNilArg1: true, 6323 symEffect: SymRead, 6324 asm: x86.AADDL, 6325 reg: regInfo{ 6326 inputs: []inputInfo{ 6327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6328 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6329 }, 6330 outputs: []outputInfo{ 6331 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6332 }, 6333 }, 6334 }, 6335 { 6336 name: "ADDQmem", 6337 auxType: auxSymOff, 6338 argLen: 3, 6339 resultInArg0: true, 6340 clobberFlags: true, 6341 faultOnNilArg1: true, 6342 symEffect: SymRead, 6343 asm: x86.AADDQ, 6344 reg: regInfo{ 6345 inputs: []inputInfo{ 6346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6347 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6348 }, 6349 outputs: []outputInfo{ 6350 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6351 }, 6352 }, 6353 }, 6354 { 6355 name: "SUBQmem", 6356 auxType: auxSymOff, 6357 argLen: 3, 6358 resultInArg0: true, 6359 clobberFlags: true, 6360 faultOnNilArg1: true, 6361 symEffect: SymRead, 6362 asm: x86.ASUBQ, 6363 reg: regInfo{ 6364 inputs: []inputInfo{ 6365 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6366 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6367 }, 6368 outputs: []outputInfo{ 6369 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6370 }, 6371 }, 6372 }, 6373 { 6374 name: "SUBLmem", 6375 auxType: auxSymOff, 6376 argLen: 3, 6377 resultInArg0: true, 6378 clobberFlags: true, 6379 faultOnNilArg1: true, 6380 symEffect: SymRead, 6381 asm: x86.ASUBL, 6382 reg: regInfo{ 6383 inputs: []inputInfo{ 6384 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6385 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6386 }, 6387 outputs: []outputInfo{ 6388 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6389 }, 6390 }, 6391 }, 6392 { 6393 name: "ANDLmem", 6394 auxType: auxSymOff, 6395 argLen: 3, 6396 resultInArg0: true, 6397 clobberFlags: true, 6398 faultOnNilArg1: true, 6399 symEffect: SymRead, 6400 asm: x86.AANDL, 6401 reg: regInfo{ 6402 inputs: []inputInfo{ 6403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6404 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6405 }, 6406 outputs: []outputInfo{ 6407 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6408 }, 6409 }, 6410 }, 6411 { 6412 name: "ANDQmem", 6413 auxType: auxSymOff, 6414 argLen: 3, 6415 resultInArg0: true, 6416 clobberFlags: true, 6417 faultOnNilArg1: true, 6418 symEffect: SymRead, 6419 asm: x86.AANDQ, 6420 reg: regInfo{ 6421 inputs: []inputInfo{ 6422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6423 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6424 }, 6425 outputs: []outputInfo{ 6426 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6427 }, 6428 }, 6429 }, 6430 { 6431 name: "ORQmem", 6432 auxType: auxSymOff, 6433 argLen: 3, 6434 resultInArg0: true, 6435 clobberFlags: true, 6436 faultOnNilArg1: true, 6437 symEffect: SymRead, 6438 asm: x86.AORQ, 6439 reg: regInfo{ 6440 inputs: []inputInfo{ 6441 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6442 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6443 }, 6444 outputs: []outputInfo{ 6445 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6446 }, 6447 }, 6448 }, 6449 { 6450 name: "ORLmem", 6451 auxType: auxSymOff, 6452 argLen: 3, 6453 resultInArg0: true, 6454 clobberFlags: true, 6455 faultOnNilArg1: true, 6456 symEffect: SymRead, 6457 asm: x86.AORL, 6458 reg: regInfo{ 6459 inputs: []inputInfo{ 6460 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6461 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6462 }, 6463 outputs: []outputInfo{ 6464 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6465 }, 6466 }, 6467 }, 6468 { 6469 name: "XORQmem", 6470 auxType: auxSymOff, 6471 argLen: 3, 6472 resultInArg0: true, 6473 clobberFlags: true, 6474 faultOnNilArg1: true, 6475 symEffect: SymRead, 6476 asm: x86.AXORQ, 6477 reg: regInfo{ 6478 inputs: []inputInfo{ 6479 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6480 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6481 }, 6482 outputs: []outputInfo{ 6483 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6484 }, 6485 }, 6486 }, 6487 { 6488 name: "XORLmem", 6489 auxType: auxSymOff, 6490 argLen: 3, 6491 resultInArg0: true, 6492 clobberFlags: true, 6493 faultOnNilArg1: true, 6494 symEffect: SymRead, 6495 asm: x86.AXORL, 6496 reg: regInfo{ 6497 inputs: []inputInfo{ 6498 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6499 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6500 }, 6501 outputs: []outputInfo{ 6502 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6503 }, 6504 }, 6505 }, 6506 { 6507 name: "NEGQ", 6508 argLen: 1, 6509 resultInArg0: true, 6510 clobberFlags: true, 6511 asm: x86.ANEGQ, 6512 reg: regInfo{ 6513 inputs: []inputInfo{ 6514 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6515 }, 6516 outputs: []outputInfo{ 6517 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6518 }, 6519 }, 6520 }, 6521 { 6522 name: "NEGL", 6523 argLen: 1, 6524 resultInArg0: true, 6525 clobberFlags: true, 6526 asm: x86.ANEGL, 6527 reg: regInfo{ 6528 inputs: []inputInfo{ 6529 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6530 }, 6531 outputs: []outputInfo{ 6532 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6533 }, 6534 }, 6535 }, 6536 { 6537 name: "NOTQ", 6538 argLen: 1, 6539 resultInArg0: true, 6540 clobberFlags: true, 6541 asm: x86.ANOTQ, 6542 reg: regInfo{ 6543 inputs: []inputInfo{ 6544 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6545 }, 6546 outputs: []outputInfo{ 6547 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6548 }, 6549 }, 6550 }, 6551 { 6552 name: "NOTL", 6553 argLen: 1, 6554 resultInArg0: true, 6555 clobberFlags: true, 6556 asm: x86.ANOTL, 6557 reg: regInfo{ 6558 inputs: []inputInfo{ 6559 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6560 }, 6561 outputs: []outputInfo{ 6562 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6563 }, 6564 }, 6565 }, 6566 { 6567 name: "BSFQ", 6568 argLen: 1, 6569 asm: x86.ABSFQ, 6570 reg: regInfo{ 6571 inputs: []inputInfo{ 6572 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6573 }, 6574 outputs: []outputInfo{ 6575 {1, 0}, 6576 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6577 }, 6578 }, 6579 }, 6580 { 6581 name: "BSFL", 6582 argLen: 1, 6583 asm: x86.ABSFL, 6584 reg: regInfo{ 6585 inputs: []inputInfo{ 6586 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6587 }, 6588 outputs: []outputInfo{ 6589 {1, 0}, 6590 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6591 }, 6592 }, 6593 }, 6594 { 6595 name: "BSRQ", 6596 argLen: 1, 6597 asm: x86.ABSRQ, 6598 reg: regInfo{ 6599 inputs: []inputInfo{ 6600 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6601 }, 6602 outputs: []outputInfo{ 6603 {1, 0}, 6604 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6605 }, 6606 }, 6607 }, 6608 { 6609 name: "BSRL", 6610 argLen: 1, 6611 asm: x86.ABSRL, 6612 reg: regInfo{ 6613 inputs: []inputInfo{ 6614 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6615 }, 6616 outputs: []outputInfo{ 6617 {1, 0}, 6618 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6619 }, 6620 }, 6621 }, 6622 { 6623 name: "CMOVQEQ", 6624 argLen: 3, 6625 resultInArg0: true, 6626 asm: x86.ACMOVQEQ, 6627 reg: regInfo{ 6628 inputs: []inputInfo{ 6629 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6630 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6631 }, 6632 outputs: []outputInfo{ 6633 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6634 }, 6635 }, 6636 }, 6637 { 6638 name: "CMOVLEQ", 6639 argLen: 3, 6640 resultInArg0: true, 6641 asm: x86.ACMOVLEQ, 6642 reg: regInfo{ 6643 inputs: []inputInfo{ 6644 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6645 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6646 }, 6647 outputs: []outputInfo{ 6648 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6649 }, 6650 }, 6651 }, 6652 { 6653 name: "BSWAPQ", 6654 argLen: 1, 6655 resultInArg0: true, 6656 clobberFlags: true, 6657 asm: x86.ABSWAPQ, 6658 reg: regInfo{ 6659 inputs: []inputInfo{ 6660 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6661 }, 6662 outputs: []outputInfo{ 6663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6664 }, 6665 }, 6666 }, 6667 { 6668 name: "BSWAPL", 6669 argLen: 1, 6670 resultInArg0: true, 6671 clobberFlags: true, 6672 asm: x86.ABSWAPL, 6673 reg: regInfo{ 6674 inputs: []inputInfo{ 6675 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6676 }, 6677 outputs: []outputInfo{ 6678 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6679 }, 6680 }, 6681 }, 6682 { 6683 name: "POPCNTQ", 6684 argLen: 1, 6685 clobberFlags: true, 6686 asm: x86.APOPCNTQ, 6687 reg: regInfo{ 6688 inputs: []inputInfo{ 6689 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6690 }, 6691 outputs: []outputInfo{ 6692 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6693 }, 6694 }, 6695 }, 6696 { 6697 name: "POPCNTL", 6698 argLen: 1, 6699 clobberFlags: true, 6700 asm: x86.APOPCNTL, 6701 reg: regInfo{ 6702 inputs: []inputInfo{ 6703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6704 }, 6705 outputs: []outputInfo{ 6706 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6707 }, 6708 }, 6709 }, 6710 { 6711 name: "SQRTSD", 6712 argLen: 1, 6713 asm: x86.ASQRTSD, 6714 reg: regInfo{ 6715 inputs: []inputInfo{ 6716 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6717 }, 6718 outputs: []outputInfo{ 6719 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6720 }, 6721 }, 6722 }, 6723 { 6724 name: "ROUNDSD", 6725 auxType: auxInt8, 6726 argLen: 1, 6727 asm: x86.AROUNDSD, 6728 reg: regInfo{ 6729 inputs: []inputInfo{ 6730 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6731 }, 6732 outputs: []outputInfo{ 6733 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6734 }, 6735 }, 6736 }, 6737 { 6738 name: "SBBQcarrymask", 6739 argLen: 1, 6740 asm: x86.ASBBQ, 6741 reg: regInfo{ 6742 outputs: []outputInfo{ 6743 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6744 }, 6745 }, 6746 }, 6747 { 6748 name: "SBBLcarrymask", 6749 argLen: 1, 6750 asm: x86.ASBBL, 6751 reg: regInfo{ 6752 outputs: []outputInfo{ 6753 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6754 }, 6755 }, 6756 }, 6757 { 6758 name: "SETEQ", 6759 argLen: 1, 6760 asm: x86.ASETEQ, 6761 reg: regInfo{ 6762 outputs: []outputInfo{ 6763 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 }, 6765 }, 6766 }, 6767 { 6768 name: "SETNE", 6769 argLen: 1, 6770 asm: x86.ASETNE, 6771 reg: regInfo{ 6772 outputs: []outputInfo{ 6773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6774 }, 6775 }, 6776 }, 6777 { 6778 name: "SETL", 6779 argLen: 1, 6780 asm: x86.ASETLT, 6781 reg: regInfo{ 6782 outputs: []outputInfo{ 6783 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6784 }, 6785 }, 6786 }, 6787 { 6788 name: "SETLE", 6789 argLen: 1, 6790 asm: x86.ASETLE, 6791 reg: regInfo{ 6792 outputs: []outputInfo{ 6793 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6794 }, 6795 }, 6796 }, 6797 { 6798 name: "SETG", 6799 argLen: 1, 6800 asm: x86.ASETGT, 6801 reg: regInfo{ 6802 outputs: []outputInfo{ 6803 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6804 }, 6805 }, 6806 }, 6807 { 6808 name: "SETGE", 6809 argLen: 1, 6810 asm: x86.ASETGE, 6811 reg: regInfo{ 6812 outputs: []outputInfo{ 6813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6814 }, 6815 }, 6816 }, 6817 { 6818 name: "SETB", 6819 argLen: 1, 6820 asm: x86.ASETCS, 6821 reg: regInfo{ 6822 outputs: []outputInfo{ 6823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6824 }, 6825 }, 6826 }, 6827 { 6828 name: "SETBE", 6829 argLen: 1, 6830 asm: x86.ASETLS, 6831 reg: regInfo{ 6832 outputs: []outputInfo{ 6833 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6834 }, 6835 }, 6836 }, 6837 { 6838 name: "SETA", 6839 argLen: 1, 6840 asm: x86.ASETHI, 6841 reg: regInfo{ 6842 outputs: []outputInfo{ 6843 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6844 }, 6845 }, 6846 }, 6847 { 6848 name: "SETAE", 6849 argLen: 1, 6850 asm: x86.ASETCC, 6851 reg: regInfo{ 6852 outputs: []outputInfo{ 6853 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6854 }, 6855 }, 6856 }, 6857 { 6858 name: "SETEQmem", 6859 auxType: auxSymOff, 6860 argLen: 3, 6861 faultOnNilArg0: true, 6862 symEffect: SymWrite, 6863 asm: x86.ASETEQ, 6864 reg: regInfo{ 6865 inputs: []inputInfo{ 6866 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6867 }, 6868 }, 6869 }, 6870 { 6871 name: "SETNEmem", 6872 auxType: auxSymOff, 6873 argLen: 3, 6874 faultOnNilArg0: true, 6875 symEffect: SymWrite, 6876 asm: x86.ASETNE, 6877 reg: regInfo{ 6878 inputs: []inputInfo{ 6879 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6880 }, 6881 }, 6882 }, 6883 { 6884 name: "SETLmem", 6885 auxType: auxSymOff, 6886 argLen: 3, 6887 faultOnNilArg0: true, 6888 symEffect: SymWrite, 6889 asm: x86.ASETLT, 6890 reg: regInfo{ 6891 inputs: []inputInfo{ 6892 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6893 }, 6894 }, 6895 }, 6896 { 6897 name: "SETLEmem", 6898 auxType: auxSymOff, 6899 argLen: 3, 6900 faultOnNilArg0: true, 6901 symEffect: SymWrite, 6902 asm: x86.ASETLE, 6903 reg: regInfo{ 6904 inputs: []inputInfo{ 6905 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6906 }, 6907 }, 6908 }, 6909 { 6910 name: "SETGmem", 6911 auxType: auxSymOff, 6912 argLen: 3, 6913 faultOnNilArg0: true, 6914 symEffect: SymWrite, 6915 asm: x86.ASETGT, 6916 reg: regInfo{ 6917 inputs: []inputInfo{ 6918 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6919 }, 6920 }, 6921 }, 6922 { 6923 name: "SETGEmem", 6924 auxType: auxSymOff, 6925 argLen: 3, 6926 faultOnNilArg0: true, 6927 symEffect: SymWrite, 6928 asm: x86.ASETGE, 6929 reg: regInfo{ 6930 inputs: []inputInfo{ 6931 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6932 }, 6933 }, 6934 }, 6935 { 6936 name: "SETBmem", 6937 auxType: auxSymOff, 6938 argLen: 3, 6939 faultOnNilArg0: true, 6940 symEffect: SymWrite, 6941 asm: x86.ASETCS, 6942 reg: regInfo{ 6943 inputs: []inputInfo{ 6944 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6945 }, 6946 }, 6947 }, 6948 { 6949 name: "SETBEmem", 6950 auxType: auxSymOff, 6951 argLen: 3, 6952 faultOnNilArg0: true, 6953 symEffect: SymWrite, 6954 asm: x86.ASETLS, 6955 reg: regInfo{ 6956 inputs: []inputInfo{ 6957 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6958 }, 6959 }, 6960 }, 6961 { 6962 name: "SETAmem", 6963 auxType: auxSymOff, 6964 argLen: 3, 6965 faultOnNilArg0: true, 6966 symEffect: SymWrite, 6967 asm: x86.ASETHI, 6968 reg: regInfo{ 6969 inputs: []inputInfo{ 6970 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6971 }, 6972 }, 6973 }, 6974 { 6975 name: "SETAEmem", 6976 auxType: auxSymOff, 6977 argLen: 3, 6978 faultOnNilArg0: true, 6979 symEffect: SymWrite, 6980 asm: x86.ASETCC, 6981 reg: regInfo{ 6982 inputs: []inputInfo{ 6983 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6984 }, 6985 }, 6986 }, 6987 { 6988 name: "SETEQF", 6989 argLen: 1, 6990 clobberFlags: true, 6991 asm: x86.ASETEQ, 6992 reg: regInfo{ 6993 clobbers: 1, // AX 6994 outputs: []outputInfo{ 6995 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6996 }, 6997 }, 6998 }, 6999 { 7000 name: "SETNEF", 7001 argLen: 1, 7002 clobberFlags: true, 7003 asm: x86.ASETNE, 7004 reg: regInfo{ 7005 clobbers: 1, // AX 7006 outputs: []outputInfo{ 7007 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7008 }, 7009 }, 7010 }, 7011 { 7012 name: "SETORD", 7013 argLen: 1, 7014 asm: x86.ASETPC, 7015 reg: regInfo{ 7016 outputs: []outputInfo{ 7017 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7018 }, 7019 }, 7020 }, 7021 { 7022 name: "SETNAN", 7023 argLen: 1, 7024 asm: x86.ASETPS, 7025 reg: regInfo{ 7026 outputs: []outputInfo{ 7027 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7028 }, 7029 }, 7030 }, 7031 { 7032 name: "SETGF", 7033 argLen: 1, 7034 asm: x86.ASETHI, 7035 reg: regInfo{ 7036 outputs: []outputInfo{ 7037 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7038 }, 7039 }, 7040 }, 7041 { 7042 name: "SETGEF", 7043 argLen: 1, 7044 asm: x86.ASETCC, 7045 reg: regInfo{ 7046 outputs: []outputInfo{ 7047 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7048 }, 7049 }, 7050 }, 7051 { 7052 name: "MOVBQSX", 7053 argLen: 1, 7054 asm: x86.AMOVBQSX, 7055 reg: regInfo{ 7056 inputs: []inputInfo{ 7057 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7058 }, 7059 outputs: []outputInfo{ 7060 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7061 }, 7062 }, 7063 }, 7064 { 7065 name: "MOVBQZX", 7066 argLen: 1, 7067 asm: x86.AMOVBLZX, 7068 reg: regInfo{ 7069 inputs: []inputInfo{ 7070 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7071 }, 7072 outputs: []outputInfo{ 7073 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7074 }, 7075 }, 7076 }, 7077 { 7078 name: "MOVWQSX", 7079 argLen: 1, 7080 asm: x86.AMOVWQSX, 7081 reg: regInfo{ 7082 inputs: []inputInfo{ 7083 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7084 }, 7085 outputs: []outputInfo{ 7086 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7087 }, 7088 }, 7089 }, 7090 { 7091 name: "MOVWQZX", 7092 argLen: 1, 7093 asm: x86.AMOVWLZX, 7094 reg: regInfo{ 7095 inputs: []inputInfo{ 7096 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7097 }, 7098 outputs: []outputInfo{ 7099 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7100 }, 7101 }, 7102 }, 7103 { 7104 name: "MOVLQSX", 7105 argLen: 1, 7106 asm: x86.AMOVLQSX, 7107 reg: regInfo{ 7108 inputs: []inputInfo{ 7109 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7110 }, 7111 outputs: []outputInfo{ 7112 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7113 }, 7114 }, 7115 }, 7116 { 7117 name: "MOVLQZX", 7118 argLen: 1, 7119 asm: x86.AMOVL, 7120 reg: regInfo{ 7121 inputs: []inputInfo{ 7122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7123 }, 7124 outputs: []outputInfo{ 7125 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7126 }, 7127 }, 7128 }, 7129 { 7130 name: "MOVLconst", 7131 auxType: auxInt32, 7132 argLen: 0, 7133 rematerializeable: true, 7134 asm: x86.AMOVL, 7135 reg: regInfo{ 7136 outputs: []outputInfo{ 7137 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7138 }, 7139 }, 7140 }, 7141 { 7142 name: "MOVQconst", 7143 auxType: auxInt64, 7144 argLen: 0, 7145 rematerializeable: true, 7146 asm: x86.AMOVQ, 7147 reg: regInfo{ 7148 outputs: []outputInfo{ 7149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7150 }, 7151 }, 7152 }, 7153 { 7154 name: "CVTTSD2SL", 7155 argLen: 1, 7156 asm: x86.ACVTTSD2SL, 7157 reg: regInfo{ 7158 inputs: []inputInfo{ 7159 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7160 }, 7161 outputs: []outputInfo{ 7162 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7163 }, 7164 }, 7165 }, 7166 { 7167 name: "CVTTSD2SQ", 7168 argLen: 1, 7169 asm: x86.ACVTTSD2SQ, 7170 reg: regInfo{ 7171 inputs: []inputInfo{ 7172 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7173 }, 7174 outputs: []outputInfo{ 7175 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7176 }, 7177 }, 7178 }, 7179 { 7180 name: "CVTTSS2SL", 7181 argLen: 1, 7182 asm: x86.ACVTTSS2SL, 7183 reg: regInfo{ 7184 inputs: []inputInfo{ 7185 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7186 }, 7187 outputs: []outputInfo{ 7188 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7189 }, 7190 }, 7191 }, 7192 { 7193 name: "CVTTSS2SQ", 7194 argLen: 1, 7195 asm: x86.ACVTTSS2SQ, 7196 reg: regInfo{ 7197 inputs: []inputInfo{ 7198 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7199 }, 7200 outputs: []outputInfo{ 7201 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7202 }, 7203 }, 7204 }, 7205 { 7206 name: "CVTSL2SS", 7207 argLen: 1, 7208 asm: x86.ACVTSL2SS, 7209 reg: regInfo{ 7210 inputs: []inputInfo{ 7211 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7212 }, 7213 outputs: []outputInfo{ 7214 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7215 }, 7216 }, 7217 }, 7218 { 7219 name: "CVTSL2SD", 7220 argLen: 1, 7221 asm: x86.ACVTSL2SD, 7222 reg: regInfo{ 7223 inputs: []inputInfo{ 7224 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7225 }, 7226 outputs: []outputInfo{ 7227 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7228 }, 7229 }, 7230 }, 7231 { 7232 name: "CVTSQ2SS", 7233 argLen: 1, 7234 asm: x86.ACVTSQ2SS, 7235 reg: regInfo{ 7236 inputs: []inputInfo{ 7237 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7238 }, 7239 outputs: []outputInfo{ 7240 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7241 }, 7242 }, 7243 }, 7244 { 7245 name: "CVTSQ2SD", 7246 argLen: 1, 7247 asm: x86.ACVTSQ2SD, 7248 reg: regInfo{ 7249 inputs: []inputInfo{ 7250 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7251 }, 7252 outputs: []outputInfo{ 7253 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7254 }, 7255 }, 7256 }, 7257 { 7258 name: "CVTSD2SS", 7259 argLen: 1, 7260 asm: x86.ACVTSD2SS, 7261 reg: regInfo{ 7262 inputs: []inputInfo{ 7263 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7264 }, 7265 outputs: []outputInfo{ 7266 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7267 }, 7268 }, 7269 }, 7270 { 7271 name: "CVTSS2SD", 7272 argLen: 1, 7273 asm: x86.ACVTSS2SD, 7274 reg: regInfo{ 7275 inputs: []inputInfo{ 7276 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7277 }, 7278 outputs: []outputInfo{ 7279 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7280 }, 7281 }, 7282 }, 7283 { 7284 name: "MOVQi2f", 7285 argLen: 1, 7286 reg: regInfo{ 7287 inputs: []inputInfo{ 7288 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7289 }, 7290 outputs: []outputInfo{ 7291 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7292 }, 7293 }, 7294 }, 7295 { 7296 name: "MOVQf2i", 7297 argLen: 1, 7298 reg: regInfo{ 7299 inputs: []inputInfo{ 7300 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7301 }, 7302 outputs: []outputInfo{ 7303 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7304 }, 7305 }, 7306 }, 7307 { 7308 name: "MOVLi2f", 7309 argLen: 1, 7310 reg: regInfo{ 7311 inputs: []inputInfo{ 7312 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7313 }, 7314 outputs: []outputInfo{ 7315 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7316 }, 7317 }, 7318 }, 7319 { 7320 name: "MOVLf2i", 7321 argLen: 1, 7322 reg: regInfo{ 7323 inputs: []inputInfo{ 7324 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7325 }, 7326 outputs: []outputInfo{ 7327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7328 }, 7329 }, 7330 }, 7331 { 7332 name: "PXOR", 7333 argLen: 2, 7334 commutative: true, 7335 resultInArg0: true, 7336 asm: x86.APXOR, 7337 reg: regInfo{ 7338 inputs: []inputInfo{ 7339 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7340 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7341 }, 7342 outputs: []outputInfo{ 7343 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7344 }, 7345 }, 7346 }, 7347 { 7348 name: "LEAQ", 7349 auxType: auxSymOff, 7350 argLen: 1, 7351 rematerializeable: true, 7352 symEffect: SymAddr, 7353 asm: x86.ALEAQ, 7354 reg: regInfo{ 7355 inputs: []inputInfo{ 7356 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7357 }, 7358 outputs: []outputInfo{ 7359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7360 }, 7361 }, 7362 }, 7363 { 7364 name: "LEAQ1", 7365 auxType: auxSymOff, 7366 argLen: 2, 7367 commutative: true, 7368 symEffect: SymAddr, 7369 reg: regInfo{ 7370 inputs: []inputInfo{ 7371 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7372 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7373 }, 7374 outputs: []outputInfo{ 7375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7376 }, 7377 }, 7378 }, 7379 { 7380 name: "LEAQ2", 7381 auxType: auxSymOff, 7382 argLen: 2, 7383 symEffect: SymAddr, 7384 reg: regInfo{ 7385 inputs: []inputInfo{ 7386 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7387 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7388 }, 7389 outputs: []outputInfo{ 7390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7391 }, 7392 }, 7393 }, 7394 { 7395 name: "LEAQ4", 7396 auxType: auxSymOff, 7397 argLen: 2, 7398 symEffect: SymAddr, 7399 reg: regInfo{ 7400 inputs: []inputInfo{ 7401 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7402 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7403 }, 7404 outputs: []outputInfo{ 7405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7406 }, 7407 }, 7408 }, 7409 { 7410 name: "LEAQ8", 7411 auxType: auxSymOff, 7412 argLen: 2, 7413 symEffect: SymAddr, 7414 reg: regInfo{ 7415 inputs: []inputInfo{ 7416 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7417 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7418 }, 7419 outputs: []outputInfo{ 7420 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7421 }, 7422 }, 7423 }, 7424 { 7425 name: "LEAL", 7426 auxType: auxSymOff, 7427 argLen: 1, 7428 rematerializeable: true, 7429 symEffect: SymAddr, 7430 asm: x86.ALEAL, 7431 reg: regInfo{ 7432 inputs: []inputInfo{ 7433 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7434 }, 7435 outputs: []outputInfo{ 7436 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7437 }, 7438 }, 7439 }, 7440 { 7441 name: "MOVBload", 7442 auxType: auxSymOff, 7443 argLen: 2, 7444 faultOnNilArg0: true, 7445 symEffect: SymRead, 7446 asm: x86.AMOVBLZX, 7447 reg: regInfo{ 7448 inputs: []inputInfo{ 7449 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7450 }, 7451 outputs: []outputInfo{ 7452 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7453 }, 7454 }, 7455 }, 7456 { 7457 name: "MOVBQSXload", 7458 auxType: auxSymOff, 7459 argLen: 2, 7460 faultOnNilArg0: true, 7461 symEffect: SymRead, 7462 asm: x86.AMOVBQSX, 7463 reg: regInfo{ 7464 inputs: []inputInfo{ 7465 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7466 }, 7467 outputs: []outputInfo{ 7468 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7469 }, 7470 }, 7471 }, 7472 { 7473 name: "MOVWload", 7474 auxType: auxSymOff, 7475 argLen: 2, 7476 faultOnNilArg0: true, 7477 symEffect: SymRead, 7478 asm: x86.AMOVWLZX, 7479 reg: regInfo{ 7480 inputs: []inputInfo{ 7481 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7482 }, 7483 outputs: []outputInfo{ 7484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7485 }, 7486 }, 7487 }, 7488 { 7489 name: "MOVWQSXload", 7490 auxType: auxSymOff, 7491 argLen: 2, 7492 faultOnNilArg0: true, 7493 symEffect: SymRead, 7494 asm: x86.AMOVWQSX, 7495 reg: regInfo{ 7496 inputs: []inputInfo{ 7497 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7498 }, 7499 outputs: []outputInfo{ 7500 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7501 }, 7502 }, 7503 }, 7504 { 7505 name: "MOVLload", 7506 auxType: auxSymOff, 7507 argLen: 2, 7508 faultOnNilArg0: true, 7509 symEffect: SymRead, 7510 asm: x86.AMOVL, 7511 reg: regInfo{ 7512 inputs: []inputInfo{ 7513 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7514 }, 7515 outputs: []outputInfo{ 7516 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7517 }, 7518 }, 7519 }, 7520 { 7521 name: "MOVLQSXload", 7522 auxType: auxSymOff, 7523 argLen: 2, 7524 faultOnNilArg0: true, 7525 symEffect: SymRead, 7526 asm: x86.AMOVLQSX, 7527 reg: regInfo{ 7528 inputs: []inputInfo{ 7529 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7530 }, 7531 outputs: []outputInfo{ 7532 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7533 }, 7534 }, 7535 }, 7536 { 7537 name: "MOVQload", 7538 auxType: auxSymOff, 7539 argLen: 2, 7540 faultOnNilArg0: true, 7541 symEffect: SymRead, 7542 asm: x86.AMOVQ, 7543 reg: regInfo{ 7544 inputs: []inputInfo{ 7545 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7546 }, 7547 outputs: []outputInfo{ 7548 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7549 }, 7550 }, 7551 }, 7552 { 7553 name: "MOVBstore", 7554 auxType: auxSymOff, 7555 argLen: 3, 7556 faultOnNilArg0: true, 7557 symEffect: SymWrite, 7558 asm: x86.AMOVB, 7559 reg: regInfo{ 7560 inputs: []inputInfo{ 7561 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7562 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7563 }, 7564 }, 7565 }, 7566 { 7567 name: "MOVWstore", 7568 auxType: auxSymOff, 7569 argLen: 3, 7570 faultOnNilArg0: true, 7571 symEffect: SymWrite, 7572 asm: x86.AMOVW, 7573 reg: regInfo{ 7574 inputs: []inputInfo{ 7575 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7576 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7577 }, 7578 }, 7579 }, 7580 { 7581 name: "MOVLstore", 7582 auxType: auxSymOff, 7583 argLen: 3, 7584 faultOnNilArg0: true, 7585 symEffect: SymWrite, 7586 asm: x86.AMOVL, 7587 reg: regInfo{ 7588 inputs: []inputInfo{ 7589 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7590 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7591 }, 7592 }, 7593 }, 7594 { 7595 name: "MOVQstore", 7596 auxType: auxSymOff, 7597 argLen: 3, 7598 faultOnNilArg0: true, 7599 symEffect: SymWrite, 7600 asm: x86.AMOVQ, 7601 reg: regInfo{ 7602 inputs: []inputInfo{ 7603 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7604 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7605 }, 7606 }, 7607 }, 7608 { 7609 name: "MOVOload", 7610 auxType: auxSymOff, 7611 argLen: 2, 7612 faultOnNilArg0: true, 7613 symEffect: SymRead, 7614 asm: x86.AMOVUPS, 7615 reg: regInfo{ 7616 inputs: []inputInfo{ 7617 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7618 }, 7619 outputs: []outputInfo{ 7620 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7621 }, 7622 }, 7623 }, 7624 { 7625 name: "MOVOstore", 7626 auxType: auxSymOff, 7627 argLen: 3, 7628 faultOnNilArg0: true, 7629 symEffect: SymWrite, 7630 asm: x86.AMOVUPS, 7631 reg: regInfo{ 7632 inputs: []inputInfo{ 7633 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 7634 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7635 }, 7636 }, 7637 }, 7638 { 7639 name: "MOVBloadidx1", 7640 auxType: auxSymOff, 7641 argLen: 3, 7642 commutative: true, 7643 symEffect: SymRead, 7644 asm: x86.AMOVBLZX, 7645 reg: regInfo{ 7646 inputs: []inputInfo{ 7647 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7648 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7649 }, 7650 outputs: []outputInfo{ 7651 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7652 }, 7653 }, 7654 }, 7655 { 7656 name: "MOVWloadidx1", 7657 auxType: auxSymOff, 7658 argLen: 3, 7659 commutative: true, 7660 symEffect: SymRead, 7661 asm: x86.AMOVWLZX, 7662 reg: regInfo{ 7663 inputs: []inputInfo{ 7664 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7665 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7666 }, 7667 outputs: []outputInfo{ 7668 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7669 }, 7670 }, 7671 }, 7672 { 7673 name: "MOVWloadidx2", 7674 auxType: auxSymOff, 7675 argLen: 3, 7676 symEffect: SymRead, 7677 asm: x86.AMOVWLZX, 7678 reg: regInfo{ 7679 inputs: []inputInfo{ 7680 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7681 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7682 }, 7683 outputs: []outputInfo{ 7684 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7685 }, 7686 }, 7687 }, 7688 { 7689 name: "MOVLloadidx1", 7690 auxType: auxSymOff, 7691 argLen: 3, 7692 commutative: true, 7693 symEffect: SymRead, 7694 asm: x86.AMOVL, 7695 reg: regInfo{ 7696 inputs: []inputInfo{ 7697 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7698 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7699 }, 7700 outputs: []outputInfo{ 7701 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7702 }, 7703 }, 7704 }, 7705 { 7706 name: "MOVLloadidx4", 7707 auxType: auxSymOff, 7708 argLen: 3, 7709 symEffect: SymRead, 7710 asm: x86.AMOVL, 7711 reg: regInfo{ 7712 inputs: []inputInfo{ 7713 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7714 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7715 }, 7716 outputs: []outputInfo{ 7717 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7718 }, 7719 }, 7720 }, 7721 { 7722 name: "MOVLloadidx8", 7723 auxType: auxSymOff, 7724 argLen: 3, 7725 symEffect: SymRead, 7726 asm: x86.AMOVL, 7727 reg: regInfo{ 7728 inputs: []inputInfo{ 7729 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7730 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7731 }, 7732 outputs: []outputInfo{ 7733 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7734 }, 7735 }, 7736 }, 7737 { 7738 name: "MOVQloadidx1", 7739 auxType: auxSymOff, 7740 argLen: 3, 7741 commutative: true, 7742 symEffect: SymRead, 7743 asm: x86.AMOVQ, 7744 reg: regInfo{ 7745 inputs: []inputInfo{ 7746 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7747 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7748 }, 7749 outputs: []outputInfo{ 7750 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7751 }, 7752 }, 7753 }, 7754 { 7755 name: "MOVQloadidx8", 7756 auxType: auxSymOff, 7757 argLen: 3, 7758 symEffect: SymRead, 7759 asm: x86.AMOVQ, 7760 reg: regInfo{ 7761 inputs: []inputInfo{ 7762 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7763 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7764 }, 7765 outputs: []outputInfo{ 7766 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7767 }, 7768 }, 7769 }, 7770 { 7771 name: "MOVBstoreidx1", 7772 auxType: auxSymOff, 7773 argLen: 4, 7774 symEffect: SymWrite, 7775 asm: x86.AMOVB, 7776 reg: regInfo{ 7777 inputs: []inputInfo{ 7778 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7779 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7780 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7781 }, 7782 }, 7783 }, 7784 { 7785 name: "MOVWstoreidx1", 7786 auxType: auxSymOff, 7787 argLen: 4, 7788 symEffect: SymWrite, 7789 asm: x86.AMOVW, 7790 reg: regInfo{ 7791 inputs: []inputInfo{ 7792 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7793 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7794 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7795 }, 7796 }, 7797 }, 7798 { 7799 name: "MOVWstoreidx2", 7800 auxType: auxSymOff, 7801 argLen: 4, 7802 symEffect: SymWrite, 7803 asm: x86.AMOVW, 7804 reg: regInfo{ 7805 inputs: []inputInfo{ 7806 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7807 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7808 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7809 }, 7810 }, 7811 }, 7812 { 7813 name: "MOVLstoreidx1", 7814 auxType: auxSymOff, 7815 argLen: 4, 7816 symEffect: SymWrite, 7817 asm: x86.AMOVL, 7818 reg: regInfo{ 7819 inputs: []inputInfo{ 7820 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7821 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7822 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7823 }, 7824 }, 7825 }, 7826 { 7827 name: "MOVLstoreidx4", 7828 auxType: auxSymOff, 7829 argLen: 4, 7830 symEffect: SymWrite, 7831 asm: x86.AMOVL, 7832 reg: regInfo{ 7833 inputs: []inputInfo{ 7834 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7835 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7836 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7837 }, 7838 }, 7839 }, 7840 { 7841 name: "MOVLstoreidx8", 7842 auxType: auxSymOff, 7843 argLen: 4, 7844 symEffect: SymWrite, 7845 asm: x86.AMOVL, 7846 reg: regInfo{ 7847 inputs: []inputInfo{ 7848 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7849 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7850 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7851 }, 7852 }, 7853 }, 7854 { 7855 name: "MOVQstoreidx1", 7856 auxType: auxSymOff, 7857 argLen: 4, 7858 symEffect: SymWrite, 7859 asm: x86.AMOVQ, 7860 reg: regInfo{ 7861 inputs: []inputInfo{ 7862 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7863 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7864 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7865 }, 7866 }, 7867 }, 7868 { 7869 name: "MOVQstoreidx8", 7870 auxType: auxSymOff, 7871 argLen: 4, 7872 symEffect: SymWrite, 7873 asm: x86.AMOVQ, 7874 reg: regInfo{ 7875 inputs: []inputInfo{ 7876 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7877 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7878 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7879 }, 7880 }, 7881 }, 7882 { 7883 name: "MOVBstoreconst", 7884 auxType: auxSymValAndOff, 7885 argLen: 2, 7886 faultOnNilArg0: true, 7887 symEffect: SymWrite, 7888 asm: x86.AMOVB, 7889 reg: regInfo{ 7890 inputs: []inputInfo{ 7891 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7892 }, 7893 }, 7894 }, 7895 { 7896 name: "MOVWstoreconst", 7897 auxType: auxSymValAndOff, 7898 argLen: 2, 7899 faultOnNilArg0: true, 7900 symEffect: SymWrite, 7901 asm: x86.AMOVW, 7902 reg: regInfo{ 7903 inputs: []inputInfo{ 7904 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7905 }, 7906 }, 7907 }, 7908 { 7909 name: "MOVLstoreconst", 7910 auxType: auxSymValAndOff, 7911 argLen: 2, 7912 faultOnNilArg0: true, 7913 symEffect: SymWrite, 7914 asm: x86.AMOVL, 7915 reg: regInfo{ 7916 inputs: []inputInfo{ 7917 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7918 }, 7919 }, 7920 }, 7921 { 7922 name: "MOVQstoreconst", 7923 auxType: auxSymValAndOff, 7924 argLen: 2, 7925 faultOnNilArg0: true, 7926 symEffect: SymWrite, 7927 asm: x86.AMOVQ, 7928 reg: regInfo{ 7929 inputs: []inputInfo{ 7930 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7931 }, 7932 }, 7933 }, 7934 { 7935 name: "MOVBstoreconstidx1", 7936 auxType: auxSymValAndOff, 7937 argLen: 3, 7938 symEffect: SymWrite, 7939 asm: x86.AMOVB, 7940 reg: regInfo{ 7941 inputs: []inputInfo{ 7942 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7943 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7944 }, 7945 }, 7946 }, 7947 { 7948 name: "MOVWstoreconstidx1", 7949 auxType: auxSymValAndOff, 7950 argLen: 3, 7951 symEffect: SymWrite, 7952 asm: x86.AMOVW, 7953 reg: regInfo{ 7954 inputs: []inputInfo{ 7955 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7956 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7957 }, 7958 }, 7959 }, 7960 { 7961 name: "MOVWstoreconstidx2", 7962 auxType: auxSymValAndOff, 7963 argLen: 3, 7964 symEffect: SymWrite, 7965 asm: x86.AMOVW, 7966 reg: regInfo{ 7967 inputs: []inputInfo{ 7968 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7969 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7970 }, 7971 }, 7972 }, 7973 { 7974 name: "MOVLstoreconstidx1", 7975 auxType: auxSymValAndOff, 7976 argLen: 3, 7977 symEffect: SymWrite, 7978 asm: x86.AMOVL, 7979 reg: regInfo{ 7980 inputs: []inputInfo{ 7981 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7982 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7983 }, 7984 }, 7985 }, 7986 { 7987 name: "MOVLstoreconstidx4", 7988 auxType: auxSymValAndOff, 7989 argLen: 3, 7990 symEffect: SymWrite, 7991 asm: x86.AMOVL, 7992 reg: regInfo{ 7993 inputs: []inputInfo{ 7994 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 7995 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 7996 }, 7997 }, 7998 }, 7999 { 8000 name: "MOVQstoreconstidx1", 8001 auxType: auxSymValAndOff, 8002 argLen: 3, 8003 symEffect: SymWrite, 8004 asm: x86.AMOVQ, 8005 reg: regInfo{ 8006 inputs: []inputInfo{ 8007 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8008 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8009 }, 8010 }, 8011 }, 8012 { 8013 name: "MOVQstoreconstidx8", 8014 auxType: auxSymValAndOff, 8015 argLen: 3, 8016 symEffect: SymWrite, 8017 asm: x86.AMOVQ, 8018 reg: regInfo{ 8019 inputs: []inputInfo{ 8020 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8021 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8022 }, 8023 }, 8024 }, 8025 { 8026 name: "DUFFZERO", 8027 auxType: auxInt64, 8028 argLen: 3, 8029 faultOnNilArg0: true, 8030 reg: regInfo{ 8031 inputs: []inputInfo{ 8032 {0, 128}, // DI 8033 {1, 65536}, // X0 8034 }, 8035 clobbers: 128, // DI 8036 }, 8037 }, 8038 { 8039 name: "MOVOconst", 8040 auxType: auxInt128, 8041 argLen: 0, 8042 rematerializeable: true, 8043 reg: regInfo{ 8044 outputs: []outputInfo{ 8045 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8046 }, 8047 }, 8048 }, 8049 { 8050 name: "REPSTOSQ", 8051 argLen: 4, 8052 faultOnNilArg0: true, 8053 reg: regInfo{ 8054 inputs: []inputInfo{ 8055 {0, 128}, // DI 8056 {1, 2}, // CX 8057 {2, 1}, // AX 8058 }, 8059 clobbers: 130, // CX DI 8060 }, 8061 }, 8062 { 8063 name: "CALLstatic", 8064 auxType: auxSymOff, 8065 argLen: 1, 8066 clobberFlags: true, 8067 call: true, 8068 symEffect: SymNone, 8069 reg: regInfo{ 8070 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8071 }, 8072 }, 8073 { 8074 name: "CALLclosure", 8075 auxType: auxInt64, 8076 argLen: 3, 8077 clobberFlags: true, 8078 call: true, 8079 reg: regInfo{ 8080 inputs: []inputInfo{ 8081 {1, 4}, // DX 8082 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8083 }, 8084 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8085 }, 8086 }, 8087 { 8088 name: "CALLinter", 8089 auxType: auxInt64, 8090 argLen: 2, 8091 clobberFlags: true, 8092 call: true, 8093 reg: regInfo{ 8094 inputs: []inputInfo{ 8095 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8096 }, 8097 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8098 }, 8099 }, 8100 { 8101 name: "DUFFCOPY", 8102 auxType: auxInt64, 8103 argLen: 3, 8104 clobberFlags: true, 8105 faultOnNilArg0: true, 8106 faultOnNilArg1: true, 8107 reg: regInfo{ 8108 inputs: []inputInfo{ 8109 {0, 128}, // DI 8110 {1, 64}, // SI 8111 }, 8112 clobbers: 65728, // SI DI X0 8113 }, 8114 }, 8115 { 8116 name: "REPMOVSQ", 8117 argLen: 4, 8118 faultOnNilArg0: true, 8119 faultOnNilArg1: true, 8120 reg: regInfo{ 8121 inputs: []inputInfo{ 8122 {0, 128}, // DI 8123 {1, 64}, // SI 8124 {2, 2}, // CX 8125 }, 8126 clobbers: 194, // CX SI DI 8127 }, 8128 }, 8129 { 8130 name: "InvertFlags", 8131 argLen: 1, 8132 reg: regInfo{}, 8133 }, 8134 { 8135 name: "LoweredGetG", 8136 argLen: 1, 8137 reg: regInfo{ 8138 outputs: []outputInfo{ 8139 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8140 }, 8141 }, 8142 }, 8143 { 8144 name: "LoweredGetClosurePtr", 8145 argLen: 0, 8146 reg: regInfo{ 8147 outputs: []outputInfo{ 8148 {0, 4}, // DX 8149 }, 8150 }, 8151 }, 8152 { 8153 name: "LoweredGetCallerPC", 8154 argLen: 0, 8155 rematerializeable: true, 8156 reg: regInfo{ 8157 outputs: []outputInfo{ 8158 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8159 }, 8160 }, 8161 }, 8162 { 8163 name: "LoweredGetCallerSP", 8164 argLen: 0, 8165 rematerializeable: true, 8166 reg: regInfo{ 8167 outputs: []outputInfo{ 8168 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8169 }, 8170 }, 8171 }, 8172 { 8173 name: "LoweredNilCheck", 8174 argLen: 2, 8175 clobberFlags: true, 8176 nilCheck: true, 8177 faultOnNilArg0: true, 8178 reg: regInfo{ 8179 inputs: []inputInfo{ 8180 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8181 }, 8182 }, 8183 }, 8184 { 8185 name: "LoweredWB", 8186 auxType: auxSym, 8187 argLen: 3, 8188 clobberFlags: true, 8189 symEffect: SymNone, 8190 reg: regInfo{ 8191 inputs: []inputInfo{ 8192 {0, 128}, // DI 8193 {1, 1}, // AX 8194 }, 8195 clobbers: 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 8196 }, 8197 }, 8198 { 8199 name: "MOVQconvert", 8200 argLen: 2, 8201 resultInArg0: true, 8202 asm: x86.AMOVQ, 8203 reg: regInfo{ 8204 inputs: []inputInfo{ 8205 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8206 }, 8207 outputs: []outputInfo{ 8208 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8209 }, 8210 }, 8211 }, 8212 { 8213 name: "MOVLconvert", 8214 argLen: 2, 8215 resultInArg0: true, 8216 asm: x86.AMOVL, 8217 reg: regInfo{ 8218 inputs: []inputInfo{ 8219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8220 }, 8221 outputs: []outputInfo{ 8222 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8223 }, 8224 }, 8225 }, 8226 { 8227 name: "FlagEQ", 8228 argLen: 0, 8229 reg: regInfo{}, 8230 }, 8231 { 8232 name: "FlagLT_ULT", 8233 argLen: 0, 8234 reg: regInfo{}, 8235 }, 8236 { 8237 name: "FlagLT_UGT", 8238 argLen: 0, 8239 reg: regInfo{}, 8240 }, 8241 { 8242 name: "FlagGT_UGT", 8243 argLen: 0, 8244 reg: regInfo{}, 8245 }, 8246 { 8247 name: "FlagGT_ULT", 8248 argLen: 0, 8249 reg: regInfo{}, 8250 }, 8251 { 8252 name: "MOVLatomicload", 8253 auxType: auxSymOff, 8254 argLen: 2, 8255 faultOnNilArg0: true, 8256 symEffect: SymRead, 8257 asm: x86.AMOVL, 8258 reg: regInfo{ 8259 inputs: []inputInfo{ 8260 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8261 }, 8262 outputs: []outputInfo{ 8263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8264 }, 8265 }, 8266 }, 8267 { 8268 name: "MOVQatomicload", 8269 auxType: auxSymOff, 8270 argLen: 2, 8271 faultOnNilArg0: true, 8272 symEffect: SymRead, 8273 asm: x86.AMOVQ, 8274 reg: regInfo{ 8275 inputs: []inputInfo{ 8276 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8277 }, 8278 outputs: []outputInfo{ 8279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8280 }, 8281 }, 8282 }, 8283 { 8284 name: "XCHGL", 8285 auxType: auxSymOff, 8286 argLen: 3, 8287 resultInArg0: true, 8288 faultOnNilArg1: true, 8289 hasSideEffects: true, 8290 symEffect: SymRdWr, 8291 asm: x86.AXCHGL, 8292 reg: regInfo{ 8293 inputs: []inputInfo{ 8294 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8295 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8296 }, 8297 outputs: []outputInfo{ 8298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8299 }, 8300 }, 8301 }, 8302 { 8303 name: "XCHGQ", 8304 auxType: auxSymOff, 8305 argLen: 3, 8306 resultInArg0: true, 8307 faultOnNilArg1: true, 8308 hasSideEffects: true, 8309 symEffect: SymRdWr, 8310 asm: x86.AXCHGQ, 8311 reg: regInfo{ 8312 inputs: []inputInfo{ 8313 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8314 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8315 }, 8316 outputs: []outputInfo{ 8317 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8318 }, 8319 }, 8320 }, 8321 { 8322 name: "XADDLlock", 8323 auxType: auxSymOff, 8324 argLen: 3, 8325 resultInArg0: true, 8326 clobberFlags: true, 8327 faultOnNilArg1: true, 8328 hasSideEffects: true, 8329 symEffect: SymRdWr, 8330 asm: x86.AXADDL, 8331 reg: regInfo{ 8332 inputs: []inputInfo{ 8333 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8334 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8335 }, 8336 outputs: []outputInfo{ 8337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8338 }, 8339 }, 8340 }, 8341 { 8342 name: "XADDQlock", 8343 auxType: auxSymOff, 8344 argLen: 3, 8345 resultInArg0: true, 8346 clobberFlags: true, 8347 faultOnNilArg1: true, 8348 hasSideEffects: true, 8349 symEffect: SymRdWr, 8350 asm: x86.AXADDQ, 8351 reg: regInfo{ 8352 inputs: []inputInfo{ 8353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8354 {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8355 }, 8356 outputs: []outputInfo{ 8357 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8358 }, 8359 }, 8360 }, 8361 { 8362 name: "AddTupleFirst32", 8363 argLen: 2, 8364 reg: regInfo{}, 8365 }, 8366 { 8367 name: "AddTupleFirst64", 8368 argLen: 2, 8369 reg: regInfo{}, 8370 }, 8371 { 8372 name: "CMPXCHGLlock", 8373 auxType: auxSymOff, 8374 argLen: 4, 8375 clobberFlags: true, 8376 faultOnNilArg0: true, 8377 hasSideEffects: true, 8378 symEffect: SymRdWr, 8379 asm: x86.ACMPXCHGL, 8380 reg: regInfo{ 8381 inputs: []inputInfo{ 8382 {1, 1}, // AX 8383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8384 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8385 }, 8386 clobbers: 1, // AX 8387 outputs: []outputInfo{ 8388 {1, 0}, 8389 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8390 }, 8391 }, 8392 }, 8393 { 8394 name: "CMPXCHGQlock", 8395 auxType: auxSymOff, 8396 argLen: 4, 8397 clobberFlags: true, 8398 faultOnNilArg0: true, 8399 hasSideEffects: true, 8400 symEffect: SymRdWr, 8401 asm: x86.ACMPXCHGQ, 8402 reg: regInfo{ 8403 inputs: []inputInfo{ 8404 {1, 1}, // AX 8405 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8406 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8407 }, 8408 clobbers: 1, // AX 8409 outputs: []outputInfo{ 8410 {1, 0}, 8411 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8412 }, 8413 }, 8414 }, 8415 { 8416 name: "ANDBlock", 8417 auxType: auxSymOff, 8418 argLen: 3, 8419 clobberFlags: true, 8420 faultOnNilArg0: true, 8421 hasSideEffects: true, 8422 symEffect: SymRdWr, 8423 asm: x86.AANDB, 8424 reg: regInfo{ 8425 inputs: []inputInfo{ 8426 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8427 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8428 }, 8429 }, 8430 }, 8431 { 8432 name: "ORBlock", 8433 auxType: auxSymOff, 8434 argLen: 3, 8435 clobberFlags: true, 8436 faultOnNilArg0: true, 8437 hasSideEffects: true, 8438 symEffect: SymRdWr, 8439 asm: x86.AORB, 8440 reg: regInfo{ 8441 inputs: []inputInfo{ 8442 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 8443 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 8444 }, 8445 }, 8446 }, 8447 8448 { 8449 name: "ADD", 8450 argLen: 2, 8451 commutative: true, 8452 asm: arm.AADD, 8453 reg: regInfo{ 8454 inputs: []inputInfo{ 8455 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8456 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8457 }, 8458 outputs: []outputInfo{ 8459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8460 }, 8461 }, 8462 }, 8463 { 8464 name: "ADDconst", 8465 auxType: auxInt32, 8466 argLen: 1, 8467 asm: arm.AADD, 8468 reg: regInfo{ 8469 inputs: []inputInfo{ 8470 {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 8471 }, 8472 outputs: []outputInfo{ 8473 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8474 }, 8475 }, 8476 }, 8477 { 8478 name: "SUB", 8479 argLen: 2, 8480 asm: arm.ASUB, 8481 reg: regInfo{ 8482 inputs: []inputInfo{ 8483 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8484 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8485 }, 8486 outputs: []outputInfo{ 8487 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8488 }, 8489 }, 8490 }, 8491 { 8492 name: "SUBconst", 8493 auxType: auxInt32, 8494 argLen: 1, 8495 asm: arm.ASUB, 8496 reg: regInfo{ 8497 inputs: []inputInfo{ 8498 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8499 }, 8500 outputs: []outputInfo{ 8501 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8502 }, 8503 }, 8504 }, 8505 { 8506 name: "RSB", 8507 argLen: 2, 8508 asm: arm.ARSB, 8509 reg: regInfo{ 8510 inputs: []inputInfo{ 8511 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8512 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8513 }, 8514 outputs: []outputInfo{ 8515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8516 }, 8517 }, 8518 }, 8519 { 8520 name: "RSBconst", 8521 auxType: auxInt32, 8522 argLen: 1, 8523 asm: arm.ARSB, 8524 reg: regInfo{ 8525 inputs: []inputInfo{ 8526 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8527 }, 8528 outputs: []outputInfo{ 8529 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8530 }, 8531 }, 8532 }, 8533 { 8534 name: "MUL", 8535 argLen: 2, 8536 commutative: true, 8537 asm: arm.AMUL, 8538 reg: regInfo{ 8539 inputs: []inputInfo{ 8540 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8541 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8542 }, 8543 outputs: []outputInfo{ 8544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8545 }, 8546 }, 8547 }, 8548 { 8549 name: "HMUL", 8550 argLen: 2, 8551 commutative: true, 8552 asm: arm.AMULL, 8553 reg: regInfo{ 8554 inputs: []inputInfo{ 8555 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8556 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8557 }, 8558 outputs: []outputInfo{ 8559 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8560 }, 8561 }, 8562 }, 8563 { 8564 name: "HMULU", 8565 argLen: 2, 8566 commutative: true, 8567 asm: arm.AMULLU, 8568 reg: regInfo{ 8569 inputs: []inputInfo{ 8570 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8571 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8572 }, 8573 outputs: []outputInfo{ 8574 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8575 }, 8576 }, 8577 }, 8578 { 8579 name: "CALLudiv", 8580 argLen: 2, 8581 clobberFlags: true, 8582 reg: regInfo{ 8583 inputs: []inputInfo{ 8584 {0, 2}, // R1 8585 {1, 1}, // R0 8586 }, 8587 clobbers: 16396, // R2 R3 R14 8588 outputs: []outputInfo{ 8589 {0, 1}, // R0 8590 {1, 2}, // R1 8591 }, 8592 }, 8593 }, 8594 { 8595 name: "ADDS", 8596 argLen: 2, 8597 commutative: true, 8598 asm: arm.AADD, 8599 reg: regInfo{ 8600 inputs: []inputInfo{ 8601 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8602 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8603 }, 8604 outputs: []outputInfo{ 8605 {1, 0}, 8606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8607 }, 8608 }, 8609 }, 8610 { 8611 name: "ADDSconst", 8612 auxType: auxInt32, 8613 argLen: 1, 8614 asm: arm.AADD, 8615 reg: regInfo{ 8616 inputs: []inputInfo{ 8617 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8618 }, 8619 outputs: []outputInfo{ 8620 {1, 0}, 8621 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8622 }, 8623 }, 8624 }, 8625 { 8626 name: "ADC", 8627 argLen: 3, 8628 commutative: true, 8629 asm: arm.AADC, 8630 reg: regInfo{ 8631 inputs: []inputInfo{ 8632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8633 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8634 }, 8635 outputs: []outputInfo{ 8636 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8637 }, 8638 }, 8639 }, 8640 { 8641 name: "ADCconst", 8642 auxType: auxInt32, 8643 argLen: 2, 8644 asm: arm.AADC, 8645 reg: regInfo{ 8646 inputs: []inputInfo{ 8647 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8648 }, 8649 outputs: []outputInfo{ 8650 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8651 }, 8652 }, 8653 }, 8654 { 8655 name: "SUBS", 8656 argLen: 2, 8657 asm: arm.ASUB, 8658 reg: regInfo{ 8659 inputs: []inputInfo{ 8660 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8661 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8662 }, 8663 outputs: []outputInfo{ 8664 {1, 0}, 8665 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8666 }, 8667 }, 8668 }, 8669 { 8670 name: "SUBSconst", 8671 auxType: auxInt32, 8672 argLen: 1, 8673 asm: arm.ASUB, 8674 reg: regInfo{ 8675 inputs: []inputInfo{ 8676 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8677 }, 8678 outputs: []outputInfo{ 8679 {1, 0}, 8680 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8681 }, 8682 }, 8683 }, 8684 { 8685 name: "RSBSconst", 8686 auxType: auxInt32, 8687 argLen: 1, 8688 asm: arm.ARSB, 8689 reg: regInfo{ 8690 inputs: []inputInfo{ 8691 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8692 }, 8693 outputs: []outputInfo{ 8694 {1, 0}, 8695 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8696 }, 8697 }, 8698 }, 8699 { 8700 name: "SBC", 8701 argLen: 3, 8702 asm: arm.ASBC, 8703 reg: regInfo{ 8704 inputs: []inputInfo{ 8705 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8706 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8707 }, 8708 outputs: []outputInfo{ 8709 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8710 }, 8711 }, 8712 }, 8713 { 8714 name: "SBCconst", 8715 auxType: auxInt32, 8716 argLen: 2, 8717 asm: arm.ASBC, 8718 reg: regInfo{ 8719 inputs: []inputInfo{ 8720 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8721 }, 8722 outputs: []outputInfo{ 8723 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8724 }, 8725 }, 8726 }, 8727 { 8728 name: "RSCconst", 8729 auxType: auxInt32, 8730 argLen: 2, 8731 asm: arm.ARSC, 8732 reg: regInfo{ 8733 inputs: []inputInfo{ 8734 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8735 }, 8736 outputs: []outputInfo{ 8737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8738 }, 8739 }, 8740 }, 8741 { 8742 name: "MULLU", 8743 argLen: 2, 8744 commutative: true, 8745 asm: arm.AMULLU, 8746 reg: regInfo{ 8747 inputs: []inputInfo{ 8748 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8749 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 8750 }, 8751 outputs: []outputInfo{ 8752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8753 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8754 }, 8755 }, 8756 }, 8757 { 8758 name: "MULA", 8759 argLen: 3, 8760 asm: arm.AMULA, 8761 reg: regInfo{ 8762 inputs: []inputInfo{ 8763 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8764 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8765 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8766 }, 8767 outputs: []outputInfo{ 8768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8769 }, 8770 }, 8771 }, 8772 { 8773 name: "MULS", 8774 argLen: 3, 8775 asm: arm.AMULS, 8776 reg: regInfo{ 8777 inputs: []inputInfo{ 8778 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8779 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8780 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8781 }, 8782 outputs: []outputInfo{ 8783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 8784 }, 8785 }, 8786 }, 8787 { 8788 name: "ADDF", 8789 argLen: 2, 8790 commutative: true, 8791 asm: arm.AADDF, 8792 reg: regInfo{ 8793 inputs: []inputInfo{ 8794 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8795 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8796 }, 8797 outputs: []outputInfo{ 8798 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8799 }, 8800 }, 8801 }, 8802 { 8803 name: "ADDD", 8804 argLen: 2, 8805 commutative: true, 8806 asm: arm.AADDD, 8807 reg: regInfo{ 8808 inputs: []inputInfo{ 8809 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8810 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8811 }, 8812 outputs: []outputInfo{ 8813 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8814 }, 8815 }, 8816 }, 8817 { 8818 name: "SUBF", 8819 argLen: 2, 8820 asm: arm.ASUBF, 8821 reg: regInfo{ 8822 inputs: []inputInfo{ 8823 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8824 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8825 }, 8826 outputs: []outputInfo{ 8827 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8828 }, 8829 }, 8830 }, 8831 { 8832 name: "SUBD", 8833 argLen: 2, 8834 asm: arm.ASUBD, 8835 reg: regInfo{ 8836 inputs: []inputInfo{ 8837 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8838 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8839 }, 8840 outputs: []outputInfo{ 8841 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8842 }, 8843 }, 8844 }, 8845 { 8846 name: "MULF", 8847 argLen: 2, 8848 commutative: true, 8849 asm: arm.AMULF, 8850 reg: regInfo{ 8851 inputs: []inputInfo{ 8852 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8853 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8854 }, 8855 outputs: []outputInfo{ 8856 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8857 }, 8858 }, 8859 }, 8860 { 8861 name: "MULD", 8862 argLen: 2, 8863 commutative: true, 8864 asm: arm.AMULD, 8865 reg: regInfo{ 8866 inputs: []inputInfo{ 8867 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8868 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8869 }, 8870 outputs: []outputInfo{ 8871 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8872 }, 8873 }, 8874 }, 8875 { 8876 name: "NMULF", 8877 argLen: 2, 8878 commutative: true, 8879 asm: arm.ANMULF, 8880 reg: regInfo{ 8881 inputs: []inputInfo{ 8882 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8883 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8884 }, 8885 outputs: []outputInfo{ 8886 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8887 }, 8888 }, 8889 }, 8890 { 8891 name: "NMULD", 8892 argLen: 2, 8893 commutative: true, 8894 asm: arm.ANMULD, 8895 reg: regInfo{ 8896 inputs: []inputInfo{ 8897 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8898 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8899 }, 8900 outputs: []outputInfo{ 8901 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8902 }, 8903 }, 8904 }, 8905 { 8906 name: "DIVF", 8907 argLen: 2, 8908 asm: arm.ADIVF, 8909 reg: regInfo{ 8910 inputs: []inputInfo{ 8911 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8912 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8913 }, 8914 outputs: []outputInfo{ 8915 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8916 }, 8917 }, 8918 }, 8919 { 8920 name: "DIVD", 8921 argLen: 2, 8922 asm: arm.ADIVD, 8923 reg: regInfo{ 8924 inputs: []inputInfo{ 8925 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8926 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8927 }, 8928 outputs: []outputInfo{ 8929 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8930 }, 8931 }, 8932 }, 8933 { 8934 name: "MULAF", 8935 argLen: 3, 8936 resultInArg0: true, 8937 asm: arm.AMULAF, 8938 reg: regInfo{ 8939 inputs: []inputInfo{ 8940 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8941 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8942 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8943 }, 8944 outputs: []outputInfo{ 8945 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8946 }, 8947 }, 8948 }, 8949 { 8950 name: "MULAD", 8951 argLen: 3, 8952 resultInArg0: true, 8953 asm: arm.AMULAD, 8954 reg: regInfo{ 8955 inputs: []inputInfo{ 8956 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8957 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8958 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8959 }, 8960 outputs: []outputInfo{ 8961 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8962 }, 8963 }, 8964 }, 8965 { 8966 name: "MULSF", 8967 argLen: 3, 8968 resultInArg0: true, 8969 asm: arm.AMULSF, 8970 reg: regInfo{ 8971 inputs: []inputInfo{ 8972 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8973 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8974 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8975 }, 8976 outputs: []outputInfo{ 8977 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8978 }, 8979 }, 8980 }, 8981 { 8982 name: "MULSD", 8983 argLen: 3, 8984 resultInArg0: true, 8985 asm: arm.AMULSD, 8986 reg: regInfo{ 8987 inputs: []inputInfo{ 8988 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8989 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8990 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8991 }, 8992 outputs: []outputInfo{ 8993 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 8994 }, 8995 }, 8996 }, 8997 { 8998 name: "AND", 8999 argLen: 2, 9000 commutative: true, 9001 asm: arm.AAND, 9002 reg: regInfo{ 9003 inputs: []inputInfo{ 9004 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9005 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9006 }, 9007 outputs: []outputInfo{ 9008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9009 }, 9010 }, 9011 }, 9012 { 9013 name: "ANDconst", 9014 auxType: auxInt32, 9015 argLen: 1, 9016 asm: arm.AAND, 9017 reg: regInfo{ 9018 inputs: []inputInfo{ 9019 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9020 }, 9021 outputs: []outputInfo{ 9022 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9023 }, 9024 }, 9025 }, 9026 { 9027 name: "OR", 9028 argLen: 2, 9029 commutative: true, 9030 asm: arm.AORR, 9031 reg: regInfo{ 9032 inputs: []inputInfo{ 9033 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9034 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9035 }, 9036 outputs: []outputInfo{ 9037 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9038 }, 9039 }, 9040 }, 9041 { 9042 name: "ORconst", 9043 auxType: auxInt32, 9044 argLen: 1, 9045 asm: arm.AORR, 9046 reg: regInfo{ 9047 inputs: []inputInfo{ 9048 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9049 }, 9050 outputs: []outputInfo{ 9051 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9052 }, 9053 }, 9054 }, 9055 { 9056 name: "XOR", 9057 argLen: 2, 9058 commutative: true, 9059 asm: arm.AEOR, 9060 reg: regInfo{ 9061 inputs: []inputInfo{ 9062 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9063 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9064 }, 9065 outputs: []outputInfo{ 9066 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9067 }, 9068 }, 9069 }, 9070 { 9071 name: "XORconst", 9072 auxType: auxInt32, 9073 argLen: 1, 9074 asm: arm.AEOR, 9075 reg: regInfo{ 9076 inputs: []inputInfo{ 9077 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9078 }, 9079 outputs: []outputInfo{ 9080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9081 }, 9082 }, 9083 }, 9084 { 9085 name: "BIC", 9086 argLen: 2, 9087 asm: arm.ABIC, 9088 reg: regInfo{ 9089 inputs: []inputInfo{ 9090 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9091 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9092 }, 9093 outputs: []outputInfo{ 9094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9095 }, 9096 }, 9097 }, 9098 { 9099 name: "BICconst", 9100 auxType: auxInt32, 9101 argLen: 1, 9102 asm: arm.ABIC, 9103 reg: regInfo{ 9104 inputs: []inputInfo{ 9105 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9106 }, 9107 outputs: []outputInfo{ 9108 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9109 }, 9110 }, 9111 }, 9112 { 9113 name: "BFX", 9114 auxType: auxInt32, 9115 argLen: 1, 9116 asm: arm.ABFX, 9117 reg: regInfo{ 9118 inputs: []inputInfo{ 9119 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9120 }, 9121 outputs: []outputInfo{ 9122 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9123 }, 9124 }, 9125 }, 9126 { 9127 name: "BFXU", 9128 auxType: auxInt32, 9129 argLen: 1, 9130 asm: arm.ABFXU, 9131 reg: regInfo{ 9132 inputs: []inputInfo{ 9133 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9134 }, 9135 outputs: []outputInfo{ 9136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9137 }, 9138 }, 9139 }, 9140 { 9141 name: "MVN", 9142 argLen: 1, 9143 asm: arm.AMVN, 9144 reg: regInfo{ 9145 inputs: []inputInfo{ 9146 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9147 }, 9148 outputs: []outputInfo{ 9149 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9150 }, 9151 }, 9152 }, 9153 { 9154 name: "NEGF", 9155 argLen: 1, 9156 asm: arm.ANEGF, 9157 reg: regInfo{ 9158 inputs: []inputInfo{ 9159 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9160 }, 9161 outputs: []outputInfo{ 9162 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9163 }, 9164 }, 9165 }, 9166 { 9167 name: "NEGD", 9168 argLen: 1, 9169 asm: arm.ANEGD, 9170 reg: regInfo{ 9171 inputs: []inputInfo{ 9172 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9173 }, 9174 outputs: []outputInfo{ 9175 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9176 }, 9177 }, 9178 }, 9179 { 9180 name: "SQRTD", 9181 argLen: 1, 9182 asm: arm.ASQRTD, 9183 reg: regInfo{ 9184 inputs: []inputInfo{ 9185 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9186 }, 9187 outputs: []outputInfo{ 9188 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9189 }, 9190 }, 9191 }, 9192 { 9193 name: "CLZ", 9194 argLen: 1, 9195 asm: arm.ACLZ, 9196 reg: regInfo{ 9197 inputs: []inputInfo{ 9198 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9199 }, 9200 outputs: []outputInfo{ 9201 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9202 }, 9203 }, 9204 }, 9205 { 9206 name: "REV", 9207 argLen: 1, 9208 asm: arm.AREV, 9209 reg: regInfo{ 9210 inputs: []inputInfo{ 9211 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9212 }, 9213 outputs: []outputInfo{ 9214 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9215 }, 9216 }, 9217 }, 9218 { 9219 name: "RBIT", 9220 argLen: 1, 9221 asm: arm.ARBIT, 9222 reg: regInfo{ 9223 inputs: []inputInfo{ 9224 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9225 }, 9226 outputs: []outputInfo{ 9227 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9228 }, 9229 }, 9230 }, 9231 { 9232 name: "SLL", 9233 argLen: 2, 9234 asm: arm.ASLL, 9235 reg: regInfo{ 9236 inputs: []inputInfo{ 9237 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9238 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9239 }, 9240 outputs: []outputInfo{ 9241 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9242 }, 9243 }, 9244 }, 9245 { 9246 name: "SLLconst", 9247 auxType: auxInt32, 9248 argLen: 1, 9249 asm: arm.ASLL, 9250 reg: regInfo{ 9251 inputs: []inputInfo{ 9252 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9253 }, 9254 outputs: []outputInfo{ 9255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9256 }, 9257 }, 9258 }, 9259 { 9260 name: "SRL", 9261 argLen: 2, 9262 asm: arm.ASRL, 9263 reg: regInfo{ 9264 inputs: []inputInfo{ 9265 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9266 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9267 }, 9268 outputs: []outputInfo{ 9269 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9270 }, 9271 }, 9272 }, 9273 { 9274 name: "SRLconst", 9275 auxType: auxInt32, 9276 argLen: 1, 9277 asm: arm.ASRL, 9278 reg: regInfo{ 9279 inputs: []inputInfo{ 9280 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9281 }, 9282 outputs: []outputInfo{ 9283 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9284 }, 9285 }, 9286 }, 9287 { 9288 name: "SRA", 9289 argLen: 2, 9290 asm: arm.ASRA, 9291 reg: regInfo{ 9292 inputs: []inputInfo{ 9293 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9294 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9295 }, 9296 outputs: []outputInfo{ 9297 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9298 }, 9299 }, 9300 }, 9301 { 9302 name: "SRAconst", 9303 auxType: auxInt32, 9304 argLen: 1, 9305 asm: arm.ASRA, 9306 reg: regInfo{ 9307 inputs: []inputInfo{ 9308 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9309 }, 9310 outputs: []outputInfo{ 9311 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9312 }, 9313 }, 9314 }, 9315 { 9316 name: "SRRconst", 9317 auxType: auxInt32, 9318 argLen: 1, 9319 reg: regInfo{ 9320 inputs: []inputInfo{ 9321 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9322 }, 9323 outputs: []outputInfo{ 9324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9325 }, 9326 }, 9327 }, 9328 { 9329 name: "ADDshiftLL", 9330 auxType: auxInt32, 9331 argLen: 2, 9332 asm: arm.AADD, 9333 reg: regInfo{ 9334 inputs: []inputInfo{ 9335 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9336 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9337 }, 9338 outputs: []outputInfo{ 9339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9340 }, 9341 }, 9342 }, 9343 { 9344 name: "ADDshiftRL", 9345 auxType: auxInt32, 9346 argLen: 2, 9347 asm: arm.AADD, 9348 reg: regInfo{ 9349 inputs: []inputInfo{ 9350 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9351 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9352 }, 9353 outputs: []outputInfo{ 9354 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9355 }, 9356 }, 9357 }, 9358 { 9359 name: "ADDshiftRA", 9360 auxType: auxInt32, 9361 argLen: 2, 9362 asm: arm.AADD, 9363 reg: regInfo{ 9364 inputs: []inputInfo{ 9365 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9366 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9367 }, 9368 outputs: []outputInfo{ 9369 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9370 }, 9371 }, 9372 }, 9373 { 9374 name: "SUBshiftLL", 9375 auxType: auxInt32, 9376 argLen: 2, 9377 asm: arm.ASUB, 9378 reg: regInfo{ 9379 inputs: []inputInfo{ 9380 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9381 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9382 }, 9383 outputs: []outputInfo{ 9384 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9385 }, 9386 }, 9387 }, 9388 { 9389 name: "SUBshiftRL", 9390 auxType: auxInt32, 9391 argLen: 2, 9392 asm: arm.ASUB, 9393 reg: regInfo{ 9394 inputs: []inputInfo{ 9395 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9396 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9397 }, 9398 outputs: []outputInfo{ 9399 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9400 }, 9401 }, 9402 }, 9403 { 9404 name: "SUBshiftRA", 9405 auxType: auxInt32, 9406 argLen: 2, 9407 asm: arm.ASUB, 9408 reg: regInfo{ 9409 inputs: []inputInfo{ 9410 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9411 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9412 }, 9413 outputs: []outputInfo{ 9414 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9415 }, 9416 }, 9417 }, 9418 { 9419 name: "RSBshiftLL", 9420 auxType: auxInt32, 9421 argLen: 2, 9422 asm: arm.ARSB, 9423 reg: regInfo{ 9424 inputs: []inputInfo{ 9425 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9426 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9427 }, 9428 outputs: []outputInfo{ 9429 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9430 }, 9431 }, 9432 }, 9433 { 9434 name: "RSBshiftRL", 9435 auxType: auxInt32, 9436 argLen: 2, 9437 asm: arm.ARSB, 9438 reg: regInfo{ 9439 inputs: []inputInfo{ 9440 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9441 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9442 }, 9443 outputs: []outputInfo{ 9444 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9445 }, 9446 }, 9447 }, 9448 { 9449 name: "RSBshiftRA", 9450 auxType: auxInt32, 9451 argLen: 2, 9452 asm: arm.ARSB, 9453 reg: regInfo{ 9454 inputs: []inputInfo{ 9455 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9456 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9457 }, 9458 outputs: []outputInfo{ 9459 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9460 }, 9461 }, 9462 }, 9463 { 9464 name: "ANDshiftLL", 9465 auxType: auxInt32, 9466 argLen: 2, 9467 asm: arm.AAND, 9468 reg: regInfo{ 9469 inputs: []inputInfo{ 9470 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9471 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9472 }, 9473 outputs: []outputInfo{ 9474 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9475 }, 9476 }, 9477 }, 9478 { 9479 name: "ANDshiftRL", 9480 auxType: auxInt32, 9481 argLen: 2, 9482 asm: arm.AAND, 9483 reg: regInfo{ 9484 inputs: []inputInfo{ 9485 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9486 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9487 }, 9488 outputs: []outputInfo{ 9489 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9490 }, 9491 }, 9492 }, 9493 { 9494 name: "ANDshiftRA", 9495 auxType: auxInt32, 9496 argLen: 2, 9497 asm: arm.AAND, 9498 reg: regInfo{ 9499 inputs: []inputInfo{ 9500 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9501 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9502 }, 9503 outputs: []outputInfo{ 9504 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9505 }, 9506 }, 9507 }, 9508 { 9509 name: "ORshiftLL", 9510 auxType: auxInt32, 9511 argLen: 2, 9512 asm: arm.AORR, 9513 reg: regInfo{ 9514 inputs: []inputInfo{ 9515 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9516 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9517 }, 9518 outputs: []outputInfo{ 9519 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9520 }, 9521 }, 9522 }, 9523 { 9524 name: "ORshiftRL", 9525 auxType: auxInt32, 9526 argLen: 2, 9527 asm: arm.AORR, 9528 reg: regInfo{ 9529 inputs: []inputInfo{ 9530 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9531 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9532 }, 9533 outputs: []outputInfo{ 9534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9535 }, 9536 }, 9537 }, 9538 { 9539 name: "ORshiftRA", 9540 auxType: auxInt32, 9541 argLen: 2, 9542 asm: arm.AORR, 9543 reg: regInfo{ 9544 inputs: []inputInfo{ 9545 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9546 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9547 }, 9548 outputs: []outputInfo{ 9549 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9550 }, 9551 }, 9552 }, 9553 { 9554 name: "XORshiftLL", 9555 auxType: auxInt32, 9556 argLen: 2, 9557 asm: arm.AEOR, 9558 reg: regInfo{ 9559 inputs: []inputInfo{ 9560 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9561 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9562 }, 9563 outputs: []outputInfo{ 9564 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9565 }, 9566 }, 9567 }, 9568 { 9569 name: "XORshiftRL", 9570 auxType: auxInt32, 9571 argLen: 2, 9572 asm: arm.AEOR, 9573 reg: regInfo{ 9574 inputs: []inputInfo{ 9575 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9576 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9577 }, 9578 outputs: []outputInfo{ 9579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9580 }, 9581 }, 9582 }, 9583 { 9584 name: "XORshiftRA", 9585 auxType: auxInt32, 9586 argLen: 2, 9587 asm: arm.AEOR, 9588 reg: regInfo{ 9589 inputs: []inputInfo{ 9590 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9591 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9592 }, 9593 outputs: []outputInfo{ 9594 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9595 }, 9596 }, 9597 }, 9598 { 9599 name: "XORshiftRR", 9600 auxType: auxInt32, 9601 argLen: 2, 9602 asm: arm.AEOR, 9603 reg: regInfo{ 9604 inputs: []inputInfo{ 9605 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9606 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9607 }, 9608 outputs: []outputInfo{ 9609 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9610 }, 9611 }, 9612 }, 9613 { 9614 name: "BICshiftLL", 9615 auxType: auxInt32, 9616 argLen: 2, 9617 asm: arm.ABIC, 9618 reg: regInfo{ 9619 inputs: []inputInfo{ 9620 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9621 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9622 }, 9623 outputs: []outputInfo{ 9624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9625 }, 9626 }, 9627 }, 9628 { 9629 name: "BICshiftRL", 9630 auxType: auxInt32, 9631 argLen: 2, 9632 asm: arm.ABIC, 9633 reg: regInfo{ 9634 inputs: []inputInfo{ 9635 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9636 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9637 }, 9638 outputs: []outputInfo{ 9639 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9640 }, 9641 }, 9642 }, 9643 { 9644 name: "BICshiftRA", 9645 auxType: auxInt32, 9646 argLen: 2, 9647 asm: arm.ABIC, 9648 reg: regInfo{ 9649 inputs: []inputInfo{ 9650 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9651 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9652 }, 9653 outputs: []outputInfo{ 9654 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9655 }, 9656 }, 9657 }, 9658 { 9659 name: "MVNshiftLL", 9660 auxType: auxInt32, 9661 argLen: 1, 9662 asm: arm.AMVN, 9663 reg: regInfo{ 9664 inputs: []inputInfo{ 9665 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9666 }, 9667 outputs: []outputInfo{ 9668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9669 }, 9670 }, 9671 }, 9672 { 9673 name: "MVNshiftRL", 9674 auxType: auxInt32, 9675 argLen: 1, 9676 asm: arm.AMVN, 9677 reg: regInfo{ 9678 inputs: []inputInfo{ 9679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9680 }, 9681 outputs: []outputInfo{ 9682 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9683 }, 9684 }, 9685 }, 9686 { 9687 name: "MVNshiftRA", 9688 auxType: auxInt32, 9689 argLen: 1, 9690 asm: arm.AMVN, 9691 reg: regInfo{ 9692 inputs: []inputInfo{ 9693 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9694 }, 9695 outputs: []outputInfo{ 9696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9697 }, 9698 }, 9699 }, 9700 { 9701 name: "ADCshiftLL", 9702 auxType: auxInt32, 9703 argLen: 3, 9704 asm: arm.AADC, 9705 reg: regInfo{ 9706 inputs: []inputInfo{ 9707 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9708 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9709 }, 9710 outputs: []outputInfo{ 9711 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9712 }, 9713 }, 9714 }, 9715 { 9716 name: "ADCshiftRL", 9717 auxType: auxInt32, 9718 argLen: 3, 9719 asm: arm.AADC, 9720 reg: regInfo{ 9721 inputs: []inputInfo{ 9722 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9723 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9724 }, 9725 outputs: []outputInfo{ 9726 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9727 }, 9728 }, 9729 }, 9730 { 9731 name: "ADCshiftRA", 9732 auxType: auxInt32, 9733 argLen: 3, 9734 asm: arm.AADC, 9735 reg: regInfo{ 9736 inputs: []inputInfo{ 9737 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9738 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9739 }, 9740 outputs: []outputInfo{ 9741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9742 }, 9743 }, 9744 }, 9745 { 9746 name: "SBCshiftLL", 9747 auxType: auxInt32, 9748 argLen: 3, 9749 asm: arm.ASBC, 9750 reg: regInfo{ 9751 inputs: []inputInfo{ 9752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9753 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9754 }, 9755 outputs: []outputInfo{ 9756 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9757 }, 9758 }, 9759 }, 9760 { 9761 name: "SBCshiftRL", 9762 auxType: auxInt32, 9763 argLen: 3, 9764 asm: arm.ASBC, 9765 reg: regInfo{ 9766 inputs: []inputInfo{ 9767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9768 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9769 }, 9770 outputs: []outputInfo{ 9771 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9772 }, 9773 }, 9774 }, 9775 { 9776 name: "SBCshiftRA", 9777 auxType: auxInt32, 9778 argLen: 3, 9779 asm: arm.ASBC, 9780 reg: regInfo{ 9781 inputs: []inputInfo{ 9782 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9783 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9784 }, 9785 outputs: []outputInfo{ 9786 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9787 }, 9788 }, 9789 }, 9790 { 9791 name: "RSCshiftLL", 9792 auxType: auxInt32, 9793 argLen: 3, 9794 asm: arm.ARSC, 9795 reg: regInfo{ 9796 inputs: []inputInfo{ 9797 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9798 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9799 }, 9800 outputs: []outputInfo{ 9801 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9802 }, 9803 }, 9804 }, 9805 { 9806 name: "RSCshiftRL", 9807 auxType: auxInt32, 9808 argLen: 3, 9809 asm: arm.ARSC, 9810 reg: regInfo{ 9811 inputs: []inputInfo{ 9812 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9813 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9814 }, 9815 outputs: []outputInfo{ 9816 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9817 }, 9818 }, 9819 }, 9820 { 9821 name: "RSCshiftRA", 9822 auxType: auxInt32, 9823 argLen: 3, 9824 asm: arm.ARSC, 9825 reg: regInfo{ 9826 inputs: []inputInfo{ 9827 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9828 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9829 }, 9830 outputs: []outputInfo{ 9831 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9832 }, 9833 }, 9834 }, 9835 { 9836 name: "ADDSshiftLL", 9837 auxType: auxInt32, 9838 argLen: 2, 9839 asm: arm.AADD, 9840 reg: regInfo{ 9841 inputs: []inputInfo{ 9842 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9843 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9844 }, 9845 outputs: []outputInfo{ 9846 {1, 0}, 9847 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9848 }, 9849 }, 9850 }, 9851 { 9852 name: "ADDSshiftRL", 9853 auxType: auxInt32, 9854 argLen: 2, 9855 asm: arm.AADD, 9856 reg: regInfo{ 9857 inputs: []inputInfo{ 9858 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9859 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9860 }, 9861 outputs: []outputInfo{ 9862 {1, 0}, 9863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9864 }, 9865 }, 9866 }, 9867 { 9868 name: "ADDSshiftRA", 9869 auxType: auxInt32, 9870 argLen: 2, 9871 asm: arm.AADD, 9872 reg: regInfo{ 9873 inputs: []inputInfo{ 9874 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9875 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9876 }, 9877 outputs: []outputInfo{ 9878 {1, 0}, 9879 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9880 }, 9881 }, 9882 }, 9883 { 9884 name: "SUBSshiftLL", 9885 auxType: auxInt32, 9886 argLen: 2, 9887 asm: arm.ASUB, 9888 reg: regInfo{ 9889 inputs: []inputInfo{ 9890 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9891 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9892 }, 9893 outputs: []outputInfo{ 9894 {1, 0}, 9895 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9896 }, 9897 }, 9898 }, 9899 { 9900 name: "SUBSshiftRL", 9901 auxType: auxInt32, 9902 argLen: 2, 9903 asm: arm.ASUB, 9904 reg: regInfo{ 9905 inputs: []inputInfo{ 9906 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9907 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9908 }, 9909 outputs: []outputInfo{ 9910 {1, 0}, 9911 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9912 }, 9913 }, 9914 }, 9915 { 9916 name: "SUBSshiftRA", 9917 auxType: auxInt32, 9918 argLen: 2, 9919 asm: arm.ASUB, 9920 reg: regInfo{ 9921 inputs: []inputInfo{ 9922 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9923 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9924 }, 9925 outputs: []outputInfo{ 9926 {1, 0}, 9927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9928 }, 9929 }, 9930 }, 9931 { 9932 name: "RSBSshiftLL", 9933 auxType: auxInt32, 9934 argLen: 2, 9935 asm: arm.ARSB, 9936 reg: regInfo{ 9937 inputs: []inputInfo{ 9938 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9939 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9940 }, 9941 outputs: []outputInfo{ 9942 {1, 0}, 9943 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9944 }, 9945 }, 9946 }, 9947 { 9948 name: "RSBSshiftRL", 9949 auxType: auxInt32, 9950 argLen: 2, 9951 asm: arm.ARSB, 9952 reg: regInfo{ 9953 inputs: []inputInfo{ 9954 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9955 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9956 }, 9957 outputs: []outputInfo{ 9958 {1, 0}, 9959 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9960 }, 9961 }, 9962 }, 9963 { 9964 name: "RSBSshiftRA", 9965 auxType: auxInt32, 9966 argLen: 2, 9967 asm: arm.ARSB, 9968 reg: regInfo{ 9969 inputs: []inputInfo{ 9970 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9971 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 9972 }, 9973 outputs: []outputInfo{ 9974 {1, 0}, 9975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9976 }, 9977 }, 9978 }, 9979 { 9980 name: "ADDshiftLLreg", 9981 argLen: 3, 9982 asm: arm.AADD, 9983 reg: regInfo{ 9984 inputs: []inputInfo{ 9985 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9986 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9987 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9988 }, 9989 outputs: []outputInfo{ 9990 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 9991 }, 9992 }, 9993 }, 9994 { 9995 name: "ADDshiftRLreg", 9996 argLen: 3, 9997 asm: arm.AADD, 9998 reg: regInfo{ 9999 inputs: []inputInfo{ 10000 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10001 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10002 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10003 }, 10004 outputs: []outputInfo{ 10005 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10006 }, 10007 }, 10008 }, 10009 { 10010 name: "ADDshiftRAreg", 10011 argLen: 3, 10012 asm: arm.AADD, 10013 reg: regInfo{ 10014 inputs: []inputInfo{ 10015 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10016 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10017 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10018 }, 10019 outputs: []outputInfo{ 10020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10021 }, 10022 }, 10023 }, 10024 { 10025 name: "SUBshiftLLreg", 10026 argLen: 3, 10027 asm: arm.ASUB, 10028 reg: regInfo{ 10029 inputs: []inputInfo{ 10030 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10031 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10032 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10033 }, 10034 outputs: []outputInfo{ 10035 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10036 }, 10037 }, 10038 }, 10039 { 10040 name: "SUBshiftRLreg", 10041 argLen: 3, 10042 asm: arm.ASUB, 10043 reg: regInfo{ 10044 inputs: []inputInfo{ 10045 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10046 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10047 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10048 }, 10049 outputs: []outputInfo{ 10050 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10051 }, 10052 }, 10053 }, 10054 { 10055 name: "SUBshiftRAreg", 10056 argLen: 3, 10057 asm: arm.ASUB, 10058 reg: regInfo{ 10059 inputs: []inputInfo{ 10060 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10061 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10062 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10063 }, 10064 outputs: []outputInfo{ 10065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10066 }, 10067 }, 10068 }, 10069 { 10070 name: "RSBshiftLLreg", 10071 argLen: 3, 10072 asm: arm.ARSB, 10073 reg: regInfo{ 10074 inputs: []inputInfo{ 10075 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10076 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10077 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10078 }, 10079 outputs: []outputInfo{ 10080 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10081 }, 10082 }, 10083 }, 10084 { 10085 name: "RSBshiftRLreg", 10086 argLen: 3, 10087 asm: arm.ARSB, 10088 reg: regInfo{ 10089 inputs: []inputInfo{ 10090 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10091 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10092 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10093 }, 10094 outputs: []outputInfo{ 10095 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10096 }, 10097 }, 10098 }, 10099 { 10100 name: "RSBshiftRAreg", 10101 argLen: 3, 10102 asm: arm.ARSB, 10103 reg: regInfo{ 10104 inputs: []inputInfo{ 10105 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10106 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10107 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10108 }, 10109 outputs: []outputInfo{ 10110 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10111 }, 10112 }, 10113 }, 10114 { 10115 name: "ANDshiftLLreg", 10116 argLen: 3, 10117 asm: arm.AAND, 10118 reg: regInfo{ 10119 inputs: []inputInfo{ 10120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10121 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10122 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10123 }, 10124 outputs: []outputInfo{ 10125 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10126 }, 10127 }, 10128 }, 10129 { 10130 name: "ANDshiftRLreg", 10131 argLen: 3, 10132 asm: arm.AAND, 10133 reg: regInfo{ 10134 inputs: []inputInfo{ 10135 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10136 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10137 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10138 }, 10139 outputs: []outputInfo{ 10140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10141 }, 10142 }, 10143 }, 10144 { 10145 name: "ANDshiftRAreg", 10146 argLen: 3, 10147 asm: arm.AAND, 10148 reg: regInfo{ 10149 inputs: []inputInfo{ 10150 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10151 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10152 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10153 }, 10154 outputs: []outputInfo{ 10155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10156 }, 10157 }, 10158 }, 10159 { 10160 name: "ORshiftLLreg", 10161 argLen: 3, 10162 asm: arm.AORR, 10163 reg: regInfo{ 10164 inputs: []inputInfo{ 10165 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10166 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10167 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10168 }, 10169 outputs: []outputInfo{ 10170 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10171 }, 10172 }, 10173 }, 10174 { 10175 name: "ORshiftRLreg", 10176 argLen: 3, 10177 asm: arm.AORR, 10178 reg: regInfo{ 10179 inputs: []inputInfo{ 10180 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10181 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10182 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10183 }, 10184 outputs: []outputInfo{ 10185 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10186 }, 10187 }, 10188 }, 10189 { 10190 name: "ORshiftRAreg", 10191 argLen: 3, 10192 asm: arm.AORR, 10193 reg: regInfo{ 10194 inputs: []inputInfo{ 10195 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10196 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10197 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10198 }, 10199 outputs: []outputInfo{ 10200 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10201 }, 10202 }, 10203 }, 10204 { 10205 name: "XORshiftLLreg", 10206 argLen: 3, 10207 asm: arm.AEOR, 10208 reg: regInfo{ 10209 inputs: []inputInfo{ 10210 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10211 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10212 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10213 }, 10214 outputs: []outputInfo{ 10215 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10216 }, 10217 }, 10218 }, 10219 { 10220 name: "XORshiftRLreg", 10221 argLen: 3, 10222 asm: arm.AEOR, 10223 reg: regInfo{ 10224 inputs: []inputInfo{ 10225 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10226 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10227 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10228 }, 10229 outputs: []outputInfo{ 10230 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10231 }, 10232 }, 10233 }, 10234 { 10235 name: "XORshiftRAreg", 10236 argLen: 3, 10237 asm: arm.AEOR, 10238 reg: regInfo{ 10239 inputs: []inputInfo{ 10240 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10241 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10242 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10243 }, 10244 outputs: []outputInfo{ 10245 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10246 }, 10247 }, 10248 }, 10249 { 10250 name: "BICshiftLLreg", 10251 argLen: 3, 10252 asm: arm.ABIC, 10253 reg: regInfo{ 10254 inputs: []inputInfo{ 10255 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10256 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10257 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10258 }, 10259 outputs: []outputInfo{ 10260 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10261 }, 10262 }, 10263 }, 10264 { 10265 name: "BICshiftRLreg", 10266 argLen: 3, 10267 asm: arm.ABIC, 10268 reg: regInfo{ 10269 inputs: []inputInfo{ 10270 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10271 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10272 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10273 }, 10274 outputs: []outputInfo{ 10275 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10276 }, 10277 }, 10278 }, 10279 { 10280 name: "BICshiftRAreg", 10281 argLen: 3, 10282 asm: arm.ABIC, 10283 reg: regInfo{ 10284 inputs: []inputInfo{ 10285 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10286 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10287 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10288 }, 10289 outputs: []outputInfo{ 10290 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10291 }, 10292 }, 10293 }, 10294 { 10295 name: "MVNshiftLLreg", 10296 argLen: 2, 10297 asm: arm.AMVN, 10298 reg: regInfo{ 10299 inputs: []inputInfo{ 10300 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10301 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10302 }, 10303 outputs: []outputInfo{ 10304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10305 }, 10306 }, 10307 }, 10308 { 10309 name: "MVNshiftRLreg", 10310 argLen: 2, 10311 asm: arm.AMVN, 10312 reg: regInfo{ 10313 inputs: []inputInfo{ 10314 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10315 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10316 }, 10317 outputs: []outputInfo{ 10318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10319 }, 10320 }, 10321 }, 10322 { 10323 name: "MVNshiftRAreg", 10324 argLen: 2, 10325 asm: arm.AMVN, 10326 reg: regInfo{ 10327 inputs: []inputInfo{ 10328 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10329 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10330 }, 10331 outputs: []outputInfo{ 10332 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10333 }, 10334 }, 10335 }, 10336 { 10337 name: "ADCshiftLLreg", 10338 argLen: 4, 10339 asm: arm.AADC, 10340 reg: regInfo{ 10341 inputs: []inputInfo{ 10342 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10343 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10344 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10345 }, 10346 outputs: []outputInfo{ 10347 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10348 }, 10349 }, 10350 }, 10351 { 10352 name: "ADCshiftRLreg", 10353 argLen: 4, 10354 asm: arm.AADC, 10355 reg: regInfo{ 10356 inputs: []inputInfo{ 10357 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10358 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10359 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10360 }, 10361 outputs: []outputInfo{ 10362 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10363 }, 10364 }, 10365 }, 10366 { 10367 name: "ADCshiftRAreg", 10368 argLen: 4, 10369 asm: arm.AADC, 10370 reg: regInfo{ 10371 inputs: []inputInfo{ 10372 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10373 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10374 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10375 }, 10376 outputs: []outputInfo{ 10377 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10378 }, 10379 }, 10380 }, 10381 { 10382 name: "SBCshiftLLreg", 10383 argLen: 4, 10384 asm: arm.ASBC, 10385 reg: regInfo{ 10386 inputs: []inputInfo{ 10387 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10388 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10389 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10390 }, 10391 outputs: []outputInfo{ 10392 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10393 }, 10394 }, 10395 }, 10396 { 10397 name: "SBCshiftRLreg", 10398 argLen: 4, 10399 asm: arm.ASBC, 10400 reg: regInfo{ 10401 inputs: []inputInfo{ 10402 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10403 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10404 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10405 }, 10406 outputs: []outputInfo{ 10407 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10408 }, 10409 }, 10410 }, 10411 { 10412 name: "SBCshiftRAreg", 10413 argLen: 4, 10414 asm: arm.ASBC, 10415 reg: regInfo{ 10416 inputs: []inputInfo{ 10417 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10418 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10419 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10420 }, 10421 outputs: []outputInfo{ 10422 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10423 }, 10424 }, 10425 }, 10426 { 10427 name: "RSCshiftLLreg", 10428 argLen: 4, 10429 asm: arm.ARSC, 10430 reg: regInfo{ 10431 inputs: []inputInfo{ 10432 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10433 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10434 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10435 }, 10436 outputs: []outputInfo{ 10437 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10438 }, 10439 }, 10440 }, 10441 { 10442 name: "RSCshiftRLreg", 10443 argLen: 4, 10444 asm: arm.ARSC, 10445 reg: regInfo{ 10446 inputs: []inputInfo{ 10447 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10448 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10449 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10450 }, 10451 outputs: []outputInfo{ 10452 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10453 }, 10454 }, 10455 }, 10456 { 10457 name: "RSCshiftRAreg", 10458 argLen: 4, 10459 asm: arm.ARSC, 10460 reg: regInfo{ 10461 inputs: []inputInfo{ 10462 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10463 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10464 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10465 }, 10466 outputs: []outputInfo{ 10467 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10468 }, 10469 }, 10470 }, 10471 { 10472 name: "ADDSshiftLLreg", 10473 argLen: 3, 10474 asm: arm.AADD, 10475 reg: regInfo{ 10476 inputs: []inputInfo{ 10477 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10478 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10479 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10480 }, 10481 outputs: []outputInfo{ 10482 {1, 0}, 10483 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10484 }, 10485 }, 10486 }, 10487 { 10488 name: "ADDSshiftRLreg", 10489 argLen: 3, 10490 asm: arm.AADD, 10491 reg: regInfo{ 10492 inputs: []inputInfo{ 10493 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10494 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10495 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10496 }, 10497 outputs: []outputInfo{ 10498 {1, 0}, 10499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10500 }, 10501 }, 10502 }, 10503 { 10504 name: "ADDSshiftRAreg", 10505 argLen: 3, 10506 asm: arm.AADD, 10507 reg: regInfo{ 10508 inputs: []inputInfo{ 10509 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10510 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10511 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10512 }, 10513 outputs: []outputInfo{ 10514 {1, 0}, 10515 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10516 }, 10517 }, 10518 }, 10519 { 10520 name: "SUBSshiftLLreg", 10521 argLen: 3, 10522 asm: arm.ASUB, 10523 reg: regInfo{ 10524 inputs: []inputInfo{ 10525 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10526 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10527 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10528 }, 10529 outputs: []outputInfo{ 10530 {1, 0}, 10531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10532 }, 10533 }, 10534 }, 10535 { 10536 name: "SUBSshiftRLreg", 10537 argLen: 3, 10538 asm: arm.ASUB, 10539 reg: regInfo{ 10540 inputs: []inputInfo{ 10541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10542 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10543 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10544 }, 10545 outputs: []outputInfo{ 10546 {1, 0}, 10547 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10548 }, 10549 }, 10550 }, 10551 { 10552 name: "SUBSshiftRAreg", 10553 argLen: 3, 10554 asm: arm.ASUB, 10555 reg: regInfo{ 10556 inputs: []inputInfo{ 10557 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10558 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10559 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10560 }, 10561 outputs: []outputInfo{ 10562 {1, 0}, 10563 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10564 }, 10565 }, 10566 }, 10567 { 10568 name: "RSBSshiftLLreg", 10569 argLen: 3, 10570 asm: arm.ARSB, 10571 reg: regInfo{ 10572 inputs: []inputInfo{ 10573 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10574 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10575 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10576 }, 10577 outputs: []outputInfo{ 10578 {1, 0}, 10579 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10580 }, 10581 }, 10582 }, 10583 { 10584 name: "RSBSshiftRLreg", 10585 argLen: 3, 10586 asm: arm.ARSB, 10587 reg: regInfo{ 10588 inputs: []inputInfo{ 10589 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10590 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10591 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10592 }, 10593 outputs: []outputInfo{ 10594 {1, 0}, 10595 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10596 }, 10597 }, 10598 }, 10599 { 10600 name: "RSBSshiftRAreg", 10601 argLen: 3, 10602 asm: arm.ARSB, 10603 reg: regInfo{ 10604 inputs: []inputInfo{ 10605 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10606 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10607 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10608 }, 10609 outputs: []outputInfo{ 10610 {1, 0}, 10611 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10612 }, 10613 }, 10614 }, 10615 { 10616 name: "CMP", 10617 argLen: 2, 10618 asm: arm.ACMP, 10619 reg: regInfo{ 10620 inputs: []inputInfo{ 10621 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10622 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10623 }, 10624 }, 10625 }, 10626 { 10627 name: "CMPconst", 10628 auxType: auxInt32, 10629 argLen: 1, 10630 asm: arm.ACMP, 10631 reg: regInfo{ 10632 inputs: []inputInfo{ 10633 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10634 }, 10635 }, 10636 }, 10637 { 10638 name: "CMN", 10639 argLen: 2, 10640 commutative: true, 10641 asm: arm.ACMN, 10642 reg: regInfo{ 10643 inputs: []inputInfo{ 10644 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10645 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10646 }, 10647 }, 10648 }, 10649 { 10650 name: "CMNconst", 10651 auxType: auxInt32, 10652 argLen: 1, 10653 asm: arm.ACMN, 10654 reg: regInfo{ 10655 inputs: []inputInfo{ 10656 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10657 }, 10658 }, 10659 }, 10660 { 10661 name: "TST", 10662 argLen: 2, 10663 commutative: true, 10664 asm: arm.ATST, 10665 reg: regInfo{ 10666 inputs: []inputInfo{ 10667 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10668 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10669 }, 10670 }, 10671 }, 10672 { 10673 name: "TSTconst", 10674 auxType: auxInt32, 10675 argLen: 1, 10676 asm: arm.ATST, 10677 reg: regInfo{ 10678 inputs: []inputInfo{ 10679 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10680 }, 10681 }, 10682 }, 10683 { 10684 name: "TEQ", 10685 argLen: 2, 10686 commutative: true, 10687 asm: arm.ATEQ, 10688 reg: regInfo{ 10689 inputs: []inputInfo{ 10690 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10691 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10692 }, 10693 }, 10694 }, 10695 { 10696 name: "TEQconst", 10697 auxType: auxInt32, 10698 argLen: 1, 10699 asm: arm.ATEQ, 10700 reg: regInfo{ 10701 inputs: []inputInfo{ 10702 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10703 }, 10704 }, 10705 }, 10706 { 10707 name: "CMPF", 10708 argLen: 2, 10709 asm: arm.ACMPF, 10710 reg: regInfo{ 10711 inputs: []inputInfo{ 10712 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10713 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10714 }, 10715 }, 10716 }, 10717 { 10718 name: "CMPD", 10719 argLen: 2, 10720 asm: arm.ACMPD, 10721 reg: regInfo{ 10722 inputs: []inputInfo{ 10723 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10724 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 10725 }, 10726 }, 10727 }, 10728 { 10729 name: "CMPshiftLL", 10730 auxType: auxInt32, 10731 argLen: 2, 10732 asm: arm.ACMP, 10733 reg: regInfo{ 10734 inputs: []inputInfo{ 10735 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10736 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10737 }, 10738 }, 10739 }, 10740 { 10741 name: "CMPshiftRL", 10742 auxType: auxInt32, 10743 argLen: 2, 10744 asm: arm.ACMP, 10745 reg: regInfo{ 10746 inputs: []inputInfo{ 10747 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10748 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10749 }, 10750 }, 10751 }, 10752 { 10753 name: "CMPshiftRA", 10754 auxType: auxInt32, 10755 argLen: 2, 10756 asm: arm.ACMP, 10757 reg: regInfo{ 10758 inputs: []inputInfo{ 10759 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10760 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10761 }, 10762 }, 10763 }, 10764 { 10765 name: "CMNshiftLL", 10766 auxType: auxInt32, 10767 argLen: 2, 10768 asm: arm.ACMN, 10769 reg: regInfo{ 10770 inputs: []inputInfo{ 10771 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10772 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10773 }, 10774 }, 10775 }, 10776 { 10777 name: "CMNshiftRL", 10778 auxType: auxInt32, 10779 argLen: 2, 10780 asm: arm.ACMN, 10781 reg: regInfo{ 10782 inputs: []inputInfo{ 10783 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10784 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10785 }, 10786 }, 10787 }, 10788 { 10789 name: "CMNshiftRA", 10790 auxType: auxInt32, 10791 argLen: 2, 10792 asm: arm.ACMN, 10793 reg: regInfo{ 10794 inputs: []inputInfo{ 10795 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10796 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10797 }, 10798 }, 10799 }, 10800 { 10801 name: "TSTshiftLL", 10802 auxType: auxInt32, 10803 argLen: 2, 10804 asm: arm.ATST, 10805 reg: regInfo{ 10806 inputs: []inputInfo{ 10807 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10808 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10809 }, 10810 }, 10811 }, 10812 { 10813 name: "TSTshiftRL", 10814 auxType: auxInt32, 10815 argLen: 2, 10816 asm: arm.ATST, 10817 reg: regInfo{ 10818 inputs: []inputInfo{ 10819 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10820 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10821 }, 10822 }, 10823 }, 10824 { 10825 name: "TSTshiftRA", 10826 auxType: auxInt32, 10827 argLen: 2, 10828 asm: arm.ATST, 10829 reg: regInfo{ 10830 inputs: []inputInfo{ 10831 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10832 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10833 }, 10834 }, 10835 }, 10836 { 10837 name: "TEQshiftLL", 10838 auxType: auxInt32, 10839 argLen: 2, 10840 asm: arm.ATEQ, 10841 reg: regInfo{ 10842 inputs: []inputInfo{ 10843 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10844 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10845 }, 10846 }, 10847 }, 10848 { 10849 name: "TEQshiftRL", 10850 auxType: auxInt32, 10851 argLen: 2, 10852 asm: arm.ATEQ, 10853 reg: regInfo{ 10854 inputs: []inputInfo{ 10855 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10856 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10857 }, 10858 }, 10859 }, 10860 { 10861 name: "TEQshiftRA", 10862 auxType: auxInt32, 10863 argLen: 2, 10864 asm: arm.ATEQ, 10865 reg: regInfo{ 10866 inputs: []inputInfo{ 10867 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10868 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 10869 }, 10870 }, 10871 }, 10872 { 10873 name: "CMPshiftLLreg", 10874 argLen: 3, 10875 asm: arm.ACMP, 10876 reg: regInfo{ 10877 inputs: []inputInfo{ 10878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10879 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10880 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10881 }, 10882 }, 10883 }, 10884 { 10885 name: "CMPshiftRLreg", 10886 argLen: 3, 10887 asm: arm.ACMP, 10888 reg: regInfo{ 10889 inputs: []inputInfo{ 10890 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10891 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10892 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10893 }, 10894 }, 10895 }, 10896 { 10897 name: "CMPshiftRAreg", 10898 argLen: 3, 10899 asm: arm.ACMP, 10900 reg: regInfo{ 10901 inputs: []inputInfo{ 10902 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10903 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10904 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10905 }, 10906 }, 10907 }, 10908 { 10909 name: "CMNshiftLLreg", 10910 argLen: 3, 10911 asm: arm.ACMN, 10912 reg: regInfo{ 10913 inputs: []inputInfo{ 10914 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10915 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10916 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10917 }, 10918 }, 10919 }, 10920 { 10921 name: "CMNshiftRLreg", 10922 argLen: 3, 10923 asm: arm.ACMN, 10924 reg: regInfo{ 10925 inputs: []inputInfo{ 10926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10927 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10928 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10929 }, 10930 }, 10931 }, 10932 { 10933 name: "CMNshiftRAreg", 10934 argLen: 3, 10935 asm: arm.ACMN, 10936 reg: regInfo{ 10937 inputs: []inputInfo{ 10938 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10939 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10940 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10941 }, 10942 }, 10943 }, 10944 { 10945 name: "TSTshiftLLreg", 10946 argLen: 3, 10947 asm: arm.ATST, 10948 reg: regInfo{ 10949 inputs: []inputInfo{ 10950 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10951 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10952 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10953 }, 10954 }, 10955 }, 10956 { 10957 name: "TSTshiftRLreg", 10958 argLen: 3, 10959 asm: arm.ATST, 10960 reg: regInfo{ 10961 inputs: []inputInfo{ 10962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10963 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10964 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10965 }, 10966 }, 10967 }, 10968 { 10969 name: "TSTshiftRAreg", 10970 argLen: 3, 10971 asm: arm.ATST, 10972 reg: regInfo{ 10973 inputs: []inputInfo{ 10974 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10975 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10976 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10977 }, 10978 }, 10979 }, 10980 { 10981 name: "TEQshiftLLreg", 10982 argLen: 3, 10983 asm: arm.ATEQ, 10984 reg: regInfo{ 10985 inputs: []inputInfo{ 10986 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10987 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10988 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10989 }, 10990 }, 10991 }, 10992 { 10993 name: "TEQshiftRLreg", 10994 argLen: 3, 10995 asm: arm.ATEQ, 10996 reg: regInfo{ 10997 inputs: []inputInfo{ 10998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 10999 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11000 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11001 }, 11002 }, 11003 }, 11004 { 11005 name: "TEQshiftRAreg", 11006 argLen: 3, 11007 asm: arm.ATEQ, 11008 reg: regInfo{ 11009 inputs: []inputInfo{ 11010 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11011 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11012 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11013 }, 11014 }, 11015 }, 11016 { 11017 name: "CMPF0", 11018 argLen: 1, 11019 asm: arm.ACMPF, 11020 reg: regInfo{ 11021 inputs: []inputInfo{ 11022 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11023 }, 11024 }, 11025 }, 11026 { 11027 name: "CMPD0", 11028 argLen: 1, 11029 asm: arm.ACMPD, 11030 reg: regInfo{ 11031 inputs: []inputInfo{ 11032 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11033 }, 11034 }, 11035 }, 11036 { 11037 name: "MOVWconst", 11038 auxType: auxInt32, 11039 argLen: 0, 11040 rematerializeable: true, 11041 asm: arm.AMOVW, 11042 reg: regInfo{ 11043 outputs: []outputInfo{ 11044 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11045 }, 11046 }, 11047 }, 11048 { 11049 name: "MOVFconst", 11050 auxType: auxFloat64, 11051 argLen: 0, 11052 rematerializeable: true, 11053 asm: arm.AMOVF, 11054 reg: regInfo{ 11055 outputs: []outputInfo{ 11056 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11057 }, 11058 }, 11059 }, 11060 { 11061 name: "MOVDconst", 11062 auxType: auxFloat64, 11063 argLen: 0, 11064 rematerializeable: true, 11065 asm: arm.AMOVD, 11066 reg: regInfo{ 11067 outputs: []outputInfo{ 11068 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11069 }, 11070 }, 11071 }, 11072 { 11073 name: "MOVWaddr", 11074 auxType: auxSymOff, 11075 argLen: 1, 11076 rematerializeable: true, 11077 symEffect: SymAddr, 11078 asm: arm.AMOVW, 11079 reg: regInfo{ 11080 inputs: []inputInfo{ 11081 {0, 4294975488}, // SP SB 11082 }, 11083 outputs: []outputInfo{ 11084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11085 }, 11086 }, 11087 }, 11088 { 11089 name: "MOVBload", 11090 auxType: auxSymOff, 11091 argLen: 2, 11092 faultOnNilArg0: true, 11093 symEffect: SymRead, 11094 asm: arm.AMOVB, 11095 reg: regInfo{ 11096 inputs: []inputInfo{ 11097 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11098 }, 11099 outputs: []outputInfo{ 11100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11101 }, 11102 }, 11103 }, 11104 { 11105 name: "MOVBUload", 11106 auxType: auxSymOff, 11107 argLen: 2, 11108 faultOnNilArg0: true, 11109 symEffect: SymRead, 11110 asm: arm.AMOVBU, 11111 reg: regInfo{ 11112 inputs: []inputInfo{ 11113 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11114 }, 11115 outputs: []outputInfo{ 11116 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11117 }, 11118 }, 11119 }, 11120 { 11121 name: "MOVHload", 11122 auxType: auxSymOff, 11123 argLen: 2, 11124 faultOnNilArg0: true, 11125 symEffect: SymRead, 11126 asm: arm.AMOVH, 11127 reg: regInfo{ 11128 inputs: []inputInfo{ 11129 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11130 }, 11131 outputs: []outputInfo{ 11132 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11133 }, 11134 }, 11135 }, 11136 { 11137 name: "MOVHUload", 11138 auxType: auxSymOff, 11139 argLen: 2, 11140 faultOnNilArg0: true, 11141 symEffect: SymRead, 11142 asm: arm.AMOVHU, 11143 reg: regInfo{ 11144 inputs: []inputInfo{ 11145 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11146 }, 11147 outputs: []outputInfo{ 11148 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11149 }, 11150 }, 11151 }, 11152 { 11153 name: "MOVWload", 11154 auxType: auxSymOff, 11155 argLen: 2, 11156 faultOnNilArg0: true, 11157 symEffect: SymRead, 11158 asm: arm.AMOVW, 11159 reg: regInfo{ 11160 inputs: []inputInfo{ 11161 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11162 }, 11163 outputs: []outputInfo{ 11164 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11165 }, 11166 }, 11167 }, 11168 { 11169 name: "MOVFload", 11170 auxType: auxSymOff, 11171 argLen: 2, 11172 faultOnNilArg0: true, 11173 symEffect: SymRead, 11174 asm: arm.AMOVF, 11175 reg: regInfo{ 11176 inputs: []inputInfo{ 11177 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11178 }, 11179 outputs: []outputInfo{ 11180 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11181 }, 11182 }, 11183 }, 11184 { 11185 name: "MOVDload", 11186 auxType: auxSymOff, 11187 argLen: 2, 11188 faultOnNilArg0: true, 11189 symEffect: SymRead, 11190 asm: arm.AMOVD, 11191 reg: regInfo{ 11192 inputs: []inputInfo{ 11193 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11194 }, 11195 outputs: []outputInfo{ 11196 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11197 }, 11198 }, 11199 }, 11200 { 11201 name: "MOVBstore", 11202 auxType: auxSymOff, 11203 argLen: 3, 11204 faultOnNilArg0: true, 11205 symEffect: SymWrite, 11206 asm: arm.AMOVB, 11207 reg: regInfo{ 11208 inputs: []inputInfo{ 11209 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11210 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11211 }, 11212 }, 11213 }, 11214 { 11215 name: "MOVHstore", 11216 auxType: auxSymOff, 11217 argLen: 3, 11218 faultOnNilArg0: true, 11219 symEffect: SymWrite, 11220 asm: arm.AMOVH, 11221 reg: regInfo{ 11222 inputs: []inputInfo{ 11223 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11224 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11225 }, 11226 }, 11227 }, 11228 { 11229 name: "MOVWstore", 11230 auxType: auxSymOff, 11231 argLen: 3, 11232 faultOnNilArg0: true, 11233 symEffect: SymWrite, 11234 asm: arm.AMOVW, 11235 reg: regInfo{ 11236 inputs: []inputInfo{ 11237 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11238 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11239 }, 11240 }, 11241 }, 11242 { 11243 name: "MOVFstore", 11244 auxType: auxSymOff, 11245 argLen: 3, 11246 faultOnNilArg0: true, 11247 symEffect: SymWrite, 11248 asm: arm.AMOVF, 11249 reg: regInfo{ 11250 inputs: []inputInfo{ 11251 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11252 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11253 }, 11254 }, 11255 }, 11256 { 11257 name: "MOVDstore", 11258 auxType: auxSymOff, 11259 argLen: 3, 11260 faultOnNilArg0: true, 11261 symEffect: SymWrite, 11262 asm: arm.AMOVD, 11263 reg: regInfo{ 11264 inputs: []inputInfo{ 11265 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11266 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11267 }, 11268 }, 11269 }, 11270 { 11271 name: "MOVWloadidx", 11272 argLen: 3, 11273 asm: arm.AMOVW, 11274 reg: regInfo{ 11275 inputs: []inputInfo{ 11276 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11277 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11278 }, 11279 outputs: []outputInfo{ 11280 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11281 }, 11282 }, 11283 }, 11284 { 11285 name: "MOVWloadshiftLL", 11286 auxType: auxInt32, 11287 argLen: 3, 11288 asm: arm.AMOVW, 11289 reg: regInfo{ 11290 inputs: []inputInfo{ 11291 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11292 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11293 }, 11294 outputs: []outputInfo{ 11295 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11296 }, 11297 }, 11298 }, 11299 { 11300 name: "MOVWloadshiftRL", 11301 auxType: auxInt32, 11302 argLen: 3, 11303 asm: arm.AMOVW, 11304 reg: regInfo{ 11305 inputs: []inputInfo{ 11306 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11307 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11308 }, 11309 outputs: []outputInfo{ 11310 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11311 }, 11312 }, 11313 }, 11314 { 11315 name: "MOVWloadshiftRA", 11316 auxType: auxInt32, 11317 argLen: 3, 11318 asm: arm.AMOVW, 11319 reg: regInfo{ 11320 inputs: []inputInfo{ 11321 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11322 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11323 }, 11324 outputs: []outputInfo{ 11325 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11326 }, 11327 }, 11328 }, 11329 { 11330 name: "MOVBUloadidx", 11331 argLen: 3, 11332 asm: arm.AMOVBU, 11333 reg: regInfo{ 11334 inputs: []inputInfo{ 11335 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11336 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11337 }, 11338 outputs: []outputInfo{ 11339 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11340 }, 11341 }, 11342 }, 11343 { 11344 name: "MOVBloadidx", 11345 argLen: 3, 11346 asm: arm.AMOVB, 11347 reg: regInfo{ 11348 inputs: []inputInfo{ 11349 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11350 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11351 }, 11352 outputs: []outputInfo{ 11353 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11354 }, 11355 }, 11356 }, 11357 { 11358 name: "MOVHUloadidx", 11359 argLen: 3, 11360 asm: arm.AMOVHU, 11361 reg: regInfo{ 11362 inputs: []inputInfo{ 11363 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11364 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11365 }, 11366 outputs: []outputInfo{ 11367 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11368 }, 11369 }, 11370 }, 11371 { 11372 name: "MOVHloadidx", 11373 argLen: 3, 11374 asm: arm.AMOVH, 11375 reg: regInfo{ 11376 inputs: []inputInfo{ 11377 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11378 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11379 }, 11380 outputs: []outputInfo{ 11381 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11382 }, 11383 }, 11384 }, 11385 { 11386 name: "MOVWstoreidx", 11387 argLen: 4, 11388 asm: arm.AMOVW, 11389 reg: regInfo{ 11390 inputs: []inputInfo{ 11391 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11392 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11393 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11394 }, 11395 }, 11396 }, 11397 { 11398 name: "MOVWstoreshiftLL", 11399 auxType: auxInt32, 11400 argLen: 4, 11401 asm: arm.AMOVW, 11402 reg: regInfo{ 11403 inputs: []inputInfo{ 11404 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11405 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11406 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11407 }, 11408 }, 11409 }, 11410 { 11411 name: "MOVWstoreshiftRL", 11412 auxType: auxInt32, 11413 argLen: 4, 11414 asm: arm.AMOVW, 11415 reg: regInfo{ 11416 inputs: []inputInfo{ 11417 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11418 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11419 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11420 }, 11421 }, 11422 }, 11423 { 11424 name: "MOVWstoreshiftRA", 11425 auxType: auxInt32, 11426 argLen: 4, 11427 asm: arm.AMOVW, 11428 reg: regInfo{ 11429 inputs: []inputInfo{ 11430 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11431 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11432 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11433 }, 11434 }, 11435 }, 11436 { 11437 name: "MOVBstoreidx", 11438 argLen: 4, 11439 asm: arm.AMOVB, 11440 reg: regInfo{ 11441 inputs: []inputInfo{ 11442 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11443 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11444 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11445 }, 11446 }, 11447 }, 11448 { 11449 name: "MOVHstoreidx", 11450 argLen: 4, 11451 asm: arm.AMOVH, 11452 reg: regInfo{ 11453 inputs: []inputInfo{ 11454 {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11455 {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11456 {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB 11457 }, 11458 }, 11459 }, 11460 { 11461 name: "MOVBreg", 11462 argLen: 1, 11463 asm: arm.AMOVBS, 11464 reg: regInfo{ 11465 inputs: []inputInfo{ 11466 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11467 }, 11468 outputs: []outputInfo{ 11469 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11470 }, 11471 }, 11472 }, 11473 { 11474 name: "MOVBUreg", 11475 argLen: 1, 11476 asm: arm.AMOVBU, 11477 reg: regInfo{ 11478 inputs: []inputInfo{ 11479 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11480 }, 11481 outputs: []outputInfo{ 11482 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11483 }, 11484 }, 11485 }, 11486 { 11487 name: "MOVHreg", 11488 argLen: 1, 11489 asm: arm.AMOVHS, 11490 reg: regInfo{ 11491 inputs: []inputInfo{ 11492 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11493 }, 11494 outputs: []outputInfo{ 11495 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11496 }, 11497 }, 11498 }, 11499 { 11500 name: "MOVHUreg", 11501 argLen: 1, 11502 asm: arm.AMOVHU, 11503 reg: regInfo{ 11504 inputs: []inputInfo{ 11505 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11506 }, 11507 outputs: []outputInfo{ 11508 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11509 }, 11510 }, 11511 }, 11512 { 11513 name: "MOVWreg", 11514 argLen: 1, 11515 asm: arm.AMOVW, 11516 reg: regInfo{ 11517 inputs: []inputInfo{ 11518 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11519 }, 11520 outputs: []outputInfo{ 11521 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11522 }, 11523 }, 11524 }, 11525 { 11526 name: "MOVWnop", 11527 argLen: 1, 11528 resultInArg0: true, 11529 reg: regInfo{ 11530 inputs: []inputInfo{ 11531 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11532 }, 11533 outputs: []outputInfo{ 11534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11535 }, 11536 }, 11537 }, 11538 { 11539 name: "MOVWF", 11540 argLen: 1, 11541 asm: arm.AMOVWF, 11542 reg: regInfo{ 11543 inputs: []inputInfo{ 11544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11545 }, 11546 clobbers: 2147483648, // F15 11547 outputs: []outputInfo{ 11548 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11549 }, 11550 }, 11551 }, 11552 { 11553 name: "MOVWD", 11554 argLen: 1, 11555 asm: arm.AMOVWD, 11556 reg: regInfo{ 11557 inputs: []inputInfo{ 11558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11559 }, 11560 clobbers: 2147483648, // F15 11561 outputs: []outputInfo{ 11562 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11563 }, 11564 }, 11565 }, 11566 { 11567 name: "MOVWUF", 11568 argLen: 1, 11569 asm: arm.AMOVWF, 11570 reg: regInfo{ 11571 inputs: []inputInfo{ 11572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11573 }, 11574 clobbers: 2147483648, // F15 11575 outputs: []outputInfo{ 11576 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11577 }, 11578 }, 11579 }, 11580 { 11581 name: "MOVWUD", 11582 argLen: 1, 11583 asm: arm.AMOVWD, 11584 reg: regInfo{ 11585 inputs: []inputInfo{ 11586 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11587 }, 11588 clobbers: 2147483648, // F15 11589 outputs: []outputInfo{ 11590 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11591 }, 11592 }, 11593 }, 11594 { 11595 name: "MOVFW", 11596 argLen: 1, 11597 asm: arm.AMOVFW, 11598 reg: regInfo{ 11599 inputs: []inputInfo{ 11600 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11601 }, 11602 clobbers: 2147483648, // F15 11603 outputs: []outputInfo{ 11604 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11605 }, 11606 }, 11607 }, 11608 { 11609 name: "MOVDW", 11610 argLen: 1, 11611 asm: arm.AMOVDW, 11612 reg: regInfo{ 11613 inputs: []inputInfo{ 11614 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11615 }, 11616 clobbers: 2147483648, // F15 11617 outputs: []outputInfo{ 11618 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11619 }, 11620 }, 11621 }, 11622 { 11623 name: "MOVFWU", 11624 argLen: 1, 11625 asm: arm.AMOVFW, 11626 reg: regInfo{ 11627 inputs: []inputInfo{ 11628 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11629 }, 11630 clobbers: 2147483648, // F15 11631 outputs: []outputInfo{ 11632 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11633 }, 11634 }, 11635 }, 11636 { 11637 name: "MOVDWU", 11638 argLen: 1, 11639 asm: arm.AMOVDW, 11640 reg: regInfo{ 11641 inputs: []inputInfo{ 11642 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11643 }, 11644 clobbers: 2147483648, // F15 11645 outputs: []outputInfo{ 11646 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11647 }, 11648 }, 11649 }, 11650 { 11651 name: "MOVFD", 11652 argLen: 1, 11653 asm: arm.AMOVFD, 11654 reg: regInfo{ 11655 inputs: []inputInfo{ 11656 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11657 }, 11658 outputs: []outputInfo{ 11659 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11660 }, 11661 }, 11662 }, 11663 { 11664 name: "MOVDF", 11665 argLen: 1, 11666 asm: arm.AMOVDF, 11667 reg: regInfo{ 11668 inputs: []inputInfo{ 11669 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11670 }, 11671 outputs: []outputInfo{ 11672 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11673 }, 11674 }, 11675 }, 11676 { 11677 name: "CMOVWHSconst", 11678 auxType: auxInt32, 11679 argLen: 2, 11680 resultInArg0: true, 11681 asm: arm.AMOVW, 11682 reg: regInfo{ 11683 inputs: []inputInfo{ 11684 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11685 }, 11686 outputs: []outputInfo{ 11687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11688 }, 11689 }, 11690 }, 11691 { 11692 name: "CMOVWLSconst", 11693 auxType: auxInt32, 11694 argLen: 2, 11695 resultInArg0: true, 11696 asm: arm.AMOVW, 11697 reg: regInfo{ 11698 inputs: []inputInfo{ 11699 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11700 }, 11701 outputs: []outputInfo{ 11702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11703 }, 11704 }, 11705 }, 11706 { 11707 name: "SRAcond", 11708 argLen: 3, 11709 asm: arm.ASRA, 11710 reg: regInfo{ 11711 inputs: []inputInfo{ 11712 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11713 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "CALLstatic", 11722 auxType: auxSymOff, 11723 argLen: 1, 11724 clobberFlags: true, 11725 call: true, 11726 symEffect: SymNone, 11727 reg: regInfo{ 11728 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11729 }, 11730 }, 11731 { 11732 name: "CALLclosure", 11733 auxType: auxInt64, 11734 argLen: 3, 11735 clobberFlags: true, 11736 call: true, 11737 reg: regInfo{ 11738 inputs: []inputInfo{ 11739 {1, 128}, // R7 11740 {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 11741 }, 11742 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11743 }, 11744 }, 11745 { 11746 name: "CALLinter", 11747 auxType: auxInt64, 11748 argLen: 2, 11749 clobberFlags: true, 11750 call: true, 11751 reg: regInfo{ 11752 inputs: []inputInfo{ 11753 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11754 }, 11755 clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 11756 }, 11757 }, 11758 { 11759 name: "LoweredNilCheck", 11760 argLen: 2, 11761 nilCheck: true, 11762 faultOnNilArg0: true, 11763 reg: regInfo{ 11764 inputs: []inputInfo{ 11765 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11766 }, 11767 }, 11768 }, 11769 { 11770 name: "Equal", 11771 argLen: 1, 11772 reg: regInfo{ 11773 outputs: []outputInfo{ 11774 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11775 }, 11776 }, 11777 }, 11778 { 11779 name: "NotEqual", 11780 argLen: 1, 11781 reg: regInfo{ 11782 outputs: []outputInfo{ 11783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11784 }, 11785 }, 11786 }, 11787 { 11788 name: "LessThan", 11789 argLen: 1, 11790 reg: regInfo{ 11791 outputs: []outputInfo{ 11792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11793 }, 11794 }, 11795 }, 11796 { 11797 name: "LessEqual", 11798 argLen: 1, 11799 reg: regInfo{ 11800 outputs: []outputInfo{ 11801 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11802 }, 11803 }, 11804 }, 11805 { 11806 name: "GreaterThan", 11807 argLen: 1, 11808 reg: regInfo{ 11809 outputs: []outputInfo{ 11810 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11811 }, 11812 }, 11813 }, 11814 { 11815 name: "GreaterEqual", 11816 argLen: 1, 11817 reg: regInfo{ 11818 outputs: []outputInfo{ 11819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11820 }, 11821 }, 11822 }, 11823 { 11824 name: "LessThanU", 11825 argLen: 1, 11826 reg: regInfo{ 11827 outputs: []outputInfo{ 11828 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11829 }, 11830 }, 11831 }, 11832 { 11833 name: "LessEqualU", 11834 argLen: 1, 11835 reg: regInfo{ 11836 outputs: []outputInfo{ 11837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11838 }, 11839 }, 11840 }, 11841 { 11842 name: "GreaterThanU", 11843 argLen: 1, 11844 reg: regInfo{ 11845 outputs: []outputInfo{ 11846 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11847 }, 11848 }, 11849 }, 11850 { 11851 name: "GreaterEqualU", 11852 argLen: 1, 11853 reg: regInfo{ 11854 outputs: []outputInfo{ 11855 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11856 }, 11857 }, 11858 }, 11859 { 11860 name: "DUFFZERO", 11861 auxType: auxInt64, 11862 argLen: 3, 11863 faultOnNilArg0: true, 11864 reg: regInfo{ 11865 inputs: []inputInfo{ 11866 {0, 2}, // R1 11867 {1, 1}, // R0 11868 }, 11869 clobbers: 16386, // R1 R14 11870 }, 11871 }, 11872 { 11873 name: "DUFFCOPY", 11874 auxType: auxInt64, 11875 argLen: 3, 11876 faultOnNilArg0: true, 11877 faultOnNilArg1: true, 11878 reg: regInfo{ 11879 inputs: []inputInfo{ 11880 {0, 4}, // R2 11881 {1, 2}, // R1 11882 }, 11883 clobbers: 16391, // R0 R1 R2 R14 11884 }, 11885 }, 11886 { 11887 name: "LoweredZero", 11888 auxType: auxInt64, 11889 argLen: 4, 11890 clobberFlags: true, 11891 faultOnNilArg0: true, 11892 reg: regInfo{ 11893 inputs: []inputInfo{ 11894 {0, 2}, // R1 11895 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11896 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11897 }, 11898 clobbers: 2, // R1 11899 }, 11900 }, 11901 { 11902 name: "LoweredMove", 11903 auxType: auxInt64, 11904 argLen: 4, 11905 clobberFlags: true, 11906 faultOnNilArg0: true, 11907 faultOnNilArg1: true, 11908 reg: regInfo{ 11909 inputs: []inputInfo{ 11910 {0, 4}, // R2 11911 {1, 2}, // R1 11912 {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11913 }, 11914 clobbers: 6, // R1 R2 11915 }, 11916 }, 11917 { 11918 name: "LoweredGetClosurePtr", 11919 argLen: 0, 11920 reg: regInfo{ 11921 outputs: []outputInfo{ 11922 {0, 128}, // R7 11923 }, 11924 }, 11925 }, 11926 { 11927 name: "LoweredGetCallerSP", 11928 argLen: 0, 11929 rematerializeable: true, 11930 reg: regInfo{ 11931 outputs: []outputInfo{ 11932 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11933 }, 11934 }, 11935 }, 11936 { 11937 name: "MOVWconvert", 11938 argLen: 2, 11939 asm: arm.AMOVW, 11940 reg: regInfo{ 11941 inputs: []inputInfo{ 11942 {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 11943 }, 11944 outputs: []outputInfo{ 11945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 11946 }, 11947 }, 11948 }, 11949 { 11950 name: "FlagEQ", 11951 argLen: 0, 11952 reg: regInfo{}, 11953 }, 11954 { 11955 name: "FlagLT_ULT", 11956 argLen: 0, 11957 reg: regInfo{}, 11958 }, 11959 { 11960 name: "FlagLT_UGT", 11961 argLen: 0, 11962 reg: regInfo{}, 11963 }, 11964 { 11965 name: "FlagGT_UGT", 11966 argLen: 0, 11967 reg: regInfo{}, 11968 }, 11969 { 11970 name: "FlagGT_ULT", 11971 argLen: 0, 11972 reg: regInfo{}, 11973 }, 11974 { 11975 name: "InvertFlags", 11976 argLen: 1, 11977 reg: regInfo{}, 11978 }, 11979 11980 { 11981 name: "ADD", 11982 argLen: 2, 11983 commutative: true, 11984 asm: arm64.AADD, 11985 reg: regInfo{ 11986 inputs: []inputInfo{ 11987 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11988 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 11989 }, 11990 outputs: []outputInfo{ 11991 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 11992 }, 11993 }, 11994 }, 11995 { 11996 name: "ADDconst", 11997 auxType: auxInt64, 11998 argLen: 1, 11999 asm: arm64.AADD, 12000 reg: regInfo{ 12001 inputs: []inputInfo{ 12002 {0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP 12003 }, 12004 outputs: []outputInfo{ 12005 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12006 }, 12007 }, 12008 }, 12009 { 12010 name: "SUB", 12011 argLen: 2, 12012 asm: arm64.ASUB, 12013 reg: regInfo{ 12014 inputs: []inputInfo{ 12015 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12016 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12017 }, 12018 outputs: []outputInfo{ 12019 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12020 }, 12021 }, 12022 }, 12023 { 12024 name: "SUBconst", 12025 auxType: auxInt64, 12026 argLen: 1, 12027 asm: arm64.ASUB, 12028 reg: regInfo{ 12029 inputs: []inputInfo{ 12030 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12031 }, 12032 outputs: []outputInfo{ 12033 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12034 }, 12035 }, 12036 }, 12037 { 12038 name: "MUL", 12039 argLen: 2, 12040 commutative: true, 12041 asm: arm64.AMUL, 12042 reg: regInfo{ 12043 inputs: []inputInfo{ 12044 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12045 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12046 }, 12047 outputs: []outputInfo{ 12048 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12049 }, 12050 }, 12051 }, 12052 { 12053 name: "MULW", 12054 argLen: 2, 12055 commutative: true, 12056 asm: arm64.AMULW, 12057 reg: regInfo{ 12058 inputs: []inputInfo{ 12059 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12060 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12061 }, 12062 outputs: []outputInfo{ 12063 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12064 }, 12065 }, 12066 }, 12067 { 12068 name: "MULH", 12069 argLen: 2, 12070 commutative: true, 12071 asm: arm64.ASMULH, 12072 reg: regInfo{ 12073 inputs: []inputInfo{ 12074 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12075 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12076 }, 12077 outputs: []outputInfo{ 12078 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12079 }, 12080 }, 12081 }, 12082 { 12083 name: "UMULH", 12084 argLen: 2, 12085 commutative: true, 12086 asm: arm64.AUMULH, 12087 reg: regInfo{ 12088 inputs: []inputInfo{ 12089 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12090 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12091 }, 12092 outputs: []outputInfo{ 12093 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12094 }, 12095 }, 12096 }, 12097 { 12098 name: "MULL", 12099 argLen: 2, 12100 commutative: true, 12101 asm: arm64.ASMULL, 12102 reg: regInfo{ 12103 inputs: []inputInfo{ 12104 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12105 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12106 }, 12107 outputs: []outputInfo{ 12108 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12109 }, 12110 }, 12111 }, 12112 { 12113 name: "UMULL", 12114 argLen: 2, 12115 commutative: true, 12116 asm: arm64.AUMULL, 12117 reg: regInfo{ 12118 inputs: []inputInfo{ 12119 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12120 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12121 }, 12122 outputs: []outputInfo{ 12123 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12124 }, 12125 }, 12126 }, 12127 { 12128 name: "DIV", 12129 argLen: 2, 12130 asm: arm64.ASDIV, 12131 reg: regInfo{ 12132 inputs: []inputInfo{ 12133 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12134 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12135 }, 12136 outputs: []outputInfo{ 12137 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12138 }, 12139 }, 12140 }, 12141 { 12142 name: "UDIV", 12143 argLen: 2, 12144 asm: arm64.AUDIV, 12145 reg: regInfo{ 12146 inputs: []inputInfo{ 12147 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12148 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12149 }, 12150 outputs: []outputInfo{ 12151 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12152 }, 12153 }, 12154 }, 12155 { 12156 name: "DIVW", 12157 argLen: 2, 12158 asm: arm64.ASDIVW, 12159 reg: regInfo{ 12160 inputs: []inputInfo{ 12161 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12162 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12163 }, 12164 outputs: []outputInfo{ 12165 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12166 }, 12167 }, 12168 }, 12169 { 12170 name: "UDIVW", 12171 argLen: 2, 12172 asm: arm64.AUDIVW, 12173 reg: regInfo{ 12174 inputs: []inputInfo{ 12175 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12176 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12177 }, 12178 outputs: []outputInfo{ 12179 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12180 }, 12181 }, 12182 }, 12183 { 12184 name: "MOD", 12185 argLen: 2, 12186 asm: arm64.AREM, 12187 reg: regInfo{ 12188 inputs: []inputInfo{ 12189 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12190 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12191 }, 12192 outputs: []outputInfo{ 12193 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12194 }, 12195 }, 12196 }, 12197 { 12198 name: "UMOD", 12199 argLen: 2, 12200 asm: arm64.AUREM, 12201 reg: regInfo{ 12202 inputs: []inputInfo{ 12203 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12204 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12205 }, 12206 outputs: []outputInfo{ 12207 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12208 }, 12209 }, 12210 }, 12211 { 12212 name: "MODW", 12213 argLen: 2, 12214 asm: arm64.AREMW, 12215 reg: regInfo{ 12216 inputs: []inputInfo{ 12217 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12218 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12219 }, 12220 outputs: []outputInfo{ 12221 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12222 }, 12223 }, 12224 }, 12225 { 12226 name: "UMODW", 12227 argLen: 2, 12228 asm: arm64.AUREMW, 12229 reg: regInfo{ 12230 inputs: []inputInfo{ 12231 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12232 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12233 }, 12234 outputs: []outputInfo{ 12235 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12236 }, 12237 }, 12238 }, 12239 { 12240 name: "FADDS", 12241 argLen: 2, 12242 commutative: true, 12243 asm: arm64.AFADDS, 12244 reg: regInfo{ 12245 inputs: []inputInfo{ 12246 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12247 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12248 }, 12249 outputs: []outputInfo{ 12250 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12251 }, 12252 }, 12253 }, 12254 { 12255 name: "FADDD", 12256 argLen: 2, 12257 commutative: true, 12258 asm: arm64.AFADDD, 12259 reg: regInfo{ 12260 inputs: []inputInfo{ 12261 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12262 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12263 }, 12264 outputs: []outputInfo{ 12265 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12266 }, 12267 }, 12268 }, 12269 { 12270 name: "FSUBS", 12271 argLen: 2, 12272 asm: arm64.AFSUBS, 12273 reg: regInfo{ 12274 inputs: []inputInfo{ 12275 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12276 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12277 }, 12278 outputs: []outputInfo{ 12279 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12280 }, 12281 }, 12282 }, 12283 { 12284 name: "FSUBD", 12285 argLen: 2, 12286 asm: arm64.AFSUBD, 12287 reg: regInfo{ 12288 inputs: []inputInfo{ 12289 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12290 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12291 }, 12292 outputs: []outputInfo{ 12293 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12294 }, 12295 }, 12296 }, 12297 { 12298 name: "FMULS", 12299 argLen: 2, 12300 commutative: true, 12301 asm: arm64.AFMULS, 12302 reg: regInfo{ 12303 inputs: []inputInfo{ 12304 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12305 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12306 }, 12307 outputs: []outputInfo{ 12308 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12309 }, 12310 }, 12311 }, 12312 { 12313 name: "FMULD", 12314 argLen: 2, 12315 commutative: true, 12316 asm: arm64.AFMULD, 12317 reg: regInfo{ 12318 inputs: []inputInfo{ 12319 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12320 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12321 }, 12322 outputs: []outputInfo{ 12323 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12324 }, 12325 }, 12326 }, 12327 { 12328 name: "FDIVS", 12329 argLen: 2, 12330 asm: arm64.AFDIVS, 12331 reg: regInfo{ 12332 inputs: []inputInfo{ 12333 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12334 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12335 }, 12336 outputs: []outputInfo{ 12337 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12338 }, 12339 }, 12340 }, 12341 { 12342 name: "FDIVD", 12343 argLen: 2, 12344 asm: arm64.AFDIVD, 12345 reg: regInfo{ 12346 inputs: []inputInfo{ 12347 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12348 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12349 }, 12350 outputs: []outputInfo{ 12351 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12352 }, 12353 }, 12354 }, 12355 { 12356 name: "AND", 12357 argLen: 2, 12358 commutative: true, 12359 asm: arm64.AAND, 12360 reg: regInfo{ 12361 inputs: []inputInfo{ 12362 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12363 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12364 }, 12365 outputs: []outputInfo{ 12366 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12367 }, 12368 }, 12369 }, 12370 { 12371 name: "ANDconst", 12372 auxType: auxInt64, 12373 argLen: 1, 12374 asm: arm64.AAND, 12375 reg: regInfo{ 12376 inputs: []inputInfo{ 12377 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12378 }, 12379 outputs: []outputInfo{ 12380 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12381 }, 12382 }, 12383 }, 12384 { 12385 name: "OR", 12386 argLen: 2, 12387 commutative: true, 12388 asm: arm64.AORR, 12389 reg: regInfo{ 12390 inputs: []inputInfo{ 12391 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12392 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12393 }, 12394 outputs: []outputInfo{ 12395 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12396 }, 12397 }, 12398 }, 12399 { 12400 name: "ORconst", 12401 auxType: auxInt64, 12402 argLen: 1, 12403 asm: arm64.AORR, 12404 reg: regInfo{ 12405 inputs: []inputInfo{ 12406 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12407 }, 12408 outputs: []outputInfo{ 12409 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12410 }, 12411 }, 12412 }, 12413 { 12414 name: "XOR", 12415 argLen: 2, 12416 commutative: true, 12417 asm: arm64.AEOR, 12418 reg: regInfo{ 12419 inputs: []inputInfo{ 12420 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12421 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12422 }, 12423 outputs: []outputInfo{ 12424 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12425 }, 12426 }, 12427 }, 12428 { 12429 name: "XORconst", 12430 auxType: auxInt64, 12431 argLen: 1, 12432 asm: arm64.AEOR, 12433 reg: regInfo{ 12434 inputs: []inputInfo{ 12435 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12436 }, 12437 outputs: []outputInfo{ 12438 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12439 }, 12440 }, 12441 }, 12442 { 12443 name: "BIC", 12444 argLen: 2, 12445 asm: arm64.ABIC, 12446 reg: regInfo{ 12447 inputs: []inputInfo{ 12448 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12449 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12450 }, 12451 outputs: []outputInfo{ 12452 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12453 }, 12454 }, 12455 }, 12456 { 12457 name: "BICconst", 12458 auxType: auxInt64, 12459 argLen: 1, 12460 asm: arm64.ABIC, 12461 reg: regInfo{ 12462 inputs: []inputInfo{ 12463 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12464 }, 12465 outputs: []outputInfo{ 12466 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12467 }, 12468 }, 12469 }, 12470 { 12471 name: "MVN", 12472 argLen: 1, 12473 asm: arm64.AMVN, 12474 reg: regInfo{ 12475 inputs: []inputInfo{ 12476 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12477 }, 12478 outputs: []outputInfo{ 12479 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12480 }, 12481 }, 12482 }, 12483 { 12484 name: "NEG", 12485 argLen: 1, 12486 asm: arm64.ANEG, 12487 reg: regInfo{ 12488 inputs: []inputInfo{ 12489 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12490 }, 12491 outputs: []outputInfo{ 12492 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12493 }, 12494 }, 12495 }, 12496 { 12497 name: "FNEGS", 12498 argLen: 1, 12499 asm: arm64.AFNEGS, 12500 reg: regInfo{ 12501 inputs: []inputInfo{ 12502 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12503 }, 12504 outputs: []outputInfo{ 12505 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12506 }, 12507 }, 12508 }, 12509 { 12510 name: "FNEGD", 12511 argLen: 1, 12512 asm: arm64.AFNEGD, 12513 reg: regInfo{ 12514 inputs: []inputInfo{ 12515 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12516 }, 12517 outputs: []outputInfo{ 12518 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12519 }, 12520 }, 12521 }, 12522 { 12523 name: "FSQRTD", 12524 argLen: 1, 12525 asm: arm64.AFSQRTD, 12526 reg: regInfo{ 12527 inputs: []inputInfo{ 12528 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12529 }, 12530 outputs: []outputInfo{ 12531 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12532 }, 12533 }, 12534 }, 12535 { 12536 name: "REV", 12537 argLen: 1, 12538 asm: arm64.AREV, 12539 reg: regInfo{ 12540 inputs: []inputInfo{ 12541 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12542 }, 12543 outputs: []outputInfo{ 12544 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12545 }, 12546 }, 12547 }, 12548 { 12549 name: "REVW", 12550 argLen: 1, 12551 asm: arm64.AREVW, 12552 reg: regInfo{ 12553 inputs: []inputInfo{ 12554 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12555 }, 12556 outputs: []outputInfo{ 12557 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12558 }, 12559 }, 12560 }, 12561 { 12562 name: "REV16W", 12563 argLen: 1, 12564 asm: arm64.AREV16W, 12565 reg: regInfo{ 12566 inputs: []inputInfo{ 12567 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12568 }, 12569 outputs: []outputInfo{ 12570 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12571 }, 12572 }, 12573 }, 12574 { 12575 name: "RBIT", 12576 argLen: 1, 12577 asm: arm64.ARBIT, 12578 reg: regInfo{ 12579 inputs: []inputInfo{ 12580 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12581 }, 12582 outputs: []outputInfo{ 12583 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12584 }, 12585 }, 12586 }, 12587 { 12588 name: "RBITW", 12589 argLen: 1, 12590 asm: arm64.ARBITW, 12591 reg: regInfo{ 12592 inputs: []inputInfo{ 12593 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12594 }, 12595 outputs: []outputInfo{ 12596 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12597 }, 12598 }, 12599 }, 12600 { 12601 name: "CLZ", 12602 argLen: 1, 12603 asm: arm64.ACLZ, 12604 reg: regInfo{ 12605 inputs: []inputInfo{ 12606 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12607 }, 12608 outputs: []outputInfo{ 12609 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12610 }, 12611 }, 12612 }, 12613 { 12614 name: "CLZW", 12615 argLen: 1, 12616 asm: arm64.ACLZW, 12617 reg: regInfo{ 12618 inputs: []inputInfo{ 12619 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12620 }, 12621 outputs: []outputInfo{ 12622 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12623 }, 12624 }, 12625 }, 12626 { 12627 name: "SLL", 12628 argLen: 2, 12629 asm: arm64.ALSL, 12630 reg: regInfo{ 12631 inputs: []inputInfo{ 12632 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12633 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12634 }, 12635 outputs: []outputInfo{ 12636 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12637 }, 12638 }, 12639 }, 12640 { 12641 name: "SLLconst", 12642 auxType: auxInt64, 12643 argLen: 1, 12644 asm: arm64.ALSL, 12645 reg: regInfo{ 12646 inputs: []inputInfo{ 12647 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12648 }, 12649 outputs: []outputInfo{ 12650 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12651 }, 12652 }, 12653 }, 12654 { 12655 name: "SRL", 12656 argLen: 2, 12657 asm: arm64.ALSR, 12658 reg: regInfo{ 12659 inputs: []inputInfo{ 12660 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12661 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12662 }, 12663 outputs: []outputInfo{ 12664 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12665 }, 12666 }, 12667 }, 12668 { 12669 name: "SRLconst", 12670 auxType: auxInt64, 12671 argLen: 1, 12672 asm: arm64.ALSR, 12673 reg: regInfo{ 12674 inputs: []inputInfo{ 12675 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12676 }, 12677 outputs: []outputInfo{ 12678 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12679 }, 12680 }, 12681 }, 12682 { 12683 name: "SRA", 12684 argLen: 2, 12685 asm: arm64.AASR, 12686 reg: regInfo{ 12687 inputs: []inputInfo{ 12688 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12689 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12690 }, 12691 outputs: []outputInfo{ 12692 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12693 }, 12694 }, 12695 }, 12696 { 12697 name: "SRAconst", 12698 auxType: auxInt64, 12699 argLen: 1, 12700 asm: arm64.AASR, 12701 reg: regInfo{ 12702 inputs: []inputInfo{ 12703 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12704 }, 12705 outputs: []outputInfo{ 12706 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12707 }, 12708 }, 12709 }, 12710 { 12711 name: "RORconst", 12712 auxType: auxInt64, 12713 argLen: 1, 12714 asm: arm64.AROR, 12715 reg: regInfo{ 12716 inputs: []inputInfo{ 12717 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12718 }, 12719 outputs: []outputInfo{ 12720 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12721 }, 12722 }, 12723 }, 12724 { 12725 name: "RORWconst", 12726 auxType: auxInt64, 12727 argLen: 1, 12728 asm: arm64.ARORW, 12729 reg: regInfo{ 12730 inputs: []inputInfo{ 12731 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12732 }, 12733 outputs: []outputInfo{ 12734 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12735 }, 12736 }, 12737 }, 12738 { 12739 name: "CMP", 12740 argLen: 2, 12741 asm: arm64.ACMP, 12742 reg: regInfo{ 12743 inputs: []inputInfo{ 12744 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12745 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12746 }, 12747 }, 12748 }, 12749 { 12750 name: "CMPconst", 12751 auxType: auxInt64, 12752 argLen: 1, 12753 asm: arm64.ACMP, 12754 reg: regInfo{ 12755 inputs: []inputInfo{ 12756 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12757 }, 12758 }, 12759 }, 12760 { 12761 name: "CMPW", 12762 argLen: 2, 12763 asm: arm64.ACMPW, 12764 reg: regInfo{ 12765 inputs: []inputInfo{ 12766 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12767 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12768 }, 12769 }, 12770 }, 12771 { 12772 name: "CMPWconst", 12773 auxType: auxInt32, 12774 argLen: 1, 12775 asm: arm64.ACMPW, 12776 reg: regInfo{ 12777 inputs: []inputInfo{ 12778 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12779 }, 12780 }, 12781 }, 12782 { 12783 name: "CMN", 12784 argLen: 2, 12785 asm: arm64.ACMN, 12786 reg: regInfo{ 12787 inputs: []inputInfo{ 12788 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12789 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12790 }, 12791 }, 12792 }, 12793 { 12794 name: "CMNconst", 12795 auxType: auxInt64, 12796 argLen: 1, 12797 asm: arm64.ACMN, 12798 reg: regInfo{ 12799 inputs: []inputInfo{ 12800 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12801 }, 12802 }, 12803 }, 12804 { 12805 name: "CMNW", 12806 argLen: 2, 12807 asm: arm64.ACMNW, 12808 reg: regInfo{ 12809 inputs: []inputInfo{ 12810 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12811 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12812 }, 12813 }, 12814 }, 12815 { 12816 name: "CMNWconst", 12817 auxType: auxInt32, 12818 argLen: 1, 12819 asm: arm64.ACMNW, 12820 reg: regInfo{ 12821 inputs: []inputInfo{ 12822 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12823 }, 12824 }, 12825 }, 12826 { 12827 name: "FCMPS", 12828 argLen: 2, 12829 asm: arm64.AFCMPS, 12830 reg: regInfo{ 12831 inputs: []inputInfo{ 12832 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12833 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12834 }, 12835 }, 12836 }, 12837 { 12838 name: "FCMPD", 12839 argLen: 2, 12840 asm: arm64.AFCMPD, 12841 reg: regInfo{ 12842 inputs: []inputInfo{ 12843 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12844 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 12845 }, 12846 }, 12847 }, 12848 { 12849 name: "ADDshiftLL", 12850 auxType: auxInt64, 12851 argLen: 2, 12852 asm: arm64.AADD, 12853 reg: regInfo{ 12854 inputs: []inputInfo{ 12855 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12856 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12857 }, 12858 outputs: []outputInfo{ 12859 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12860 }, 12861 }, 12862 }, 12863 { 12864 name: "ADDshiftRL", 12865 auxType: auxInt64, 12866 argLen: 2, 12867 asm: arm64.AADD, 12868 reg: regInfo{ 12869 inputs: []inputInfo{ 12870 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12871 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12872 }, 12873 outputs: []outputInfo{ 12874 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12875 }, 12876 }, 12877 }, 12878 { 12879 name: "ADDshiftRA", 12880 auxType: auxInt64, 12881 argLen: 2, 12882 asm: arm64.AADD, 12883 reg: regInfo{ 12884 inputs: []inputInfo{ 12885 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12886 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12887 }, 12888 outputs: []outputInfo{ 12889 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12890 }, 12891 }, 12892 }, 12893 { 12894 name: "SUBshiftLL", 12895 auxType: auxInt64, 12896 argLen: 2, 12897 asm: arm64.ASUB, 12898 reg: regInfo{ 12899 inputs: []inputInfo{ 12900 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12901 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12902 }, 12903 outputs: []outputInfo{ 12904 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12905 }, 12906 }, 12907 }, 12908 { 12909 name: "SUBshiftRL", 12910 auxType: auxInt64, 12911 argLen: 2, 12912 asm: arm64.ASUB, 12913 reg: regInfo{ 12914 inputs: []inputInfo{ 12915 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12916 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12917 }, 12918 outputs: []outputInfo{ 12919 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12920 }, 12921 }, 12922 }, 12923 { 12924 name: "SUBshiftRA", 12925 auxType: auxInt64, 12926 argLen: 2, 12927 asm: arm64.ASUB, 12928 reg: regInfo{ 12929 inputs: []inputInfo{ 12930 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12931 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12932 }, 12933 outputs: []outputInfo{ 12934 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12935 }, 12936 }, 12937 }, 12938 { 12939 name: "ANDshiftLL", 12940 auxType: auxInt64, 12941 argLen: 2, 12942 asm: arm64.AAND, 12943 reg: regInfo{ 12944 inputs: []inputInfo{ 12945 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12946 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12947 }, 12948 outputs: []outputInfo{ 12949 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12950 }, 12951 }, 12952 }, 12953 { 12954 name: "ANDshiftRL", 12955 auxType: auxInt64, 12956 argLen: 2, 12957 asm: arm64.AAND, 12958 reg: regInfo{ 12959 inputs: []inputInfo{ 12960 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12961 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12962 }, 12963 outputs: []outputInfo{ 12964 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12965 }, 12966 }, 12967 }, 12968 { 12969 name: "ANDshiftRA", 12970 auxType: auxInt64, 12971 argLen: 2, 12972 asm: arm64.AAND, 12973 reg: regInfo{ 12974 inputs: []inputInfo{ 12975 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12976 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12977 }, 12978 outputs: []outputInfo{ 12979 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12980 }, 12981 }, 12982 }, 12983 { 12984 name: "ORshiftLL", 12985 auxType: auxInt64, 12986 argLen: 2, 12987 asm: arm64.AORR, 12988 reg: regInfo{ 12989 inputs: []inputInfo{ 12990 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12991 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 12992 }, 12993 outputs: []outputInfo{ 12994 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 12995 }, 12996 }, 12997 }, 12998 { 12999 name: "ORshiftRL", 13000 auxType: auxInt64, 13001 argLen: 2, 13002 asm: arm64.AORR, 13003 reg: regInfo{ 13004 inputs: []inputInfo{ 13005 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13006 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13007 }, 13008 outputs: []outputInfo{ 13009 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13010 }, 13011 }, 13012 }, 13013 { 13014 name: "ORshiftRA", 13015 auxType: auxInt64, 13016 argLen: 2, 13017 asm: arm64.AORR, 13018 reg: regInfo{ 13019 inputs: []inputInfo{ 13020 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13021 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13022 }, 13023 outputs: []outputInfo{ 13024 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13025 }, 13026 }, 13027 }, 13028 { 13029 name: "XORshiftLL", 13030 auxType: auxInt64, 13031 argLen: 2, 13032 asm: arm64.AEOR, 13033 reg: regInfo{ 13034 inputs: []inputInfo{ 13035 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13036 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13037 }, 13038 outputs: []outputInfo{ 13039 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13040 }, 13041 }, 13042 }, 13043 { 13044 name: "XORshiftRL", 13045 auxType: auxInt64, 13046 argLen: 2, 13047 asm: arm64.AEOR, 13048 reg: regInfo{ 13049 inputs: []inputInfo{ 13050 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13051 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13052 }, 13053 outputs: []outputInfo{ 13054 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13055 }, 13056 }, 13057 }, 13058 { 13059 name: "XORshiftRA", 13060 auxType: auxInt64, 13061 argLen: 2, 13062 asm: arm64.AEOR, 13063 reg: regInfo{ 13064 inputs: []inputInfo{ 13065 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13066 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13067 }, 13068 outputs: []outputInfo{ 13069 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13070 }, 13071 }, 13072 }, 13073 { 13074 name: "BICshiftLL", 13075 auxType: auxInt64, 13076 argLen: 2, 13077 asm: arm64.ABIC, 13078 reg: regInfo{ 13079 inputs: []inputInfo{ 13080 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13081 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13082 }, 13083 outputs: []outputInfo{ 13084 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13085 }, 13086 }, 13087 }, 13088 { 13089 name: "BICshiftRL", 13090 auxType: auxInt64, 13091 argLen: 2, 13092 asm: arm64.ABIC, 13093 reg: regInfo{ 13094 inputs: []inputInfo{ 13095 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13096 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13097 }, 13098 outputs: []outputInfo{ 13099 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13100 }, 13101 }, 13102 }, 13103 { 13104 name: "BICshiftRA", 13105 auxType: auxInt64, 13106 argLen: 2, 13107 asm: arm64.ABIC, 13108 reg: regInfo{ 13109 inputs: []inputInfo{ 13110 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13111 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13112 }, 13113 outputs: []outputInfo{ 13114 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13115 }, 13116 }, 13117 }, 13118 { 13119 name: "CMPshiftLL", 13120 auxType: auxInt64, 13121 argLen: 2, 13122 asm: arm64.ACMP, 13123 reg: regInfo{ 13124 inputs: []inputInfo{ 13125 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13126 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13127 }, 13128 }, 13129 }, 13130 { 13131 name: "CMPshiftRL", 13132 auxType: auxInt64, 13133 argLen: 2, 13134 asm: arm64.ACMP, 13135 reg: regInfo{ 13136 inputs: []inputInfo{ 13137 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13138 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13139 }, 13140 }, 13141 }, 13142 { 13143 name: "CMPshiftRA", 13144 auxType: auxInt64, 13145 argLen: 2, 13146 asm: arm64.ACMP, 13147 reg: regInfo{ 13148 inputs: []inputInfo{ 13149 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13150 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13151 }, 13152 }, 13153 }, 13154 { 13155 name: "MOVDconst", 13156 auxType: auxInt64, 13157 argLen: 0, 13158 rematerializeable: true, 13159 asm: arm64.AMOVD, 13160 reg: regInfo{ 13161 outputs: []outputInfo{ 13162 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13163 }, 13164 }, 13165 }, 13166 { 13167 name: "FMOVSconst", 13168 auxType: auxFloat64, 13169 argLen: 0, 13170 rematerializeable: true, 13171 asm: arm64.AFMOVS, 13172 reg: regInfo{ 13173 outputs: []outputInfo{ 13174 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13175 }, 13176 }, 13177 }, 13178 { 13179 name: "FMOVDconst", 13180 auxType: auxFloat64, 13181 argLen: 0, 13182 rematerializeable: true, 13183 asm: arm64.AFMOVD, 13184 reg: regInfo{ 13185 outputs: []outputInfo{ 13186 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13187 }, 13188 }, 13189 }, 13190 { 13191 name: "MOVDaddr", 13192 auxType: auxSymOff, 13193 argLen: 1, 13194 rematerializeable: true, 13195 symEffect: SymAddr, 13196 asm: arm64.AMOVD, 13197 reg: regInfo{ 13198 inputs: []inputInfo{ 13199 {0, 9223372037928517632}, // SP SB 13200 }, 13201 outputs: []outputInfo{ 13202 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13203 }, 13204 }, 13205 }, 13206 { 13207 name: "MOVBload", 13208 auxType: auxSymOff, 13209 argLen: 2, 13210 faultOnNilArg0: true, 13211 symEffect: SymRead, 13212 asm: arm64.AMOVB, 13213 reg: regInfo{ 13214 inputs: []inputInfo{ 13215 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13216 }, 13217 outputs: []outputInfo{ 13218 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13219 }, 13220 }, 13221 }, 13222 { 13223 name: "MOVBUload", 13224 auxType: auxSymOff, 13225 argLen: 2, 13226 faultOnNilArg0: true, 13227 symEffect: SymRead, 13228 asm: arm64.AMOVBU, 13229 reg: regInfo{ 13230 inputs: []inputInfo{ 13231 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13232 }, 13233 outputs: []outputInfo{ 13234 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13235 }, 13236 }, 13237 }, 13238 { 13239 name: "MOVHload", 13240 auxType: auxSymOff, 13241 argLen: 2, 13242 faultOnNilArg0: true, 13243 symEffect: SymRead, 13244 asm: arm64.AMOVH, 13245 reg: regInfo{ 13246 inputs: []inputInfo{ 13247 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13248 }, 13249 outputs: []outputInfo{ 13250 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13251 }, 13252 }, 13253 }, 13254 { 13255 name: "MOVHUload", 13256 auxType: auxSymOff, 13257 argLen: 2, 13258 faultOnNilArg0: true, 13259 symEffect: SymRead, 13260 asm: arm64.AMOVHU, 13261 reg: regInfo{ 13262 inputs: []inputInfo{ 13263 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13264 }, 13265 outputs: []outputInfo{ 13266 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13267 }, 13268 }, 13269 }, 13270 { 13271 name: "MOVWload", 13272 auxType: auxSymOff, 13273 argLen: 2, 13274 faultOnNilArg0: true, 13275 symEffect: SymRead, 13276 asm: arm64.AMOVW, 13277 reg: regInfo{ 13278 inputs: []inputInfo{ 13279 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13280 }, 13281 outputs: []outputInfo{ 13282 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13283 }, 13284 }, 13285 }, 13286 { 13287 name: "MOVWUload", 13288 auxType: auxSymOff, 13289 argLen: 2, 13290 faultOnNilArg0: true, 13291 symEffect: SymRead, 13292 asm: arm64.AMOVWU, 13293 reg: regInfo{ 13294 inputs: []inputInfo{ 13295 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13296 }, 13297 outputs: []outputInfo{ 13298 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13299 }, 13300 }, 13301 }, 13302 { 13303 name: "MOVDload", 13304 auxType: auxSymOff, 13305 argLen: 2, 13306 faultOnNilArg0: true, 13307 symEffect: SymRead, 13308 asm: arm64.AMOVD, 13309 reg: regInfo{ 13310 inputs: []inputInfo{ 13311 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13312 }, 13313 outputs: []outputInfo{ 13314 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13315 }, 13316 }, 13317 }, 13318 { 13319 name: "FMOVSload", 13320 auxType: auxSymOff, 13321 argLen: 2, 13322 faultOnNilArg0: true, 13323 symEffect: SymRead, 13324 asm: arm64.AFMOVS, 13325 reg: regInfo{ 13326 inputs: []inputInfo{ 13327 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13328 }, 13329 outputs: []outputInfo{ 13330 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13331 }, 13332 }, 13333 }, 13334 { 13335 name: "FMOVDload", 13336 auxType: auxSymOff, 13337 argLen: 2, 13338 faultOnNilArg0: true, 13339 symEffect: SymRead, 13340 asm: arm64.AFMOVD, 13341 reg: regInfo{ 13342 inputs: []inputInfo{ 13343 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13344 }, 13345 outputs: []outputInfo{ 13346 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13347 }, 13348 }, 13349 }, 13350 { 13351 name: "MOVBstore", 13352 auxType: auxSymOff, 13353 argLen: 3, 13354 faultOnNilArg0: true, 13355 symEffect: SymWrite, 13356 asm: arm64.AMOVB, 13357 reg: regInfo{ 13358 inputs: []inputInfo{ 13359 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13360 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13361 }, 13362 }, 13363 }, 13364 { 13365 name: "MOVHstore", 13366 auxType: auxSymOff, 13367 argLen: 3, 13368 faultOnNilArg0: true, 13369 symEffect: SymWrite, 13370 asm: arm64.AMOVH, 13371 reg: regInfo{ 13372 inputs: []inputInfo{ 13373 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13374 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13375 }, 13376 }, 13377 }, 13378 { 13379 name: "MOVWstore", 13380 auxType: auxSymOff, 13381 argLen: 3, 13382 faultOnNilArg0: true, 13383 symEffect: SymWrite, 13384 asm: arm64.AMOVW, 13385 reg: regInfo{ 13386 inputs: []inputInfo{ 13387 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13388 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13389 }, 13390 }, 13391 }, 13392 { 13393 name: "MOVDstore", 13394 auxType: auxSymOff, 13395 argLen: 3, 13396 faultOnNilArg0: true, 13397 symEffect: SymWrite, 13398 asm: arm64.AMOVD, 13399 reg: regInfo{ 13400 inputs: []inputInfo{ 13401 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13402 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13403 }, 13404 }, 13405 }, 13406 { 13407 name: "STP", 13408 auxType: auxSymOff, 13409 argLen: 4, 13410 faultOnNilArg0: true, 13411 symEffect: SymWrite, 13412 asm: arm64.ASTP, 13413 reg: regInfo{ 13414 inputs: []inputInfo{ 13415 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13416 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13417 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13418 }, 13419 }, 13420 }, 13421 { 13422 name: "FMOVSstore", 13423 auxType: auxSymOff, 13424 argLen: 3, 13425 faultOnNilArg0: true, 13426 symEffect: SymWrite, 13427 asm: arm64.AFMOVS, 13428 reg: regInfo{ 13429 inputs: []inputInfo{ 13430 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13431 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13432 }, 13433 }, 13434 }, 13435 { 13436 name: "FMOVDstore", 13437 auxType: auxSymOff, 13438 argLen: 3, 13439 faultOnNilArg0: true, 13440 symEffect: SymWrite, 13441 asm: arm64.AFMOVD, 13442 reg: regInfo{ 13443 inputs: []inputInfo{ 13444 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13445 {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13446 }, 13447 }, 13448 }, 13449 { 13450 name: "MOVBstorezero", 13451 auxType: auxSymOff, 13452 argLen: 2, 13453 faultOnNilArg0: true, 13454 symEffect: SymWrite, 13455 asm: arm64.AMOVB, 13456 reg: regInfo{ 13457 inputs: []inputInfo{ 13458 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13459 }, 13460 }, 13461 }, 13462 { 13463 name: "MOVHstorezero", 13464 auxType: auxSymOff, 13465 argLen: 2, 13466 faultOnNilArg0: true, 13467 symEffect: SymWrite, 13468 asm: arm64.AMOVH, 13469 reg: regInfo{ 13470 inputs: []inputInfo{ 13471 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13472 }, 13473 }, 13474 }, 13475 { 13476 name: "MOVWstorezero", 13477 auxType: auxSymOff, 13478 argLen: 2, 13479 faultOnNilArg0: true, 13480 symEffect: SymWrite, 13481 asm: arm64.AMOVW, 13482 reg: regInfo{ 13483 inputs: []inputInfo{ 13484 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13485 }, 13486 }, 13487 }, 13488 { 13489 name: "MOVDstorezero", 13490 auxType: auxSymOff, 13491 argLen: 2, 13492 faultOnNilArg0: true, 13493 symEffect: SymWrite, 13494 asm: arm64.AMOVD, 13495 reg: regInfo{ 13496 inputs: []inputInfo{ 13497 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13498 }, 13499 }, 13500 }, 13501 { 13502 name: "MOVQstorezero", 13503 auxType: auxSymOff, 13504 argLen: 2, 13505 faultOnNilArg0: true, 13506 symEffect: SymWrite, 13507 asm: arm64.ASTP, 13508 reg: regInfo{ 13509 inputs: []inputInfo{ 13510 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 13511 }, 13512 }, 13513 }, 13514 { 13515 name: "MOVBreg", 13516 argLen: 1, 13517 asm: arm64.AMOVB, 13518 reg: regInfo{ 13519 inputs: []inputInfo{ 13520 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13521 }, 13522 outputs: []outputInfo{ 13523 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13524 }, 13525 }, 13526 }, 13527 { 13528 name: "MOVBUreg", 13529 argLen: 1, 13530 asm: arm64.AMOVBU, 13531 reg: regInfo{ 13532 inputs: []inputInfo{ 13533 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13534 }, 13535 outputs: []outputInfo{ 13536 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13537 }, 13538 }, 13539 }, 13540 { 13541 name: "MOVHreg", 13542 argLen: 1, 13543 asm: arm64.AMOVH, 13544 reg: regInfo{ 13545 inputs: []inputInfo{ 13546 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13547 }, 13548 outputs: []outputInfo{ 13549 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13550 }, 13551 }, 13552 }, 13553 { 13554 name: "MOVHUreg", 13555 argLen: 1, 13556 asm: arm64.AMOVHU, 13557 reg: regInfo{ 13558 inputs: []inputInfo{ 13559 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13560 }, 13561 outputs: []outputInfo{ 13562 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13563 }, 13564 }, 13565 }, 13566 { 13567 name: "MOVWreg", 13568 argLen: 1, 13569 asm: arm64.AMOVW, 13570 reg: regInfo{ 13571 inputs: []inputInfo{ 13572 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13573 }, 13574 outputs: []outputInfo{ 13575 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13576 }, 13577 }, 13578 }, 13579 { 13580 name: "MOVWUreg", 13581 argLen: 1, 13582 asm: arm64.AMOVWU, 13583 reg: regInfo{ 13584 inputs: []inputInfo{ 13585 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13586 }, 13587 outputs: []outputInfo{ 13588 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13589 }, 13590 }, 13591 }, 13592 { 13593 name: "MOVDreg", 13594 argLen: 1, 13595 asm: arm64.AMOVD, 13596 reg: regInfo{ 13597 inputs: []inputInfo{ 13598 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13599 }, 13600 outputs: []outputInfo{ 13601 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13602 }, 13603 }, 13604 }, 13605 { 13606 name: "MOVDnop", 13607 argLen: 1, 13608 resultInArg0: true, 13609 reg: regInfo{ 13610 inputs: []inputInfo{ 13611 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13612 }, 13613 outputs: []outputInfo{ 13614 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13615 }, 13616 }, 13617 }, 13618 { 13619 name: "SCVTFWS", 13620 argLen: 1, 13621 asm: arm64.ASCVTFWS, 13622 reg: regInfo{ 13623 inputs: []inputInfo{ 13624 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13625 }, 13626 outputs: []outputInfo{ 13627 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13628 }, 13629 }, 13630 }, 13631 { 13632 name: "SCVTFWD", 13633 argLen: 1, 13634 asm: arm64.ASCVTFWD, 13635 reg: regInfo{ 13636 inputs: []inputInfo{ 13637 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13638 }, 13639 outputs: []outputInfo{ 13640 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13641 }, 13642 }, 13643 }, 13644 { 13645 name: "UCVTFWS", 13646 argLen: 1, 13647 asm: arm64.AUCVTFWS, 13648 reg: regInfo{ 13649 inputs: []inputInfo{ 13650 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13651 }, 13652 outputs: []outputInfo{ 13653 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13654 }, 13655 }, 13656 }, 13657 { 13658 name: "UCVTFWD", 13659 argLen: 1, 13660 asm: arm64.AUCVTFWD, 13661 reg: regInfo{ 13662 inputs: []inputInfo{ 13663 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13664 }, 13665 outputs: []outputInfo{ 13666 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13667 }, 13668 }, 13669 }, 13670 { 13671 name: "SCVTFS", 13672 argLen: 1, 13673 asm: arm64.ASCVTFS, 13674 reg: regInfo{ 13675 inputs: []inputInfo{ 13676 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13677 }, 13678 outputs: []outputInfo{ 13679 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13680 }, 13681 }, 13682 }, 13683 { 13684 name: "SCVTFD", 13685 argLen: 1, 13686 asm: arm64.ASCVTFD, 13687 reg: regInfo{ 13688 inputs: []inputInfo{ 13689 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13690 }, 13691 outputs: []outputInfo{ 13692 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13693 }, 13694 }, 13695 }, 13696 { 13697 name: "UCVTFS", 13698 argLen: 1, 13699 asm: arm64.AUCVTFS, 13700 reg: regInfo{ 13701 inputs: []inputInfo{ 13702 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13703 }, 13704 outputs: []outputInfo{ 13705 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13706 }, 13707 }, 13708 }, 13709 { 13710 name: "UCVTFD", 13711 argLen: 1, 13712 asm: arm64.AUCVTFD, 13713 reg: regInfo{ 13714 inputs: []inputInfo{ 13715 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13716 }, 13717 outputs: []outputInfo{ 13718 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13719 }, 13720 }, 13721 }, 13722 { 13723 name: "FCVTZSSW", 13724 argLen: 1, 13725 asm: arm64.AFCVTZSSW, 13726 reg: regInfo{ 13727 inputs: []inputInfo{ 13728 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13729 }, 13730 outputs: []outputInfo{ 13731 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13732 }, 13733 }, 13734 }, 13735 { 13736 name: "FCVTZSDW", 13737 argLen: 1, 13738 asm: arm64.AFCVTZSDW, 13739 reg: regInfo{ 13740 inputs: []inputInfo{ 13741 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13742 }, 13743 outputs: []outputInfo{ 13744 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13745 }, 13746 }, 13747 }, 13748 { 13749 name: "FCVTZUSW", 13750 argLen: 1, 13751 asm: arm64.AFCVTZUSW, 13752 reg: regInfo{ 13753 inputs: []inputInfo{ 13754 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13755 }, 13756 outputs: []outputInfo{ 13757 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13758 }, 13759 }, 13760 }, 13761 { 13762 name: "FCVTZUDW", 13763 argLen: 1, 13764 asm: arm64.AFCVTZUDW, 13765 reg: regInfo{ 13766 inputs: []inputInfo{ 13767 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13768 }, 13769 outputs: []outputInfo{ 13770 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13771 }, 13772 }, 13773 }, 13774 { 13775 name: "FCVTZSS", 13776 argLen: 1, 13777 asm: arm64.AFCVTZSS, 13778 reg: regInfo{ 13779 inputs: []inputInfo{ 13780 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13781 }, 13782 outputs: []outputInfo{ 13783 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13784 }, 13785 }, 13786 }, 13787 { 13788 name: "FCVTZSD", 13789 argLen: 1, 13790 asm: arm64.AFCVTZSD, 13791 reg: regInfo{ 13792 inputs: []inputInfo{ 13793 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13794 }, 13795 outputs: []outputInfo{ 13796 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13797 }, 13798 }, 13799 }, 13800 { 13801 name: "FCVTZUS", 13802 argLen: 1, 13803 asm: arm64.AFCVTZUS, 13804 reg: regInfo{ 13805 inputs: []inputInfo{ 13806 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13807 }, 13808 outputs: []outputInfo{ 13809 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13810 }, 13811 }, 13812 }, 13813 { 13814 name: "FCVTZUD", 13815 argLen: 1, 13816 asm: arm64.AFCVTZUD, 13817 reg: regInfo{ 13818 inputs: []inputInfo{ 13819 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13820 }, 13821 outputs: []outputInfo{ 13822 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13823 }, 13824 }, 13825 }, 13826 { 13827 name: "FCVTSD", 13828 argLen: 1, 13829 asm: arm64.AFCVTSD, 13830 reg: regInfo{ 13831 inputs: []inputInfo{ 13832 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13833 }, 13834 outputs: []outputInfo{ 13835 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13836 }, 13837 }, 13838 }, 13839 { 13840 name: "FCVTDS", 13841 argLen: 1, 13842 asm: arm64.AFCVTDS, 13843 reg: regInfo{ 13844 inputs: []inputInfo{ 13845 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13846 }, 13847 outputs: []outputInfo{ 13848 {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13849 }, 13850 }, 13851 }, 13852 { 13853 name: "CSELULT", 13854 argLen: 3, 13855 asm: arm64.ACSEL, 13856 reg: regInfo{ 13857 inputs: []inputInfo{ 13858 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13859 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13860 }, 13861 outputs: []outputInfo{ 13862 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13863 }, 13864 }, 13865 }, 13866 { 13867 name: "CSELULT0", 13868 argLen: 2, 13869 asm: arm64.ACSEL, 13870 reg: regInfo{ 13871 inputs: []inputInfo{ 13872 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13873 }, 13874 outputs: []outputInfo{ 13875 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13876 }, 13877 }, 13878 }, 13879 { 13880 name: "CALLstatic", 13881 auxType: auxSymOff, 13882 argLen: 1, 13883 clobberFlags: true, 13884 call: true, 13885 symEffect: SymNone, 13886 reg: regInfo{ 13887 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13888 }, 13889 }, 13890 { 13891 name: "CALLclosure", 13892 auxType: auxInt64, 13893 argLen: 3, 13894 clobberFlags: true, 13895 call: true, 13896 reg: regInfo{ 13897 inputs: []inputInfo{ 13898 {1, 67108864}, // R26 13899 {0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP 13900 }, 13901 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13902 }, 13903 }, 13904 { 13905 name: "CALLinter", 13906 auxType: auxInt64, 13907 argLen: 2, 13908 clobberFlags: true, 13909 call: true, 13910 reg: regInfo{ 13911 inputs: []inputInfo{ 13912 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13913 }, 13914 clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 13915 }, 13916 }, 13917 { 13918 name: "LoweredNilCheck", 13919 argLen: 2, 13920 nilCheck: true, 13921 faultOnNilArg0: true, 13922 reg: regInfo{ 13923 inputs: []inputInfo{ 13924 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 13925 }, 13926 }, 13927 }, 13928 { 13929 name: "Equal", 13930 argLen: 1, 13931 reg: regInfo{ 13932 outputs: []outputInfo{ 13933 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13934 }, 13935 }, 13936 }, 13937 { 13938 name: "NotEqual", 13939 argLen: 1, 13940 reg: regInfo{ 13941 outputs: []outputInfo{ 13942 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13943 }, 13944 }, 13945 }, 13946 { 13947 name: "LessThan", 13948 argLen: 1, 13949 reg: regInfo{ 13950 outputs: []outputInfo{ 13951 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13952 }, 13953 }, 13954 }, 13955 { 13956 name: "LessEqual", 13957 argLen: 1, 13958 reg: regInfo{ 13959 outputs: []outputInfo{ 13960 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13961 }, 13962 }, 13963 }, 13964 { 13965 name: "GreaterThan", 13966 argLen: 1, 13967 reg: regInfo{ 13968 outputs: []outputInfo{ 13969 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13970 }, 13971 }, 13972 }, 13973 { 13974 name: "GreaterEqual", 13975 argLen: 1, 13976 reg: regInfo{ 13977 outputs: []outputInfo{ 13978 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13979 }, 13980 }, 13981 }, 13982 { 13983 name: "LessThanU", 13984 argLen: 1, 13985 reg: regInfo{ 13986 outputs: []outputInfo{ 13987 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13988 }, 13989 }, 13990 }, 13991 { 13992 name: "LessEqualU", 13993 argLen: 1, 13994 reg: regInfo{ 13995 outputs: []outputInfo{ 13996 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 13997 }, 13998 }, 13999 }, 14000 { 14001 name: "GreaterThanU", 14002 argLen: 1, 14003 reg: regInfo{ 14004 outputs: []outputInfo{ 14005 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14006 }, 14007 }, 14008 }, 14009 { 14010 name: "GreaterEqualU", 14011 argLen: 1, 14012 reg: regInfo{ 14013 outputs: []outputInfo{ 14014 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14015 }, 14016 }, 14017 }, 14018 { 14019 name: "DUFFZERO", 14020 auxType: auxInt64, 14021 argLen: 2, 14022 faultOnNilArg0: true, 14023 reg: regInfo{ 14024 inputs: []inputInfo{ 14025 {0, 65536}, // R16 14026 }, 14027 clobbers: 536936448, // R16 R30 14028 }, 14029 }, 14030 { 14031 name: "LoweredZero", 14032 argLen: 3, 14033 clobberFlags: true, 14034 faultOnNilArg0: true, 14035 reg: regInfo{ 14036 inputs: []inputInfo{ 14037 {0, 65536}, // R16 14038 {1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14039 }, 14040 clobbers: 65536, // R16 14041 }, 14042 }, 14043 { 14044 name: "DUFFCOPY", 14045 auxType: auxInt64, 14046 argLen: 3, 14047 faultOnNilArg0: true, 14048 faultOnNilArg1: true, 14049 reg: regInfo{ 14050 inputs: []inputInfo{ 14051 {0, 131072}, // R17 14052 {1, 65536}, // R16 14053 }, 14054 clobbers: 537067520, // R16 R17 R30 14055 }, 14056 }, 14057 { 14058 name: "LoweredMove", 14059 argLen: 4, 14060 clobberFlags: true, 14061 faultOnNilArg0: true, 14062 faultOnNilArg1: true, 14063 reg: regInfo{ 14064 inputs: []inputInfo{ 14065 {0, 131072}, // R17 14066 {1, 65536}, // R16 14067 {2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14068 }, 14069 clobbers: 196608, // R16 R17 14070 }, 14071 }, 14072 { 14073 name: "LoweredGetClosurePtr", 14074 argLen: 0, 14075 reg: regInfo{ 14076 outputs: []outputInfo{ 14077 {0, 67108864}, // R26 14078 }, 14079 }, 14080 }, 14081 { 14082 name: "LoweredGetCallerSP", 14083 argLen: 0, 14084 rematerializeable: true, 14085 reg: regInfo{ 14086 outputs: []outputInfo{ 14087 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14088 }, 14089 }, 14090 }, 14091 { 14092 name: "MOVDconvert", 14093 argLen: 2, 14094 asm: arm64.AMOVD, 14095 reg: regInfo{ 14096 inputs: []inputInfo{ 14097 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14098 }, 14099 outputs: []outputInfo{ 14100 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14101 }, 14102 }, 14103 }, 14104 { 14105 name: "FlagEQ", 14106 argLen: 0, 14107 reg: regInfo{}, 14108 }, 14109 { 14110 name: "FlagLT_ULT", 14111 argLen: 0, 14112 reg: regInfo{}, 14113 }, 14114 { 14115 name: "FlagLT_UGT", 14116 argLen: 0, 14117 reg: regInfo{}, 14118 }, 14119 { 14120 name: "FlagGT_UGT", 14121 argLen: 0, 14122 reg: regInfo{}, 14123 }, 14124 { 14125 name: "FlagGT_ULT", 14126 argLen: 0, 14127 reg: regInfo{}, 14128 }, 14129 { 14130 name: "InvertFlags", 14131 argLen: 1, 14132 reg: regInfo{}, 14133 }, 14134 { 14135 name: "LDAR", 14136 argLen: 2, 14137 faultOnNilArg0: true, 14138 asm: arm64.ALDAR, 14139 reg: regInfo{ 14140 inputs: []inputInfo{ 14141 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14142 }, 14143 outputs: []outputInfo{ 14144 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14145 }, 14146 }, 14147 }, 14148 { 14149 name: "LDARW", 14150 argLen: 2, 14151 faultOnNilArg0: true, 14152 asm: arm64.ALDARW, 14153 reg: regInfo{ 14154 inputs: []inputInfo{ 14155 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14156 }, 14157 outputs: []outputInfo{ 14158 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14159 }, 14160 }, 14161 }, 14162 { 14163 name: "STLR", 14164 argLen: 3, 14165 faultOnNilArg0: true, 14166 hasSideEffects: true, 14167 asm: arm64.ASTLR, 14168 reg: regInfo{ 14169 inputs: []inputInfo{ 14170 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14171 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14172 }, 14173 }, 14174 }, 14175 { 14176 name: "STLRW", 14177 argLen: 3, 14178 faultOnNilArg0: true, 14179 hasSideEffects: true, 14180 asm: arm64.ASTLRW, 14181 reg: regInfo{ 14182 inputs: []inputInfo{ 14183 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14184 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14185 }, 14186 }, 14187 }, 14188 { 14189 name: "LoweredAtomicExchange64", 14190 argLen: 3, 14191 resultNotInArgs: true, 14192 faultOnNilArg0: true, 14193 hasSideEffects: true, 14194 reg: regInfo{ 14195 inputs: []inputInfo{ 14196 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14197 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14198 }, 14199 outputs: []outputInfo{ 14200 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14201 }, 14202 }, 14203 }, 14204 { 14205 name: "LoweredAtomicExchange32", 14206 argLen: 3, 14207 resultNotInArgs: true, 14208 faultOnNilArg0: true, 14209 hasSideEffects: true, 14210 reg: regInfo{ 14211 inputs: []inputInfo{ 14212 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14213 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14214 }, 14215 outputs: []outputInfo{ 14216 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14217 }, 14218 }, 14219 }, 14220 { 14221 name: "LoweredAtomicAdd64", 14222 argLen: 3, 14223 resultNotInArgs: true, 14224 faultOnNilArg0: true, 14225 hasSideEffects: true, 14226 reg: regInfo{ 14227 inputs: []inputInfo{ 14228 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14229 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14230 }, 14231 outputs: []outputInfo{ 14232 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14233 }, 14234 }, 14235 }, 14236 { 14237 name: "LoweredAtomicAdd32", 14238 argLen: 3, 14239 resultNotInArgs: true, 14240 faultOnNilArg0: true, 14241 hasSideEffects: true, 14242 reg: regInfo{ 14243 inputs: []inputInfo{ 14244 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14245 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14246 }, 14247 outputs: []outputInfo{ 14248 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14249 }, 14250 }, 14251 }, 14252 { 14253 name: "LoweredAtomicCas64", 14254 argLen: 4, 14255 resultNotInArgs: true, 14256 clobberFlags: true, 14257 faultOnNilArg0: true, 14258 hasSideEffects: true, 14259 reg: regInfo{ 14260 inputs: []inputInfo{ 14261 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14262 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14263 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14264 }, 14265 outputs: []outputInfo{ 14266 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14267 }, 14268 }, 14269 }, 14270 { 14271 name: "LoweredAtomicCas32", 14272 argLen: 4, 14273 resultNotInArgs: true, 14274 clobberFlags: true, 14275 faultOnNilArg0: true, 14276 hasSideEffects: true, 14277 reg: regInfo{ 14278 inputs: []inputInfo{ 14279 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14280 {2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14281 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14282 }, 14283 outputs: []outputInfo{ 14284 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 14285 }, 14286 }, 14287 }, 14288 { 14289 name: "LoweredAtomicAnd8", 14290 argLen: 3, 14291 faultOnNilArg0: true, 14292 hasSideEffects: true, 14293 asm: arm64.AAND, 14294 reg: regInfo{ 14295 inputs: []inputInfo{ 14296 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14297 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14298 }, 14299 }, 14300 }, 14301 { 14302 name: "LoweredAtomicOr8", 14303 argLen: 3, 14304 faultOnNilArg0: true, 14305 hasSideEffects: true, 14306 asm: arm64.AORR, 14307 reg: regInfo{ 14308 inputs: []inputInfo{ 14309 {1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 14310 {0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB 14311 }, 14312 }, 14313 }, 14314 14315 { 14316 name: "ADD", 14317 argLen: 2, 14318 commutative: true, 14319 asm: mips.AADDU, 14320 reg: regInfo{ 14321 inputs: []inputInfo{ 14322 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14323 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14324 }, 14325 outputs: []outputInfo{ 14326 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14327 }, 14328 }, 14329 }, 14330 { 14331 name: "ADDconst", 14332 auxType: auxInt32, 14333 argLen: 1, 14334 asm: mips.AADDU, 14335 reg: regInfo{ 14336 inputs: []inputInfo{ 14337 {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 14338 }, 14339 outputs: []outputInfo{ 14340 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14341 }, 14342 }, 14343 }, 14344 { 14345 name: "SUB", 14346 argLen: 2, 14347 asm: mips.ASUBU, 14348 reg: regInfo{ 14349 inputs: []inputInfo{ 14350 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14351 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14352 }, 14353 outputs: []outputInfo{ 14354 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14355 }, 14356 }, 14357 }, 14358 { 14359 name: "SUBconst", 14360 auxType: auxInt32, 14361 argLen: 1, 14362 asm: mips.ASUBU, 14363 reg: regInfo{ 14364 inputs: []inputInfo{ 14365 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14366 }, 14367 outputs: []outputInfo{ 14368 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14369 }, 14370 }, 14371 }, 14372 { 14373 name: "MUL", 14374 argLen: 2, 14375 commutative: true, 14376 asm: mips.AMUL, 14377 reg: regInfo{ 14378 inputs: []inputInfo{ 14379 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14380 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14381 }, 14382 clobbers: 105553116266496, // HI LO 14383 outputs: []outputInfo{ 14384 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14385 }, 14386 }, 14387 }, 14388 { 14389 name: "MULT", 14390 argLen: 2, 14391 commutative: true, 14392 asm: mips.AMUL, 14393 reg: regInfo{ 14394 inputs: []inputInfo{ 14395 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14396 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14397 }, 14398 outputs: []outputInfo{ 14399 {0, 35184372088832}, // HI 14400 {1, 70368744177664}, // LO 14401 }, 14402 }, 14403 }, 14404 { 14405 name: "MULTU", 14406 argLen: 2, 14407 commutative: true, 14408 asm: mips.AMULU, 14409 reg: regInfo{ 14410 inputs: []inputInfo{ 14411 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14412 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14413 }, 14414 outputs: []outputInfo{ 14415 {0, 35184372088832}, // HI 14416 {1, 70368744177664}, // LO 14417 }, 14418 }, 14419 }, 14420 { 14421 name: "DIV", 14422 argLen: 2, 14423 asm: mips.ADIV, 14424 reg: regInfo{ 14425 inputs: []inputInfo{ 14426 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14427 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14428 }, 14429 outputs: []outputInfo{ 14430 {0, 35184372088832}, // HI 14431 {1, 70368744177664}, // LO 14432 }, 14433 }, 14434 }, 14435 { 14436 name: "DIVU", 14437 argLen: 2, 14438 asm: mips.ADIVU, 14439 reg: regInfo{ 14440 inputs: []inputInfo{ 14441 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14442 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14443 }, 14444 outputs: []outputInfo{ 14445 {0, 35184372088832}, // HI 14446 {1, 70368744177664}, // LO 14447 }, 14448 }, 14449 }, 14450 { 14451 name: "ADDF", 14452 argLen: 2, 14453 commutative: true, 14454 asm: mips.AADDF, 14455 reg: regInfo{ 14456 inputs: []inputInfo{ 14457 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14458 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14459 }, 14460 outputs: []outputInfo{ 14461 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14462 }, 14463 }, 14464 }, 14465 { 14466 name: "ADDD", 14467 argLen: 2, 14468 commutative: true, 14469 asm: mips.AADDD, 14470 reg: regInfo{ 14471 inputs: []inputInfo{ 14472 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14473 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14474 }, 14475 outputs: []outputInfo{ 14476 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14477 }, 14478 }, 14479 }, 14480 { 14481 name: "SUBF", 14482 argLen: 2, 14483 asm: mips.ASUBF, 14484 reg: regInfo{ 14485 inputs: []inputInfo{ 14486 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14487 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14488 }, 14489 outputs: []outputInfo{ 14490 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14491 }, 14492 }, 14493 }, 14494 { 14495 name: "SUBD", 14496 argLen: 2, 14497 asm: mips.ASUBD, 14498 reg: regInfo{ 14499 inputs: []inputInfo{ 14500 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14501 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14502 }, 14503 outputs: []outputInfo{ 14504 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14505 }, 14506 }, 14507 }, 14508 { 14509 name: "MULF", 14510 argLen: 2, 14511 commutative: true, 14512 asm: mips.AMULF, 14513 reg: regInfo{ 14514 inputs: []inputInfo{ 14515 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14516 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14517 }, 14518 outputs: []outputInfo{ 14519 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14520 }, 14521 }, 14522 }, 14523 { 14524 name: "MULD", 14525 argLen: 2, 14526 commutative: true, 14527 asm: mips.AMULD, 14528 reg: regInfo{ 14529 inputs: []inputInfo{ 14530 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14531 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14532 }, 14533 outputs: []outputInfo{ 14534 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14535 }, 14536 }, 14537 }, 14538 { 14539 name: "DIVF", 14540 argLen: 2, 14541 asm: mips.ADIVF, 14542 reg: regInfo{ 14543 inputs: []inputInfo{ 14544 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14545 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14546 }, 14547 outputs: []outputInfo{ 14548 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14549 }, 14550 }, 14551 }, 14552 { 14553 name: "DIVD", 14554 argLen: 2, 14555 asm: mips.ADIVD, 14556 reg: regInfo{ 14557 inputs: []inputInfo{ 14558 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14559 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14560 }, 14561 outputs: []outputInfo{ 14562 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14563 }, 14564 }, 14565 }, 14566 { 14567 name: "AND", 14568 argLen: 2, 14569 commutative: true, 14570 asm: mips.AAND, 14571 reg: regInfo{ 14572 inputs: []inputInfo{ 14573 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14574 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14575 }, 14576 outputs: []outputInfo{ 14577 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14578 }, 14579 }, 14580 }, 14581 { 14582 name: "ANDconst", 14583 auxType: auxInt32, 14584 argLen: 1, 14585 asm: mips.AAND, 14586 reg: regInfo{ 14587 inputs: []inputInfo{ 14588 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14589 }, 14590 outputs: []outputInfo{ 14591 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14592 }, 14593 }, 14594 }, 14595 { 14596 name: "OR", 14597 argLen: 2, 14598 commutative: true, 14599 asm: mips.AOR, 14600 reg: regInfo{ 14601 inputs: []inputInfo{ 14602 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14603 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14604 }, 14605 outputs: []outputInfo{ 14606 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14607 }, 14608 }, 14609 }, 14610 { 14611 name: "ORconst", 14612 auxType: auxInt32, 14613 argLen: 1, 14614 asm: mips.AOR, 14615 reg: regInfo{ 14616 inputs: []inputInfo{ 14617 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14618 }, 14619 outputs: []outputInfo{ 14620 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14621 }, 14622 }, 14623 }, 14624 { 14625 name: "XOR", 14626 argLen: 2, 14627 commutative: true, 14628 asm: mips.AXOR, 14629 reg: regInfo{ 14630 inputs: []inputInfo{ 14631 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14632 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14633 }, 14634 outputs: []outputInfo{ 14635 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14636 }, 14637 }, 14638 }, 14639 { 14640 name: "XORconst", 14641 auxType: auxInt32, 14642 argLen: 1, 14643 asm: mips.AXOR, 14644 reg: regInfo{ 14645 inputs: []inputInfo{ 14646 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14647 }, 14648 outputs: []outputInfo{ 14649 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14650 }, 14651 }, 14652 }, 14653 { 14654 name: "NOR", 14655 argLen: 2, 14656 commutative: true, 14657 asm: mips.ANOR, 14658 reg: regInfo{ 14659 inputs: []inputInfo{ 14660 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14661 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14662 }, 14663 outputs: []outputInfo{ 14664 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14665 }, 14666 }, 14667 }, 14668 { 14669 name: "NORconst", 14670 auxType: auxInt32, 14671 argLen: 1, 14672 asm: mips.ANOR, 14673 reg: regInfo{ 14674 inputs: []inputInfo{ 14675 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14676 }, 14677 outputs: []outputInfo{ 14678 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14679 }, 14680 }, 14681 }, 14682 { 14683 name: "NEG", 14684 argLen: 1, 14685 reg: regInfo{ 14686 inputs: []inputInfo{ 14687 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14688 }, 14689 outputs: []outputInfo{ 14690 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14691 }, 14692 }, 14693 }, 14694 { 14695 name: "NEGF", 14696 argLen: 1, 14697 asm: mips.ANEGF, 14698 reg: regInfo{ 14699 inputs: []inputInfo{ 14700 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14701 }, 14702 outputs: []outputInfo{ 14703 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14704 }, 14705 }, 14706 }, 14707 { 14708 name: "NEGD", 14709 argLen: 1, 14710 asm: mips.ANEGD, 14711 reg: regInfo{ 14712 inputs: []inputInfo{ 14713 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14714 }, 14715 outputs: []outputInfo{ 14716 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14717 }, 14718 }, 14719 }, 14720 { 14721 name: "SQRTD", 14722 argLen: 1, 14723 asm: mips.ASQRTD, 14724 reg: regInfo{ 14725 inputs: []inputInfo{ 14726 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14727 }, 14728 outputs: []outputInfo{ 14729 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14730 }, 14731 }, 14732 }, 14733 { 14734 name: "SLL", 14735 argLen: 2, 14736 asm: mips.ASLL, 14737 reg: regInfo{ 14738 inputs: []inputInfo{ 14739 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14740 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14741 }, 14742 outputs: []outputInfo{ 14743 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14744 }, 14745 }, 14746 }, 14747 { 14748 name: "SLLconst", 14749 auxType: auxInt32, 14750 argLen: 1, 14751 asm: mips.ASLL, 14752 reg: regInfo{ 14753 inputs: []inputInfo{ 14754 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14755 }, 14756 outputs: []outputInfo{ 14757 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14758 }, 14759 }, 14760 }, 14761 { 14762 name: "SRL", 14763 argLen: 2, 14764 asm: mips.ASRL, 14765 reg: regInfo{ 14766 inputs: []inputInfo{ 14767 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14768 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14769 }, 14770 outputs: []outputInfo{ 14771 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14772 }, 14773 }, 14774 }, 14775 { 14776 name: "SRLconst", 14777 auxType: auxInt32, 14778 argLen: 1, 14779 asm: mips.ASRL, 14780 reg: regInfo{ 14781 inputs: []inputInfo{ 14782 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14783 }, 14784 outputs: []outputInfo{ 14785 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14786 }, 14787 }, 14788 }, 14789 { 14790 name: "SRA", 14791 argLen: 2, 14792 asm: mips.ASRA, 14793 reg: regInfo{ 14794 inputs: []inputInfo{ 14795 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14796 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14797 }, 14798 outputs: []outputInfo{ 14799 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14800 }, 14801 }, 14802 }, 14803 { 14804 name: "SRAconst", 14805 auxType: auxInt32, 14806 argLen: 1, 14807 asm: mips.ASRA, 14808 reg: regInfo{ 14809 inputs: []inputInfo{ 14810 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14811 }, 14812 outputs: []outputInfo{ 14813 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14814 }, 14815 }, 14816 }, 14817 { 14818 name: "CLZ", 14819 argLen: 1, 14820 asm: mips.ACLZ, 14821 reg: regInfo{ 14822 inputs: []inputInfo{ 14823 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14824 }, 14825 outputs: []outputInfo{ 14826 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14827 }, 14828 }, 14829 }, 14830 { 14831 name: "SGT", 14832 argLen: 2, 14833 asm: mips.ASGT, 14834 reg: regInfo{ 14835 inputs: []inputInfo{ 14836 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14837 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14838 }, 14839 outputs: []outputInfo{ 14840 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14841 }, 14842 }, 14843 }, 14844 { 14845 name: "SGTconst", 14846 auxType: auxInt32, 14847 argLen: 1, 14848 asm: mips.ASGT, 14849 reg: regInfo{ 14850 inputs: []inputInfo{ 14851 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14852 }, 14853 outputs: []outputInfo{ 14854 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14855 }, 14856 }, 14857 }, 14858 { 14859 name: "SGTzero", 14860 argLen: 1, 14861 asm: mips.ASGT, 14862 reg: regInfo{ 14863 inputs: []inputInfo{ 14864 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14865 }, 14866 outputs: []outputInfo{ 14867 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14868 }, 14869 }, 14870 }, 14871 { 14872 name: "SGTU", 14873 argLen: 2, 14874 asm: mips.ASGTU, 14875 reg: regInfo{ 14876 inputs: []inputInfo{ 14877 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14878 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14879 }, 14880 outputs: []outputInfo{ 14881 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14882 }, 14883 }, 14884 }, 14885 { 14886 name: "SGTUconst", 14887 auxType: auxInt32, 14888 argLen: 1, 14889 asm: mips.ASGTU, 14890 reg: regInfo{ 14891 inputs: []inputInfo{ 14892 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14893 }, 14894 outputs: []outputInfo{ 14895 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14896 }, 14897 }, 14898 }, 14899 { 14900 name: "SGTUzero", 14901 argLen: 1, 14902 asm: mips.ASGTU, 14903 reg: regInfo{ 14904 inputs: []inputInfo{ 14905 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 14906 }, 14907 outputs: []outputInfo{ 14908 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14909 }, 14910 }, 14911 }, 14912 { 14913 name: "CMPEQF", 14914 argLen: 2, 14915 asm: mips.ACMPEQF, 14916 reg: regInfo{ 14917 inputs: []inputInfo{ 14918 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14919 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14920 }, 14921 }, 14922 }, 14923 { 14924 name: "CMPEQD", 14925 argLen: 2, 14926 asm: mips.ACMPEQD, 14927 reg: regInfo{ 14928 inputs: []inputInfo{ 14929 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14930 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14931 }, 14932 }, 14933 }, 14934 { 14935 name: "CMPGEF", 14936 argLen: 2, 14937 asm: mips.ACMPGEF, 14938 reg: regInfo{ 14939 inputs: []inputInfo{ 14940 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14941 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14942 }, 14943 }, 14944 }, 14945 { 14946 name: "CMPGED", 14947 argLen: 2, 14948 asm: mips.ACMPGED, 14949 reg: regInfo{ 14950 inputs: []inputInfo{ 14951 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14952 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14953 }, 14954 }, 14955 }, 14956 { 14957 name: "CMPGTF", 14958 argLen: 2, 14959 asm: mips.ACMPGTF, 14960 reg: regInfo{ 14961 inputs: []inputInfo{ 14962 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14963 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14964 }, 14965 }, 14966 }, 14967 { 14968 name: "CMPGTD", 14969 argLen: 2, 14970 asm: mips.ACMPGTD, 14971 reg: regInfo{ 14972 inputs: []inputInfo{ 14973 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14974 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14975 }, 14976 }, 14977 }, 14978 { 14979 name: "MOVWconst", 14980 auxType: auxInt32, 14981 argLen: 0, 14982 rematerializeable: true, 14983 asm: mips.AMOVW, 14984 reg: regInfo{ 14985 outputs: []outputInfo{ 14986 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 14987 }, 14988 }, 14989 }, 14990 { 14991 name: "MOVFconst", 14992 auxType: auxFloat32, 14993 argLen: 0, 14994 rematerializeable: true, 14995 asm: mips.AMOVF, 14996 reg: regInfo{ 14997 outputs: []outputInfo{ 14998 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 14999 }, 15000 }, 15001 }, 15002 { 15003 name: "MOVDconst", 15004 auxType: auxFloat64, 15005 argLen: 0, 15006 rematerializeable: true, 15007 asm: mips.AMOVD, 15008 reg: regInfo{ 15009 outputs: []outputInfo{ 15010 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15011 }, 15012 }, 15013 }, 15014 { 15015 name: "MOVWaddr", 15016 auxType: auxSymOff, 15017 argLen: 1, 15018 rematerializeable: true, 15019 symEffect: SymAddr, 15020 asm: mips.AMOVW, 15021 reg: regInfo{ 15022 inputs: []inputInfo{ 15023 {0, 140737555464192}, // SP SB 15024 }, 15025 outputs: []outputInfo{ 15026 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15027 }, 15028 }, 15029 }, 15030 { 15031 name: "MOVBload", 15032 auxType: auxSymOff, 15033 argLen: 2, 15034 faultOnNilArg0: true, 15035 symEffect: SymRead, 15036 asm: mips.AMOVB, 15037 reg: regInfo{ 15038 inputs: []inputInfo{ 15039 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15040 }, 15041 outputs: []outputInfo{ 15042 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15043 }, 15044 }, 15045 }, 15046 { 15047 name: "MOVBUload", 15048 auxType: auxSymOff, 15049 argLen: 2, 15050 faultOnNilArg0: true, 15051 symEffect: SymRead, 15052 asm: mips.AMOVBU, 15053 reg: regInfo{ 15054 inputs: []inputInfo{ 15055 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15056 }, 15057 outputs: []outputInfo{ 15058 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15059 }, 15060 }, 15061 }, 15062 { 15063 name: "MOVHload", 15064 auxType: auxSymOff, 15065 argLen: 2, 15066 faultOnNilArg0: true, 15067 symEffect: SymRead, 15068 asm: mips.AMOVH, 15069 reg: regInfo{ 15070 inputs: []inputInfo{ 15071 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15072 }, 15073 outputs: []outputInfo{ 15074 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15075 }, 15076 }, 15077 }, 15078 { 15079 name: "MOVHUload", 15080 auxType: auxSymOff, 15081 argLen: 2, 15082 faultOnNilArg0: true, 15083 symEffect: SymRead, 15084 asm: mips.AMOVHU, 15085 reg: regInfo{ 15086 inputs: []inputInfo{ 15087 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15088 }, 15089 outputs: []outputInfo{ 15090 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15091 }, 15092 }, 15093 }, 15094 { 15095 name: "MOVWload", 15096 auxType: auxSymOff, 15097 argLen: 2, 15098 faultOnNilArg0: true, 15099 symEffect: SymRead, 15100 asm: mips.AMOVW, 15101 reg: regInfo{ 15102 inputs: []inputInfo{ 15103 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15104 }, 15105 outputs: []outputInfo{ 15106 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15107 }, 15108 }, 15109 }, 15110 { 15111 name: "MOVFload", 15112 auxType: auxSymOff, 15113 argLen: 2, 15114 faultOnNilArg0: true, 15115 symEffect: SymRead, 15116 asm: mips.AMOVF, 15117 reg: regInfo{ 15118 inputs: []inputInfo{ 15119 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15120 }, 15121 outputs: []outputInfo{ 15122 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15123 }, 15124 }, 15125 }, 15126 { 15127 name: "MOVDload", 15128 auxType: auxSymOff, 15129 argLen: 2, 15130 faultOnNilArg0: true, 15131 symEffect: SymRead, 15132 asm: mips.AMOVD, 15133 reg: regInfo{ 15134 inputs: []inputInfo{ 15135 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15136 }, 15137 outputs: []outputInfo{ 15138 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15139 }, 15140 }, 15141 }, 15142 { 15143 name: "MOVBstore", 15144 auxType: auxSymOff, 15145 argLen: 3, 15146 faultOnNilArg0: true, 15147 symEffect: SymWrite, 15148 asm: mips.AMOVB, 15149 reg: regInfo{ 15150 inputs: []inputInfo{ 15151 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15152 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15153 }, 15154 }, 15155 }, 15156 { 15157 name: "MOVHstore", 15158 auxType: auxSymOff, 15159 argLen: 3, 15160 faultOnNilArg0: true, 15161 symEffect: SymWrite, 15162 asm: mips.AMOVH, 15163 reg: regInfo{ 15164 inputs: []inputInfo{ 15165 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15166 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15167 }, 15168 }, 15169 }, 15170 { 15171 name: "MOVWstore", 15172 auxType: auxSymOff, 15173 argLen: 3, 15174 faultOnNilArg0: true, 15175 symEffect: SymWrite, 15176 asm: mips.AMOVW, 15177 reg: regInfo{ 15178 inputs: []inputInfo{ 15179 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15180 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15181 }, 15182 }, 15183 }, 15184 { 15185 name: "MOVFstore", 15186 auxType: auxSymOff, 15187 argLen: 3, 15188 faultOnNilArg0: true, 15189 symEffect: SymWrite, 15190 asm: mips.AMOVF, 15191 reg: regInfo{ 15192 inputs: []inputInfo{ 15193 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15194 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15195 }, 15196 }, 15197 }, 15198 { 15199 name: "MOVDstore", 15200 auxType: auxSymOff, 15201 argLen: 3, 15202 faultOnNilArg0: true, 15203 symEffect: SymWrite, 15204 asm: mips.AMOVD, 15205 reg: regInfo{ 15206 inputs: []inputInfo{ 15207 {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15208 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15209 }, 15210 }, 15211 }, 15212 { 15213 name: "MOVBstorezero", 15214 auxType: auxSymOff, 15215 argLen: 2, 15216 faultOnNilArg0: true, 15217 symEffect: SymWrite, 15218 asm: mips.AMOVB, 15219 reg: regInfo{ 15220 inputs: []inputInfo{ 15221 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15222 }, 15223 }, 15224 }, 15225 { 15226 name: "MOVHstorezero", 15227 auxType: auxSymOff, 15228 argLen: 2, 15229 faultOnNilArg0: true, 15230 symEffect: SymWrite, 15231 asm: mips.AMOVH, 15232 reg: regInfo{ 15233 inputs: []inputInfo{ 15234 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15235 }, 15236 }, 15237 }, 15238 { 15239 name: "MOVWstorezero", 15240 auxType: auxSymOff, 15241 argLen: 2, 15242 faultOnNilArg0: true, 15243 symEffect: SymWrite, 15244 asm: mips.AMOVW, 15245 reg: regInfo{ 15246 inputs: []inputInfo{ 15247 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15248 }, 15249 }, 15250 }, 15251 { 15252 name: "MOVBreg", 15253 argLen: 1, 15254 asm: mips.AMOVB, 15255 reg: regInfo{ 15256 inputs: []inputInfo{ 15257 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15258 }, 15259 outputs: []outputInfo{ 15260 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15261 }, 15262 }, 15263 }, 15264 { 15265 name: "MOVBUreg", 15266 argLen: 1, 15267 asm: mips.AMOVBU, 15268 reg: regInfo{ 15269 inputs: []inputInfo{ 15270 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15271 }, 15272 outputs: []outputInfo{ 15273 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15274 }, 15275 }, 15276 }, 15277 { 15278 name: "MOVHreg", 15279 argLen: 1, 15280 asm: mips.AMOVH, 15281 reg: regInfo{ 15282 inputs: []inputInfo{ 15283 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15284 }, 15285 outputs: []outputInfo{ 15286 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15287 }, 15288 }, 15289 }, 15290 { 15291 name: "MOVHUreg", 15292 argLen: 1, 15293 asm: mips.AMOVHU, 15294 reg: regInfo{ 15295 inputs: []inputInfo{ 15296 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15297 }, 15298 outputs: []outputInfo{ 15299 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15300 }, 15301 }, 15302 }, 15303 { 15304 name: "MOVWreg", 15305 argLen: 1, 15306 asm: mips.AMOVW, 15307 reg: regInfo{ 15308 inputs: []inputInfo{ 15309 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15310 }, 15311 outputs: []outputInfo{ 15312 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15313 }, 15314 }, 15315 }, 15316 { 15317 name: "MOVWnop", 15318 argLen: 1, 15319 resultInArg0: true, 15320 reg: regInfo{ 15321 inputs: []inputInfo{ 15322 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15323 }, 15324 outputs: []outputInfo{ 15325 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15326 }, 15327 }, 15328 }, 15329 { 15330 name: "CMOVZ", 15331 argLen: 3, 15332 resultInArg0: true, 15333 asm: mips.ACMOVZ, 15334 reg: regInfo{ 15335 inputs: []inputInfo{ 15336 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15337 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15338 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15339 }, 15340 outputs: []outputInfo{ 15341 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15342 }, 15343 }, 15344 }, 15345 { 15346 name: "CMOVZzero", 15347 argLen: 2, 15348 resultInArg0: true, 15349 asm: mips.ACMOVZ, 15350 reg: regInfo{ 15351 inputs: []inputInfo{ 15352 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15353 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15354 }, 15355 outputs: []outputInfo{ 15356 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15357 }, 15358 }, 15359 }, 15360 { 15361 name: "MOVWF", 15362 argLen: 1, 15363 asm: mips.AMOVWF, 15364 reg: regInfo{ 15365 inputs: []inputInfo{ 15366 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15367 }, 15368 outputs: []outputInfo{ 15369 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15370 }, 15371 }, 15372 }, 15373 { 15374 name: "MOVWD", 15375 argLen: 1, 15376 asm: mips.AMOVWD, 15377 reg: regInfo{ 15378 inputs: []inputInfo{ 15379 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15380 }, 15381 outputs: []outputInfo{ 15382 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15383 }, 15384 }, 15385 }, 15386 { 15387 name: "TRUNCFW", 15388 argLen: 1, 15389 asm: mips.ATRUNCFW, 15390 reg: regInfo{ 15391 inputs: []inputInfo{ 15392 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15393 }, 15394 outputs: []outputInfo{ 15395 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15396 }, 15397 }, 15398 }, 15399 { 15400 name: "TRUNCDW", 15401 argLen: 1, 15402 asm: mips.ATRUNCDW, 15403 reg: regInfo{ 15404 inputs: []inputInfo{ 15405 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15406 }, 15407 outputs: []outputInfo{ 15408 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15409 }, 15410 }, 15411 }, 15412 { 15413 name: "MOVFD", 15414 argLen: 1, 15415 asm: mips.AMOVFD, 15416 reg: regInfo{ 15417 inputs: []inputInfo{ 15418 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15419 }, 15420 outputs: []outputInfo{ 15421 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15422 }, 15423 }, 15424 }, 15425 { 15426 name: "MOVDF", 15427 argLen: 1, 15428 asm: mips.AMOVDF, 15429 reg: regInfo{ 15430 inputs: []inputInfo{ 15431 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15432 }, 15433 outputs: []outputInfo{ 15434 {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 15435 }, 15436 }, 15437 }, 15438 { 15439 name: "CALLstatic", 15440 auxType: auxSymOff, 15441 argLen: 1, 15442 clobberFlags: true, 15443 call: true, 15444 symEffect: SymNone, 15445 reg: regInfo{ 15446 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15447 }, 15448 }, 15449 { 15450 name: "CALLclosure", 15451 auxType: auxInt64, 15452 argLen: 3, 15453 clobberFlags: true, 15454 call: true, 15455 reg: regInfo{ 15456 inputs: []inputInfo{ 15457 {1, 4194304}, // R22 15458 {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 15459 }, 15460 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15461 }, 15462 }, 15463 { 15464 name: "CALLinter", 15465 auxType: auxInt64, 15466 argLen: 2, 15467 clobberFlags: true, 15468 call: true, 15469 reg: regInfo{ 15470 inputs: []inputInfo{ 15471 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15472 }, 15473 clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO 15474 }, 15475 }, 15476 { 15477 name: "LoweredAtomicLoad", 15478 argLen: 2, 15479 faultOnNilArg0: true, 15480 reg: regInfo{ 15481 inputs: []inputInfo{ 15482 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15483 }, 15484 outputs: []outputInfo{ 15485 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15486 }, 15487 }, 15488 }, 15489 { 15490 name: "LoweredAtomicStore", 15491 argLen: 3, 15492 faultOnNilArg0: true, 15493 hasSideEffects: true, 15494 reg: regInfo{ 15495 inputs: []inputInfo{ 15496 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15497 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15498 }, 15499 }, 15500 }, 15501 { 15502 name: "LoweredAtomicStorezero", 15503 argLen: 2, 15504 faultOnNilArg0: true, 15505 hasSideEffects: true, 15506 reg: regInfo{ 15507 inputs: []inputInfo{ 15508 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15509 }, 15510 }, 15511 }, 15512 { 15513 name: "LoweredAtomicExchange", 15514 argLen: 3, 15515 resultNotInArgs: true, 15516 faultOnNilArg0: true, 15517 hasSideEffects: true, 15518 reg: regInfo{ 15519 inputs: []inputInfo{ 15520 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15521 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15522 }, 15523 outputs: []outputInfo{ 15524 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15525 }, 15526 }, 15527 }, 15528 { 15529 name: "LoweredAtomicAdd", 15530 argLen: 3, 15531 resultNotInArgs: true, 15532 faultOnNilArg0: true, 15533 hasSideEffects: true, 15534 reg: regInfo{ 15535 inputs: []inputInfo{ 15536 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15537 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15538 }, 15539 outputs: []outputInfo{ 15540 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15541 }, 15542 }, 15543 }, 15544 { 15545 name: "LoweredAtomicAddconst", 15546 auxType: auxInt32, 15547 argLen: 2, 15548 resultNotInArgs: true, 15549 faultOnNilArg0: true, 15550 hasSideEffects: true, 15551 reg: regInfo{ 15552 inputs: []inputInfo{ 15553 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15554 }, 15555 outputs: []outputInfo{ 15556 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15557 }, 15558 }, 15559 }, 15560 { 15561 name: "LoweredAtomicCas", 15562 argLen: 4, 15563 resultNotInArgs: true, 15564 faultOnNilArg0: true, 15565 hasSideEffects: true, 15566 reg: regInfo{ 15567 inputs: []inputInfo{ 15568 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15569 {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15570 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15571 }, 15572 outputs: []outputInfo{ 15573 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15574 }, 15575 }, 15576 }, 15577 { 15578 name: "LoweredAtomicAnd", 15579 argLen: 3, 15580 faultOnNilArg0: true, 15581 hasSideEffects: true, 15582 asm: mips.AAND, 15583 reg: regInfo{ 15584 inputs: []inputInfo{ 15585 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15586 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15587 }, 15588 }, 15589 }, 15590 { 15591 name: "LoweredAtomicOr", 15592 argLen: 3, 15593 faultOnNilArg0: true, 15594 hasSideEffects: true, 15595 asm: mips.AOR, 15596 reg: regInfo{ 15597 inputs: []inputInfo{ 15598 {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15599 {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB 15600 }, 15601 }, 15602 }, 15603 { 15604 name: "LoweredZero", 15605 auxType: auxInt32, 15606 argLen: 3, 15607 faultOnNilArg0: true, 15608 reg: regInfo{ 15609 inputs: []inputInfo{ 15610 {0, 2}, // R1 15611 {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15612 }, 15613 clobbers: 2, // R1 15614 }, 15615 }, 15616 { 15617 name: "LoweredMove", 15618 auxType: auxInt32, 15619 argLen: 4, 15620 faultOnNilArg0: true, 15621 faultOnNilArg1: true, 15622 reg: regInfo{ 15623 inputs: []inputInfo{ 15624 {0, 4}, // R2 15625 {1, 2}, // R1 15626 {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15627 }, 15628 clobbers: 6, // R1 R2 15629 }, 15630 }, 15631 { 15632 name: "LoweredNilCheck", 15633 argLen: 2, 15634 nilCheck: true, 15635 faultOnNilArg0: true, 15636 reg: regInfo{ 15637 inputs: []inputInfo{ 15638 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15639 }, 15640 }, 15641 }, 15642 { 15643 name: "FPFlagTrue", 15644 argLen: 1, 15645 reg: regInfo{ 15646 outputs: []outputInfo{ 15647 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15648 }, 15649 }, 15650 }, 15651 { 15652 name: "FPFlagFalse", 15653 argLen: 1, 15654 reg: regInfo{ 15655 outputs: []outputInfo{ 15656 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15657 }, 15658 }, 15659 }, 15660 { 15661 name: "LoweredGetClosurePtr", 15662 argLen: 0, 15663 reg: regInfo{ 15664 outputs: []outputInfo{ 15665 {0, 4194304}, // R22 15666 }, 15667 }, 15668 }, 15669 { 15670 name: "LoweredGetCallerSP", 15671 argLen: 0, 15672 rematerializeable: true, 15673 reg: regInfo{ 15674 outputs: []outputInfo{ 15675 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15676 }, 15677 }, 15678 }, 15679 { 15680 name: "MOVWconvert", 15681 argLen: 2, 15682 asm: mips.AMOVW, 15683 reg: regInfo{ 15684 inputs: []inputInfo{ 15685 {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 15686 }, 15687 outputs: []outputInfo{ 15688 {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 15689 }, 15690 }, 15691 }, 15692 15693 { 15694 name: "ADDV", 15695 argLen: 2, 15696 commutative: true, 15697 asm: mips.AADDVU, 15698 reg: regInfo{ 15699 inputs: []inputInfo{ 15700 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15701 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15702 }, 15703 outputs: []outputInfo{ 15704 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15705 }, 15706 }, 15707 }, 15708 { 15709 name: "ADDVconst", 15710 auxType: auxInt64, 15711 argLen: 1, 15712 asm: mips.AADDVU, 15713 reg: regInfo{ 15714 inputs: []inputInfo{ 15715 {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 15716 }, 15717 outputs: []outputInfo{ 15718 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15719 }, 15720 }, 15721 }, 15722 { 15723 name: "SUBV", 15724 argLen: 2, 15725 asm: mips.ASUBVU, 15726 reg: regInfo{ 15727 inputs: []inputInfo{ 15728 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15729 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15730 }, 15731 outputs: []outputInfo{ 15732 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15733 }, 15734 }, 15735 }, 15736 { 15737 name: "SUBVconst", 15738 auxType: auxInt64, 15739 argLen: 1, 15740 asm: mips.ASUBVU, 15741 reg: regInfo{ 15742 inputs: []inputInfo{ 15743 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15744 }, 15745 outputs: []outputInfo{ 15746 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15747 }, 15748 }, 15749 }, 15750 { 15751 name: "MULV", 15752 argLen: 2, 15753 commutative: true, 15754 asm: mips.AMULV, 15755 reg: regInfo{ 15756 inputs: []inputInfo{ 15757 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15758 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15759 }, 15760 outputs: []outputInfo{ 15761 {0, 1152921504606846976}, // HI 15762 {1, 2305843009213693952}, // LO 15763 }, 15764 }, 15765 }, 15766 { 15767 name: "MULVU", 15768 argLen: 2, 15769 commutative: true, 15770 asm: mips.AMULVU, 15771 reg: regInfo{ 15772 inputs: []inputInfo{ 15773 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15774 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15775 }, 15776 outputs: []outputInfo{ 15777 {0, 1152921504606846976}, // HI 15778 {1, 2305843009213693952}, // LO 15779 }, 15780 }, 15781 }, 15782 { 15783 name: "DIVV", 15784 argLen: 2, 15785 asm: mips.ADIVV, 15786 reg: regInfo{ 15787 inputs: []inputInfo{ 15788 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15789 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15790 }, 15791 outputs: []outputInfo{ 15792 {0, 1152921504606846976}, // HI 15793 {1, 2305843009213693952}, // LO 15794 }, 15795 }, 15796 }, 15797 { 15798 name: "DIVVU", 15799 argLen: 2, 15800 asm: mips.ADIVVU, 15801 reg: regInfo{ 15802 inputs: []inputInfo{ 15803 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15804 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15805 }, 15806 outputs: []outputInfo{ 15807 {0, 1152921504606846976}, // HI 15808 {1, 2305843009213693952}, // LO 15809 }, 15810 }, 15811 }, 15812 { 15813 name: "ADDF", 15814 argLen: 2, 15815 commutative: true, 15816 asm: mips.AADDF, 15817 reg: regInfo{ 15818 inputs: []inputInfo{ 15819 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15820 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15821 }, 15822 outputs: []outputInfo{ 15823 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15824 }, 15825 }, 15826 }, 15827 { 15828 name: "ADDD", 15829 argLen: 2, 15830 commutative: true, 15831 asm: mips.AADDD, 15832 reg: regInfo{ 15833 inputs: []inputInfo{ 15834 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15835 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15836 }, 15837 outputs: []outputInfo{ 15838 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15839 }, 15840 }, 15841 }, 15842 { 15843 name: "SUBF", 15844 argLen: 2, 15845 asm: mips.ASUBF, 15846 reg: regInfo{ 15847 inputs: []inputInfo{ 15848 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15849 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15850 }, 15851 outputs: []outputInfo{ 15852 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15853 }, 15854 }, 15855 }, 15856 { 15857 name: "SUBD", 15858 argLen: 2, 15859 asm: mips.ASUBD, 15860 reg: regInfo{ 15861 inputs: []inputInfo{ 15862 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15863 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15864 }, 15865 outputs: []outputInfo{ 15866 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15867 }, 15868 }, 15869 }, 15870 { 15871 name: "MULF", 15872 argLen: 2, 15873 commutative: true, 15874 asm: mips.AMULF, 15875 reg: regInfo{ 15876 inputs: []inputInfo{ 15877 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15878 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15879 }, 15880 outputs: []outputInfo{ 15881 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15882 }, 15883 }, 15884 }, 15885 { 15886 name: "MULD", 15887 argLen: 2, 15888 commutative: true, 15889 asm: mips.AMULD, 15890 reg: regInfo{ 15891 inputs: []inputInfo{ 15892 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15893 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15894 }, 15895 outputs: []outputInfo{ 15896 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15897 }, 15898 }, 15899 }, 15900 { 15901 name: "DIVF", 15902 argLen: 2, 15903 asm: mips.ADIVF, 15904 reg: regInfo{ 15905 inputs: []inputInfo{ 15906 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15907 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15908 }, 15909 outputs: []outputInfo{ 15910 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15911 }, 15912 }, 15913 }, 15914 { 15915 name: "DIVD", 15916 argLen: 2, 15917 asm: mips.ADIVD, 15918 reg: regInfo{ 15919 inputs: []inputInfo{ 15920 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15921 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15922 }, 15923 outputs: []outputInfo{ 15924 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 15925 }, 15926 }, 15927 }, 15928 { 15929 name: "AND", 15930 argLen: 2, 15931 commutative: true, 15932 asm: mips.AAND, 15933 reg: regInfo{ 15934 inputs: []inputInfo{ 15935 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15936 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15937 }, 15938 outputs: []outputInfo{ 15939 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15940 }, 15941 }, 15942 }, 15943 { 15944 name: "ANDconst", 15945 auxType: auxInt64, 15946 argLen: 1, 15947 asm: mips.AAND, 15948 reg: regInfo{ 15949 inputs: []inputInfo{ 15950 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15951 }, 15952 outputs: []outputInfo{ 15953 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15954 }, 15955 }, 15956 }, 15957 { 15958 name: "OR", 15959 argLen: 2, 15960 commutative: true, 15961 asm: mips.AOR, 15962 reg: regInfo{ 15963 inputs: []inputInfo{ 15964 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15965 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15966 }, 15967 outputs: []outputInfo{ 15968 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15969 }, 15970 }, 15971 }, 15972 { 15973 name: "ORconst", 15974 auxType: auxInt64, 15975 argLen: 1, 15976 asm: mips.AOR, 15977 reg: regInfo{ 15978 inputs: []inputInfo{ 15979 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15980 }, 15981 outputs: []outputInfo{ 15982 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15983 }, 15984 }, 15985 }, 15986 { 15987 name: "XOR", 15988 argLen: 2, 15989 commutative: true, 15990 asm: mips.AXOR, 15991 reg: regInfo{ 15992 inputs: []inputInfo{ 15993 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15994 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 15995 }, 15996 outputs: []outputInfo{ 15997 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 15998 }, 15999 }, 16000 }, 16001 { 16002 name: "XORconst", 16003 auxType: auxInt64, 16004 argLen: 1, 16005 asm: mips.AXOR, 16006 reg: regInfo{ 16007 inputs: []inputInfo{ 16008 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16009 }, 16010 outputs: []outputInfo{ 16011 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16012 }, 16013 }, 16014 }, 16015 { 16016 name: "NOR", 16017 argLen: 2, 16018 commutative: true, 16019 asm: mips.ANOR, 16020 reg: regInfo{ 16021 inputs: []inputInfo{ 16022 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16023 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16024 }, 16025 outputs: []outputInfo{ 16026 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16027 }, 16028 }, 16029 }, 16030 { 16031 name: "NORconst", 16032 auxType: auxInt64, 16033 argLen: 1, 16034 asm: mips.ANOR, 16035 reg: regInfo{ 16036 inputs: []inputInfo{ 16037 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16038 }, 16039 outputs: []outputInfo{ 16040 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16041 }, 16042 }, 16043 }, 16044 { 16045 name: "NEGV", 16046 argLen: 1, 16047 reg: regInfo{ 16048 inputs: []inputInfo{ 16049 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16050 }, 16051 outputs: []outputInfo{ 16052 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16053 }, 16054 }, 16055 }, 16056 { 16057 name: "NEGF", 16058 argLen: 1, 16059 asm: mips.ANEGF, 16060 reg: regInfo{ 16061 inputs: []inputInfo{ 16062 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16063 }, 16064 outputs: []outputInfo{ 16065 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16066 }, 16067 }, 16068 }, 16069 { 16070 name: "NEGD", 16071 argLen: 1, 16072 asm: mips.ANEGD, 16073 reg: regInfo{ 16074 inputs: []inputInfo{ 16075 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16076 }, 16077 outputs: []outputInfo{ 16078 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16079 }, 16080 }, 16081 }, 16082 { 16083 name: "SLLV", 16084 argLen: 2, 16085 asm: mips.ASLLV, 16086 reg: regInfo{ 16087 inputs: []inputInfo{ 16088 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16089 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16090 }, 16091 outputs: []outputInfo{ 16092 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16093 }, 16094 }, 16095 }, 16096 { 16097 name: "SLLVconst", 16098 auxType: auxInt64, 16099 argLen: 1, 16100 asm: mips.ASLLV, 16101 reg: regInfo{ 16102 inputs: []inputInfo{ 16103 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16104 }, 16105 outputs: []outputInfo{ 16106 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16107 }, 16108 }, 16109 }, 16110 { 16111 name: "SRLV", 16112 argLen: 2, 16113 asm: mips.ASRLV, 16114 reg: regInfo{ 16115 inputs: []inputInfo{ 16116 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16117 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16118 }, 16119 outputs: []outputInfo{ 16120 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16121 }, 16122 }, 16123 }, 16124 { 16125 name: "SRLVconst", 16126 auxType: auxInt64, 16127 argLen: 1, 16128 asm: mips.ASRLV, 16129 reg: regInfo{ 16130 inputs: []inputInfo{ 16131 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16132 }, 16133 outputs: []outputInfo{ 16134 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16135 }, 16136 }, 16137 }, 16138 { 16139 name: "SRAV", 16140 argLen: 2, 16141 asm: mips.ASRAV, 16142 reg: regInfo{ 16143 inputs: []inputInfo{ 16144 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16145 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16146 }, 16147 outputs: []outputInfo{ 16148 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16149 }, 16150 }, 16151 }, 16152 { 16153 name: "SRAVconst", 16154 auxType: auxInt64, 16155 argLen: 1, 16156 asm: mips.ASRAV, 16157 reg: regInfo{ 16158 inputs: []inputInfo{ 16159 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16160 }, 16161 outputs: []outputInfo{ 16162 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16163 }, 16164 }, 16165 }, 16166 { 16167 name: "SGT", 16168 argLen: 2, 16169 asm: mips.ASGT, 16170 reg: regInfo{ 16171 inputs: []inputInfo{ 16172 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16173 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16174 }, 16175 outputs: []outputInfo{ 16176 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16177 }, 16178 }, 16179 }, 16180 { 16181 name: "SGTconst", 16182 auxType: auxInt64, 16183 argLen: 1, 16184 asm: mips.ASGT, 16185 reg: regInfo{ 16186 inputs: []inputInfo{ 16187 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16188 }, 16189 outputs: []outputInfo{ 16190 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16191 }, 16192 }, 16193 }, 16194 { 16195 name: "SGTU", 16196 argLen: 2, 16197 asm: mips.ASGTU, 16198 reg: regInfo{ 16199 inputs: []inputInfo{ 16200 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16201 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16202 }, 16203 outputs: []outputInfo{ 16204 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16205 }, 16206 }, 16207 }, 16208 { 16209 name: "SGTUconst", 16210 auxType: auxInt64, 16211 argLen: 1, 16212 asm: mips.ASGTU, 16213 reg: regInfo{ 16214 inputs: []inputInfo{ 16215 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16216 }, 16217 outputs: []outputInfo{ 16218 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16219 }, 16220 }, 16221 }, 16222 { 16223 name: "CMPEQF", 16224 argLen: 2, 16225 asm: mips.ACMPEQF, 16226 reg: regInfo{ 16227 inputs: []inputInfo{ 16228 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16229 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16230 }, 16231 }, 16232 }, 16233 { 16234 name: "CMPEQD", 16235 argLen: 2, 16236 asm: mips.ACMPEQD, 16237 reg: regInfo{ 16238 inputs: []inputInfo{ 16239 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16240 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16241 }, 16242 }, 16243 }, 16244 { 16245 name: "CMPGEF", 16246 argLen: 2, 16247 asm: mips.ACMPGEF, 16248 reg: regInfo{ 16249 inputs: []inputInfo{ 16250 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16251 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16252 }, 16253 }, 16254 }, 16255 { 16256 name: "CMPGED", 16257 argLen: 2, 16258 asm: mips.ACMPGED, 16259 reg: regInfo{ 16260 inputs: []inputInfo{ 16261 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16262 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16263 }, 16264 }, 16265 }, 16266 { 16267 name: "CMPGTF", 16268 argLen: 2, 16269 asm: mips.ACMPGTF, 16270 reg: regInfo{ 16271 inputs: []inputInfo{ 16272 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16273 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16274 }, 16275 }, 16276 }, 16277 { 16278 name: "CMPGTD", 16279 argLen: 2, 16280 asm: mips.ACMPGTD, 16281 reg: regInfo{ 16282 inputs: []inputInfo{ 16283 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16284 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16285 }, 16286 }, 16287 }, 16288 { 16289 name: "MOVVconst", 16290 auxType: auxInt64, 16291 argLen: 0, 16292 rematerializeable: true, 16293 asm: mips.AMOVV, 16294 reg: regInfo{ 16295 outputs: []outputInfo{ 16296 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16297 }, 16298 }, 16299 }, 16300 { 16301 name: "MOVFconst", 16302 auxType: auxFloat64, 16303 argLen: 0, 16304 rematerializeable: true, 16305 asm: mips.AMOVF, 16306 reg: regInfo{ 16307 outputs: []outputInfo{ 16308 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16309 }, 16310 }, 16311 }, 16312 { 16313 name: "MOVDconst", 16314 auxType: auxFloat64, 16315 argLen: 0, 16316 rematerializeable: true, 16317 asm: mips.AMOVD, 16318 reg: regInfo{ 16319 outputs: []outputInfo{ 16320 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16321 }, 16322 }, 16323 }, 16324 { 16325 name: "MOVVaddr", 16326 auxType: auxSymOff, 16327 argLen: 1, 16328 rematerializeable: true, 16329 symEffect: SymAddr, 16330 asm: mips.AMOVV, 16331 reg: regInfo{ 16332 inputs: []inputInfo{ 16333 {0, 4611686018460942336}, // SP SB 16334 }, 16335 outputs: []outputInfo{ 16336 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16337 }, 16338 }, 16339 }, 16340 { 16341 name: "MOVBload", 16342 auxType: auxSymOff, 16343 argLen: 2, 16344 faultOnNilArg0: true, 16345 symEffect: SymRead, 16346 asm: mips.AMOVB, 16347 reg: regInfo{ 16348 inputs: []inputInfo{ 16349 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16350 }, 16351 outputs: []outputInfo{ 16352 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16353 }, 16354 }, 16355 }, 16356 { 16357 name: "MOVBUload", 16358 auxType: auxSymOff, 16359 argLen: 2, 16360 faultOnNilArg0: true, 16361 symEffect: SymRead, 16362 asm: mips.AMOVBU, 16363 reg: regInfo{ 16364 inputs: []inputInfo{ 16365 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16366 }, 16367 outputs: []outputInfo{ 16368 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16369 }, 16370 }, 16371 }, 16372 { 16373 name: "MOVHload", 16374 auxType: auxSymOff, 16375 argLen: 2, 16376 faultOnNilArg0: true, 16377 symEffect: SymRead, 16378 asm: mips.AMOVH, 16379 reg: regInfo{ 16380 inputs: []inputInfo{ 16381 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16382 }, 16383 outputs: []outputInfo{ 16384 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16385 }, 16386 }, 16387 }, 16388 { 16389 name: "MOVHUload", 16390 auxType: auxSymOff, 16391 argLen: 2, 16392 faultOnNilArg0: true, 16393 symEffect: SymRead, 16394 asm: mips.AMOVHU, 16395 reg: regInfo{ 16396 inputs: []inputInfo{ 16397 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16398 }, 16399 outputs: []outputInfo{ 16400 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16401 }, 16402 }, 16403 }, 16404 { 16405 name: "MOVWload", 16406 auxType: auxSymOff, 16407 argLen: 2, 16408 faultOnNilArg0: true, 16409 symEffect: SymRead, 16410 asm: mips.AMOVW, 16411 reg: regInfo{ 16412 inputs: []inputInfo{ 16413 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16414 }, 16415 outputs: []outputInfo{ 16416 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16417 }, 16418 }, 16419 }, 16420 { 16421 name: "MOVWUload", 16422 auxType: auxSymOff, 16423 argLen: 2, 16424 faultOnNilArg0: true, 16425 symEffect: SymRead, 16426 asm: mips.AMOVWU, 16427 reg: regInfo{ 16428 inputs: []inputInfo{ 16429 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16430 }, 16431 outputs: []outputInfo{ 16432 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16433 }, 16434 }, 16435 }, 16436 { 16437 name: "MOVVload", 16438 auxType: auxSymOff, 16439 argLen: 2, 16440 faultOnNilArg0: true, 16441 symEffect: SymRead, 16442 asm: mips.AMOVV, 16443 reg: regInfo{ 16444 inputs: []inputInfo{ 16445 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16446 }, 16447 outputs: []outputInfo{ 16448 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16449 }, 16450 }, 16451 }, 16452 { 16453 name: "MOVFload", 16454 auxType: auxSymOff, 16455 argLen: 2, 16456 faultOnNilArg0: true, 16457 symEffect: SymRead, 16458 asm: mips.AMOVF, 16459 reg: regInfo{ 16460 inputs: []inputInfo{ 16461 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16462 }, 16463 outputs: []outputInfo{ 16464 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16465 }, 16466 }, 16467 }, 16468 { 16469 name: "MOVDload", 16470 auxType: auxSymOff, 16471 argLen: 2, 16472 faultOnNilArg0: true, 16473 symEffect: SymRead, 16474 asm: mips.AMOVD, 16475 reg: regInfo{ 16476 inputs: []inputInfo{ 16477 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16478 }, 16479 outputs: []outputInfo{ 16480 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16481 }, 16482 }, 16483 }, 16484 { 16485 name: "MOVBstore", 16486 auxType: auxSymOff, 16487 argLen: 3, 16488 faultOnNilArg0: true, 16489 symEffect: SymWrite, 16490 asm: mips.AMOVB, 16491 reg: regInfo{ 16492 inputs: []inputInfo{ 16493 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16494 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16495 }, 16496 }, 16497 }, 16498 { 16499 name: "MOVHstore", 16500 auxType: auxSymOff, 16501 argLen: 3, 16502 faultOnNilArg0: true, 16503 symEffect: SymWrite, 16504 asm: mips.AMOVH, 16505 reg: regInfo{ 16506 inputs: []inputInfo{ 16507 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16508 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16509 }, 16510 }, 16511 }, 16512 { 16513 name: "MOVWstore", 16514 auxType: auxSymOff, 16515 argLen: 3, 16516 faultOnNilArg0: true, 16517 symEffect: SymWrite, 16518 asm: mips.AMOVW, 16519 reg: regInfo{ 16520 inputs: []inputInfo{ 16521 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16522 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16523 }, 16524 }, 16525 }, 16526 { 16527 name: "MOVVstore", 16528 auxType: auxSymOff, 16529 argLen: 3, 16530 faultOnNilArg0: true, 16531 symEffect: SymWrite, 16532 asm: mips.AMOVV, 16533 reg: regInfo{ 16534 inputs: []inputInfo{ 16535 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16536 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16537 }, 16538 }, 16539 }, 16540 { 16541 name: "MOVFstore", 16542 auxType: auxSymOff, 16543 argLen: 3, 16544 faultOnNilArg0: true, 16545 symEffect: SymWrite, 16546 asm: mips.AMOVF, 16547 reg: regInfo{ 16548 inputs: []inputInfo{ 16549 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16550 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16551 }, 16552 }, 16553 }, 16554 { 16555 name: "MOVDstore", 16556 auxType: auxSymOff, 16557 argLen: 3, 16558 faultOnNilArg0: true, 16559 symEffect: SymWrite, 16560 asm: mips.AMOVD, 16561 reg: regInfo{ 16562 inputs: []inputInfo{ 16563 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16564 {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16565 }, 16566 }, 16567 }, 16568 { 16569 name: "MOVBstorezero", 16570 auxType: auxSymOff, 16571 argLen: 2, 16572 faultOnNilArg0: true, 16573 symEffect: SymWrite, 16574 asm: mips.AMOVB, 16575 reg: regInfo{ 16576 inputs: []inputInfo{ 16577 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16578 }, 16579 }, 16580 }, 16581 { 16582 name: "MOVHstorezero", 16583 auxType: auxSymOff, 16584 argLen: 2, 16585 faultOnNilArg0: true, 16586 symEffect: SymWrite, 16587 asm: mips.AMOVH, 16588 reg: regInfo{ 16589 inputs: []inputInfo{ 16590 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16591 }, 16592 }, 16593 }, 16594 { 16595 name: "MOVWstorezero", 16596 auxType: auxSymOff, 16597 argLen: 2, 16598 faultOnNilArg0: true, 16599 symEffect: SymWrite, 16600 asm: mips.AMOVW, 16601 reg: regInfo{ 16602 inputs: []inputInfo{ 16603 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16604 }, 16605 }, 16606 }, 16607 { 16608 name: "MOVVstorezero", 16609 auxType: auxSymOff, 16610 argLen: 2, 16611 faultOnNilArg0: true, 16612 symEffect: SymWrite, 16613 asm: mips.AMOVV, 16614 reg: regInfo{ 16615 inputs: []inputInfo{ 16616 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16617 }, 16618 }, 16619 }, 16620 { 16621 name: "MOVBreg", 16622 argLen: 1, 16623 asm: mips.AMOVB, 16624 reg: regInfo{ 16625 inputs: []inputInfo{ 16626 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16627 }, 16628 outputs: []outputInfo{ 16629 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16630 }, 16631 }, 16632 }, 16633 { 16634 name: "MOVBUreg", 16635 argLen: 1, 16636 asm: mips.AMOVBU, 16637 reg: regInfo{ 16638 inputs: []inputInfo{ 16639 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16640 }, 16641 outputs: []outputInfo{ 16642 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16643 }, 16644 }, 16645 }, 16646 { 16647 name: "MOVHreg", 16648 argLen: 1, 16649 asm: mips.AMOVH, 16650 reg: regInfo{ 16651 inputs: []inputInfo{ 16652 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16653 }, 16654 outputs: []outputInfo{ 16655 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16656 }, 16657 }, 16658 }, 16659 { 16660 name: "MOVHUreg", 16661 argLen: 1, 16662 asm: mips.AMOVHU, 16663 reg: regInfo{ 16664 inputs: []inputInfo{ 16665 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16666 }, 16667 outputs: []outputInfo{ 16668 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16669 }, 16670 }, 16671 }, 16672 { 16673 name: "MOVWreg", 16674 argLen: 1, 16675 asm: mips.AMOVW, 16676 reg: regInfo{ 16677 inputs: []inputInfo{ 16678 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16679 }, 16680 outputs: []outputInfo{ 16681 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16682 }, 16683 }, 16684 }, 16685 { 16686 name: "MOVWUreg", 16687 argLen: 1, 16688 asm: mips.AMOVWU, 16689 reg: regInfo{ 16690 inputs: []inputInfo{ 16691 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16692 }, 16693 outputs: []outputInfo{ 16694 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16695 }, 16696 }, 16697 }, 16698 { 16699 name: "MOVVreg", 16700 argLen: 1, 16701 asm: mips.AMOVV, 16702 reg: regInfo{ 16703 inputs: []inputInfo{ 16704 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16705 }, 16706 outputs: []outputInfo{ 16707 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16708 }, 16709 }, 16710 }, 16711 { 16712 name: "MOVVnop", 16713 argLen: 1, 16714 resultInArg0: true, 16715 reg: regInfo{ 16716 inputs: []inputInfo{ 16717 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16718 }, 16719 outputs: []outputInfo{ 16720 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16721 }, 16722 }, 16723 }, 16724 { 16725 name: "MOVWF", 16726 argLen: 1, 16727 asm: mips.AMOVWF, 16728 reg: regInfo{ 16729 inputs: []inputInfo{ 16730 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16731 }, 16732 outputs: []outputInfo{ 16733 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16734 }, 16735 }, 16736 }, 16737 { 16738 name: "MOVWD", 16739 argLen: 1, 16740 asm: mips.AMOVWD, 16741 reg: regInfo{ 16742 inputs: []inputInfo{ 16743 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16744 }, 16745 outputs: []outputInfo{ 16746 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16747 }, 16748 }, 16749 }, 16750 { 16751 name: "MOVVF", 16752 argLen: 1, 16753 asm: mips.AMOVVF, 16754 reg: regInfo{ 16755 inputs: []inputInfo{ 16756 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16757 }, 16758 outputs: []outputInfo{ 16759 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16760 }, 16761 }, 16762 }, 16763 { 16764 name: "MOVVD", 16765 argLen: 1, 16766 asm: mips.AMOVVD, 16767 reg: regInfo{ 16768 inputs: []inputInfo{ 16769 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16770 }, 16771 outputs: []outputInfo{ 16772 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16773 }, 16774 }, 16775 }, 16776 { 16777 name: "TRUNCFW", 16778 argLen: 1, 16779 asm: mips.ATRUNCFW, 16780 reg: regInfo{ 16781 inputs: []inputInfo{ 16782 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16783 }, 16784 outputs: []outputInfo{ 16785 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16786 }, 16787 }, 16788 }, 16789 { 16790 name: "TRUNCDW", 16791 argLen: 1, 16792 asm: mips.ATRUNCDW, 16793 reg: regInfo{ 16794 inputs: []inputInfo{ 16795 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16796 }, 16797 outputs: []outputInfo{ 16798 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16799 }, 16800 }, 16801 }, 16802 { 16803 name: "TRUNCFV", 16804 argLen: 1, 16805 asm: mips.ATRUNCFV, 16806 reg: regInfo{ 16807 inputs: []inputInfo{ 16808 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16809 }, 16810 outputs: []outputInfo{ 16811 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16812 }, 16813 }, 16814 }, 16815 { 16816 name: "TRUNCDV", 16817 argLen: 1, 16818 asm: mips.ATRUNCDV, 16819 reg: regInfo{ 16820 inputs: []inputInfo{ 16821 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16822 }, 16823 outputs: []outputInfo{ 16824 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16825 }, 16826 }, 16827 }, 16828 { 16829 name: "MOVFD", 16830 argLen: 1, 16831 asm: mips.AMOVFD, 16832 reg: regInfo{ 16833 inputs: []inputInfo{ 16834 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16835 }, 16836 outputs: []outputInfo{ 16837 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16838 }, 16839 }, 16840 }, 16841 { 16842 name: "MOVDF", 16843 argLen: 1, 16844 asm: mips.AMOVDF, 16845 reg: regInfo{ 16846 inputs: []inputInfo{ 16847 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16848 }, 16849 outputs: []outputInfo{ 16850 {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 16851 }, 16852 }, 16853 }, 16854 { 16855 name: "CALLstatic", 16856 auxType: auxSymOff, 16857 argLen: 1, 16858 clobberFlags: true, 16859 call: true, 16860 symEffect: SymNone, 16861 reg: regInfo{ 16862 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16863 }, 16864 }, 16865 { 16866 name: "CALLclosure", 16867 auxType: auxInt64, 16868 argLen: 3, 16869 clobberFlags: true, 16870 call: true, 16871 reg: regInfo{ 16872 inputs: []inputInfo{ 16873 {1, 4194304}, // R22 16874 {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 16875 }, 16876 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16877 }, 16878 }, 16879 { 16880 name: "CALLinter", 16881 auxType: auxInt64, 16882 argLen: 2, 16883 clobberFlags: true, 16884 call: true, 16885 reg: regInfo{ 16886 inputs: []inputInfo{ 16887 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16888 }, 16889 clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO 16890 }, 16891 }, 16892 { 16893 name: "DUFFZERO", 16894 auxType: auxInt64, 16895 argLen: 2, 16896 faultOnNilArg0: true, 16897 reg: regInfo{ 16898 inputs: []inputInfo{ 16899 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16900 }, 16901 clobbers: 134217730, // R1 R31 16902 }, 16903 }, 16904 { 16905 name: "LoweredZero", 16906 auxType: auxInt64, 16907 argLen: 3, 16908 clobberFlags: true, 16909 faultOnNilArg0: true, 16910 reg: regInfo{ 16911 inputs: []inputInfo{ 16912 {0, 2}, // R1 16913 {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16914 }, 16915 clobbers: 2, // R1 16916 }, 16917 }, 16918 { 16919 name: "LoweredMove", 16920 auxType: auxInt64, 16921 argLen: 4, 16922 clobberFlags: true, 16923 faultOnNilArg0: true, 16924 faultOnNilArg1: true, 16925 reg: regInfo{ 16926 inputs: []inputInfo{ 16927 {0, 4}, // R2 16928 {1, 2}, // R1 16929 {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16930 }, 16931 clobbers: 6, // R1 R2 16932 }, 16933 }, 16934 { 16935 name: "LoweredAtomicLoad32", 16936 argLen: 2, 16937 faultOnNilArg0: true, 16938 reg: regInfo{ 16939 inputs: []inputInfo{ 16940 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16941 }, 16942 outputs: []outputInfo{ 16943 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16944 }, 16945 }, 16946 }, 16947 { 16948 name: "LoweredAtomicLoad64", 16949 argLen: 2, 16950 faultOnNilArg0: true, 16951 reg: regInfo{ 16952 inputs: []inputInfo{ 16953 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16954 }, 16955 outputs: []outputInfo{ 16956 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 16957 }, 16958 }, 16959 }, 16960 { 16961 name: "LoweredAtomicStore32", 16962 argLen: 3, 16963 faultOnNilArg0: true, 16964 hasSideEffects: true, 16965 reg: regInfo{ 16966 inputs: []inputInfo{ 16967 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16968 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16969 }, 16970 }, 16971 }, 16972 { 16973 name: "LoweredAtomicStore64", 16974 argLen: 3, 16975 faultOnNilArg0: true, 16976 hasSideEffects: true, 16977 reg: regInfo{ 16978 inputs: []inputInfo{ 16979 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 16980 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16981 }, 16982 }, 16983 }, 16984 { 16985 name: "LoweredAtomicStorezero32", 16986 argLen: 2, 16987 faultOnNilArg0: true, 16988 hasSideEffects: true, 16989 reg: regInfo{ 16990 inputs: []inputInfo{ 16991 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 16992 }, 16993 }, 16994 }, 16995 { 16996 name: "LoweredAtomicStorezero64", 16997 argLen: 2, 16998 faultOnNilArg0: true, 16999 hasSideEffects: true, 17000 reg: regInfo{ 17001 inputs: []inputInfo{ 17002 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17003 }, 17004 }, 17005 }, 17006 { 17007 name: "LoweredAtomicExchange32", 17008 argLen: 3, 17009 resultNotInArgs: true, 17010 faultOnNilArg0: true, 17011 hasSideEffects: true, 17012 reg: regInfo{ 17013 inputs: []inputInfo{ 17014 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17015 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17016 }, 17017 outputs: []outputInfo{ 17018 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17019 }, 17020 }, 17021 }, 17022 { 17023 name: "LoweredAtomicExchange64", 17024 argLen: 3, 17025 resultNotInArgs: true, 17026 faultOnNilArg0: true, 17027 hasSideEffects: true, 17028 reg: regInfo{ 17029 inputs: []inputInfo{ 17030 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17031 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17032 }, 17033 outputs: []outputInfo{ 17034 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17035 }, 17036 }, 17037 }, 17038 { 17039 name: "LoweredAtomicAdd32", 17040 argLen: 3, 17041 resultNotInArgs: true, 17042 faultOnNilArg0: true, 17043 hasSideEffects: true, 17044 reg: regInfo{ 17045 inputs: []inputInfo{ 17046 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17047 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17048 }, 17049 outputs: []outputInfo{ 17050 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17051 }, 17052 }, 17053 }, 17054 { 17055 name: "LoweredAtomicAdd64", 17056 argLen: 3, 17057 resultNotInArgs: true, 17058 faultOnNilArg0: true, 17059 hasSideEffects: true, 17060 reg: regInfo{ 17061 inputs: []inputInfo{ 17062 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17063 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17064 }, 17065 outputs: []outputInfo{ 17066 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17067 }, 17068 }, 17069 }, 17070 { 17071 name: "LoweredAtomicAddconst32", 17072 auxType: auxInt32, 17073 argLen: 2, 17074 resultNotInArgs: true, 17075 faultOnNilArg0: true, 17076 hasSideEffects: true, 17077 reg: regInfo{ 17078 inputs: []inputInfo{ 17079 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17080 }, 17081 outputs: []outputInfo{ 17082 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17083 }, 17084 }, 17085 }, 17086 { 17087 name: "LoweredAtomicAddconst64", 17088 auxType: auxInt64, 17089 argLen: 2, 17090 resultNotInArgs: true, 17091 faultOnNilArg0: true, 17092 hasSideEffects: true, 17093 reg: regInfo{ 17094 inputs: []inputInfo{ 17095 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17096 }, 17097 outputs: []outputInfo{ 17098 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17099 }, 17100 }, 17101 }, 17102 { 17103 name: "LoweredAtomicCas32", 17104 argLen: 4, 17105 resultNotInArgs: true, 17106 faultOnNilArg0: true, 17107 hasSideEffects: true, 17108 reg: regInfo{ 17109 inputs: []inputInfo{ 17110 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17111 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17112 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17113 }, 17114 outputs: []outputInfo{ 17115 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17116 }, 17117 }, 17118 }, 17119 { 17120 name: "LoweredAtomicCas64", 17121 argLen: 4, 17122 resultNotInArgs: true, 17123 faultOnNilArg0: true, 17124 hasSideEffects: true, 17125 reg: regInfo{ 17126 inputs: []inputInfo{ 17127 {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17128 {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17129 {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB 17130 }, 17131 outputs: []outputInfo{ 17132 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17133 }, 17134 }, 17135 }, 17136 { 17137 name: "LoweredNilCheck", 17138 argLen: 2, 17139 nilCheck: true, 17140 faultOnNilArg0: true, 17141 reg: regInfo{ 17142 inputs: []inputInfo{ 17143 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17144 }, 17145 }, 17146 }, 17147 { 17148 name: "FPFlagTrue", 17149 argLen: 1, 17150 reg: regInfo{ 17151 outputs: []outputInfo{ 17152 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17153 }, 17154 }, 17155 }, 17156 { 17157 name: "FPFlagFalse", 17158 argLen: 1, 17159 reg: regInfo{ 17160 outputs: []outputInfo{ 17161 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17162 }, 17163 }, 17164 }, 17165 { 17166 name: "LoweredGetClosurePtr", 17167 argLen: 0, 17168 reg: regInfo{ 17169 outputs: []outputInfo{ 17170 {0, 4194304}, // R22 17171 }, 17172 }, 17173 }, 17174 { 17175 name: "LoweredGetCallerSP", 17176 argLen: 0, 17177 rematerializeable: true, 17178 reg: regInfo{ 17179 outputs: []outputInfo{ 17180 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17181 }, 17182 }, 17183 }, 17184 { 17185 name: "MOVVconvert", 17186 argLen: 2, 17187 asm: mips.AMOVV, 17188 reg: regInfo{ 17189 inputs: []inputInfo{ 17190 {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 17191 }, 17192 outputs: []outputInfo{ 17193 {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 17194 }, 17195 }, 17196 }, 17197 17198 { 17199 name: "ADD", 17200 argLen: 2, 17201 commutative: true, 17202 asm: ppc64.AADD, 17203 reg: regInfo{ 17204 inputs: []inputInfo{ 17205 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17206 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17207 }, 17208 outputs: []outputInfo{ 17209 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17210 }, 17211 }, 17212 }, 17213 { 17214 name: "ADDconst", 17215 auxType: auxInt64, 17216 argLen: 1, 17217 asm: ppc64.AADD, 17218 reg: regInfo{ 17219 inputs: []inputInfo{ 17220 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17221 }, 17222 outputs: []outputInfo{ 17223 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17224 }, 17225 }, 17226 }, 17227 { 17228 name: "FADD", 17229 argLen: 2, 17230 commutative: true, 17231 asm: ppc64.AFADD, 17232 reg: regInfo{ 17233 inputs: []inputInfo{ 17234 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17235 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17236 }, 17237 outputs: []outputInfo{ 17238 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17239 }, 17240 }, 17241 }, 17242 { 17243 name: "FADDS", 17244 argLen: 2, 17245 commutative: true, 17246 asm: ppc64.AFADDS, 17247 reg: regInfo{ 17248 inputs: []inputInfo{ 17249 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17250 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17251 }, 17252 outputs: []outputInfo{ 17253 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17254 }, 17255 }, 17256 }, 17257 { 17258 name: "SUB", 17259 argLen: 2, 17260 asm: ppc64.ASUB, 17261 reg: regInfo{ 17262 inputs: []inputInfo{ 17263 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17264 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17265 }, 17266 outputs: []outputInfo{ 17267 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17268 }, 17269 }, 17270 }, 17271 { 17272 name: "FSUB", 17273 argLen: 2, 17274 asm: ppc64.AFSUB, 17275 reg: regInfo{ 17276 inputs: []inputInfo{ 17277 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17278 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17279 }, 17280 outputs: []outputInfo{ 17281 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17282 }, 17283 }, 17284 }, 17285 { 17286 name: "FSUBS", 17287 argLen: 2, 17288 asm: ppc64.AFSUBS, 17289 reg: regInfo{ 17290 inputs: []inputInfo{ 17291 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17292 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17293 }, 17294 outputs: []outputInfo{ 17295 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17296 }, 17297 }, 17298 }, 17299 { 17300 name: "MULLD", 17301 argLen: 2, 17302 commutative: true, 17303 asm: ppc64.AMULLD, 17304 reg: regInfo{ 17305 inputs: []inputInfo{ 17306 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17307 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17308 }, 17309 outputs: []outputInfo{ 17310 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17311 }, 17312 }, 17313 }, 17314 { 17315 name: "MULLW", 17316 argLen: 2, 17317 commutative: true, 17318 asm: ppc64.AMULLW, 17319 reg: regInfo{ 17320 inputs: []inputInfo{ 17321 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17322 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17323 }, 17324 outputs: []outputInfo{ 17325 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17326 }, 17327 }, 17328 }, 17329 { 17330 name: "MULHD", 17331 argLen: 2, 17332 commutative: true, 17333 asm: ppc64.AMULHD, 17334 reg: regInfo{ 17335 inputs: []inputInfo{ 17336 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17337 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17338 }, 17339 outputs: []outputInfo{ 17340 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17341 }, 17342 }, 17343 }, 17344 { 17345 name: "MULHW", 17346 argLen: 2, 17347 commutative: true, 17348 asm: ppc64.AMULHW, 17349 reg: regInfo{ 17350 inputs: []inputInfo{ 17351 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17352 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17353 }, 17354 outputs: []outputInfo{ 17355 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17356 }, 17357 }, 17358 }, 17359 { 17360 name: "MULHDU", 17361 argLen: 2, 17362 commutative: true, 17363 asm: ppc64.AMULHDU, 17364 reg: regInfo{ 17365 inputs: []inputInfo{ 17366 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17367 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17368 }, 17369 outputs: []outputInfo{ 17370 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17371 }, 17372 }, 17373 }, 17374 { 17375 name: "MULHWU", 17376 argLen: 2, 17377 commutative: true, 17378 asm: ppc64.AMULHWU, 17379 reg: regInfo{ 17380 inputs: []inputInfo{ 17381 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17382 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17383 }, 17384 outputs: []outputInfo{ 17385 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17386 }, 17387 }, 17388 }, 17389 { 17390 name: "FMUL", 17391 argLen: 2, 17392 commutative: true, 17393 asm: ppc64.AFMUL, 17394 reg: regInfo{ 17395 inputs: []inputInfo{ 17396 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17397 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17398 }, 17399 outputs: []outputInfo{ 17400 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17401 }, 17402 }, 17403 }, 17404 { 17405 name: "FMULS", 17406 argLen: 2, 17407 commutative: true, 17408 asm: ppc64.AFMULS, 17409 reg: regInfo{ 17410 inputs: []inputInfo{ 17411 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17412 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17413 }, 17414 outputs: []outputInfo{ 17415 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17416 }, 17417 }, 17418 }, 17419 { 17420 name: "FMADD", 17421 argLen: 3, 17422 asm: ppc64.AFMADD, 17423 reg: regInfo{ 17424 inputs: []inputInfo{ 17425 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17426 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17427 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17428 }, 17429 outputs: []outputInfo{ 17430 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17431 }, 17432 }, 17433 }, 17434 { 17435 name: "FMADDS", 17436 argLen: 3, 17437 asm: ppc64.AFMADDS, 17438 reg: regInfo{ 17439 inputs: []inputInfo{ 17440 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17441 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17442 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17443 }, 17444 outputs: []outputInfo{ 17445 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17446 }, 17447 }, 17448 }, 17449 { 17450 name: "FMSUB", 17451 argLen: 3, 17452 asm: ppc64.AFMSUB, 17453 reg: regInfo{ 17454 inputs: []inputInfo{ 17455 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17456 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17457 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17458 }, 17459 outputs: []outputInfo{ 17460 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17461 }, 17462 }, 17463 }, 17464 { 17465 name: "FMSUBS", 17466 argLen: 3, 17467 asm: ppc64.AFMSUBS, 17468 reg: regInfo{ 17469 inputs: []inputInfo{ 17470 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17471 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17472 {2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17473 }, 17474 outputs: []outputInfo{ 17475 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17476 }, 17477 }, 17478 }, 17479 { 17480 name: "SRAD", 17481 argLen: 2, 17482 asm: ppc64.ASRAD, 17483 reg: regInfo{ 17484 inputs: []inputInfo{ 17485 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17486 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17487 }, 17488 outputs: []outputInfo{ 17489 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17490 }, 17491 }, 17492 }, 17493 { 17494 name: "SRAW", 17495 argLen: 2, 17496 asm: ppc64.ASRAW, 17497 reg: regInfo{ 17498 inputs: []inputInfo{ 17499 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17500 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17501 }, 17502 outputs: []outputInfo{ 17503 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17504 }, 17505 }, 17506 }, 17507 { 17508 name: "SRD", 17509 argLen: 2, 17510 asm: ppc64.ASRD, 17511 reg: regInfo{ 17512 inputs: []inputInfo{ 17513 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17514 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17515 }, 17516 outputs: []outputInfo{ 17517 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17518 }, 17519 }, 17520 }, 17521 { 17522 name: "SRW", 17523 argLen: 2, 17524 asm: ppc64.ASRW, 17525 reg: regInfo{ 17526 inputs: []inputInfo{ 17527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17528 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17529 }, 17530 outputs: []outputInfo{ 17531 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17532 }, 17533 }, 17534 }, 17535 { 17536 name: "SLD", 17537 argLen: 2, 17538 asm: ppc64.ASLD, 17539 reg: regInfo{ 17540 inputs: []inputInfo{ 17541 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17542 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17543 }, 17544 outputs: []outputInfo{ 17545 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17546 }, 17547 }, 17548 }, 17549 { 17550 name: "SLW", 17551 argLen: 2, 17552 asm: ppc64.ASLW, 17553 reg: regInfo{ 17554 inputs: []inputInfo{ 17555 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17556 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17557 }, 17558 outputs: []outputInfo{ 17559 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17560 }, 17561 }, 17562 }, 17563 { 17564 name: "ROTL", 17565 argLen: 2, 17566 asm: ppc64.AROTL, 17567 reg: regInfo{ 17568 inputs: []inputInfo{ 17569 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17570 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17571 }, 17572 outputs: []outputInfo{ 17573 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17574 }, 17575 }, 17576 }, 17577 { 17578 name: "ROTLW", 17579 argLen: 2, 17580 asm: ppc64.AROTLW, 17581 reg: regInfo{ 17582 inputs: []inputInfo{ 17583 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17584 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17585 }, 17586 outputs: []outputInfo{ 17587 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17588 }, 17589 }, 17590 }, 17591 { 17592 name: "ADDconstForCarry", 17593 auxType: auxInt16, 17594 argLen: 1, 17595 asm: ppc64.AADDC, 17596 reg: regInfo{ 17597 inputs: []inputInfo{ 17598 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17599 }, 17600 clobbers: 2147483648, // R31 17601 }, 17602 }, 17603 { 17604 name: "MaskIfNotCarry", 17605 argLen: 1, 17606 asm: ppc64.AADDME, 17607 reg: regInfo{ 17608 outputs: []outputInfo{ 17609 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17610 }, 17611 }, 17612 }, 17613 { 17614 name: "SRADconst", 17615 auxType: auxInt64, 17616 argLen: 1, 17617 asm: ppc64.ASRAD, 17618 reg: regInfo{ 17619 inputs: []inputInfo{ 17620 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17621 }, 17622 outputs: []outputInfo{ 17623 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17624 }, 17625 }, 17626 }, 17627 { 17628 name: "SRAWconst", 17629 auxType: auxInt64, 17630 argLen: 1, 17631 asm: ppc64.ASRAW, 17632 reg: regInfo{ 17633 inputs: []inputInfo{ 17634 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17635 }, 17636 outputs: []outputInfo{ 17637 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17638 }, 17639 }, 17640 }, 17641 { 17642 name: "SRDconst", 17643 auxType: auxInt64, 17644 argLen: 1, 17645 asm: ppc64.ASRD, 17646 reg: regInfo{ 17647 inputs: []inputInfo{ 17648 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17649 }, 17650 outputs: []outputInfo{ 17651 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17652 }, 17653 }, 17654 }, 17655 { 17656 name: "SRWconst", 17657 auxType: auxInt64, 17658 argLen: 1, 17659 asm: ppc64.ASRW, 17660 reg: regInfo{ 17661 inputs: []inputInfo{ 17662 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17663 }, 17664 outputs: []outputInfo{ 17665 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17666 }, 17667 }, 17668 }, 17669 { 17670 name: "SLDconst", 17671 auxType: auxInt64, 17672 argLen: 1, 17673 asm: ppc64.ASLD, 17674 reg: regInfo{ 17675 inputs: []inputInfo{ 17676 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17677 }, 17678 outputs: []outputInfo{ 17679 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17680 }, 17681 }, 17682 }, 17683 { 17684 name: "SLWconst", 17685 auxType: auxInt64, 17686 argLen: 1, 17687 asm: ppc64.ASLW, 17688 reg: regInfo{ 17689 inputs: []inputInfo{ 17690 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17691 }, 17692 outputs: []outputInfo{ 17693 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17694 }, 17695 }, 17696 }, 17697 { 17698 name: "ROTLconst", 17699 auxType: auxInt64, 17700 argLen: 1, 17701 asm: ppc64.AROTL, 17702 reg: regInfo{ 17703 inputs: []inputInfo{ 17704 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17705 }, 17706 outputs: []outputInfo{ 17707 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17708 }, 17709 }, 17710 }, 17711 { 17712 name: "ROTLWconst", 17713 auxType: auxInt64, 17714 argLen: 1, 17715 asm: ppc64.AROTLW, 17716 reg: regInfo{ 17717 inputs: []inputInfo{ 17718 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17719 }, 17720 outputs: []outputInfo{ 17721 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17722 }, 17723 }, 17724 }, 17725 { 17726 name: "CNTLZD", 17727 argLen: 1, 17728 clobberFlags: true, 17729 asm: ppc64.ACNTLZD, 17730 reg: regInfo{ 17731 inputs: []inputInfo{ 17732 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17733 }, 17734 outputs: []outputInfo{ 17735 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17736 }, 17737 }, 17738 }, 17739 { 17740 name: "CNTLZW", 17741 argLen: 1, 17742 clobberFlags: true, 17743 asm: ppc64.ACNTLZW, 17744 reg: regInfo{ 17745 inputs: []inputInfo{ 17746 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17747 }, 17748 outputs: []outputInfo{ 17749 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17750 }, 17751 }, 17752 }, 17753 { 17754 name: "POPCNTD", 17755 argLen: 1, 17756 asm: ppc64.APOPCNTD, 17757 reg: regInfo{ 17758 inputs: []inputInfo{ 17759 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17760 }, 17761 outputs: []outputInfo{ 17762 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17763 }, 17764 }, 17765 }, 17766 { 17767 name: "POPCNTW", 17768 argLen: 1, 17769 asm: ppc64.APOPCNTW, 17770 reg: regInfo{ 17771 inputs: []inputInfo{ 17772 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17773 }, 17774 outputs: []outputInfo{ 17775 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17776 }, 17777 }, 17778 }, 17779 { 17780 name: "POPCNTB", 17781 argLen: 1, 17782 asm: ppc64.APOPCNTB, 17783 reg: regInfo{ 17784 inputs: []inputInfo{ 17785 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17786 }, 17787 outputs: []outputInfo{ 17788 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17789 }, 17790 }, 17791 }, 17792 { 17793 name: "FDIV", 17794 argLen: 2, 17795 asm: ppc64.AFDIV, 17796 reg: regInfo{ 17797 inputs: []inputInfo{ 17798 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17799 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17800 }, 17801 outputs: []outputInfo{ 17802 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17803 }, 17804 }, 17805 }, 17806 { 17807 name: "FDIVS", 17808 argLen: 2, 17809 asm: ppc64.AFDIVS, 17810 reg: regInfo{ 17811 inputs: []inputInfo{ 17812 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17813 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17814 }, 17815 outputs: []outputInfo{ 17816 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17817 }, 17818 }, 17819 }, 17820 { 17821 name: "DIVD", 17822 argLen: 2, 17823 asm: ppc64.ADIVD, 17824 reg: regInfo{ 17825 inputs: []inputInfo{ 17826 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17827 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17828 }, 17829 outputs: []outputInfo{ 17830 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17831 }, 17832 }, 17833 }, 17834 { 17835 name: "DIVW", 17836 argLen: 2, 17837 asm: ppc64.ADIVW, 17838 reg: regInfo{ 17839 inputs: []inputInfo{ 17840 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17841 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17842 }, 17843 outputs: []outputInfo{ 17844 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17845 }, 17846 }, 17847 }, 17848 { 17849 name: "DIVDU", 17850 argLen: 2, 17851 asm: ppc64.ADIVDU, 17852 reg: regInfo{ 17853 inputs: []inputInfo{ 17854 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17855 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17856 }, 17857 outputs: []outputInfo{ 17858 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17859 }, 17860 }, 17861 }, 17862 { 17863 name: "DIVWU", 17864 argLen: 2, 17865 asm: ppc64.ADIVWU, 17866 reg: regInfo{ 17867 inputs: []inputInfo{ 17868 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17869 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17870 }, 17871 outputs: []outputInfo{ 17872 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17873 }, 17874 }, 17875 }, 17876 { 17877 name: "FCTIDZ", 17878 argLen: 1, 17879 asm: ppc64.AFCTIDZ, 17880 reg: regInfo{ 17881 inputs: []inputInfo{ 17882 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17883 }, 17884 outputs: []outputInfo{ 17885 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17886 }, 17887 }, 17888 }, 17889 { 17890 name: "FCTIWZ", 17891 argLen: 1, 17892 asm: ppc64.AFCTIWZ, 17893 reg: regInfo{ 17894 inputs: []inputInfo{ 17895 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17896 }, 17897 outputs: []outputInfo{ 17898 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17899 }, 17900 }, 17901 }, 17902 { 17903 name: "FCFID", 17904 argLen: 1, 17905 asm: ppc64.AFCFID, 17906 reg: regInfo{ 17907 inputs: []inputInfo{ 17908 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17909 }, 17910 outputs: []outputInfo{ 17911 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17912 }, 17913 }, 17914 }, 17915 { 17916 name: "FCFIDS", 17917 argLen: 1, 17918 asm: ppc64.AFCFIDS, 17919 reg: regInfo{ 17920 inputs: []inputInfo{ 17921 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17922 }, 17923 outputs: []outputInfo{ 17924 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17925 }, 17926 }, 17927 }, 17928 { 17929 name: "FRSP", 17930 argLen: 1, 17931 asm: ppc64.AFRSP, 17932 reg: regInfo{ 17933 inputs: []inputInfo{ 17934 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17935 }, 17936 outputs: []outputInfo{ 17937 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17938 }, 17939 }, 17940 }, 17941 { 17942 name: "MFVSRD", 17943 argLen: 1, 17944 asm: ppc64.AMFVSRD, 17945 reg: regInfo{ 17946 inputs: []inputInfo{ 17947 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17948 }, 17949 outputs: []outputInfo{ 17950 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17951 }, 17952 }, 17953 }, 17954 { 17955 name: "MTVSRD", 17956 argLen: 1, 17957 asm: ppc64.AMTVSRD, 17958 reg: regInfo{ 17959 inputs: []inputInfo{ 17960 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17961 }, 17962 outputs: []outputInfo{ 17963 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 17964 }, 17965 }, 17966 }, 17967 { 17968 name: "AND", 17969 argLen: 2, 17970 commutative: true, 17971 asm: ppc64.AAND, 17972 reg: regInfo{ 17973 inputs: []inputInfo{ 17974 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17975 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17976 }, 17977 outputs: []outputInfo{ 17978 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17979 }, 17980 }, 17981 }, 17982 { 17983 name: "ANDN", 17984 argLen: 2, 17985 asm: ppc64.AANDN, 17986 reg: regInfo{ 17987 inputs: []inputInfo{ 17988 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17989 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17990 }, 17991 outputs: []outputInfo{ 17992 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 17993 }, 17994 }, 17995 }, 17996 { 17997 name: "OR", 17998 argLen: 2, 17999 commutative: true, 18000 asm: ppc64.AOR, 18001 reg: regInfo{ 18002 inputs: []inputInfo{ 18003 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18004 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18005 }, 18006 outputs: []outputInfo{ 18007 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18008 }, 18009 }, 18010 }, 18011 { 18012 name: "ORN", 18013 argLen: 2, 18014 asm: ppc64.AORN, 18015 reg: regInfo{ 18016 inputs: []inputInfo{ 18017 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18018 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18019 }, 18020 outputs: []outputInfo{ 18021 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18022 }, 18023 }, 18024 }, 18025 { 18026 name: "NOR", 18027 argLen: 2, 18028 commutative: true, 18029 asm: ppc64.ANOR, 18030 reg: regInfo{ 18031 inputs: []inputInfo{ 18032 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18033 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18034 }, 18035 outputs: []outputInfo{ 18036 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18037 }, 18038 }, 18039 }, 18040 { 18041 name: "XOR", 18042 argLen: 2, 18043 commutative: true, 18044 asm: ppc64.AXOR, 18045 reg: regInfo{ 18046 inputs: []inputInfo{ 18047 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18048 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18049 }, 18050 outputs: []outputInfo{ 18051 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18052 }, 18053 }, 18054 }, 18055 { 18056 name: "EQV", 18057 argLen: 2, 18058 commutative: true, 18059 asm: ppc64.AEQV, 18060 reg: regInfo{ 18061 inputs: []inputInfo{ 18062 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18063 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18064 }, 18065 outputs: []outputInfo{ 18066 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18067 }, 18068 }, 18069 }, 18070 { 18071 name: "NEG", 18072 argLen: 1, 18073 asm: ppc64.ANEG, 18074 reg: regInfo{ 18075 inputs: []inputInfo{ 18076 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18077 }, 18078 outputs: []outputInfo{ 18079 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18080 }, 18081 }, 18082 }, 18083 { 18084 name: "FNEG", 18085 argLen: 1, 18086 asm: ppc64.AFNEG, 18087 reg: regInfo{ 18088 inputs: []inputInfo{ 18089 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18090 }, 18091 outputs: []outputInfo{ 18092 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18093 }, 18094 }, 18095 }, 18096 { 18097 name: "FSQRT", 18098 argLen: 1, 18099 asm: ppc64.AFSQRT, 18100 reg: regInfo{ 18101 inputs: []inputInfo{ 18102 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18103 }, 18104 outputs: []outputInfo{ 18105 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18106 }, 18107 }, 18108 }, 18109 { 18110 name: "FSQRTS", 18111 argLen: 1, 18112 asm: ppc64.AFSQRTS, 18113 reg: regInfo{ 18114 inputs: []inputInfo{ 18115 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18116 }, 18117 outputs: []outputInfo{ 18118 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18119 }, 18120 }, 18121 }, 18122 { 18123 name: "FFLOOR", 18124 argLen: 1, 18125 asm: ppc64.AFRIM, 18126 reg: regInfo{ 18127 inputs: []inputInfo{ 18128 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18129 }, 18130 outputs: []outputInfo{ 18131 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18132 }, 18133 }, 18134 }, 18135 { 18136 name: "FCEIL", 18137 argLen: 1, 18138 asm: ppc64.AFRIP, 18139 reg: regInfo{ 18140 inputs: []inputInfo{ 18141 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18142 }, 18143 outputs: []outputInfo{ 18144 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18145 }, 18146 }, 18147 }, 18148 { 18149 name: "FTRUNC", 18150 argLen: 1, 18151 asm: ppc64.AFRIZ, 18152 reg: regInfo{ 18153 inputs: []inputInfo{ 18154 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18155 }, 18156 outputs: []outputInfo{ 18157 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18158 }, 18159 }, 18160 }, 18161 { 18162 name: "FABS", 18163 argLen: 1, 18164 asm: ppc64.AFABS, 18165 reg: regInfo{ 18166 inputs: []inputInfo{ 18167 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18168 }, 18169 outputs: []outputInfo{ 18170 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18171 }, 18172 }, 18173 }, 18174 { 18175 name: "FNABS", 18176 argLen: 1, 18177 asm: ppc64.AFNABS, 18178 reg: regInfo{ 18179 inputs: []inputInfo{ 18180 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18181 }, 18182 outputs: []outputInfo{ 18183 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18184 }, 18185 }, 18186 }, 18187 { 18188 name: "FCPSGN", 18189 argLen: 2, 18190 asm: ppc64.AFCPSGN, 18191 reg: regInfo{ 18192 inputs: []inputInfo{ 18193 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18194 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18195 }, 18196 outputs: []outputInfo{ 18197 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18198 }, 18199 }, 18200 }, 18201 { 18202 name: "ORconst", 18203 auxType: auxInt64, 18204 argLen: 1, 18205 asm: ppc64.AOR, 18206 reg: regInfo{ 18207 inputs: []inputInfo{ 18208 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18209 }, 18210 outputs: []outputInfo{ 18211 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18212 }, 18213 }, 18214 }, 18215 { 18216 name: "XORconst", 18217 auxType: auxInt64, 18218 argLen: 1, 18219 asm: ppc64.AXOR, 18220 reg: regInfo{ 18221 inputs: []inputInfo{ 18222 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18223 }, 18224 outputs: []outputInfo{ 18225 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18226 }, 18227 }, 18228 }, 18229 { 18230 name: "ANDconst", 18231 auxType: auxInt64, 18232 argLen: 1, 18233 clobberFlags: true, 18234 asm: ppc64.AANDCC, 18235 reg: regInfo{ 18236 inputs: []inputInfo{ 18237 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18238 }, 18239 outputs: []outputInfo{ 18240 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18241 }, 18242 }, 18243 }, 18244 { 18245 name: "ANDCCconst", 18246 auxType: auxInt64, 18247 argLen: 1, 18248 asm: ppc64.AANDCC, 18249 reg: regInfo{ 18250 inputs: []inputInfo{ 18251 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18252 }, 18253 }, 18254 }, 18255 { 18256 name: "MOVBreg", 18257 argLen: 1, 18258 asm: ppc64.AMOVB, 18259 reg: regInfo{ 18260 inputs: []inputInfo{ 18261 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18262 }, 18263 outputs: []outputInfo{ 18264 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18265 }, 18266 }, 18267 }, 18268 { 18269 name: "MOVBZreg", 18270 argLen: 1, 18271 asm: ppc64.AMOVBZ, 18272 reg: regInfo{ 18273 inputs: []inputInfo{ 18274 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18275 }, 18276 outputs: []outputInfo{ 18277 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18278 }, 18279 }, 18280 }, 18281 { 18282 name: "MOVHreg", 18283 argLen: 1, 18284 asm: ppc64.AMOVH, 18285 reg: regInfo{ 18286 inputs: []inputInfo{ 18287 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18288 }, 18289 outputs: []outputInfo{ 18290 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18291 }, 18292 }, 18293 }, 18294 { 18295 name: "MOVHZreg", 18296 argLen: 1, 18297 asm: ppc64.AMOVHZ, 18298 reg: regInfo{ 18299 inputs: []inputInfo{ 18300 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18301 }, 18302 outputs: []outputInfo{ 18303 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18304 }, 18305 }, 18306 }, 18307 { 18308 name: "MOVWreg", 18309 argLen: 1, 18310 asm: ppc64.AMOVW, 18311 reg: regInfo{ 18312 inputs: []inputInfo{ 18313 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18314 }, 18315 outputs: []outputInfo{ 18316 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18317 }, 18318 }, 18319 }, 18320 { 18321 name: "MOVWZreg", 18322 argLen: 1, 18323 asm: ppc64.AMOVWZ, 18324 reg: regInfo{ 18325 inputs: []inputInfo{ 18326 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18327 }, 18328 outputs: []outputInfo{ 18329 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18330 }, 18331 }, 18332 }, 18333 { 18334 name: "MOVBZload", 18335 auxType: auxSymOff, 18336 argLen: 2, 18337 faultOnNilArg0: true, 18338 symEffect: SymRead, 18339 asm: ppc64.AMOVBZ, 18340 reg: regInfo{ 18341 inputs: []inputInfo{ 18342 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18343 }, 18344 outputs: []outputInfo{ 18345 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18346 }, 18347 }, 18348 }, 18349 { 18350 name: "MOVHload", 18351 auxType: auxSymOff, 18352 argLen: 2, 18353 faultOnNilArg0: true, 18354 symEffect: SymRead, 18355 asm: ppc64.AMOVH, 18356 reg: regInfo{ 18357 inputs: []inputInfo{ 18358 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18359 }, 18360 outputs: []outputInfo{ 18361 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18362 }, 18363 }, 18364 }, 18365 { 18366 name: "MOVHZload", 18367 auxType: auxSymOff, 18368 argLen: 2, 18369 faultOnNilArg0: true, 18370 symEffect: SymRead, 18371 asm: ppc64.AMOVHZ, 18372 reg: regInfo{ 18373 inputs: []inputInfo{ 18374 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18375 }, 18376 outputs: []outputInfo{ 18377 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18378 }, 18379 }, 18380 }, 18381 { 18382 name: "MOVWload", 18383 auxType: auxSymOff, 18384 argLen: 2, 18385 faultOnNilArg0: true, 18386 symEffect: SymRead, 18387 asm: ppc64.AMOVW, 18388 reg: regInfo{ 18389 inputs: []inputInfo{ 18390 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18391 }, 18392 outputs: []outputInfo{ 18393 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18394 }, 18395 }, 18396 }, 18397 { 18398 name: "MOVWZload", 18399 auxType: auxSymOff, 18400 argLen: 2, 18401 faultOnNilArg0: true, 18402 symEffect: SymRead, 18403 asm: ppc64.AMOVWZ, 18404 reg: regInfo{ 18405 inputs: []inputInfo{ 18406 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18407 }, 18408 outputs: []outputInfo{ 18409 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18410 }, 18411 }, 18412 }, 18413 { 18414 name: "MOVDload", 18415 auxType: auxSymOff, 18416 argLen: 2, 18417 faultOnNilArg0: true, 18418 symEffect: SymRead, 18419 asm: ppc64.AMOVD, 18420 reg: regInfo{ 18421 inputs: []inputInfo{ 18422 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18423 }, 18424 outputs: []outputInfo{ 18425 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18426 }, 18427 }, 18428 }, 18429 { 18430 name: "FMOVDload", 18431 auxType: auxSymOff, 18432 argLen: 2, 18433 faultOnNilArg0: true, 18434 symEffect: SymRead, 18435 asm: ppc64.AFMOVD, 18436 reg: regInfo{ 18437 inputs: []inputInfo{ 18438 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18439 }, 18440 outputs: []outputInfo{ 18441 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18442 }, 18443 }, 18444 }, 18445 { 18446 name: "FMOVSload", 18447 auxType: auxSymOff, 18448 argLen: 2, 18449 faultOnNilArg0: true, 18450 symEffect: SymRead, 18451 asm: ppc64.AFMOVS, 18452 reg: regInfo{ 18453 inputs: []inputInfo{ 18454 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18455 }, 18456 outputs: []outputInfo{ 18457 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18458 }, 18459 }, 18460 }, 18461 { 18462 name: "MOVBstore", 18463 auxType: auxSymOff, 18464 argLen: 3, 18465 faultOnNilArg0: true, 18466 symEffect: SymWrite, 18467 asm: ppc64.AMOVB, 18468 reg: regInfo{ 18469 inputs: []inputInfo{ 18470 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18471 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18472 }, 18473 }, 18474 }, 18475 { 18476 name: "MOVHstore", 18477 auxType: auxSymOff, 18478 argLen: 3, 18479 faultOnNilArg0: true, 18480 symEffect: SymWrite, 18481 asm: ppc64.AMOVH, 18482 reg: regInfo{ 18483 inputs: []inputInfo{ 18484 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18485 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18486 }, 18487 }, 18488 }, 18489 { 18490 name: "MOVWstore", 18491 auxType: auxSymOff, 18492 argLen: 3, 18493 faultOnNilArg0: true, 18494 symEffect: SymWrite, 18495 asm: ppc64.AMOVW, 18496 reg: regInfo{ 18497 inputs: []inputInfo{ 18498 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18499 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18500 }, 18501 }, 18502 }, 18503 { 18504 name: "MOVDstore", 18505 auxType: auxSymOff, 18506 argLen: 3, 18507 faultOnNilArg0: true, 18508 symEffect: SymWrite, 18509 asm: ppc64.AMOVD, 18510 reg: regInfo{ 18511 inputs: []inputInfo{ 18512 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18513 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18514 }, 18515 }, 18516 }, 18517 { 18518 name: "FMOVDstore", 18519 auxType: auxSymOff, 18520 argLen: 3, 18521 faultOnNilArg0: true, 18522 symEffect: SymWrite, 18523 asm: ppc64.AFMOVD, 18524 reg: regInfo{ 18525 inputs: []inputInfo{ 18526 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18527 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18528 }, 18529 }, 18530 }, 18531 { 18532 name: "FMOVSstore", 18533 auxType: auxSymOff, 18534 argLen: 3, 18535 faultOnNilArg0: true, 18536 symEffect: SymWrite, 18537 asm: ppc64.AFMOVS, 18538 reg: regInfo{ 18539 inputs: []inputInfo{ 18540 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18541 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18542 }, 18543 }, 18544 }, 18545 { 18546 name: "MOVBstorezero", 18547 auxType: auxSymOff, 18548 argLen: 2, 18549 faultOnNilArg0: true, 18550 symEffect: SymWrite, 18551 asm: ppc64.AMOVB, 18552 reg: regInfo{ 18553 inputs: []inputInfo{ 18554 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18555 }, 18556 }, 18557 }, 18558 { 18559 name: "MOVHstorezero", 18560 auxType: auxSymOff, 18561 argLen: 2, 18562 faultOnNilArg0: true, 18563 symEffect: SymWrite, 18564 asm: ppc64.AMOVH, 18565 reg: regInfo{ 18566 inputs: []inputInfo{ 18567 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18568 }, 18569 }, 18570 }, 18571 { 18572 name: "MOVWstorezero", 18573 auxType: auxSymOff, 18574 argLen: 2, 18575 faultOnNilArg0: true, 18576 symEffect: SymWrite, 18577 asm: ppc64.AMOVW, 18578 reg: regInfo{ 18579 inputs: []inputInfo{ 18580 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18581 }, 18582 }, 18583 }, 18584 { 18585 name: "MOVDstorezero", 18586 auxType: auxSymOff, 18587 argLen: 2, 18588 faultOnNilArg0: true, 18589 symEffect: SymWrite, 18590 asm: ppc64.AMOVD, 18591 reg: regInfo{ 18592 inputs: []inputInfo{ 18593 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18594 }, 18595 }, 18596 }, 18597 { 18598 name: "MOVDaddr", 18599 auxType: auxSymOff, 18600 argLen: 1, 18601 rematerializeable: true, 18602 symEffect: SymAddr, 18603 asm: ppc64.AMOVD, 18604 reg: regInfo{ 18605 inputs: []inputInfo{ 18606 {0, 6}, // SP SB 18607 }, 18608 outputs: []outputInfo{ 18609 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18610 }, 18611 }, 18612 }, 18613 { 18614 name: "MOVDconst", 18615 auxType: auxInt64, 18616 argLen: 0, 18617 rematerializeable: true, 18618 asm: ppc64.AMOVD, 18619 reg: regInfo{ 18620 outputs: []outputInfo{ 18621 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18622 }, 18623 }, 18624 }, 18625 { 18626 name: "FMOVDconst", 18627 auxType: auxFloat64, 18628 argLen: 0, 18629 rematerializeable: true, 18630 asm: ppc64.AFMOVD, 18631 reg: regInfo{ 18632 outputs: []outputInfo{ 18633 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18634 }, 18635 }, 18636 }, 18637 { 18638 name: "FMOVSconst", 18639 auxType: auxFloat32, 18640 argLen: 0, 18641 rematerializeable: true, 18642 asm: ppc64.AFMOVS, 18643 reg: regInfo{ 18644 outputs: []outputInfo{ 18645 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18646 }, 18647 }, 18648 }, 18649 { 18650 name: "FCMPU", 18651 argLen: 2, 18652 asm: ppc64.AFCMPU, 18653 reg: regInfo{ 18654 inputs: []inputInfo{ 18655 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18656 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18657 }, 18658 }, 18659 }, 18660 { 18661 name: "CMP", 18662 argLen: 2, 18663 asm: ppc64.ACMP, 18664 reg: regInfo{ 18665 inputs: []inputInfo{ 18666 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18667 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18668 }, 18669 }, 18670 }, 18671 { 18672 name: "CMPU", 18673 argLen: 2, 18674 asm: ppc64.ACMPU, 18675 reg: regInfo{ 18676 inputs: []inputInfo{ 18677 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18678 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18679 }, 18680 }, 18681 }, 18682 { 18683 name: "CMPW", 18684 argLen: 2, 18685 asm: ppc64.ACMPW, 18686 reg: regInfo{ 18687 inputs: []inputInfo{ 18688 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18689 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18690 }, 18691 }, 18692 }, 18693 { 18694 name: "CMPWU", 18695 argLen: 2, 18696 asm: ppc64.ACMPWU, 18697 reg: regInfo{ 18698 inputs: []inputInfo{ 18699 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18700 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18701 }, 18702 }, 18703 }, 18704 { 18705 name: "CMPconst", 18706 auxType: auxInt64, 18707 argLen: 1, 18708 asm: ppc64.ACMP, 18709 reg: regInfo{ 18710 inputs: []inputInfo{ 18711 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18712 }, 18713 }, 18714 }, 18715 { 18716 name: "CMPUconst", 18717 auxType: auxInt64, 18718 argLen: 1, 18719 asm: ppc64.ACMPU, 18720 reg: regInfo{ 18721 inputs: []inputInfo{ 18722 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18723 }, 18724 }, 18725 }, 18726 { 18727 name: "CMPWconst", 18728 auxType: auxInt32, 18729 argLen: 1, 18730 asm: ppc64.ACMPW, 18731 reg: regInfo{ 18732 inputs: []inputInfo{ 18733 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18734 }, 18735 }, 18736 }, 18737 { 18738 name: "CMPWUconst", 18739 auxType: auxInt32, 18740 argLen: 1, 18741 asm: ppc64.ACMPWU, 18742 reg: regInfo{ 18743 inputs: []inputInfo{ 18744 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18745 }, 18746 }, 18747 }, 18748 { 18749 name: "Equal", 18750 argLen: 1, 18751 reg: regInfo{ 18752 outputs: []outputInfo{ 18753 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18754 }, 18755 }, 18756 }, 18757 { 18758 name: "NotEqual", 18759 argLen: 1, 18760 reg: regInfo{ 18761 outputs: []outputInfo{ 18762 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18763 }, 18764 }, 18765 }, 18766 { 18767 name: "LessThan", 18768 argLen: 1, 18769 reg: regInfo{ 18770 outputs: []outputInfo{ 18771 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18772 }, 18773 }, 18774 }, 18775 { 18776 name: "FLessThan", 18777 argLen: 1, 18778 reg: regInfo{ 18779 outputs: []outputInfo{ 18780 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18781 }, 18782 }, 18783 }, 18784 { 18785 name: "LessEqual", 18786 argLen: 1, 18787 reg: regInfo{ 18788 outputs: []outputInfo{ 18789 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18790 }, 18791 }, 18792 }, 18793 { 18794 name: "FLessEqual", 18795 argLen: 1, 18796 reg: regInfo{ 18797 outputs: []outputInfo{ 18798 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18799 }, 18800 }, 18801 }, 18802 { 18803 name: "GreaterThan", 18804 argLen: 1, 18805 reg: regInfo{ 18806 outputs: []outputInfo{ 18807 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18808 }, 18809 }, 18810 }, 18811 { 18812 name: "FGreaterThan", 18813 argLen: 1, 18814 reg: regInfo{ 18815 outputs: []outputInfo{ 18816 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18817 }, 18818 }, 18819 }, 18820 { 18821 name: "GreaterEqual", 18822 argLen: 1, 18823 reg: regInfo{ 18824 outputs: []outputInfo{ 18825 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18826 }, 18827 }, 18828 }, 18829 { 18830 name: "FGreaterEqual", 18831 argLen: 1, 18832 reg: regInfo{ 18833 outputs: []outputInfo{ 18834 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18835 }, 18836 }, 18837 }, 18838 { 18839 name: "LoweredGetClosurePtr", 18840 argLen: 0, 18841 reg: regInfo{ 18842 outputs: []outputInfo{ 18843 {0, 2048}, // R11 18844 }, 18845 }, 18846 }, 18847 { 18848 name: "LoweredGetCallerSP", 18849 argLen: 0, 18850 rematerializeable: true, 18851 reg: regInfo{ 18852 outputs: []outputInfo{ 18853 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18854 }, 18855 }, 18856 }, 18857 { 18858 name: "LoweredNilCheck", 18859 argLen: 2, 18860 clobberFlags: true, 18861 nilCheck: true, 18862 faultOnNilArg0: true, 18863 reg: regInfo{ 18864 inputs: []inputInfo{ 18865 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18866 }, 18867 clobbers: 2147483648, // R31 18868 }, 18869 }, 18870 { 18871 name: "LoweredRound32F", 18872 argLen: 1, 18873 resultInArg0: true, 18874 reg: regInfo{ 18875 inputs: []inputInfo{ 18876 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18877 }, 18878 outputs: []outputInfo{ 18879 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18880 }, 18881 }, 18882 }, 18883 { 18884 name: "LoweredRound64F", 18885 argLen: 1, 18886 resultInArg0: true, 18887 reg: regInfo{ 18888 inputs: []inputInfo{ 18889 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18890 }, 18891 outputs: []outputInfo{ 18892 {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18893 }, 18894 }, 18895 }, 18896 { 18897 name: "MOVDconvert", 18898 argLen: 2, 18899 asm: ppc64.AMOVD, 18900 reg: regInfo{ 18901 inputs: []inputInfo{ 18902 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18903 }, 18904 outputs: []outputInfo{ 18905 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18906 }, 18907 }, 18908 }, 18909 { 18910 name: "CALLstatic", 18911 auxType: auxSymOff, 18912 argLen: 1, 18913 clobberFlags: true, 18914 call: true, 18915 symEffect: SymNone, 18916 reg: regInfo{ 18917 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18918 }, 18919 }, 18920 { 18921 name: "CALLclosure", 18922 auxType: auxInt64, 18923 argLen: 3, 18924 clobberFlags: true, 18925 call: true, 18926 reg: regInfo{ 18927 inputs: []inputInfo{ 18928 {0, 4096}, // R12 18929 {1, 2048}, // R11 18930 }, 18931 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18932 }, 18933 }, 18934 { 18935 name: "CALLinter", 18936 auxType: auxInt64, 18937 argLen: 2, 18938 clobberFlags: true, 18939 call: true, 18940 reg: regInfo{ 18941 inputs: []inputInfo{ 18942 {0, 4096}, // R12 18943 }, 18944 clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 18945 }, 18946 }, 18947 { 18948 name: "LoweredZero", 18949 auxType: auxInt64, 18950 argLen: 2, 18951 clobberFlags: true, 18952 faultOnNilArg0: true, 18953 reg: regInfo{ 18954 inputs: []inputInfo{ 18955 {0, 8}, // R3 18956 }, 18957 clobbers: 8, // R3 18958 }, 18959 }, 18960 { 18961 name: "LoweredMove", 18962 auxType: auxInt64, 18963 argLen: 3, 18964 clobberFlags: true, 18965 faultOnNilArg0: true, 18966 faultOnNilArg1: true, 18967 reg: regInfo{ 18968 inputs: []inputInfo{ 18969 {0, 8}, // R3 18970 {1, 16}, // R4 18971 }, 18972 clobbers: 1944, // R3 R4 R7 R8 R9 R10 18973 }, 18974 }, 18975 { 18976 name: "LoweredAtomicStore32", 18977 argLen: 3, 18978 faultOnNilArg0: true, 18979 hasSideEffects: true, 18980 reg: regInfo{ 18981 inputs: []inputInfo{ 18982 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18983 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18984 }, 18985 }, 18986 }, 18987 { 18988 name: "LoweredAtomicStore64", 18989 argLen: 3, 18990 faultOnNilArg0: true, 18991 hasSideEffects: true, 18992 reg: regInfo{ 18993 inputs: []inputInfo{ 18994 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18995 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 18996 }, 18997 }, 18998 }, 18999 { 19000 name: "LoweredAtomicLoad32", 19001 argLen: 2, 19002 clobberFlags: true, 19003 faultOnNilArg0: true, 19004 reg: regInfo{ 19005 inputs: []inputInfo{ 19006 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19007 }, 19008 outputs: []outputInfo{ 19009 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19010 }, 19011 }, 19012 }, 19013 { 19014 name: "LoweredAtomicLoad64", 19015 argLen: 2, 19016 clobberFlags: true, 19017 faultOnNilArg0: true, 19018 reg: regInfo{ 19019 inputs: []inputInfo{ 19020 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19021 }, 19022 outputs: []outputInfo{ 19023 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19024 }, 19025 }, 19026 }, 19027 { 19028 name: "LoweredAtomicLoadPtr", 19029 argLen: 2, 19030 clobberFlags: true, 19031 faultOnNilArg0: true, 19032 reg: regInfo{ 19033 inputs: []inputInfo{ 19034 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19035 }, 19036 outputs: []outputInfo{ 19037 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19038 }, 19039 }, 19040 }, 19041 { 19042 name: "LoweredAtomicAdd32", 19043 argLen: 3, 19044 resultNotInArgs: true, 19045 clobberFlags: true, 19046 faultOnNilArg0: true, 19047 hasSideEffects: true, 19048 reg: regInfo{ 19049 inputs: []inputInfo{ 19050 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19051 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19052 }, 19053 outputs: []outputInfo{ 19054 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19055 }, 19056 }, 19057 }, 19058 { 19059 name: "LoweredAtomicAdd64", 19060 argLen: 3, 19061 resultNotInArgs: true, 19062 clobberFlags: true, 19063 faultOnNilArg0: true, 19064 hasSideEffects: true, 19065 reg: regInfo{ 19066 inputs: []inputInfo{ 19067 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19068 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19069 }, 19070 outputs: []outputInfo{ 19071 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19072 }, 19073 }, 19074 }, 19075 { 19076 name: "LoweredAtomicExchange32", 19077 argLen: 3, 19078 resultNotInArgs: true, 19079 clobberFlags: true, 19080 faultOnNilArg0: true, 19081 hasSideEffects: true, 19082 reg: regInfo{ 19083 inputs: []inputInfo{ 19084 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19085 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19086 }, 19087 outputs: []outputInfo{ 19088 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19089 }, 19090 }, 19091 }, 19092 { 19093 name: "LoweredAtomicExchange64", 19094 argLen: 3, 19095 resultNotInArgs: true, 19096 clobberFlags: true, 19097 faultOnNilArg0: true, 19098 hasSideEffects: true, 19099 reg: regInfo{ 19100 inputs: []inputInfo{ 19101 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19102 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19103 }, 19104 outputs: []outputInfo{ 19105 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19106 }, 19107 }, 19108 }, 19109 { 19110 name: "LoweredAtomicCas64", 19111 argLen: 4, 19112 resultNotInArgs: true, 19113 clobberFlags: true, 19114 faultOnNilArg0: true, 19115 hasSideEffects: true, 19116 reg: regInfo{ 19117 inputs: []inputInfo{ 19118 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19119 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19120 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19121 }, 19122 outputs: []outputInfo{ 19123 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19124 }, 19125 }, 19126 }, 19127 { 19128 name: "LoweredAtomicCas32", 19129 argLen: 4, 19130 resultNotInArgs: true, 19131 clobberFlags: true, 19132 faultOnNilArg0: true, 19133 hasSideEffects: true, 19134 reg: regInfo{ 19135 inputs: []inputInfo{ 19136 {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19137 {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19138 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19139 }, 19140 outputs: []outputInfo{ 19141 {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19142 }, 19143 }, 19144 }, 19145 { 19146 name: "LoweredAtomicAnd8", 19147 argLen: 3, 19148 faultOnNilArg0: true, 19149 hasSideEffects: true, 19150 asm: ppc64.AAND, 19151 reg: regInfo{ 19152 inputs: []inputInfo{ 19153 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19154 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19155 }, 19156 }, 19157 }, 19158 { 19159 name: "LoweredAtomicOr8", 19160 argLen: 3, 19161 faultOnNilArg0: true, 19162 hasSideEffects: true, 19163 asm: ppc64.AOR, 19164 reg: regInfo{ 19165 inputs: []inputInfo{ 19166 {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19167 {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 19168 }, 19169 }, 19170 }, 19171 { 19172 name: "InvertFlags", 19173 argLen: 1, 19174 reg: regInfo{}, 19175 }, 19176 { 19177 name: "FlagEQ", 19178 argLen: 0, 19179 reg: regInfo{}, 19180 }, 19181 { 19182 name: "FlagLT", 19183 argLen: 0, 19184 reg: regInfo{}, 19185 }, 19186 { 19187 name: "FlagGT", 19188 argLen: 0, 19189 reg: regInfo{}, 19190 }, 19191 19192 { 19193 name: "FADDS", 19194 argLen: 2, 19195 commutative: true, 19196 resultInArg0: true, 19197 clobberFlags: true, 19198 asm: s390x.AFADDS, 19199 reg: regInfo{ 19200 inputs: []inputInfo{ 19201 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19202 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19203 }, 19204 outputs: []outputInfo{ 19205 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19206 }, 19207 }, 19208 }, 19209 { 19210 name: "FADD", 19211 argLen: 2, 19212 commutative: true, 19213 resultInArg0: true, 19214 clobberFlags: true, 19215 asm: s390x.AFADD, 19216 reg: regInfo{ 19217 inputs: []inputInfo{ 19218 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19219 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19220 }, 19221 outputs: []outputInfo{ 19222 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19223 }, 19224 }, 19225 }, 19226 { 19227 name: "FSUBS", 19228 argLen: 2, 19229 resultInArg0: true, 19230 clobberFlags: true, 19231 asm: s390x.AFSUBS, 19232 reg: regInfo{ 19233 inputs: []inputInfo{ 19234 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19235 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19236 }, 19237 outputs: []outputInfo{ 19238 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19239 }, 19240 }, 19241 }, 19242 { 19243 name: "FSUB", 19244 argLen: 2, 19245 resultInArg0: true, 19246 clobberFlags: true, 19247 asm: s390x.AFSUB, 19248 reg: regInfo{ 19249 inputs: []inputInfo{ 19250 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19251 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19252 }, 19253 outputs: []outputInfo{ 19254 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19255 }, 19256 }, 19257 }, 19258 { 19259 name: "FMULS", 19260 argLen: 2, 19261 commutative: true, 19262 resultInArg0: true, 19263 asm: s390x.AFMULS, 19264 reg: regInfo{ 19265 inputs: []inputInfo{ 19266 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19267 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19268 }, 19269 outputs: []outputInfo{ 19270 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19271 }, 19272 }, 19273 }, 19274 { 19275 name: "FMUL", 19276 argLen: 2, 19277 commutative: true, 19278 resultInArg0: true, 19279 asm: s390x.AFMUL, 19280 reg: regInfo{ 19281 inputs: []inputInfo{ 19282 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19283 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19284 }, 19285 outputs: []outputInfo{ 19286 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19287 }, 19288 }, 19289 }, 19290 { 19291 name: "FDIVS", 19292 argLen: 2, 19293 resultInArg0: true, 19294 asm: s390x.AFDIVS, 19295 reg: regInfo{ 19296 inputs: []inputInfo{ 19297 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19298 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19299 }, 19300 outputs: []outputInfo{ 19301 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19302 }, 19303 }, 19304 }, 19305 { 19306 name: "FDIV", 19307 argLen: 2, 19308 resultInArg0: true, 19309 asm: s390x.AFDIV, 19310 reg: regInfo{ 19311 inputs: []inputInfo{ 19312 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19313 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19314 }, 19315 outputs: []outputInfo{ 19316 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19317 }, 19318 }, 19319 }, 19320 { 19321 name: "FNEGS", 19322 argLen: 1, 19323 clobberFlags: true, 19324 asm: s390x.AFNEGS, 19325 reg: regInfo{ 19326 inputs: []inputInfo{ 19327 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19328 }, 19329 outputs: []outputInfo{ 19330 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19331 }, 19332 }, 19333 }, 19334 { 19335 name: "FNEG", 19336 argLen: 1, 19337 clobberFlags: true, 19338 asm: s390x.AFNEG, 19339 reg: regInfo{ 19340 inputs: []inputInfo{ 19341 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19342 }, 19343 outputs: []outputInfo{ 19344 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19345 }, 19346 }, 19347 }, 19348 { 19349 name: "FMADDS", 19350 argLen: 3, 19351 resultInArg0: true, 19352 asm: s390x.AFMADDS, 19353 reg: regInfo{ 19354 inputs: []inputInfo{ 19355 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19356 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19357 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19358 }, 19359 outputs: []outputInfo{ 19360 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19361 }, 19362 }, 19363 }, 19364 { 19365 name: "FMADD", 19366 argLen: 3, 19367 resultInArg0: true, 19368 asm: s390x.AFMADD, 19369 reg: regInfo{ 19370 inputs: []inputInfo{ 19371 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19372 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19373 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19374 }, 19375 outputs: []outputInfo{ 19376 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19377 }, 19378 }, 19379 }, 19380 { 19381 name: "FMSUBS", 19382 argLen: 3, 19383 resultInArg0: true, 19384 asm: s390x.AFMSUBS, 19385 reg: regInfo{ 19386 inputs: []inputInfo{ 19387 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19388 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19389 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19390 }, 19391 outputs: []outputInfo{ 19392 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19393 }, 19394 }, 19395 }, 19396 { 19397 name: "FMSUB", 19398 argLen: 3, 19399 resultInArg0: true, 19400 asm: s390x.AFMSUB, 19401 reg: regInfo{ 19402 inputs: []inputInfo{ 19403 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19404 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19405 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19406 }, 19407 outputs: []outputInfo{ 19408 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19409 }, 19410 }, 19411 }, 19412 { 19413 name: "LPDFR", 19414 argLen: 1, 19415 asm: s390x.ALPDFR, 19416 reg: regInfo{ 19417 inputs: []inputInfo{ 19418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19419 }, 19420 outputs: []outputInfo{ 19421 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19422 }, 19423 }, 19424 }, 19425 { 19426 name: "LNDFR", 19427 argLen: 1, 19428 asm: s390x.ALNDFR, 19429 reg: regInfo{ 19430 inputs: []inputInfo{ 19431 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19432 }, 19433 outputs: []outputInfo{ 19434 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19435 }, 19436 }, 19437 }, 19438 { 19439 name: "CPSDR", 19440 argLen: 2, 19441 asm: s390x.ACPSDR, 19442 reg: regInfo{ 19443 inputs: []inputInfo{ 19444 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19445 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19446 }, 19447 outputs: []outputInfo{ 19448 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19449 }, 19450 }, 19451 }, 19452 { 19453 name: "FIDBR", 19454 auxType: auxInt8, 19455 argLen: 1, 19456 asm: s390x.AFIDBR, 19457 reg: regInfo{ 19458 inputs: []inputInfo{ 19459 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19460 }, 19461 outputs: []outputInfo{ 19462 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19463 }, 19464 }, 19465 }, 19466 { 19467 name: "FMOVSload", 19468 auxType: auxSymOff, 19469 argLen: 2, 19470 faultOnNilArg0: true, 19471 symEffect: SymRead, 19472 asm: s390x.AFMOVS, 19473 reg: regInfo{ 19474 inputs: []inputInfo{ 19475 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19476 }, 19477 outputs: []outputInfo{ 19478 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19479 }, 19480 }, 19481 }, 19482 { 19483 name: "FMOVDload", 19484 auxType: auxSymOff, 19485 argLen: 2, 19486 faultOnNilArg0: true, 19487 symEffect: SymRead, 19488 asm: s390x.AFMOVD, 19489 reg: regInfo{ 19490 inputs: []inputInfo{ 19491 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19492 }, 19493 outputs: []outputInfo{ 19494 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19495 }, 19496 }, 19497 }, 19498 { 19499 name: "FMOVSconst", 19500 auxType: auxFloat32, 19501 argLen: 0, 19502 rematerializeable: true, 19503 asm: s390x.AFMOVS, 19504 reg: regInfo{ 19505 outputs: []outputInfo{ 19506 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19507 }, 19508 }, 19509 }, 19510 { 19511 name: "FMOVDconst", 19512 auxType: auxFloat64, 19513 argLen: 0, 19514 rematerializeable: true, 19515 asm: s390x.AFMOVD, 19516 reg: regInfo{ 19517 outputs: []outputInfo{ 19518 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19519 }, 19520 }, 19521 }, 19522 { 19523 name: "FMOVSloadidx", 19524 auxType: auxSymOff, 19525 argLen: 3, 19526 symEffect: SymRead, 19527 asm: s390x.AFMOVS, 19528 reg: regInfo{ 19529 inputs: []inputInfo{ 19530 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19531 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19532 }, 19533 outputs: []outputInfo{ 19534 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19535 }, 19536 }, 19537 }, 19538 { 19539 name: "FMOVDloadidx", 19540 auxType: auxSymOff, 19541 argLen: 3, 19542 symEffect: SymRead, 19543 asm: s390x.AFMOVD, 19544 reg: regInfo{ 19545 inputs: []inputInfo{ 19546 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19547 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19548 }, 19549 outputs: []outputInfo{ 19550 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19551 }, 19552 }, 19553 }, 19554 { 19555 name: "FMOVSstore", 19556 auxType: auxSymOff, 19557 argLen: 3, 19558 faultOnNilArg0: true, 19559 symEffect: SymWrite, 19560 asm: s390x.AFMOVS, 19561 reg: regInfo{ 19562 inputs: []inputInfo{ 19563 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19564 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19565 }, 19566 }, 19567 }, 19568 { 19569 name: "FMOVDstore", 19570 auxType: auxSymOff, 19571 argLen: 3, 19572 faultOnNilArg0: true, 19573 symEffect: SymWrite, 19574 asm: s390x.AFMOVD, 19575 reg: regInfo{ 19576 inputs: []inputInfo{ 19577 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 19578 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19579 }, 19580 }, 19581 }, 19582 { 19583 name: "FMOVSstoreidx", 19584 auxType: auxSymOff, 19585 argLen: 4, 19586 symEffect: SymWrite, 19587 asm: s390x.AFMOVS, 19588 reg: regInfo{ 19589 inputs: []inputInfo{ 19590 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19591 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19592 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19593 }, 19594 }, 19595 }, 19596 { 19597 name: "FMOVDstoreidx", 19598 auxType: auxSymOff, 19599 argLen: 4, 19600 symEffect: SymWrite, 19601 asm: s390x.AFMOVD, 19602 reg: regInfo{ 19603 inputs: []inputInfo{ 19604 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19605 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19606 {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 19607 }, 19608 }, 19609 }, 19610 { 19611 name: "ADD", 19612 argLen: 2, 19613 commutative: true, 19614 clobberFlags: true, 19615 asm: s390x.AADD, 19616 reg: regInfo{ 19617 inputs: []inputInfo{ 19618 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19619 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19620 }, 19621 outputs: []outputInfo{ 19622 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19623 }, 19624 }, 19625 }, 19626 { 19627 name: "ADDW", 19628 argLen: 2, 19629 commutative: true, 19630 clobberFlags: true, 19631 asm: s390x.AADDW, 19632 reg: regInfo{ 19633 inputs: []inputInfo{ 19634 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19635 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19636 }, 19637 outputs: []outputInfo{ 19638 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19639 }, 19640 }, 19641 }, 19642 { 19643 name: "ADDconst", 19644 auxType: auxInt32, 19645 argLen: 1, 19646 clobberFlags: true, 19647 asm: s390x.AADD, 19648 reg: regInfo{ 19649 inputs: []inputInfo{ 19650 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19651 }, 19652 outputs: []outputInfo{ 19653 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19654 }, 19655 }, 19656 }, 19657 { 19658 name: "ADDWconst", 19659 auxType: auxInt32, 19660 argLen: 1, 19661 clobberFlags: true, 19662 asm: s390x.AADDW, 19663 reg: regInfo{ 19664 inputs: []inputInfo{ 19665 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19666 }, 19667 outputs: []outputInfo{ 19668 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19669 }, 19670 }, 19671 }, 19672 { 19673 name: "ADDload", 19674 auxType: auxSymOff, 19675 argLen: 3, 19676 resultInArg0: true, 19677 clobberFlags: true, 19678 faultOnNilArg1: true, 19679 symEffect: SymRead, 19680 asm: s390x.AADD, 19681 reg: regInfo{ 19682 inputs: []inputInfo{ 19683 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19684 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19685 }, 19686 outputs: []outputInfo{ 19687 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19688 }, 19689 }, 19690 }, 19691 { 19692 name: "ADDWload", 19693 auxType: auxSymOff, 19694 argLen: 3, 19695 resultInArg0: true, 19696 clobberFlags: true, 19697 faultOnNilArg1: true, 19698 symEffect: SymRead, 19699 asm: s390x.AADDW, 19700 reg: regInfo{ 19701 inputs: []inputInfo{ 19702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19703 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19704 }, 19705 outputs: []outputInfo{ 19706 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19707 }, 19708 }, 19709 }, 19710 { 19711 name: "SUB", 19712 argLen: 2, 19713 clobberFlags: true, 19714 asm: s390x.ASUB, 19715 reg: regInfo{ 19716 inputs: []inputInfo{ 19717 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19718 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19719 }, 19720 outputs: []outputInfo{ 19721 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19722 }, 19723 }, 19724 }, 19725 { 19726 name: "SUBW", 19727 argLen: 2, 19728 clobberFlags: true, 19729 asm: s390x.ASUBW, 19730 reg: regInfo{ 19731 inputs: []inputInfo{ 19732 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19733 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19734 }, 19735 outputs: []outputInfo{ 19736 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19737 }, 19738 }, 19739 }, 19740 { 19741 name: "SUBconst", 19742 auxType: auxInt32, 19743 argLen: 1, 19744 resultInArg0: true, 19745 clobberFlags: true, 19746 asm: s390x.ASUB, 19747 reg: regInfo{ 19748 inputs: []inputInfo{ 19749 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19750 }, 19751 outputs: []outputInfo{ 19752 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19753 }, 19754 }, 19755 }, 19756 { 19757 name: "SUBWconst", 19758 auxType: auxInt32, 19759 argLen: 1, 19760 resultInArg0: true, 19761 clobberFlags: true, 19762 asm: s390x.ASUBW, 19763 reg: regInfo{ 19764 inputs: []inputInfo{ 19765 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19766 }, 19767 outputs: []outputInfo{ 19768 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19769 }, 19770 }, 19771 }, 19772 { 19773 name: "SUBload", 19774 auxType: auxSymOff, 19775 argLen: 3, 19776 resultInArg0: true, 19777 clobberFlags: true, 19778 faultOnNilArg1: true, 19779 symEffect: SymRead, 19780 asm: s390x.ASUB, 19781 reg: regInfo{ 19782 inputs: []inputInfo{ 19783 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19784 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19785 }, 19786 outputs: []outputInfo{ 19787 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19788 }, 19789 }, 19790 }, 19791 { 19792 name: "SUBWload", 19793 auxType: auxSymOff, 19794 argLen: 3, 19795 resultInArg0: true, 19796 clobberFlags: true, 19797 faultOnNilArg1: true, 19798 symEffect: SymRead, 19799 asm: s390x.ASUBW, 19800 reg: regInfo{ 19801 inputs: []inputInfo{ 19802 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19803 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19804 }, 19805 outputs: []outputInfo{ 19806 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19807 }, 19808 }, 19809 }, 19810 { 19811 name: "MULLD", 19812 argLen: 2, 19813 commutative: true, 19814 resultInArg0: true, 19815 clobberFlags: true, 19816 asm: s390x.AMULLD, 19817 reg: regInfo{ 19818 inputs: []inputInfo{ 19819 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19820 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19821 }, 19822 outputs: []outputInfo{ 19823 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19824 }, 19825 }, 19826 }, 19827 { 19828 name: "MULLW", 19829 argLen: 2, 19830 commutative: true, 19831 resultInArg0: true, 19832 clobberFlags: true, 19833 asm: s390x.AMULLW, 19834 reg: regInfo{ 19835 inputs: []inputInfo{ 19836 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19837 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19838 }, 19839 outputs: []outputInfo{ 19840 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19841 }, 19842 }, 19843 }, 19844 { 19845 name: "MULLDconst", 19846 auxType: auxInt32, 19847 argLen: 1, 19848 resultInArg0: true, 19849 clobberFlags: true, 19850 asm: s390x.AMULLD, 19851 reg: regInfo{ 19852 inputs: []inputInfo{ 19853 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19854 }, 19855 outputs: []outputInfo{ 19856 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19857 }, 19858 }, 19859 }, 19860 { 19861 name: "MULLWconst", 19862 auxType: auxInt32, 19863 argLen: 1, 19864 resultInArg0: true, 19865 clobberFlags: true, 19866 asm: s390x.AMULLW, 19867 reg: regInfo{ 19868 inputs: []inputInfo{ 19869 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19870 }, 19871 outputs: []outputInfo{ 19872 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19873 }, 19874 }, 19875 }, 19876 { 19877 name: "MULLDload", 19878 auxType: auxSymOff, 19879 argLen: 3, 19880 resultInArg0: true, 19881 clobberFlags: true, 19882 faultOnNilArg1: true, 19883 symEffect: SymRead, 19884 asm: s390x.AMULLD, 19885 reg: regInfo{ 19886 inputs: []inputInfo{ 19887 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19888 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19889 }, 19890 outputs: []outputInfo{ 19891 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19892 }, 19893 }, 19894 }, 19895 { 19896 name: "MULLWload", 19897 auxType: auxSymOff, 19898 argLen: 3, 19899 resultInArg0: true, 19900 clobberFlags: true, 19901 faultOnNilArg1: true, 19902 symEffect: SymRead, 19903 asm: s390x.AMULLW, 19904 reg: regInfo{ 19905 inputs: []inputInfo{ 19906 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19907 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 19908 }, 19909 outputs: []outputInfo{ 19910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19911 }, 19912 }, 19913 }, 19914 { 19915 name: "MULHD", 19916 argLen: 2, 19917 commutative: true, 19918 resultInArg0: true, 19919 clobberFlags: true, 19920 asm: s390x.AMULHD, 19921 reg: regInfo{ 19922 inputs: []inputInfo{ 19923 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19924 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19925 }, 19926 outputs: []outputInfo{ 19927 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19928 }, 19929 }, 19930 }, 19931 { 19932 name: "MULHDU", 19933 argLen: 2, 19934 commutative: true, 19935 resultInArg0: true, 19936 clobberFlags: true, 19937 asm: s390x.AMULHDU, 19938 reg: regInfo{ 19939 inputs: []inputInfo{ 19940 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19941 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19942 }, 19943 outputs: []outputInfo{ 19944 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19945 }, 19946 }, 19947 }, 19948 { 19949 name: "DIVD", 19950 argLen: 2, 19951 resultInArg0: true, 19952 clobberFlags: true, 19953 asm: s390x.ADIVD, 19954 reg: regInfo{ 19955 inputs: []inputInfo{ 19956 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19957 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19958 }, 19959 outputs: []outputInfo{ 19960 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19961 }, 19962 }, 19963 }, 19964 { 19965 name: "DIVW", 19966 argLen: 2, 19967 resultInArg0: true, 19968 clobberFlags: true, 19969 asm: s390x.ADIVW, 19970 reg: regInfo{ 19971 inputs: []inputInfo{ 19972 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19973 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19974 }, 19975 outputs: []outputInfo{ 19976 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19977 }, 19978 }, 19979 }, 19980 { 19981 name: "DIVDU", 19982 argLen: 2, 19983 resultInArg0: true, 19984 clobberFlags: true, 19985 asm: s390x.ADIVDU, 19986 reg: regInfo{ 19987 inputs: []inputInfo{ 19988 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19989 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19990 }, 19991 outputs: []outputInfo{ 19992 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 19993 }, 19994 }, 19995 }, 19996 { 19997 name: "DIVWU", 19998 argLen: 2, 19999 resultInArg0: true, 20000 clobberFlags: true, 20001 asm: s390x.ADIVWU, 20002 reg: regInfo{ 20003 inputs: []inputInfo{ 20004 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20005 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20006 }, 20007 outputs: []outputInfo{ 20008 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20009 }, 20010 }, 20011 }, 20012 { 20013 name: "MODD", 20014 argLen: 2, 20015 resultInArg0: true, 20016 clobberFlags: true, 20017 asm: s390x.AMODD, 20018 reg: regInfo{ 20019 inputs: []inputInfo{ 20020 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20021 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20022 }, 20023 outputs: []outputInfo{ 20024 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20025 }, 20026 }, 20027 }, 20028 { 20029 name: "MODW", 20030 argLen: 2, 20031 resultInArg0: true, 20032 clobberFlags: true, 20033 asm: s390x.AMODW, 20034 reg: regInfo{ 20035 inputs: []inputInfo{ 20036 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20037 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20038 }, 20039 outputs: []outputInfo{ 20040 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20041 }, 20042 }, 20043 }, 20044 { 20045 name: "MODDU", 20046 argLen: 2, 20047 resultInArg0: true, 20048 clobberFlags: true, 20049 asm: s390x.AMODDU, 20050 reg: regInfo{ 20051 inputs: []inputInfo{ 20052 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20053 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20054 }, 20055 outputs: []outputInfo{ 20056 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20057 }, 20058 }, 20059 }, 20060 { 20061 name: "MODWU", 20062 argLen: 2, 20063 resultInArg0: true, 20064 clobberFlags: true, 20065 asm: s390x.AMODWU, 20066 reg: regInfo{ 20067 inputs: []inputInfo{ 20068 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20069 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20070 }, 20071 outputs: []outputInfo{ 20072 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20073 }, 20074 }, 20075 }, 20076 { 20077 name: "AND", 20078 argLen: 2, 20079 commutative: true, 20080 clobberFlags: true, 20081 asm: s390x.AAND, 20082 reg: regInfo{ 20083 inputs: []inputInfo{ 20084 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20085 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20086 }, 20087 outputs: []outputInfo{ 20088 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20089 }, 20090 }, 20091 }, 20092 { 20093 name: "ANDW", 20094 argLen: 2, 20095 commutative: true, 20096 clobberFlags: true, 20097 asm: s390x.AANDW, 20098 reg: regInfo{ 20099 inputs: []inputInfo{ 20100 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20101 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20102 }, 20103 outputs: []outputInfo{ 20104 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20105 }, 20106 }, 20107 }, 20108 { 20109 name: "ANDconst", 20110 auxType: auxInt64, 20111 argLen: 1, 20112 resultInArg0: true, 20113 clobberFlags: true, 20114 asm: s390x.AAND, 20115 reg: regInfo{ 20116 inputs: []inputInfo{ 20117 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20118 }, 20119 outputs: []outputInfo{ 20120 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20121 }, 20122 }, 20123 }, 20124 { 20125 name: "ANDWconst", 20126 auxType: auxInt32, 20127 argLen: 1, 20128 resultInArg0: true, 20129 clobberFlags: true, 20130 asm: s390x.AANDW, 20131 reg: regInfo{ 20132 inputs: []inputInfo{ 20133 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20134 }, 20135 outputs: []outputInfo{ 20136 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20137 }, 20138 }, 20139 }, 20140 { 20141 name: "ANDload", 20142 auxType: auxSymOff, 20143 argLen: 3, 20144 resultInArg0: true, 20145 clobberFlags: true, 20146 faultOnNilArg1: true, 20147 symEffect: SymRead, 20148 asm: s390x.AAND, 20149 reg: regInfo{ 20150 inputs: []inputInfo{ 20151 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20152 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20153 }, 20154 outputs: []outputInfo{ 20155 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20156 }, 20157 }, 20158 }, 20159 { 20160 name: "ANDWload", 20161 auxType: auxSymOff, 20162 argLen: 3, 20163 resultInArg0: true, 20164 clobberFlags: true, 20165 faultOnNilArg1: true, 20166 symEffect: SymRead, 20167 asm: s390x.AANDW, 20168 reg: regInfo{ 20169 inputs: []inputInfo{ 20170 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20171 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20172 }, 20173 outputs: []outputInfo{ 20174 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20175 }, 20176 }, 20177 }, 20178 { 20179 name: "OR", 20180 argLen: 2, 20181 commutative: true, 20182 clobberFlags: true, 20183 asm: s390x.AOR, 20184 reg: regInfo{ 20185 inputs: []inputInfo{ 20186 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20187 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20188 }, 20189 outputs: []outputInfo{ 20190 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20191 }, 20192 }, 20193 }, 20194 { 20195 name: "ORW", 20196 argLen: 2, 20197 commutative: true, 20198 clobberFlags: true, 20199 asm: s390x.AORW, 20200 reg: regInfo{ 20201 inputs: []inputInfo{ 20202 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20203 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20204 }, 20205 outputs: []outputInfo{ 20206 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20207 }, 20208 }, 20209 }, 20210 { 20211 name: "ORconst", 20212 auxType: auxInt64, 20213 argLen: 1, 20214 resultInArg0: true, 20215 clobberFlags: true, 20216 asm: s390x.AOR, 20217 reg: regInfo{ 20218 inputs: []inputInfo{ 20219 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20220 }, 20221 outputs: []outputInfo{ 20222 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20223 }, 20224 }, 20225 }, 20226 { 20227 name: "ORWconst", 20228 auxType: auxInt32, 20229 argLen: 1, 20230 resultInArg0: true, 20231 clobberFlags: true, 20232 asm: s390x.AORW, 20233 reg: regInfo{ 20234 inputs: []inputInfo{ 20235 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20236 }, 20237 outputs: []outputInfo{ 20238 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20239 }, 20240 }, 20241 }, 20242 { 20243 name: "ORload", 20244 auxType: auxSymOff, 20245 argLen: 3, 20246 resultInArg0: true, 20247 clobberFlags: true, 20248 faultOnNilArg1: true, 20249 symEffect: SymRead, 20250 asm: s390x.AOR, 20251 reg: regInfo{ 20252 inputs: []inputInfo{ 20253 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20254 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20255 }, 20256 outputs: []outputInfo{ 20257 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20258 }, 20259 }, 20260 }, 20261 { 20262 name: "ORWload", 20263 auxType: auxSymOff, 20264 argLen: 3, 20265 resultInArg0: true, 20266 clobberFlags: true, 20267 faultOnNilArg1: true, 20268 symEffect: SymRead, 20269 asm: s390x.AORW, 20270 reg: regInfo{ 20271 inputs: []inputInfo{ 20272 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20273 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20274 }, 20275 outputs: []outputInfo{ 20276 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20277 }, 20278 }, 20279 }, 20280 { 20281 name: "XOR", 20282 argLen: 2, 20283 commutative: true, 20284 clobberFlags: true, 20285 asm: s390x.AXOR, 20286 reg: regInfo{ 20287 inputs: []inputInfo{ 20288 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20289 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20290 }, 20291 outputs: []outputInfo{ 20292 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20293 }, 20294 }, 20295 }, 20296 { 20297 name: "XORW", 20298 argLen: 2, 20299 commutative: true, 20300 clobberFlags: true, 20301 asm: s390x.AXORW, 20302 reg: regInfo{ 20303 inputs: []inputInfo{ 20304 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20305 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20306 }, 20307 outputs: []outputInfo{ 20308 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20309 }, 20310 }, 20311 }, 20312 { 20313 name: "XORconst", 20314 auxType: auxInt64, 20315 argLen: 1, 20316 resultInArg0: true, 20317 clobberFlags: true, 20318 asm: s390x.AXOR, 20319 reg: regInfo{ 20320 inputs: []inputInfo{ 20321 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20322 }, 20323 outputs: []outputInfo{ 20324 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20325 }, 20326 }, 20327 }, 20328 { 20329 name: "XORWconst", 20330 auxType: auxInt32, 20331 argLen: 1, 20332 resultInArg0: true, 20333 clobberFlags: true, 20334 asm: s390x.AXORW, 20335 reg: regInfo{ 20336 inputs: []inputInfo{ 20337 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20338 }, 20339 outputs: []outputInfo{ 20340 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20341 }, 20342 }, 20343 }, 20344 { 20345 name: "XORload", 20346 auxType: auxSymOff, 20347 argLen: 3, 20348 resultInArg0: true, 20349 clobberFlags: true, 20350 faultOnNilArg1: true, 20351 symEffect: SymRead, 20352 asm: s390x.AXOR, 20353 reg: regInfo{ 20354 inputs: []inputInfo{ 20355 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20356 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20357 }, 20358 outputs: []outputInfo{ 20359 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20360 }, 20361 }, 20362 }, 20363 { 20364 name: "XORWload", 20365 auxType: auxSymOff, 20366 argLen: 3, 20367 resultInArg0: true, 20368 clobberFlags: true, 20369 faultOnNilArg1: true, 20370 symEffect: SymRead, 20371 asm: s390x.AXORW, 20372 reg: regInfo{ 20373 inputs: []inputInfo{ 20374 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20375 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20376 }, 20377 outputs: []outputInfo{ 20378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20379 }, 20380 }, 20381 }, 20382 { 20383 name: "CMP", 20384 argLen: 2, 20385 asm: s390x.ACMP, 20386 reg: regInfo{ 20387 inputs: []inputInfo{ 20388 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20389 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20390 }, 20391 }, 20392 }, 20393 { 20394 name: "CMPW", 20395 argLen: 2, 20396 asm: s390x.ACMPW, 20397 reg: regInfo{ 20398 inputs: []inputInfo{ 20399 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20400 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20401 }, 20402 }, 20403 }, 20404 { 20405 name: "CMPU", 20406 argLen: 2, 20407 asm: s390x.ACMPU, 20408 reg: regInfo{ 20409 inputs: []inputInfo{ 20410 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20411 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20412 }, 20413 }, 20414 }, 20415 { 20416 name: "CMPWU", 20417 argLen: 2, 20418 asm: s390x.ACMPWU, 20419 reg: regInfo{ 20420 inputs: []inputInfo{ 20421 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20422 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20423 }, 20424 }, 20425 }, 20426 { 20427 name: "CMPconst", 20428 auxType: auxInt32, 20429 argLen: 1, 20430 asm: s390x.ACMP, 20431 reg: regInfo{ 20432 inputs: []inputInfo{ 20433 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20434 }, 20435 }, 20436 }, 20437 { 20438 name: "CMPWconst", 20439 auxType: auxInt32, 20440 argLen: 1, 20441 asm: s390x.ACMPW, 20442 reg: regInfo{ 20443 inputs: []inputInfo{ 20444 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20445 }, 20446 }, 20447 }, 20448 { 20449 name: "CMPUconst", 20450 auxType: auxInt32, 20451 argLen: 1, 20452 asm: s390x.ACMPU, 20453 reg: regInfo{ 20454 inputs: []inputInfo{ 20455 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20456 }, 20457 }, 20458 }, 20459 { 20460 name: "CMPWUconst", 20461 auxType: auxInt32, 20462 argLen: 1, 20463 asm: s390x.ACMPWU, 20464 reg: regInfo{ 20465 inputs: []inputInfo{ 20466 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20467 }, 20468 }, 20469 }, 20470 { 20471 name: "FCMPS", 20472 argLen: 2, 20473 asm: s390x.ACEBR, 20474 reg: regInfo{ 20475 inputs: []inputInfo{ 20476 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20477 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20478 }, 20479 }, 20480 }, 20481 { 20482 name: "FCMP", 20483 argLen: 2, 20484 asm: s390x.AFCMPU, 20485 reg: regInfo{ 20486 inputs: []inputInfo{ 20487 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20488 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20489 }, 20490 }, 20491 }, 20492 { 20493 name: "SLD", 20494 argLen: 2, 20495 asm: s390x.ASLD, 20496 reg: regInfo{ 20497 inputs: []inputInfo{ 20498 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20499 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20500 }, 20501 outputs: []outputInfo{ 20502 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20503 }, 20504 }, 20505 }, 20506 { 20507 name: "SLW", 20508 argLen: 2, 20509 asm: s390x.ASLW, 20510 reg: regInfo{ 20511 inputs: []inputInfo{ 20512 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20513 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20514 }, 20515 outputs: []outputInfo{ 20516 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20517 }, 20518 }, 20519 }, 20520 { 20521 name: "SLDconst", 20522 auxType: auxInt8, 20523 argLen: 1, 20524 asm: s390x.ASLD, 20525 reg: regInfo{ 20526 inputs: []inputInfo{ 20527 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20528 }, 20529 outputs: []outputInfo{ 20530 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20531 }, 20532 }, 20533 }, 20534 { 20535 name: "SLWconst", 20536 auxType: auxInt8, 20537 argLen: 1, 20538 asm: s390x.ASLW, 20539 reg: regInfo{ 20540 inputs: []inputInfo{ 20541 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20542 }, 20543 outputs: []outputInfo{ 20544 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20545 }, 20546 }, 20547 }, 20548 { 20549 name: "SRD", 20550 argLen: 2, 20551 asm: s390x.ASRD, 20552 reg: regInfo{ 20553 inputs: []inputInfo{ 20554 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20555 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20556 }, 20557 outputs: []outputInfo{ 20558 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20559 }, 20560 }, 20561 }, 20562 { 20563 name: "SRW", 20564 argLen: 2, 20565 asm: s390x.ASRW, 20566 reg: regInfo{ 20567 inputs: []inputInfo{ 20568 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20569 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20570 }, 20571 outputs: []outputInfo{ 20572 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20573 }, 20574 }, 20575 }, 20576 { 20577 name: "SRDconst", 20578 auxType: auxInt8, 20579 argLen: 1, 20580 asm: s390x.ASRD, 20581 reg: regInfo{ 20582 inputs: []inputInfo{ 20583 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20584 }, 20585 outputs: []outputInfo{ 20586 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20587 }, 20588 }, 20589 }, 20590 { 20591 name: "SRWconst", 20592 auxType: auxInt8, 20593 argLen: 1, 20594 asm: s390x.ASRW, 20595 reg: regInfo{ 20596 inputs: []inputInfo{ 20597 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20598 }, 20599 outputs: []outputInfo{ 20600 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20601 }, 20602 }, 20603 }, 20604 { 20605 name: "SRAD", 20606 argLen: 2, 20607 clobberFlags: true, 20608 asm: s390x.ASRAD, 20609 reg: regInfo{ 20610 inputs: []inputInfo{ 20611 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20612 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20613 }, 20614 outputs: []outputInfo{ 20615 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20616 }, 20617 }, 20618 }, 20619 { 20620 name: "SRAW", 20621 argLen: 2, 20622 clobberFlags: true, 20623 asm: s390x.ASRAW, 20624 reg: regInfo{ 20625 inputs: []inputInfo{ 20626 {1, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20627 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20628 }, 20629 outputs: []outputInfo{ 20630 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20631 }, 20632 }, 20633 }, 20634 { 20635 name: "SRADconst", 20636 auxType: auxInt8, 20637 argLen: 1, 20638 clobberFlags: true, 20639 asm: s390x.ASRAD, 20640 reg: regInfo{ 20641 inputs: []inputInfo{ 20642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20643 }, 20644 outputs: []outputInfo{ 20645 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20646 }, 20647 }, 20648 }, 20649 { 20650 name: "SRAWconst", 20651 auxType: auxInt8, 20652 argLen: 1, 20653 clobberFlags: true, 20654 asm: s390x.ASRAW, 20655 reg: regInfo{ 20656 inputs: []inputInfo{ 20657 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20658 }, 20659 outputs: []outputInfo{ 20660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20661 }, 20662 }, 20663 }, 20664 { 20665 name: "RLLGconst", 20666 auxType: auxInt8, 20667 argLen: 1, 20668 asm: s390x.ARLLG, 20669 reg: regInfo{ 20670 inputs: []inputInfo{ 20671 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20672 }, 20673 outputs: []outputInfo{ 20674 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20675 }, 20676 }, 20677 }, 20678 { 20679 name: "RLLconst", 20680 auxType: auxInt8, 20681 argLen: 1, 20682 asm: s390x.ARLL, 20683 reg: regInfo{ 20684 inputs: []inputInfo{ 20685 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20686 }, 20687 outputs: []outputInfo{ 20688 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20689 }, 20690 }, 20691 }, 20692 { 20693 name: "NEG", 20694 argLen: 1, 20695 clobberFlags: true, 20696 asm: s390x.ANEG, 20697 reg: regInfo{ 20698 inputs: []inputInfo{ 20699 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20700 }, 20701 outputs: []outputInfo{ 20702 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20703 }, 20704 }, 20705 }, 20706 { 20707 name: "NEGW", 20708 argLen: 1, 20709 clobberFlags: true, 20710 asm: s390x.ANEGW, 20711 reg: regInfo{ 20712 inputs: []inputInfo{ 20713 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20714 }, 20715 outputs: []outputInfo{ 20716 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20717 }, 20718 }, 20719 }, 20720 { 20721 name: "NOT", 20722 argLen: 1, 20723 resultInArg0: true, 20724 clobberFlags: true, 20725 reg: regInfo{ 20726 inputs: []inputInfo{ 20727 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20728 }, 20729 outputs: []outputInfo{ 20730 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20731 }, 20732 }, 20733 }, 20734 { 20735 name: "NOTW", 20736 argLen: 1, 20737 resultInArg0: true, 20738 clobberFlags: true, 20739 reg: regInfo{ 20740 inputs: []inputInfo{ 20741 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20742 }, 20743 outputs: []outputInfo{ 20744 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20745 }, 20746 }, 20747 }, 20748 { 20749 name: "FSQRT", 20750 argLen: 1, 20751 asm: s390x.AFSQRT, 20752 reg: regInfo{ 20753 inputs: []inputInfo{ 20754 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20755 }, 20756 outputs: []outputInfo{ 20757 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 20758 }, 20759 }, 20760 }, 20761 { 20762 name: "SUBEcarrymask", 20763 argLen: 1, 20764 asm: s390x.ASUBE, 20765 reg: regInfo{ 20766 outputs: []outputInfo{ 20767 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20768 }, 20769 }, 20770 }, 20771 { 20772 name: "SUBEWcarrymask", 20773 argLen: 1, 20774 asm: s390x.ASUBE, 20775 reg: regInfo{ 20776 outputs: []outputInfo{ 20777 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20778 }, 20779 }, 20780 }, 20781 { 20782 name: "MOVDEQ", 20783 argLen: 3, 20784 resultInArg0: true, 20785 asm: s390x.AMOVDEQ, 20786 reg: regInfo{ 20787 inputs: []inputInfo{ 20788 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20789 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20790 }, 20791 outputs: []outputInfo{ 20792 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20793 }, 20794 }, 20795 }, 20796 { 20797 name: "MOVDNE", 20798 argLen: 3, 20799 resultInArg0: true, 20800 asm: s390x.AMOVDNE, 20801 reg: regInfo{ 20802 inputs: []inputInfo{ 20803 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20804 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20805 }, 20806 outputs: []outputInfo{ 20807 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20808 }, 20809 }, 20810 }, 20811 { 20812 name: "MOVDLT", 20813 argLen: 3, 20814 resultInArg0: true, 20815 asm: s390x.AMOVDLT, 20816 reg: regInfo{ 20817 inputs: []inputInfo{ 20818 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20819 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20820 }, 20821 outputs: []outputInfo{ 20822 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20823 }, 20824 }, 20825 }, 20826 { 20827 name: "MOVDLE", 20828 argLen: 3, 20829 resultInArg0: true, 20830 asm: s390x.AMOVDLE, 20831 reg: regInfo{ 20832 inputs: []inputInfo{ 20833 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20834 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20835 }, 20836 outputs: []outputInfo{ 20837 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20838 }, 20839 }, 20840 }, 20841 { 20842 name: "MOVDGT", 20843 argLen: 3, 20844 resultInArg0: true, 20845 asm: s390x.AMOVDGT, 20846 reg: regInfo{ 20847 inputs: []inputInfo{ 20848 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20849 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20850 }, 20851 outputs: []outputInfo{ 20852 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20853 }, 20854 }, 20855 }, 20856 { 20857 name: "MOVDGE", 20858 argLen: 3, 20859 resultInArg0: true, 20860 asm: s390x.AMOVDGE, 20861 reg: regInfo{ 20862 inputs: []inputInfo{ 20863 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20864 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20865 }, 20866 outputs: []outputInfo{ 20867 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20868 }, 20869 }, 20870 }, 20871 { 20872 name: "MOVDGTnoinv", 20873 argLen: 3, 20874 resultInArg0: true, 20875 asm: s390x.AMOVDGT, 20876 reg: regInfo{ 20877 inputs: []inputInfo{ 20878 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20879 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20880 }, 20881 outputs: []outputInfo{ 20882 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20883 }, 20884 }, 20885 }, 20886 { 20887 name: "MOVDGEnoinv", 20888 argLen: 3, 20889 resultInArg0: true, 20890 asm: s390x.AMOVDGE, 20891 reg: regInfo{ 20892 inputs: []inputInfo{ 20893 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20894 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20895 }, 20896 outputs: []outputInfo{ 20897 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20898 }, 20899 }, 20900 }, 20901 { 20902 name: "MOVBreg", 20903 argLen: 1, 20904 asm: s390x.AMOVB, 20905 reg: regInfo{ 20906 inputs: []inputInfo{ 20907 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20908 }, 20909 outputs: []outputInfo{ 20910 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20911 }, 20912 }, 20913 }, 20914 { 20915 name: "MOVBZreg", 20916 argLen: 1, 20917 asm: s390x.AMOVBZ, 20918 reg: regInfo{ 20919 inputs: []inputInfo{ 20920 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20921 }, 20922 outputs: []outputInfo{ 20923 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20924 }, 20925 }, 20926 }, 20927 { 20928 name: "MOVHreg", 20929 argLen: 1, 20930 asm: s390x.AMOVH, 20931 reg: regInfo{ 20932 inputs: []inputInfo{ 20933 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20934 }, 20935 outputs: []outputInfo{ 20936 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20937 }, 20938 }, 20939 }, 20940 { 20941 name: "MOVHZreg", 20942 argLen: 1, 20943 asm: s390x.AMOVHZ, 20944 reg: regInfo{ 20945 inputs: []inputInfo{ 20946 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20947 }, 20948 outputs: []outputInfo{ 20949 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20950 }, 20951 }, 20952 }, 20953 { 20954 name: "MOVWreg", 20955 argLen: 1, 20956 asm: s390x.AMOVW, 20957 reg: regInfo{ 20958 inputs: []inputInfo{ 20959 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20960 }, 20961 outputs: []outputInfo{ 20962 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20963 }, 20964 }, 20965 }, 20966 { 20967 name: "MOVWZreg", 20968 argLen: 1, 20969 asm: s390x.AMOVWZ, 20970 reg: regInfo{ 20971 inputs: []inputInfo{ 20972 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20973 }, 20974 outputs: []outputInfo{ 20975 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20976 }, 20977 }, 20978 }, 20979 { 20980 name: "MOVDreg", 20981 argLen: 1, 20982 asm: s390x.AMOVD, 20983 reg: regInfo{ 20984 inputs: []inputInfo{ 20985 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 20986 }, 20987 outputs: []outputInfo{ 20988 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20989 }, 20990 }, 20991 }, 20992 { 20993 name: "MOVDnop", 20994 argLen: 1, 20995 resultInArg0: true, 20996 reg: regInfo{ 20997 inputs: []inputInfo{ 20998 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 20999 }, 21000 outputs: []outputInfo{ 21001 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21002 }, 21003 }, 21004 }, 21005 { 21006 name: "MOVDconst", 21007 auxType: auxInt64, 21008 argLen: 0, 21009 rematerializeable: true, 21010 asm: s390x.AMOVD, 21011 reg: regInfo{ 21012 outputs: []outputInfo{ 21013 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21014 }, 21015 }, 21016 }, 21017 { 21018 name: "LDGR", 21019 argLen: 1, 21020 asm: s390x.ALDGR, 21021 reg: regInfo{ 21022 inputs: []inputInfo{ 21023 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21024 }, 21025 outputs: []outputInfo{ 21026 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21027 }, 21028 }, 21029 }, 21030 { 21031 name: "LGDR", 21032 argLen: 1, 21033 asm: s390x.ALGDR, 21034 reg: regInfo{ 21035 inputs: []inputInfo{ 21036 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21037 }, 21038 outputs: []outputInfo{ 21039 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21040 }, 21041 }, 21042 }, 21043 { 21044 name: "CFDBRA", 21045 argLen: 1, 21046 asm: s390x.ACFDBRA, 21047 reg: regInfo{ 21048 inputs: []inputInfo{ 21049 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21050 }, 21051 outputs: []outputInfo{ 21052 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21053 }, 21054 }, 21055 }, 21056 { 21057 name: "CGDBRA", 21058 argLen: 1, 21059 asm: s390x.ACGDBRA, 21060 reg: regInfo{ 21061 inputs: []inputInfo{ 21062 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21063 }, 21064 outputs: []outputInfo{ 21065 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21066 }, 21067 }, 21068 }, 21069 { 21070 name: "CFEBRA", 21071 argLen: 1, 21072 asm: s390x.ACFEBRA, 21073 reg: regInfo{ 21074 inputs: []inputInfo{ 21075 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21076 }, 21077 outputs: []outputInfo{ 21078 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21079 }, 21080 }, 21081 }, 21082 { 21083 name: "CGEBRA", 21084 argLen: 1, 21085 asm: s390x.ACGEBRA, 21086 reg: regInfo{ 21087 inputs: []inputInfo{ 21088 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21089 }, 21090 outputs: []outputInfo{ 21091 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21092 }, 21093 }, 21094 }, 21095 { 21096 name: "CEFBRA", 21097 argLen: 1, 21098 asm: s390x.ACEFBRA, 21099 reg: regInfo{ 21100 inputs: []inputInfo{ 21101 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21102 }, 21103 outputs: []outputInfo{ 21104 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21105 }, 21106 }, 21107 }, 21108 { 21109 name: "CDFBRA", 21110 argLen: 1, 21111 asm: s390x.ACDFBRA, 21112 reg: regInfo{ 21113 inputs: []inputInfo{ 21114 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21115 }, 21116 outputs: []outputInfo{ 21117 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21118 }, 21119 }, 21120 }, 21121 { 21122 name: "CEGBRA", 21123 argLen: 1, 21124 asm: s390x.ACEGBRA, 21125 reg: regInfo{ 21126 inputs: []inputInfo{ 21127 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21128 }, 21129 outputs: []outputInfo{ 21130 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21131 }, 21132 }, 21133 }, 21134 { 21135 name: "CDGBRA", 21136 argLen: 1, 21137 asm: s390x.ACDGBRA, 21138 reg: regInfo{ 21139 inputs: []inputInfo{ 21140 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21141 }, 21142 outputs: []outputInfo{ 21143 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21144 }, 21145 }, 21146 }, 21147 { 21148 name: "LEDBR", 21149 argLen: 1, 21150 asm: s390x.ALEDBR, 21151 reg: regInfo{ 21152 inputs: []inputInfo{ 21153 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21154 }, 21155 outputs: []outputInfo{ 21156 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21157 }, 21158 }, 21159 }, 21160 { 21161 name: "LDEBR", 21162 argLen: 1, 21163 asm: s390x.ALDEBR, 21164 reg: regInfo{ 21165 inputs: []inputInfo{ 21166 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21167 }, 21168 outputs: []outputInfo{ 21169 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21170 }, 21171 }, 21172 }, 21173 { 21174 name: "MOVDaddr", 21175 auxType: auxSymOff, 21176 argLen: 1, 21177 rematerializeable: true, 21178 symEffect: SymRead, 21179 reg: regInfo{ 21180 inputs: []inputInfo{ 21181 {0, 4295000064}, // SP SB 21182 }, 21183 outputs: []outputInfo{ 21184 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21185 }, 21186 }, 21187 }, 21188 { 21189 name: "MOVDaddridx", 21190 auxType: auxSymOff, 21191 argLen: 2, 21192 symEffect: SymRead, 21193 reg: regInfo{ 21194 inputs: []inputInfo{ 21195 {0, 4295000064}, // SP SB 21196 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21197 }, 21198 outputs: []outputInfo{ 21199 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21200 }, 21201 }, 21202 }, 21203 { 21204 name: "MOVBZload", 21205 auxType: auxSymOff, 21206 argLen: 2, 21207 clobberFlags: true, 21208 faultOnNilArg0: true, 21209 symEffect: SymRead, 21210 asm: s390x.AMOVBZ, 21211 reg: regInfo{ 21212 inputs: []inputInfo{ 21213 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21214 }, 21215 outputs: []outputInfo{ 21216 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21217 }, 21218 }, 21219 }, 21220 { 21221 name: "MOVBload", 21222 auxType: auxSymOff, 21223 argLen: 2, 21224 clobberFlags: true, 21225 faultOnNilArg0: true, 21226 symEffect: SymRead, 21227 asm: s390x.AMOVB, 21228 reg: regInfo{ 21229 inputs: []inputInfo{ 21230 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21231 }, 21232 outputs: []outputInfo{ 21233 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21234 }, 21235 }, 21236 }, 21237 { 21238 name: "MOVHZload", 21239 auxType: auxSymOff, 21240 argLen: 2, 21241 clobberFlags: true, 21242 faultOnNilArg0: true, 21243 symEffect: SymRead, 21244 asm: s390x.AMOVHZ, 21245 reg: regInfo{ 21246 inputs: []inputInfo{ 21247 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21248 }, 21249 outputs: []outputInfo{ 21250 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21251 }, 21252 }, 21253 }, 21254 { 21255 name: "MOVHload", 21256 auxType: auxSymOff, 21257 argLen: 2, 21258 clobberFlags: true, 21259 faultOnNilArg0: true, 21260 symEffect: SymRead, 21261 asm: s390x.AMOVH, 21262 reg: regInfo{ 21263 inputs: []inputInfo{ 21264 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21265 }, 21266 outputs: []outputInfo{ 21267 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21268 }, 21269 }, 21270 }, 21271 { 21272 name: "MOVWZload", 21273 auxType: auxSymOff, 21274 argLen: 2, 21275 clobberFlags: true, 21276 faultOnNilArg0: true, 21277 symEffect: SymRead, 21278 asm: s390x.AMOVWZ, 21279 reg: regInfo{ 21280 inputs: []inputInfo{ 21281 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21282 }, 21283 outputs: []outputInfo{ 21284 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21285 }, 21286 }, 21287 }, 21288 { 21289 name: "MOVWload", 21290 auxType: auxSymOff, 21291 argLen: 2, 21292 clobberFlags: true, 21293 faultOnNilArg0: true, 21294 symEffect: SymRead, 21295 asm: s390x.AMOVW, 21296 reg: regInfo{ 21297 inputs: []inputInfo{ 21298 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21299 }, 21300 outputs: []outputInfo{ 21301 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21302 }, 21303 }, 21304 }, 21305 { 21306 name: "MOVDload", 21307 auxType: auxSymOff, 21308 argLen: 2, 21309 clobberFlags: true, 21310 faultOnNilArg0: true, 21311 symEffect: SymRead, 21312 asm: s390x.AMOVD, 21313 reg: regInfo{ 21314 inputs: []inputInfo{ 21315 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21316 }, 21317 outputs: []outputInfo{ 21318 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21319 }, 21320 }, 21321 }, 21322 { 21323 name: "MOVWBR", 21324 argLen: 1, 21325 asm: s390x.AMOVWBR, 21326 reg: regInfo{ 21327 inputs: []inputInfo{ 21328 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21329 }, 21330 outputs: []outputInfo{ 21331 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21332 }, 21333 }, 21334 }, 21335 { 21336 name: "MOVDBR", 21337 argLen: 1, 21338 asm: s390x.AMOVDBR, 21339 reg: regInfo{ 21340 inputs: []inputInfo{ 21341 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21342 }, 21343 outputs: []outputInfo{ 21344 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21345 }, 21346 }, 21347 }, 21348 { 21349 name: "MOVHBRload", 21350 auxType: auxSymOff, 21351 argLen: 2, 21352 clobberFlags: true, 21353 faultOnNilArg0: true, 21354 symEffect: SymRead, 21355 asm: s390x.AMOVHBR, 21356 reg: regInfo{ 21357 inputs: []inputInfo{ 21358 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21359 }, 21360 outputs: []outputInfo{ 21361 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21362 }, 21363 }, 21364 }, 21365 { 21366 name: "MOVWBRload", 21367 auxType: auxSymOff, 21368 argLen: 2, 21369 clobberFlags: true, 21370 faultOnNilArg0: true, 21371 symEffect: SymRead, 21372 asm: s390x.AMOVWBR, 21373 reg: regInfo{ 21374 inputs: []inputInfo{ 21375 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21376 }, 21377 outputs: []outputInfo{ 21378 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21379 }, 21380 }, 21381 }, 21382 { 21383 name: "MOVDBRload", 21384 auxType: auxSymOff, 21385 argLen: 2, 21386 clobberFlags: true, 21387 faultOnNilArg0: true, 21388 symEffect: SymRead, 21389 asm: s390x.AMOVDBR, 21390 reg: regInfo{ 21391 inputs: []inputInfo{ 21392 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21393 }, 21394 outputs: []outputInfo{ 21395 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21396 }, 21397 }, 21398 }, 21399 { 21400 name: "MOVBstore", 21401 auxType: auxSymOff, 21402 argLen: 3, 21403 clobberFlags: true, 21404 faultOnNilArg0: true, 21405 symEffect: SymWrite, 21406 asm: s390x.AMOVB, 21407 reg: regInfo{ 21408 inputs: []inputInfo{ 21409 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21410 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21411 }, 21412 }, 21413 }, 21414 { 21415 name: "MOVHstore", 21416 auxType: auxSymOff, 21417 argLen: 3, 21418 clobberFlags: true, 21419 faultOnNilArg0: true, 21420 symEffect: SymWrite, 21421 asm: s390x.AMOVH, 21422 reg: regInfo{ 21423 inputs: []inputInfo{ 21424 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21425 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21426 }, 21427 }, 21428 }, 21429 { 21430 name: "MOVWstore", 21431 auxType: auxSymOff, 21432 argLen: 3, 21433 clobberFlags: true, 21434 faultOnNilArg0: true, 21435 symEffect: SymWrite, 21436 asm: s390x.AMOVW, 21437 reg: regInfo{ 21438 inputs: []inputInfo{ 21439 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21440 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21441 }, 21442 }, 21443 }, 21444 { 21445 name: "MOVDstore", 21446 auxType: auxSymOff, 21447 argLen: 3, 21448 clobberFlags: true, 21449 faultOnNilArg0: true, 21450 symEffect: SymWrite, 21451 asm: s390x.AMOVD, 21452 reg: regInfo{ 21453 inputs: []inputInfo{ 21454 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21455 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21456 }, 21457 }, 21458 }, 21459 { 21460 name: "MOVHBRstore", 21461 auxType: auxSymOff, 21462 argLen: 3, 21463 clobberFlags: true, 21464 faultOnNilArg0: true, 21465 symEffect: SymWrite, 21466 asm: s390x.AMOVHBR, 21467 reg: regInfo{ 21468 inputs: []inputInfo{ 21469 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21470 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21471 }, 21472 }, 21473 }, 21474 { 21475 name: "MOVWBRstore", 21476 auxType: auxSymOff, 21477 argLen: 3, 21478 clobberFlags: true, 21479 faultOnNilArg0: true, 21480 symEffect: SymWrite, 21481 asm: s390x.AMOVWBR, 21482 reg: regInfo{ 21483 inputs: []inputInfo{ 21484 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21485 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21486 }, 21487 }, 21488 }, 21489 { 21490 name: "MOVDBRstore", 21491 auxType: auxSymOff, 21492 argLen: 3, 21493 clobberFlags: true, 21494 faultOnNilArg0: true, 21495 symEffect: SymWrite, 21496 asm: s390x.AMOVDBR, 21497 reg: regInfo{ 21498 inputs: []inputInfo{ 21499 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21500 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21501 }, 21502 }, 21503 }, 21504 { 21505 name: "MVC", 21506 auxType: auxSymValAndOff, 21507 argLen: 3, 21508 clobberFlags: true, 21509 faultOnNilArg0: true, 21510 faultOnNilArg1: true, 21511 symEffect: SymNone, 21512 asm: s390x.AMVC, 21513 reg: regInfo{ 21514 inputs: []inputInfo{ 21515 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21516 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21517 }, 21518 }, 21519 }, 21520 { 21521 name: "MOVBZloadidx", 21522 auxType: auxSymOff, 21523 argLen: 3, 21524 commutative: true, 21525 clobberFlags: true, 21526 symEffect: SymRead, 21527 asm: s390x.AMOVBZ, 21528 reg: regInfo{ 21529 inputs: []inputInfo{ 21530 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21531 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21532 }, 21533 outputs: []outputInfo{ 21534 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21535 }, 21536 }, 21537 }, 21538 { 21539 name: "MOVBloadidx", 21540 auxType: auxSymOff, 21541 argLen: 3, 21542 commutative: true, 21543 clobberFlags: true, 21544 symEffect: SymRead, 21545 asm: s390x.AMOVB, 21546 reg: regInfo{ 21547 inputs: []inputInfo{ 21548 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21549 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21550 }, 21551 outputs: []outputInfo{ 21552 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21553 }, 21554 }, 21555 }, 21556 { 21557 name: "MOVHZloadidx", 21558 auxType: auxSymOff, 21559 argLen: 3, 21560 commutative: true, 21561 clobberFlags: true, 21562 symEffect: SymRead, 21563 asm: s390x.AMOVHZ, 21564 reg: regInfo{ 21565 inputs: []inputInfo{ 21566 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21567 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21568 }, 21569 outputs: []outputInfo{ 21570 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21571 }, 21572 }, 21573 }, 21574 { 21575 name: "MOVHloadidx", 21576 auxType: auxSymOff, 21577 argLen: 3, 21578 commutative: true, 21579 clobberFlags: true, 21580 symEffect: SymRead, 21581 asm: s390x.AMOVH, 21582 reg: regInfo{ 21583 inputs: []inputInfo{ 21584 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21585 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21586 }, 21587 outputs: []outputInfo{ 21588 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21589 }, 21590 }, 21591 }, 21592 { 21593 name: "MOVWZloadidx", 21594 auxType: auxSymOff, 21595 argLen: 3, 21596 commutative: true, 21597 clobberFlags: true, 21598 symEffect: SymRead, 21599 asm: s390x.AMOVWZ, 21600 reg: regInfo{ 21601 inputs: []inputInfo{ 21602 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21603 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21604 }, 21605 outputs: []outputInfo{ 21606 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21607 }, 21608 }, 21609 }, 21610 { 21611 name: "MOVWloadidx", 21612 auxType: auxSymOff, 21613 argLen: 3, 21614 commutative: true, 21615 clobberFlags: true, 21616 symEffect: SymRead, 21617 asm: s390x.AMOVW, 21618 reg: regInfo{ 21619 inputs: []inputInfo{ 21620 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21621 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21622 }, 21623 outputs: []outputInfo{ 21624 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21625 }, 21626 }, 21627 }, 21628 { 21629 name: "MOVDloadidx", 21630 auxType: auxSymOff, 21631 argLen: 3, 21632 commutative: true, 21633 clobberFlags: true, 21634 symEffect: SymRead, 21635 asm: s390x.AMOVD, 21636 reg: regInfo{ 21637 inputs: []inputInfo{ 21638 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21639 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21640 }, 21641 outputs: []outputInfo{ 21642 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21643 }, 21644 }, 21645 }, 21646 { 21647 name: "MOVHBRloadidx", 21648 auxType: auxSymOff, 21649 argLen: 3, 21650 commutative: true, 21651 clobberFlags: true, 21652 symEffect: SymRead, 21653 asm: s390x.AMOVHBR, 21654 reg: regInfo{ 21655 inputs: []inputInfo{ 21656 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21657 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21658 }, 21659 outputs: []outputInfo{ 21660 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21661 }, 21662 }, 21663 }, 21664 { 21665 name: "MOVWBRloadidx", 21666 auxType: auxSymOff, 21667 argLen: 3, 21668 commutative: true, 21669 clobberFlags: true, 21670 symEffect: SymRead, 21671 asm: s390x.AMOVWBR, 21672 reg: regInfo{ 21673 inputs: []inputInfo{ 21674 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21675 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21676 }, 21677 outputs: []outputInfo{ 21678 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21679 }, 21680 }, 21681 }, 21682 { 21683 name: "MOVDBRloadidx", 21684 auxType: auxSymOff, 21685 argLen: 3, 21686 commutative: true, 21687 clobberFlags: true, 21688 symEffect: SymRead, 21689 asm: s390x.AMOVDBR, 21690 reg: regInfo{ 21691 inputs: []inputInfo{ 21692 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21693 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21694 }, 21695 outputs: []outputInfo{ 21696 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21697 }, 21698 }, 21699 }, 21700 { 21701 name: "MOVBstoreidx", 21702 auxType: auxSymOff, 21703 argLen: 4, 21704 commutative: true, 21705 clobberFlags: true, 21706 symEffect: SymWrite, 21707 asm: s390x.AMOVB, 21708 reg: regInfo{ 21709 inputs: []inputInfo{ 21710 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21711 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21712 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21713 }, 21714 }, 21715 }, 21716 { 21717 name: "MOVHstoreidx", 21718 auxType: auxSymOff, 21719 argLen: 4, 21720 commutative: true, 21721 clobberFlags: true, 21722 symEffect: SymWrite, 21723 asm: s390x.AMOVH, 21724 reg: regInfo{ 21725 inputs: []inputInfo{ 21726 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21727 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21728 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21729 }, 21730 }, 21731 }, 21732 { 21733 name: "MOVWstoreidx", 21734 auxType: auxSymOff, 21735 argLen: 4, 21736 commutative: true, 21737 clobberFlags: true, 21738 symEffect: SymWrite, 21739 asm: s390x.AMOVW, 21740 reg: regInfo{ 21741 inputs: []inputInfo{ 21742 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21743 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21744 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21745 }, 21746 }, 21747 }, 21748 { 21749 name: "MOVDstoreidx", 21750 auxType: auxSymOff, 21751 argLen: 4, 21752 commutative: true, 21753 clobberFlags: true, 21754 symEffect: SymWrite, 21755 asm: s390x.AMOVD, 21756 reg: regInfo{ 21757 inputs: []inputInfo{ 21758 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21759 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21760 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21761 }, 21762 }, 21763 }, 21764 { 21765 name: "MOVHBRstoreidx", 21766 auxType: auxSymOff, 21767 argLen: 4, 21768 commutative: true, 21769 clobberFlags: true, 21770 symEffect: SymWrite, 21771 asm: s390x.AMOVHBR, 21772 reg: regInfo{ 21773 inputs: []inputInfo{ 21774 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21775 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21776 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21777 }, 21778 }, 21779 }, 21780 { 21781 name: "MOVWBRstoreidx", 21782 auxType: auxSymOff, 21783 argLen: 4, 21784 commutative: true, 21785 clobberFlags: true, 21786 symEffect: SymWrite, 21787 asm: s390x.AMOVWBR, 21788 reg: regInfo{ 21789 inputs: []inputInfo{ 21790 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21791 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21792 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21793 }, 21794 }, 21795 }, 21796 { 21797 name: "MOVDBRstoreidx", 21798 auxType: auxSymOff, 21799 argLen: 4, 21800 commutative: true, 21801 clobberFlags: true, 21802 symEffect: SymWrite, 21803 asm: s390x.AMOVDBR, 21804 reg: regInfo{ 21805 inputs: []inputInfo{ 21806 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21807 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21808 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21809 }, 21810 }, 21811 }, 21812 { 21813 name: "MOVBstoreconst", 21814 auxType: auxSymValAndOff, 21815 argLen: 2, 21816 faultOnNilArg0: true, 21817 symEffect: SymWrite, 21818 asm: s390x.AMOVB, 21819 reg: regInfo{ 21820 inputs: []inputInfo{ 21821 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21822 }, 21823 }, 21824 }, 21825 { 21826 name: "MOVHstoreconst", 21827 auxType: auxSymValAndOff, 21828 argLen: 2, 21829 faultOnNilArg0: true, 21830 symEffect: SymWrite, 21831 asm: s390x.AMOVH, 21832 reg: regInfo{ 21833 inputs: []inputInfo{ 21834 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21835 }, 21836 }, 21837 }, 21838 { 21839 name: "MOVWstoreconst", 21840 auxType: auxSymValAndOff, 21841 argLen: 2, 21842 faultOnNilArg0: true, 21843 symEffect: SymWrite, 21844 asm: s390x.AMOVW, 21845 reg: regInfo{ 21846 inputs: []inputInfo{ 21847 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21848 }, 21849 }, 21850 }, 21851 { 21852 name: "MOVDstoreconst", 21853 auxType: auxSymValAndOff, 21854 argLen: 2, 21855 faultOnNilArg0: true, 21856 symEffect: SymWrite, 21857 asm: s390x.AMOVD, 21858 reg: regInfo{ 21859 inputs: []inputInfo{ 21860 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 21861 }, 21862 }, 21863 }, 21864 { 21865 name: "CLEAR", 21866 auxType: auxSymValAndOff, 21867 argLen: 2, 21868 clobberFlags: true, 21869 faultOnNilArg0: true, 21870 symEffect: SymWrite, 21871 asm: s390x.ACLEAR, 21872 reg: regInfo{ 21873 inputs: []inputInfo{ 21874 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21875 }, 21876 }, 21877 }, 21878 { 21879 name: "CALLstatic", 21880 auxType: auxSymOff, 21881 argLen: 1, 21882 clobberFlags: true, 21883 call: true, 21884 symEffect: SymNone, 21885 reg: regInfo{ 21886 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21887 }, 21888 }, 21889 { 21890 name: "CALLclosure", 21891 auxType: auxInt64, 21892 argLen: 3, 21893 clobberFlags: true, 21894 call: true, 21895 reg: regInfo{ 21896 inputs: []inputInfo{ 21897 {1, 4096}, // R12 21898 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21899 }, 21900 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21901 }, 21902 }, 21903 { 21904 name: "CALLinter", 21905 auxType: auxInt64, 21906 argLen: 2, 21907 clobberFlags: true, 21908 call: true, 21909 reg: regInfo{ 21910 inputs: []inputInfo{ 21911 {0, 21502}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21912 }, 21913 clobbers: 4294923263, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21914 }, 21915 }, 21916 { 21917 name: "InvertFlags", 21918 argLen: 1, 21919 reg: regInfo{}, 21920 }, 21921 { 21922 name: "LoweredGetG", 21923 argLen: 1, 21924 reg: regInfo{ 21925 outputs: []outputInfo{ 21926 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21927 }, 21928 }, 21929 }, 21930 { 21931 name: "LoweredGetClosurePtr", 21932 argLen: 0, 21933 reg: regInfo{ 21934 outputs: []outputInfo{ 21935 {0, 4096}, // R12 21936 }, 21937 }, 21938 }, 21939 { 21940 name: "LoweredGetCallerSP", 21941 argLen: 0, 21942 rematerializeable: true, 21943 reg: regInfo{ 21944 outputs: []outputInfo{ 21945 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21946 }, 21947 }, 21948 }, 21949 { 21950 name: "LoweredNilCheck", 21951 argLen: 2, 21952 clobberFlags: true, 21953 nilCheck: true, 21954 faultOnNilArg0: true, 21955 reg: regInfo{ 21956 inputs: []inputInfo{ 21957 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21958 }, 21959 }, 21960 }, 21961 { 21962 name: "LoweredRound32F", 21963 argLen: 1, 21964 resultInArg0: true, 21965 reg: regInfo{ 21966 inputs: []inputInfo{ 21967 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21968 }, 21969 outputs: []outputInfo{ 21970 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21971 }, 21972 }, 21973 }, 21974 { 21975 name: "LoweredRound64F", 21976 argLen: 1, 21977 resultInArg0: true, 21978 reg: regInfo{ 21979 inputs: []inputInfo{ 21980 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21981 }, 21982 outputs: []outputInfo{ 21983 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 21984 }, 21985 }, 21986 }, 21987 { 21988 name: "MOVDconvert", 21989 argLen: 2, 21990 asm: s390x.AMOVD, 21991 reg: regInfo{ 21992 inputs: []inputInfo{ 21993 {0, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 21994 }, 21995 outputs: []outputInfo{ 21996 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 21997 }, 21998 }, 21999 }, 22000 { 22001 name: "FlagEQ", 22002 argLen: 0, 22003 reg: regInfo{}, 22004 }, 22005 { 22006 name: "FlagLT", 22007 argLen: 0, 22008 reg: regInfo{}, 22009 }, 22010 { 22011 name: "FlagGT", 22012 argLen: 0, 22013 reg: regInfo{}, 22014 }, 22015 { 22016 name: "MOVWZatomicload", 22017 auxType: auxSymOff, 22018 argLen: 2, 22019 faultOnNilArg0: true, 22020 symEffect: SymRead, 22021 asm: s390x.AMOVWZ, 22022 reg: regInfo{ 22023 inputs: []inputInfo{ 22024 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22025 }, 22026 outputs: []outputInfo{ 22027 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22028 }, 22029 }, 22030 }, 22031 { 22032 name: "MOVDatomicload", 22033 auxType: auxSymOff, 22034 argLen: 2, 22035 faultOnNilArg0: true, 22036 symEffect: SymRead, 22037 asm: s390x.AMOVD, 22038 reg: regInfo{ 22039 inputs: []inputInfo{ 22040 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22041 }, 22042 outputs: []outputInfo{ 22043 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22044 }, 22045 }, 22046 }, 22047 { 22048 name: "MOVWatomicstore", 22049 auxType: auxSymOff, 22050 argLen: 3, 22051 clobberFlags: true, 22052 faultOnNilArg0: true, 22053 hasSideEffects: true, 22054 symEffect: SymWrite, 22055 asm: s390x.AMOVW, 22056 reg: regInfo{ 22057 inputs: []inputInfo{ 22058 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22059 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22060 }, 22061 }, 22062 }, 22063 { 22064 name: "MOVDatomicstore", 22065 auxType: auxSymOff, 22066 argLen: 3, 22067 clobberFlags: true, 22068 faultOnNilArg0: true, 22069 hasSideEffects: true, 22070 symEffect: SymWrite, 22071 asm: s390x.AMOVD, 22072 reg: regInfo{ 22073 inputs: []inputInfo{ 22074 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22075 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22076 }, 22077 }, 22078 }, 22079 { 22080 name: "LAA", 22081 auxType: auxSymOff, 22082 argLen: 3, 22083 clobberFlags: true, 22084 faultOnNilArg0: true, 22085 hasSideEffects: true, 22086 symEffect: SymRdWr, 22087 asm: s390x.ALAA, 22088 reg: regInfo{ 22089 inputs: []inputInfo{ 22090 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22091 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22092 }, 22093 outputs: []outputInfo{ 22094 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22095 }, 22096 }, 22097 }, 22098 { 22099 name: "LAAG", 22100 auxType: auxSymOff, 22101 argLen: 3, 22102 clobberFlags: true, 22103 faultOnNilArg0: true, 22104 hasSideEffects: true, 22105 symEffect: SymRdWr, 22106 asm: s390x.ALAAG, 22107 reg: regInfo{ 22108 inputs: []inputInfo{ 22109 {0, 4295021566}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP SB 22110 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22111 }, 22112 outputs: []outputInfo{ 22113 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22114 }, 22115 }, 22116 }, 22117 { 22118 name: "AddTupleFirst32", 22119 argLen: 2, 22120 reg: regInfo{}, 22121 }, 22122 { 22123 name: "AddTupleFirst64", 22124 argLen: 2, 22125 reg: regInfo{}, 22126 }, 22127 { 22128 name: "LoweredAtomicCas32", 22129 auxType: auxSymOff, 22130 argLen: 4, 22131 clobberFlags: true, 22132 faultOnNilArg0: true, 22133 hasSideEffects: true, 22134 symEffect: SymRdWr, 22135 asm: s390x.ACS, 22136 reg: regInfo{ 22137 inputs: []inputInfo{ 22138 {1, 1}, // R0 22139 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22140 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22141 }, 22142 clobbers: 1, // R0 22143 outputs: []outputInfo{ 22144 {1, 0}, 22145 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22146 }, 22147 }, 22148 }, 22149 { 22150 name: "LoweredAtomicCas64", 22151 auxType: auxSymOff, 22152 argLen: 4, 22153 clobberFlags: true, 22154 faultOnNilArg0: true, 22155 hasSideEffects: true, 22156 symEffect: SymRdWr, 22157 asm: s390x.ACSG, 22158 reg: regInfo{ 22159 inputs: []inputInfo{ 22160 {1, 1}, // R0 22161 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22162 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22163 }, 22164 clobbers: 1, // R0 22165 outputs: []outputInfo{ 22166 {1, 0}, 22167 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22168 }, 22169 }, 22170 }, 22171 { 22172 name: "LoweredAtomicExchange32", 22173 auxType: auxSymOff, 22174 argLen: 3, 22175 clobberFlags: true, 22176 faultOnNilArg0: true, 22177 hasSideEffects: true, 22178 symEffect: SymRdWr, 22179 asm: s390x.ACS, 22180 reg: regInfo{ 22181 inputs: []inputInfo{ 22182 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22183 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22184 }, 22185 outputs: []outputInfo{ 22186 {1, 0}, 22187 {0, 1}, // R0 22188 }, 22189 }, 22190 }, 22191 { 22192 name: "LoweredAtomicExchange64", 22193 auxType: auxSymOff, 22194 argLen: 3, 22195 clobberFlags: true, 22196 faultOnNilArg0: true, 22197 hasSideEffects: true, 22198 symEffect: SymRdWr, 22199 asm: s390x.ACSG, 22200 reg: regInfo{ 22201 inputs: []inputInfo{ 22202 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22203 {1, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22204 }, 22205 outputs: []outputInfo{ 22206 {1, 0}, 22207 {0, 1}, // R0 22208 }, 22209 }, 22210 }, 22211 { 22212 name: "FLOGR", 22213 argLen: 1, 22214 clobberFlags: true, 22215 asm: s390x.AFLOGR, 22216 reg: regInfo{ 22217 inputs: []inputInfo{ 22218 {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 22219 }, 22220 clobbers: 2, // R1 22221 outputs: []outputInfo{ 22222 {0, 1}, // R0 22223 }, 22224 }, 22225 }, 22226 { 22227 name: "STMG2", 22228 auxType: auxSymOff, 22229 argLen: 4, 22230 faultOnNilArg0: true, 22231 symEffect: SymWrite, 22232 asm: s390x.ASTMG, 22233 reg: regInfo{ 22234 inputs: []inputInfo{ 22235 {1, 2}, // R1 22236 {2, 4}, // R2 22237 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22238 }, 22239 }, 22240 }, 22241 { 22242 name: "STMG3", 22243 auxType: auxSymOff, 22244 argLen: 5, 22245 faultOnNilArg0: true, 22246 symEffect: SymWrite, 22247 asm: s390x.ASTMG, 22248 reg: regInfo{ 22249 inputs: []inputInfo{ 22250 {1, 2}, // R1 22251 {2, 4}, // R2 22252 {3, 8}, // R3 22253 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22254 }, 22255 }, 22256 }, 22257 { 22258 name: "STMG4", 22259 auxType: auxSymOff, 22260 argLen: 6, 22261 faultOnNilArg0: true, 22262 symEffect: SymWrite, 22263 asm: s390x.ASTMG, 22264 reg: regInfo{ 22265 inputs: []inputInfo{ 22266 {1, 2}, // R1 22267 {2, 4}, // R2 22268 {3, 8}, // R3 22269 {4, 16}, // R4 22270 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22271 }, 22272 }, 22273 }, 22274 { 22275 name: "STM2", 22276 auxType: auxSymOff, 22277 argLen: 4, 22278 faultOnNilArg0: true, 22279 symEffect: SymWrite, 22280 asm: s390x.ASTMY, 22281 reg: regInfo{ 22282 inputs: []inputInfo{ 22283 {1, 2}, // R1 22284 {2, 4}, // R2 22285 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22286 }, 22287 }, 22288 }, 22289 { 22290 name: "STM3", 22291 auxType: auxSymOff, 22292 argLen: 5, 22293 faultOnNilArg0: true, 22294 symEffect: SymWrite, 22295 asm: s390x.ASTMY, 22296 reg: regInfo{ 22297 inputs: []inputInfo{ 22298 {1, 2}, // R1 22299 {2, 4}, // R2 22300 {3, 8}, // R3 22301 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22302 }, 22303 }, 22304 }, 22305 { 22306 name: "STM4", 22307 auxType: auxSymOff, 22308 argLen: 6, 22309 faultOnNilArg0: true, 22310 symEffect: SymWrite, 22311 asm: s390x.ASTMY, 22312 reg: regInfo{ 22313 inputs: []inputInfo{ 22314 {1, 2}, // R1 22315 {2, 4}, // R2 22316 {3, 8}, // R3 22317 {4, 16}, // R4 22318 {0, 54270}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22319 }, 22320 }, 22321 }, 22322 { 22323 name: "LoweredMove", 22324 auxType: auxInt64, 22325 argLen: 4, 22326 clobberFlags: true, 22327 faultOnNilArg0: true, 22328 faultOnNilArg1: true, 22329 reg: regInfo{ 22330 inputs: []inputInfo{ 22331 {0, 2}, // R1 22332 {1, 4}, // R2 22333 {2, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22334 }, 22335 clobbers: 6, // R1 R2 22336 }, 22337 }, 22338 { 22339 name: "LoweredZero", 22340 auxType: auxInt64, 22341 argLen: 3, 22342 clobberFlags: true, 22343 faultOnNilArg0: true, 22344 reg: regInfo{ 22345 inputs: []inputInfo{ 22346 {0, 2}, // R1 22347 {1, 54271}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 SP 22348 }, 22349 clobbers: 2, // R1 22350 }, 22351 }, 22352 22353 { 22354 name: "Add8", 22355 argLen: 2, 22356 commutative: true, 22357 generic: true, 22358 }, 22359 { 22360 name: "Add16", 22361 argLen: 2, 22362 commutative: true, 22363 generic: true, 22364 }, 22365 { 22366 name: "Add32", 22367 argLen: 2, 22368 commutative: true, 22369 generic: true, 22370 }, 22371 { 22372 name: "Add64", 22373 argLen: 2, 22374 commutative: true, 22375 generic: true, 22376 }, 22377 { 22378 name: "AddPtr", 22379 argLen: 2, 22380 generic: true, 22381 }, 22382 { 22383 name: "Add32F", 22384 argLen: 2, 22385 commutative: true, 22386 generic: true, 22387 }, 22388 { 22389 name: "Add64F", 22390 argLen: 2, 22391 commutative: true, 22392 generic: true, 22393 }, 22394 { 22395 name: "Sub8", 22396 argLen: 2, 22397 generic: true, 22398 }, 22399 { 22400 name: "Sub16", 22401 argLen: 2, 22402 generic: true, 22403 }, 22404 { 22405 name: "Sub32", 22406 argLen: 2, 22407 generic: true, 22408 }, 22409 { 22410 name: "Sub64", 22411 argLen: 2, 22412 generic: true, 22413 }, 22414 { 22415 name: "SubPtr", 22416 argLen: 2, 22417 generic: true, 22418 }, 22419 { 22420 name: "Sub32F", 22421 argLen: 2, 22422 generic: true, 22423 }, 22424 { 22425 name: "Sub64F", 22426 argLen: 2, 22427 generic: true, 22428 }, 22429 { 22430 name: "Mul8", 22431 argLen: 2, 22432 commutative: true, 22433 generic: true, 22434 }, 22435 { 22436 name: "Mul16", 22437 argLen: 2, 22438 commutative: true, 22439 generic: true, 22440 }, 22441 { 22442 name: "Mul32", 22443 argLen: 2, 22444 commutative: true, 22445 generic: true, 22446 }, 22447 { 22448 name: "Mul64", 22449 argLen: 2, 22450 commutative: true, 22451 generic: true, 22452 }, 22453 { 22454 name: "Mul32F", 22455 argLen: 2, 22456 commutative: true, 22457 generic: true, 22458 }, 22459 { 22460 name: "Mul64F", 22461 argLen: 2, 22462 commutative: true, 22463 generic: true, 22464 }, 22465 { 22466 name: "Div32F", 22467 argLen: 2, 22468 generic: true, 22469 }, 22470 { 22471 name: "Div64F", 22472 argLen: 2, 22473 generic: true, 22474 }, 22475 { 22476 name: "Hmul32", 22477 argLen: 2, 22478 commutative: true, 22479 generic: true, 22480 }, 22481 { 22482 name: "Hmul32u", 22483 argLen: 2, 22484 commutative: true, 22485 generic: true, 22486 }, 22487 { 22488 name: "Hmul64", 22489 argLen: 2, 22490 commutative: true, 22491 generic: true, 22492 }, 22493 { 22494 name: "Hmul64u", 22495 argLen: 2, 22496 commutative: true, 22497 generic: true, 22498 }, 22499 { 22500 name: "Mul32uhilo", 22501 argLen: 2, 22502 commutative: true, 22503 generic: true, 22504 }, 22505 { 22506 name: "Mul64uhilo", 22507 argLen: 2, 22508 commutative: true, 22509 generic: true, 22510 }, 22511 { 22512 name: "Avg32u", 22513 argLen: 2, 22514 generic: true, 22515 }, 22516 { 22517 name: "Avg64u", 22518 argLen: 2, 22519 generic: true, 22520 }, 22521 { 22522 name: "Div8", 22523 argLen: 2, 22524 generic: true, 22525 }, 22526 { 22527 name: "Div8u", 22528 argLen: 2, 22529 generic: true, 22530 }, 22531 { 22532 name: "Div16", 22533 argLen: 2, 22534 generic: true, 22535 }, 22536 { 22537 name: "Div16u", 22538 argLen: 2, 22539 generic: true, 22540 }, 22541 { 22542 name: "Div32", 22543 argLen: 2, 22544 generic: true, 22545 }, 22546 { 22547 name: "Div32u", 22548 argLen: 2, 22549 generic: true, 22550 }, 22551 { 22552 name: "Div64", 22553 argLen: 2, 22554 generic: true, 22555 }, 22556 { 22557 name: "Div64u", 22558 argLen: 2, 22559 generic: true, 22560 }, 22561 { 22562 name: "Div128u", 22563 argLen: 3, 22564 generic: true, 22565 }, 22566 { 22567 name: "Mod8", 22568 argLen: 2, 22569 generic: true, 22570 }, 22571 { 22572 name: "Mod8u", 22573 argLen: 2, 22574 generic: true, 22575 }, 22576 { 22577 name: "Mod16", 22578 argLen: 2, 22579 generic: true, 22580 }, 22581 { 22582 name: "Mod16u", 22583 argLen: 2, 22584 generic: true, 22585 }, 22586 { 22587 name: "Mod32", 22588 argLen: 2, 22589 generic: true, 22590 }, 22591 { 22592 name: "Mod32u", 22593 argLen: 2, 22594 generic: true, 22595 }, 22596 { 22597 name: "Mod64", 22598 argLen: 2, 22599 generic: true, 22600 }, 22601 { 22602 name: "Mod64u", 22603 argLen: 2, 22604 generic: true, 22605 }, 22606 { 22607 name: "And8", 22608 argLen: 2, 22609 commutative: true, 22610 generic: true, 22611 }, 22612 { 22613 name: "And16", 22614 argLen: 2, 22615 commutative: true, 22616 generic: true, 22617 }, 22618 { 22619 name: "And32", 22620 argLen: 2, 22621 commutative: true, 22622 generic: true, 22623 }, 22624 { 22625 name: "And64", 22626 argLen: 2, 22627 commutative: true, 22628 generic: true, 22629 }, 22630 { 22631 name: "Or8", 22632 argLen: 2, 22633 commutative: true, 22634 generic: true, 22635 }, 22636 { 22637 name: "Or16", 22638 argLen: 2, 22639 commutative: true, 22640 generic: true, 22641 }, 22642 { 22643 name: "Or32", 22644 argLen: 2, 22645 commutative: true, 22646 generic: true, 22647 }, 22648 { 22649 name: "Or64", 22650 argLen: 2, 22651 commutative: true, 22652 generic: true, 22653 }, 22654 { 22655 name: "Xor8", 22656 argLen: 2, 22657 commutative: true, 22658 generic: true, 22659 }, 22660 { 22661 name: "Xor16", 22662 argLen: 2, 22663 commutative: true, 22664 generic: true, 22665 }, 22666 { 22667 name: "Xor32", 22668 argLen: 2, 22669 commutative: true, 22670 generic: true, 22671 }, 22672 { 22673 name: "Xor64", 22674 argLen: 2, 22675 commutative: true, 22676 generic: true, 22677 }, 22678 { 22679 name: "Lsh8x8", 22680 argLen: 2, 22681 generic: true, 22682 }, 22683 { 22684 name: "Lsh8x16", 22685 argLen: 2, 22686 generic: true, 22687 }, 22688 { 22689 name: "Lsh8x32", 22690 argLen: 2, 22691 generic: true, 22692 }, 22693 { 22694 name: "Lsh8x64", 22695 argLen: 2, 22696 generic: true, 22697 }, 22698 { 22699 name: "Lsh16x8", 22700 argLen: 2, 22701 generic: true, 22702 }, 22703 { 22704 name: "Lsh16x16", 22705 argLen: 2, 22706 generic: true, 22707 }, 22708 { 22709 name: "Lsh16x32", 22710 argLen: 2, 22711 generic: true, 22712 }, 22713 { 22714 name: "Lsh16x64", 22715 argLen: 2, 22716 generic: true, 22717 }, 22718 { 22719 name: "Lsh32x8", 22720 argLen: 2, 22721 generic: true, 22722 }, 22723 { 22724 name: "Lsh32x16", 22725 argLen: 2, 22726 generic: true, 22727 }, 22728 { 22729 name: "Lsh32x32", 22730 argLen: 2, 22731 generic: true, 22732 }, 22733 { 22734 name: "Lsh32x64", 22735 argLen: 2, 22736 generic: true, 22737 }, 22738 { 22739 name: "Lsh64x8", 22740 argLen: 2, 22741 generic: true, 22742 }, 22743 { 22744 name: "Lsh64x16", 22745 argLen: 2, 22746 generic: true, 22747 }, 22748 { 22749 name: "Lsh64x32", 22750 argLen: 2, 22751 generic: true, 22752 }, 22753 { 22754 name: "Lsh64x64", 22755 argLen: 2, 22756 generic: true, 22757 }, 22758 { 22759 name: "Rsh8x8", 22760 argLen: 2, 22761 generic: true, 22762 }, 22763 { 22764 name: "Rsh8x16", 22765 argLen: 2, 22766 generic: true, 22767 }, 22768 { 22769 name: "Rsh8x32", 22770 argLen: 2, 22771 generic: true, 22772 }, 22773 { 22774 name: "Rsh8x64", 22775 argLen: 2, 22776 generic: true, 22777 }, 22778 { 22779 name: "Rsh16x8", 22780 argLen: 2, 22781 generic: true, 22782 }, 22783 { 22784 name: "Rsh16x16", 22785 argLen: 2, 22786 generic: true, 22787 }, 22788 { 22789 name: "Rsh16x32", 22790 argLen: 2, 22791 generic: true, 22792 }, 22793 { 22794 name: "Rsh16x64", 22795 argLen: 2, 22796 generic: true, 22797 }, 22798 { 22799 name: "Rsh32x8", 22800 argLen: 2, 22801 generic: true, 22802 }, 22803 { 22804 name: "Rsh32x16", 22805 argLen: 2, 22806 generic: true, 22807 }, 22808 { 22809 name: "Rsh32x32", 22810 argLen: 2, 22811 generic: true, 22812 }, 22813 { 22814 name: "Rsh32x64", 22815 argLen: 2, 22816 generic: true, 22817 }, 22818 { 22819 name: "Rsh64x8", 22820 argLen: 2, 22821 generic: true, 22822 }, 22823 { 22824 name: "Rsh64x16", 22825 argLen: 2, 22826 generic: true, 22827 }, 22828 { 22829 name: "Rsh64x32", 22830 argLen: 2, 22831 generic: true, 22832 }, 22833 { 22834 name: "Rsh64x64", 22835 argLen: 2, 22836 generic: true, 22837 }, 22838 { 22839 name: "Rsh8Ux8", 22840 argLen: 2, 22841 generic: true, 22842 }, 22843 { 22844 name: "Rsh8Ux16", 22845 argLen: 2, 22846 generic: true, 22847 }, 22848 { 22849 name: "Rsh8Ux32", 22850 argLen: 2, 22851 generic: true, 22852 }, 22853 { 22854 name: "Rsh8Ux64", 22855 argLen: 2, 22856 generic: true, 22857 }, 22858 { 22859 name: "Rsh16Ux8", 22860 argLen: 2, 22861 generic: true, 22862 }, 22863 { 22864 name: "Rsh16Ux16", 22865 argLen: 2, 22866 generic: true, 22867 }, 22868 { 22869 name: "Rsh16Ux32", 22870 argLen: 2, 22871 generic: true, 22872 }, 22873 { 22874 name: "Rsh16Ux64", 22875 argLen: 2, 22876 generic: true, 22877 }, 22878 { 22879 name: "Rsh32Ux8", 22880 argLen: 2, 22881 generic: true, 22882 }, 22883 { 22884 name: "Rsh32Ux16", 22885 argLen: 2, 22886 generic: true, 22887 }, 22888 { 22889 name: "Rsh32Ux32", 22890 argLen: 2, 22891 generic: true, 22892 }, 22893 { 22894 name: "Rsh32Ux64", 22895 argLen: 2, 22896 generic: true, 22897 }, 22898 { 22899 name: "Rsh64Ux8", 22900 argLen: 2, 22901 generic: true, 22902 }, 22903 { 22904 name: "Rsh64Ux16", 22905 argLen: 2, 22906 generic: true, 22907 }, 22908 { 22909 name: "Rsh64Ux32", 22910 argLen: 2, 22911 generic: true, 22912 }, 22913 { 22914 name: "Rsh64Ux64", 22915 argLen: 2, 22916 generic: true, 22917 }, 22918 { 22919 name: "Eq8", 22920 argLen: 2, 22921 commutative: true, 22922 generic: true, 22923 }, 22924 { 22925 name: "Eq16", 22926 argLen: 2, 22927 commutative: true, 22928 generic: true, 22929 }, 22930 { 22931 name: "Eq32", 22932 argLen: 2, 22933 commutative: true, 22934 generic: true, 22935 }, 22936 { 22937 name: "Eq64", 22938 argLen: 2, 22939 commutative: true, 22940 generic: true, 22941 }, 22942 { 22943 name: "EqPtr", 22944 argLen: 2, 22945 commutative: true, 22946 generic: true, 22947 }, 22948 { 22949 name: "EqInter", 22950 argLen: 2, 22951 generic: true, 22952 }, 22953 { 22954 name: "EqSlice", 22955 argLen: 2, 22956 generic: true, 22957 }, 22958 { 22959 name: "Eq32F", 22960 argLen: 2, 22961 commutative: true, 22962 generic: true, 22963 }, 22964 { 22965 name: "Eq64F", 22966 argLen: 2, 22967 commutative: true, 22968 generic: true, 22969 }, 22970 { 22971 name: "Neq8", 22972 argLen: 2, 22973 commutative: true, 22974 generic: true, 22975 }, 22976 { 22977 name: "Neq16", 22978 argLen: 2, 22979 commutative: true, 22980 generic: true, 22981 }, 22982 { 22983 name: "Neq32", 22984 argLen: 2, 22985 commutative: true, 22986 generic: true, 22987 }, 22988 { 22989 name: "Neq64", 22990 argLen: 2, 22991 commutative: true, 22992 generic: true, 22993 }, 22994 { 22995 name: "NeqPtr", 22996 argLen: 2, 22997 commutative: true, 22998 generic: true, 22999 }, 23000 { 23001 name: "NeqInter", 23002 argLen: 2, 23003 generic: true, 23004 }, 23005 { 23006 name: "NeqSlice", 23007 argLen: 2, 23008 generic: true, 23009 }, 23010 { 23011 name: "Neq32F", 23012 argLen: 2, 23013 commutative: true, 23014 generic: true, 23015 }, 23016 { 23017 name: "Neq64F", 23018 argLen: 2, 23019 commutative: true, 23020 generic: true, 23021 }, 23022 { 23023 name: "Less8", 23024 argLen: 2, 23025 generic: true, 23026 }, 23027 { 23028 name: "Less8U", 23029 argLen: 2, 23030 generic: true, 23031 }, 23032 { 23033 name: "Less16", 23034 argLen: 2, 23035 generic: true, 23036 }, 23037 { 23038 name: "Less16U", 23039 argLen: 2, 23040 generic: true, 23041 }, 23042 { 23043 name: "Less32", 23044 argLen: 2, 23045 generic: true, 23046 }, 23047 { 23048 name: "Less32U", 23049 argLen: 2, 23050 generic: true, 23051 }, 23052 { 23053 name: "Less64", 23054 argLen: 2, 23055 generic: true, 23056 }, 23057 { 23058 name: "Less64U", 23059 argLen: 2, 23060 generic: true, 23061 }, 23062 { 23063 name: "Less32F", 23064 argLen: 2, 23065 generic: true, 23066 }, 23067 { 23068 name: "Less64F", 23069 argLen: 2, 23070 generic: true, 23071 }, 23072 { 23073 name: "Leq8", 23074 argLen: 2, 23075 generic: true, 23076 }, 23077 { 23078 name: "Leq8U", 23079 argLen: 2, 23080 generic: true, 23081 }, 23082 { 23083 name: "Leq16", 23084 argLen: 2, 23085 generic: true, 23086 }, 23087 { 23088 name: "Leq16U", 23089 argLen: 2, 23090 generic: true, 23091 }, 23092 { 23093 name: "Leq32", 23094 argLen: 2, 23095 generic: true, 23096 }, 23097 { 23098 name: "Leq32U", 23099 argLen: 2, 23100 generic: true, 23101 }, 23102 { 23103 name: "Leq64", 23104 argLen: 2, 23105 generic: true, 23106 }, 23107 { 23108 name: "Leq64U", 23109 argLen: 2, 23110 generic: true, 23111 }, 23112 { 23113 name: "Leq32F", 23114 argLen: 2, 23115 generic: true, 23116 }, 23117 { 23118 name: "Leq64F", 23119 argLen: 2, 23120 generic: true, 23121 }, 23122 { 23123 name: "Greater8", 23124 argLen: 2, 23125 generic: true, 23126 }, 23127 { 23128 name: "Greater8U", 23129 argLen: 2, 23130 generic: true, 23131 }, 23132 { 23133 name: "Greater16", 23134 argLen: 2, 23135 generic: true, 23136 }, 23137 { 23138 name: "Greater16U", 23139 argLen: 2, 23140 generic: true, 23141 }, 23142 { 23143 name: "Greater32", 23144 argLen: 2, 23145 generic: true, 23146 }, 23147 { 23148 name: "Greater32U", 23149 argLen: 2, 23150 generic: true, 23151 }, 23152 { 23153 name: "Greater64", 23154 argLen: 2, 23155 generic: true, 23156 }, 23157 { 23158 name: "Greater64U", 23159 argLen: 2, 23160 generic: true, 23161 }, 23162 { 23163 name: "Greater32F", 23164 argLen: 2, 23165 generic: true, 23166 }, 23167 { 23168 name: "Greater64F", 23169 argLen: 2, 23170 generic: true, 23171 }, 23172 { 23173 name: "Geq8", 23174 argLen: 2, 23175 generic: true, 23176 }, 23177 { 23178 name: "Geq8U", 23179 argLen: 2, 23180 generic: true, 23181 }, 23182 { 23183 name: "Geq16", 23184 argLen: 2, 23185 generic: true, 23186 }, 23187 { 23188 name: "Geq16U", 23189 argLen: 2, 23190 generic: true, 23191 }, 23192 { 23193 name: "Geq32", 23194 argLen: 2, 23195 generic: true, 23196 }, 23197 { 23198 name: "Geq32U", 23199 argLen: 2, 23200 generic: true, 23201 }, 23202 { 23203 name: "Geq64", 23204 argLen: 2, 23205 generic: true, 23206 }, 23207 { 23208 name: "Geq64U", 23209 argLen: 2, 23210 generic: true, 23211 }, 23212 { 23213 name: "Geq32F", 23214 argLen: 2, 23215 generic: true, 23216 }, 23217 { 23218 name: "Geq64F", 23219 argLen: 2, 23220 generic: true, 23221 }, 23222 { 23223 name: "AndB", 23224 argLen: 2, 23225 commutative: true, 23226 generic: true, 23227 }, 23228 { 23229 name: "OrB", 23230 argLen: 2, 23231 commutative: true, 23232 generic: true, 23233 }, 23234 { 23235 name: "EqB", 23236 argLen: 2, 23237 commutative: true, 23238 generic: true, 23239 }, 23240 { 23241 name: "NeqB", 23242 argLen: 2, 23243 commutative: true, 23244 generic: true, 23245 }, 23246 { 23247 name: "Not", 23248 argLen: 1, 23249 generic: true, 23250 }, 23251 { 23252 name: "Neg8", 23253 argLen: 1, 23254 generic: true, 23255 }, 23256 { 23257 name: "Neg16", 23258 argLen: 1, 23259 generic: true, 23260 }, 23261 { 23262 name: "Neg32", 23263 argLen: 1, 23264 generic: true, 23265 }, 23266 { 23267 name: "Neg64", 23268 argLen: 1, 23269 generic: true, 23270 }, 23271 { 23272 name: "Neg32F", 23273 argLen: 1, 23274 generic: true, 23275 }, 23276 { 23277 name: "Neg64F", 23278 argLen: 1, 23279 generic: true, 23280 }, 23281 { 23282 name: "Com8", 23283 argLen: 1, 23284 generic: true, 23285 }, 23286 { 23287 name: "Com16", 23288 argLen: 1, 23289 generic: true, 23290 }, 23291 { 23292 name: "Com32", 23293 argLen: 1, 23294 generic: true, 23295 }, 23296 { 23297 name: "Com64", 23298 argLen: 1, 23299 generic: true, 23300 }, 23301 { 23302 name: "Ctz32", 23303 argLen: 1, 23304 generic: true, 23305 }, 23306 { 23307 name: "Ctz64", 23308 argLen: 1, 23309 generic: true, 23310 }, 23311 { 23312 name: "BitLen32", 23313 argLen: 1, 23314 generic: true, 23315 }, 23316 { 23317 name: "BitLen64", 23318 argLen: 1, 23319 generic: true, 23320 }, 23321 { 23322 name: "Bswap32", 23323 argLen: 1, 23324 generic: true, 23325 }, 23326 { 23327 name: "Bswap64", 23328 argLen: 1, 23329 generic: true, 23330 }, 23331 { 23332 name: "BitRev8", 23333 argLen: 1, 23334 generic: true, 23335 }, 23336 { 23337 name: "BitRev16", 23338 argLen: 1, 23339 generic: true, 23340 }, 23341 { 23342 name: "BitRev32", 23343 argLen: 1, 23344 generic: true, 23345 }, 23346 { 23347 name: "BitRev64", 23348 argLen: 1, 23349 generic: true, 23350 }, 23351 { 23352 name: "PopCount8", 23353 argLen: 1, 23354 generic: true, 23355 }, 23356 { 23357 name: "PopCount16", 23358 argLen: 1, 23359 generic: true, 23360 }, 23361 { 23362 name: "PopCount32", 23363 argLen: 1, 23364 generic: true, 23365 }, 23366 { 23367 name: "PopCount64", 23368 argLen: 1, 23369 generic: true, 23370 }, 23371 { 23372 name: "Sqrt", 23373 argLen: 1, 23374 generic: true, 23375 }, 23376 { 23377 name: "Floor", 23378 argLen: 1, 23379 generic: true, 23380 }, 23381 { 23382 name: "Ceil", 23383 argLen: 1, 23384 generic: true, 23385 }, 23386 { 23387 name: "Trunc", 23388 argLen: 1, 23389 generic: true, 23390 }, 23391 { 23392 name: "Round", 23393 argLen: 1, 23394 generic: true, 23395 }, 23396 { 23397 name: "RoundToEven", 23398 argLen: 1, 23399 generic: true, 23400 }, 23401 { 23402 name: "Abs", 23403 argLen: 1, 23404 generic: true, 23405 }, 23406 { 23407 name: "Copysign", 23408 argLen: 2, 23409 generic: true, 23410 }, 23411 { 23412 name: "Phi", 23413 argLen: -1, 23414 generic: true, 23415 }, 23416 { 23417 name: "Copy", 23418 argLen: 1, 23419 generic: true, 23420 }, 23421 { 23422 name: "Convert", 23423 argLen: 2, 23424 generic: true, 23425 }, 23426 { 23427 name: "ConstBool", 23428 auxType: auxBool, 23429 argLen: 0, 23430 generic: true, 23431 }, 23432 { 23433 name: "ConstString", 23434 auxType: auxString, 23435 argLen: 0, 23436 generic: true, 23437 }, 23438 { 23439 name: "ConstNil", 23440 argLen: 0, 23441 generic: true, 23442 }, 23443 { 23444 name: "Const8", 23445 auxType: auxInt8, 23446 argLen: 0, 23447 generic: true, 23448 }, 23449 { 23450 name: "Const16", 23451 auxType: auxInt16, 23452 argLen: 0, 23453 generic: true, 23454 }, 23455 { 23456 name: "Const32", 23457 auxType: auxInt32, 23458 argLen: 0, 23459 generic: true, 23460 }, 23461 { 23462 name: "Const64", 23463 auxType: auxInt64, 23464 argLen: 0, 23465 generic: true, 23466 }, 23467 { 23468 name: "Const32F", 23469 auxType: auxFloat32, 23470 argLen: 0, 23471 generic: true, 23472 }, 23473 { 23474 name: "Const64F", 23475 auxType: auxFloat64, 23476 argLen: 0, 23477 generic: true, 23478 }, 23479 { 23480 name: "ConstInterface", 23481 argLen: 0, 23482 generic: true, 23483 }, 23484 { 23485 name: "ConstSlice", 23486 argLen: 0, 23487 generic: true, 23488 }, 23489 { 23490 name: "InitMem", 23491 argLen: 0, 23492 generic: true, 23493 }, 23494 { 23495 name: "Arg", 23496 auxType: auxSymOff, 23497 argLen: 0, 23498 symEffect: SymRead, 23499 generic: true, 23500 }, 23501 { 23502 name: "Addr", 23503 auxType: auxSym, 23504 argLen: 1, 23505 symEffect: SymAddr, 23506 generic: true, 23507 }, 23508 { 23509 name: "SP", 23510 argLen: 0, 23511 generic: true, 23512 }, 23513 { 23514 name: "SB", 23515 argLen: 0, 23516 generic: true, 23517 }, 23518 { 23519 name: "Load", 23520 argLen: 2, 23521 generic: true, 23522 }, 23523 { 23524 name: "Store", 23525 auxType: auxTyp, 23526 argLen: 3, 23527 generic: true, 23528 }, 23529 { 23530 name: "Move", 23531 auxType: auxTypSize, 23532 argLen: 3, 23533 generic: true, 23534 }, 23535 { 23536 name: "Zero", 23537 auxType: auxTypSize, 23538 argLen: 2, 23539 generic: true, 23540 }, 23541 { 23542 name: "StoreWB", 23543 auxType: auxTyp, 23544 argLen: 3, 23545 generic: true, 23546 }, 23547 { 23548 name: "MoveWB", 23549 auxType: auxTypSize, 23550 argLen: 3, 23551 generic: true, 23552 }, 23553 { 23554 name: "ZeroWB", 23555 auxType: auxTypSize, 23556 argLen: 2, 23557 generic: true, 23558 }, 23559 { 23560 name: "WB", 23561 auxType: auxSym, 23562 argLen: 3, 23563 symEffect: SymNone, 23564 generic: true, 23565 }, 23566 { 23567 name: "ClosureCall", 23568 auxType: auxInt64, 23569 argLen: 3, 23570 call: true, 23571 generic: true, 23572 }, 23573 { 23574 name: "StaticCall", 23575 auxType: auxSymOff, 23576 argLen: 1, 23577 call: true, 23578 symEffect: SymNone, 23579 generic: true, 23580 }, 23581 { 23582 name: "InterCall", 23583 auxType: auxInt64, 23584 argLen: 2, 23585 call: true, 23586 generic: true, 23587 }, 23588 { 23589 name: "SignExt8to16", 23590 argLen: 1, 23591 generic: true, 23592 }, 23593 { 23594 name: "SignExt8to32", 23595 argLen: 1, 23596 generic: true, 23597 }, 23598 { 23599 name: "SignExt8to64", 23600 argLen: 1, 23601 generic: true, 23602 }, 23603 { 23604 name: "SignExt16to32", 23605 argLen: 1, 23606 generic: true, 23607 }, 23608 { 23609 name: "SignExt16to64", 23610 argLen: 1, 23611 generic: true, 23612 }, 23613 { 23614 name: "SignExt32to64", 23615 argLen: 1, 23616 generic: true, 23617 }, 23618 { 23619 name: "ZeroExt8to16", 23620 argLen: 1, 23621 generic: true, 23622 }, 23623 { 23624 name: "ZeroExt8to32", 23625 argLen: 1, 23626 generic: true, 23627 }, 23628 { 23629 name: "ZeroExt8to64", 23630 argLen: 1, 23631 generic: true, 23632 }, 23633 { 23634 name: "ZeroExt16to32", 23635 argLen: 1, 23636 generic: true, 23637 }, 23638 { 23639 name: "ZeroExt16to64", 23640 argLen: 1, 23641 generic: true, 23642 }, 23643 { 23644 name: "ZeroExt32to64", 23645 argLen: 1, 23646 generic: true, 23647 }, 23648 { 23649 name: "Trunc16to8", 23650 argLen: 1, 23651 generic: true, 23652 }, 23653 { 23654 name: "Trunc32to8", 23655 argLen: 1, 23656 generic: true, 23657 }, 23658 { 23659 name: "Trunc32to16", 23660 argLen: 1, 23661 generic: true, 23662 }, 23663 { 23664 name: "Trunc64to8", 23665 argLen: 1, 23666 generic: true, 23667 }, 23668 { 23669 name: "Trunc64to16", 23670 argLen: 1, 23671 generic: true, 23672 }, 23673 { 23674 name: "Trunc64to32", 23675 argLen: 1, 23676 generic: true, 23677 }, 23678 { 23679 name: "Cvt32to32F", 23680 argLen: 1, 23681 generic: true, 23682 }, 23683 { 23684 name: "Cvt32to64F", 23685 argLen: 1, 23686 generic: true, 23687 }, 23688 { 23689 name: "Cvt64to32F", 23690 argLen: 1, 23691 generic: true, 23692 }, 23693 { 23694 name: "Cvt64to64F", 23695 argLen: 1, 23696 generic: true, 23697 }, 23698 { 23699 name: "Cvt32Fto32", 23700 argLen: 1, 23701 generic: true, 23702 }, 23703 { 23704 name: "Cvt32Fto64", 23705 argLen: 1, 23706 generic: true, 23707 }, 23708 { 23709 name: "Cvt64Fto32", 23710 argLen: 1, 23711 generic: true, 23712 }, 23713 { 23714 name: "Cvt64Fto64", 23715 argLen: 1, 23716 generic: true, 23717 }, 23718 { 23719 name: "Cvt32Fto64F", 23720 argLen: 1, 23721 generic: true, 23722 }, 23723 { 23724 name: "Cvt64Fto32F", 23725 argLen: 1, 23726 generic: true, 23727 }, 23728 { 23729 name: "Round32F", 23730 argLen: 1, 23731 generic: true, 23732 }, 23733 { 23734 name: "Round64F", 23735 argLen: 1, 23736 generic: true, 23737 }, 23738 { 23739 name: "IsNonNil", 23740 argLen: 1, 23741 generic: true, 23742 }, 23743 { 23744 name: "IsInBounds", 23745 argLen: 2, 23746 generic: true, 23747 }, 23748 { 23749 name: "IsSliceInBounds", 23750 argLen: 2, 23751 generic: true, 23752 }, 23753 { 23754 name: "NilCheck", 23755 argLen: 2, 23756 generic: true, 23757 }, 23758 { 23759 name: "GetG", 23760 argLen: 1, 23761 generic: true, 23762 }, 23763 { 23764 name: "GetClosurePtr", 23765 argLen: 0, 23766 generic: true, 23767 }, 23768 { 23769 name: "GetCallerPC", 23770 argLen: 0, 23771 generic: true, 23772 }, 23773 { 23774 name: "GetCallerSP", 23775 argLen: 0, 23776 generic: true, 23777 }, 23778 { 23779 name: "PtrIndex", 23780 argLen: 2, 23781 generic: true, 23782 }, 23783 { 23784 name: "OffPtr", 23785 auxType: auxInt64, 23786 argLen: 1, 23787 generic: true, 23788 }, 23789 { 23790 name: "SliceMake", 23791 argLen: 3, 23792 generic: true, 23793 }, 23794 { 23795 name: "SlicePtr", 23796 argLen: 1, 23797 generic: true, 23798 }, 23799 { 23800 name: "SliceLen", 23801 argLen: 1, 23802 generic: true, 23803 }, 23804 { 23805 name: "SliceCap", 23806 argLen: 1, 23807 generic: true, 23808 }, 23809 { 23810 name: "ComplexMake", 23811 argLen: 2, 23812 generic: true, 23813 }, 23814 { 23815 name: "ComplexReal", 23816 argLen: 1, 23817 generic: true, 23818 }, 23819 { 23820 name: "ComplexImag", 23821 argLen: 1, 23822 generic: true, 23823 }, 23824 { 23825 name: "StringMake", 23826 argLen: 2, 23827 generic: true, 23828 }, 23829 { 23830 name: "StringPtr", 23831 argLen: 1, 23832 generic: true, 23833 }, 23834 { 23835 name: "StringLen", 23836 argLen: 1, 23837 generic: true, 23838 }, 23839 { 23840 name: "IMake", 23841 argLen: 2, 23842 generic: true, 23843 }, 23844 { 23845 name: "ITab", 23846 argLen: 1, 23847 generic: true, 23848 }, 23849 { 23850 name: "IData", 23851 argLen: 1, 23852 generic: true, 23853 }, 23854 { 23855 name: "StructMake0", 23856 argLen: 0, 23857 generic: true, 23858 }, 23859 { 23860 name: "StructMake1", 23861 argLen: 1, 23862 generic: true, 23863 }, 23864 { 23865 name: "StructMake2", 23866 argLen: 2, 23867 generic: true, 23868 }, 23869 { 23870 name: "StructMake3", 23871 argLen: 3, 23872 generic: true, 23873 }, 23874 { 23875 name: "StructMake4", 23876 argLen: 4, 23877 generic: true, 23878 }, 23879 { 23880 name: "StructSelect", 23881 auxType: auxInt64, 23882 argLen: 1, 23883 generic: true, 23884 }, 23885 { 23886 name: "ArrayMake0", 23887 argLen: 0, 23888 generic: true, 23889 }, 23890 { 23891 name: "ArrayMake1", 23892 argLen: 1, 23893 generic: true, 23894 }, 23895 { 23896 name: "ArraySelect", 23897 auxType: auxInt64, 23898 argLen: 1, 23899 generic: true, 23900 }, 23901 { 23902 name: "StoreReg", 23903 argLen: 1, 23904 generic: true, 23905 }, 23906 { 23907 name: "LoadReg", 23908 argLen: 1, 23909 generic: true, 23910 }, 23911 { 23912 name: "FwdRef", 23913 auxType: auxSym, 23914 argLen: 0, 23915 symEffect: SymNone, 23916 generic: true, 23917 }, 23918 { 23919 name: "Unknown", 23920 argLen: 0, 23921 generic: true, 23922 }, 23923 { 23924 name: "VarDef", 23925 auxType: auxSym, 23926 argLen: 1, 23927 symEffect: SymNone, 23928 generic: true, 23929 }, 23930 { 23931 name: "VarKill", 23932 auxType: auxSym, 23933 argLen: 1, 23934 symEffect: SymNone, 23935 generic: true, 23936 }, 23937 { 23938 name: "VarLive", 23939 auxType: auxSym, 23940 argLen: 1, 23941 symEffect: SymRead, 23942 generic: true, 23943 }, 23944 { 23945 name: "KeepAlive", 23946 argLen: 2, 23947 generic: true, 23948 }, 23949 { 23950 name: "RegKill", 23951 argLen: 0, 23952 generic: true, 23953 }, 23954 { 23955 name: "Int64Make", 23956 argLen: 2, 23957 generic: true, 23958 }, 23959 { 23960 name: "Int64Hi", 23961 argLen: 1, 23962 generic: true, 23963 }, 23964 { 23965 name: "Int64Lo", 23966 argLen: 1, 23967 generic: true, 23968 }, 23969 { 23970 name: "Add32carry", 23971 argLen: 2, 23972 commutative: true, 23973 generic: true, 23974 }, 23975 { 23976 name: "Add32withcarry", 23977 argLen: 3, 23978 commutative: true, 23979 generic: true, 23980 }, 23981 { 23982 name: "Sub32carry", 23983 argLen: 2, 23984 generic: true, 23985 }, 23986 { 23987 name: "Sub32withcarry", 23988 argLen: 3, 23989 generic: true, 23990 }, 23991 { 23992 name: "Signmask", 23993 argLen: 1, 23994 generic: true, 23995 }, 23996 { 23997 name: "Zeromask", 23998 argLen: 1, 23999 generic: true, 24000 }, 24001 { 24002 name: "Slicemask", 24003 argLen: 1, 24004 generic: true, 24005 }, 24006 { 24007 name: "Cvt32Uto32F", 24008 argLen: 1, 24009 generic: true, 24010 }, 24011 { 24012 name: "Cvt32Uto64F", 24013 argLen: 1, 24014 generic: true, 24015 }, 24016 { 24017 name: "Cvt32Fto32U", 24018 argLen: 1, 24019 generic: true, 24020 }, 24021 { 24022 name: "Cvt64Fto32U", 24023 argLen: 1, 24024 generic: true, 24025 }, 24026 { 24027 name: "Cvt64Uto32F", 24028 argLen: 1, 24029 generic: true, 24030 }, 24031 { 24032 name: "Cvt64Uto64F", 24033 argLen: 1, 24034 generic: true, 24035 }, 24036 { 24037 name: "Cvt32Fto64U", 24038 argLen: 1, 24039 generic: true, 24040 }, 24041 { 24042 name: "Cvt64Fto64U", 24043 argLen: 1, 24044 generic: true, 24045 }, 24046 { 24047 name: "Select0", 24048 argLen: 1, 24049 generic: true, 24050 }, 24051 { 24052 name: "Select1", 24053 argLen: 1, 24054 generic: true, 24055 }, 24056 { 24057 name: "AtomicLoad32", 24058 argLen: 2, 24059 generic: true, 24060 }, 24061 { 24062 name: "AtomicLoad64", 24063 argLen: 2, 24064 generic: true, 24065 }, 24066 { 24067 name: "AtomicLoadPtr", 24068 argLen: 2, 24069 generic: true, 24070 }, 24071 { 24072 name: "AtomicStore32", 24073 argLen: 3, 24074 hasSideEffects: true, 24075 generic: true, 24076 }, 24077 { 24078 name: "AtomicStore64", 24079 argLen: 3, 24080 hasSideEffects: true, 24081 generic: true, 24082 }, 24083 { 24084 name: "AtomicStorePtrNoWB", 24085 argLen: 3, 24086 hasSideEffects: true, 24087 generic: true, 24088 }, 24089 { 24090 name: "AtomicExchange32", 24091 argLen: 3, 24092 hasSideEffects: true, 24093 generic: true, 24094 }, 24095 { 24096 name: "AtomicExchange64", 24097 argLen: 3, 24098 hasSideEffects: true, 24099 generic: true, 24100 }, 24101 { 24102 name: "AtomicAdd32", 24103 argLen: 3, 24104 hasSideEffects: true, 24105 generic: true, 24106 }, 24107 { 24108 name: "AtomicAdd64", 24109 argLen: 3, 24110 hasSideEffects: true, 24111 generic: true, 24112 }, 24113 { 24114 name: "AtomicCompareAndSwap32", 24115 argLen: 4, 24116 hasSideEffects: true, 24117 generic: true, 24118 }, 24119 { 24120 name: "AtomicCompareAndSwap64", 24121 argLen: 4, 24122 hasSideEffects: true, 24123 generic: true, 24124 }, 24125 { 24126 name: "AtomicAnd8", 24127 argLen: 3, 24128 hasSideEffects: true, 24129 generic: true, 24130 }, 24131 { 24132 name: "AtomicOr8", 24133 argLen: 3, 24134 hasSideEffects: true, 24135 generic: true, 24136 }, 24137 { 24138 name: "Clobber", 24139 auxType: auxSymOff, 24140 argLen: 0, 24141 symEffect: SymNone, 24142 generic: true, 24143 }, 24144 } 24145 24146 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 24147 func (o Op) String() string { return opcodeTable[o].name } 24148 func (o Op) UsesScratch() bool { return opcodeTable[o].usesScratch } 24149 func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect } 24150 func (o Op) IsCall() bool { return opcodeTable[o].call } 24151 24152 var registers386 = [...]Register{ 24153 {0, x86.REG_AX, "AX"}, 24154 {1, x86.REG_CX, "CX"}, 24155 {2, x86.REG_DX, "DX"}, 24156 {3, x86.REG_BX, "BX"}, 24157 {4, x86.REGSP, "SP"}, 24158 {5, x86.REG_BP, "BP"}, 24159 {6, x86.REG_SI, "SI"}, 24160 {7, x86.REG_DI, "DI"}, 24161 {8, x86.REG_X0, "X0"}, 24162 {9, x86.REG_X1, "X1"}, 24163 {10, x86.REG_X2, "X2"}, 24164 {11, x86.REG_X3, "X3"}, 24165 {12, x86.REG_X4, "X4"}, 24166 {13, x86.REG_X5, "X5"}, 24167 {14, x86.REG_X6, "X6"}, 24168 {15, x86.REG_X7, "X7"}, 24169 {16, 0, "SB"}, 24170 } 24171 var gpRegMask386 = regMask(239) 24172 var fpRegMask386 = regMask(65280) 24173 var specialRegMask386 = regMask(0) 24174 var framepointerReg386 = int8(5) 24175 var linkReg386 = int8(-1) 24176 var registersAMD64 = [...]Register{ 24177 {0, x86.REG_AX, "AX"}, 24178 {1, x86.REG_CX, "CX"}, 24179 {2, x86.REG_DX, "DX"}, 24180 {3, x86.REG_BX, "BX"}, 24181 {4, x86.REGSP, "SP"}, 24182 {5, x86.REG_BP, "BP"}, 24183 {6, x86.REG_SI, "SI"}, 24184 {7, x86.REG_DI, "DI"}, 24185 {8, x86.REG_R8, "R8"}, 24186 {9, x86.REG_R9, "R9"}, 24187 {10, x86.REG_R10, "R10"}, 24188 {11, x86.REG_R11, "R11"}, 24189 {12, x86.REG_R12, "R12"}, 24190 {13, x86.REG_R13, "R13"}, 24191 {14, x86.REG_R14, "R14"}, 24192 {15, x86.REG_R15, "R15"}, 24193 {16, x86.REG_X0, "X0"}, 24194 {17, x86.REG_X1, "X1"}, 24195 {18, x86.REG_X2, "X2"}, 24196 {19, x86.REG_X3, "X3"}, 24197 {20, x86.REG_X4, "X4"}, 24198 {21, x86.REG_X5, "X5"}, 24199 {22, x86.REG_X6, "X6"}, 24200 {23, x86.REG_X7, "X7"}, 24201 {24, x86.REG_X8, "X8"}, 24202 {25, x86.REG_X9, "X9"}, 24203 {26, x86.REG_X10, "X10"}, 24204 {27, x86.REG_X11, "X11"}, 24205 {28, x86.REG_X12, "X12"}, 24206 {29, x86.REG_X13, "X13"}, 24207 {30, x86.REG_X14, "X14"}, 24208 {31, x86.REG_X15, "X15"}, 24209 {32, 0, "SB"}, 24210 } 24211 var gpRegMaskAMD64 = regMask(65519) 24212 var fpRegMaskAMD64 = regMask(4294901760) 24213 var specialRegMaskAMD64 = regMask(0) 24214 var framepointerRegAMD64 = int8(5) 24215 var linkRegAMD64 = int8(-1) 24216 var registersARM = [...]Register{ 24217 {0, arm.REG_R0, "R0"}, 24218 {1, arm.REG_R1, "R1"}, 24219 {2, arm.REG_R2, "R2"}, 24220 {3, arm.REG_R3, "R3"}, 24221 {4, arm.REG_R4, "R4"}, 24222 {5, arm.REG_R5, "R5"}, 24223 {6, arm.REG_R6, "R6"}, 24224 {7, arm.REG_R7, "R7"}, 24225 {8, arm.REG_R8, "R8"}, 24226 {9, arm.REG_R9, "R9"}, 24227 {10, arm.REGG, "g"}, 24228 {11, arm.REG_R11, "R11"}, 24229 {12, arm.REG_R12, "R12"}, 24230 {13, arm.REGSP, "SP"}, 24231 {14, arm.REG_R14, "R14"}, 24232 {15, arm.REG_R15, "R15"}, 24233 {16, arm.REG_F0, "F0"}, 24234 {17, arm.REG_F1, "F1"}, 24235 {18, arm.REG_F2, "F2"}, 24236 {19, arm.REG_F3, "F3"}, 24237 {20, arm.REG_F4, "F4"}, 24238 {21, arm.REG_F5, "F5"}, 24239 {22, arm.REG_F6, "F6"}, 24240 {23, arm.REG_F7, "F7"}, 24241 {24, arm.REG_F8, "F8"}, 24242 {25, arm.REG_F9, "F9"}, 24243 {26, arm.REG_F10, "F10"}, 24244 {27, arm.REG_F11, "F11"}, 24245 {28, arm.REG_F12, "F12"}, 24246 {29, arm.REG_F13, "F13"}, 24247 {30, arm.REG_F14, "F14"}, 24248 {31, arm.REG_F15, "F15"}, 24249 {32, 0, "SB"}, 24250 } 24251 var gpRegMaskARM = regMask(21503) 24252 var fpRegMaskARM = regMask(4294901760) 24253 var specialRegMaskARM = regMask(0) 24254 var framepointerRegARM = int8(-1) 24255 var linkRegARM = int8(14) 24256 var registersARM64 = [...]Register{ 24257 {0, arm64.REG_R0, "R0"}, 24258 {1, arm64.REG_R1, "R1"}, 24259 {2, arm64.REG_R2, "R2"}, 24260 {3, arm64.REG_R3, "R3"}, 24261 {4, arm64.REG_R4, "R4"}, 24262 {5, arm64.REG_R5, "R5"}, 24263 {6, arm64.REG_R6, "R6"}, 24264 {7, arm64.REG_R7, "R7"}, 24265 {8, arm64.REG_R8, "R8"}, 24266 {9, arm64.REG_R9, "R9"}, 24267 {10, arm64.REG_R10, "R10"}, 24268 {11, arm64.REG_R11, "R11"}, 24269 {12, arm64.REG_R12, "R12"}, 24270 {13, arm64.REG_R13, "R13"}, 24271 {14, arm64.REG_R14, "R14"}, 24272 {15, arm64.REG_R15, "R15"}, 24273 {16, arm64.REG_R16, "R16"}, 24274 {17, arm64.REG_R17, "R17"}, 24275 {18, arm64.REG_R18, "R18"}, 24276 {19, arm64.REG_R19, "R19"}, 24277 {20, arm64.REG_R20, "R20"}, 24278 {21, arm64.REG_R21, "R21"}, 24279 {22, arm64.REG_R22, "R22"}, 24280 {23, arm64.REG_R23, "R23"}, 24281 {24, arm64.REG_R24, "R24"}, 24282 {25, arm64.REG_R25, "R25"}, 24283 {26, arm64.REG_R26, "R26"}, 24284 {27, arm64.REGG, "g"}, 24285 {28, arm64.REG_R29, "R29"}, 24286 {29, arm64.REG_R30, "R30"}, 24287 {30, arm64.REGSP, "SP"}, 24288 {31, arm64.REG_F0, "F0"}, 24289 {32, arm64.REG_F1, "F1"}, 24290 {33, arm64.REG_F2, "F2"}, 24291 {34, arm64.REG_F3, "F3"}, 24292 {35, arm64.REG_F4, "F4"}, 24293 {36, arm64.REG_F5, "F5"}, 24294 {37, arm64.REG_F6, "F6"}, 24295 {38, arm64.REG_F7, "F7"}, 24296 {39, arm64.REG_F8, "F8"}, 24297 {40, arm64.REG_F9, "F9"}, 24298 {41, arm64.REG_F10, "F10"}, 24299 {42, arm64.REG_F11, "F11"}, 24300 {43, arm64.REG_F12, "F12"}, 24301 {44, arm64.REG_F13, "F13"}, 24302 {45, arm64.REG_F14, "F14"}, 24303 {46, arm64.REG_F15, "F15"}, 24304 {47, arm64.REG_F16, "F16"}, 24305 {48, arm64.REG_F17, "F17"}, 24306 {49, arm64.REG_F18, "F18"}, 24307 {50, arm64.REG_F19, "F19"}, 24308 {51, arm64.REG_F20, "F20"}, 24309 {52, arm64.REG_F21, "F21"}, 24310 {53, arm64.REG_F22, "F22"}, 24311 {54, arm64.REG_F23, "F23"}, 24312 {55, arm64.REG_F24, "F24"}, 24313 {56, arm64.REG_F25, "F25"}, 24314 {57, arm64.REG_F26, "F26"}, 24315 {58, arm64.REG_F27, "F27"}, 24316 {59, arm64.REG_F28, "F28"}, 24317 {60, arm64.REG_F29, "F29"}, 24318 {61, arm64.REG_F30, "F30"}, 24319 {62, arm64.REG_F31, "F31"}, 24320 {63, 0, "SB"}, 24321 } 24322 var gpRegMaskARM64 = regMask(670826495) 24323 var fpRegMaskARM64 = regMask(9223372034707292160) 24324 var specialRegMaskARM64 = regMask(0) 24325 var framepointerRegARM64 = int8(-1) 24326 var linkRegARM64 = int8(29) 24327 var registersMIPS = [...]Register{ 24328 {0, mips.REG_R0, "R0"}, 24329 {1, mips.REG_R1, "R1"}, 24330 {2, mips.REG_R2, "R2"}, 24331 {3, mips.REG_R3, "R3"}, 24332 {4, mips.REG_R4, "R4"}, 24333 {5, mips.REG_R5, "R5"}, 24334 {6, mips.REG_R6, "R6"}, 24335 {7, mips.REG_R7, "R7"}, 24336 {8, mips.REG_R8, "R8"}, 24337 {9, mips.REG_R9, "R9"}, 24338 {10, mips.REG_R10, "R10"}, 24339 {11, mips.REG_R11, "R11"}, 24340 {12, mips.REG_R12, "R12"}, 24341 {13, mips.REG_R13, "R13"}, 24342 {14, mips.REG_R14, "R14"}, 24343 {15, mips.REG_R15, "R15"}, 24344 {16, mips.REG_R16, "R16"}, 24345 {17, mips.REG_R17, "R17"}, 24346 {18, mips.REG_R18, "R18"}, 24347 {19, mips.REG_R19, "R19"}, 24348 {20, mips.REG_R20, "R20"}, 24349 {21, mips.REG_R21, "R21"}, 24350 {22, mips.REG_R22, "R22"}, 24351 {23, mips.REG_R24, "R24"}, 24352 {24, mips.REG_R25, "R25"}, 24353 {25, mips.REG_R28, "R28"}, 24354 {26, mips.REGSP, "SP"}, 24355 {27, mips.REGG, "g"}, 24356 {28, mips.REG_R31, "R31"}, 24357 {29, mips.REG_F0, "F0"}, 24358 {30, mips.REG_F2, "F2"}, 24359 {31, mips.REG_F4, "F4"}, 24360 {32, mips.REG_F6, "F6"}, 24361 {33, mips.REG_F8, "F8"}, 24362 {34, mips.REG_F10, "F10"}, 24363 {35, mips.REG_F12, "F12"}, 24364 {36, mips.REG_F14, "F14"}, 24365 {37, mips.REG_F16, "F16"}, 24366 {38, mips.REG_F18, "F18"}, 24367 {39, mips.REG_F20, "F20"}, 24368 {40, mips.REG_F22, "F22"}, 24369 {41, mips.REG_F24, "F24"}, 24370 {42, mips.REG_F26, "F26"}, 24371 {43, mips.REG_F28, "F28"}, 24372 {44, mips.REG_F30, "F30"}, 24373 {45, mips.REG_HI, "HI"}, 24374 {46, mips.REG_LO, "LO"}, 24375 {47, 0, "SB"}, 24376 } 24377 var gpRegMaskMIPS = regMask(335544318) 24378 var fpRegMaskMIPS = regMask(35183835217920) 24379 var specialRegMaskMIPS = regMask(105553116266496) 24380 var framepointerRegMIPS = int8(-1) 24381 var linkRegMIPS = int8(28) 24382 var registersMIPS64 = [...]Register{ 24383 {0, mips.REG_R0, "R0"}, 24384 {1, mips.REG_R1, "R1"}, 24385 {2, mips.REG_R2, "R2"}, 24386 {3, mips.REG_R3, "R3"}, 24387 {4, mips.REG_R4, "R4"}, 24388 {5, mips.REG_R5, "R5"}, 24389 {6, mips.REG_R6, "R6"}, 24390 {7, mips.REG_R7, "R7"}, 24391 {8, mips.REG_R8, "R8"}, 24392 {9, mips.REG_R9, "R9"}, 24393 {10, mips.REG_R10, "R10"}, 24394 {11, mips.REG_R11, "R11"}, 24395 {12, mips.REG_R12, "R12"}, 24396 {13, mips.REG_R13, "R13"}, 24397 {14, mips.REG_R14, "R14"}, 24398 {15, mips.REG_R15, "R15"}, 24399 {16, mips.REG_R16, "R16"}, 24400 {17, mips.REG_R17, "R17"}, 24401 {18, mips.REG_R18, "R18"}, 24402 {19, mips.REG_R19, "R19"}, 24403 {20, mips.REG_R20, "R20"}, 24404 {21, mips.REG_R21, "R21"}, 24405 {22, mips.REG_R22, "R22"}, 24406 {23, mips.REG_R24, "R24"}, 24407 {24, mips.REG_R25, "R25"}, 24408 {25, mips.REGSP, "SP"}, 24409 {26, mips.REGG, "g"}, 24410 {27, mips.REG_R31, "R31"}, 24411 {28, mips.REG_F0, "F0"}, 24412 {29, mips.REG_F1, "F1"}, 24413 {30, mips.REG_F2, "F2"}, 24414 {31, mips.REG_F3, "F3"}, 24415 {32, mips.REG_F4, "F4"}, 24416 {33, mips.REG_F5, "F5"}, 24417 {34, mips.REG_F6, "F6"}, 24418 {35, mips.REG_F7, "F7"}, 24419 {36, mips.REG_F8, "F8"}, 24420 {37, mips.REG_F9, "F9"}, 24421 {38, mips.REG_F10, "F10"}, 24422 {39, mips.REG_F11, "F11"}, 24423 {40, mips.REG_F12, "F12"}, 24424 {41, mips.REG_F13, "F13"}, 24425 {42, mips.REG_F14, "F14"}, 24426 {43, mips.REG_F15, "F15"}, 24427 {44, mips.REG_F16, "F16"}, 24428 {45, mips.REG_F17, "F17"}, 24429 {46, mips.REG_F18, "F18"}, 24430 {47, mips.REG_F19, "F19"}, 24431 {48, mips.REG_F20, "F20"}, 24432 {49, mips.REG_F21, "F21"}, 24433 {50, mips.REG_F22, "F22"}, 24434 {51, mips.REG_F23, "F23"}, 24435 {52, mips.REG_F24, "F24"}, 24436 {53, mips.REG_F25, "F25"}, 24437 {54, mips.REG_F26, "F26"}, 24438 {55, mips.REG_F27, "F27"}, 24439 {56, mips.REG_F28, "F28"}, 24440 {57, mips.REG_F29, "F29"}, 24441 {58, mips.REG_F30, "F30"}, 24442 {59, mips.REG_F31, "F31"}, 24443 {60, mips.REG_HI, "HI"}, 24444 {61, mips.REG_LO, "LO"}, 24445 {62, 0, "SB"}, 24446 } 24447 var gpRegMaskMIPS64 = regMask(167772158) 24448 var fpRegMaskMIPS64 = regMask(1152921504338411520) 24449 var specialRegMaskMIPS64 = regMask(3458764513820540928) 24450 var framepointerRegMIPS64 = int8(-1) 24451 var linkRegMIPS64 = int8(27) 24452 var registersPPC64 = [...]Register{ 24453 {0, ppc64.REG_R0, "R0"}, 24454 {1, ppc64.REGSP, "SP"}, 24455 {2, 0, "SB"}, 24456 {3, ppc64.REG_R3, "R3"}, 24457 {4, ppc64.REG_R4, "R4"}, 24458 {5, ppc64.REG_R5, "R5"}, 24459 {6, ppc64.REG_R6, "R6"}, 24460 {7, ppc64.REG_R7, "R7"}, 24461 {8, ppc64.REG_R8, "R8"}, 24462 {9, ppc64.REG_R9, "R9"}, 24463 {10, ppc64.REG_R10, "R10"}, 24464 {11, ppc64.REG_R11, "R11"}, 24465 {12, ppc64.REG_R12, "R12"}, 24466 {13, ppc64.REG_R13, "R13"}, 24467 {14, ppc64.REG_R14, "R14"}, 24468 {15, ppc64.REG_R15, "R15"}, 24469 {16, ppc64.REG_R16, "R16"}, 24470 {17, ppc64.REG_R17, "R17"}, 24471 {18, ppc64.REG_R18, "R18"}, 24472 {19, ppc64.REG_R19, "R19"}, 24473 {20, ppc64.REG_R20, "R20"}, 24474 {21, ppc64.REG_R21, "R21"}, 24475 {22, ppc64.REG_R22, "R22"}, 24476 {23, ppc64.REG_R23, "R23"}, 24477 {24, ppc64.REG_R24, "R24"}, 24478 {25, ppc64.REG_R25, "R25"}, 24479 {26, ppc64.REG_R26, "R26"}, 24480 {27, ppc64.REG_R27, "R27"}, 24481 {28, ppc64.REG_R28, "R28"}, 24482 {29, ppc64.REG_R29, "R29"}, 24483 {30, ppc64.REGG, "g"}, 24484 {31, ppc64.REG_R31, "R31"}, 24485 {32, ppc64.REG_F0, "F0"}, 24486 {33, ppc64.REG_F1, "F1"}, 24487 {34, ppc64.REG_F2, "F2"}, 24488 {35, ppc64.REG_F3, "F3"}, 24489 {36, ppc64.REG_F4, "F4"}, 24490 {37, ppc64.REG_F5, "F5"}, 24491 {38, ppc64.REG_F6, "F6"}, 24492 {39, ppc64.REG_F7, "F7"}, 24493 {40, ppc64.REG_F8, "F8"}, 24494 {41, ppc64.REG_F9, "F9"}, 24495 {42, ppc64.REG_F10, "F10"}, 24496 {43, ppc64.REG_F11, "F11"}, 24497 {44, ppc64.REG_F12, "F12"}, 24498 {45, ppc64.REG_F13, "F13"}, 24499 {46, ppc64.REG_F14, "F14"}, 24500 {47, ppc64.REG_F15, "F15"}, 24501 {48, ppc64.REG_F16, "F16"}, 24502 {49, ppc64.REG_F17, "F17"}, 24503 {50, ppc64.REG_F18, "F18"}, 24504 {51, ppc64.REG_F19, "F19"}, 24505 {52, ppc64.REG_F20, "F20"}, 24506 {53, ppc64.REG_F21, "F21"}, 24507 {54, ppc64.REG_F22, "F22"}, 24508 {55, ppc64.REG_F23, "F23"}, 24509 {56, ppc64.REG_F24, "F24"}, 24510 {57, ppc64.REG_F25, "F25"}, 24511 {58, ppc64.REG_F26, "F26"}, 24512 {59, ppc64.REG_F27, "F27"}, 24513 {60, ppc64.REG_F28, "F28"}, 24514 {61, ppc64.REG_F29, "F29"}, 24515 {62, ppc64.REG_F30, "F30"}, 24516 {63, ppc64.REG_F31, "F31"}, 24517 } 24518 var gpRegMaskPPC64 = regMask(1073733624) 24519 var fpRegMaskPPC64 = regMask(576460743713488896) 24520 var specialRegMaskPPC64 = regMask(0) 24521 var framepointerRegPPC64 = int8(1) 24522 var linkRegPPC64 = int8(-1) 24523 var registersS390X = [...]Register{ 24524 {0, s390x.REG_R0, "R0"}, 24525 {1, s390x.REG_R1, "R1"}, 24526 {2, s390x.REG_R2, "R2"}, 24527 {3, s390x.REG_R3, "R3"}, 24528 {4, s390x.REG_R4, "R4"}, 24529 {5, s390x.REG_R5, "R5"}, 24530 {6, s390x.REG_R6, "R6"}, 24531 {7, s390x.REG_R7, "R7"}, 24532 {8, s390x.REG_R8, "R8"}, 24533 {9, s390x.REG_R9, "R9"}, 24534 {10, s390x.REG_R10, "R10"}, 24535 {11, s390x.REG_R11, "R11"}, 24536 {12, s390x.REG_R12, "R12"}, 24537 {13, s390x.REGG, "g"}, 24538 {14, s390x.REG_R14, "R14"}, 24539 {15, s390x.REGSP, "SP"}, 24540 {16, s390x.REG_F0, "F0"}, 24541 {17, s390x.REG_F1, "F1"}, 24542 {18, s390x.REG_F2, "F2"}, 24543 {19, s390x.REG_F3, "F3"}, 24544 {20, s390x.REG_F4, "F4"}, 24545 {21, s390x.REG_F5, "F5"}, 24546 {22, s390x.REG_F6, "F6"}, 24547 {23, s390x.REG_F7, "F7"}, 24548 {24, s390x.REG_F8, "F8"}, 24549 {25, s390x.REG_F9, "F9"}, 24550 {26, s390x.REG_F10, "F10"}, 24551 {27, s390x.REG_F11, "F11"}, 24552 {28, s390x.REG_F12, "F12"}, 24553 {29, s390x.REG_F13, "F13"}, 24554 {30, s390x.REG_F14, "F14"}, 24555 {31, s390x.REG_F15, "F15"}, 24556 {32, 0, "SB"}, 24557 } 24558 var gpRegMaskS390X = regMask(21503) 24559 var fpRegMaskS390X = regMask(4294901760) 24560 var specialRegMaskS390X = regMask(0) 24561 var framepointerRegS390X = int8(-1) 24562 var linkRegS390X = int8(14)