github.com/epfl-dcsl/gotee@v0.0.0-20200909122901-014b35f5e5e9/src/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167 ) 168 169 // bits 0-4 indicates register: Vn 170 // bits 5-8 indicates arrangement: <T> 171 const ( 172 REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> 173 REG_ELEM // Vn.<T>[index] 174 REG_ELEM_END 175 ) 176 177 // Not registers, but flags that can be combined with regular register 178 // constants to indicate extended register conversion. When checking, 179 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 180 // indicates extended register, bits 8-10 select the conversion mode. 181 const REG_EXT = obj.RBaseARM64 + 1<<11 182 183 const ( 184 REG_UXTB = REG_EXT + iota<<8 185 REG_UXTH 186 REG_UXTW 187 REG_UXTX 188 REG_SXTB 189 REG_SXTH 190 REG_SXTW 191 REG_SXTX 192 ) 193 194 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 195 // a special register and the low bits select the register. 196 const ( 197 REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota 198 REG_DAIF 199 REG_NZCV 200 REG_FPSR 201 REG_FPCR 202 REG_SPSR_EL1 203 REG_ELR_EL1 204 REG_SPSR_EL2 205 REG_ELR_EL2 206 REG_CurrentEL 207 REG_SP_EL0 208 REG_SPSel 209 REG_DAIFSet 210 REG_DAIFClr 211 ) 212 213 // Register assignments: 214 // 215 // compiler allocates R0 up as temps 216 // compiler allocates register variables R7-R25 217 // compiler allocates external registers R26 down 218 // 219 // compiler allocates register variables F7-F26 220 // compiler allocates external registers F26 down 221 const ( 222 REGMIN = REG_R7 // register variables allocated from here to REGMAX 223 REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy 224 REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy 225 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 226 REGMAX = REG_R25 227 228 REGCTXT = REG_R26 // environment for closures 229 REGTMP = REG_R27 // reserved for liblink 230 REGG = REG_R28 // G 231 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 232 REGLINK = REG_R30 233 234 // ARM64 uses R31 as both stack pointer and zero register, 235 // depending on the instruction. To differentiate RSP from ZR, 236 // we use a different numeric value for REGZERO and REGSP. 237 REGZERO = REG_R31 238 REGSP = REG_RSP 239 240 FREGRET = REG_F0 241 FREGMIN = REG_F7 // first register variable 242 FREGMAX = REG_F26 // last register variable for 7g only 243 FREGEXT = REG_F26 // first external register 244 ) 245 246 const ( 247 BIG = 2048 - 8 248 ) 249 250 const ( 251 /* mark flags */ 252 LABEL = 1 << iota 253 LEAF 254 FLOAT 255 BRANCH 256 LOAD 257 FCMP 258 SYNC 259 LIST 260 FOLL 261 NOSCHED 262 ) 263 264 const ( 265 // optab is sorted based on the order of these constants 266 // and the first match is chosen. 267 // The more specific class needs to come earlier. 268 C_NONE = iota 269 C_REG // R0..R30 270 C_RSP // R0..R30, RSP 271 C_FREG // F0..F31 272 C_VREG // V0..V31 273 C_PAIR // (Rn, Rm) 274 C_SHIFT // Rn<<2 275 C_EXTREG // Rn.UXTB[<<3] 276 C_SPR // REG_NZCV 277 C_COND // EQ, NE, etc 278 C_ARNG // Vn.<T> 279 C_ELEM // Vn.<T>[index] 280 C_LIST // [V1, V2, V3] 281 282 C_ZCON // $0 or ZR 283 C_ABCON0 // could be C_ADDCON0 or C_BITCON 284 C_ADDCON0 // 12-bit unsigned, unshifted 285 C_ABCON // could be C_ADDCON or C_BITCON 286 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 287 C_MBCON // could be C_MOVCON or C_BITCON 288 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 289 C_BITCON // bitfield and logical immediate masks 290 C_LCON // 32-bit constant 291 C_VCON // 64-bit constant 292 C_FCON // floating-point constant 293 C_VCONADDR // 64-bit memory address 294 295 C_AACON // ADDCON offset in auto constant $a(FP) 296 C_LACON // 32-bit offset in auto constant $a(FP) 297 C_AECON // ADDCON offset in extern constant $e(SB) 298 299 // TODO(aram): only one branch class should be enough 300 C_SBRA // for TYPE_BRANCH 301 C_LBRA 302 303 C_NPAUTO // -512 <= x < 0, 0 mod 8 304 C_NSAUTO // -256 <= x < 0 305 C_PSAUTO_8 // 0 to 255, 0 mod 8 306 C_PSAUTO // 0 to 255 307 C_PPAUTO // 0 to 504, 0 mod 8 308 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 309 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 310 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 311 C_UAUTO4K // 0 to 4095 312 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 313 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 314 C_UAUTO8K // 0 to 8190, 0 mod 2 315 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 316 C_UAUTO16K // 0 to 16380, 0 mod 4 317 C_UAUTO32K // 0 to 32760, 0 mod 8 318 C_LAUTO // any other 32-bit constant 319 320 C_SEXT1 // 0 to 4095, direct 321 C_SEXT2 // 0 to 8190 322 C_SEXT4 // 0 to 16380 323 C_SEXT8 // 0 to 32760 324 C_SEXT16 // 0 to 65520 325 C_LEXT 326 327 C_ZOREG // 0(R) 328 C_NPOREG // must mirror NPAUTO, etc 329 C_NSOREG 330 C_PSOREG_8 331 C_PSOREG 332 C_PPOREG 333 C_UOREG4K_8 334 C_UOREG4K_4 335 C_UOREG4K_2 336 C_UOREG4K 337 C_UOREG8K_8 338 C_UOREG8K_4 339 C_UOREG8K 340 C_UOREG16K_8 341 C_UOREG16K 342 C_UOREG32K 343 C_LOREG 344 345 C_ADDR // TODO(aram): explain difference from C_VCONADDR 346 347 // The GOT slot for a symbol in -dynlink mode. 348 C_GOTADDR 349 350 // TLS "var" in local exec mode: will become a constant offset from 351 // thread local base that is ultimately chosen by the program linker. 352 C_TLS_LE 353 354 // TLS "var" in initial exec mode: will become a memory address (chosen 355 // by the program linker) that the dynamic linker will fill with the 356 // offset from the thread local base. 357 C_TLS_IE 358 359 C_ROFF // register offset (including register extended) 360 361 C_GOK 362 C_TEXTSIZE 363 C_NCLASS // must be last 364 ) 365 366 const ( 367 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 368 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 369 ) 370 371 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 372 373 const ( 374 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 375 AADCS 376 AADCSW 377 AADCW 378 AADD 379 AADDS 380 AADDSW 381 AADDW 382 AADR 383 AADRP 384 AAND 385 AANDS 386 AANDSW 387 AANDW 388 AASR 389 AASRW 390 AAT 391 ABFI 392 ABFIW 393 ABFM 394 ABFMW 395 ABFXIL 396 ABFXILW 397 ABIC 398 ABICS 399 ABICSW 400 ABICW 401 ABRK 402 ACBNZ 403 ACBNZW 404 ACBZ 405 ACBZW 406 ACCMN 407 ACCMNW 408 ACCMP 409 ACCMPW 410 ACINC 411 ACINCW 412 ACINV 413 ACINVW 414 ACLREX 415 ACLS 416 ACLSW 417 ACLZ 418 ACLZW 419 ACMN 420 ACMNW 421 ACMP 422 ACMPW 423 ACNEG 424 ACNEGW 425 ACRC32B 426 ACRC32CB 427 ACRC32CH 428 ACRC32CW 429 ACRC32CX 430 ACRC32H 431 ACRC32W 432 ACRC32X 433 ACSEL 434 ACSELW 435 ACSET 436 ACSETM 437 ACSETMW 438 ACSETW 439 ACSINC 440 ACSINCW 441 ACSINV 442 ACSINVW 443 ACSNEG 444 ACSNEGW 445 ADC 446 ADCPS1 447 ADCPS2 448 ADCPS3 449 ADMB 450 ADRPS 451 ADSB 452 AEON 453 AEONW 454 AEOR 455 AEORW 456 AERET 457 AEXTR 458 AEXTRW 459 AHINT 460 AHLT 461 AHVC 462 AIC 463 AISB 464 ALDAR 465 ALDARB 466 ALDARH 467 ALDARW 468 ALDAXP 469 ALDAXPW 470 ALDAXR 471 ALDAXRB 472 ALDAXRH 473 ALDAXRW 474 ALDP 475 ALDXR 476 ALDXRB 477 ALDXRH 478 ALDXRW 479 ALDXP 480 ALDXPW 481 ALSL 482 ALSLW 483 ALSR 484 ALSRW 485 AMADD 486 AMADDW 487 AMNEG 488 AMNEGW 489 AMOVK 490 AMOVKW 491 AMOVN 492 AMOVNW 493 AMOVZ 494 AMOVZW 495 AMRS 496 AMSR 497 AMSUB 498 AMSUBW 499 AMUL 500 AMULW 501 AMVN 502 AMVNW 503 ANEG 504 ANEGS 505 ANEGSW 506 ANEGW 507 ANGC 508 ANGCS 509 ANGCSW 510 ANGCW 511 AORN 512 AORNW 513 AORR 514 AORRW 515 APRFM 516 APRFUM 517 ARBIT 518 ARBITW 519 AREM 520 AREMW 521 AREV 522 AREV16 523 AREV16W 524 AREV32 525 AREVW 526 AROR 527 ARORW 528 ASBC 529 ASBCS 530 ASBCSW 531 ASBCW 532 ASBFIZ 533 ASBFIZW 534 ASBFM 535 ASBFMW 536 ASBFX 537 ASBFXW 538 ASDIV 539 ASDIVW 540 ASEV 541 ASEVL 542 ASMADDL 543 ASMC 544 ASMNEGL 545 ASMSUBL 546 ASMULH 547 ASMULL 548 ASTXR 549 ASTXRB 550 ASTXRH 551 ASTXP 552 ASTXPW 553 ASTXRW 554 ASTLP 555 ASTLPW 556 ASTLR 557 ASTLRB 558 ASTLRH 559 ASTLRW 560 ASTLXP 561 ASTLXPW 562 ASTLXR 563 ASTLXRB 564 ASTLXRH 565 ASTLXRW 566 ASTP 567 ASUB 568 ASUBS 569 ASUBSW 570 ASUBW 571 ASVC 572 ASXTB 573 ASXTBW 574 ASXTH 575 ASXTHW 576 ASXTW 577 ASYS 578 ASYSL 579 ATBNZ 580 ATBZ 581 ATLBI 582 ATST 583 ATSTW 584 AUBFIZ 585 AUBFIZW 586 AUBFM 587 AUBFMW 588 AUBFX 589 AUBFXW 590 AUDIV 591 AUDIVW 592 AUMADDL 593 AUMNEGL 594 AUMSUBL 595 AUMULH 596 AUMULL 597 AUREM 598 AUREMW 599 AUXTB 600 AUXTH 601 AUXTW 602 AUXTBW 603 AUXTHW 604 AWFE 605 AWFI 606 AYIELD 607 AMOVB 608 AMOVBU 609 AMOVH 610 AMOVHU 611 AMOVW 612 AMOVWU 613 AMOVD 614 AMOVNP 615 AMOVNPW 616 AMOVP 617 AMOVPD 618 AMOVPQ 619 AMOVPS 620 AMOVPSW 621 AMOVPW 622 ABEQ 623 ABNE 624 ABCS 625 ABHS 626 ABCC 627 ABLO 628 ABMI 629 ABPL 630 ABVS 631 ABVC 632 ABHI 633 ABLS 634 ABGE 635 ABLT 636 ABGT 637 ABLE 638 AFABSD 639 AFABSS 640 AFADDD 641 AFADDS 642 AFCCMPD 643 AFCCMPED 644 AFCCMPS 645 AFCCMPES 646 AFCMPD 647 AFCMPED 648 AFCMPES 649 AFCMPS 650 AFCVTSD 651 AFCVTDS 652 AFCVTZSD 653 AFCVTZSDW 654 AFCVTZSS 655 AFCVTZSSW 656 AFCVTZUD 657 AFCVTZUDW 658 AFCVTZUS 659 AFCVTZUSW 660 AFDIVD 661 AFDIVS 662 AFMOVD 663 AFMOVS 664 AFMULD 665 AFMULS 666 AFNEGD 667 AFNEGS 668 AFSQRTD 669 AFSQRTS 670 AFSUBD 671 AFSUBS 672 ASCVTFD 673 ASCVTFS 674 ASCVTFWD 675 ASCVTFWS 676 AUCVTFD 677 AUCVTFS 678 AUCVTFWD 679 AUCVTFWS 680 AWORD 681 ADWORD 682 AFCSELS 683 AFCSELD 684 AFMAXS 685 AFMINS 686 AFMAXD 687 AFMIND 688 AFMAXNMS 689 AFMAXNMD 690 AFNMULS 691 AFNMULD 692 AFRINTNS 693 AFRINTND 694 AFRINTPS 695 AFRINTPD 696 AFRINTMS 697 AFRINTMD 698 AFRINTZS 699 AFRINTZD 700 AFRINTAS 701 AFRINTAD 702 AFRINTXS 703 AFRINTXD 704 AFRINTIS 705 AFRINTID 706 AFMADDS 707 AFMADDD 708 AFMSUBS 709 AFMSUBD 710 AFNMADDS 711 AFNMADDD 712 AFNMSUBS 713 AFNMSUBD 714 AFMINNMS 715 AFMINNMD 716 AFCVTDH 717 AFCVTHS 718 AFCVTHD 719 AFCVTSH 720 AAESD 721 AAESE 722 AAESIMC 723 AAESMC 724 ASHA1C 725 ASHA1H 726 ASHA1M 727 ASHA1P 728 ASHA1SU0 729 ASHA1SU1 730 ASHA256H 731 ASHA256H2 732 ASHA256SU0 733 ASHA256SU1 734 AVADD 735 AVADDP 736 AVAND 737 AVCMEQ 738 AVEOR 739 AVMOV 740 AVLD1 741 AVORR 742 AVREV32 743 AVST1 744 AVDUP 745 AVMOVS 746 AVADDV 747 AVMOVI 748 AVUADDLV 749 AVSUB 750 ALAST 751 AB = obj.AJMP 752 ABL = obj.ACALL 753 ) 754 755 const ( 756 // shift types 757 SHIFT_LL = 0 << 22 758 SHIFT_LR = 1 << 22 759 SHIFT_AR = 2 << 22 760 ) 761 762 // Arrangement for ARM64 SIMD instructions 763 const ( 764 // arrangement types 765 ARNG_8B = iota 766 ARNG_16B 767 ARNG_1D 768 ARNG_4H 769 ARNG_8H 770 ARNG_2S 771 ARNG_4S 772 ARNG_2D 773 ARNG_B 774 ARNG_H 775 ARNG_S 776 ARNG_D 777 )