github.com/epfl-dcsl/gotee@v0.0.0-20200909122901-014b35f5e5e9/src/cmd/internal/obj/arm64/doc.go (about)

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package arm64
     6  
     7  /*
     8  
     9  Go Assembly for ARM64 Reference Manual
    10  
    11  1. Alphabetical list of basic instructions
    12      // TODO
    13  
    14  2. Alphabetical list of float-point instructions
    15      // TODO
    16  
    17  3. Alphabetical list of SIMD instructions
    18      VADD: Add (scalar)
    19        VADD	<Vm>, <Vn>, <Vd>
    20          Add corresponding low 64-bit elements in <Vm> and <Vn>,
    21          place the result into low 64-bit element of <Vd>.
    22  
    23      VADD: Add (vector).
    24        VADD	<Vm>.T, <Vn>.<T>, <Vd>.<T>
    25          <T> Is an arrangement specifier and can have the following values:
    26          8B, 16B, H4, H8, S2, S4, D2
    27  
    28      VADDP: Add Pairwise (vector)
    29        VADDP	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    30          <T> Is an arrangement specifier and can have the following values:
    31          B8, B16, H4, H8, S2, S4, D2
    32  
    33      VADDV: Add across Vector.
    34        VADDV	<Vn>.<T>, Vd
    35          <T> Is an arrangement specifier and can have the following values:
    36          8B, 16B, H4, H8, S4
    37  
    38      VAND: Bitwise AND (vector)
    39        VAND	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    40          <T> Is an arrangement specifier and can have the following values:
    41          B8, B16
    42  
    43      VCMEQ: Compare bitwise Equal (vector)
    44        VCMEQ	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    45          <T> Is an arrangement specifier and can have the following values:
    46          B8, B16, H4, H8, S2, S4, D2
    47  
    48      VDUP: Duplicate vector element to vector or scalar.
    49        VDUP	<Vn>.<Ts>[index], <Vd>.<T>
    50          <T> Is an arrangement specifier and can have the following values:
    51          8B, 16B, H4, H8, S2, S4, D2
    52          <Ts> Is an element size specifier and can have the following values:
    53          B, H, S, D
    54  
    55      VEOR: Bitwise exclusive OR (vector, register)
    56        VEOR	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
    57          <T> Is an arrangement specifier and can have the following values:
    58          B8, B16
    59  
    60      VLD1: Load multiple single-element structures
    61        VLD1	(Rn), [<Vt>.<T>, <Vt2>.<T> ...]     // no offset
    62        VLD1.P	imm(Rn), [<Vt>.<T>, <Vt2>.<T> ...]  // immediate offset variant
    63        VLD1.P	(Rn)(Rm), [<Vt>.<T>, <Vt2>.<T> ...] // register offset variant
    64          <T> Is an arrangement specifier and can have the following values:
    65          B8, B16, H4, H8, S2, S4, D1, D2
    66  
    67      VMOV: move
    68        VMOV	<Vn>.<T>[index], Rd // Move vector element to general-purpose register.
    69          <T> Is a source width specifier and can have the following values:
    70          B, H, S (Wd)
    71          D (Xd)
    72  
    73        VMOV	Rn, <Vd>.<T> // Duplicate general-purpose register to vector.
    74          <T> Is an arrangement specifier and can have the following values:
    75          B8, B16, H4, H8, S2, S4 (Wn)
    76          D2 (Xn)
    77  
    78        VMOV	<Vn>.<T>, <Vd>.<T> // Move vector.
    79          <T> Is an arrangement specifier and can have the following values:
    80          B8, B16
    81  
    82        VMOV	Rn, <Vd>.<T>[index] // Move general-purpose register to a vector element.
    83          <T> Is a source width specifier and can have the following values:
    84          B, H, S (Wd)
    85          D (Xd)
    86  
    87        VMOV	<Vn>.<T>[index], Vn  // Move vector element to scalar.
    88          <T> Is an element size specifier and can have the following values:
    89          B, H, S, D
    90  
    91      VMOVI: Move Immediate (vector).
    92        VMOVI	$imm8, <Vd>.<T>
    93          <T> is an arrangement specifier and can have the following values:
    94          8B, 16B
    95  
    96      VMOVS: Load SIMD&FP Register (immediate offset). ARMv8: LDR (immediate, SIMD&FP)
    97        Store SIMD&FP register (immediate offset). ARMv8: STR (immediate, SIMD&FP)
    98        VMOVS	(Rn), Vn
    99        VMOVS.W	imm(Rn), Vn
   100        VMOVS.P	imm(Rn), Vn
   101        VMOVS	Vn, (Rn)
   102        VMOVS.W	Vn, imm(Rn)
   103        VMOVS.P	Vn, imm(Rn)
   104  
   105      VORR: Bitwise inclusive OR (vector, register)
   106        VORR	<Vm>.<T>, <Vn>.<T>, <Vd>.<T>
   107          <T> Is an arrangement specifier and can have the following values:
   108          B8, B16
   109  
   110      VREV32: Reverse elements in 32-bit words (vector).
   111        REV32 <Vn>.<T>, <Vd>.<T>
   112          <T> Is an arrangement specifier and can have the following values:
   113          B8, B16, H4, H8
   114  
   115      VST1: Store multiple single-element structures
   116        VST1	[<Vt>.<T>, <Vt2>.<T> ...], (Rn)         // no offset
   117        VST1.P	[<Vt>.<T>, <Vt2>.<T> ...], imm(Rn)      // immediate offset variant
   118        VST1.P	[<Vt>.<T>, <Vt2>.<T> ...], (Rn)(Rm)     // register offset variant
   119          <T> Is an arrangement specifier and can have the following values:
   120          B8, B16, H4, H8, S2, S4, D1, D2
   121  
   122      VSUB: Sub (scalar)
   123        VSUB	<Vm>, <Vn>, <Vd>
   124          Subtract low 64-bit element in <Vm> from the correponding element in <Vn>,
   125          place the result into low 64-bit element of <Vd>.
   126  
   127      VUADDLV: Unsigned sum Long across Vector.
   128        VUADDLV	<Vn>.<T>, Vd
   129          <T> Is an arrangement specifier and can have the following values:
   130          8B, 16B, H4, H8, S4
   131  
   132  4. Alphabetical list of cryptographic extension instructions
   133  
   134      SHA1C, SHA1M, SHA1P: SHA1 hash update.
   135        SHA1C	<Vm>.S4, Vn, Vd
   136        SHA1M	<Vm>.S4, Vn, Vd
   137        SHA1P	<Vm>.S4, Vn, Vd
   138  
   139      SHA1H: SHA1 fixed rotate.
   140        SHA1H	Vn, Vd
   141  
   142      SHA1SU0:   SHA1 schedule update 0.
   143      SHA256SU1: SHA256 schedule update 1.
   144        SHA1SU0	<Vm>.S4, <Vn>.S4, <Vd>.S4
   145        SHA256SU1	<Vm>.S4, <Vn>.S4, <Vd>.S4
   146  
   147      SHA1SU1:   SHA1 schedule update 1.
   148      SHA256SU0: SHA256 schedule update 0.
   149        SHA1SU1	<Vn>.S4, <Vd>.S4
   150        SHA256SU0	<Vn>.S4, <Vd>.S4
   151  
   152      SHA256H, SHA256H2: SHA256 hash update.
   153        SHA256H	<Vm>.S4, Vn, Vd
   154        SHA256H2	<Vm>.S4, Vn, Vd
   155  
   156  
   157  */