github.com/epfl-dcsl/gotee@v0.0.0-20200909122901-014b35f5e5e9/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 16 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form */ 366 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 367 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 368 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */ 369 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */ 370 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */ 371 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */ 372 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */ 373 374 /* Vector instructions */ 375 376 /* Vector load */ 377 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 378 379 /* Vector store */ 380 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 381 382 /* Vector logical */ 383 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 384 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 385 386 /* Vector add */ 387 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 388 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 389 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 390 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 391 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 392 393 /* Vector subtract */ 394 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 395 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 396 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 397 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 398 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 399 400 /* Vector multiply */ 401 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 402 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */ 403 404 /* Vector rotate */ 405 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 406 407 /* Vector shift */ 408 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 409 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 410 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 411 412 /* Vector count */ 413 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 414 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 415 416 /* Vector compare */ 417 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 418 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 419 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */ 420 421 /* Vector permute */ 422 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 423 424 /* Vector bit permute */ 425 {AVBPERMQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector bit permute, vx-form */ 426 427 /* Vector select */ 428 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 429 430 /* Vector splat */ 431 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 432 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 433 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 434 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 435 436 /* Vector AES */ 437 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 438 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 439 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 440 441 /* Vector SHA */ 442 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 443 444 /* VSX vector load */ 445 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 446 447 /* VSX vector store */ 448 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 449 450 /* VSX scalar load */ 451 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 452 453 /* VSX scalar store */ 454 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 455 456 /* VSX scalar as integer load */ 457 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 458 459 /* VSX scalar store as integer */ 460 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 461 462 /* VSX move from VSR */ 463 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 464 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 465 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 466 467 /* VSX move to VSR */ 468 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 469 {AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0}, 470 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 471 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 472 473 /* VSX logical */ 474 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 475 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 476 477 /* VSX select */ 478 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 479 480 /* VSX merge */ 481 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 482 483 /* VSX splat */ 484 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 485 486 /* VSX permute */ 487 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 488 489 /* VSX shift */ 490 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 491 492 /* VSX scalar FP-FP conversion */ 493 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 494 495 /* VSX vector FP-FP conversion */ 496 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 497 498 /* VSX scalar FP-integer conversion */ 499 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 500 501 /* VSX scalar integer-FP conversion */ 502 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 503 504 /* VSX vector FP-integer conversion */ 505 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 506 507 /* VSX vector integer-FP conversion */ 508 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 509 510 /* 64-bit special registers */ 511 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 512 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 513 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 514 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 515 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 516 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 517 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 518 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 519 520 /* 32-bit special registers (gloss over sign-extension or not?) */ 521 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 522 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 523 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 524 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 525 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 526 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 527 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 528 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 529 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 530 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 531 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 532 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 533 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 534 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 535 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 536 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 537 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 538 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 539 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 540 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 541 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 542 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 543 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 544 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 545 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 546 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 547 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 548 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 549 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 550 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 551 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 552 {ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 553 {ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0}, 554 {ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0}, 555 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 556 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 557 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 558 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 559 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 560 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 561 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 562 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 563 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 564 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 565 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 566 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 567 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 568 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 569 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 570 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 571 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 572 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 573 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 574 575 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 576 } 577 578 var oprange [ALAST & obj.AMask][]Optab 579 580 var xcmp [C_NCLASS][C_NCLASS]bool 581 582 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 583 p := cursym.Func.Text 584 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 585 return 586 } 587 588 if oprange[AANDN&obj.AMask] == nil { 589 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 590 } 591 592 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 593 594 pc := int64(0) 595 p.Pc = pc 596 597 var m int 598 var o *Optab 599 for p = p.Link; p != nil; p = p.Link { 600 p.Pc = pc 601 o = c.oplook(p) 602 m = int(o.size) 603 if m == 0 { 604 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 605 c.ctxt.Diag("zero-width instruction\n%v", p) 606 } 607 continue 608 } 609 610 pc += int64(m) 611 } 612 613 c.cursym.Size = pc 614 615 /* 616 * if any procedure is large enough to 617 * generate a large SBRA branch, then 618 * generate extra passes putting branches 619 * around jmps to fix. this is rare. 620 */ 621 bflag := 1 622 623 var otxt int64 624 var q *obj.Prog 625 for bflag != 0 { 626 bflag = 0 627 pc = 0 628 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 629 p.Pc = pc 630 o = c.oplook(p) 631 632 // very large conditional branches 633 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 634 otxt = p.Pcond.Pc - pc 635 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 636 q = c.newprog() 637 q.Link = p.Link 638 p.Link = q 639 q.As = ABR 640 q.To.Type = obj.TYPE_BRANCH 641 q.Pcond = p.Pcond 642 p.Pcond = q 643 q = c.newprog() 644 q.Link = p.Link 645 p.Link = q 646 q.As = ABR 647 q.To.Type = obj.TYPE_BRANCH 648 q.Pcond = q.Link.Link 649 650 //addnop(p->link); 651 //addnop(p); 652 bflag = 1 653 } 654 } 655 656 m = int(o.size) 657 if m == 0 { 658 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 659 c.ctxt.Diag("zero-width instruction\n%v", p) 660 } 661 continue 662 } 663 664 pc += int64(m) 665 } 666 667 c.cursym.Size = pc 668 } 669 670 pc += -pc & (funcAlign - 1) 671 c.cursym.Size = pc 672 673 /* 674 * lay out the code, emitting code and data relocations. 675 */ 676 677 c.cursym.Grow(c.cursym.Size) 678 679 bp := c.cursym.P 680 var i int32 681 var out [6]uint32 682 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 683 c.pc = p.Pc 684 o = c.oplook(p) 685 if int(o.size) > 4*len(out) { 686 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 687 } 688 c.asmout(p, o, out[:]) 689 for i = 0; i < int32(o.size/4); i++ { 690 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 691 bp = bp[4:] 692 } 693 } 694 } 695 696 func isint32(v int64) bool { 697 return int64(int32(v)) == v 698 } 699 700 func isuint32(v uint64) bool { 701 return uint64(uint32(v)) == v 702 } 703 704 func (c *ctxt9) aclass(a *obj.Addr) int { 705 switch a.Type { 706 case obj.TYPE_NONE: 707 return C_NONE 708 709 case obj.TYPE_REG: 710 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 711 return C_REG 712 } 713 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 714 return C_FREG 715 } 716 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 717 return C_VREG 718 } 719 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 720 return C_VSREG 721 } 722 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 723 return C_CREG 724 } 725 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 726 switch a.Reg { 727 case REG_LR: 728 return C_LR 729 730 case REG_XER: 731 return C_XER 732 733 case REG_CTR: 734 return C_CTR 735 } 736 737 return C_SPR 738 } 739 740 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 741 return C_SPR 742 } 743 if a.Reg == REG_FPSCR { 744 return C_FPSCR 745 } 746 if a.Reg == REG_MSR { 747 return C_MSR 748 } 749 return C_GOK 750 751 case obj.TYPE_MEM: 752 switch a.Name { 753 case obj.NAME_EXTERN, 754 obj.NAME_STATIC: 755 if a.Sym == nil { 756 break 757 } 758 c.instoffset = a.Offset 759 if a.Sym != nil { // use relocation 760 if a.Sym.Type == objabi.STLSBSS { 761 if c.ctxt.Flag_shared { 762 return C_TLS_IE 763 } else { 764 return C_TLS_LE 765 } 766 } 767 return C_ADDR 768 } 769 return C_LEXT 770 771 case obj.NAME_GOTREF: 772 return C_GOTADDR 773 774 case obj.NAME_AUTO: 775 c.instoffset = int64(c.autosize) + a.Offset 776 if c.instoffset >= -BIG && c.instoffset < BIG { 777 return C_SAUTO 778 } 779 return C_LAUTO 780 781 case obj.NAME_PARAM: 782 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 783 if c.instoffset >= -BIG && c.instoffset < BIG { 784 return C_SAUTO 785 } 786 return C_LAUTO 787 788 case obj.NAME_NONE: 789 c.instoffset = a.Offset 790 if c.instoffset == 0 { 791 return C_ZOREG 792 } 793 if c.instoffset >= -BIG && c.instoffset < BIG { 794 return C_SOREG 795 } 796 return C_LOREG 797 } 798 799 return C_GOK 800 801 case obj.TYPE_TEXTSIZE: 802 return C_TEXTSIZE 803 804 case obj.TYPE_CONST, 805 obj.TYPE_ADDR: 806 switch a.Name { 807 case obj.NAME_NONE: 808 c.instoffset = a.Offset 809 if a.Reg != 0 { 810 if -BIG <= c.instoffset && c.instoffset <= BIG { 811 return C_SACON 812 } 813 if isint32(c.instoffset) { 814 return C_LACON 815 } 816 return C_DACON 817 } 818 819 goto consize 820 821 case obj.NAME_EXTERN, 822 obj.NAME_STATIC: 823 s := a.Sym 824 if s == nil { 825 break 826 } 827 828 c.instoffset = a.Offset 829 830 /* not sure why this barfs */ 831 return C_LCON 832 833 case obj.NAME_AUTO: 834 c.instoffset = int64(c.autosize) + a.Offset 835 if c.instoffset >= -BIG && c.instoffset < BIG { 836 return C_SACON 837 } 838 return C_LACON 839 840 case obj.NAME_PARAM: 841 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 842 if c.instoffset >= -BIG && c.instoffset < BIG { 843 return C_SACON 844 } 845 return C_LACON 846 } 847 848 return C_GOK 849 850 consize: 851 if c.instoffset >= 0 { 852 if c.instoffset == 0 { 853 return C_ZCON 854 } 855 if c.instoffset <= 0x7fff { 856 return C_SCON 857 } 858 if c.instoffset <= 0xffff { 859 return C_ANDCON 860 } 861 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 862 return C_UCON 863 } 864 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 865 return C_LCON 866 } 867 return C_DCON 868 } 869 870 if c.instoffset >= -0x8000 { 871 return C_ADDCON 872 } 873 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 874 return C_UCON 875 } 876 if isint32(c.instoffset) { 877 return C_LCON 878 } 879 return C_DCON 880 881 case obj.TYPE_BRANCH: 882 if a.Sym != nil && c.ctxt.Flag_dynlink { 883 return C_LBRAPIC 884 } 885 return C_SBRA 886 } 887 888 return C_GOK 889 } 890 891 func prasm(p *obj.Prog) { 892 fmt.Printf("%v\n", p) 893 } 894 895 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 896 a1 := int(p.Optab) 897 if a1 != 0 { 898 return &optab[a1-1] 899 } 900 a1 = int(p.From.Class) 901 if a1 == 0 { 902 a1 = c.aclass(&p.From) + 1 903 p.From.Class = int8(a1) 904 } 905 906 a1-- 907 a3 := C_NONE + 1 908 if p.GetFrom3() != nil { 909 a3 = int(p.GetFrom3().Class) 910 if a3 == 0 { 911 a3 = c.aclass(p.GetFrom3()) + 1 912 p.GetFrom3().Class = int8(a3) 913 } 914 } 915 916 a3-- 917 a4 := int(p.To.Class) 918 if a4 == 0 { 919 a4 = c.aclass(&p.To) + 1 920 p.To.Class = int8(a4) 921 } 922 923 a4-- 924 a2 := C_NONE 925 if p.Reg != 0 { 926 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 927 a2 = C_REG 928 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 929 a2 = C_VREG 930 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 931 a2 = C_VSREG 932 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 933 a2 = C_FREG 934 } 935 } 936 937 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 938 ops := oprange[p.As&obj.AMask] 939 c1 := &xcmp[a1] 940 c3 := &xcmp[a3] 941 c4 := &xcmp[a4] 942 for i := range ops { 943 op := &ops[i] 944 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 945 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 946 return op 947 } 948 } 949 950 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 951 prasm(p) 952 if ops == nil { 953 ops = optab 954 } 955 return &ops[0] 956 } 957 958 func cmp(a int, b int) bool { 959 if a == b { 960 return true 961 } 962 switch a { 963 case C_LCON: 964 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 965 return true 966 } 967 968 case C_ADDCON: 969 if b == C_ZCON || b == C_SCON { 970 return true 971 } 972 973 case C_ANDCON: 974 if b == C_ZCON || b == C_SCON { 975 return true 976 } 977 978 case C_SPR: 979 if b == C_LR || b == C_XER || b == C_CTR { 980 return true 981 } 982 983 case C_UCON: 984 if b == C_ZCON { 985 return true 986 } 987 988 case C_SCON: 989 if b == C_ZCON { 990 return true 991 } 992 993 case C_LACON: 994 if b == C_SACON { 995 return true 996 } 997 998 case C_LBRA: 999 if b == C_SBRA { 1000 return true 1001 } 1002 1003 case C_LEXT: 1004 if b == C_SEXT { 1005 return true 1006 } 1007 1008 case C_LAUTO: 1009 if b == C_SAUTO { 1010 return true 1011 } 1012 1013 case C_REG: 1014 if b == C_ZCON { 1015 return r0iszero != 0 /*TypeKind(100016)*/ 1016 } 1017 1018 case C_LOREG: 1019 if b == C_ZOREG || b == C_SOREG { 1020 return true 1021 } 1022 1023 case C_SOREG: 1024 if b == C_ZOREG { 1025 return true 1026 } 1027 1028 case C_ANY: 1029 return true 1030 } 1031 1032 return false 1033 } 1034 1035 type ocmp []Optab 1036 1037 func (x ocmp) Len() int { 1038 return len(x) 1039 } 1040 1041 func (x ocmp) Swap(i, j int) { 1042 x[i], x[j] = x[j], x[i] 1043 } 1044 1045 func (x ocmp) Less(i, j int) bool { 1046 p1 := &x[i] 1047 p2 := &x[j] 1048 n := int(p1.as) - int(p2.as) 1049 if n != 0 { 1050 return n < 0 1051 } 1052 n = int(p1.a1) - int(p2.a1) 1053 if n != 0 { 1054 return n < 0 1055 } 1056 n = int(p1.a2) - int(p2.a2) 1057 if n != 0 { 1058 return n < 0 1059 } 1060 n = int(p1.a3) - int(p2.a3) 1061 if n != 0 { 1062 return n < 0 1063 } 1064 n = int(p1.a4) - int(p2.a4) 1065 if n != 0 { 1066 return n < 0 1067 } 1068 return false 1069 } 1070 func opset(a, b0 obj.As) { 1071 oprange[a&obj.AMask] = oprange[b0] 1072 } 1073 1074 func buildop(ctxt *obj.Link) { 1075 if oprange[AANDN&obj.AMask] != nil { 1076 // Already initialized; stop now. 1077 // This happens in the cmd/asm tests, 1078 // each of which re-initializes the arch. 1079 return 1080 } 1081 1082 var n int 1083 1084 for i := 0; i < C_NCLASS; i++ { 1085 for n = 0; n < C_NCLASS; n++ { 1086 if cmp(n, i) { 1087 xcmp[i][n] = true 1088 } 1089 } 1090 } 1091 for n = 0; optab[n].as != obj.AXXX; n++ { 1092 } 1093 sort.Sort(ocmp(optab[:n])) 1094 for i := 0; i < n; i++ { 1095 r := optab[i].as 1096 r0 := r & obj.AMask 1097 start := i 1098 for optab[i].as == r { 1099 i++ 1100 } 1101 oprange[r0] = optab[start:i] 1102 i-- 1103 1104 switch r { 1105 default: 1106 ctxt.Diag("unknown op in build: %v", r) 1107 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1108 1109 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1110 opset(ADCBI, r0) 1111 1112 opset(ADCBST, r0) 1113 opset(ADCBT, r0) 1114 opset(ADCBTST, r0) 1115 opset(ADCBZ, r0) 1116 opset(AICBI, r0) 1117 1118 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1119 opset(ASTWCCC, r0) 1120 opset(ASTBCCC, r0) 1121 1122 opset(ASTDCCC, r0) 1123 1124 case AREM: /* macro */ 1125 opset(AREMCC, r0) 1126 1127 opset(AREMV, r0) 1128 opset(AREMVCC, r0) 1129 1130 case AREMU: 1131 opset(AREMU, r0) 1132 opset(AREMUCC, r0) 1133 opset(AREMUV, r0) 1134 opset(AREMUVCC, r0) 1135 1136 case AREMD: 1137 opset(AREMDCC, r0) 1138 opset(AREMDV, r0) 1139 opset(AREMDVCC, r0) 1140 1141 case AREMDU: 1142 opset(AREMDU, r0) 1143 opset(AREMDUCC, r0) 1144 opset(AREMDUV, r0) 1145 opset(AREMDUVCC, r0) 1146 1147 case ADIVW: /* op Rb[,Ra],Rd */ 1148 opset(AMULHW, r0) 1149 1150 opset(AMULHWCC, r0) 1151 opset(AMULHWU, r0) 1152 opset(AMULHWUCC, r0) 1153 opset(AMULLWCC, r0) 1154 opset(AMULLWVCC, r0) 1155 opset(AMULLWV, r0) 1156 opset(ADIVWCC, r0) 1157 opset(ADIVWV, r0) 1158 opset(ADIVWVCC, r0) 1159 opset(ADIVWU, r0) 1160 opset(ADIVWUCC, r0) 1161 opset(ADIVWUV, r0) 1162 opset(ADIVWUVCC, r0) 1163 opset(AADDCC, r0) 1164 opset(AADDCV, r0) 1165 opset(AADDCVCC, r0) 1166 opset(AADDV, r0) 1167 opset(AADDVCC, r0) 1168 opset(AADDE, r0) 1169 opset(AADDECC, r0) 1170 opset(AADDEV, r0) 1171 opset(AADDEVCC, r0) 1172 opset(ACRAND, r0) 1173 opset(ACRANDN, r0) 1174 opset(ACREQV, r0) 1175 opset(ACRNAND, r0) 1176 opset(ACRNOR, r0) 1177 opset(ACROR, r0) 1178 opset(ACRORN, r0) 1179 opset(ACRXOR, r0) 1180 opset(AMULHD, r0) 1181 opset(AMULHDCC, r0) 1182 opset(AMULHDU, r0) 1183 opset(AMULHDUCC, r0) 1184 opset(AMULLD, r0) 1185 opset(AMULLDCC, r0) 1186 opset(AMULLDVCC, r0) 1187 opset(AMULLDV, r0) 1188 opset(ADIVD, r0) 1189 opset(ADIVDCC, r0) 1190 opset(ADIVDE, r0) 1191 opset(ADIVDEU, r0) 1192 opset(ADIVDECC, r0) 1193 opset(ADIVDEUCC, r0) 1194 opset(ADIVDVCC, r0) 1195 opset(ADIVDV, r0) 1196 opset(ADIVDU, r0) 1197 opset(ADIVDUCC, r0) 1198 opset(ADIVDUVCC, r0) 1199 opset(ADIVDUCC, r0) 1200 1201 case APOPCNTD: 1202 opset(APOPCNTW, r0) 1203 opset(APOPCNTB, r0) 1204 1205 case ACOPY: /* copy, paste. */ 1206 opset(APASTECC, r0) 1207 1208 case AMADDHD: /* maddhd, maddhdu, maddld */ 1209 opset(AMADDHDU, r0) 1210 opset(AMADDLD, r0) 1211 1212 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1213 opset(AMOVH, r0) 1214 opset(AMOVHZ, r0) 1215 1216 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1217 opset(AMOVHU, r0) 1218 1219 opset(AMOVHZU, r0) 1220 opset(AMOVWU, r0) 1221 opset(AMOVWZU, r0) 1222 opset(AMOVDU, r0) 1223 opset(AMOVMW, r0) 1224 1225 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1226 opset(ALVEBX, r0) 1227 opset(ALVEHX, r0) 1228 opset(ALVEWX, r0) 1229 opset(ALVX, r0) 1230 opset(ALVXL, r0) 1231 opset(ALVSL, r0) 1232 opset(ALVSR, r0) 1233 1234 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1235 opset(ASTVEBX, r0) 1236 opset(ASTVEHX, r0) 1237 opset(ASTVEWX, r0) 1238 opset(ASTVX, r0) 1239 opset(ASTVXL, r0) 1240 1241 case AVAND: /* vand, vandc, vnand */ 1242 opset(AVAND, r0) 1243 opset(AVANDC, r0) 1244 opset(AVNAND, r0) 1245 1246 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1247 opset(AVOR, r0) 1248 opset(AVORC, r0) 1249 opset(AVXOR, r0) 1250 opset(AVNOR, r0) 1251 opset(AVEQV, r0) 1252 1253 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1254 opset(AVADDUBM, r0) 1255 opset(AVADDUHM, r0) 1256 opset(AVADDUWM, r0) 1257 opset(AVADDUDM, r0) 1258 opset(AVADDUQM, r0) 1259 1260 case AVADDCU: /* vaddcuq, vaddcuw */ 1261 opset(AVADDCUQ, r0) 1262 opset(AVADDCUW, r0) 1263 1264 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1265 opset(AVADDUBS, r0) 1266 opset(AVADDUHS, r0) 1267 opset(AVADDUWS, r0) 1268 1269 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1270 opset(AVADDSBS, r0) 1271 opset(AVADDSHS, r0) 1272 opset(AVADDSWS, r0) 1273 1274 case AVADDE: /* vaddeuqm, vaddecuq */ 1275 opset(AVADDEUQM, r0) 1276 opset(AVADDECUQ, r0) 1277 1278 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1279 opset(AVSUBUBM, r0) 1280 opset(AVSUBUHM, r0) 1281 opset(AVSUBUWM, r0) 1282 opset(AVSUBUDM, r0) 1283 opset(AVSUBUQM, r0) 1284 1285 case AVSUBCU: /* vsubcuq, vsubcuw */ 1286 opset(AVSUBCUQ, r0) 1287 opset(AVSUBCUW, r0) 1288 1289 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1290 opset(AVSUBUBS, r0) 1291 opset(AVSUBUHS, r0) 1292 opset(AVSUBUWS, r0) 1293 1294 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1295 opset(AVSUBSBS, r0) 1296 opset(AVSUBSHS, r0) 1297 opset(AVSUBSWS, r0) 1298 1299 case AVSUBE: /* vsubeuqm, vsubecuq */ 1300 opset(AVSUBEUQM, r0) 1301 opset(AVSUBECUQ, r0) 1302 1303 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1304 opset(AVPMSUMB, r0) 1305 opset(AVPMSUMH, r0) 1306 opset(AVPMSUMW, r0) 1307 opset(AVPMSUMD, r0) 1308 1309 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1310 opset(AVRLB, r0) 1311 opset(AVRLH, r0) 1312 opset(AVRLW, r0) 1313 opset(AVRLD, r0) 1314 1315 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1316 opset(AVSLB, r0) 1317 opset(AVSLH, r0) 1318 opset(AVSLW, r0) 1319 opset(AVSL, r0) 1320 opset(AVSLO, r0) 1321 opset(AVSRB, r0) 1322 opset(AVSRH, r0) 1323 opset(AVSRW, r0) 1324 opset(AVSR, r0) 1325 opset(AVSRO, r0) 1326 opset(AVSLD, r0) 1327 opset(AVSRD, r0) 1328 1329 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1330 opset(AVSRAB, r0) 1331 opset(AVSRAH, r0) 1332 opset(AVSRAW, r0) 1333 opset(AVSRAD, r0) 1334 1335 case AVSOI: /* vsldoi */ 1336 opset(AVSLDOI, r0) 1337 1338 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1339 opset(AVCLZB, r0) 1340 opset(AVCLZH, r0) 1341 opset(AVCLZW, r0) 1342 opset(AVCLZD, r0) 1343 1344 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1345 opset(AVPOPCNTB, r0) 1346 opset(AVPOPCNTH, r0) 1347 opset(AVPOPCNTW, r0) 1348 opset(AVPOPCNTD, r0) 1349 1350 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1351 opset(AVCMPEQUB, r0) 1352 opset(AVCMPEQUBCC, r0) 1353 opset(AVCMPEQUH, r0) 1354 opset(AVCMPEQUHCC, r0) 1355 opset(AVCMPEQUW, r0) 1356 opset(AVCMPEQUWCC, r0) 1357 opset(AVCMPEQUD, r0) 1358 opset(AVCMPEQUDCC, r0) 1359 1360 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1361 opset(AVCMPGTUB, r0) 1362 opset(AVCMPGTUBCC, r0) 1363 opset(AVCMPGTUH, r0) 1364 opset(AVCMPGTUHCC, r0) 1365 opset(AVCMPGTUW, r0) 1366 opset(AVCMPGTUWCC, r0) 1367 opset(AVCMPGTUD, r0) 1368 opset(AVCMPGTUDCC, r0) 1369 opset(AVCMPGTSB, r0) 1370 opset(AVCMPGTSBCC, r0) 1371 opset(AVCMPGTSH, r0) 1372 opset(AVCMPGTSHCC, r0) 1373 opset(AVCMPGTSW, r0) 1374 opset(AVCMPGTSWCC, r0) 1375 opset(AVCMPGTSD, r0) 1376 opset(AVCMPGTSDCC, r0) 1377 1378 case AVCMPNEZB: /* vcmpnezb[.] */ 1379 opset(AVCMPNEZBCC, r0) 1380 1381 case AVPERM: /* vperm */ 1382 opset(AVPERM, r0) 1383 1384 case AVBPERMQ: /* vbpermq, vbpermd */ 1385 opset(AVBPERMD, r0) 1386 1387 case AVSEL: /* vsel */ 1388 opset(AVSEL, r0) 1389 1390 case AVSPLT: /* vspltb, vsplth, vspltw */ 1391 opset(AVSPLTB, r0) 1392 opset(AVSPLTH, r0) 1393 opset(AVSPLTW, r0) 1394 1395 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1396 opset(AVSPLTISB, r0) 1397 opset(AVSPLTISH, r0) 1398 opset(AVSPLTISW, r0) 1399 1400 case AVCIPH: /* vcipher, vcipherlast */ 1401 opset(AVCIPHER, r0) 1402 opset(AVCIPHERLAST, r0) 1403 1404 case AVNCIPH: /* vncipher, vncipherlast */ 1405 opset(AVNCIPHER, r0) 1406 opset(AVNCIPHERLAST, r0) 1407 1408 case AVSBOX: /* vsbox */ 1409 opset(AVSBOX, r0) 1410 1411 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1412 opset(AVSHASIGMAW, r0) 1413 opset(AVSHASIGMAD, r0) 1414 1415 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1416 opset(ALXVD2X, r0) 1417 opset(ALXVDSX, r0) 1418 opset(ALXVW4X, r0) 1419 1420 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1421 opset(ASTXVD2X, r0) 1422 opset(ASTXVW4X, r0) 1423 1424 case ALXS: /* lxsdx */ 1425 opset(ALXSDX, r0) 1426 1427 case ASTXS: /* stxsdx */ 1428 opset(ASTXSDX, r0) 1429 1430 case ALXSI: /* lxsiwax, lxsiwzx */ 1431 opset(ALXSIWAX, r0) 1432 opset(ALXSIWZX, r0) 1433 1434 case ASTXSI: /* stxsiwx */ 1435 opset(ASTXSIWX, r0) 1436 1437 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */ 1438 opset(AMFVSRD, r0) 1439 opset(AMFFPRD, r0) 1440 opset(AMFVRD, r0) 1441 opset(AMFVSRWZ, r0) 1442 opset(AMFVSRLD, r0) 1443 1444 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */ 1445 opset(AMTVSRD, r0) 1446 opset(AMTFPRD, r0) 1447 opset(AMTVRD, r0) 1448 opset(AMTVSRWA, r0) 1449 opset(AMTVSRWZ, r0) 1450 opset(AMTVSRDD, r0) 1451 opset(AMTVSRWS, r0) 1452 1453 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1454 opset(AXXLANDQ, r0) 1455 opset(AXXLANDC, r0) 1456 opset(AXXLEQV, r0) 1457 opset(AXXLNAND, r0) 1458 1459 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1460 opset(AXXLORC, r0) 1461 opset(AXXLNOR, r0) 1462 opset(AXXLORQ, r0) 1463 opset(AXXLXOR, r0) 1464 1465 case AXXSEL: /* xxsel */ 1466 opset(AXXSEL, r0) 1467 1468 case AXXMRG: /* xxmrghw, xxmrglw */ 1469 opset(AXXMRGHW, r0) 1470 opset(AXXMRGLW, r0) 1471 1472 case AXXSPLT: /* xxspltw */ 1473 opset(AXXSPLTW, r0) 1474 1475 case AXXPERM: /* xxpermdi */ 1476 opset(AXXPERMDI, r0) 1477 1478 case AXXSI: /* xxsldwi */ 1479 opset(AXXSLDWI, r0) 1480 1481 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1482 opset(AXSCVDPSP, r0) 1483 opset(AXSCVSPDP, r0) 1484 opset(AXSCVDPSPN, r0) 1485 opset(AXSCVSPDPN, r0) 1486 1487 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1488 opset(AXVCVDPSP, r0) 1489 opset(AXVCVSPDP, r0) 1490 1491 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1492 opset(AXSCVDPSXDS, r0) 1493 opset(AXSCVDPSXWS, r0) 1494 opset(AXSCVDPUXDS, r0) 1495 opset(AXSCVDPUXWS, r0) 1496 1497 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1498 opset(AXSCVSXDDP, r0) 1499 opset(AXSCVUXDDP, r0) 1500 opset(AXSCVSXDSP, r0) 1501 opset(AXSCVUXDSP, r0) 1502 1503 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1504 opset(AXVCVDPSXDS, r0) 1505 opset(AXVCVDPSXWS, r0) 1506 opset(AXVCVDPUXDS, r0) 1507 opset(AXVCVDPUXWS, r0) 1508 opset(AXVCVSPSXDS, r0) 1509 opset(AXVCVSPSXWS, r0) 1510 opset(AXVCVSPUXDS, r0) 1511 opset(AXVCVSPUXWS, r0) 1512 1513 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1514 opset(AXVCVSXDDP, r0) 1515 opset(AXVCVSXWDP, r0) 1516 opset(AXVCVUXDDP, r0) 1517 opset(AXVCVUXWDP, r0) 1518 opset(AXVCVSXDSP, r0) 1519 opset(AXVCVSXWSP, r0) 1520 opset(AXVCVUXDSP, r0) 1521 opset(AXVCVUXWSP, r0) 1522 1523 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1524 opset(AANDN, r0) 1525 1526 opset(AANDNCC, r0) 1527 opset(AEQV, r0) 1528 opset(AEQVCC, r0) 1529 opset(ANAND, r0) 1530 opset(ANANDCC, r0) 1531 opset(ANOR, r0) 1532 opset(ANORCC, r0) 1533 opset(AORCC, r0) 1534 opset(AORN, r0) 1535 opset(AORNCC, r0) 1536 opset(AXORCC, r0) 1537 1538 case AADDME: /* op Ra, Rd */ 1539 opset(AADDMECC, r0) 1540 1541 opset(AADDMEV, r0) 1542 opset(AADDMEVCC, r0) 1543 opset(AADDZE, r0) 1544 opset(AADDZECC, r0) 1545 opset(AADDZEV, r0) 1546 opset(AADDZEVCC, r0) 1547 opset(ASUBME, r0) 1548 opset(ASUBMECC, r0) 1549 opset(ASUBMEV, r0) 1550 opset(ASUBMEVCC, r0) 1551 opset(ASUBZE, r0) 1552 opset(ASUBZECC, r0) 1553 opset(ASUBZEV, r0) 1554 opset(ASUBZEVCC, r0) 1555 1556 case AADDC: 1557 opset(AADDCCC, r0) 1558 1559 case ABEQ: 1560 opset(ABGE, r0) 1561 opset(ABGT, r0) 1562 opset(ABLE, r0) 1563 opset(ABLT, r0) 1564 opset(ABNE, r0) 1565 opset(ABVC, r0) 1566 opset(ABVS, r0) 1567 1568 case ABR: 1569 opset(ABL, r0) 1570 1571 case ABC: 1572 opset(ABCL, r0) 1573 1574 case AEXTSB: /* op Rs, Ra */ 1575 opset(AEXTSBCC, r0) 1576 1577 opset(AEXTSH, r0) 1578 opset(AEXTSHCC, r0) 1579 opset(ACNTLZW, r0) 1580 opset(ACNTLZWCC, r0) 1581 opset(ACNTLZD, r0) 1582 opset(AEXTSW, r0) 1583 opset(AEXTSWCC, r0) 1584 opset(ACNTLZDCC, r0) 1585 1586 case AFABS: /* fop [s,]d */ 1587 opset(AFABSCC, r0) 1588 1589 opset(AFNABS, r0) 1590 opset(AFNABSCC, r0) 1591 opset(AFNEG, r0) 1592 opset(AFNEGCC, r0) 1593 opset(AFRSP, r0) 1594 opset(AFRSPCC, r0) 1595 opset(AFCTIW, r0) 1596 opset(AFCTIWCC, r0) 1597 opset(AFCTIWZ, r0) 1598 opset(AFCTIWZCC, r0) 1599 opset(AFCTID, r0) 1600 opset(AFCTIDCC, r0) 1601 opset(AFCTIDZ, r0) 1602 opset(AFCTIDZCC, r0) 1603 opset(AFCFID, r0) 1604 opset(AFCFIDCC, r0) 1605 opset(AFCFIDU, r0) 1606 opset(AFCFIDUCC, r0) 1607 opset(AFCFIDS, r0) 1608 opset(AFCFIDSCC, r0) 1609 opset(AFRES, r0) 1610 opset(AFRESCC, r0) 1611 opset(AFRIM, r0) 1612 opset(AFRIMCC, r0) 1613 opset(AFRIP, r0) 1614 opset(AFRIPCC, r0) 1615 opset(AFRIZ, r0) 1616 opset(AFRIZCC, r0) 1617 opset(AFRSQRTE, r0) 1618 opset(AFRSQRTECC, r0) 1619 opset(AFSQRT, r0) 1620 opset(AFSQRTCC, r0) 1621 opset(AFSQRTS, r0) 1622 opset(AFSQRTSCC, r0) 1623 1624 case AFADD: 1625 opset(AFADDS, r0) 1626 opset(AFADDCC, r0) 1627 opset(AFADDSCC, r0) 1628 opset(AFCPSGN, r0) 1629 opset(AFCPSGNCC, r0) 1630 opset(AFDIV, r0) 1631 opset(AFDIVS, r0) 1632 opset(AFDIVCC, r0) 1633 opset(AFDIVSCC, r0) 1634 opset(AFSUB, r0) 1635 opset(AFSUBS, r0) 1636 opset(AFSUBCC, r0) 1637 opset(AFSUBSCC, r0) 1638 1639 case AFMADD: 1640 opset(AFMADDCC, r0) 1641 opset(AFMADDS, r0) 1642 opset(AFMADDSCC, r0) 1643 opset(AFMSUB, r0) 1644 opset(AFMSUBCC, r0) 1645 opset(AFMSUBS, r0) 1646 opset(AFMSUBSCC, r0) 1647 opset(AFNMADD, r0) 1648 opset(AFNMADDCC, r0) 1649 opset(AFNMADDS, r0) 1650 opset(AFNMADDSCC, r0) 1651 opset(AFNMSUB, r0) 1652 opset(AFNMSUBCC, r0) 1653 opset(AFNMSUBS, r0) 1654 opset(AFNMSUBSCC, r0) 1655 opset(AFSEL, r0) 1656 opset(AFSELCC, r0) 1657 1658 case AFMUL: 1659 opset(AFMULS, r0) 1660 opset(AFMULCC, r0) 1661 opset(AFMULSCC, r0) 1662 1663 case AFCMPO: 1664 opset(AFCMPU, r0) 1665 1666 case AISEL: 1667 opset(AISEL, r0) 1668 1669 case AMTFSB0: 1670 opset(AMTFSB0CC, r0) 1671 opset(AMTFSB1, r0) 1672 opset(AMTFSB1CC, r0) 1673 1674 case ANEG: /* op [Ra,] Rd */ 1675 opset(ANEGCC, r0) 1676 1677 opset(ANEGV, r0) 1678 opset(ANEGVCC, r0) 1679 1680 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1681 opset(AXOR, r0) 1682 1683 case ASLW: 1684 opset(ASLWCC, r0) 1685 opset(ASRW, r0) 1686 opset(ASRWCC, r0) 1687 opset(AROTLW, r0) 1688 1689 case ASLD: 1690 opset(ASLDCC, r0) 1691 opset(ASRD, r0) 1692 opset(ASRDCC, r0) 1693 opset(AROTL, r0) 1694 1695 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1696 opset(ASRAWCC, r0) 1697 1698 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1699 opset(ASRADCC, r0) 1700 1701 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1702 opset(ASUB, r0) 1703 1704 opset(ASUBCC, r0) 1705 opset(ASUBV, r0) 1706 opset(ASUBVCC, r0) 1707 opset(ASUBCCC, r0) 1708 opset(ASUBCV, r0) 1709 opset(ASUBCVCC, r0) 1710 opset(ASUBE, r0) 1711 opset(ASUBECC, r0) 1712 opset(ASUBEV, r0) 1713 opset(ASUBEVCC, r0) 1714 1715 case ASYNC: 1716 opset(AISYNC, r0) 1717 opset(ALWSYNC, r0) 1718 opset(APTESYNC, r0) 1719 opset(ATLBSYNC, r0) 1720 1721 case ARLWMI: 1722 opset(ARLWMICC, r0) 1723 opset(ARLWNM, r0) 1724 opset(ARLWNMCC, r0) 1725 1726 case ARLDMI: 1727 opset(ARLDMICC, r0) 1728 opset(ARLDIMI, r0) 1729 opset(ARLDIMICC, r0) 1730 1731 case ARLDC: 1732 opset(ARLDCCC, r0) 1733 1734 case ARLDCL: 1735 opset(ARLDCR, r0) 1736 opset(ARLDCLCC, r0) 1737 opset(ARLDCRCC, r0) 1738 1739 case ARLDICL: 1740 opset(ARLDICLCC, r0) 1741 opset(ARLDICR, r0) 1742 opset(ARLDICRCC, r0) 1743 1744 case AFMOVD: 1745 opset(AFMOVDCC, r0) 1746 opset(AFMOVDU, r0) 1747 opset(AFMOVS, r0) 1748 opset(AFMOVSU, r0) 1749 1750 case AECIWX: 1751 opset(ALBAR, r0) 1752 opset(ALWAR, r0) 1753 opset(ALDAR, r0) 1754 1755 case ASYSCALL: /* just the op; flow of control */ 1756 opset(ARFI, r0) 1757 1758 opset(ARFCI, r0) 1759 opset(ARFID, r0) 1760 opset(AHRFID, r0) 1761 1762 case AMOVHBR: 1763 opset(AMOVWBR, r0) 1764 opset(AMOVDBR, r0) 1765 1766 case ASLBMFEE: 1767 opset(ASLBMFEV, r0) 1768 1769 case ATW: 1770 opset(ATD, r0) 1771 1772 case ATLBIE: 1773 opset(ASLBIE, r0) 1774 opset(ATLBIEL, r0) 1775 1776 case AEIEIO: 1777 opset(ASLBIA, r0) 1778 1779 case ACMP: 1780 opset(ACMPW, r0) 1781 1782 case ACMPU: 1783 opset(ACMPWU, r0) 1784 1785 case ACMPB: 1786 opset(ACMPB, r0) 1787 1788 case AFTDIV: 1789 opset(AFTDIV, r0) 1790 1791 case AFTSQRT: 1792 opset(AFTSQRT, r0) 1793 1794 case AADD, 1795 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1796 AFMOVSX, 1797 AFMOVSZ, 1798 ALSW, 1799 AMOVW, 1800 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1801 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1802 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1803 AMOVB, /* macro: move byte with sign extension */ 1804 AMOVBU, /* macro: move byte with sign extension & update */ 1805 AMOVFL, 1806 AMULLW, 1807 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1808 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1809 ASTSW, 1810 ASLBMTE, 1811 AWORD, 1812 ADWORD, 1813 ADARN, 1814 ALDMX, 1815 AVMSUMUDM, 1816 AADDEX, 1817 ACMPEQB, 1818 obj.ANOP, 1819 obj.ATEXT, 1820 obj.AUNDEF, 1821 obj.AFUNCDATA, 1822 obj.APCDATA, 1823 obj.ADUFFZERO, 1824 obj.ADUFFCOPY: 1825 break 1826 } 1827 } 1828 } 1829 1830 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1831 return o<<26 | xo<<1 | oe<<11 1832 } 1833 1834 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1835 return o<<26 | xo<<2 | oe<<11 1836 } 1837 1838 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1839 return o<<26 | xo<<3 | oe<<11 1840 } 1841 1842 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1843 return o<<26 | xo<<4 | oe<<11 1844 } 1845 1846 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1847 return o<<26 | xo | oe<<11 | rc&1 1848 } 1849 1850 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1851 return o<<26 | xo | oe<<11 | (rc&1)<<10 1852 } 1853 1854 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1855 return o<<26 | xo<<1 | oe<<10 | rc&1 1856 } 1857 1858 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1859 return OPVCC(o, xo, 0, rc) 1860 } 1861 1862 func OP(o uint32, xo uint32) uint32 { 1863 return OPVCC(o, xo, 0, 0) 1864 } 1865 1866 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1867 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1868 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1869 } 1870 1871 /* VX-form 2-register operands, r/none/r */ 1872 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1873 return op | (d&31)<<21 | (a&31)<<11 1874 } 1875 1876 /* VA-form 4-register operands */ 1877 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1878 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1879 } 1880 1881 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1882 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1883 } 1884 1885 /* VX-form 2-register + UIM operands */ 1886 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1887 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1888 } 1889 1890 /* VX-form 2-register + ST + SIX operands */ 1891 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1892 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1893 } 1894 1895 /* VA-form 3-register + SHB operands */ 1896 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1897 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1898 } 1899 1900 /* VX-form 1-register + SIM operands */ 1901 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1902 return op | (d&31)<<21 | (simm&31)<<16 1903 } 1904 1905 /* XX1-form 3-register operands, 1 VSR operand */ 1906 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1907 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1908 /* between 0-63, so we can properly set the rightmost bits. */ 1909 r := d - REG_VS0 1910 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1911 } 1912 1913 /* XX2-form 3-register operands, 2 VSR operands */ 1914 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1915 xt := d - REG_VS0 1916 xb := b - REG_VS0 1917 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1918 } 1919 1920 /* XX3-form 3 VSR operands */ 1921 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1922 xt := d - REG_VS0 1923 xa := a - REG_VS0 1924 xb := b - REG_VS0 1925 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1926 } 1927 1928 /* XX3-form 3 VSR operands + immediate */ 1929 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1930 xt := d - REG_VS0 1931 xa := a - REG_VS0 1932 xb := b - REG_VS0 1933 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1934 } 1935 1936 /* XX4-form, 4 VSR operands */ 1937 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1938 xt := d - REG_VS0 1939 xa := a - REG_VS0 1940 xb := b - REG_VS0 1941 xc := c - REG_VS0 1942 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1943 } 1944 1945 /* Z23-form, 3-register operands + CY field */ 1946 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1947 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7 1948 } 1949 1950 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1951 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1952 } 1953 1954 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1955 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1956 } 1957 1958 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1959 return op | li&0x03FFFFFC | aa<<1 1960 } 1961 1962 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1963 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1964 } 1965 1966 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1967 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1968 } 1969 1970 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1971 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1972 } 1973 1974 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1975 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1976 } 1977 1978 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1979 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1980 } 1981 1982 const ( 1983 /* each rhs is OPVCC(_, _, _, _) */ 1984 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1985 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1986 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1987 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1988 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1989 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1990 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1991 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1992 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1993 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1994 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1995 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1996 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1997 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1998 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1999 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 2000 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 2001 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 2002 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 2003 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 2004 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 2005 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 2006 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 2007 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 2008 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 2009 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 2010 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 2011 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 2012 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 2013 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 2014 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 2015 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 2016 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 2017 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 2018 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 2019 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 2020 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 2021 ) 2022 2023 func oclass(a *obj.Addr) int { 2024 return int(a.Class) - 1 2025 } 2026 2027 const ( 2028 D_FORM = iota 2029 DS_FORM 2030 ) 2031 2032 // This function determines when a non-indexed load or store is D or 2033 // DS form for use in finding the size of the offset field in the instruction. 2034 // The size is needed when setting the offset value in the instruction 2035 // and when generating relocation for that field. 2036 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 2037 // loads and stores with an offset field are D form. This function should 2038 // only be called with the same opcodes as are handled by opstore and opload. 2039 func (c *ctxt9) opform(insn uint32) int { 2040 switch insn { 2041 default: 2042 c.ctxt.Diag("bad insn in loadform: %x", insn) 2043 case OPVCC(58, 0, 0, 0), // ld 2044 OPVCC(58, 0, 0, 1), // ldu 2045 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2046 OPVCC(62, 0, 0, 0), // std 2047 OPVCC(62, 0, 0, 1): //stdu 2048 return DS_FORM 2049 case OP_ADDI, // add 2050 OPVCC(32, 0, 0, 0), // lwz 2051 OPVCC(33, 0, 0, 0), // lwzu 2052 OPVCC(34, 0, 0, 0), // lbz 2053 OPVCC(35, 0, 0, 0), // lbzu 2054 OPVCC(40, 0, 0, 0), // lhz 2055 OPVCC(41, 0, 0, 0), // lhzu 2056 OPVCC(42, 0, 0, 0), // lha 2057 OPVCC(43, 0, 0, 0), // lhau 2058 OPVCC(46, 0, 0, 0), // lmw 2059 OPVCC(48, 0, 0, 0), // lfs 2060 OPVCC(49, 0, 0, 0), // lfsu 2061 OPVCC(50, 0, 0, 0), // lfd 2062 OPVCC(51, 0, 0, 0), // lfdu 2063 OPVCC(36, 0, 0, 0), // stw 2064 OPVCC(37, 0, 0, 0), // stwu 2065 OPVCC(38, 0, 0, 0), // stb 2066 OPVCC(39, 0, 0, 0), // stbu 2067 OPVCC(44, 0, 0, 0), // sth 2068 OPVCC(45, 0, 0, 0), // sthu 2069 OPVCC(47, 0, 0, 0), // stmw 2070 OPVCC(52, 0, 0, 0), // stfs 2071 OPVCC(53, 0, 0, 0), // stfsu 2072 OPVCC(54, 0, 0, 0), // stfd 2073 OPVCC(55, 0, 0, 0): // stfdu 2074 return D_FORM 2075 } 2076 return 0 2077 } 2078 2079 // Encode instructions and create relocation for accessing s+d according to the 2080 // instruction op with source or destination (as appropriate) register reg. 2081 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2082 var base uint32 2083 form := c.opform(op) 2084 if c.ctxt.Flag_shared { 2085 base = REG_R2 2086 } else { 2087 base = REG_R0 2088 } 2089 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2090 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2091 rel := obj.Addrel(c.cursym) 2092 rel.Off = int32(c.pc) 2093 rel.Siz = 8 2094 rel.Sym = s 2095 rel.Add = d 2096 if c.ctxt.Flag_shared { 2097 switch form { 2098 case D_FORM: 2099 rel.Type = objabi.R_ADDRPOWER_TOCREL 2100 case DS_FORM: 2101 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2102 } 2103 2104 } else { 2105 switch form { 2106 case D_FORM: 2107 rel.Type = objabi.R_ADDRPOWER 2108 case DS_FORM: 2109 rel.Type = objabi.R_ADDRPOWER_DS 2110 } 2111 } 2112 return 2113 } 2114 2115 /* 2116 * 32-bit masks 2117 */ 2118 func getmask(m []byte, v uint32) bool { 2119 m[1] = 0 2120 m[0] = m[1] 2121 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2122 if getmask(m, ^v) { 2123 i := int(m[0]) 2124 m[0] = m[1] + 1 2125 m[1] = byte(i - 1) 2126 return true 2127 } 2128 2129 return false 2130 } 2131 2132 for i := 0; i < 32; i++ { 2133 if v&(1<<uint(31-i)) != 0 { 2134 m[0] = byte(i) 2135 for { 2136 m[1] = byte(i) 2137 i++ 2138 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2139 break 2140 } 2141 } 2142 2143 for ; i < 32; i++ { 2144 if v&(1<<uint(31-i)) != 0 { 2145 return false 2146 } 2147 } 2148 return true 2149 } 2150 } 2151 2152 return false 2153 } 2154 2155 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2156 if !getmask(m, v) { 2157 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2158 } 2159 } 2160 2161 /* 2162 * 64-bit masks (rldic etc) 2163 */ 2164 func getmask64(m []byte, v uint64) bool { 2165 m[1] = 0 2166 m[0] = m[1] 2167 for i := 0; i < 64; i++ { 2168 if v&(uint64(1)<<uint(63-i)) != 0 { 2169 m[0] = byte(i) 2170 for { 2171 m[1] = byte(i) 2172 i++ 2173 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2174 break 2175 } 2176 } 2177 2178 for ; i < 64; i++ { 2179 if v&(uint64(1)<<uint(63-i)) != 0 { 2180 return false 2181 } 2182 } 2183 return true 2184 } 2185 } 2186 2187 return false 2188 } 2189 2190 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2191 if !getmask64(m, v) { 2192 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2193 } 2194 } 2195 2196 func loadu32(r int, d int64) uint32 { 2197 v := int32(d >> 16) 2198 if isuint32(uint64(d)) { 2199 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2200 } 2201 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2202 } 2203 2204 func high16adjusted(d int32) uint16 { 2205 if d&0x8000 != 0 { 2206 return uint16((d >> 16) + 1) 2207 } 2208 return uint16(d >> 16) 2209 } 2210 2211 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2212 o1 := uint32(0) 2213 o2 := uint32(0) 2214 o3 := uint32(0) 2215 o4 := uint32(0) 2216 o5 := uint32(0) 2217 2218 //print("%v => case %d\n", p, o->type); 2219 switch o.type_ { 2220 default: 2221 c.ctxt.Diag("unknown type %d", o.type_) 2222 prasm(p) 2223 2224 case 0: /* pseudo ops */ 2225 break 2226 2227 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2228 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2229 v := c.regoff(&p.From) 2230 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2231 //nerrors--; 2232 c.ctxt.Diag("literal operation on R0\n%v", p) 2233 } 2234 2235 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2236 break 2237 } 2238 2239 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2240 2241 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2242 r := int(p.Reg) 2243 2244 if r == 0 { 2245 r = int(p.To.Reg) 2246 } 2247 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2248 2249 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2250 d := c.vregoff(&p.From) 2251 2252 v := int32(d) 2253 r := int(p.From.Reg) 2254 if r == 0 { 2255 r = int(o.param) 2256 } 2257 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2258 c.ctxt.Diag("literal operation on R0\n%v", p) 2259 } 2260 a := OP_ADDI 2261 if o.a1 == C_UCON { 2262 if d&0xffff != 0 { 2263 log.Fatalf("invalid handling of %v", p) 2264 } 2265 v >>= 16 2266 if r == REGZERO && isuint32(uint64(d)) { 2267 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2268 break 2269 } 2270 2271 a = OP_ADDIS 2272 } else { 2273 if int64(int16(d)) != d { 2274 log.Fatalf("invalid handling of %v", p) 2275 } 2276 } 2277 2278 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2279 2280 case 4: /* add/mul $scon,[r1],r2 */ 2281 v := c.regoff(&p.From) 2282 2283 r := int(p.Reg) 2284 if r == 0 { 2285 r = int(p.To.Reg) 2286 } 2287 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2288 c.ctxt.Diag("literal operation on R0\n%v", p) 2289 } 2290 if int32(int16(v)) != v { 2291 log.Fatalf("mishandled instruction %v", p) 2292 } 2293 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2294 2295 case 5: /* syscall */ 2296 o1 = c.oprrr(p.As) 2297 2298 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2299 r := int(p.Reg) 2300 2301 if r == 0 { 2302 r = int(p.To.Reg) 2303 } 2304 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2305 switch p.As { 2306 case AROTL: 2307 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2308 case AROTLW: 2309 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2310 default: 2311 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2312 } 2313 2314 case 7: /* mov r, soreg ==> stw o(r) */ 2315 r := int(p.To.Reg) 2316 2317 if r == 0 { 2318 r = int(o.param) 2319 } 2320 v := c.regoff(&p.To) 2321 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2322 if v != 0 { 2323 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2324 } 2325 if c.ctxt.Flag_shared && r == REG_R13 { 2326 rel := obj.Addrel(c.cursym) 2327 rel.Off = int32(c.pc) 2328 rel.Siz = 4 2329 // This (and the matching part in the load case 2330 // below) are the only places in the ppc64 toolchain 2331 // that knows the name of the tls variable. Possibly 2332 // we could add some assembly syntax so that the name 2333 // of the variable does not have to be assumed. 2334 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2335 rel.Type = objabi.R_POWER_TLS 2336 } 2337 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2338 } else { 2339 if int32(int16(v)) != v { 2340 log.Fatalf("mishandled instruction %v", p) 2341 } 2342 // Offsets in DS form stores must be a multiple of 4 2343 inst := c.opstore(p.As) 2344 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2345 log.Fatalf("invalid offset for DS form load/store %v", p) 2346 } 2347 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2348 } 2349 2350 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2351 r := int(p.From.Reg) 2352 2353 if r == 0 { 2354 r = int(o.param) 2355 } 2356 v := c.regoff(&p.From) 2357 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2358 if v != 0 { 2359 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2360 } 2361 if c.ctxt.Flag_shared && r == REG_R13 { 2362 rel := obj.Addrel(c.cursym) 2363 rel.Off = int32(c.pc) 2364 rel.Siz = 4 2365 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2366 rel.Type = objabi.R_POWER_TLS 2367 } 2368 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2369 } else { 2370 if int32(int16(v)) != v { 2371 log.Fatalf("mishandled instruction %v", p) 2372 } 2373 // Offsets in DS form loads must be a multiple of 4 2374 inst := c.opload(p.As) 2375 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2376 log.Fatalf("invalid offset for DS form load/store %v", p) 2377 } 2378 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2379 } 2380 2381 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2382 r := int(p.From.Reg) 2383 2384 if r == 0 { 2385 r = int(o.param) 2386 } 2387 v := c.regoff(&p.From) 2388 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2389 if v != 0 { 2390 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2391 } 2392 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2393 } else { 2394 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2395 } 2396 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2397 2398 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2399 r := int(p.Reg) 2400 2401 if r == 0 { 2402 r = int(p.To.Reg) 2403 } 2404 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2405 2406 case 11: /* br/bl lbra */ 2407 v := int32(0) 2408 2409 if p.Pcond != nil { 2410 v = int32(p.Pcond.Pc - p.Pc) 2411 if v&03 != 0 { 2412 c.ctxt.Diag("odd branch target address\n%v", p) 2413 v &^= 03 2414 } 2415 2416 if v < -(1<<25) || v >= 1<<24 { 2417 c.ctxt.Diag("branch too far\n%v", p) 2418 } 2419 } 2420 2421 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2422 if p.To.Sym != nil { 2423 rel := obj.Addrel(c.cursym) 2424 rel.Off = int32(c.pc) 2425 rel.Siz = 4 2426 rel.Sym = p.To.Sym 2427 v += int32(p.To.Offset) 2428 if v&03 != 0 { 2429 c.ctxt.Diag("odd branch target address\n%v", p) 2430 v &^= 03 2431 } 2432 2433 rel.Add = int64(v) 2434 rel.Type = objabi.R_CALLPOWER 2435 } 2436 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2437 2438 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2439 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2440 v := c.regoff(&p.From) 2441 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2442 c.ctxt.Diag("literal operation on R0\n%v", p) 2443 } 2444 2445 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2446 break 2447 } 2448 2449 if p.As == AMOVW { 2450 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2451 } else { 2452 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2453 } 2454 2455 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2456 if p.As == AMOVBZ { 2457 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2458 } else if p.As == AMOVH { 2459 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2460 } else if p.As == AMOVHZ { 2461 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2462 } else if p.As == AMOVWZ { 2463 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2464 } else { 2465 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2466 } 2467 2468 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2469 r := int(p.Reg) 2470 2471 if r == 0 { 2472 r = int(p.To.Reg) 2473 } 2474 d := c.vregoff(p.GetFrom3()) 2475 var a int 2476 switch p.As { 2477 2478 // These opcodes expect a mask operand that has to be converted into the 2479 // appropriate operand. The way these were defined, not all valid masks are possible. 2480 // Left here for compatibility in case they were used or generated. 2481 case ARLDCL, ARLDCLCC: 2482 var mask [2]uint8 2483 c.maskgen64(p, mask[:], uint64(d)) 2484 2485 a = int(mask[0]) /* MB */ 2486 if mask[1] != 63 { 2487 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2488 } 2489 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2490 o1 |= (uint32(a) & 31) << 6 2491 if a&0x20 != 0 { 2492 o1 |= 1 << 5 /* mb[5] is top bit */ 2493 } 2494 2495 case ARLDCR, ARLDCRCC: 2496 var mask [2]uint8 2497 c.maskgen64(p, mask[:], uint64(d)) 2498 2499 a = int(mask[1]) /* ME */ 2500 if mask[0] != 0 { 2501 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2502 } 2503 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2504 o1 |= (uint32(a) & 31) << 6 2505 if a&0x20 != 0 { 2506 o1 |= 1 << 5 /* mb[5] is top bit */ 2507 } 2508 2509 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2510 case ARLDICR, ARLDICRCC: 2511 me := int(d) 2512 sh := c.regoff(&p.From) 2513 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2514 2515 case ARLDICL, ARLDICLCC: 2516 mb := int(d) 2517 sh := c.regoff(&p.From) 2518 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2519 2520 default: 2521 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2522 a = 0 2523 } 2524 2525 case 17, /* bc bo,bi,lbra (same for now) */ 2526 16: /* bc bo,bi,sbra */ 2527 a := 0 2528 2529 r := int(p.Reg) 2530 2531 if p.From.Type == obj.TYPE_CONST { 2532 a = int(c.regoff(&p.From)) 2533 } else if p.From.Type == obj.TYPE_REG { 2534 if r != 0 { 2535 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2536 } 2537 // BI values for the CR 2538 switch p.From.Reg { 2539 case REG_CR0: 2540 r = BI_CR0 2541 case REG_CR1: 2542 r = BI_CR1 2543 case REG_CR2: 2544 r = BI_CR2 2545 case REG_CR3: 2546 r = BI_CR3 2547 case REG_CR4: 2548 r = BI_CR4 2549 case REG_CR5: 2550 r = BI_CR5 2551 case REG_CR6: 2552 r = BI_CR6 2553 case REG_CR7: 2554 r = BI_CR7 2555 default: 2556 c.ctxt.Diag("unrecognized register: expecting CR\n") 2557 } 2558 } 2559 v := int32(0) 2560 if p.Pcond != nil { 2561 v = int32(p.Pcond.Pc - p.Pc) 2562 } 2563 if v&03 != 0 { 2564 c.ctxt.Diag("odd branch target address\n%v", p) 2565 v &^= 03 2566 } 2567 2568 if v < -(1<<16) || v >= 1<<15 { 2569 c.ctxt.Diag("branch too far\n%v", p) 2570 } 2571 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2572 2573 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2574 var v int32 2575 if p.As == ABC || p.As == ABCL { 2576 v = c.regoff(&p.To) & 31 2577 } else { 2578 v = 20 /* unconditional */ 2579 } 2580 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2581 o2 = OPVCC(19, 16, 0, 0) 2582 if p.As == ABL || p.As == ABCL { 2583 o2 |= 1 2584 } 2585 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2586 2587 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2588 var v int32 2589 if p.As == ABC || p.As == ABCL { 2590 v = c.regoff(&p.From) & 31 2591 } else { 2592 v = 20 /* unconditional */ 2593 } 2594 r := int(p.Reg) 2595 if r == 0 { 2596 r = 0 2597 } 2598 switch oclass(&p.To) { 2599 case C_CTR: 2600 o1 = OPVCC(19, 528, 0, 0) 2601 2602 case C_LR: 2603 o1 = OPVCC(19, 16, 0, 0) 2604 2605 default: 2606 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2607 v = 0 2608 } 2609 2610 if p.As == ABL || p.As == ABCL { 2611 o1 |= 1 2612 } 2613 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2614 2615 case 19: /* mov $lcon,r ==> cau+or */ 2616 d := c.vregoff(&p.From) 2617 2618 if p.From.Sym == nil { 2619 o1 = loadu32(int(p.To.Reg), d) 2620 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2621 } else { 2622 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2623 } 2624 2625 //if(dlm) reloc(&p->from, p->pc, 0); 2626 2627 case 20: /* add $ucon,,r */ 2628 v := c.regoff(&p.From) 2629 2630 r := int(p.Reg) 2631 if r == 0 { 2632 r = int(p.To.Reg) 2633 } 2634 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2635 c.ctxt.Diag("literal operation on R0\n%v", p) 2636 } 2637 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2638 2639 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2640 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2641 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2642 } 2643 d := c.vregoff(&p.From) 2644 o1 = loadu32(REGTMP, d) 2645 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2646 r := int(p.Reg) 2647 if r == 0 { 2648 r = int(p.To.Reg) 2649 } 2650 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2651 if p.From.Sym != nil { 2652 c.ctxt.Diag("%v is not supported", p) 2653 } 2654 2655 //if(dlm) reloc(&p->from, p->pc, 0); 2656 2657 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2658 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2659 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2660 } 2661 d := c.vregoff(&p.From) 2662 o1 = loadu32(REGTMP, d) 2663 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2664 r := int(p.Reg) 2665 if r == 0 { 2666 r = int(p.To.Reg) 2667 } 2668 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2669 if p.From.Sym != nil { 2670 c.ctxt.Diag("%v is not supported", p) 2671 } 2672 2673 //if(dlm) reloc(&p->from, p->pc, 0); 2674 2675 /*24*/ 2676 case 25: 2677 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2678 v := c.regoff(&p.From) 2679 2680 if v < 0 { 2681 v = 0 2682 } else if v > 63 { 2683 v = 63 2684 } 2685 r := int(p.Reg) 2686 if r == 0 { 2687 r = int(p.To.Reg) 2688 } 2689 var a int 2690 op := uint32(0) 2691 switch p.As { 2692 case ASLD, ASLDCC: 2693 a = int(63 - v) 2694 op = OP_RLDICR 2695 2696 case ASRD, ASRDCC: 2697 a = int(v) 2698 v = 64 - v 2699 op = OP_RLDICL 2700 case AROTL: 2701 a = int(0) 2702 op = OP_RLDICL 2703 default: 2704 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2705 a = 0 2706 o1 = 0 2707 } 2708 2709 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2710 if p.As == ASLDCC || p.As == ASRDCC { 2711 o1 |= 1 // Set the condition code bit 2712 } 2713 2714 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2715 if p.To.Reg == REGTMP { 2716 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2717 } 2718 v := c.regoff(&p.From) 2719 r := int(p.From.Reg) 2720 if r == 0 { 2721 r = int(o.param) 2722 } 2723 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2724 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2725 2726 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2727 v := c.regoff(p.GetFrom3()) 2728 2729 r := int(p.From.Reg) 2730 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2731 2732 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2733 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2734 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2735 } 2736 v := c.regoff(p.GetFrom3()) 2737 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2738 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2739 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2740 if p.From.Sym != nil { 2741 c.ctxt.Diag("%v is not supported", p) 2742 } 2743 2744 //if(dlm) reloc(&p->from3, p->pc, 0); 2745 2746 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2747 v := c.regoff(&p.From) 2748 2749 d := c.vregoff(p.GetFrom3()) 2750 var mask [2]uint8 2751 c.maskgen64(p, mask[:], uint64(d)) 2752 var a int 2753 switch p.As { 2754 case ARLDC, ARLDCCC: 2755 a = int(mask[0]) /* MB */ 2756 if int32(mask[1]) != (63 - v) { 2757 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2758 } 2759 2760 case ARLDCL, ARLDCLCC: 2761 a = int(mask[0]) /* MB */ 2762 if mask[1] != 63 { 2763 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2764 } 2765 2766 case ARLDCR, ARLDCRCC: 2767 a = int(mask[1]) /* ME */ 2768 if mask[0] != 0 { 2769 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2770 } 2771 2772 default: 2773 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2774 a = 0 2775 } 2776 2777 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2778 o1 |= (uint32(a) & 31) << 6 2779 if v&0x20 != 0 { 2780 o1 |= 1 << 1 2781 } 2782 if a&0x20 != 0 { 2783 o1 |= 1 << 5 /* mb[5] is top bit */ 2784 } 2785 2786 case 30: /* rldimi $sh,s,$mask,a */ 2787 v := c.regoff(&p.From) 2788 2789 d := c.vregoff(p.GetFrom3()) 2790 2791 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2792 // the ppc64 asm. 2793 switch p.As { 2794 case ARLDMI, ARLDMICC: 2795 var mask [2]uint8 2796 c.maskgen64(p, mask[:], uint64(d)) 2797 if int32(mask[1]) != (63 - v) { 2798 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2799 } 2800 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2801 o1 |= (uint32(mask[0]) & 31) << 6 2802 if v&0x20 != 0 { 2803 o1 |= 1 << 1 2804 } 2805 if mask[0]&0x20 != 0 { 2806 o1 |= 1 << 5 /* mb[5] is top bit */ 2807 } 2808 2809 // Opcodes with shift count operands. 2810 case ARLDIMI, ARLDIMICC: 2811 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2812 o1 |= (uint32(d) & 31) << 6 2813 if d&0x20 != 0 { 2814 o1 |= 1 << 5 2815 } 2816 if v&0x20 != 0 { 2817 o1 |= 1 << 1 2818 } 2819 } 2820 2821 case 31: /* dword */ 2822 d := c.vregoff(&p.From) 2823 2824 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2825 o1 = uint32(d >> 32) 2826 o2 = uint32(d) 2827 } else { 2828 o1 = uint32(d) 2829 o2 = uint32(d >> 32) 2830 } 2831 2832 if p.From.Sym != nil { 2833 rel := obj.Addrel(c.cursym) 2834 rel.Off = int32(c.pc) 2835 rel.Siz = 8 2836 rel.Sym = p.From.Sym 2837 rel.Add = p.From.Offset 2838 rel.Type = objabi.R_ADDR 2839 o2 = 0 2840 o1 = o2 2841 } 2842 2843 case 32: /* fmul frc,fra,frd */ 2844 r := int(p.Reg) 2845 2846 if r == 0 { 2847 r = int(p.To.Reg) 2848 } 2849 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2850 2851 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2852 r := int(p.From.Reg) 2853 2854 if oclass(&p.From) == C_NONE { 2855 r = int(p.To.Reg) 2856 } 2857 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2858 2859 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2860 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6 2861 2862 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2863 v := c.regoff(&p.To) 2864 2865 r := int(p.To.Reg) 2866 if r == 0 { 2867 r = int(o.param) 2868 } 2869 // Offsets in DS form stores must be a multiple of 4 2870 inst := c.opstore(p.As) 2871 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2872 log.Fatalf("invalid offset for DS form load/store %v", p) 2873 } 2874 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2875 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2876 2877 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2878 v := c.regoff(&p.From) 2879 2880 r := int(p.From.Reg) 2881 if r == 0 { 2882 r = int(o.param) 2883 } 2884 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2885 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2886 2887 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2888 v := c.regoff(&p.From) 2889 2890 r := int(p.From.Reg) 2891 if r == 0 { 2892 r = int(o.param) 2893 } 2894 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2895 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2896 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2897 2898 case 40: /* word */ 2899 o1 = uint32(c.regoff(&p.From)) 2900 2901 case 41: /* stswi */ 2902 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2903 2904 case 42: /* lswi */ 2905 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 2906 2907 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */ 2908 /* TH field for dcbt/dcbtst: */ 2909 /* 0 = Block access - program will soon access EA. */ 2910 /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */ 2911 /* 16 = Block access - program will soon make a transient access to EA. */ 2912 /* 17 = Block access - program will not access EA for a long time. */ 2913 2914 /* L field for dcbf: */ 2915 /* 0 = invalidates the block containing EA in all processors. */ 2916 /* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */ 2917 /* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */ 2918 if p.To.Type == obj.TYPE_NONE { 2919 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2920 } else { 2921 th := c.regoff(&p.To) 2922 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg)) 2923 } 2924 2925 case 44: /* indexed store */ 2926 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2927 2928 case 45: /* indexed load */ 2929 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2930 2931 case 46: /* plain op */ 2932 o1 = c.oprrr(p.As) 2933 2934 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2935 r := int(p.From.Reg) 2936 2937 if r == 0 { 2938 r = int(p.To.Reg) 2939 } 2940 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2941 2942 case 48: /* op Rs, Ra */ 2943 r := int(p.From.Reg) 2944 2945 if r == 0 { 2946 r = int(p.To.Reg) 2947 } 2948 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2949 2950 case 49: /* op Rb; op $n, Rb */ 2951 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2952 v := c.regoff(&p.From) & 1 2953 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2954 } else { 2955 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2956 } 2957 2958 case 50: /* rem[u] r1[,r2],r3 */ 2959 r := int(p.Reg) 2960 2961 if r == 0 { 2962 r = int(p.To.Reg) 2963 } 2964 v := c.oprrr(p.As) 2965 t := v & (1<<10 | 1) /* OE|Rc */ 2966 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2967 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2968 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2969 if p.As == AREMU { 2970 o4 = o3 2971 2972 /* Clear top 32 bits */ 2973 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2974 } 2975 2976 case 51: /* remd[u] r1[,r2],r3 */ 2977 r := int(p.Reg) 2978 2979 if r == 0 { 2980 r = int(p.To.Reg) 2981 } 2982 v := c.oprrr(p.As) 2983 t := v & (1<<10 | 1) /* OE|Rc */ 2984 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2985 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2986 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2987 2988 case 52: /* mtfsbNx cr(n) */ 2989 v := c.regoff(&p.From) & 31 2990 2991 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2992 2993 case 53: /* mffsX ,fr1 */ 2994 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2995 2996 case 54: /* mov msr,r1; mov r1, msr*/ 2997 if oclass(&p.From) == C_REG { 2998 if p.As == AMOVD { 2999 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 3000 } else { 3001 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 3002 } 3003 } else { 3004 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 3005 } 3006 3007 case 55: /* op Rb, Rd */ 3008 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 3009 3010 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 3011 v := c.regoff(&p.From) 3012 3013 r := int(p.Reg) 3014 if r == 0 { 3015 r = int(p.To.Reg) 3016 } 3017 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 3018 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 3019 o1 |= 1 << 1 /* mb[5] */ 3020 } 3021 3022 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 3023 v := c.regoff(&p.From) 3024 3025 r := int(p.Reg) 3026 if r == 0 { 3027 r = int(p.To.Reg) 3028 } 3029 3030 /* 3031 * Let user (gs) shoot himself in the foot. 3032 * qc has already complained. 3033 * 3034 if(v < 0 || v > 31) 3035 ctxt->diag("illegal shift %ld\n%v", v, p); 3036 */ 3037 if v < 0 { 3038 v = 0 3039 } else if v > 32 { 3040 v = 32 3041 } 3042 var mask [2]uint8 3043 switch p.As { 3044 case AROTLW: 3045 mask[0], mask[1] = 0, 31 3046 case ASRW, ASRWCC: 3047 mask[0], mask[1] = uint8(v), 31 3048 v = 32 - v 3049 default: 3050 mask[0], mask[1] = 0, uint8(31-v) 3051 } 3052 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3053 if p.As == ASLWCC || p.As == ASRWCC { 3054 o1 |= 1 // set the condition code 3055 } 3056 3057 case 58: /* logical $andcon,[s],a */ 3058 v := c.regoff(&p.From) 3059 3060 r := int(p.Reg) 3061 if r == 0 { 3062 r = int(p.To.Reg) 3063 } 3064 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3065 3066 case 59: /* or/and $ucon,,r */ 3067 v := c.regoff(&p.From) 3068 3069 r := int(p.Reg) 3070 if r == 0 { 3071 r = int(p.To.Reg) 3072 } 3073 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3074 3075 case 60: /* tw to,a,b */ 3076 r := int(c.regoff(&p.From) & 31) 3077 3078 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3079 3080 case 61: /* tw to,a,$simm */ 3081 r := int(c.regoff(&p.From) & 31) 3082 3083 v := c.regoff(&p.To) 3084 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3085 3086 case 62: /* rlwmi $sh,s,$mask,a */ 3087 v := c.regoff(&p.From) 3088 3089 var mask [2]uint8 3090 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3091 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3092 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3093 3094 case 63: /* rlwmi b,s,$mask,a */ 3095 var mask [2]uint8 3096 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3097 3098 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3099 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3100 3101 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3102 var v int32 3103 if p.From3Type() != obj.TYPE_NONE { 3104 v = c.regoff(p.GetFrom3()) & 255 3105 } else { 3106 v = 255 3107 } 3108 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3109 3110 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3111 if p.To.Reg == 0 { 3112 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3113 } 3114 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3115 3116 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3117 var r int 3118 var v int32 3119 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3120 r = int(p.From.Reg) 3121 v = int32(p.To.Reg) 3122 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3123 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3124 } else { 3125 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3126 } 3127 } else { 3128 r = int(p.To.Reg) 3129 v = int32(p.From.Reg) 3130 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3131 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3132 } else { 3133 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3134 } 3135 } 3136 3137 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3138 3139 case 67: /* mcrf crfD,crfS */ 3140 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3141 c.ctxt.Diag("illegal CR field number\n%v", p) 3142 } 3143 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3144 3145 case 68: /* mfcr rD; mfocrf CRM,rD */ 3146 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3147 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3148 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3149 } else { 3150 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3151 } 3152 3153 case 69: /* mtcrf CRM,rS */ 3154 var v int32 3155 if p.From3Type() != obj.TYPE_NONE { 3156 if p.To.Reg != 0 { 3157 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3158 } 3159 v = c.regoff(p.GetFrom3()) & 0xff 3160 } else { 3161 if p.To.Reg == 0 { 3162 v = 0xff /* CR */ 3163 } else { 3164 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3165 } 3166 } 3167 3168 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3169 3170 case 70: /* [f]cmp r,r,cr*/ 3171 var r int 3172 if p.Reg == 0 { 3173 r = 0 3174 } else { 3175 r = (int(p.Reg) & 7) << 2 3176 } 3177 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3178 3179 case 71: /* cmp[l] r,i,cr*/ 3180 var r int 3181 if p.Reg == 0 { 3182 r = 0 3183 } else { 3184 r = (int(p.Reg) & 7) << 2 3185 } 3186 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3187 3188 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3189 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3190 3191 case 73: /* mcrfs crfD,crfS */ 3192 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3193 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3194 } 3195 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3196 3197 case 77: /* syscall $scon, syscall Rx */ 3198 if p.From.Type == obj.TYPE_CONST { 3199 if p.From.Offset > BIG || p.From.Offset < -BIG { 3200 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3201 } 3202 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3203 } else if p.From.Type == obj.TYPE_REG { 3204 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3205 } else { 3206 c.ctxt.Diag("illegal syscall: %v", p) 3207 o1 = 0x7fe00008 // trap always 3208 } 3209 3210 o2 = c.oprrr(p.As) 3211 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3212 3213 case 78: /* undef */ 3214 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3215 always to be an illegal instruction." */ 3216 3217 /* relocation operations */ 3218 case 74: 3219 v := c.vregoff(&p.To) 3220 // Offsets in DS form stores must be a multiple of 4 3221 inst := c.opstore(p.As) 3222 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3223 log.Fatalf("invalid offset for DS form load/store %v", p) 3224 } 3225 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3226 3227 //if(dlm) reloc(&p->to, p->pc, 1); 3228 3229 case 75: 3230 v := c.vregoff(&p.From) 3231 // Offsets in DS form loads must be a multiple of 4 3232 inst := c.opload(p.As) 3233 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3234 log.Fatalf("invalid offset for DS form load/store %v", p) 3235 } 3236 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3237 3238 //if(dlm) reloc(&p->from, p->pc, 1); 3239 3240 case 76: 3241 v := c.vregoff(&p.From) 3242 // Offsets in DS form loads must be a multiple of 4 3243 inst := c.opload(p.As) 3244 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3245 log.Fatalf("invalid offset for DS form load/store %v", p) 3246 } 3247 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3248 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3249 3250 //if(dlm) reloc(&p->from, p->pc, 1); 3251 3252 case 79: 3253 if p.From.Offset != 0 { 3254 c.ctxt.Diag("invalid offset against tls var %v", p) 3255 } 3256 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3257 rel := obj.Addrel(c.cursym) 3258 rel.Off = int32(c.pc) 3259 rel.Siz = 4 3260 rel.Sym = p.From.Sym 3261 rel.Type = objabi.R_POWER_TLS_LE 3262 3263 case 80: 3264 if p.From.Offset != 0 { 3265 c.ctxt.Diag("invalid offset against tls var %v", p) 3266 } 3267 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3268 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3269 rel := obj.Addrel(c.cursym) 3270 rel.Off = int32(c.pc) 3271 rel.Siz = 8 3272 rel.Sym = p.From.Sym 3273 rel.Type = objabi.R_POWER_TLS_IE 3274 3275 case 81: 3276 v := c.vregoff(&p.To) 3277 if v != 0 { 3278 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3279 } 3280 3281 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3282 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3283 rel := obj.Addrel(c.cursym) 3284 rel.Off = int32(c.pc) 3285 rel.Siz = 8 3286 rel.Sym = p.From.Sym 3287 rel.Type = objabi.R_ADDRPOWER_GOT 3288 case 82: /* vector instructions, VX-form and VC-form */ 3289 if p.From.Type == obj.TYPE_REG { 3290 /* reg reg none OR reg reg reg */ 3291 /* 3-register operand order: VRA, VRB, VRT */ 3292 /* 2-register operand order: VRA, VRT */ 3293 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3294 } else if p.From3Type() == obj.TYPE_CONST { 3295 /* imm imm reg reg */ 3296 /* operand order: SIX, VRA, ST, VRT */ 3297 six := int(c.regoff(&p.From)) 3298 st := int(c.regoff(p.GetFrom3())) 3299 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3300 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3301 /* imm reg reg */ 3302 /* operand order: UIM, VRB, VRT */ 3303 uim := int(c.regoff(&p.From)) 3304 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3305 } else { 3306 /* imm reg */ 3307 /* operand order: SIM, VRT */ 3308 sim := int(c.regoff(&p.From)) 3309 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3310 } 3311 3312 case 83: /* vector instructions, VA-form */ 3313 if p.From.Type == obj.TYPE_REG { 3314 /* reg reg reg reg */ 3315 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3316 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3317 } else if p.From.Type == obj.TYPE_CONST { 3318 /* imm reg reg reg */ 3319 /* operand order: SHB, VRA, VRB, VRT */ 3320 shb := int(c.regoff(&p.From)) 3321 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb)) 3322 } 3323 3324 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3325 bc := c.vregoff(&p.From) 3326 3327 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3328 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc)) 3329 3330 case 85: /* vector instructions, VX-form */ 3331 /* reg none reg */ 3332 /* 2-register operand order: VRB, VRT */ 3333 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3334 3335 case 86: /* VSX indexed store, XX1-form */ 3336 /* reg reg reg */ 3337 /* 3-register operand order: XT, (RB)(RA*1) */ 3338 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3339 3340 case 87: /* VSX indexed load, XX1-form */ 3341 /* reg reg reg */ 3342 /* 3-register operand order: (RB)(RA*1), XT */ 3343 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3344 3345 case 88: /* VSX instructions, XX1-form */ 3346 /* reg reg none OR reg reg reg */ 3347 /* 3-register operand order: RA, RB, XT */ 3348 /* 2-register operand order: XS, RA or RA, XT */ 3349 xt := int32(p.To.Reg) 3350 xs := int32(p.From.Reg) 3351 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3352 if REG_V0 <= xt && xt <= REG_V31 { 3353 /* Convert V0-V31 to VS32-VS63 */ 3354 xt = xt + 64 3355 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3356 } else if REG_F0 <= xt && xt <= REG_F31 { 3357 /* Convert F0-F31 to VS0-VS31 */ 3358 xt = xt + 64 3359 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3360 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3361 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3362 } else if REG_V0 <= xs && xs <= REG_V31 { 3363 /* Likewise for XS */ 3364 xs = xs + 64 3365 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3366 } else if REG_F0 <= xs && xs <= REG_F31 { 3367 xs = xs + 64 3368 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3369 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3370 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3371 } 3372 3373 case 89: /* VSX instructions, XX2-form */ 3374 /* reg none reg OR reg imm reg */ 3375 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3376 uim := int(c.regoff(p.GetFrom3())) 3377 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3378 3379 case 90: /* VSX instructions, XX3-form */ 3380 if p.From3Type() == obj.TYPE_NONE { 3381 /* reg reg reg */ 3382 /* 3-register operand order: XA, XB, XT */ 3383 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3384 } else if p.From3Type() == obj.TYPE_CONST { 3385 /* reg reg reg imm */ 3386 /* operand order: XA, XB, DM, XT */ 3387 dm := int(c.regoff(p.GetFrom3())) 3388 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3389 } 3390 3391 case 91: /* VSX instructions, XX4-form */ 3392 /* reg reg reg reg */ 3393 /* 3-register operand order: XA, XB, XC, XT */ 3394 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3395 3396 case 92: /* X-form instructions, 3-operands */ 3397 if p.To.Type == obj.TYPE_CONST { 3398 /* imm reg reg */ 3399 xf := int32(p.From.Reg) 3400 if REG_F0 <= xf && xf <= REG_F31 { 3401 /* operand order: FRA, FRB, BF */ 3402 bf := int(c.regoff(&p.To)) << 2 3403 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3404 } else { 3405 /* operand order: RA, RB, L */ 3406 l := int(c.regoff(&p.To)) 3407 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg)) 3408 } 3409 } else if p.From3Type() == obj.TYPE_CONST { 3410 /* reg reg imm */ 3411 /* operand order: RB, L, RA */ 3412 l := int(c.regoff(p.GetFrom3())) 3413 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg)) 3414 } else if p.To.Type == obj.TYPE_REG { 3415 cr := int32(p.To.Reg) 3416 if REG_CR0 <= cr && cr <= REG_CR7 { 3417 /* cr reg reg */ 3418 /* operand order: RA, RB, BF */ 3419 bf := (int(p.To.Reg) & 7) << 2 3420 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3421 } else if p.From.Type == obj.TYPE_CONST { 3422 /* reg imm */ 3423 /* operand order: L, RT */ 3424 l := int(c.regoff(&p.From)) 3425 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg)) 3426 } else { 3427 switch p.As { 3428 case ACOPY, APASTECC: 3429 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg)) 3430 default: 3431 /* reg reg reg */ 3432 /* operand order: RS, RB, RA */ 3433 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3434 } 3435 } 3436 } 3437 3438 case 93: /* X-form instructions, 2-operands */ 3439 if p.To.Type == obj.TYPE_CONST { 3440 /* imm reg */ 3441 /* operand order: FRB, BF */ 3442 bf := int(c.regoff(&p.To)) << 2 3443 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3444 } else if p.Reg == 0 { 3445 /* popcnt* r,r, X-form */ 3446 /* operand order: RS, RA */ 3447 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3448 } 3449 3450 case 94: /* Z23-form instructions, 4-operands */ 3451 /* reg reg reg imm */ 3452 /* operand order: RA, RB, CY, RT */ 3453 cy := int(c.regoff(p.GetFrom3())) 3454 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy)) 3455 } 3456 3457 out[0] = o1 3458 out[1] = o2 3459 out[2] = o3 3460 out[3] = o4 3461 out[4] = o5 3462 return 3463 } 3464 3465 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3466 c.instoffset = 0 3467 if a != nil { 3468 c.aclass(a) 3469 } 3470 return c.instoffset 3471 } 3472 3473 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3474 return int32(c.vregoff(a)) 3475 } 3476 3477 func (c *ctxt9) oprrr(a obj.As) uint32 { 3478 switch a { 3479 case AADD: 3480 return OPVCC(31, 266, 0, 0) 3481 case AADDCC: 3482 return OPVCC(31, 266, 0, 1) 3483 case AADDV: 3484 return OPVCC(31, 266, 1, 0) 3485 case AADDVCC: 3486 return OPVCC(31, 266, 1, 1) 3487 case AADDC: 3488 return OPVCC(31, 10, 0, 0) 3489 case AADDCCC: 3490 return OPVCC(31, 10, 0, 1) 3491 case AADDCV: 3492 return OPVCC(31, 10, 1, 0) 3493 case AADDCVCC: 3494 return OPVCC(31, 10, 1, 1) 3495 case AADDE: 3496 return OPVCC(31, 138, 0, 0) 3497 case AADDECC: 3498 return OPVCC(31, 138, 0, 1) 3499 case AADDEV: 3500 return OPVCC(31, 138, 1, 0) 3501 case AADDEVCC: 3502 return OPVCC(31, 138, 1, 1) 3503 case AADDME: 3504 return OPVCC(31, 234, 0, 0) 3505 case AADDMECC: 3506 return OPVCC(31, 234, 0, 1) 3507 case AADDMEV: 3508 return OPVCC(31, 234, 1, 0) 3509 case AADDMEVCC: 3510 return OPVCC(31, 234, 1, 1) 3511 case AADDZE: 3512 return OPVCC(31, 202, 0, 0) 3513 case AADDZECC: 3514 return OPVCC(31, 202, 0, 1) 3515 case AADDZEV: 3516 return OPVCC(31, 202, 1, 0) 3517 case AADDZEVCC: 3518 return OPVCC(31, 202, 1, 1) 3519 case AADDEX: 3520 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */ 3521 3522 case AAND: 3523 return OPVCC(31, 28, 0, 0) 3524 case AANDCC: 3525 return OPVCC(31, 28, 0, 1) 3526 case AANDN: 3527 return OPVCC(31, 60, 0, 0) 3528 case AANDNCC: 3529 return OPVCC(31, 60, 0, 1) 3530 3531 case ACMP: 3532 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3533 case ACMPU: 3534 return OPVCC(31, 32, 0, 0) | 1<<21 3535 case ACMPW: 3536 return OPVCC(31, 0, 0, 0) /* L=0 */ 3537 case ACMPWU: 3538 return OPVCC(31, 32, 0, 0) 3539 case ACMPB: 3540 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3541 3542 case ACNTLZW: 3543 return OPVCC(31, 26, 0, 0) 3544 case ACNTLZWCC: 3545 return OPVCC(31, 26, 0, 1) 3546 case ACNTLZD: 3547 return OPVCC(31, 58, 0, 0) 3548 case ACNTLZDCC: 3549 return OPVCC(31, 58, 0, 1) 3550 3551 case ACRAND: 3552 return OPVCC(19, 257, 0, 0) 3553 case ACRANDN: 3554 return OPVCC(19, 129, 0, 0) 3555 case ACREQV: 3556 return OPVCC(19, 289, 0, 0) 3557 case ACRNAND: 3558 return OPVCC(19, 225, 0, 0) 3559 case ACRNOR: 3560 return OPVCC(19, 33, 0, 0) 3561 case ACROR: 3562 return OPVCC(19, 449, 0, 0) 3563 case ACRORN: 3564 return OPVCC(19, 417, 0, 0) 3565 case ACRXOR: 3566 return OPVCC(19, 193, 0, 0) 3567 3568 case ADCBF: 3569 return OPVCC(31, 86, 0, 0) 3570 case ADCBI: 3571 return OPVCC(31, 470, 0, 0) 3572 case ADCBST: 3573 return OPVCC(31, 54, 0, 0) 3574 case ADCBT: 3575 return OPVCC(31, 278, 0, 0) 3576 case ADCBTST: 3577 return OPVCC(31, 246, 0, 0) 3578 case ADCBZ: 3579 return OPVCC(31, 1014, 0, 0) 3580 3581 case AREM, ADIVW: 3582 return OPVCC(31, 491, 0, 0) 3583 3584 case AREMCC, ADIVWCC: 3585 return OPVCC(31, 491, 0, 1) 3586 3587 case AREMV, ADIVWV: 3588 return OPVCC(31, 491, 1, 0) 3589 3590 case AREMVCC, ADIVWVCC: 3591 return OPVCC(31, 491, 1, 1) 3592 3593 case AREMU, ADIVWU: 3594 return OPVCC(31, 459, 0, 0) 3595 3596 case AREMUCC, ADIVWUCC: 3597 return OPVCC(31, 459, 0, 1) 3598 3599 case AREMUV, ADIVWUV: 3600 return OPVCC(31, 459, 1, 0) 3601 3602 case AREMUVCC, ADIVWUVCC: 3603 return OPVCC(31, 459, 1, 1) 3604 3605 case AREMD, ADIVD: 3606 return OPVCC(31, 489, 0, 0) 3607 3608 case AREMDCC, ADIVDCC: 3609 return OPVCC(31, 489, 0, 1) 3610 3611 case ADIVDE: 3612 return OPVCC(31, 425, 0, 0) 3613 3614 case ADIVDECC: 3615 return OPVCC(31, 425, 0, 1) 3616 3617 case ADIVDEU: 3618 return OPVCC(31, 393, 0, 0) 3619 3620 case ADIVDEUCC: 3621 return OPVCC(31, 393, 0, 1) 3622 3623 case AREMDV, ADIVDV: 3624 return OPVCC(31, 489, 1, 0) 3625 3626 case AREMDVCC, ADIVDVCC: 3627 return OPVCC(31, 489, 1, 1) 3628 3629 case AREMDU, ADIVDU: 3630 return OPVCC(31, 457, 0, 0) 3631 3632 case AREMDUCC, ADIVDUCC: 3633 return OPVCC(31, 457, 0, 1) 3634 3635 case AREMDUV, ADIVDUV: 3636 return OPVCC(31, 457, 1, 0) 3637 3638 case AREMDUVCC, ADIVDUVCC: 3639 return OPVCC(31, 457, 1, 1) 3640 3641 case AEIEIO: 3642 return OPVCC(31, 854, 0, 0) 3643 3644 case AEQV: 3645 return OPVCC(31, 284, 0, 0) 3646 case AEQVCC: 3647 return OPVCC(31, 284, 0, 1) 3648 3649 case AEXTSB: 3650 return OPVCC(31, 954, 0, 0) 3651 case AEXTSBCC: 3652 return OPVCC(31, 954, 0, 1) 3653 case AEXTSH: 3654 return OPVCC(31, 922, 0, 0) 3655 case AEXTSHCC: 3656 return OPVCC(31, 922, 0, 1) 3657 case AEXTSW: 3658 return OPVCC(31, 986, 0, 0) 3659 case AEXTSWCC: 3660 return OPVCC(31, 986, 0, 1) 3661 3662 case AFABS: 3663 return OPVCC(63, 264, 0, 0) 3664 case AFABSCC: 3665 return OPVCC(63, 264, 0, 1) 3666 case AFADD: 3667 return OPVCC(63, 21, 0, 0) 3668 case AFADDCC: 3669 return OPVCC(63, 21, 0, 1) 3670 case AFADDS: 3671 return OPVCC(59, 21, 0, 0) 3672 case AFADDSCC: 3673 return OPVCC(59, 21, 0, 1) 3674 case AFCMPO: 3675 return OPVCC(63, 32, 0, 0) 3676 case AFCMPU: 3677 return OPVCC(63, 0, 0, 0) 3678 case AFCFID: 3679 return OPVCC(63, 846, 0, 0) 3680 case AFCFIDCC: 3681 return OPVCC(63, 846, 0, 1) 3682 case AFCFIDU: 3683 return OPVCC(63, 974, 0, 0) 3684 case AFCFIDUCC: 3685 return OPVCC(63, 974, 0, 1) 3686 case AFCFIDS: 3687 return OPVCC(59, 846, 0, 0) 3688 case AFCFIDSCC: 3689 return OPVCC(59, 846, 0, 1) 3690 case AFCTIW: 3691 return OPVCC(63, 14, 0, 0) 3692 case AFCTIWCC: 3693 return OPVCC(63, 14, 0, 1) 3694 case AFCTIWZ: 3695 return OPVCC(63, 15, 0, 0) 3696 case AFCTIWZCC: 3697 return OPVCC(63, 15, 0, 1) 3698 case AFCTID: 3699 return OPVCC(63, 814, 0, 0) 3700 case AFCTIDCC: 3701 return OPVCC(63, 814, 0, 1) 3702 case AFCTIDZ: 3703 return OPVCC(63, 815, 0, 0) 3704 case AFCTIDZCC: 3705 return OPVCC(63, 815, 0, 1) 3706 case AFDIV: 3707 return OPVCC(63, 18, 0, 0) 3708 case AFDIVCC: 3709 return OPVCC(63, 18, 0, 1) 3710 case AFDIVS: 3711 return OPVCC(59, 18, 0, 0) 3712 case AFDIVSCC: 3713 return OPVCC(59, 18, 0, 1) 3714 case AFMADD: 3715 return OPVCC(63, 29, 0, 0) 3716 case AFMADDCC: 3717 return OPVCC(63, 29, 0, 1) 3718 case AFMADDS: 3719 return OPVCC(59, 29, 0, 0) 3720 case AFMADDSCC: 3721 return OPVCC(59, 29, 0, 1) 3722 3723 case AFMOVS, AFMOVD: 3724 return OPVCC(63, 72, 0, 0) /* load */ 3725 case AFMOVDCC: 3726 return OPVCC(63, 72, 0, 1) 3727 case AFMSUB: 3728 return OPVCC(63, 28, 0, 0) 3729 case AFMSUBCC: 3730 return OPVCC(63, 28, 0, 1) 3731 case AFMSUBS: 3732 return OPVCC(59, 28, 0, 0) 3733 case AFMSUBSCC: 3734 return OPVCC(59, 28, 0, 1) 3735 case AFMUL: 3736 return OPVCC(63, 25, 0, 0) 3737 case AFMULCC: 3738 return OPVCC(63, 25, 0, 1) 3739 case AFMULS: 3740 return OPVCC(59, 25, 0, 0) 3741 case AFMULSCC: 3742 return OPVCC(59, 25, 0, 1) 3743 case AFNABS: 3744 return OPVCC(63, 136, 0, 0) 3745 case AFNABSCC: 3746 return OPVCC(63, 136, 0, 1) 3747 case AFNEG: 3748 return OPVCC(63, 40, 0, 0) 3749 case AFNEGCC: 3750 return OPVCC(63, 40, 0, 1) 3751 case AFNMADD: 3752 return OPVCC(63, 31, 0, 0) 3753 case AFNMADDCC: 3754 return OPVCC(63, 31, 0, 1) 3755 case AFNMADDS: 3756 return OPVCC(59, 31, 0, 0) 3757 case AFNMADDSCC: 3758 return OPVCC(59, 31, 0, 1) 3759 case AFNMSUB: 3760 return OPVCC(63, 30, 0, 0) 3761 case AFNMSUBCC: 3762 return OPVCC(63, 30, 0, 1) 3763 case AFNMSUBS: 3764 return OPVCC(59, 30, 0, 0) 3765 case AFNMSUBSCC: 3766 return OPVCC(59, 30, 0, 1) 3767 case AFCPSGN: 3768 return OPVCC(63, 8, 0, 0) 3769 case AFCPSGNCC: 3770 return OPVCC(63, 8, 0, 1) 3771 case AFRES: 3772 return OPVCC(59, 24, 0, 0) 3773 case AFRESCC: 3774 return OPVCC(59, 24, 0, 1) 3775 case AFRIM: 3776 return OPVCC(63, 488, 0, 0) 3777 case AFRIMCC: 3778 return OPVCC(63, 488, 0, 1) 3779 case AFRIP: 3780 return OPVCC(63, 456, 0, 0) 3781 case AFRIPCC: 3782 return OPVCC(63, 456, 0, 1) 3783 case AFRIZ: 3784 return OPVCC(63, 424, 0, 0) 3785 case AFRIZCC: 3786 return OPVCC(63, 424, 0, 1) 3787 case AFRSP: 3788 return OPVCC(63, 12, 0, 0) 3789 case AFRSPCC: 3790 return OPVCC(63, 12, 0, 1) 3791 case AFRSQRTE: 3792 return OPVCC(63, 26, 0, 0) 3793 case AFRSQRTECC: 3794 return OPVCC(63, 26, 0, 1) 3795 case AFSEL: 3796 return OPVCC(63, 23, 0, 0) 3797 case AFSELCC: 3798 return OPVCC(63, 23, 0, 1) 3799 case AFSQRT: 3800 return OPVCC(63, 22, 0, 0) 3801 case AFSQRTCC: 3802 return OPVCC(63, 22, 0, 1) 3803 case AFSQRTS: 3804 return OPVCC(59, 22, 0, 0) 3805 case AFSQRTSCC: 3806 return OPVCC(59, 22, 0, 1) 3807 case AFSUB: 3808 return OPVCC(63, 20, 0, 0) 3809 case AFSUBCC: 3810 return OPVCC(63, 20, 0, 1) 3811 case AFSUBS: 3812 return OPVCC(59, 20, 0, 0) 3813 case AFSUBSCC: 3814 return OPVCC(59, 20, 0, 1) 3815 3816 case AICBI: 3817 return OPVCC(31, 982, 0, 0) 3818 case AISYNC: 3819 return OPVCC(19, 150, 0, 0) 3820 3821 case AMTFSB0: 3822 return OPVCC(63, 70, 0, 0) 3823 case AMTFSB0CC: 3824 return OPVCC(63, 70, 0, 1) 3825 case AMTFSB1: 3826 return OPVCC(63, 38, 0, 0) 3827 case AMTFSB1CC: 3828 return OPVCC(63, 38, 0, 1) 3829 3830 case AMULHW: 3831 return OPVCC(31, 75, 0, 0) 3832 case AMULHWCC: 3833 return OPVCC(31, 75, 0, 1) 3834 case AMULHWU: 3835 return OPVCC(31, 11, 0, 0) 3836 case AMULHWUCC: 3837 return OPVCC(31, 11, 0, 1) 3838 case AMULLW: 3839 return OPVCC(31, 235, 0, 0) 3840 case AMULLWCC: 3841 return OPVCC(31, 235, 0, 1) 3842 case AMULLWV: 3843 return OPVCC(31, 235, 1, 0) 3844 case AMULLWVCC: 3845 return OPVCC(31, 235, 1, 1) 3846 3847 case AMULHD: 3848 return OPVCC(31, 73, 0, 0) 3849 case AMULHDCC: 3850 return OPVCC(31, 73, 0, 1) 3851 case AMULHDU: 3852 return OPVCC(31, 9, 0, 0) 3853 case AMULHDUCC: 3854 return OPVCC(31, 9, 0, 1) 3855 case AMULLD: 3856 return OPVCC(31, 233, 0, 0) 3857 case AMULLDCC: 3858 return OPVCC(31, 233, 0, 1) 3859 case AMULLDV: 3860 return OPVCC(31, 233, 1, 0) 3861 case AMULLDVCC: 3862 return OPVCC(31, 233, 1, 1) 3863 3864 case ANAND: 3865 return OPVCC(31, 476, 0, 0) 3866 case ANANDCC: 3867 return OPVCC(31, 476, 0, 1) 3868 case ANEG: 3869 return OPVCC(31, 104, 0, 0) 3870 case ANEGCC: 3871 return OPVCC(31, 104, 0, 1) 3872 case ANEGV: 3873 return OPVCC(31, 104, 1, 0) 3874 case ANEGVCC: 3875 return OPVCC(31, 104, 1, 1) 3876 case ANOR: 3877 return OPVCC(31, 124, 0, 0) 3878 case ANORCC: 3879 return OPVCC(31, 124, 0, 1) 3880 case AOR: 3881 return OPVCC(31, 444, 0, 0) 3882 case AORCC: 3883 return OPVCC(31, 444, 0, 1) 3884 case AORN: 3885 return OPVCC(31, 412, 0, 0) 3886 case AORNCC: 3887 return OPVCC(31, 412, 0, 1) 3888 3889 case APOPCNTD: 3890 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3891 case APOPCNTW: 3892 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3893 case APOPCNTB: 3894 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3895 3896 case ARFI: 3897 return OPVCC(19, 50, 0, 0) 3898 case ARFCI: 3899 return OPVCC(19, 51, 0, 0) 3900 case ARFID: 3901 return OPVCC(19, 18, 0, 0) 3902 case AHRFID: 3903 return OPVCC(19, 274, 0, 0) 3904 3905 case ARLWMI: 3906 return OPVCC(20, 0, 0, 0) 3907 case ARLWMICC: 3908 return OPVCC(20, 0, 0, 1) 3909 case ARLWNM: 3910 return OPVCC(23, 0, 0, 0) 3911 case ARLWNMCC: 3912 return OPVCC(23, 0, 0, 1) 3913 3914 case ARLDCL: 3915 return OPVCC(30, 8, 0, 0) 3916 case ARLDCR: 3917 return OPVCC(30, 9, 0, 0) 3918 3919 case ARLDICL: 3920 return OPVCC(30, 0, 0, 0) 3921 case ARLDICLCC: 3922 return OPVCC(30, 0, 0, 1) 3923 case ARLDICR: 3924 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3925 case ARLDICRCC: 3926 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3927 3928 case ASYSCALL: 3929 return OPVCC(17, 1, 0, 0) 3930 3931 case ASLW: 3932 return OPVCC(31, 24, 0, 0) 3933 case ASLWCC: 3934 return OPVCC(31, 24, 0, 1) 3935 case ASLD: 3936 return OPVCC(31, 27, 0, 0) 3937 case ASLDCC: 3938 return OPVCC(31, 27, 0, 1) 3939 3940 case ASRAW: 3941 return OPVCC(31, 792, 0, 0) 3942 case ASRAWCC: 3943 return OPVCC(31, 792, 0, 1) 3944 case ASRAD: 3945 return OPVCC(31, 794, 0, 0) 3946 case ASRADCC: 3947 return OPVCC(31, 794, 0, 1) 3948 3949 case ASRW: 3950 return OPVCC(31, 536, 0, 0) 3951 case ASRWCC: 3952 return OPVCC(31, 536, 0, 1) 3953 case ASRD: 3954 return OPVCC(31, 539, 0, 0) 3955 case ASRDCC: 3956 return OPVCC(31, 539, 0, 1) 3957 3958 case ASUB: 3959 return OPVCC(31, 40, 0, 0) 3960 case ASUBCC: 3961 return OPVCC(31, 40, 0, 1) 3962 case ASUBV: 3963 return OPVCC(31, 40, 1, 0) 3964 case ASUBVCC: 3965 return OPVCC(31, 40, 1, 1) 3966 case ASUBC: 3967 return OPVCC(31, 8, 0, 0) 3968 case ASUBCCC: 3969 return OPVCC(31, 8, 0, 1) 3970 case ASUBCV: 3971 return OPVCC(31, 8, 1, 0) 3972 case ASUBCVCC: 3973 return OPVCC(31, 8, 1, 1) 3974 case ASUBE: 3975 return OPVCC(31, 136, 0, 0) 3976 case ASUBECC: 3977 return OPVCC(31, 136, 0, 1) 3978 case ASUBEV: 3979 return OPVCC(31, 136, 1, 0) 3980 case ASUBEVCC: 3981 return OPVCC(31, 136, 1, 1) 3982 case ASUBME: 3983 return OPVCC(31, 232, 0, 0) 3984 case ASUBMECC: 3985 return OPVCC(31, 232, 0, 1) 3986 case ASUBMEV: 3987 return OPVCC(31, 232, 1, 0) 3988 case ASUBMEVCC: 3989 return OPVCC(31, 232, 1, 1) 3990 case ASUBZE: 3991 return OPVCC(31, 200, 0, 0) 3992 case ASUBZECC: 3993 return OPVCC(31, 200, 0, 1) 3994 case ASUBZEV: 3995 return OPVCC(31, 200, 1, 0) 3996 case ASUBZEVCC: 3997 return OPVCC(31, 200, 1, 1) 3998 3999 case ASYNC: 4000 return OPVCC(31, 598, 0, 0) 4001 case ALWSYNC: 4002 return OPVCC(31, 598, 0, 0) | 1<<21 4003 4004 case APTESYNC: 4005 return OPVCC(31, 598, 0, 0) | 2<<21 4006 4007 case ATLBIE: 4008 return OPVCC(31, 306, 0, 0) 4009 case ATLBIEL: 4010 return OPVCC(31, 274, 0, 0) 4011 case ATLBSYNC: 4012 return OPVCC(31, 566, 0, 0) 4013 case ASLBIA: 4014 return OPVCC(31, 498, 0, 0) 4015 case ASLBIE: 4016 return OPVCC(31, 434, 0, 0) 4017 case ASLBMFEE: 4018 return OPVCC(31, 915, 0, 0) 4019 case ASLBMFEV: 4020 return OPVCC(31, 851, 0, 0) 4021 case ASLBMTE: 4022 return OPVCC(31, 402, 0, 0) 4023 4024 case ATW: 4025 return OPVCC(31, 4, 0, 0) 4026 case ATD: 4027 return OPVCC(31, 68, 0, 0) 4028 4029 /* Vector (VMX/Altivec) instructions */ 4030 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4031 /* are enabled starting at POWER6 (ISA 2.05). */ 4032 case AVAND: 4033 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 4034 case AVANDC: 4035 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 4036 case AVNAND: 4037 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 4038 4039 case AVOR: 4040 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 4041 case AVORC: 4042 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 4043 case AVNOR: 4044 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 4045 case AVXOR: 4046 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 4047 case AVEQV: 4048 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 4049 4050 case AVADDUBM: 4051 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 4052 case AVADDUHM: 4053 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 4054 case AVADDUWM: 4055 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 4056 case AVADDUDM: 4057 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 4058 case AVADDUQM: 4059 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 4060 4061 case AVADDCUQ: 4062 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 4063 case AVADDCUW: 4064 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 4065 4066 case AVADDUBS: 4067 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 4068 case AVADDUHS: 4069 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 4070 case AVADDUWS: 4071 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 4072 4073 case AVADDSBS: 4074 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 4075 case AVADDSHS: 4076 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 4077 case AVADDSWS: 4078 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 4079 4080 case AVADDEUQM: 4081 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 4082 case AVADDECUQ: 4083 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4084 4085 case AVPMSUMB: 4086 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4087 case AVPMSUMH: 4088 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4089 case AVPMSUMW: 4090 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4091 case AVPMSUMD: 4092 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4093 4094 case AVMSUMUDM: 4095 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */ 4096 4097 case AVSUBUBM: 4098 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4099 case AVSUBUHM: 4100 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4101 case AVSUBUWM: 4102 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4103 case AVSUBUDM: 4104 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4105 case AVSUBUQM: 4106 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4107 4108 case AVSUBCUQ: 4109 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4110 case AVSUBCUW: 4111 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4112 4113 case AVSUBUBS: 4114 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4115 case AVSUBUHS: 4116 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4117 case AVSUBUWS: 4118 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4119 4120 case AVSUBSBS: 4121 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4122 case AVSUBSHS: 4123 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4124 case AVSUBSWS: 4125 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4126 4127 case AVSUBEUQM: 4128 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4129 case AVSUBECUQ: 4130 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4131 4132 case AVRLB: 4133 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4134 case AVRLH: 4135 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4136 case AVRLW: 4137 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4138 case AVRLD: 4139 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4140 4141 case AVSLB: 4142 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4143 case AVSLH: 4144 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4145 case AVSLW: 4146 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4147 case AVSL: 4148 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4149 case AVSLO: 4150 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4151 case AVSRB: 4152 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4153 case AVSRH: 4154 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4155 case AVSRW: 4156 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4157 case AVSR: 4158 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4159 case AVSRO: 4160 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4161 case AVSLD: 4162 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4163 case AVSRD: 4164 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4165 4166 case AVSRAB: 4167 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4168 case AVSRAH: 4169 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4170 case AVSRAW: 4171 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4172 case AVSRAD: 4173 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4174 4175 case AVBPERMQ: 4176 return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */ 4177 case AVBPERMD: 4178 return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */ 4179 4180 case AVCLZB: 4181 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4182 case AVCLZH: 4183 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4184 case AVCLZW: 4185 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4186 case AVCLZD: 4187 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4188 4189 case AVPOPCNTB: 4190 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4191 case AVPOPCNTH: 4192 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4193 case AVPOPCNTW: 4194 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4195 case AVPOPCNTD: 4196 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4197 4198 case AVCMPEQUB: 4199 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4200 case AVCMPEQUBCC: 4201 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4202 case AVCMPEQUH: 4203 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4204 case AVCMPEQUHCC: 4205 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4206 case AVCMPEQUW: 4207 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4208 case AVCMPEQUWCC: 4209 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4210 case AVCMPEQUD: 4211 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4212 case AVCMPEQUDCC: 4213 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4214 4215 case AVCMPGTUB: 4216 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4217 case AVCMPGTUBCC: 4218 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4219 case AVCMPGTUH: 4220 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4221 case AVCMPGTUHCC: 4222 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4223 case AVCMPGTUW: 4224 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4225 case AVCMPGTUWCC: 4226 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4227 case AVCMPGTUD: 4228 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4229 case AVCMPGTUDCC: 4230 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4231 case AVCMPGTSB: 4232 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4233 case AVCMPGTSBCC: 4234 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4235 case AVCMPGTSH: 4236 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4237 case AVCMPGTSHCC: 4238 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4239 case AVCMPGTSW: 4240 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4241 case AVCMPGTSWCC: 4242 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4243 case AVCMPGTSD: 4244 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4245 case AVCMPGTSDCC: 4246 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4247 4248 case AVCMPNEZB: 4249 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */ 4250 case AVCMPNEZBCC: 4251 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */ 4252 4253 case AVPERM: 4254 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4255 4256 case AVSEL: 4257 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4258 4259 case AVCIPHER: 4260 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4261 case AVCIPHERLAST: 4262 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4263 case AVNCIPHER: 4264 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4265 case AVNCIPHERLAST: 4266 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4267 case AVSBOX: 4268 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4269 /* End of vector instructions */ 4270 4271 /* Vector scalar (VSX) instructions */ 4272 /* ISA 2.06 enables these for POWER7. */ 4273 case AMFVSRD, AMFVRD, AMFFPRD: 4274 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4275 case AMFVSRWZ: 4276 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4277 case AMFVSRLD: 4278 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */ 4279 4280 case AMTVSRD, AMTFPRD, AMTVRD: 4281 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4282 case AMTVSRWA: 4283 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4284 case AMTVSRWZ: 4285 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4286 case AMTVSRDD: 4287 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */ 4288 case AMTVSRWS: 4289 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */ 4290 4291 case AXXLANDQ: 4292 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4293 case AXXLANDC: 4294 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4295 case AXXLEQV: 4296 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4297 case AXXLNAND: 4298 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4299 4300 case AXXLORC: 4301 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4302 case AXXLNOR: 4303 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4304 case AXXLORQ: 4305 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4306 case AXXLXOR: 4307 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4308 4309 case AXXSEL: 4310 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4311 4312 case AXXMRGHW: 4313 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4314 case AXXMRGLW: 4315 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4316 4317 case AXXSPLTW: 4318 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4319 4320 case AXXPERMDI: 4321 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4322 4323 case AXXSLDWI: 4324 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4325 4326 case AXSCVDPSP: 4327 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4328 case AXSCVSPDP: 4329 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4330 case AXSCVDPSPN: 4331 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4332 case AXSCVSPDPN: 4333 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4334 4335 case AXVCVDPSP: 4336 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4337 case AXVCVSPDP: 4338 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4339 4340 case AXSCVDPSXDS: 4341 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4342 case AXSCVDPSXWS: 4343 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4344 case AXSCVDPUXDS: 4345 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4346 case AXSCVDPUXWS: 4347 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4348 4349 case AXSCVSXDDP: 4350 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4351 case AXSCVUXDDP: 4352 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4353 case AXSCVSXDSP: 4354 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4355 case AXSCVUXDSP: 4356 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4357 4358 case AXVCVDPSXDS: 4359 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4360 case AXVCVDPSXWS: 4361 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4362 case AXVCVDPUXDS: 4363 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4364 case AXVCVDPUXWS: 4365 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4366 case AXVCVSPSXDS: 4367 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4368 case AXVCVSPSXWS: 4369 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4370 case AXVCVSPUXDS: 4371 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4372 case AXVCVSPUXWS: 4373 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4374 4375 case AXVCVSXDDP: 4376 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4377 case AXVCVSXWDP: 4378 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4379 case AXVCVUXDDP: 4380 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4381 case AXVCVUXWDP: 4382 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4383 case AXVCVSXDSP: 4384 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4385 case AXVCVSXWSP: 4386 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4387 case AXVCVUXDSP: 4388 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4389 case AXVCVUXWSP: 4390 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4391 /* End of VSX instructions */ 4392 4393 case AMADDHD: 4394 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */ 4395 case AMADDHDU: 4396 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */ 4397 case AMADDLD: 4398 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */ 4399 4400 case AXOR: 4401 return OPVCC(31, 316, 0, 0) 4402 case AXORCC: 4403 return OPVCC(31, 316, 0, 1) 4404 } 4405 4406 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4407 return 0 4408 } 4409 4410 func (c *ctxt9) opirrr(a obj.As) uint32 { 4411 switch a { 4412 /* Vector (VMX/Altivec) instructions */ 4413 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4414 /* are enabled starting at POWER6 (ISA 2.05). */ 4415 case AVSLDOI: 4416 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4417 } 4418 4419 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4420 return 0 4421 } 4422 4423 func (c *ctxt9) opiirr(a obj.As) uint32 { 4424 switch a { 4425 /* Vector (VMX/Altivec) instructions */ 4426 /* ISA 2.07 enables these for POWER8 and beyond. */ 4427 case AVSHASIGMAW: 4428 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4429 case AVSHASIGMAD: 4430 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4431 } 4432 4433 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4434 return 0 4435 } 4436 4437 func (c *ctxt9) opirr(a obj.As) uint32 { 4438 switch a { 4439 case AADD: 4440 return OPVCC(14, 0, 0, 0) 4441 case AADDC: 4442 return OPVCC(12, 0, 0, 0) 4443 case AADDCCC: 4444 return OPVCC(13, 0, 0, 0) 4445 case -AADD: 4446 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4447 4448 case AANDCC: 4449 return OPVCC(28, 0, 0, 0) 4450 case -AANDCC: 4451 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4452 4453 case ABR: 4454 return OPVCC(18, 0, 0, 0) 4455 case ABL: 4456 return OPVCC(18, 0, 0, 0) | 1 4457 case obj.ADUFFZERO: 4458 return OPVCC(18, 0, 0, 0) | 1 4459 case obj.ADUFFCOPY: 4460 return OPVCC(18, 0, 0, 0) | 1 4461 case ABC: 4462 return OPVCC(16, 0, 0, 0) 4463 case ABCL: 4464 return OPVCC(16, 0, 0, 0) | 1 4465 4466 case ABEQ: 4467 return AOP_RRR(16<<26, 12, 2, 0) 4468 case ABGE: 4469 return AOP_RRR(16<<26, 4, 0, 0) 4470 case ABGT: 4471 return AOP_RRR(16<<26, 12, 1, 0) 4472 case ABLE: 4473 return AOP_RRR(16<<26, 4, 1, 0) 4474 case ABLT: 4475 return AOP_RRR(16<<26, 12, 0, 0) 4476 case ABNE: 4477 return AOP_RRR(16<<26, 4, 2, 0) 4478 case ABVC: 4479 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4480 case ABVS: 4481 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4482 4483 case ACMP: 4484 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4485 case ACMPU: 4486 return OPVCC(10, 0, 0, 0) | 1<<21 4487 case ACMPW: 4488 return OPVCC(11, 0, 0, 0) /* L=0 */ 4489 case ACMPWU: 4490 return OPVCC(10, 0, 0, 0) 4491 case ACMPEQB: 4492 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 4493 4494 case ALSW: 4495 return OPVCC(31, 597, 0, 0) 4496 4497 case ACOPY: 4498 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */ 4499 case APASTECC: 4500 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */ 4501 case ADARN: 4502 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */ 4503 4504 case AMULLW: 4505 return OPVCC(7, 0, 0, 0) 4506 4507 case AOR: 4508 return OPVCC(24, 0, 0, 0) 4509 case -AOR: 4510 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4511 4512 case ARLWMI: 4513 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4514 case ARLWMICC: 4515 return OPVCC(20, 0, 0, 1) 4516 case ARLDMI: 4517 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4518 case ARLDMICC: 4519 return OPVCC(30, 0, 0, 1) | 3<<2 4520 case ARLDIMI: 4521 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4522 case ARLDIMICC: 4523 return OPVCC(30, 0, 0, 1) | 3<<2 4524 case ARLWNM: 4525 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4526 case ARLWNMCC: 4527 return OPVCC(21, 0, 0, 1) 4528 4529 case ARLDCL: 4530 return OPVCC(30, 0, 0, 0) /* rldicl */ 4531 case ARLDCLCC: 4532 return OPVCC(30, 0, 0, 1) 4533 case ARLDCR: 4534 return OPVCC(30, 1, 0, 0) /* rldicr */ 4535 case ARLDCRCC: 4536 return OPVCC(30, 1, 0, 1) 4537 case ARLDC: 4538 return OPVCC(30, 0, 0, 0) | 2<<2 4539 case ARLDCCC: 4540 return OPVCC(30, 0, 0, 1) | 2<<2 4541 4542 case ASRAW: 4543 return OPVCC(31, 824, 0, 0) 4544 case ASRAWCC: 4545 return OPVCC(31, 824, 0, 1) 4546 case ASRAD: 4547 return OPVCC(31, (413 << 1), 0, 0) 4548 case ASRADCC: 4549 return OPVCC(31, (413 << 1), 0, 1) 4550 4551 case ASTSW: 4552 return OPVCC(31, 725, 0, 0) 4553 4554 case ASUBC: 4555 return OPVCC(8, 0, 0, 0) 4556 4557 case ATW: 4558 return OPVCC(3, 0, 0, 0) 4559 case ATD: 4560 return OPVCC(2, 0, 0, 0) 4561 4562 /* Vector (VMX/Altivec) instructions */ 4563 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4564 /* are enabled starting at POWER6 (ISA 2.05). */ 4565 case AVSPLTB: 4566 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4567 case AVSPLTH: 4568 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4569 case AVSPLTW: 4570 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4571 4572 case AVSPLTISB: 4573 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4574 case AVSPLTISH: 4575 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4576 case AVSPLTISW: 4577 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4578 /* End of vector instructions */ 4579 4580 case AFTDIV: 4581 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4582 case AFTSQRT: 4583 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4584 4585 case AXOR: 4586 return OPVCC(26, 0, 0, 0) /* XORIL */ 4587 case -AXOR: 4588 return OPVCC(27, 0, 0, 0) /* XORIU */ 4589 } 4590 4591 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4592 return 0 4593 } 4594 4595 /* 4596 * load o(a),d 4597 */ 4598 func (c *ctxt9) opload(a obj.As) uint32 { 4599 switch a { 4600 case AMOVD: 4601 return OPVCC(58, 0, 0, 0) /* ld */ 4602 case AMOVDU: 4603 return OPVCC(58, 0, 0, 1) /* ldu */ 4604 case AMOVWZ: 4605 return OPVCC(32, 0, 0, 0) /* lwz */ 4606 case AMOVWZU: 4607 return OPVCC(33, 0, 0, 0) /* lwzu */ 4608 case AMOVW: 4609 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4610 4611 /* no AMOVWU */ 4612 case AMOVB, AMOVBZ: 4613 return OPVCC(34, 0, 0, 0) 4614 /* load */ 4615 4616 case AMOVBU, AMOVBZU: 4617 return OPVCC(35, 0, 0, 0) 4618 case AFMOVD: 4619 return OPVCC(50, 0, 0, 0) 4620 case AFMOVDU: 4621 return OPVCC(51, 0, 0, 0) 4622 case AFMOVS: 4623 return OPVCC(48, 0, 0, 0) 4624 case AFMOVSU: 4625 return OPVCC(49, 0, 0, 0) 4626 case AMOVH: 4627 return OPVCC(42, 0, 0, 0) 4628 case AMOVHU: 4629 return OPVCC(43, 0, 0, 0) 4630 case AMOVHZ: 4631 return OPVCC(40, 0, 0, 0) 4632 case AMOVHZU: 4633 return OPVCC(41, 0, 0, 0) 4634 case AMOVMW: 4635 return OPVCC(46, 0, 0, 0) /* lmw */ 4636 } 4637 4638 c.ctxt.Diag("bad load opcode %v", a) 4639 return 0 4640 } 4641 4642 /* 4643 * indexed load a(b),d 4644 */ 4645 func (c *ctxt9) oploadx(a obj.As) uint32 { 4646 switch a { 4647 case AMOVWZ: 4648 return OPVCC(31, 23, 0, 0) /* lwzx */ 4649 case AMOVWZU: 4650 return OPVCC(31, 55, 0, 0) /* lwzux */ 4651 case AMOVW: 4652 return OPVCC(31, 341, 0, 0) /* lwax */ 4653 case AMOVWU: 4654 return OPVCC(31, 373, 0, 0) /* lwaux */ 4655 4656 case AMOVB, AMOVBZ: 4657 return OPVCC(31, 87, 0, 0) /* lbzx */ 4658 4659 case AMOVBU, AMOVBZU: 4660 return OPVCC(31, 119, 0, 0) /* lbzux */ 4661 case AFMOVD: 4662 return OPVCC(31, 599, 0, 0) /* lfdx */ 4663 case AFMOVDU: 4664 return OPVCC(31, 631, 0, 0) /* lfdux */ 4665 case AFMOVS: 4666 return OPVCC(31, 535, 0, 0) /* lfsx */ 4667 case AFMOVSU: 4668 return OPVCC(31, 567, 0, 0) /* lfsux */ 4669 case AFMOVSX: 4670 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4671 case AFMOVSZ: 4672 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4673 case AMOVH: 4674 return OPVCC(31, 343, 0, 0) /* lhax */ 4675 case AMOVHU: 4676 return OPVCC(31, 375, 0, 0) /* lhaux */ 4677 case AMOVHBR: 4678 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4679 case AMOVWBR: 4680 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4681 case AMOVDBR: 4682 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4683 case AMOVHZ: 4684 return OPVCC(31, 279, 0, 0) /* lhzx */ 4685 case AMOVHZU: 4686 return OPVCC(31, 311, 0, 0) /* lhzux */ 4687 case AECIWX: 4688 return OPVCC(31, 310, 0, 0) /* eciwx */ 4689 case ALBAR: 4690 return OPVCC(31, 52, 0, 0) /* lbarx */ 4691 case ALWAR: 4692 return OPVCC(31, 20, 0, 0) /* lwarx */ 4693 case ALDAR: 4694 return OPVCC(31, 84, 0, 0) 4695 case ALSW: 4696 return OPVCC(31, 533, 0, 0) /* lswx */ 4697 case AMOVD: 4698 return OPVCC(31, 21, 0, 0) /* ldx */ 4699 case AMOVDU: 4700 return OPVCC(31, 53, 0, 0) /* ldux */ 4701 case ALDMX: 4702 return OPVCC(31, 309, 0, 0) /* ldmx */ 4703 4704 /* Vector (VMX/Altivec) instructions */ 4705 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4706 /* are enabled starting at POWER6 (ISA 2.05). */ 4707 case ALVEBX: 4708 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4709 case ALVEHX: 4710 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4711 case ALVEWX: 4712 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4713 case ALVX: 4714 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4715 case ALVXL: 4716 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4717 case ALVSL: 4718 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4719 case ALVSR: 4720 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4721 /* End of vector instructions */ 4722 4723 /* Vector scalar (VSX) instructions */ 4724 /* ISA 2.06 enables these for POWER7. */ 4725 case ALXVD2X: 4726 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4727 case ALXVDSX: 4728 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4729 case ALXVW4X: 4730 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4731 4732 case ALXSDX: 4733 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4734 4735 case ALXSIWAX: 4736 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4737 case ALXSIWZX: 4738 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4739 /* End of vector scalar instructions */ 4740 4741 } 4742 4743 c.ctxt.Diag("bad loadx opcode %v", a) 4744 return 0 4745 } 4746 4747 /* 4748 * store s,o(d) 4749 */ 4750 func (c *ctxt9) opstore(a obj.As) uint32 { 4751 switch a { 4752 case AMOVB, AMOVBZ: 4753 return OPVCC(38, 0, 0, 0) /* stb */ 4754 4755 case AMOVBU, AMOVBZU: 4756 return OPVCC(39, 0, 0, 0) /* stbu */ 4757 case AFMOVD: 4758 return OPVCC(54, 0, 0, 0) /* stfd */ 4759 case AFMOVDU: 4760 return OPVCC(55, 0, 0, 0) /* stfdu */ 4761 case AFMOVS: 4762 return OPVCC(52, 0, 0, 0) /* stfs */ 4763 case AFMOVSU: 4764 return OPVCC(53, 0, 0, 0) /* stfsu */ 4765 4766 case AMOVHZ, AMOVH: 4767 return OPVCC(44, 0, 0, 0) /* sth */ 4768 4769 case AMOVHZU, AMOVHU: 4770 return OPVCC(45, 0, 0, 0) /* sthu */ 4771 case AMOVMW: 4772 return OPVCC(47, 0, 0, 0) /* stmw */ 4773 case ASTSW: 4774 return OPVCC(31, 725, 0, 0) /* stswi */ 4775 4776 case AMOVWZ, AMOVW: 4777 return OPVCC(36, 0, 0, 0) /* stw */ 4778 4779 case AMOVWZU, AMOVWU: 4780 return OPVCC(37, 0, 0, 0) /* stwu */ 4781 case AMOVD: 4782 return OPVCC(62, 0, 0, 0) /* std */ 4783 case AMOVDU: 4784 return OPVCC(62, 0, 0, 1) /* stdu */ 4785 } 4786 4787 c.ctxt.Diag("unknown store opcode %v", a) 4788 return 0 4789 } 4790 4791 /* 4792 * indexed store s,a(b) 4793 */ 4794 func (c *ctxt9) opstorex(a obj.As) uint32 { 4795 switch a { 4796 case AMOVB, AMOVBZ: 4797 return OPVCC(31, 215, 0, 0) /* stbx */ 4798 4799 case AMOVBU, AMOVBZU: 4800 return OPVCC(31, 247, 0, 0) /* stbux */ 4801 case AFMOVD: 4802 return OPVCC(31, 727, 0, 0) /* stfdx */ 4803 case AFMOVDU: 4804 return OPVCC(31, 759, 0, 0) /* stfdux */ 4805 case AFMOVS: 4806 return OPVCC(31, 663, 0, 0) /* stfsx */ 4807 case AFMOVSU: 4808 return OPVCC(31, 695, 0, 0) /* stfsux */ 4809 case AFMOVSX: 4810 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4811 4812 case AMOVHZ, AMOVH: 4813 return OPVCC(31, 407, 0, 0) /* sthx */ 4814 case AMOVHBR: 4815 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4816 4817 case AMOVHZU, AMOVHU: 4818 return OPVCC(31, 439, 0, 0) /* sthux */ 4819 4820 case AMOVWZ, AMOVW: 4821 return OPVCC(31, 151, 0, 0) /* stwx */ 4822 4823 case AMOVWZU, AMOVWU: 4824 return OPVCC(31, 183, 0, 0) /* stwux */ 4825 case ASTSW: 4826 return OPVCC(31, 661, 0, 0) /* stswx */ 4827 case AMOVWBR: 4828 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4829 case ASTBCCC: 4830 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4831 case ASTWCCC: 4832 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4833 case ASTDCCC: 4834 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4835 case AECOWX: 4836 return OPVCC(31, 438, 0, 0) /* ecowx */ 4837 case AMOVD: 4838 return OPVCC(31, 149, 0, 0) /* stdx */ 4839 case AMOVDU: 4840 return OPVCC(31, 181, 0, 0) /* stdux */ 4841 4842 /* Vector (VMX/Altivec) instructions */ 4843 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4844 /* are enabled starting at POWER6 (ISA 2.05). */ 4845 case ASTVEBX: 4846 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4847 case ASTVEHX: 4848 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4849 case ASTVEWX: 4850 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4851 case ASTVX: 4852 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4853 case ASTVXL: 4854 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4855 /* End of vector instructions */ 4856 4857 /* Vector scalar (VSX) instructions */ 4858 /* ISA 2.06 enables these for POWER7. */ 4859 case ASTXVD2X: 4860 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4861 case ASTXVW4X: 4862 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4863 4864 case ASTXSDX: 4865 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4866 4867 case ASTXSIWX: 4868 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4869 /* End of vector scalar instructions */ 4870 4871 } 4872 4873 c.ctxt.Diag("unknown storex opcode %v", a) 4874 return 0 4875 }