github.com/euank/go@v0.0.0-20160829210321-495514729181/src/cmd/compile/internal/ssa/gen/386Ops.go (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // +build ignore 6 7 package main 8 9 import "strings" 10 11 // Notes: 12 // - Integer types live in the low portion of registers. Upper portions are junk. 13 // - Boolean types use the low-order byte of a register. 0=false, 1=true. 14 // Upper bytes are junk. 15 // - Floating-point types live in the low natural slot of an sse2 register. 16 // Unused portions are junk. 17 // - We do not use AH,BH,CH,DH registers. 18 // - When doing sub-register operations, we try to write the whole 19 // destination register to avoid a partial-register write. 20 // - Unused portions of AuxInt (or the Val portion of ValAndOff) are 21 // filled by sign-extending the used portion. Users of AuxInt which interpret 22 // AuxInt as unsigned (e.g. shifts) must be careful. 23 24 // Suffixes encode the bit width of various instructions. 25 // L (long word) = 32 bit 26 // W (word) = 16 bit 27 // B (byte) = 8 bit 28 29 // copied from ../../x86/reg.go 30 var regNames386 = []string{ 31 "AX", 32 "CX", 33 "DX", 34 "BX", 35 "SP", 36 "BP", 37 "SI", 38 "DI", 39 "X0", 40 "X1", 41 "X2", 42 "X3", 43 "X4", 44 "X5", 45 "X6", 46 "X7", 47 48 // pseudo-registers 49 "SB", 50 } 51 52 // Notes on 387 support. 53 // - The 387 has a weird stack-register setup for floating-point registers. 54 // We use these registers when SSE registers are not available (when GO386=387). 55 // - We use the same register names (X0-X7) but they refer to the 387 56 // floating-point registers. That way, most of the SSA backend is unchanged. 57 // - The instruction generation pass maintains an SSE->387 register mapping. 58 // This mapping is updated whenever the FP stack is pushed or popped so that 59 // we can always find a given SSE register even when the TOS pointer has changed. 60 // - To facilitate the mapping from SSE to 387, we enforce that 61 // every basic block starts and ends with an empty floating-point stack. 62 63 func init() { 64 // Make map from reg names to reg integers. 65 if len(regNames386) > 64 { 66 panic("too many registers") 67 } 68 num := map[string]int{} 69 for i, name := range regNames386 { 70 num[name] = i 71 } 72 buildReg := func(s string) regMask { 73 m := regMask(0) 74 for _, r := range strings.Split(s, " ") { 75 if n, ok := num[r]; ok { 76 m |= regMask(1) << uint(n) 77 continue 78 } 79 panic("register " + r + " not found") 80 } 81 return m 82 } 83 84 // Common individual register masks 85 var ( 86 ax = buildReg("AX") 87 cx = buildReg("CX") 88 dx = buildReg("DX") 89 gp = buildReg("AX CX DX BX BP SI DI") 90 fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7") 91 x7 = buildReg("X7") 92 gpsp = gp | buildReg("SP") 93 gpspsb = gpsp | buildReg("SB") 94 callerSave = gp | fp 95 ) 96 // Common slices of register masks 97 var ( 98 gponly = []regMask{gp} 99 fponly = []regMask{fp} 100 ) 101 102 // Common regInfo 103 var ( 104 gp01 = regInfo{inputs: nil, outputs: gponly} 105 gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly} 106 gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly} 107 gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly} 108 gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} 109 gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp, 0}} 110 gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp, 0}} 111 gp1carry1 = regInfo{inputs: []regMask{gp}, outputs: gponly} 112 gp2carry1 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly} 113 gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly} 114 gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly} 115 gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}} 116 gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax}, clobbers: dx} 117 gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx}, clobbers: ax} 118 gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx}, clobbers: ax} 119 gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}} 120 121 gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}} 122 gp1flags = regInfo{inputs: []regMask{gpsp}} 123 flagsgp = regInfo{inputs: nil, outputs: gponly} 124 125 readflags = regInfo{inputs: nil, outputs: gponly} 126 flagsgpax = regInfo{inputs: nil, clobbers: ax, outputs: []regMask{gp &^ ax}} 127 128 gpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: gponly} 129 gploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: gponly} 130 131 gpstore = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} 132 gpstoreconst = regInfo{inputs: []regMask{gpspsb, 0}} 133 gpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, gpsp, 0}} 134 gpstoreconstidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}} 135 136 fp01 = regInfo{inputs: nil, outputs: fponly} 137 fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly} 138 fp21x7 = regInfo{inputs: []regMask{fp &^ x7, fp &^ x7}, 139 clobbers: x7, outputs: []regMask{fp &^ x7}} 140 fpgp = regInfo{inputs: fponly, outputs: gponly} 141 gpfp = regInfo{inputs: gponly, outputs: fponly} 142 fp11 = regInfo{inputs: fponly, outputs: fponly} 143 fp2flags = regInfo{inputs: []regMask{fp, fp}} 144 145 fpload = regInfo{inputs: []regMask{gpspsb, 0}, outputs: fponly} 146 fploadidx = regInfo{inputs: []regMask{gpspsb, gpsp, 0}, outputs: fponly} 147 148 fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}} 149 fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}} 150 ) 151 152 var _386ops = []opData{ 153 // fp ops 154 {name: "ADDSS", argLength: 2, reg: fp21, asm: "ADDSS", commutative: true, resultInArg0: true}, // fp32 add 155 {name: "ADDSD", argLength: 2, reg: fp21, asm: "ADDSD", commutative: true, resultInArg0: true}, // fp64 add 156 {name: "SUBSS", argLength: 2, reg: fp21x7, asm: "SUBSS", resultInArg0: true}, // fp32 sub 157 {name: "SUBSD", argLength: 2, reg: fp21x7, asm: "SUBSD", resultInArg0: true}, // fp64 sub 158 {name: "MULSS", argLength: 2, reg: fp21, asm: "MULSS", commutative: true, resultInArg0: true}, // fp32 mul 159 {name: "MULSD", argLength: 2, reg: fp21, asm: "MULSD", commutative: true, resultInArg0: true}, // fp64 mul 160 {name: "DIVSS", argLength: 2, reg: fp21x7, asm: "DIVSS", resultInArg0: true}, // fp32 div 161 {name: "DIVSD", argLength: 2, reg: fp21x7, asm: "DIVSD", resultInArg0: true}, // fp64 div 162 163 {name: "MOVSSload", argLength: 2, reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load 164 {name: "MOVSDload", argLength: 2, reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load 165 {name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float32", rematerializeable: true}, // fp32 constant 166 {name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float64", rematerializeable: true}, // fp64 constant 167 {name: "MOVSSloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff"}, // fp32 load indexed by i 168 {name: "MOVSSloadidx4", argLength: 3, reg: fploadidx, asm: "MOVSS", aux: "SymOff"}, // fp32 load indexed by 4*i 169 {name: "MOVSDloadidx1", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff"}, // fp64 load indexed by i 170 {name: "MOVSDloadidx8", argLength: 3, reg: fploadidx, asm: "MOVSD", aux: "SymOff"}, // fp64 load indexed by 8*i 171 172 {name: "MOVSSstore", argLength: 3, reg: fpstore, asm: "MOVSS", aux: "SymOff"}, // fp32 store 173 {name: "MOVSDstore", argLength: 3, reg: fpstore, asm: "MOVSD", aux: "SymOff"}, // fp64 store 174 {name: "MOVSSstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff"}, // fp32 indexed by i store 175 {name: "MOVSSstoreidx4", argLength: 4, reg: fpstoreidx, asm: "MOVSS", aux: "SymOff"}, // fp32 indexed by 4i store 176 {name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by i store 177 {name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store 178 179 // binary ops 180 {name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1 181 {name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32", clobberFlags: true}, // arg0 + auxint 182 183 {name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1, generates <carry,result> pair 184 {name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates <carry,result> pair 185 {name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0+arg1+carry(arg2), where arg2 is flags 186 {name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0+auxint+carry(arg1), where arg1 is flags 187 188 {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, // arg0 - arg1 189 {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint 190 191 {name: "SUBLcarry", argLength: 2, reg: gp21carry, asm: "SUBL", resultInArg0: true}, // arg0-arg1, generates <borrow,result> pair 192 {name: "SUBLconstcarry", argLength: 1, reg: gp11carry, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0-auxint, generates <borrow,result> pair 193 {name: "SBBL", argLength: 3, reg: gp2carry1, asm: "SBBL", resultInArg0: true, clobberFlags: true}, // arg0-arg1-borrow(arg2), where arg2 is flags 194 {name: "SBBLconst", argLength: 2, reg: gp1carry1, asm: "SBBL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0-auxint-borrow(arg1), where arg1 is flags 195 196 {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1 197 {name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 * auxint 198 199 {name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL", clobberFlags: true}, // (arg0 * arg1) >> width 200 {name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL", clobberFlags: true}, // (arg0 * arg1) >> width 201 {name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW", clobberFlags: true}, // (arg0 * arg1) >> width 202 {name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB", clobberFlags: true}, // (arg0 * arg1) >> width 203 {name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW", clobberFlags: true}, // (arg0 * arg1) >> width 204 {name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB", clobberFlags: true}, // (arg0 * arg1) >> width 205 206 {name: "MULLQU", argLength: 2, reg: gp21mul, asm: "MULL", clobberFlags: true}, // arg0 * arg1, high 32 in result[0], low 32 in result[1] 207 208 {name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL", clobberFlags: true}, // arg0 / arg1 209 {name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW", clobberFlags: true}, // arg0 / arg1 210 {name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL", clobberFlags: true}, // arg0 / arg1 211 {name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW", clobberFlags: true}, // arg0 / arg1 212 213 {name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL", clobberFlags: true}, // arg0 % arg1 214 {name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW", clobberFlags: true}, // arg0 % arg1 215 {name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL", clobberFlags: true}, // arg0 % arg1 216 {name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW", clobberFlags: true}, // arg0 % arg1 217 218 {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 & arg1 219 {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint 220 221 {name: "ORL", argLength: 2, reg: gp21, asm: "ORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 | arg1 222 {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint 223 224 {name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1 225 {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint 226 227 {name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1 228 {name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1 229 {name: "CMPB", argLength: 2, reg: gp2flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to arg1 230 {name: "CMPLconst", argLength: 1, reg: gp1flags, asm: "CMPL", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint 231 {name: "CMPWconst", argLength: 1, reg: gp1flags, asm: "CMPW", typ: "Flags", aux: "Int16"}, // arg0 compare to auxint 232 {name: "CMPBconst", argLength: 1, reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint 233 234 {name: "UCOMISS", argLength: 2, reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32 235 {name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64 236 237 {name: "TESTL", argLength: 2, reg: gp2flags, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0 238 {name: "TESTW", argLength: 2, reg: gp2flags, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0 239 {name: "TESTB", argLength: 2, reg: gp2flags, asm: "TESTB", typ: "Flags"}, // (arg0 & arg1) compare to 0 240 {name: "TESTLconst", argLength: 1, reg: gp1flags, asm: "TESTL", typ: "Flags", aux: "Int32"}, // (arg0 & auxint) compare to 0 241 {name: "TESTWconst", argLength: 1, reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0 242 {name: "TESTBconst", argLength: 1, reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0 243 244 {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL", resultInArg0: true, clobberFlags: true}, // arg0 << arg1, shift amount is mod 32 245 {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 << auxint, shift amount 0-31 246 // Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount! 247 248 {name: "SHRL", argLength: 2, reg: gp21shift, asm: "SHRL", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 249 {name: "SHRW", argLength: 2, reg: gp21shift, asm: "SHRW", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 250 {name: "SHRB", argLength: 2, reg: gp21shift, asm: "SHRB", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> arg1, shift amount is mod 32 251 {name: "SHRLconst", argLength: 1, reg: gp11, asm: "SHRL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31 252 {name: "SHRWconst", argLength: 1, reg: gp11, asm: "SHRW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31 253 {name: "SHRBconst", argLength: 1, reg: gp11, asm: "SHRB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // unsigned arg0 >> auxint, shift amount 0-31 254 255 {name: "SARL", argLength: 2, reg: gp21shift, asm: "SARL", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 256 {name: "SARW", argLength: 2, reg: gp21shift, asm: "SARW", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 257 {name: "SARB", argLength: 2, reg: gp21shift, asm: "SARB", resultInArg0: true, clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32 258 {name: "SARLconst", argLength: 1, reg: gp11, asm: "SARL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31 259 {name: "SARWconst", argLength: 1, reg: gp11, asm: "SARW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31 260 {name: "SARBconst", argLength: 1, reg: gp11, asm: "SARB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31 261 262 {name: "ROLLconst", argLength: 1, reg: gp11, asm: "ROLL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-31 263 {name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15 264 {name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7 265 266 // unary ops 267 {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true}, // -arg0 268 269 {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL", resultInArg0: true, clobberFlags: true}, // ^arg0 270 271 {name: "BSFL", argLength: 1, reg: gp11, asm: "BSFL", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero 272 {name: "BSFW", argLength: 1, reg: gp11, asm: "BSFW", clobberFlags: true}, // arg0 # of low-order zeroes ; undef if zero 273 274 {name: "BSRL", argLength: 1, reg: gp11, asm: "BSRL", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero 275 {name: "BSRW", argLength: 1, reg: gp11, asm: "BSRW", clobberFlags: true}, // arg0 # of high-order zeroes ; undef if zero 276 277 {name: "BSWAPL", argLength: 1, reg: gp11, asm: "BSWAPL", resultInArg0: true, clobberFlags: true}, // arg0 swap bytes 278 279 {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0) 280 281 {name: "SBBLcarrymask", argLength: 1, reg: flagsgp, asm: "SBBL"}, // (int32)(-1) if carry is set, 0 if carry is clear. 282 // Note: SBBW and SBBB are subsumed by SBBL 283 284 {name: "SETEQ", argLength: 1, reg: readflags, asm: "SETEQ"}, // extract == condition from arg0 285 {name: "SETNE", argLength: 1, reg: readflags, asm: "SETNE"}, // extract != condition from arg0 286 {name: "SETL", argLength: 1, reg: readflags, asm: "SETLT"}, // extract signed < condition from arg0 287 {name: "SETLE", argLength: 1, reg: readflags, asm: "SETLE"}, // extract signed <= condition from arg0 288 {name: "SETG", argLength: 1, reg: readflags, asm: "SETGT"}, // extract signed > condition from arg0 289 {name: "SETGE", argLength: 1, reg: readflags, asm: "SETGE"}, // extract signed >= condition from arg0 290 {name: "SETB", argLength: 1, reg: readflags, asm: "SETCS"}, // extract unsigned < condition from arg0 291 {name: "SETBE", argLength: 1, reg: readflags, asm: "SETLS"}, // extract unsigned <= condition from arg0 292 {name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0 293 {name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0 294 // Need different opcodes for floating point conditions because 295 // any comparison involving a NaN is always FALSE and thus 296 // the patterns for inverting conditions cannot be used. 297 {name: "SETEQF", argLength: 1, reg: flagsgpax, asm: "SETEQ", clobberFlags: true}, // extract == condition from arg0 298 {name: "SETNEF", argLength: 1, reg: flagsgpax, asm: "SETNE", clobberFlags: true}, // extract != condition from arg0 299 {name: "SETORD", argLength: 1, reg: flagsgp, asm: "SETPC"}, // extract "ordered" (No Nan present) condition from arg0 300 {name: "SETNAN", argLength: 1, reg: flagsgp, asm: "SETPS"}, // extract "unordered" (Nan present) condition from arg0 301 302 {name: "SETGF", argLength: 1, reg: flagsgp, asm: "SETHI"}, // extract floating > condition from arg0 303 {name: "SETGEF", argLength: 1, reg: flagsgp, asm: "SETCC"}, // extract floating >= condition from arg0 304 305 {name: "MOVBLSX", argLength: 1, reg: gp11, asm: "MOVBLSX"}, // sign extend arg0 from int8 to int32 306 {name: "MOVBLZX", argLength: 1, reg: gp11, asm: "MOVBLZX"}, // zero extend arg0 from int8 to int32 307 {name: "MOVWLSX", argLength: 1, reg: gp11, asm: "MOVWLSX"}, // sign extend arg0 from int16 to int32 308 {name: "MOVWLZX", argLength: 1, reg: gp11, asm: "MOVWLZX"}, // zero extend arg0 from int16 to int32 309 310 {name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint 311 312 {name: "CVTTSD2SL", argLength: 1, reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32 313 {name: "CVTTSS2SL", argLength: 1, reg: fpgp, asm: "CVTTSS2SL"}, // convert float32 to int32 314 {name: "CVTSL2SS", argLength: 1, reg: gpfp, asm: "CVTSL2SS"}, // convert int32 to float32 315 {name: "CVTSL2SD", argLength: 1, reg: gpfp, asm: "CVTSL2SD"}, // convert int32 to float64 316 {name: "CVTSD2SS", argLength: 1, reg: fp11, asm: "CVTSD2SS"}, // convert float64 to float32 317 {name: "CVTSS2SD", argLength: 1, reg: fp11, asm: "CVTSS2SD"}, // convert float32 to float64 318 319 {name: "PXOR", argLength: 2, reg: fp21, asm: "PXOR", commutative: true, resultInArg0: true}, // exclusive or, applied to X regs for float negation. 320 321 {name: "LEAL", argLength: 1, reg: gp11sb, aux: "SymOff", rematerializeable: true}, // arg0 + auxint + offset encoded in aux 322 {name: "LEAL1", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + arg1 + auxint + aux 323 {name: "LEAL2", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 2*arg1 + auxint + aux 324 {name: "LEAL4", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 4*arg1 + auxint + aux 325 {name: "LEAL8", argLength: 2, reg: gp21sb, aux: "SymOff"}, // arg0 + 8*arg1 + auxint + aux 326 // Note: LEAL{1,2,4,8} must not have OpSB as either argument. 327 328 // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address 329 {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend. 330 {name: "MOVBLSXload", argLength: 2, reg: gpload, asm: "MOVBLSX", aux: "SymOff"}, // ditto, sign extend to int32 331 {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend. 332 {name: "MOVWLSXload", argLength: 2, reg: gpload, asm: "MOVWLSX", aux: "SymOff"}, // ditto, sign extend to int32 333 {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend. 334 {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem 335 {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem 336 {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem 337 338 // indexed loads/stores 339 {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVBLZX", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem 340 {name: "MOVWloadidx1", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem 341 {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem 342 {name: "MOVLloadidx1", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem 343 {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem 344 // TODO: sign-extending indexed loads 345 {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem 346 {name: "MOVWstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem 347 {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem 348 {name: "MOVLstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff"}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem 349 {name: "MOVLstoreidx4", argLength: 4, reg: gpstoreidx, asm: "MOVL", aux: "SymOff"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem 350 // TODO: add size-mismatched indexed loads, like MOVBstoreidx4. 351 352 // For storeconst ops, the AuxInt field encodes both 353 // the value to store and an address offset of the store. 354 // Cast AuxInt to a ValAndOff to extract Val and Off fields. 355 {name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem 356 {name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... 357 {name: "MOVLstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... 358 359 {name: "MOVBstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+1*arg1+ValAndOff(AuxInt).Off()+aux. arg2=mem 360 {name: "MOVWstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... arg1 ... 361 {name: "MOVWstoreconstidx2", argLength: 3, reg: gpstoreconstidx, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ... 2*arg1 ... 362 {name: "MOVLstoreconstidx1", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... arg1 ... 363 {name: "MOVLstoreconstidx4", argLength: 3, reg: gpstoreconstidx, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ... 4*arg1 ... 364 365 // arg0 = pointer to start of memory to zero 366 // arg1 = value to store (will always be zero) 367 // arg2 = mem 368 // auxint = offset into duffzero code to start executing 369 // returns mem 370 { 371 name: "DUFFZERO", 372 aux: "Int64", 373 argLength: 3, 374 reg: regInfo{ 375 inputs: []regMask{buildReg("DI"), buildReg("AX")}, 376 clobbers: buildReg("DI CX"), 377 // Note: CX is only clobbered when dynamic linking. 378 }, 379 }, 380 381 // arg0 = address of memory to zero 382 // arg1 = # of 4-byte words to zero 383 // arg2 = value to store (will always be zero) 384 // arg3 = mem 385 // returns mem 386 { 387 name: "REPSTOSL", 388 argLength: 4, 389 reg: regInfo{ 390 inputs: []regMask{buildReg("DI"), buildReg("CX"), buildReg("AX")}, 391 clobbers: buildReg("DI CX"), 392 }, 393 }, 394 395 {name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem 396 {name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("DX"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem 397 {name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem 398 {name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call newproc. arg0=mem, auxint=argsize, returns mem 399 {name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64", clobberFlags: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem 400 401 // arg0 = destination pointer 402 // arg1 = source pointer 403 // arg2 = mem 404 // auxint = offset from duffcopy symbol to call 405 // returns memory 406 { 407 name: "DUFFCOPY", 408 aux: "Int64", 409 argLength: 3, 410 reg: regInfo{ 411 inputs: []regMask{buildReg("DI"), buildReg("SI")}, 412 clobbers: buildReg("DI SI CX"), // uses CX as a temporary 413 }, 414 clobberFlags: true, 415 }, 416 417 // arg0 = destination pointer 418 // arg1 = source pointer 419 // arg2 = # of 8-byte words to copy 420 // arg3 = mem 421 // returns memory 422 { 423 name: "REPMOVSL", 424 argLength: 4, 425 reg: regInfo{ 426 inputs: []regMask{buildReg("DI"), buildReg("SI"), buildReg("CX")}, 427 clobbers: buildReg("DI SI CX"), 428 }, 429 }, 430 431 // (InvertFlags (CMPL a b)) == (CMPL b a) 432 // So if we want (SETL (CMPL a b)) but we can't do that because a is a constant, 433 // then we do (SETL (InvertFlags (CMPL b a))) instead. 434 // Rewrites will convert this to (SETG (CMPL b a)). 435 // InvertFlags is a pseudo-op which can't appear in assembly output. 436 {name: "InvertFlags", argLength: 1}, // reverse direction of arg0 437 438 // Pseudo-ops 439 {name: "LoweredGetG", argLength: 1, reg: gp01}, // arg0=mem 440 // Scheduler ensures LoweredGetClosurePtr occurs only in entry block, 441 // and sorts it to the very beginning of the block to prevent other 442 // use of DX (the closure pointer) 443 {name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("DX")}}}, 444 //arg0=ptr,arg1=mem, returns void. Faults if ptr is nil. 445 {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}}, clobberFlags: true}, 446 447 // MOVLconvert converts between pointers and integers. 448 // We have a special op for this so as to not confuse GC 449 // (particularly stack maps). It takes a memory arg so it 450 // gets correctly ordered with respect to GC safepoints. 451 // arg0=ptr/int arg1=mem, output=int/ptr 452 {name: "MOVLconvert", argLength: 2, reg: gp11, asm: "MOVL"}, 453 454 // Constant flag values. For any comparison, there are 5 possible 455 // outcomes: the three from the signed total order (<,==,>) and the 456 // three from the unsigned total order. The == cases overlap. 457 // Note: there's a sixth "unordered" outcome for floating-point 458 // comparisons, but we don't use such a beast yet. 459 // These ops are for temporary use by rewrite rules. They 460 // cannot appear in the generated assembly. 461 {name: "FlagEQ"}, // equal 462 {name: "FlagLT_ULT"}, // signed < and unsigned < 463 {name: "FlagLT_UGT"}, // signed < and unsigned > 464 {name: "FlagGT_UGT"}, // signed > and unsigned < 465 {name: "FlagGT_ULT"}, // signed > and unsigned > 466 467 // Special op for -x on 387 468 {name: "FCHS", argLength: 1, reg: fp11}, 469 470 // Special ops for PIC floating-point constants. 471 // MOVSXconst1 loads the address of the constant-pool entry into a register. 472 // MOVSXconst2 loads the constant from that address. 473 // MOVSXconst1 returns a pointer, but we type it as uint32 because it can never point to the Go heap. 474 {name: "MOVSSconst1", reg: gp01, typ: "UInt32", aux: "Float32"}, 475 {name: "MOVSDconst1", reg: gp01, typ: "UInt32", aux: "Float64"}, 476 {name: "MOVSSconst2", argLength: 1, reg: gpfp, asm: "MOVSS"}, 477 {name: "MOVSDconst2", argLength: 1, reg: gpfp, asm: "MOVSD"}, 478 } 479 480 var _386blocks = []blockData{ 481 {name: "EQ"}, 482 {name: "NE"}, 483 {name: "LT"}, 484 {name: "LE"}, 485 {name: "GT"}, 486 {name: "GE"}, 487 {name: "ULT"}, 488 {name: "ULE"}, 489 {name: "UGT"}, 490 {name: "UGE"}, 491 {name: "EQF"}, 492 {name: "NEF"}, 493 {name: "ORD"}, // FP, ordered comparison (parity zero) 494 {name: "NAN"}, // FP, unordered comparison (parity one) 495 } 496 497 archs = append(archs, arch{ 498 name: "386", 499 pkg: "cmd/internal/obj/x86", 500 genfile: "../../x86/ssa.go", 501 ops: _386ops, 502 blocks: _386blocks, 503 regnames: regNames386, 504 gpregmask: gp, 505 fpregmask: fp, 506 framepointerreg: int8(num["BP"]), 507 }) 508 }