github.com/euank/go@v0.0.0-20160829210321-495514729181/src/cmd/compile/internal/ssa/gen/MIPS64.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 (AddPtr x y) -> (ADDV x y) 6 (Add64 x y) -> (ADDV x y) 7 (Add32 x y) -> (ADDV x y) 8 (Add16 x y) -> (ADDV x y) 9 (Add8 x y) -> (ADDV x y) 10 (Add32F x y) -> (ADDF x y) 11 (Add64F x y) -> (ADDD x y) 12 13 (SubPtr x y) -> (SUBV x y) 14 (Sub64 x y) -> (SUBV x y) 15 (Sub32 x y) -> (SUBV x y) 16 (Sub16 x y) -> (SUBV x y) 17 (Sub8 x y) -> (SUBV x y) 18 (Sub32F x y) -> (SUBF x y) 19 (Sub64F x y) -> (SUBD x y) 20 21 (Mul64 x y) -> (Select1 (MULVU x y)) 22 (Mul32 x y) -> (Select1 (MULVU x y)) 23 (Mul16 x y) -> (Select1 (MULVU x y)) 24 (Mul8 x y) -> (Select1 (MULVU x y)) 25 (Mul32F x y) -> (MULF x y) 26 (Mul64F x y) -> (MULD x y) 27 28 (Hmul64 x y) -> (Select0 (MULV x y)) 29 (Hmul64u x y) -> (Select0 (MULVU x y)) 30 (Hmul32 x y) -> (SRAVconst (Select1 <config.fe.TypeInt64()> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32]) 31 (Hmul32u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt64()> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32]) 32 (Hmul16 x y) -> (SRAVconst (Select1 <config.fe.TypeInt32()> (MULV (SignExt16to64 x) (SignExt16to64 y))) [16]) 33 (Hmul16u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt32()> (MULVU (ZeroExt16to64 x) (ZeroExt16to64 y))) [16]) 34 (Hmul8 x y) -> (SRAVconst (Select1 <config.fe.TypeInt16()> (MULV (SignExt8to64 x) (SignExt8to64 y))) [8]) 35 (Hmul8u x y) -> (SRLVconst (Select1 <config.fe.TypeUInt16()> (MULVU (ZeroExt8to64 x) (ZeroExt8to64 y))) [8]) 36 37 (Div64 x y) -> (Select1 (DIVV x y)) 38 (Div64u x y) -> (Select1 (DIVVU x y)) 39 (Div32 x y) -> (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 40 (Div32u x y) -> (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 41 (Div16 x y) -> (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 42 (Div16u x y) -> (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 43 (Div8 x y) -> (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 44 (Div8u x y) -> (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 45 (Div32F x y) -> (DIVF x y) 46 (Div64F x y) -> (DIVD x y) 47 48 (Mod64 x y) -> (Select0 (DIVV x y)) 49 (Mod64u x y) -> (Select0 (DIVVU x y)) 50 (Mod32 x y) -> (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y))) 51 (Mod32u x y) -> (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) 52 (Mod16 x y) -> (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y))) 53 (Mod16u x y) -> (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) 54 (Mod8 x y) -> (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y))) 55 (Mod8u x y) -> (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))) 56 57 (Avg64u <t> x y) -> (ADDV (ADDV <t> (SRLVconst <t> x [1]) (SRLVconst <t> y [1])) (AND <t> (AND <t> x y) (MOVVconst [1]))) 58 59 (And64 x y) -> (AND x y) 60 (And32 x y) -> (AND x y) 61 (And16 x y) -> (AND x y) 62 (And8 x y) -> (AND x y) 63 64 (Or64 x y) -> (OR x y) 65 (Or32 x y) -> (OR x y) 66 (Or16 x y) -> (OR x y) 67 (Or8 x y) -> (OR x y) 68 69 (Xor64 x y) -> (XOR x y) 70 (Xor32 x y) -> (XOR x y) 71 (Xor16 x y) -> (XOR x y) 72 (Xor8 x y) -> (XOR x y) 73 74 // shifts 75 // hardware instruction uses only the low 6 bits of the shift 76 // we compare to 64 to ensure Go semantics for large shifts 77 (Lsh64x64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SLLV <t> x y)) 78 (Lsh64x32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 79 (Lsh64x16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 80 (Lsh64x8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 81 82 (Lsh32x64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SLLV <t> x y)) 83 (Lsh32x32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 84 (Lsh32x16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 85 (Lsh32x8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 86 87 (Lsh16x64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SLLV <t> x y)) 88 (Lsh16x32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 89 (Lsh16x16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 90 (Lsh16x8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 91 92 (Lsh8x64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SLLV <t> x y)) 93 (Lsh8x32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y))) 94 (Lsh8x16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y))) 95 (Lsh8x8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y))) 96 97 (Rsh64Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SRLV <t> x y)) 98 (Rsh64Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y))) 99 (Rsh64Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y))) 100 (Rsh64Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y))) 101 102 (Rsh32Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y)) 103 (Rsh32Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y))) 104 (Rsh32Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y))) 105 (Rsh32Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y))) 106 107 (Rsh16Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y)) 108 (Rsh16Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y))) 109 (Rsh16Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y))) 110 (Rsh16Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y))) 111 112 (Rsh8Ux64 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y)) 113 (Rsh8Ux32 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y))) 114 (Rsh8Ux16 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y))) 115 (Rsh8Ux8 <t> x y) -> (AND (NEGV <t> (SGTU (Const64 <config.fe.TypeUInt64()> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y))) 116 117 (Rsh64x64 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU y (Const64 <config.fe.TypeUInt64()> [63]))) y)) 118 (Rsh64x32 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt32to64 y))) 119 (Rsh64x16 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt16to64 y))) 120 (Rsh64x8 <t> x y) -> (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt8to64 y))) 121 122 (Rsh32x64 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (Const64 <config.fe.TypeUInt64()> [63]))) y)) 123 (Rsh32x32 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt32to64 y))) 124 (Rsh32x16 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt16to64 y))) 125 (Rsh32x8 <t> x y) -> (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt8to64 y))) 126 127 (Rsh16x64 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (Const64 <config.fe.TypeUInt64()> [63]))) y)) 128 (Rsh16x32 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt32to64 y))) 129 (Rsh16x16 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt16to64 y))) 130 (Rsh16x8 <t> x y) -> (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt8to64 y))) 131 132 (Rsh8x64 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (Const64 <config.fe.TypeUInt64()> [63]))) y)) 133 (Rsh8x32 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt32to64 y))) 134 (Rsh8x16 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt16to64 y))) 135 (Rsh8x8 <t> x y) -> (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (Const64 <config.fe.TypeUInt64()> [63]))) (ZeroExt8to64 y))) 136 137 // unary ops 138 (Neg64 x) -> (NEGV x) 139 (Neg32 x) -> (NEGV x) 140 (Neg16 x) -> (NEGV x) 141 (Neg8 x) -> (NEGV x) 142 (Neg32F x) -> (NEGF x) 143 (Neg64F x) -> (NEGD x) 144 145 (Com64 x) -> (NOR (MOVVconst [0]) x) 146 (Com32 x) -> (NOR (MOVVconst [0]) x) 147 (Com16 x) -> (NOR (MOVVconst [0]) x) 148 (Com8 x) -> (NOR (MOVVconst [0]) x) 149 150 // boolean ops -- booleans are represented with 0=false, 1=true 151 (AndB x y) -> (AND x y) 152 (OrB x y) -> (OR x y) 153 (EqB x y) -> (XOR (MOVVconst [1]) (XOR <config.fe.TypeBool()> x y)) 154 (NeqB x y) -> (XOR x y) 155 (Not x) -> (XOR (MOVVconst [1]) x) 156 157 // constants 158 (Const64 [val]) -> (MOVVconst [val]) 159 (Const32 [val]) -> (MOVVconst [val]) 160 (Const16 [val]) -> (MOVVconst [val]) 161 (Const8 [val]) -> (MOVVconst [val]) 162 (Const32F [val]) -> (MOVFconst [val]) 163 (Const64F [val]) -> (MOVDconst [val]) 164 (ConstNil) -> (MOVVconst [0]) 165 (ConstBool [b]) -> (MOVVconst [b]) 166 167 // truncations 168 // Because we ignore high parts of registers, truncates are just copies. 169 (Trunc16to8 x) -> x 170 (Trunc32to8 x) -> x 171 (Trunc32to16 x) -> x 172 (Trunc64to8 x) -> x 173 (Trunc64to16 x) -> x 174 (Trunc64to32 x) -> x 175 176 // Zero-/Sign-extensions 177 (ZeroExt8to16 x) -> (MOVBUreg x) 178 (ZeroExt8to32 x) -> (MOVBUreg x) 179 (ZeroExt16to32 x) -> (MOVHUreg x) 180 (ZeroExt8to64 x) -> (MOVBUreg x) 181 (ZeroExt16to64 x) -> (MOVHUreg x) 182 (ZeroExt32to64 x) -> (MOVWUreg x) 183 184 (SignExt8to16 x) -> (MOVBreg x) 185 (SignExt8to32 x) -> (MOVBreg x) 186 (SignExt16to32 x) -> (MOVHreg x) 187 (SignExt8to64 x) -> (MOVBreg x) 188 (SignExt16to64 x) -> (MOVHreg x) 189 (SignExt32to64 x) -> (MOVWreg x) 190 191 // float <-> int conversion 192 (Cvt32to32F x) -> (MOVWF x) 193 (Cvt32to64F x) -> (MOVWD x) 194 (Cvt64to32F x) -> (MOVVF x) 195 (Cvt64to64F x) -> (MOVVD x) 196 (Cvt32Fto32 x) -> (TRUNCFW x) 197 (Cvt64Fto32 x) -> (TRUNCDW x) 198 (Cvt32Fto64 x) -> (TRUNCFV x) 199 (Cvt64Fto64 x) -> (TRUNCDV x) 200 (Cvt32Fto64F x) -> (MOVFD x) 201 (Cvt64Fto32F x) -> (MOVDF x) 202 203 // comparisons 204 (Eq8 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y))) 205 (Eq16 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y))) 206 (Eq32 x y) -> (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y))) 207 (Eq64 x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 208 (EqPtr x y) -> (SGTU (MOVVconst [1]) (XOR x y)) 209 (Eq32F x y) -> (FPFlagTrue (CMPEQF x y)) 210 (Eq64F x y) -> (FPFlagTrue (CMPEQD x y)) 211 212 (Neq8 x y) -> (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0])) 213 (Neq16 x y) -> (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0])) 214 (Neq32 x y) -> (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0])) 215 (Neq64 x y) -> (SGTU (XOR x y) (MOVVconst [0])) 216 (NeqPtr x y) -> (SGTU (XOR x y) (MOVVconst [0])) 217 (Neq32F x y) -> (FPFlagFalse (CMPEQF x y)) 218 (Neq64F x y) -> (FPFlagFalse (CMPEQD x y)) 219 220 (Less8 x y) -> (SGT (SignExt8to64 y) (SignExt8to64 x)) 221 (Less16 x y) -> (SGT (SignExt16to64 y) (SignExt16to64 x)) 222 (Less32 x y) -> (SGT (SignExt32to64 y) (SignExt32to64 x)) 223 (Less64 x y) -> (SGT y x) 224 (Less32F x y) -> (FPFlagTrue (CMPGTF y x)) // reverse operands to work around NaN 225 (Less64F x y) -> (FPFlagTrue (CMPGTD y x)) // reverse operands to work around NaN 226 227 (Less8U x y) -> (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x)) 228 (Less16U x y) -> (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x)) 229 (Less32U x y) -> (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x)) 230 (Less64U x y) -> (SGTU y x) 231 232 (Leq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y))) 233 (Leq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y))) 234 (Leq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y))) 235 (Leq64 x y) -> (XOR (MOVVconst [1]) (SGT x y)) 236 (Leq32F x y) -> (FPFlagTrue (CMPGEF y x)) // reverse operands to work around NaN 237 (Leq64F x y) -> (FPFlagTrue (CMPGED y x)) // reverse operands to work around NaN 238 239 (Leq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y))) 240 (Leq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y))) 241 (Leq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y))) 242 (Leq64U x y) -> (XOR (MOVVconst [1]) (SGTU x y)) 243 244 (Greater8 x y) -> (SGT (SignExt8to64 x) (SignExt8to64 y)) 245 (Greater16 x y) -> (SGT (SignExt16to64 x) (SignExt16to64 y)) 246 (Greater32 x y) -> (SGT (SignExt32to64 x) (SignExt32to64 y)) 247 (Greater64 x y) -> (SGT x y) 248 (Greater32F x y) -> (FPFlagTrue (CMPGTF x y)) 249 (Greater64F x y) -> (FPFlagTrue (CMPGTD x y)) 250 251 (Greater8U x y) -> (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)) 252 (Greater16U x y) -> (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)) 253 (Greater32U x y) -> (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)) 254 (Greater64U x y) -> (SGTU x y) 255 256 (Geq8 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt8to64 y) (SignExt8to64 x))) 257 (Geq16 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt16to64 y) (SignExt16to64 x))) 258 (Geq32 x y) -> (XOR (MOVVconst [1]) (SGT (SignExt32to64 y) (SignExt32to64 x))) 259 (Geq64 x y) -> (XOR (MOVVconst [1]) (SGT y x)) 260 (Geq32F x y) -> (FPFlagTrue (CMPGEF x y)) 261 (Geq64F x y) -> (FPFlagTrue (CMPGED x y)) 262 263 (Geq8U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))) 264 (Geq16U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))) 265 (Geq32U x y) -> (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))) 266 (Geq64U x y) -> (XOR (MOVVconst [1]) (SGTU y x)) 267 268 (OffPtr [off] ptr:(SP)) -> (MOVVaddr [off] ptr) 269 (OffPtr [off] ptr) -> (ADDVconst [off] ptr) 270 271 (Addr {sym} base) -> (MOVVaddr {sym} base) 272 273 // loads 274 (Load <t> ptr mem) && t.IsBoolean() -> (MOVBUload ptr mem) 275 (Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) -> (MOVBload ptr mem) 276 (Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) -> (MOVBUload ptr mem) 277 (Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) -> (MOVHload ptr mem) 278 (Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) -> (MOVHUload ptr mem) 279 (Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) -> (MOVWload ptr mem) 280 (Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) -> (MOVWUload ptr mem) 281 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVVload ptr mem) 282 (Load <t> ptr mem) && is32BitFloat(t) -> (MOVFload ptr mem) 283 (Load <t> ptr mem) && is64BitFloat(t) -> (MOVDload ptr mem) 284 285 // stores 286 (Store [1] ptr val mem) -> (MOVBstore ptr val mem) 287 (Store [2] ptr val mem) -> (MOVHstore ptr val mem) 288 (Store [4] ptr val mem) && !is32BitFloat(val.Type) -> (MOVWstore ptr val mem) 289 (Store [8] ptr val mem) && !is64BitFloat(val.Type) -> (MOVVstore ptr val mem) 290 (Store [4] ptr val mem) && is32BitFloat(val.Type) -> (MOVFstore ptr val mem) 291 (Store [8] ptr val mem) && is64BitFloat(val.Type) -> (MOVDstore ptr val mem) 292 293 // zeroing 294 (Zero [s] _ mem) && SizeAndAlign(s).Size() == 0 -> mem 295 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore ptr (MOVVconst [0]) mem) 296 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 -> 297 (MOVHstore ptr (MOVVconst [0]) mem) 298 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 2 -> 299 (MOVBstore [1] ptr (MOVVconst [0]) 300 (MOVBstore [0] ptr (MOVVconst [0]) mem)) 301 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 -> 302 (MOVWstore ptr (MOVVconst [0]) mem) 303 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 -> 304 (MOVHstore [2] ptr (MOVVconst [0]) 305 (MOVHstore [0] ptr (MOVVconst [0]) mem)) 306 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 -> 307 (MOVBstore [3] ptr (MOVVconst [0]) 308 (MOVBstore [2] ptr (MOVVconst [0]) 309 (MOVBstore [1] ptr (MOVVconst [0]) 310 (MOVBstore [0] ptr (MOVVconst [0]) mem)))) 311 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 -> 312 (MOVVstore ptr (MOVVconst [0]) mem) 313 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 -> 314 (MOVWstore [4] ptr (MOVVconst [0]) 315 (MOVWstore [0] ptr (MOVVconst [0]) mem)) 316 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 4 -> 317 (MOVHstore [6] ptr (MOVVconst [0]) 318 (MOVHstore [4] ptr (MOVVconst [0]) 319 (MOVHstore [2] ptr (MOVVconst [0]) 320 (MOVHstore [0] ptr (MOVVconst [0]) mem)))) 321 322 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 3 -> 323 (MOVBstore [2] ptr (MOVVconst [0]) 324 (MOVBstore [1] ptr (MOVVconst [0]) 325 (MOVBstore [0] ptr (MOVVconst [0]) mem))) 326 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 -> 327 (MOVHstore [4] ptr (MOVVconst [0]) 328 (MOVHstore [2] ptr (MOVVconst [0]) 329 (MOVHstore [0] ptr (MOVVconst [0]) mem))) 330 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 -> 331 (MOVWstore [8] ptr (MOVVconst [0]) 332 (MOVWstore [4] ptr (MOVVconst [0]) 333 (MOVWstore [0] ptr (MOVVconst [0]) mem))) 334 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 -> 335 (MOVVstore [8] ptr (MOVVconst [0]) 336 (MOVVstore [0] ptr (MOVVconst [0]) mem)) 337 (Zero [s] ptr mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 -> 338 (MOVVstore [16] ptr (MOVVconst [0]) 339 (MOVVstore [8] ptr (MOVVconst [0]) 340 (MOVVstore [0] ptr (MOVVconst [0]) mem))) 341 342 // medium zeroing uses a duff device 343 // 8, and 128 are magic constants, see runtime/mkduff.go 344 (Zero [s] ptr mem) 345 && SizeAndAlign(s).Size()%8 == 0 && SizeAndAlign(s).Size() > 24 && SizeAndAlign(s).Size() <= 8*128 346 && SizeAndAlign(s).Align()%8 == 0 && !config.noDuffDevice -> 347 (DUFFZERO [8 * (128 - int64(SizeAndAlign(s).Size()/8))] ptr mem) 348 349 // large or unaligned zeroing uses a loop 350 (Zero [s] ptr mem) 351 && (SizeAndAlign(s).Size() > 8*128 || config.noDuffDevice) || SizeAndAlign(s).Align()%8 != 0 -> 352 (LoweredZero [SizeAndAlign(s).Align()] 353 ptr 354 (ADDVconst <ptr.Type> ptr [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) 355 mem) 356 357 // moves 358 (Move [s] _ _ mem) && SizeAndAlign(s).Size() == 0 -> mem 359 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 1 -> (MOVBstore dst (MOVBload src mem) mem) 360 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 && SizeAndAlign(s).Align()%2 == 0 -> 361 (MOVHstore dst (MOVHload src mem) mem) 362 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 2 -> 363 (MOVBstore [1] dst (MOVBload [1] src mem) 364 (MOVBstore dst (MOVBload src mem) mem)) 365 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%4 == 0 -> 366 (MOVWstore dst (MOVWload src mem) mem) 367 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 && SizeAndAlign(s).Align()%2 == 0 -> 368 (MOVHstore [2] dst (MOVHload [2] src mem) 369 (MOVHstore dst (MOVHload src mem) mem)) 370 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 4 -> 371 (MOVBstore [3] dst (MOVBload [3] src mem) 372 (MOVBstore [2] dst (MOVBload [2] src mem) 373 (MOVBstore [1] dst (MOVBload [1] src mem) 374 (MOVBstore dst (MOVBload src mem) mem)))) 375 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%8 == 0 -> 376 (MOVVstore dst (MOVVload src mem) mem) 377 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%4 == 0 -> 378 (MOVWstore [4] dst (MOVWload [4] src mem) 379 (MOVWstore dst (MOVWload src mem) mem)) 380 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 8 && SizeAndAlign(s).Align()%2 == 0 -> 381 (MOVHstore [6] dst (MOVHload [6] src mem) 382 (MOVHstore [4] dst (MOVHload [4] src mem) 383 (MOVHstore [2] dst (MOVHload [2] src mem) 384 (MOVHstore dst (MOVHload src mem) mem)))) 385 386 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 3 -> 387 (MOVBstore [2] dst (MOVBload [2] src mem) 388 (MOVBstore [1] dst (MOVBload [1] src mem) 389 (MOVBstore dst (MOVBload src mem) mem))) 390 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 6 && SizeAndAlign(s).Align()%2 == 0 -> 391 (MOVHstore [4] dst (MOVHload [4] src mem) 392 (MOVHstore [2] dst (MOVHload [2] src mem) 393 (MOVHstore dst (MOVHload src mem) mem))) 394 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 12 && SizeAndAlign(s).Align()%4 == 0 -> 395 (MOVWstore [8] dst (MOVWload [8] src mem) 396 (MOVWstore [4] dst (MOVWload [4] src mem) 397 (MOVWstore dst (MOVWload src mem) mem))) 398 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 16 && SizeAndAlign(s).Align()%8 == 0 -> 399 (MOVVstore [8] dst (MOVVload [8] src mem) 400 (MOVVstore dst (MOVVload src mem) mem)) 401 (Move [s] dst src mem) && SizeAndAlign(s).Size() == 24 && SizeAndAlign(s).Align()%8 == 0 -> 402 (MOVVstore [16] dst (MOVVload [16] src mem) 403 (MOVVstore [8] dst (MOVVload [8] src mem) 404 (MOVVstore dst (MOVVload src mem) mem))) 405 406 // large or unaligned move uses a loop 407 (Move [s] dst src mem) 408 && SizeAndAlign(s).Size() > 24 || SizeAndAlign(s).Align()%8 != 0 -> 409 (LoweredMove [SizeAndAlign(s).Align()] 410 dst 411 src 412 (ADDVconst <src.Type> src [SizeAndAlign(s).Size()-moveSize(SizeAndAlign(s).Align(), config)]) 413 mem) 414 415 // calls 416 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 417 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 418 (DeferCall [argwid] mem) -> (CALLdefer [argwid] mem) 419 (GoCall [argwid] mem) -> (CALLgo [argwid] mem) 420 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 421 422 // checks 423 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 424 (IsNonNil ptr) -> (SGTU ptr (MOVVconst [0])) 425 (IsInBounds idx len) -> (SGTU len idx) 426 (IsSliceInBounds idx len) -> (XOR (MOVVconst [1]) (SGTU idx len)) 427 428 // pseudo-ops 429 (GetClosurePtr) -> (LoweredGetClosurePtr) 430 (Convert x mem) -> (MOVVconvert x mem) 431 432 (If cond yes no) -> (NE cond yes no) 433 434 // Optimizations 435 436 // Absorb boolean tests into block 437 (NE (FPFlagTrue cmp) yes no) -> (FPT cmp yes no) 438 (NE (FPFlagFalse cmp) yes no) -> (FPF cmp yes no) 439 (EQ (FPFlagTrue cmp) yes no) -> (FPF cmp yes no) 440 (EQ (FPFlagFalse cmp) yes no) -> (FPT cmp yes no) 441 (NE (XORconst [1] cmp:(SGT _ _)) yes no) -> (EQ cmp yes no) 442 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) -> (EQ cmp yes no) 443 (NE (XORconst [1] cmp:(SGTconst _)) yes no) -> (EQ cmp yes no) 444 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) -> (EQ cmp yes no) 445 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) -> (NE cmp yes no) 446 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) -> (NE cmp yes no) 447 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) -> (NE cmp yes no) 448 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) -> (NE cmp yes no) 449 (NE (SGTUconst [1] x) yes no) -> (EQ x yes no) 450 (EQ (SGTUconst [1] x) yes no) -> (NE x yes no) 451 (NE (SGTU x (MOVVconst [0])) yes no) -> (NE x yes no) 452 (EQ (SGTU x (MOVVconst [0])) yes no) -> (EQ x yes no) 453 (NE (SGTconst [0] x) yes no) -> (LTZ x yes no) 454 (EQ (SGTconst [0] x) yes no) -> (GEZ x yes no) 455 (NE (SGT x (MOVVconst [0])) yes no) -> (GTZ x yes no) 456 (EQ (SGT x (MOVVconst [0])) yes no) -> (LEZ x yes no) 457 458 // fold offset into address 459 (ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) -> (MOVVaddr [off1+off2] {sym} ptr) 460 461 // fold address into load/store 462 (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem) 463 (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBUload [off1+off2] {sym} ptr mem) 464 (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem) 465 (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHUload [off1+off2] {sym} ptr mem) 466 (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem) 467 (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWUload [off1+off2] {sym} ptr mem) 468 (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVload [off1+off2] {sym} ptr mem) 469 (MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVFload [off1+off2] {sym} ptr mem) 470 (MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem) 471 472 (MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem) 473 (MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem) 474 (MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem) 475 (MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVVstore [off1+off2] {sym} ptr val mem) 476 (MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVFstore [off1+off2] {sym} ptr val mem) 477 (MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem) 478 (MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBstorezero [off1+off2] {sym} ptr mem) 479 (MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHstorezero [off1+off2] {sym} ptr mem) 480 (MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWstorezero [off1+off2] {sym} ptr mem) 481 (MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVVstorezero [off1+off2] {sym} ptr mem) 482 483 (MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 484 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 485 (MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 486 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 487 (MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 488 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 489 (MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 490 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 491 (MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 492 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 493 (MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 494 (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 495 (MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 496 (MOVVload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 497 (MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 498 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 499 (MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 500 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 501 502 (MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 503 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 504 (MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 505 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 506 (MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 507 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 508 (MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 509 (MOVVstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 510 (MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 511 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 512 (MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 513 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 514 (MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 515 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 516 (MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 517 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 518 (MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 519 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 520 (MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(off1+off2) -> 521 (MOVVstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 522 523 // store zero 524 (MOVBstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem) 525 (MOVHstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem) 526 (MOVWstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem) 527 (MOVVstore [off] {sym} ptr (MOVVconst [0]) mem) -> (MOVVstorezero [off] {sym} ptr mem) 528 529 // don't extend after proper load 530 (MOVBreg x:(MOVBload _ _)) -> (MOVVreg x) 531 (MOVBUreg x:(MOVBUload _ _)) -> (MOVVreg x) 532 (MOVHreg x:(MOVBload _ _)) -> (MOVVreg x) 533 (MOVHreg x:(MOVBUload _ _)) -> (MOVVreg x) 534 (MOVHreg x:(MOVHload _ _)) -> (MOVVreg x) 535 (MOVHUreg x:(MOVBUload _ _)) -> (MOVVreg x) 536 (MOVHUreg x:(MOVHUload _ _)) -> (MOVVreg x) 537 (MOVWreg x:(MOVBload _ _)) -> (MOVVreg x) 538 (MOVWreg x:(MOVBUload _ _)) -> (MOVVreg x) 539 (MOVWreg x:(MOVHload _ _)) -> (MOVVreg x) 540 (MOVWreg x:(MOVHUload _ _)) -> (MOVVreg x) 541 (MOVWreg x:(MOVWload _ _)) -> (MOVVreg x) 542 (MOVWUreg x:(MOVBUload _ _)) -> (MOVVreg x) 543 (MOVWUreg x:(MOVHUload _ _)) -> (MOVVreg x) 544 (MOVWUreg x:(MOVWUload _ _)) -> (MOVVreg x) 545 546 // fold double extensions 547 (MOVBreg x:(MOVBreg _)) -> (MOVVreg x) 548 (MOVBUreg x:(MOVBUreg _)) -> (MOVVreg x) 549 (MOVHreg x:(MOVBreg _)) -> (MOVVreg x) 550 (MOVHreg x:(MOVBUreg _)) -> (MOVVreg x) 551 (MOVHreg x:(MOVHreg _)) -> (MOVVreg x) 552 (MOVHUreg x:(MOVBUreg _)) -> (MOVVreg x) 553 (MOVHUreg x:(MOVHUreg _)) -> (MOVVreg x) 554 (MOVWreg x:(MOVBreg _)) -> (MOVVreg x) 555 (MOVWreg x:(MOVBUreg _)) -> (MOVVreg x) 556 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 557 (MOVWreg x:(MOVHreg _)) -> (MOVVreg x) 558 (MOVWreg x:(MOVWreg _)) -> (MOVVreg x) 559 (MOVWUreg x:(MOVBUreg _)) -> (MOVVreg x) 560 (MOVWUreg x:(MOVHUreg _)) -> (MOVVreg x) 561 (MOVWUreg x:(MOVWUreg _)) -> (MOVVreg x) 562 563 // don't extend before store 564 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 565 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 566 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 567 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 568 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 569 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 570 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 571 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 572 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 573 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 574 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 575 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 576 577 // if a register move has only 1 use, just use the same register without emitting instruction 578 // MOVVnop doesn't emit instruction, only for ensuring the type. 579 (MOVVreg x) && x.Uses == 1 -> (MOVVnop x) 580 581 // fold constant into arithmatic ops 582 (ADDV (MOVVconst [c]) x) && is32Bit(c) -> (ADDVconst [c] x) 583 (ADDV x (MOVVconst [c])) && is32Bit(c) -> (ADDVconst [c] x) 584 (SUBV x (MOVVconst [c])) && is32Bit(c) -> (SUBVconst [c] x) 585 (AND (MOVVconst [c]) x) && is32Bit(c) -> (ANDconst [c] x) 586 (AND x (MOVVconst [c])) && is32Bit(c) -> (ANDconst [c] x) 587 (OR (MOVVconst [c]) x) && is32Bit(c) -> (ORconst [c] x) 588 (OR x (MOVVconst [c])) && is32Bit(c) -> (ORconst [c] x) 589 (XOR (MOVVconst [c]) x) && is32Bit(c) -> (XORconst [c] x) 590 (XOR x (MOVVconst [c])) && is32Bit(c) -> (XORconst [c] x) 591 (NOR (MOVVconst [c]) x) && is32Bit(c) -> (NORconst [c] x) 592 (NOR x (MOVVconst [c])) && is32Bit(c) -> (NORconst [c] x) 593 594 (SLLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 595 (SRLV _ (MOVVconst [c])) && uint64(c)>=64 -> (MOVVconst [0]) 596 (SRAV x (MOVVconst [c])) && uint64(c)>=64 -> (SRAVconst x [63]) 597 (SLLV x (MOVVconst [c])) -> (SLLVconst x [c]) 598 (SRLV x (MOVVconst [c])) -> (SRLVconst x [c]) 599 (SRAV x (MOVVconst [c])) -> (SRAVconst x [c]) 600 601 (SGT (MOVVconst [c]) x) && is32Bit(c) -> (SGTconst [c] x) 602 (SGTU (MOVVconst [c]) x) && is32Bit(c) -> (SGTUconst [c] x) 603 604 // mul by constant 605 (Select1 (MULVU x (MOVVconst [-1]))) -> (NEGV x) 606 (Select1 (MULVU _ (MOVVconst [0]))) -> (MOVVconst [0]) 607 (Select1 (MULVU x (MOVVconst [1]))) -> x 608 (Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 609 610 (Select1 (MULVU (MOVVconst [-1]) x)) -> (NEGV x) 611 (Select1 (MULVU (MOVVconst [0]) _)) -> (MOVVconst [0]) 612 (Select1 (MULVU (MOVVconst [1]) x)) -> x 613 (Select1 (MULVU (MOVVconst [c]) x)) && isPowerOfTwo(c) -> (SLLVconst [log2(c)] x) 614 615 // div by constant 616 (Select1 (DIVVU x (MOVVconst [1]))) -> x 617 (Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (SRLVconst [log2(c)] x) 618 (Select0 (DIVVU _ (MOVVconst [1]))) -> (MOVVconst [0]) // mod 619 (Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) -> (ANDconst [c-1] x) // mod 620 621 // generic simplifications 622 (ADDV x (NEGV y)) -> (SUBV x y) 623 (ADDV (NEGV y) x) -> (SUBV x y) 624 (SUBV x x) -> (MOVVconst [0]) 625 (SUBV (MOVVconst [0]) x) -> (NEGV x) 626 (AND x x) -> x 627 (OR x x) -> x 628 (XOR x x) -> (MOVVconst [0]) 629 630 // remove redundant *const ops 631 (ADDVconst [0] x) -> x 632 (SUBVconst [0] x) -> x 633 (ANDconst [0] _) -> (MOVVconst [0]) 634 (ANDconst [-1] x) -> x 635 (ORconst [0] x) -> x 636 (ORconst [-1] _) -> (MOVVconst [-1]) 637 (XORconst [0] x) -> x 638 (XORconst [-1] x) -> (NORconst [0] x) 639 640 // generic constant folding 641 (ADDVconst [c] (MOVVconst [d])) -> (MOVVconst [c+d]) 642 (ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) -> (ADDVconst [c+d] x) 643 (ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) -> (ADDVconst [c-d] x) 644 (SUBVconst [c] (MOVVconst [d])) -> (MOVVconst [d-c]) 645 (SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) -> (ADDVconst [-c-d] x) 646 (SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) -> (ADDVconst [-c+d] x) 647 (SLLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)<<uint64(c)]) 648 (SRLVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(uint64(d)>>uint64(c))]) 649 (SRAVconst [c] (MOVVconst [d])) -> (MOVVconst [int64(d)>>uint64(c)]) 650 (Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [c*d]) 651 (Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)/int64(d)]) 652 (Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)/uint64(d))]) 653 (Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(c)%int64(d)]) // mod 654 (Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) -> (MOVVconst [int64(uint64(c)%uint64(d))]) // mod 655 (ANDconst [c] (MOVVconst [d])) -> (MOVVconst [c&d]) 656 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x) 657 (ORconst [c] (MOVVconst [d])) -> (MOVVconst [c|d]) 658 (ORconst [c] (ORconst [d] x)) && is32Bit(c|d) -> (ORconst [c|d] x) 659 (XORconst [c] (MOVVconst [d])) -> (MOVVconst [c^d]) 660 (XORconst [c] (XORconst [d] x)) && is32Bit(c^d) -> (XORconst [c^d] x) 661 (NORconst [c] (MOVVconst [d])) -> (MOVVconst [^(c|d)]) 662 (NEGV (MOVVconst [c])) -> (MOVVconst [-c]) 663 (MOVBreg (MOVVconst [c])) -> (MOVVconst [int64(int8(c))]) 664 (MOVBUreg (MOVVconst [c])) -> (MOVVconst [int64(uint8(c))]) 665 (MOVHreg (MOVVconst [c])) -> (MOVVconst [int64(int16(c))]) 666 (MOVHUreg (MOVVconst [c])) -> (MOVVconst [int64(uint16(c))]) 667 (MOVWreg (MOVVconst [c])) -> (MOVVconst [int64(int32(c))]) 668 (MOVWUreg (MOVVconst [c])) -> (MOVVconst [int64(uint32(c))]) 669 (MOVVreg (MOVVconst [c])) -> (MOVVconst [c]) 670 671 // constant comparisons 672 (SGTconst [c] (MOVVconst [d])) && int64(c)>int64(d) -> (MOVVconst [1]) 673 (SGTconst [c] (MOVVconst [d])) && int64(c)<=int64(d) -> (MOVVconst [0]) 674 (SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) -> (MOVVconst [1]) 675 (SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) -> (MOVVconst [0]) 676 677 // other known comparisons 678 (SGTconst [c] (MOVBreg _)) && 0x7f < int64(c) -> (MOVVconst [1]) 679 (SGTconst [c] (MOVBreg _)) && int64(c) <= -0x80 -> (MOVVconst [0]) 680 (SGTconst [c] (MOVBUreg _)) && 0xff < int64(c) -> (MOVVconst [1]) 681 (SGTconst [c] (MOVBUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 682 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) -> (MOVVconst [1]) 683 (SGTconst [c] (MOVHreg _)) && 0x7fff < int64(c) -> (MOVVconst [1]) 684 (SGTconst [c] (MOVHreg _)) && int64(c) <= -0x8000 -> (MOVVconst [0]) 685 (SGTconst [c] (MOVHUreg _)) && 0xffff < int64(c) -> (MOVVconst [1]) 686 (SGTconst [c] (MOVHUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 687 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) -> (MOVVconst [1]) 688 (SGTconst [c] (MOVWUreg _)) && int64(c) < 0 -> (MOVVconst [0]) 689 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c -> (MOVVconst [1]) 690 (SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) -> (MOVVconst [1]) 691 (SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 1<<uint64(64-d) <= c -> (MOVVconst [1]) 692 (SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 1<<uint64(64-d) <= uint64(c) -> (MOVVconst [1]) 693 694 // absorb constants into branches 695 (EQ (MOVVconst [0]) yes no) -> (First nil yes no) 696 (EQ (MOVVconst [c]) yes no) && c != 0 -> (First nil no yes) 697 (NE (MOVVconst [0]) yes no) -> (First nil no yes) 698 (NE (MOVVconst [c]) yes no) && c != 0 -> (First nil yes no) 699 (LTZ (MOVVconst [c]) yes no) && c < 0 -> (First nil yes no) 700 (LTZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil no yes) 701 (LEZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil yes no) 702 (LEZ (MOVVconst [c]) yes no) && c > 0 -> (First nil no yes) 703 (GTZ (MOVVconst [c]) yes no) && c > 0 -> (First nil yes no) 704 (GTZ (MOVVconst [c]) yes no) && c <= 0 -> (First nil no yes) 705 (GEZ (MOVVconst [c]) yes no) && c >= 0 -> (First nil yes no) 706 (GEZ (MOVVconst [c]) yes no) && c < 0 -> (First nil no yes)