github.com/euank/go@v0.0.0-20160829210321-495514729181/src/cmd/compile/internal/ssa/opGen.go (about) 1 // autogenerated: do not edit! 2 // generated from gen/*Ops.go 3 4 package ssa 5 6 import ( 7 "cmd/internal/obj" 8 "cmd/internal/obj/arm" 9 "cmd/internal/obj/arm64" 10 "cmd/internal/obj/mips" 11 "cmd/internal/obj/ppc64" 12 "cmd/internal/obj/x86" 13 ) 14 15 const ( 16 BlockInvalid BlockKind = iota 17 18 Block386EQ 19 Block386NE 20 Block386LT 21 Block386LE 22 Block386GT 23 Block386GE 24 Block386ULT 25 Block386ULE 26 Block386UGT 27 Block386UGE 28 Block386EQF 29 Block386NEF 30 Block386ORD 31 Block386NAN 32 33 BlockAMD64EQ 34 BlockAMD64NE 35 BlockAMD64LT 36 BlockAMD64LE 37 BlockAMD64GT 38 BlockAMD64GE 39 BlockAMD64ULT 40 BlockAMD64ULE 41 BlockAMD64UGT 42 BlockAMD64UGE 43 BlockAMD64EQF 44 BlockAMD64NEF 45 BlockAMD64ORD 46 BlockAMD64NAN 47 48 BlockARMEQ 49 BlockARMNE 50 BlockARMLT 51 BlockARMLE 52 BlockARMGT 53 BlockARMGE 54 BlockARMULT 55 BlockARMULE 56 BlockARMUGT 57 BlockARMUGE 58 59 BlockARM64EQ 60 BlockARM64NE 61 BlockARM64LT 62 BlockARM64LE 63 BlockARM64GT 64 BlockARM64GE 65 BlockARM64ULT 66 BlockARM64ULE 67 BlockARM64UGT 68 BlockARM64UGE 69 70 BlockMIPS64EQ 71 BlockMIPS64NE 72 BlockMIPS64LTZ 73 BlockMIPS64LEZ 74 BlockMIPS64GTZ 75 BlockMIPS64GEZ 76 BlockMIPS64FPT 77 BlockMIPS64FPF 78 79 BlockPPC64EQ 80 BlockPPC64NE 81 BlockPPC64LT 82 BlockPPC64LE 83 BlockPPC64GT 84 BlockPPC64GE 85 BlockPPC64FLT 86 BlockPPC64FLE 87 BlockPPC64FGT 88 BlockPPC64FGE 89 90 BlockPlain 91 BlockIf 92 BlockCall 93 BlockDefer 94 BlockCheck 95 BlockRet 96 BlockRetJmp 97 BlockExit 98 BlockFirst 99 ) 100 101 var blockString = [...]string{ 102 BlockInvalid: "BlockInvalid", 103 104 Block386EQ: "EQ", 105 Block386NE: "NE", 106 Block386LT: "LT", 107 Block386LE: "LE", 108 Block386GT: "GT", 109 Block386GE: "GE", 110 Block386ULT: "ULT", 111 Block386ULE: "ULE", 112 Block386UGT: "UGT", 113 Block386UGE: "UGE", 114 Block386EQF: "EQF", 115 Block386NEF: "NEF", 116 Block386ORD: "ORD", 117 Block386NAN: "NAN", 118 119 BlockAMD64EQ: "EQ", 120 BlockAMD64NE: "NE", 121 BlockAMD64LT: "LT", 122 BlockAMD64LE: "LE", 123 BlockAMD64GT: "GT", 124 BlockAMD64GE: "GE", 125 BlockAMD64ULT: "ULT", 126 BlockAMD64ULE: "ULE", 127 BlockAMD64UGT: "UGT", 128 BlockAMD64UGE: "UGE", 129 BlockAMD64EQF: "EQF", 130 BlockAMD64NEF: "NEF", 131 BlockAMD64ORD: "ORD", 132 BlockAMD64NAN: "NAN", 133 134 BlockARMEQ: "EQ", 135 BlockARMNE: "NE", 136 BlockARMLT: "LT", 137 BlockARMLE: "LE", 138 BlockARMGT: "GT", 139 BlockARMGE: "GE", 140 BlockARMULT: "ULT", 141 BlockARMULE: "ULE", 142 BlockARMUGT: "UGT", 143 BlockARMUGE: "UGE", 144 145 BlockARM64EQ: "EQ", 146 BlockARM64NE: "NE", 147 BlockARM64LT: "LT", 148 BlockARM64LE: "LE", 149 BlockARM64GT: "GT", 150 BlockARM64GE: "GE", 151 BlockARM64ULT: "ULT", 152 BlockARM64ULE: "ULE", 153 BlockARM64UGT: "UGT", 154 BlockARM64UGE: "UGE", 155 156 BlockMIPS64EQ: "EQ", 157 BlockMIPS64NE: "NE", 158 BlockMIPS64LTZ: "LTZ", 159 BlockMIPS64LEZ: "LEZ", 160 BlockMIPS64GTZ: "GTZ", 161 BlockMIPS64GEZ: "GEZ", 162 BlockMIPS64FPT: "FPT", 163 BlockMIPS64FPF: "FPF", 164 165 BlockPPC64EQ: "EQ", 166 BlockPPC64NE: "NE", 167 BlockPPC64LT: "LT", 168 BlockPPC64LE: "LE", 169 BlockPPC64GT: "GT", 170 BlockPPC64GE: "GE", 171 BlockPPC64FLT: "FLT", 172 BlockPPC64FLE: "FLE", 173 BlockPPC64FGT: "FGT", 174 BlockPPC64FGE: "FGE", 175 176 BlockPlain: "Plain", 177 BlockIf: "If", 178 BlockCall: "Call", 179 BlockDefer: "Defer", 180 BlockCheck: "Check", 181 BlockRet: "Ret", 182 BlockRetJmp: "RetJmp", 183 BlockExit: "Exit", 184 BlockFirst: "First", 185 } 186 187 func (k BlockKind) String() string { return blockString[k] } 188 189 const ( 190 OpInvalid Op = iota 191 192 Op386ADDSS 193 Op386ADDSD 194 Op386SUBSS 195 Op386SUBSD 196 Op386MULSS 197 Op386MULSD 198 Op386DIVSS 199 Op386DIVSD 200 Op386MOVSSload 201 Op386MOVSDload 202 Op386MOVSSconst 203 Op386MOVSDconst 204 Op386MOVSSloadidx1 205 Op386MOVSSloadidx4 206 Op386MOVSDloadidx1 207 Op386MOVSDloadidx8 208 Op386MOVSSstore 209 Op386MOVSDstore 210 Op386MOVSSstoreidx1 211 Op386MOVSSstoreidx4 212 Op386MOVSDstoreidx1 213 Op386MOVSDstoreidx8 214 Op386ADDL 215 Op386ADDLconst 216 Op386ADDLcarry 217 Op386ADDLconstcarry 218 Op386ADCL 219 Op386ADCLconst 220 Op386SUBL 221 Op386SUBLconst 222 Op386SUBLcarry 223 Op386SUBLconstcarry 224 Op386SBBL 225 Op386SBBLconst 226 Op386MULL 227 Op386MULLconst 228 Op386HMULL 229 Op386HMULLU 230 Op386HMULW 231 Op386HMULB 232 Op386HMULWU 233 Op386HMULBU 234 Op386MULLQU 235 Op386DIVL 236 Op386DIVW 237 Op386DIVLU 238 Op386DIVWU 239 Op386MODL 240 Op386MODW 241 Op386MODLU 242 Op386MODWU 243 Op386ANDL 244 Op386ANDLconst 245 Op386ORL 246 Op386ORLconst 247 Op386XORL 248 Op386XORLconst 249 Op386CMPL 250 Op386CMPW 251 Op386CMPB 252 Op386CMPLconst 253 Op386CMPWconst 254 Op386CMPBconst 255 Op386UCOMISS 256 Op386UCOMISD 257 Op386TESTL 258 Op386TESTW 259 Op386TESTB 260 Op386TESTLconst 261 Op386TESTWconst 262 Op386TESTBconst 263 Op386SHLL 264 Op386SHLLconst 265 Op386SHRL 266 Op386SHRW 267 Op386SHRB 268 Op386SHRLconst 269 Op386SHRWconst 270 Op386SHRBconst 271 Op386SARL 272 Op386SARW 273 Op386SARB 274 Op386SARLconst 275 Op386SARWconst 276 Op386SARBconst 277 Op386ROLLconst 278 Op386ROLWconst 279 Op386ROLBconst 280 Op386NEGL 281 Op386NOTL 282 Op386BSFL 283 Op386BSFW 284 Op386BSRL 285 Op386BSRW 286 Op386BSWAPL 287 Op386SQRTSD 288 Op386SBBLcarrymask 289 Op386SETEQ 290 Op386SETNE 291 Op386SETL 292 Op386SETLE 293 Op386SETG 294 Op386SETGE 295 Op386SETB 296 Op386SETBE 297 Op386SETA 298 Op386SETAE 299 Op386SETEQF 300 Op386SETNEF 301 Op386SETORD 302 Op386SETNAN 303 Op386SETGF 304 Op386SETGEF 305 Op386MOVBLSX 306 Op386MOVBLZX 307 Op386MOVWLSX 308 Op386MOVWLZX 309 Op386MOVLconst 310 Op386CVTTSD2SL 311 Op386CVTTSS2SL 312 Op386CVTSL2SS 313 Op386CVTSL2SD 314 Op386CVTSD2SS 315 Op386CVTSS2SD 316 Op386PXOR 317 Op386LEAL 318 Op386LEAL1 319 Op386LEAL2 320 Op386LEAL4 321 Op386LEAL8 322 Op386MOVBload 323 Op386MOVBLSXload 324 Op386MOVWload 325 Op386MOVWLSXload 326 Op386MOVLload 327 Op386MOVBstore 328 Op386MOVWstore 329 Op386MOVLstore 330 Op386MOVBloadidx1 331 Op386MOVWloadidx1 332 Op386MOVWloadidx2 333 Op386MOVLloadidx1 334 Op386MOVLloadidx4 335 Op386MOVBstoreidx1 336 Op386MOVWstoreidx1 337 Op386MOVWstoreidx2 338 Op386MOVLstoreidx1 339 Op386MOVLstoreidx4 340 Op386MOVBstoreconst 341 Op386MOVWstoreconst 342 Op386MOVLstoreconst 343 Op386MOVBstoreconstidx1 344 Op386MOVWstoreconstidx1 345 Op386MOVWstoreconstidx2 346 Op386MOVLstoreconstidx1 347 Op386MOVLstoreconstidx4 348 Op386DUFFZERO 349 Op386REPSTOSL 350 Op386CALLstatic 351 Op386CALLclosure 352 Op386CALLdefer 353 Op386CALLgo 354 Op386CALLinter 355 Op386DUFFCOPY 356 Op386REPMOVSL 357 Op386InvertFlags 358 Op386LoweredGetG 359 Op386LoweredGetClosurePtr 360 Op386LoweredNilCheck 361 Op386MOVLconvert 362 Op386FlagEQ 363 Op386FlagLT_ULT 364 Op386FlagLT_UGT 365 Op386FlagGT_UGT 366 Op386FlagGT_ULT 367 Op386FCHS 368 Op386MOVSSconst1 369 Op386MOVSDconst1 370 Op386MOVSSconst2 371 Op386MOVSDconst2 372 373 OpAMD64ADDSS 374 OpAMD64ADDSD 375 OpAMD64SUBSS 376 OpAMD64SUBSD 377 OpAMD64MULSS 378 OpAMD64MULSD 379 OpAMD64DIVSS 380 OpAMD64DIVSD 381 OpAMD64MOVSSload 382 OpAMD64MOVSDload 383 OpAMD64MOVSSconst 384 OpAMD64MOVSDconst 385 OpAMD64MOVSSloadidx1 386 OpAMD64MOVSSloadidx4 387 OpAMD64MOVSDloadidx1 388 OpAMD64MOVSDloadidx8 389 OpAMD64MOVSSstore 390 OpAMD64MOVSDstore 391 OpAMD64MOVSSstoreidx1 392 OpAMD64MOVSSstoreidx4 393 OpAMD64MOVSDstoreidx1 394 OpAMD64MOVSDstoreidx8 395 OpAMD64ADDQ 396 OpAMD64ADDL 397 OpAMD64ADDQconst 398 OpAMD64ADDLconst 399 OpAMD64SUBQ 400 OpAMD64SUBL 401 OpAMD64SUBQconst 402 OpAMD64SUBLconst 403 OpAMD64MULQ 404 OpAMD64MULL 405 OpAMD64MULQconst 406 OpAMD64MULLconst 407 OpAMD64HMULQ 408 OpAMD64HMULL 409 OpAMD64HMULW 410 OpAMD64HMULB 411 OpAMD64HMULQU 412 OpAMD64HMULLU 413 OpAMD64HMULWU 414 OpAMD64HMULBU 415 OpAMD64AVGQU 416 OpAMD64DIVQ 417 OpAMD64DIVL 418 OpAMD64DIVW 419 OpAMD64DIVQU 420 OpAMD64DIVLU 421 OpAMD64DIVWU 422 OpAMD64ANDQ 423 OpAMD64ANDL 424 OpAMD64ANDQconst 425 OpAMD64ANDLconst 426 OpAMD64ORQ 427 OpAMD64ORL 428 OpAMD64ORQconst 429 OpAMD64ORLconst 430 OpAMD64XORQ 431 OpAMD64XORL 432 OpAMD64XORQconst 433 OpAMD64XORLconst 434 OpAMD64CMPQ 435 OpAMD64CMPL 436 OpAMD64CMPW 437 OpAMD64CMPB 438 OpAMD64CMPQconst 439 OpAMD64CMPLconst 440 OpAMD64CMPWconst 441 OpAMD64CMPBconst 442 OpAMD64UCOMISS 443 OpAMD64UCOMISD 444 OpAMD64TESTQ 445 OpAMD64TESTL 446 OpAMD64TESTW 447 OpAMD64TESTB 448 OpAMD64TESTQconst 449 OpAMD64TESTLconst 450 OpAMD64TESTWconst 451 OpAMD64TESTBconst 452 OpAMD64SHLQ 453 OpAMD64SHLL 454 OpAMD64SHLQconst 455 OpAMD64SHLLconst 456 OpAMD64SHRQ 457 OpAMD64SHRL 458 OpAMD64SHRW 459 OpAMD64SHRB 460 OpAMD64SHRQconst 461 OpAMD64SHRLconst 462 OpAMD64SHRWconst 463 OpAMD64SHRBconst 464 OpAMD64SARQ 465 OpAMD64SARL 466 OpAMD64SARW 467 OpAMD64SARB 468 OpAMD64SARQconst 469 OpAMD64SARLconst 470 OpAMD64SARWconst 471 OpAMD64SARBconst 472 OpAMD64ROLQconst 473 OpAMD64ROLLconst 474 OpAMD64ROLWconst 475 OpAMD64ROLBconst 476 OpAMD64NEGQ 477 OpAMD64NEGL 478 OpAMD64NOTQ 479 OpAMD64NOTL 480 OpAMD64BSFQ 481 OpAMD64BSFL 482 OpAMD64CMOVQEQ 483 OpAMD64CMOVLEQ 484 OpAMD64BSWAPQ 485 OpAMD64BSWAPL 486 OpAMD64SQRTSD 487 OpAMD64SBBQcarrymask 488 OpAMD64SBBLcarrymask 489 OpAMD64SETEQ 490 OpAMD64SETNE 491 OpAMD64SETL 492 OpAMD64SETLE 493 OpAMD64SETG 494 OpAMD64SETGE 495 OpAMD64SETB 496 OpAMD64SETBE 497 OpAMD64SETA 498 OpAMD64SETAE 499 OpAMD64SETEQF 500 OpAMD64SETNEF 501 OpAMD64SETORD 502 OpAMD64SETNAN 503 OpAMD64SETGF 504 OpAMD64SETGEF 505 OpAMD64MOVBQSX 506 OpAMD64MOVBQZX 507 OpAMD64MOVWQSX 508 OpAMD64MOVWQZX 509 OpAMD64MOVLQSX 510 OpAMD64MOVLQZX 511 OpAMD64MOVLconst 512 OpAMD64MOVQconst 513 OpAMD64CVTTSD2SL 514 OpAMD64CVTTSD2SQ 515 OpAMD64CVTTSS2SL 516 OpAMD64CVTTSS2SQ 517 OpAMD64CVTSL2SS 518 OpAMD64CVTSL2SD 519 OpAMD64CVTSQ2SS 520 OpAMD64CVTSQ2SD 521 OpAMD64CVTSD2SS 522 OpAMD64CVTSS2SD 523 OpAMD64PXOR 524 OpAMD64LEAQ 525 OpAMD64LEAQ1 526 OpAMD64LEAQ2 527 OpAMD64LEAQ4 528 OpAMD64LEAQ8 529 OpAMD64LEAL 530 OpAMD64MOVBload 531 OpAMD64MOVBQSXload 532 OpAMD64MOVWload 533 OpAMD64MOVWQSXload 534 OpAMD64MOVLload 535 OpAMD64MOVLQSXload 536 OpAMD64MOVQload 537 OpAMD64MOVBstore 538 OpAMD64MOVWstore 539 OpAMD64MOVLstore 540 OpAMD64MOVQstore 541 OpAMD64MOVOload 542 OpAMD64MOVOstore 543 OpAMD64MOVBloadidx1 544 OpAMD64MOVWloadidx1 545 OpAMD64MOVWloadidx2 546 OpAMD64MOVLloadidx1 547 OpAMD64MOVLloadidx4 548 OpAMD64MOVQloadidx1 549 OpAMD64MOVQloadidx8 550 OpAMD64MOVBstoreidx1 551 OpAMD64MOVWstoreidx1 552 OpAMD64MOVWstoreidx2 553 OpAMD64MOVLstoreidx1 554 OpAMD64MOVLstoreidx4 555 OpAMD64MOVQstoreidx1 556 OpAMD64MOVQstoreidx8 557 OpAMD64MOVBstoreconst 558 OpAMD64MOVWstoreconst 559 OpAMD64MOVLstoreconst 560 OpAMD64MOVQstoreconst 561 OpAMD64MOVBstoreconstidx1 562 OpAMD64MOVWstoreconstidx1 563 OpAMD64MOVWstoreconstidx2 564 OpAMD64MOVLstoreconstidx1 565 OpAMD64MOVLstoreconstidx4 566 OpAMD64MOVQstoreconstidx1 567 OpAMD64MOVQstoreconstidx8 568 OpAMD64DUFFZERO 569 OpAMD64MOVOconst 570 OpAMD64REPSTOSQ 571 OpAMD64CALLstatic 572 OpAMD64CALLclosure 573 OpAMD64CALLdefer 574 OpAMD64CALLgo 575 OpAMD64CALLinter 576 OpAMD64DUFFCOPY 577 OpAMD64REPMOVSQ 578 OpAMD64InvertFlags 579 OpAMD64LoweredGetG 580 OpAMD64LoweredGetClosurePtr 581 OpAMD64LoweredNilCheck 582 OpAMD64MOVQconvert 583 OpAMD64MOVLconvert 584 OpAMD64FlagEQ 585 OpAMD64FlagLT_ULT 586 OpAMD64FlagLT_UGT 587 OpAMD64FlagGT_UGT 588 OpAMD64FlagGT_ULT 589 OpAMD64MOVLatomicload 590 OpAMD64MOVQatomicload 591 OpAMD64XCHGL 592 OpAMD64XCHGQ 593 OpAMD64XADDLlock 594 OpAMD64XADDQlock 595 OpAMD64AddTupleFirst32 596 OpAMD64AddTupleFirst64 597 OpAMD64CMPXCHGLlock 598 OpAMD64CMPXCHGQlock 599 OpAMD64ANDBlock 600 OpAMD64ORBlock 601 602 OpARMADD 603 OpARMADDconst 604 OpARMSUB 605 OpARMSUBconst 606 OpARMRSB 607 OpARMRSBconst 608 OpARMMUL 609 OpARMHMUL 610 OpARMHMULU 611 OpARMDIV 612 OpARMDIVU 613 OpARMMOD 614 OpARMMODU 615 OpARMADDS 616 OpARMADDSconst 617 OpARMADC 618 OpARMADCconst 619 OpARMSUBS 620 OpARMSUBSconst 621 OpARMRSBSconst 622 OpARMSBC 623 OpARMSBCconst 624 OpARMRSCconst 625 OpARMMULLU 626 OpARMMULA 627 OpARMADDF 628 OpARMADDD 629 OpARMSUBF 630 OpARMSUBD 631 OpARMMULF 632 OpARMMULD 633 OpARMDIVF 634 OpARMDIVD 635 OpARMAND 636 OpARMANDconst 637 OpARMOR 638 OpARMORconst 639 OpARMXOR 640 OpARMXORconst 641 OpARMBIC 642 OpARMBICconst 643 OpARMMVN 644 OpARMNEGF 645 OpARMNEGD 646 OpARMSQRTD 647 OpARMSLL 648 OpARMSLLconst 649 OpARMSRL 650 OpARMSRLconst 651 OpARMSRA 652 OpARMSRAconst 653 OpARMSRRconst 654 OpARMADDshiftLL 655 OpARMADDshiftRL 656 OpARMADDshiftRA 657 OpARMSUBshiftLL 658 OpARMSUBshiftRL 659 OpARMSUBshiftRA 660 OpARMRSBshiftLL 661 OpARMRSBshiftRL 662 OpARMRSBshiftRA 663 OpARMANDshiftLL 664 OpARMANDshiftRL 665 OpARMANDshiftRA 666 OpARMORshiftLL 667 OpARMORshiftRL 668 OpARMORshiftRA 669 OpARMXORshiftLL 670 OpARMXORshiftRL 671 OpARMXORshiftRA 672 OpARMBICshiftLL 673 OpARMBICshiftRL 674 OpARMBICshiftRA 675 OpARMMVNshiftLL 676 OpARMMVNshiftRL 677 OpARMMVNshiftRA 678 OpARMADCshiftLL 679 OpARMADCshiftRL 680 OpARMADCshiftRA 681 OpARMSBCshiftLL 682 OpARMSBCshiftRL 683 OpARMSBCshiftRA 684 OpARMRSCshiftLL 685 OpARMRSCshiftRL 686 OpARMRSCshiftRA 687 OpARMADDSshiftLL 688 OpARMADDSshiftRL 689 OpARMADDSshiftRA 690 OpARMSUBSshiftLL 691 OpARMSUBSshiftRL 692 OpARMSUBSshiftRA 693 OpARMRSBSshiftLL 694 OpARMRSBSshiftRL 695 OpARMRSBSshiftRA 696 OpARMADDshiftLLreg 697 OpARMADDshiftRLreg 698 OpARMADDshiftRAreg 699 OpARMSUBshiftLLreg 700 OpARMSUBshiftRLreg 701 OpARMSUBshiftRAreg 702 OpARMRSBshiftLLreg 703 OpARMRSBshiftRLreg 704 OpARMRSBshiftRAreg 705 OpARMANDshiftLLreg 706 OpARMANDshiftRLreg 707 OpARMANDshiftRAreg 708 OpARMORshiftLLreg 709 OpARMORshiftRLreg 710 OpARMORshiftRAreg 711 OpARMXORshiftLLreg 712 OpARMXORshiftRLreg 713 OpARMXORshiftRAreg 714 OpARMBICshiftLLreg 715 OpARMBICshiftRLreg 716 OpARMBICshiftRAreg 717 OpARMMVNshiftLLreg 718 OpARMMVNshiftRLreg 719 OpARMMVNshiftRAreg 720 OpARMADCshiftLLreg 721 OpARMADCshiftRLreg 722 OpARMADCshiftRAreg 723 OpARMSBCshiftLLreg 724 OpARMSBCshiftRLreg 725 OpARMSBCshiftRAreg 726 OpARMRSCshiftLLreg 727 OpARMRSCshiftRLreg 728 OpARMRSCshiftRAreg 729 OpARMADDSshiftLLreg 730 OpARMADDSshiftRLreg 731 OpARMADDSshiftRAreg 732 OpARMSUBSshiftLLreg 733 OpARMSUBSshiftRLreg 734 OpARMSUBSshiftRAreg 735 OpARMRSBSshiftLLreg 736 OpARMRSBSshiftRLreg 737 OpARMRSBSshiftRAreg 738 OpARMCMP 739 OpARMCMPconst 740 OpARMCMN 741 OpARMCMNconst 742 OpARMTST 743 OpARMTSTconst 744 OpARMTEQ 745 OpARMTEQconst 746 OpARMCMPF 747 OpARMCMPD 748 OpARMCMPshiftLL 749 OpARMCMPshiftRL 750 OpARMCMPshiftRA 751 OpARMCMPshiftLLreg 752 OpARMCMPshiftRLreg 753 OpARMCMPshiftRAreg 754 OpARMCMPF0 755 OpARMCMPD0 756 OpARMMOVWconst 757 OpARMMOVFconst 758 OpARMMOVDconst 759 OpARMMOVWaddr 760 OpARMMOVBload 761 OpARMMOVBUload 762 OpARMMOVHload 763 OpARMMOVHUload 764 OpARMMOVWload 765 OpARMMOVFload 766 OpARMMOVDload 767 OpARMMOVBstore 768 OpARMMOVHstore 769 OpARMMOVWstore 770 OpARMMOVFstore 771 OpARMMOVDstore 772 OpARMMOVWloadidx 773 OpARMMOVWloadshiftLL 774 OpARMMOVWloadshiftRL 775 OpARMMOVWloadshiftRA 776 OpARMMOVWstoreidx 777 OpARMMOVWstoreshiftLL 778 OpARMMOVWstoreshiftRL 779 OpARMMOVWstoreshiftRA 780 OpARMMOVBreg 781 OpARMMOVBUreg 782 OpARMMOVHreg 783 OpARMMOVHUreg 784 OpARMMOVWreg 785 OpARMMOVWnop 786 OpARMMOVWF 787 OpARMMOVWD 788 OpARMMOVWUF 789 OpARMMOVWUD 790 OpARMMOVFW 791 OpARMMOVDW 792 OpARMMOVFWU 793 OpARMMOVDWU 794 OpARMMOVFD 795 OpARMMOVDF 796 OpARMCMOVWHSconst 797 OpARMCMOVWLSconst 798 OpARMSRAcond 799 OpARMCALLstatic 800 OpARMCALLclosure 801 OpARMCALLdefer 802 OpARMCALLgo 803 OpARMCALLinter 804 OpARMLoweredNilCheck 805 OpARMEqual 806 OpARMNotEqual 807 OpARMLessThan 808 OpARMLessEqual 809 OpARMGreaterThan 810 OpARMGreaterEqual 811 OpARMLessThanU 812 OpARMLessEqualU 813 OpARMGreaterThanU 814 OpARMGreaterEqualU 815 OpARMDUFFZERO 816 OpARMDUFFCOPY 817 OpARMLoweredZero 818 OpARMLoweredMove 819 OpARMLoweredGetClosurePtr 820 OpARMMOVWconvert 821 OpARMFlagEQ 822 OpARMFlagLT_ULT 823 OpARMFlagLT_UGT 824 OpARMFlagGT_UGT 825 OpARMFlagGT_ULT 826 OpARMInvertFlags 827 828 OpARM64ADD 829 OpARM64ADDconst 830 OpARM64SUB 831 OpARM64SUBconst 832 OpARM64MUL 833 OpARM64MULW 834 OpARM64MULH 835 OpARM64UMULH 836 OpARM64MULL 837 OpARM64UMULL 838 OpARM64DIV 839 OpARM64UDIV 840 OpARM64DIVW 841 OpARM64UDIVW 842 OpARM64MOD 843 OpARM64UMOD 844 OpARM64MODW 845 OpARM64UMODW 846 OpARM64FADDS 847 OpARM64FADDD 848 OpARM64FSUBS 849 OpARM64FSUBD 850 OpARM64FMULS 851 OpARM64FMULD 852 OpARM64FDIVS 853 OpARM64FDIVD 854 OpARM64AND 855 OpARM64ANDconst 856 OpARM64OR 857 OpARM64ORconst 858 OpARM64XOR 859 OpARM64XORconst 860 OpARM64BIC 861 OpARM64BICconst 862 OpARM64MVN 863 OpARM64NEG 864 OpARM64FNEGS 865 OpARM64FNEGD 866 OpARM64FSQRTD 867 OpARM64REV 868 OpARM64REVW 869 OpARM64REV16W 870 OpARM64SLL 871 OpARM64SLLconst 872 OpARM64SRL 873 OpARM64SRLconst 874 OpARM64SRA 875 OpARM64SRAconst 876 OpARM64RORconst 877 OpARM64RORWconst 878 OpARM64CMP 879 OpARM64CMPconst 880 OpARM64CMPW 881 OpARM64CMPWconst 882 OpARM64CMN 883 OpARM64CMNconst 884 OpARM64CMNW 885 OpARM64CMNWconst 886 OpARM64FCMPS 887 OpARM64FCMPD 888 OpARM64ADDshiftLL 889 OpARM64ADDshiftRL 890 OpARM64ADDshiftRA 891 OpARM64SUBshiftLL 892 OpARM64SUBshiftRL 893 OpARM64SUBshiftRA 894 OpARM64ANDshiftLL 895 OpARM64ANDshiftRL 896 OpARM64ANDshiftRA 897 OpARM64ORshiftLL 898 OpARM64ORshiftRL 899 OpARM64ORshiftRA 900 OpARM64XORshiftLL 901 OpARM64XORshiftRL 902 OpARM64XORshiftRA 903 OpARM64BICshiftLL 904 OpARM64BICshiftRL 905 OpARM64BICshiftRA 906 OpARM64CMPshiftLL 907 OpARM64CMPshiftRL 908 OpARM64CMPshiftRA 909 OpARM64MOVDconst 910 OpARM64FMOVSconst 911 OpARM64FMOVDconst 912 OpARM64MOVDaddr 913 OpARM64MOVBload 914 OpARM64MOVBUload 915 OpARM64MOVHload 916 OpARM64MOVHUload 917 OpARM64MOVWload 918 OpARM64MOVWUload 919 OpARM64MOVDload 920 OpARM64FMOVSload 921 OpARM64FMOVDload 922 OpARM64MOVBstore 923 OpARM64MOVHstore 924 OpARM64MOVWstore 925 OpARM64MOVDstore 926 OpARM64FMOVSstore 927 OpARM64FMOVDstore 928 OpARM64MOVBstorezero 929 OpARM64MOVHstorezero 930 OpARM64MOVWstorezero 931 OpARM64MOVDstorezero 932 OpARM64MOVBreg 933 OpARM64MOVBUreg 934 OpARM64MOVHreg 935 OpARM64MOVHUreg 936 OpARM64MOVWreg 937 OpARM64MOVWUreg 938 OpARM64MOVDreg 939 OpARM64MOVDnop 940 OpARM64SCVTFWS 941 OpARM64SCVTFWD 942 OpARM64UCVTFWS 943 OpARM64UCVTFWD 944 OpARM64SCVTFS 945 OpARM64SCVTFD 946 OpARM64UCVTFS 947 OpARM64UCVTFD 948 OpARM64FCVTZSSW 949 OpARM64FCVTZSDW 950 OpARM64FCVTZUSW 951 OpARM64FCVTZUDW 952 OpARM64FCVTZSS 953 OpARM64FCVTZSD 954 OpARM64FCVTZUS 955 OpARM64FCVTZUD 956 OpARM64FCVTSD 957 OpARM64FCVTDS 958 OpARM64CSELULT 959 OpARM64CSELULT0 960 OpARM64CALLstatic 961 OpARM64CALLclosure 962 OpARM64CALLdefer 963 OpARM64CALLgo 964 OpARM64CALLinter 965 OpARM64LoweredNilCheck 966 OpARM64Equal 967 OpARM64NotEqual 968 OpARM64LessThan 969 OpARM64LessEqual 970 OpARM64GreaterThan 971 OpARM64GreaterEqual 972 OpARM64LessThanU 973 OpARM64LessEqualU 974 OpARM64GreaterThanU 975 OpARM64GreaterEqualU 976 OpARM64DUFFZERO 977 OpARM64LoweredZero 978 OpARM64LoweredMove 979 OpARM64LoweredGetClosurePtr 980 OpARM64MOVDconvert 981 OpARM64FlagEQ 982 OpARM64FlagLT_ULT 983 OpARM64FlagLT_UGT 984 OpARM64FlagGT_UGT 985 OpARM64FlagGT_ULT 986 OpARM64InvertFlags 987 988 OpMIPS64ADDV 989 OpMIPS64ADDVconst 990 OpMIPS64SUBV 991 OpMIPS64SUBVconst 992 OpMIPS64MULV 993 OpMIPS64MULVU 994 OpMIPS64DIVV 995 OpMIPS64DIVVU 996 OpMIPS64ADDF 997 OpMIPS64ADDD 998 OpMIPS64SUBF 999 OpMIPS64SUBD 1000 OpMIPS64MULF 1001 OpMIPS64MULD 1002 OpMIPS64DIVF 1003 OpMIPS64DIVD 1004 OpMIPS64AND 1005 OpMIPS64ANDconst 1006 OpMIPS64OR 1007 OpMIPS64ORconst 1008 OpMIPS64XOR 1009 OpMIPS64XORconst 1010 OpMIPS64NOR 1011 OpMIPS64NORconst 1012 OpMIPS64NEGV 1013 OpMIPS64NEGF 1014 OpMIPS64NEGD 1015 OpMIPS64SLLV 1016 OpMIPS64SLLVconst 1017 OpMIPS64SRLV 1018 OpMIPS64SRLVconst 1019 OpMIPS64SRAV 1020 OpMIPS64SRAVconst 1021 OpMIPS64SGT 1022 OpMIPS64SGTconst 1023 OpMIPS64SGTU 1024 OpMIPS64SGTUconst 1025 OpMIPS64CMPEQF 1026 OpMIPS64CMPEQD 1027 OpMIPS64CMPGEF 1028 OpMIPS64CMPGED 1029 OpMIPS64CMPGTF 1030 OpMIPS64CMPGTD 1031 OpMIPS64MOVVconst 1032 OpMIPS64MOVFconst 1033 OpMIPS64MOVDconst 1034 OpMIPS64MOVVaddr 1035 OpMIPS64MOVBload 1036 OpMIPS64MOVBUload 1037 OpMIPS64MOVHload 1038 OpMIPS64MOVHUload 1039 OpMIPS64MOVWload 1040 OpMIPS64MOVWUload 1041 OpMIPS64MOVVload 1042 OpMIPS64MOVFload 1043 OpMIPS64MOVDload 1044 OpMIPS64MOVBstore 1045 OpMIPS64MOVHstore 1046 OpMIPS64MOVWstore 1047 OpMIPS64MOVVstore 1048 OpMIPS64MOVFstore 1049 OpMIPS64MOVDstore 1050 OpMIPS64MOVBstorezero 1051 OpMIPS64MOVHstorezero 1052 OpMIPS64MOVWstorezero 1053 OpMIPS64MOVVstorezero 1054 OpMIPS64MOVBreg 1055 OpMIPS64MOVBUreg 1056 OpMIPS64MOVHreg 1057 OpMIPS64MOVHUreg 1058 OpMIPS64MOVWreg 1059 OpMIPS64MOVWUreg 1060 OpMIPS64MOVVreg 1061 OpMIPS64MOVVnop 1062 OpMIPS64MOVWF 1063 OpMIPS64MOVWD 1064 OpMIPS64MOVVF 1065 OpMIPS64MOVVD 1066 OpMIPS64TRUNCFW 1067 OpMIPS64TRUNCDW 1068 OpMIPS64TRUNCFV 1069 OpMIPS64TRUNCDV 1070 OpMIPS64MOVFD 1071 OpMIPS64MOVDF 1072 OpMIPS64CALLstatic 1073 OpMIPS64CALLclosure 1074 OpMIPS64CALLdefer 1075 OpMIPS64CALLgo 1076 OpMIPS64CALLinter 1077 OpMIPS64DUFFZERO 1078 OpMIPS64LoweredZero 1079 OpMIPS64LoweredMove 1080 OpMIPS64LoweredNilCheck 1081 OpMIPS64FPFlagTrue 1082 OpMIPS64FPFlagFalse 1083 OpMIPS64LoweredGetClosurePtr 1084 OpMIPS64MOVVconvert 1085 1086 OpPPC64ADD 1087 OpPPC64ADDconst 1088 OpPPC64FADD 1089 OpPPC64FADDS 1090 OpPPC64SUB 1091 OpPPC64FSUB 1092 OpPPC64FSUBS 1093 OpPPC64MULLD 1094 OpPPC64MULLW 1095 OpPPC64MULHD 1096 OpPPC64MULHW 1097 OpPPC64MULHDU 1098 OpPPC64MULHWU 1099 OpPPC64FMUL 1100 OpPPC64FMULS 1101 OpPPC64SRAD 1102 OpPPC64SRAW 1103 OpPPC64SRD 1104 OpPPC64SRW 1105 OpPPC64SLD 1106 OpPPC64SLW 1107 OpPPC64ADDconstForCarry 1108 OpPPC64MaskIfNotCarry 1109 OpPPC64SRADconst 1110 OpPPC64SRAWconst 1111 OpPPC64SRDconst 1112 OpPPC64SRWconst 1113 OpPPC64SLDconst 1114 OpPPC64SLWconst 1115 OpPPC64FDIV 1116 OpPPC64FDIVS 1117 OpPPC64DIVD 1118 OpPPC64DIVW 1119 OpPPC64DIVDU 1120 OpPPC64DIVWU 1121 OpPPC64FCTIDZ 1122 OpPPC64FCTIWZ 1123 OpPPC64FCFID 1124 OpPPC64FRSP 1125 OpPPC64Xf2i64 1126 OpPPC64Xi2f64 1127 OpPPC64AND 1128 OpPPC64ANDN 1129 OpPPC64OR 1130 OpPPC64ORN 1131 OpPPC64XOR 1132 OpPPC64EQV 1133 OpPPC64NEG 1134 OpPPC64FNEG 1135 OpPPC64FSQRT 1136 OpPPC64FSQRTS 1137 OpPPC64ORconst 1138 OpPPC64XORconst 1139 OpPPC64ANDconst 1140 OpPPC64MOVBreg 1141 OpPPC64MOVBZreg 1142 OpPPC64MOVHreg 1143 OpPPC64MOVHZreg 1144 OpPPC64MOVWreg 1145 OpPPC64MOVWZreg 1146 OpPPC64MOVBload 1147 OpPPC64MOVBZload 1148 OpPPC64MOVHload 1149 OpPPC64MOVHZload 1150 OpPPC64MOVWload 1151 OpPPC64MOVWZload 1152 OpPPC64MOVDload 1153 OpPPC64FMOVDload 1154 OpPPC64FMOVSload 1155 OpPPC64MOVBstore 1156 OpPPC64MOVHstore 1157 OpPPC64MOVWstore 1158 OpPPC64MOVDstore 1159 OpPPC64FMOVDstore 1160 OpPPC64FMOVSstore 1161 OpPPC64MOVBstorezero 1162 OpPPC64MOVHstorezero 1163 OpPPC64MOVWstorezero 1164 OpPPC64MOVDstorezero 1165 OpPPC64MOVDaddr 1166 OpPPC64MOVDconst 1167 OpPPC64MOVWconst 1168 OpPPC64FMOVDconst 1169 OpPPC64FMOVSconst 1170 OpPPC64FCMPU 1171 OpPPC64CMP 1172 OpPPC64CMPU 1173 OpPPC64CMPW 1174 OpPPC64CMPWU 1175 OpPPC64CMPconst 1176 OpPPC64CMPUconst 1177 OpPPC64CMPWconst 1178 OpPPC64CMPWUconst 1179 OpPPC64Equal 1180 OpPPC64NotEqual 1181 OpPPC64LessThan 1182 OpPPC64FLessThan 1183 OpPPC64LessEqual 1184 OpPPC64FLessEqual 1185 OpPPC64GreaterThan 1186 OpPPC64FGreaterThan 1187 OpPPC64GreaterEqual 1188 OpPPC64FGreaterEqual 1189 OpPPC64LoweredGetClosurePtr 1190 OpPPC64LoweredNilCheck 1191 OpPPC64MOVDconvert 1192 OpPPC64CALLstatic 1193 OpPPC64CALLclosure 1194 OpPPC64CALLdefer 1195 OpPPC64CALLgo 1196 OpPPC64CALLinter 1197 OpPPC64LoweredZero 1198 OpPPC64LoweredMove 1199 OpPPC64InvertFlags 1200 OpPPC64FlagEQ 1201 OpPPC64FlagLT 1202 OpPPC64FlagGT 1203 1204 OpAdd8 1205 OpAdd16 1206 OpAdd32 1207 OpAdd64 1208 OpAddPtr 1209 OpAdd32F 1210 OpAdd64F 1211 OpSub8 1212 OpSub16 1213 OpSub32 1214 OpSub64 1215 OpSubPtr 1216 OpSub32F 1217 OpSub64F 1218 OpMul8 1219 OpMul16 1220 OpMul32 1221 OpMul64 1222 OpMul32F 1223 OpMul64F 1224 OpDiv32F 1225 OpDiv64F 1226 OpHmul8 1227 OpHmul8u 1228 OpHmul16 1229 OpHmul16u 1230 OpHmul32 1231 OpHmul32u 1232 OpHmul64 1233 OpHmul64u 1234 OpAvg64u 1235 OpDiv8 1236 OpDiv8u 1237 OpDiv16 1238 OpDiv16u 1239 OpDiv32 1240 OpDiv32u 1241 OpDiv64 1242 OpDiv64u 1243 OpMod8 1244 OpMod8u 1245 OpMod16 1246 OpMod16u 1247 OpMod32 1248 OpMod32u 1249 OpMod64 1250 OpMod64u 1251 OpAnd8 1252 OpAnd16 1253 OpAnd32 1254 OpAnd64 1255 OpOr8 1256 OpOr16 1257 OpOr32 1258 OpOr64 1259 OpXor8 1260 OpXor16 1261 OpXor32 1262 OpXor64 1263 OpLsh8x8 1264 OpLsh8x16 1265 OpLsh8x32 1266 OpLsh8x64 1267 OpLsh16x8 1268 OpLsh16x16 1269 OpLsh16x32 1270 OpLsh16x64 1271 OpLsh32x8 1272 OpLsh32x16 1273 OpLsh32x32 1274 OpLsh32x64 1275 OpLsh64x8 1276 OpLsh64x16 1277 OpLsh64x32 1278 OpLsh64x64 1279 OpRsh8x8 1280 OpRsh8x16 1281 OpRsh8x32 1282 OpRsh8x64 1283 OpRsh16x8 1284 OpRsh16x16 1285 OpRsh16x32 1286 OpRsh16x64 1287 OpRsh32x8 1288 OpRsh32x16 1289 OpRsh32x32 1290 OpRsh32x64 1291 OpRsh64x8 1292 OpRsh64x16 1293 OpRsh64x32 1294 OpRsh64x64 1295 OpRsh8Ux8 1296 OpRsh8Ux16 1297 OpRsh8Ux32 1298 OpRsh8Ux64 1299 OpRsh16Ux8 1300 OpRsh16Ux16 1301 OpRsh16Ux32 1302 OpRsh16Ux64 1303 OpRsh32Ux8 1304 OpRsh32Ux16 1305 OpRsh32Ux32 1306 OpRsh32Ux64 1307 OpRsh64Ux8 1308 OpRsh64Ux16 1309 OpRsh64Ux32 1310 OpRsh64Ux64 1311 OpLrot8 1312 OpLrot16 1313 OpLrot32 1314 OpLrot64 1315 OpEq8 1316 OpEq16 1317 OpEq32 1318 OpEq64 1319 OpEqPtr 1320 OpEqInter 1321 OpEqSlice 1322 OpEq32F 1323 OpEq64F 1324 OpNeq8 1325 OpNeq16 1326 OpNeq32 1327 OpNeq64 1328 OpNeqPtr 1329 OpNeqInter 1330 OpNeqSlice 1331 OpNeq32F 1332 OpNeq64F 1333 OpLess8 1334 OpLess8U 1335 OpLess16 1336 OpLess16U 1337 OpLess32 1338 OpLess32U 1339 OpLess64 1340 OpLess64U 1341 OpLess32F 1342 OpLess64F 1343 OpLeq8 1344 OpLeq8U 1345 OpLeq16 1346 OpLeq16U 1347 OpLeq32 1348 OpLeq32U 1349 OpLeq64 1350 OpLeq64U 1351 OpLeq32F 1352 OpLeq64F 1353 OpGreater8 1354 OpGreater8U 1355 OpGreater16 1356 OpGreater16U 1357 OpGreater32 1358 OpGreater32U 1359 OpGreater64 1360 OpGreater64U 1361 OpGreater32F 1362 OpGreater64F 1363 OpGeq8 1364 OpGeq8U 1365 OpGeq16 1366 OpGeq16U 1367 OpGeq32 1368 OpGeq32U 1369 OpGeq64 1370 OpGeq64U 1371 OpGeq32F 1372 OpGeq64F 1373 OpAndB 1374 OpOrB 1375 OpEqB 1376 OpNeqB 1377 OpNot 1378 OpNeg8 1379 OpNeg16 1380 OpNeg32 1381 OpNeg64 1382 OpNeg32F 1383 OpNeg64F 1384 OpCom8 1385 OpCom16 1386 OpCom32 1387 OpCom64 1388 OpCtz32 1389 OpCtz64 1390 OpBswap32 1391 OpBswap64 1392 OpSqrt 1393 OpPhi 1394 OpCopy 1395 OpConvert 1396 OpConstBool 1397 OpConstString 1398 OpConstNil 1399 OpConst8 1400 OpConst16 1401 OpConst32 1402 OpConst64 1403 OpConst32F 1404 OpConst64F 1405 OpConstInterface 1406 OpConstSlice 1407 OpInitMem 1408 OpArg 1409 OpAddr 1410 OpSP 1411 OpSB 1412 OpFunc 1413 OpLoad 1414 OpStore 1415 OpMove 1416 OpZero 1417 OpClosureCall 1418 OpStaticCall 1419 OpDeferCall 1420 OpGoCall 1421 OpInterCall 1422 OpSignExt8to16 1423 OpSignExt8to32 1424 OpSignExt8to64 1425 OpSignExt16to32 1426 OpSignExt16to64 1427 OpSignExt32to64 1428 OpZeroExt8to16 1429 OpZeroExt8to32 1430 OpZeroExt8to64 1431 OpZeroExt16to32 1432 OpZeroExt16to64 1433 OpZeroExt32to64 1434 OpTrunc16to8 1435 OpTrunc32to8 1436 OpTrunc32to16 1437 OpTrunc64to8 1438 OpTrunc64to16 1439 OpTrunc64to32 1440 OpCvt32to32F 1441 OpCvt32to64F 1442 OpCvt64to32F 1443 OpCvt64to64F 1444 OpCvt32Fto32 1445 OpCvt32Fto64 1446 OpCvt64Fto32 1447 OpCvt64Fto64 1448 OpCvt32Fto64F 1449 OpCvt64Fto32F 1450 OpIsNonNil 1451 OpIsInBounds 1452 OpIsSliceInBounds 1453 OpNilCheck 1454 OpGetG 1455 OpGetClosurePtr 1456 OpArrayIndex 1457 OpPtrIndex 1458 OpOffPtr 1459 OpSliceMake 1460 OpSlicePtr 1461 OpSliceLen 1462 OpSliceCap 1463 OpComplexMake 1464 OpComplexReal 1465 OpComplexImag 1466 OpStringMake 1467 OpStringPtr 1468 OpStringLen 1469 OpIMake 1470 OpITab 1471 OpIData 1472 OpStructMake0 1473 OpStructMake1 1474 OpStructMake2 1475 OpStructMake3 1476 OpStructMake4 1477 OpStructSelect 1478 OpStoreReg 1479 OpLoadReg 1480 OpFwdRef 1481 OpUnknown 1482 OpVarDef 1483 OpVarKill 1484 OpVarLive 1485 OpKeepAlive 1486 OpInt64Make 1487 OpInt64Hi 1488 OpInt64Lo 1489 OpAdd32carry 1490 OpAdd32withcarry 1491 OpSub32carry 1492 OpSub32withcarry 1493 OpMul32uhilo 1494 OpSignmask 1495 OpZeromask 1496 OpCvt32Uto32F 1497 OpCvt32Uto64F 1498 OpCvt32Fto32U 1499 OpCvt64Fto32U 1500 OpCvt64Uto32F 1501 OpCvt64Uto64F 1502 OpCvt32Fto64U 1503 OpCvt64Fto64U 1504 OpSelect0 1505 OpSelect1 1506 OpAtomicLoad32 1507 OpAtomicLoad64 1508 OpAtomicLoadPtr 1509 OpAtomicStore32 1510 OpAtomicStore64 1511 OpAtomicStorePtrNoWB 1512 OpAtomicExchange32 1513 OpAtomicExchange64 1514 OpAtomicAdd32 1515 OpAtomicAdd64 1516 OpAtomicCompareAndSwap32 1517 OpAtomicCompareAndSwap64 1518 OpAtomicAnd8 1519 OpAtomicOr8 1520 ) 1521 1522 var opcodeTable = [...]opInfo{ 1523 {name: "OpInvalid"}, 1524 1525 { 1526 name: "ADDSS", 1527 argLen: 2, 1528 commutative: true, 1529 resultInArg0: true, 1530 asm: x86.AADDSS, 1531 reg: regInfo{ 1532 inputs: []inputInfo{ 1533 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1534 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1535 }, 1536 outputs: []outputInfo{ 1537 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1538 }, 1539 }, 1540 }, 1541 { 1542 name: "ADDSD", 1543 argLen: 2, 1544 commutative: true, 1545 resultInArg0: true, 1546 asm: x86.AADDSD, 1547 reg: regInfo{ 1548 inputs: []inputInfo{ 1549 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1550 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1551 }, 1552 outputs: []outputInfo{ 1553 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1554 }, 1555 }, 1556 }, 1557 { 1558 name: "SUBSS", 1559 argLen: 2, 1560 resultInArg0: true, 1561 asm: x86.ASUBSS, 1562 reg: regInfo{ 1563 inputs: []inputInfo{ 1564 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1565 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1566 }, 1567 clobbers: 32768, // X7 1568 outputs: []outputInfo{ 1569 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1570 }, 1571 }, 1572 }, 1573 { 1574 name: "SUBSD", 1575 argLen: 2, 1576 resultInArg0: true, 1577 asm: x86.ASUBSD, 1578 reg: regInfo{ 1579 inputs: []inputInfo{ 1580 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1581 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1582 }, 1583 clobbers: 32768, // X7 1584 outputs: []outputInfo{ 1585 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1586 }, 1587 }, 1588 }, 1589 { 1590 name: "MULSS", 1591 argLen: 2, 1592 commutative: true, 1593 resultInArg0: true, 1594 asm: x86.AMULSS, 1595 reg: regInfo{ 1596 inputs: []inputInfo{ 1597 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1598 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1599 }, 1600 outputs: []outputInfo{ 1601 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1602 }, 1603 }, 1604 }, 1605 { 1606 name: "MULSD", 1607 argLen: 2, 1608 commutative: true, 1609 resultInArg0: true, 1610 asm: x86.AMULSD, 1611 reg: regInfo{ 1612 inputs: []inputInfo{ 1613 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1614 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1615 }, 1616 outputs: []outputInfo{ 1617 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1618 }, 1619 }, 1620 }, 1621 { 1622 name: "DIVSS", 1623 argLen: 2, 1624 resultInArg0: true, 1625 asm: x86.ADIVSS, 1626 reg: regInfo{ 1627 inputs: []inputInfo{ 1628 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1629 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1630 }, 1631 clobbers: 32768, // X7 1632 outputs: []outputInfo{ 1633 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1634 }, 1635 }, 1636 }, 1637 { 1638 name: "DIVSD", 1639 argLen: 2, 1640 resultInArg0: true, 1641 asm: x86.ADIVSD, 1642 reg: regInfo{ 1643 inputs: []inputInfo{ 1644 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1645 {1, 32512}, // X0 X1 X2 X3 X4 X5 X6 1646 }, 1647 clobbers: 32768, // X7 1648 outputs: []outputInfo{ 1649 {0, 32512}, // X0 X1 X2 X3 X4 X5 X6 1650 }, 1651 }, 1652 }, 1653 { 1654 name: "MOVSSload", 1655 auxType: auxSymOff, 1656 argLen: 2, 1657 asm: x86.AMOVSS, 1658 reg: regInfo{ 1659 inputs: []inputInfo{ 1660 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1661 }, 1662 outputs: []outputInfo{ 1663 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1664 }, 1665 }, 1666 }, 1667 { 1668 name: "MOVSDload", 1669 auxType: auxSymOff, 1670 argLen: 2, 1671 asm: x86.AMOVSD, 1672 reg: regInfo{ 1673 inputs: []inputInfo{ 1674 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1675 }, 1676 outputs: []outputInfo{ 1677 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1678 }, 1679 }, 1680 }, 1681 { 1682 name: "MOVSSconst", 1683 auxType: auxFloat32, 1684 argLen: 0, 1685 rematerializeable: true, 1686 asm: x86.AMOVSS, 1687 reg: regInfo{ 1688 outputs: []outputInfo{ 1689 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1690 }, 1691 }, 1692 }, 1693 { 1694 name: "MOVSDconst", 1695 auxType: auxFloat64, 1696 argLen: 0, 1697 rematerializeable: true, 1698 asm: x86.AMOVSD, 1699 reg: regInfo{ 1700 outputs: []outputInfo{ 1701 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1702 }, 1703 }, 1704 }, 1705 { 1706 name: "MOVSSloadidx1", 1707 auxType: auxSymOff, 1708 argLen: 3, 1709 asm: x86.AMOVSS, 1710 reg: regInfo{ 1711 inputs: []inputInfo{ 1712 {1, 255}, // AX CX DX BX SP BP SI DI 1713 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1714 }, 1715 outputs: []outputInfo{ 1716 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1717 }, 1718 }, 1719 }, 1720 { 1721 name: "MOVSSloadidx4", 1722 auxType: auxSymOff, 1723 argLen: 3, 1724 asm: x86.AMOVSS, 1725 reg: regInfo{ 1726 inputs: []inputInfo{ 1727 {1, 255}, // AX CX DX BX SP BP SI DI 1728 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1729 }, 1730 outputs: []outputInfo{ 1731 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1732 }, 1733 }, 1734 }, 1735 { 1736 name: "MOVSDloadidx1", 1737 auxType: auxSymOff, 1738 argLen: 3, 1739 asm: x86.AMOVSD, 1740 reg: regInfo{ 1741 inputs: []inputInfo{ 1742 {1, 255}, // AX CX DX BX SP BP SI DI 1743 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1744 }, 1745 outputs: []outputInfo{ 1746 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1747 }, 1748 }, 1749 }, 1750 { 1751 name: "MOVSDloadidx8", 1752 auxType: auxSymOff, 1753 argLen: 3, 1754 asm: x86.AMOVSD, 1755 reg: regInfo{ 1756 inputs: []inputInfo{ 1757 {1, 255}, // AX CX DX BX SP BP SI DI 1758 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1759 }, 1760 outputs: []outputInfo{ 1761 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1762 }, 1763 }, 1764 }, 1765 { 1766 name: "MOVSSstore", 1767 auxType: auxSymOff, 1768 argLen: 3, 1769 asm: x86.AMOVSS, 1770 reg: regInfo{ 1771 inputs: []inputInfo{ 1772 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1773 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1774 }, 1775 }, 1776 }, 1777 { 1778 name: "MOVSDstore", 1779 auxType: auxSymOff, 1780 argLen: 3, 1781 asm: x86.AMOVSD, 1782 reg: regInfo{ 1783 inputs: []inputInfo{ 1784 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1785 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1786 }, 1787 }, 1788 }, 1789 { 1790 name: "MOVSSstoreidx1", 1791 auxType: auxSymOff, 1792 argLen: 4, 1793 asm: x86.AMOVSS, 1794 reg: regInfo{ 1795 inputs: []inputInfo{ 1796 {1, 255}, // AX CX DX BX SP BP SI DI 1797 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1798 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1799 }, 1800 }, 1801 }, 1802 { 1803 name: "MOVSSstoreidx4", 1804 auxType: auxSymOff, 1805 argLen: 4, 1806 asm: x86.AMOVSS, 1807 reg: regInfo{ 1808 inputs: []inputInfo{ 1809 {1, 255}, // AX CX DX BX SP BP SI DI 1810 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1811 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1812 }, 1813 }, 1814 }, 1815 { 1816 name: "MOVSDstoreidx1", 1817 auxType: auxSymOff, 1818 argLen: 4, 1819 asm: x86.AMOVSD, 1820 reg: regInfo{ 1821 inputs: []inputInfo{ 1822 {1, 255}, // AX CX DX BX SP BP SI DI 1823 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1824 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1825 }, 1826 }, 1827 }, 1828 { 1829 name: "MOVSDstoreidx8", 1830 auxType: auxSymOff, 1831 argLen: 4, 1832 asm: x86.AMOVSD, 1833 reg: regInfo{ 1834 inputs: []inputInfo{ 1835 {1, 255}, // AX CX DX BX SP BP SI DI 1836 {2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 1837 {0, 65791}, // AX CX DX BX SP BP SI DI SB 1838 }, 1839 }, 1840 }, 1841 { 1842 name: "ADDL", 1843 argLen: 2, 1844 commutative: true, 1845 clobberFlags: true, 1846 asm: x86.AADDL, 1847 reg: regInfo{ 1848 inputs: []inputInfo{ 1849 {1, 239}, // AX CX DX BX BP SI DI 1850 {0, 255}, // AX CX DX BX SP BP SI DI 1851 }, 1852 outputs: []outputInfo{ 1853 {0, 239}, // AX CX DX BX BP SI DI 1854 }, 1855 }, 1856 }, 1857 { 1858 name: "ADDLconst", 1859 auxType: auxInt32, 1860 argLen: 1, 1861 clobberFlags: true, 1862 asm: x86.AADDL, 1863 reg: regInfo{ 1864 inputs: []inputInfo{ 1865 {0, 255}, // AX CX DX BX SP BP SI DI 1866 }, 1867 outputs: []outputInfo{ 1868 {0, 239}, // AX CX DX BX BP SI DI 1869 }, 1870 }, 1871 }, 1872 { 1873 name: "ADDLcarry", 1874 argLen: 2, 1875 commutative: true, 1876 resultInArg0: true, 1877 asm: x86.AADDL, 1878 reg: regInfo{ 1879 inputs: []inputInfo{ 1880 {0, 239}, // AX CX DX BX BP SI DI 1881 {1, 239}, // AX CX DX BX BP SI DI 1882 }, 1883 outputs: []outputInfo{ 1884 {1, 0}, 1885 {0, 239}, // AX CX DX BX BP SI DI 1886 }, 1887 }, 1888 }, 1889 { 1890 name: "ADDLconstcarry", 1891 auxType: auxInt32, 1892 argLen: 1, 1893 resultInArg0: true, 1894 asm: x86.AADDL, 1895 reg: regInfo{ 1896 inputs: []inputInfo{ 1897 {0, 239}, // AX CX DX BX BP SI DI 1898 }, 1899 outputs: []outputInfo{ 1900 {1, 0}, 1901 {0, 239}, // AX CX DX BX BP SI DI 1902 }, 1903 }, 1904 }, 1905 { 1906 name: "ADCL", 1907 argLen: 3, 1908 commutative: true, 1909 resultInArg0: true, 1910 clobberFlags: true, 1911 asm: x86.AADCL, 1912 reg: regInfo{ 1913 inputs: []inputInfo{ 1914 {0, 239}, // AX CX DX BX BP SI DI 1915 {1, 239}, // AX CX DX BX BP SI DI 1916 }, 1917 outputs: []outputInfo{ 1918 {0, 239}, // AX CX DX BX BP SI DI 1919 }, 1920 }, 1921 }, 1922 { 1923 name: "ADCLconst", 1924 auxType: auxInt32, 1925 argLen: 2, 1926 resultInArg0: true, 1927 clobberFlags: true, 1928 asm: x86.AADCL, 1929 reg: regInfo{ 1930 inputs: []inputInfo{ 1931 {0, 239}, // AX CX DX BX BP SI DI 1932 }, 1933 outputs: []outputInfo{ 1934 {0, 239}, // AX CX DX BX BP SI DI 1935 }, 1936 }, 1937 }, 1938 { 1939 name: "SUBL", 1940 argLen: 2, 1941 resultInArg0: true, 1942 clobberFlags: true, 1943 asm: x86.ASUBL, 1944 reg: regInfo{ 1945 inputs: []inputInfo{ 1946 {0, 239}, // AX CX DX BX BP SI DI 1947 {1, 239}, // AX CX DX BX BP SI DI 1948 }, 1949 outputs: []outputInfo{ 1950 {0, 239}, // AX CX DX BX BP SI DI 1951 }, 1952 }, 1953 }, 1954 { 1955 name: "SUBLconst", 1956 auxType: auxInt32, 1957 argLen: 1, 1958 resultInArg0: true, 1959 clobberFlags: true, 1960 asm: x86.ASUBL, 1961 reg: regInfo{ 1962 inputs: []inputInfo{ 1963 {0, 239}, // AX CX DX BX BP SI DI 1964 }, 1965 outputs: []outputInfo{ 1966 {0, 239}, // AX CX DX BX BP SI DI 1967 }, 1968 }, 1969 }, 1970 { 1971 name: "SUBLcarry", 1972 argLen: 2, 1973 resultInArg0: true, 1974 asm: x86.ASUBL, 1975 reg: regInfo{ 1976 inputs: []inputInfo{ 1977 {0, 239}, // AX CX DX BX BP SI DI 1978 {1, 239}, // AX CX DX BX BP SI DI 1979 }, 1980 outputs: []outputInfo{ 1981 {1, 0}, 1982 {0, 239}, // AX CX DX BX BP SI DI 1983 }, 1984 }, 1985 }, 1986 { 1987 name: "SUBLconstcarry", 1988 auxType: auxInt32, 1989 argLen: 1, 1990 resultInArg0: true, 1991 asm: x86.ASUBL, 1992 reg: regInfo{ 1993 inputs: []inputInfo{ 1994 {0, 239}, // AX CX DX BX BP SI DI 1995 }, 1996 outputs: []outputInfo{ 1997 {1, 0}, 1998 {0, 239}, // AX CX DX BX BP SI DI 1999 }, 2000 }, 2001 }, 2002 { 2003 name: "SBBL", 2004 argLen: 3, 2005 resultInArg0: true, 2006 clobberFlags: true, 2007 asm: x86.ASBBL, 2008 reg: regInfo{ 2009 inputs: []inputInfo{ 2010 {0, 239}, // AX CX DX BX BP SI DI 2011 {1, 239}, // AX CX DX BX BP SI DI 2012 }, 2013 outputs: []outputInfo{ 2014 {0, 239}, // AX CX DX BX BP SI DI 2015 }, 2016 }, 2017 }, 2018 { 2019 name: "SBBLconst", 2020 auxType: auxInt32, 2021 argLen: 2, 2022 resultInArg0: true, 2023 clobberFlags: true, 2024 asm: x86.ASBBL, 2025 reg: regInfo{ 2026 inputs: []inputInfo{ 2027 {0, 239}, // AX CX DX BX BP SI DI 2028 }, 2029 outputs: []outputInfo{ 2030 {0, 239}, // AX CX DX BX BP SI DI 2031 }, 2032 }, 2033 }, 2034 { 2035 name: "MULL", 2036 argLen: 2, 2037 commutative: true, 2038 resultInArg0: true, 2039 clobberFlags: true, 2040 asm: x86.AIMULL, 2041 reg: regInfo{ 2042 inputs: []inputInfo{ 2043 {0, 239}, // AX CX DX BX BP SI DI 2044 {1, 239}, // AX CX DX BX BP SI DI 2045 }, 2046 outputs: []outputInfo{ 2047 {0, 239}, // AX CX DX BX BP SI DI 2048 }, 2049 }, 2050 }, 2051 { 2052 name: "MULLconst", 2053 auxType: auxInt32, 2054 argLen: 1, 2055 resultInArg0: true, 2056 clobberFlags: true, 2057 asm: x86.AIMULL, 2058 reg: regInfo{ 2059 inputs: []inputInfo{ 2060 {0, 239}, // AX CX DX BX BP SI DI 2061 }, 2062 outputs: []outputInfo{ 2063 {0, 239}, // AX CX DX BX BP SI DI 2064 }, 2065 }, 2066 }, 2067 { 2068 name: "HMULL", 2069 argLen: 2, 2070 clobberFlags: true, 2071 asm: x86.AIMULL, 2072 reg: regInfo{ 2073 inputs: []inputInfo{ 2074 {0, 1}, // AX 2075 {1, 255}, // AX CX DX BX SP BP SI DI 2076 }, 2077 clobbers: 1, // AX 2078 outputs: []outputInfo{ 2079 {0, 4}, // DX 2080 }, 2081 }, 2082 }, 2083 { 2084 name: "HMULLU", 2085 argLen: 2, 2086 clobberFlags: true, 2087 asm: x86.AMULL, 2088 reg: regInfo{ 2089 inputs: []inputInfo{ 2090 {0, 1}, // AX 2091 {1, 255}, // AX CX DX BX SP BP SI DI 2092 }, 2093 clobbers: 1, // AX 2094 outputs: []outputInfo{ 2095 {0, 4}, // DX 2096 }, 2097 }, 2098 }, 2099 { 2100 name: "HMULW", 2101 argLen: 2, 2102 clobberFlags: true, 2103 asm: x86.AIMULW, 2104 reg: regInfo{ 2105 inputs: []inputInfo{ 2106 {0, 1}, // AX 2107 {1, 255}, // AX CX DX BX SP BP SI DI 2108 }, 2109 clobbers: 1, // AX 2110 outputs: []outputInfo{ 2111 {0, 4}, // DX 2112 }, 2113 }, 2114 }, 2115 { 2116 name: "HMULB", 2117 argLen: 2, 2118 clobberFlags: true, 2119 asm: x86.AIMULB, 2120 reg: regInfo{ 2121 inputs: []inputInfo{ 2122 {0, 1}, // AX 2123 {1, 255}, // AX CX DX BX SP BP SI DI 2124 }, 2125 clobbers: 1, // AX 2126 outputs: []outputInfo{ 2127 {0, 4}, // DX 2128 }, 2129 }, 2130 }, 2131 { 2132 name: "HMULWU", 2133 argLen: 2, 2134 clobberFlags: true, 2135 asm: x86.AMULW, 2136 reg: regInfo{ 2137 inputs: []inputInfo{ 2138 {0, 1}, // AX 2139 {1, 255}, // AX CX DX BX SP BP SI DI 2140 }, 2141 clobbers: 1, // AX 2142 outputs: []outputInfo{ 2143 {0, 4}, // DX 2144 }, 2145 }, 2146 }, 2147 { 2148 name: "HMULBU", 2149 argLen: 2, 2150 clobberFlags: true, 2151 asm: x86.AMULB, 2152 reg: regInfo{ 2153 inputs: []inputInfo{ 2154 {0, 1}, // AX 2155 {1, 255}, // AX CX DX BX SP BP SI DI 2156 }, 2157 clobbers: 1, // AX 2158 outputs: []outputInfo{ 2159 {0, 4}, // DX 2160 }, 2161 }, 2162 }, 2163 { 2164 name: "MULLQU", 2165 argLen: 2, 2166 clobberFlags: true, 2167 asm: x86.AMULL, 2168 reg: regInfo{ 2169 inputs: []inputInfo{ 2170 {0, 1}, // AX 2171 {1, 255}, // AX CX DX BX SP BP SI DI 2172 }, 2173 outputs: []outputInfo{ 2174 {0, 4}, // DX 2175 {1, 1}, // AX 2176 }, 2177 }, 2178 }, 2179 { 2180 name: "DIVL", 2181 argLen: 2, 2182 clobberFlags: true, 2183 asm: x86.AIDIVL, 2184 reg: regInfo{ 2185 inputs: []inputInfo{ 2186 {0, 1}, // AX 2187 {1, 251}, // AX CX BX SP BP SI DI 2188 }, 2189 clobbers: 4, // DX 2190 outputs: []outputInfo{ 2191 {0, 1}, // AX 2192 }, 2193 }, 2194 }, 2195 { 2196 name: "DIVW", 2197 argLen: 2, 2198 clobberFlags: true, 2199 asm: x86.AIDIVW, 2200 reg: regInfo{ 2201 inputs: []inputInfo{ 2202 {0, 1}, // AX 2203 {1, 251}, // AX CX BX SP BP SI DI 2204 }, 2205 clobbers: 4, // DX 2206 outputs: []outputInfo{ 2207 {0, 1}, // AX 2208 }, 2209 }, 2210 }, 2211 { 2212 name: "DIVLU", 2213 argLen: 2, 2214 clobberFlags: true, 2215 asm: x86.ADIVL, 2216 reg: regInfo{ 2217 inputs: []inputInfo{ 2218 {0, 1}, // AX 2219 {1, 251}, // AX CX BX SP BP SI DI 2220 }, 2221 clobbers: 4, // DX 2222 outputs: []outputInfo{ 2223 {0, 1}, // AX 2224 }, 2225 }, 2226 }, 2227 { 2228 name: "DIVWU", 2229 argLen: 2, 2230 clobberFlags: true, 2231 asm: x86.ADIVW, 2232 reg: regInfo{ 2233 inputs: []inputInfo{ 2234 {0, 1}, // AX 2235 {1, 251}, // AX CX BX SP BP SI DI 2236 }, 2237 clobbers: 4, // DX 2238 outputs: []outputInfo{ 2239 {0, 1}, // AX 2240 }, 2241 }, 2242 }, 2243 { 2244 name: "MODL", 2245 argLen: 2, 2246 clobberFlags: true, 2247 asm: x86.AIDIVL, 2248 reg: regInfo{ 2249 inputs: []inputInfo{ 2250 {0, 1}, // AX 2251 {1, 251}, // AX CX BX SP BP SI DI 2252 }, 2253 clobbers: 1, // AX 2254 outputs: []outputInfo{ 2255 {0, 4}, // DX 2256 }, 2257 }, 2258 }, 2259 { 2260 name: "MODW", 2261 argLen: 2, 2262 clobberFlags: true, 2263 asm: x86.AIDIVW, 2264 reg: regInfo{ 2265 inputs: []inputInfo{ 2266 {0, 1}, // AX 2267 {1, 251}, // AX CX BX SP BP SI DI 2268 }, 2269 clobbers: 1, // AX 2270 outputs: []outputInfo{ 2271 {0, 4}, // DX 2272 }, 2273 }, 2274 }, 2275 { 2276 name: "MODLU", 2277 argLen: 2, 2278 clobberFlags: true, 2279 asm: x86.ADIVL, 2280 reg: regInfo{ 2281 inputs: []inputInfo{ 2282 {0, 1}, // AX 2283 {1, 251}, // AX CX BX SP BP SI DI 2284 }, 2285 clobbers: 1, // AX 2286 outputs: []outputInfo{ 2287 {0, 4}, // DX 2288 }, 2289 }, 2290 }, 2291 { 2292 name: "MODWU", 2293 argLen: 2, 2294 clobberFlags: true, 2295 asm: x86.ADIVW, 2296 reg: regInfo{ 2297 inputs: []inputInfo{ 2298 {0, 1}, // AX 2299 {1, 251}, // AX CX BX SP BP SI DI 2300 }, 2301 clobbers: 1, // AX 2302 outputs: []outputInfo{ 2303 {0, 4}, // DX 2304 }, 2305 }, 2306 }, 2307 { 2308 name: "ANDL", 2309 argLen: 2, 2310 commutative: true, 2311 resultInArg0: true, 2312 clobberFlags: true, 2313 asm: x86.AANDL, 2314 reg: regInfo{ 2315 inputs: []inputInfo{ 2316 {0, 239}, // AX CX DX BX BP SI DI 2317 {1, 239}, // AX CX DX BX BP SI DI 2318 }, 2319 outputs: []outputInfo{ 2320 {0, 239}, // AX CX DX BX BP SI DI 2321 }, 2322 }, 2323 }, 2324 { 2325 name: "ANDLconst", 2326 auxType: auxInt32, 2327 argLen: 1, 2328 resultInArg0: true, 2329 clobberFlags: true, 2330 asm: x86.AANDL, 2331 reg: regInfo{ 2332 inputs: []inputInfo{ 2333 {0, 239}, // AX CX DX BX BP SI DI 2334 }, 2335 outputs: []outputInfo{ 2336 {0, 239}, // AX CX DX BX BP SI DI 2337 }, 2338 }, 2339 }, 2340 { 2341 name: "ORL", 2342 argLen: 2, 2343 commutative: true, 2344 resultInArg0: true, 2345 clobberFlags: true, 2346 asm: x86.AORL, 2347 reg: regInfo{ 2348 inputs: []inputInfo{ 2349 {0, 239}, // AX CX DX BX BP SI DI 2350 {1, 239}, // AX CX DX BX BP SI DI 2351 }, 2352 outputs: []outputInfo{ 2353 {0, 239}, // AX CX DX BX BP SI DI 2354 }, 2355 }, 2356 }, 2357 { 2358 name: "ORLconst", 2359 auxType: auxInt32, 2360 argLen: 1, 2361 resultInArg0: true, 2362 clobberFlags: true, 2363 asm: x86.AORL, 2364 reg: regInfo{ 2365 inputs: []inputInfo{ 2366 {0, 239}, // AX CX DX BX BP SI DI 2367 }, 2368 outputs: []outputInfo{ 2369 {0, 239}, // AX CX DX BX BP SI DI 2370 }, 2371 }, 2372 }, 2373 { 2374 name: "XORL", 2375 argLen: 2, 2376 commutative: true, 2377 resultInArg0: true, 2378 clobberFlags: true, 2379 asm: x86.AXORL, 2380 reg: regInfo{ 2381 inputs: []inputInfo{ 2382 {0, 239}, // AX CX DX BX BP SI DI 2383 {1, 239}, // AX CX DX BX BP SI DI 2384 }, 2385 outputs: []outputInfo{ 2386 {0, 239}, // AX CX DX BX BP SI DI 2387 }, 2388 }, 2389 }, 2390 { 2391 name: "XORLconst", 2392 auxType: auxInt32, 2393 argLen: 1, 2394 resultInArg0: true, 2395 clobberFlags: true, 2396 asm: x86.AXORL, 2397 reg: regInfo{ 2398 inputs: []inputInfo{ 2399 {0, 239}, // AX CX DX BX BP SI DI 2400 }, 2401 outputs: []outputInfo{ 2402 {0, 239}, // AX CX DX BX BP SI DI 2403 }, 2404 }, 2405 }, 2406 { 2407 name: "CMPL", 2408 argLen: 2, 2409 asm: x86.ACMPL, 2410 reg: regInfo{ 2411 inputs: []inputInfo{ 2412 {0, 255}, // AX CX DX BX SP BP SI DI 2413 {1, 255}, // AX CX DX BX SP BP SI DI 2414 }, 2415 }, 2416 }, 2417 { 2418 name: "CMPW", 2419 argLen: 2, 2420 asm: x86.ACMPW, 2421 reg: regInfo{ 2422 inputs: []inputInfo{ 2423 {0, 255}, // AX CX DX BX SP BP SI DI 2424 {1, 255}, // AX CX DX BX SP BP SI DI 2425 }, 2426 }, 2427 }, 2428 { 2429 name: "CMPB", 2430 argLen: 2, 2431 asm: x86.ACMPB, 2432 reg: regInfo{ 2433 inputs: []inputInfo{ 2434 {0, 255}, // AX CX DX BX SP BP SI DI 2435 {1, 255}, // AX CX DX BX SP BP SI DI 2436 }, 2437 }, 2438 }, 2439 { 2440 name: "CMPLconst", 2441 auxType: auxInt32, 2442 argLen: 1, 2443 asm: x86.ACMPL, 2444 reg: regInfo{ 2445 inputs: []inputInfo{ 2446 {0, 255}, // AX CX DX BX SP BP SI DI 2447 }, 2448 }, 2449 }, 2450 { 2451 name: "CMPWconst", 2452 auxType: auxInt16, 2453 argLen: 1, 2454 asm: x86.ACMPW, 2455 reg: regInfo{ 2456 inputs: []inputInfo{ 2457 {0, 255}, // AX CX DX BX SP BP SI DI 2458 }, 2459 }, 2460 }, 2461 { 2462 name: "CMPBconst", 2463 auxType: auxInt8, 2464 argLen: 1, 2465 asm: x86.ACMPB, 2466 reg: regInfo{ 2467 inputs: []inputInfo{ 2468 {0, 255}, // AX CX DX BX SP BP SI DI 2469 }, 2470 }, 2471 }, 2472 { 2473 name: "UCOMISS", 2474 argLen: 2, 2475 asm: x86.AUCOMISS, 2476 reg: regInfo{ 2477 inputs: []inputInfo{ 2478 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2479 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2480 }, 2481 }, 2482 }, 2483 { 2484 name: "UCOMISD", 2485 argLen: 2, 2486 asm: x86.AUCOMISD, 2487 reg: regInfo{ 2488 inputs: []inputInfo{ 2489 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2490 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2491 }, 2492 }, 2493 }, 2494 { 2495 name: "TESTL", 2496 argLen: 2, 2497 asm: x86.ATESTL, 2498 reg: regInfo{ 2499 inputs: []inputInfo{ 2500 {0, 255}, // AX CX DX BX SP BP SI DI 2501 {1, 255}, // AX CX DX BX SP BP SI DI 2502 }, 2503 }, 2504 }, 2505 { 2506 name: "TESTW", 2507 argLen: 2, 2508 asm: x86.ATESTW, 2509 reg: regInfo{ 2510 inputs: []inputInfo{ 2511 {0, 255}, // AX CX DX BX SP BP SI DI 2512 {1, 255}, // AX CX DX BX SP BP SI DI 2513 }, 2514 }, 2515 }, 2516 { 2517 name: "TESTB", 2518 argLen: 2, 2519 asm: x86.ATESTB, 2520 reg: regInfo{ 2521 inputs: []inputInfo{ 2522 {0, 255}, // AX CX DX BX SP BP SI DI 2523 {1, 255}, // AX CX DX BX SP BP SI DI 2524 }, 2525 }, 2526 }, 2527 { 2528 name: "TESTLconst", 2529 auxType: auxInt32, 2530 argLen: 1, 2531 asm: x86.ATESTL, 2532 reg: regInfo{ 2533 inputs: []inputInfo{ 2534 {0, 255}, // AX CX DX BX SP BP SI DI 2535 }, 2536 }, 2537 }, 2538 { 2539 name: "TESTWconst", 2540 auxType: auxInt16, 2541 argLen: 1, 2542 asm: x86.ATESTW, 2543 reg: regInfo{ 2544 inputs: []inputInfo{ 2545 {0, 255}, // AX CX DX BX SP BP SI DI 2546 }, 2547 }, 2548 }, 2549 { 2550 name: "TESTBconst", 2551 auxType: auxInt8, 2552 argLen: 1, 2553 asm: x86.ATESTB, 2554 reg: regInfo{ 2555 inputs: []inputInfo{ 2556 {0, 255}, // AX CX DX BX SP BP SI DI 2557 }, 2558 }, 2559 }, 2560 { 2561 name: "SHLL", 2562 argLen: 2, 2563 resultInArg0: true, 2564 clobberFlags: true, 2565 asm: x86.ASHLL, 2566 reg: regInfo{ 2567 inputs: []inputInfo{ 2568 {1, 2}, // CX 2569 {0, 239}, // AX CX DX BX BP SI DI 2570 }, 2571 outputs: []outputInfo{ 2572 {0, 239}, // AX CX DX BX BP SI DI 2573 }, 2574 }, 2575 }, 2576 { 2577 name: "SHLLconst", 2578 auxType: auxInt32, 2579 argLen: 1, 2580 resultInArg0: true, 2581 clobberFlags: true, 2582 asm: x86.ASHLL, 2583 reg: regInfo{ 2584 inputs: []inputInfo{ 2585 {0, 239}, // AX CX DX BX BP SI DI 2586 }, 2587 outputs: []outputInfo{ 2588 {0, 239}, // AX CX DX BX BP SI DI 2589 }, 2590 }, 2591 }, 2592 { 2593 name: "SHRL", 2594 argLen: 2, 2595 resultInArg0: true, 2596 clobberFlags: true, 2597 asm: x86.ASHRL, 2598 reg: regInfo{ 2599 inputs: []inputInfo{ 2600 {1, 2}, // CX 2601 {0, 239}, // AX CX DX BX BP SI DI 2602 }, 2603 outputs: []outputInfo{ 2604 {0, 239}, // AX CX DX BX BP SI DI 2605 }, 2606 }, 2607 }, 2608 { 2609 name: "SHRW", 2610 argLen: 2, 2611 resultInArg0: true, 2612 clobberFlags: true, 2613 asm: x86.ASHRW, 2614 reg: regInfo{ 2615 inputs: []inputInfo{ 2616 {1, 2}, // CX 2617 {0, 239}, // AX CX DX BX BP SI DI 2618 }, 2619 outputs: []outputInfo{ 2620 {0, 239}, // AX CX DX BX BP SI DI 2621 }, 2622 }, 2623 }, 2624 { 2625 name: "SHRB", 2626 argLen: 2, 2627 resultInArg0: true, 2628 clobberFlags: true, 2629 asm: x86.ASHRB, 2630 reg: regInfo{ 2631 inputs: []inputInfo{ 2632 {1, 2}, // CX 2633 {0, 239}, // AX CX DX BX BP SI DI 2634 }, 2635 outputs: []outputInfo{ 2636 {0, 239}, // AX CX DX BX BP SI DI 2637 }, 2638 }, 2639 }, 2640 { 2641 name: "SHRLconst", 2642 auxType: auxInt32, 2643 argLen: 1, 2644 resultInArg0: true, 2645 clobberFlags: true, 2646 asm: x86.ASHRL, 2647 reg: regInfo{ 2648 inputs: []inputInfo{ 2649 {0, 239}, // AX CX DX BX BP SI DI 2650 }, 2651 outputs: []outputInfo{ 2652 {0, 239}, // AX CX DX BX BP SI DI 2653 }, 2654 }, 2655 }, 2656 { 2657 name: "SHRWconst", 2658 auxType: auxInt16, 2659 argLen: 1, 2660 resultInArg0: true, 2661 clobberFlags: true, 2662 asm: x86.ASHRW, 2663 reg: regInfo{ 2664 inputs: []inputInfo{ 2665 {0, 239}, // AX CX DX BX BP SI DI 2666 }, 2667 outputs: []outputInfo{ 2668 {0, 239}, // AX CX DX BX BP SI DI 2669 }, 2670 }, 2671 }, 2672 { 2673 name: "SHRBconst", 2674 auxType: auxInt8, 2675 argLen: 1, 2676 resultInArg0: true, 2677 clobberFlags: true, 2678 asm: x86.ASHRB, 2679 reg: regInfo{ 2680 inputs: []inputInfo{ 2681 {0, 239}, // AX CX DX BX BP SI DI 2682 }, 2683 outputs: []outputInfo{ 2684 {0, 239}, // AX CX DX BX BP SI DI 2685 }, 2686 }, 2687 }, 2688 { 2689 name: "SARL", 2690 argLen: 2, 2691 resultInArg0: true, 2692 clobberFlags: true, 2693 asm: x86.ASARL, 2694 reg: regInfo{ 2695 inputs: []inputInfo{ 2696 {1, 2}, // CX 2697 {0, 239}, // AX CX DX BX BP SI DI 2698 }, 2699 outputs: []outputInfo{ 2700 {0, 239}, // AX CX DX BX BP SI DI 2701 }, 2702 }, 2703 }, 2704 { 2705 name: "SARW", 2706 argLen: 2, 2707 resultInArg0: true, 2708 clobberFlags: true, 2709 asm: x86.ASARW, 2710 reg: regInfo{ 2711 inputs: []inputInfo{ 2712 {1, 2}, // CX 2713 {0, 239}, // AX CX DX BX BP SI DI 2714 }, 2715 outputs: []outputInfo{ 2716 {0, 239}, // AX CX DX BX BP SI DI 2717 }, 2718 }, 2719 }, 2720 { 2721 name: "SARB", 2722 argLen: 2, 2723 resultInArg0: true, 2724 clobberFlags: true, 2725 asm: x86.ASARB, 2726 reg: regInfo{ 2727 inputs: []inputInfo{ 2728 {1, 2}, // CX 2729 {0, 239}, // AX CX DX BX BP SI DI 2730 }, 2731 outputs: []outputInfo{ 2732 {0, 239}, // AX CX DX BX BP SI DI 2733 }, 2734 }, 2735 }, 2736 { 2737 name: "SARLconst", 2738 auxType: auxInt32, 2739 argLen: 1, 2740 resultInArg0: true, 2741 clobberFlags: true, 2742 asm: x86.ASARL, 2743 reg: regInfo{ 2744 inputs: []inputInfo{ 2745 {0, 239}, // AX CX DX BX BP SI DI 2746 }, 2747 outputs: []outputInfo{ 2748 {0, 239}, // AX CX DX BX BP SI DI 2749 }, 2750 }, 2751 }, 2752 { 2753 name: "SARWconst", 2754 auxType: auxInt16, 2755 argLen: 1, 2756 resultInArg0: true, 2757 clobberFlags: true, 2758 asm: x86.ASARW, 2759 reg: regInfo{ 2760 inputs: []inputInfo{ 2761 {0, 239}, // AX CX DX BX BP SI DI 2762 }, 2763 outputs: []outputInfo{ 2764 {0, 239}, // AX CX DX BX BP SI DI 2765 }, 2766 }, 2767 }, 2768 { 2769 name: "SARBconst", 2770 auxType: auxInt8, 2771 argLen: 1, 2772 resultInArg0: true, 2773 clobberFlags: true, 2774 asm: x86.ASARB, 2775 reg: regInfo{ 2776 inputs: []inputInfo{ 2777 {0, 239}, // AX CX DX BX BP SI DI 2778 }, 2779 outputs: []outputInfo{ 2780 {0, 239}, // AX CX DX BX BP SI DI 2781 }, 2782 }, 2783 }, 2784 { 2785 name: "ROLLconst", 2786 auxType: auxInt32, 2787 argLen: 1, 2788 resultInArg0: true, 2789 clobberFlags: true, 2790 asm: x86.AROLL, 2791 reg: regInfo{ 2792 inputs: []inputInfo{ 2793 {0, 239}, // AX CX DX BX BP SI DI 2794 }, 2795 outputs: []outputInfo{ 2796 {0, 239}, // AX CX DX BX BP SI DI 2797 }, 2798 }, 2799 }, 2800 { 2801 name: "ROLWconst", 2802 auxType: auxInt16, 2803 argLen: 1, 2804 resultInArg0: true, 2805 clobberFlags: true, 2806 asm: x86.AROLW, 2807 reg: regInfo{ 2808 inputs: []inputInfo{ 2809 {0, 239}, // AX CX DX BX BP SI DI 2810 }, 2811 outputs: []outputInfo{ 2812 {0, 239}, // AX CX DX BX BP SI DI 2813 }, 2814 }, 2815 }, 2816 { 2817 name: "ROLBconst", 2818 auxType: auxInt8, 2819 argLen: 1, 2820 resultInArg0: true, 2821 clobberFlags: true, 2822 asm: x86.AROLB, 2823 reg: regInfo{ 2824 inputs: []inputInfo{ 2825 {0, 239}, // AX CX DX BX BP SI DI 2826 }, 2827 outputs: []outputInfo{ 2828 {0, 239}, // AX CX DX BX BP SI DI 2829 }, 2830 }, 2831 }, 2832 { 2833 name: "NEGL", 2834 argLen: 1, 2835 resultInArg0: true, 2836 clobberFlags: true, 2837 asm: x86.ANEGL, 2838 reg: regInfo{ 2839 inputs: []inputInfo{ 2840 {0, 239}, // AX CX DX BX BP SI DI 2841 }, 2842 outputs: []outputInfo{ 2843 {0, 239}, // AX CX DX BX BP SI DI 2844 }, 2845 }, 2846 }, 2847 { 2848 name: "NOTL", 2849 argLen: 1, 2850 resultInArg0: true, 2851 clobberFlags: true, 2852 asm: x86.ANOTL, 2853 reg: regInfo{ 2854 inputs: []inputInfo{ 2855 {0, 239}, // AX CX DX BX BP SI DI 2856 }, 2857 outputs: []outputInfo{ 2858 {0, 239}, // AX CX DX BX BP SI DI 2859 }, 2860 }, 2861 }, 2862 { 2863 name: "BSFL", 2864 argLen: 1, 2865 clobberFlags: true, 2866 asm: x86.ABSFL, 2867 reg: regInfo{ 2868 inputs: []inputInfo{ 2869 {0, 239}, // AX CX DX BX BP SI DI 2870 }, 2871 outputs: []outputInfo{ 2872 {0, 239}, // AX CX DX BX BP SI DI 2873 }, 2874 }, 2875 }, 2876 { 2877 name: "BSFW", 2878 argLen: 1, 2879 clobberFlags: true, 2880 asm: x86.ABSFW, 2881 reg: regInfo{ 2882 inputs: []inputInfo{ 2883 {0, 239}, // AX CX DX BX BP SI DI 2884 }, 2885 outputs: []outputInfo{ 2886 {0, 239}, // AX CX DX BX BP SI DI 2887 }, 2888 }, 2889 }, 2890 { 2891 name: "BSRL", 2892 argLen: 1, 2893 clobberFlags: true, 2894 asm: x86.ABSRL, 2895 reg: regInfo{ 2896 inputs: []inputInfo{ 2897 {0, 239}, // AX CX DX BX BP SI DI 2898 }, 2899 outputs: []outputInfo{ 2900 {0, 239}, // AX CX DX BX BP SI DI 2901 }, 2902 }, 2903 }, 2904 { 2905 name: "BSRW", 2906 argLen: 1, 2907 clobberFlags: true, 2908 asm: x86.ABSRW, 2909 reg: regInfo{ 2910 inputs: []inputInfo{ 2911 {0, 239}, // AX CX DX BX BP SI DI 2912 }, 2913 outputs: []outputInfo{ 2914 {0, 239}, // AX CX DX BX BP SI DI 2915 }, 2916 }, 2917 }, 2918 { 2919 name: "BSWAPL", 2920 argLen: 1, 2921 resultInArg0: true, 2922 clobberFlags: true, 2923 asm: x86.ABSWAPL, 2924 reg: regInfo{ 2925 inputs: []inputInfo{ 2926 {0, 239}, // AX CX DX BX BP SI DI 2927 }, 2928 outputs: []outputInfo{ 2929 {0, 239}, // AX CX DX BX BP SI DI 2930 }, 2931 }, 2932 }, 2933 { 2934 name: "SQRTSD", 2935 argLen: 1, 2936 asm: x86.ASQRTSD, 2937 reg: regInfo{ 2938 inputs: []inputInfo{ 2939 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2940 }, 2941 outputs: []outputInfo{ 2942 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 2943 }, 2944 }, 2945 }, 2946 { 2947 name: "SBBLcarrymask", 2948 argLen: 1, 2949 asm: x86.ASBBL, 2950 reg: regInfo{ 2951 outputs: []outputInfo{ 2952 {0, 239}, // AX CX DX BX BP SI DI 2953 }, 2954 }, 2955 }, 2956 { 2957 name: "SETEQ", 2958 argLen: 1, 2959 asm: x86.ASETEQ, 2960 reg: regInfo{ 2961 outputs: []outputInfo{ 2962 {0, 239}, // AX CX DX BX BP SI DI 2963 }, 2964 }, 2965 }, 2966 { 2967 name: "SETNE", 2968 argLen: 1, 2969 asm: x86.ASETNE, 2970 reg: regInfo{ 2971 outputs: []outputInfo{ 2972 {0, 239}, // AX CX DX BX BP SI DI 2973 }, 2974 }, 2975 }, 2976 { 2977 name: "SETL", 2978 argLen: 1, 2979 asm: x86.ASETLT, 2980 reg: regInfo{ 2981 outputs: []outputInfo{ 2982 {0, 239}, // AX CX DX BX BP SI DI 2983 }, 2984 }, 2985 }, 2986 { 2987 name: "SETLE", 2988 argLen: 1, 2989 asm: x86.ASETLE, 2990 reg: regInfo{ 2991 outputs: []outputInfo{ 2992 {0, 239}, // AX CX DX BX BP SI DI 2993 }, 2994 }, 2995 }, 2996 { 2997 name: "SETG", 2998 argLen: 1, 2999 asm: x86.ASETGT, 3000 reg: regInfo{ 3001 outputs: []outputInfo{ 3002 {0, 239}, // AX CX DX BX BP SI DI 3003 }, 3004 }, 3005 }, 3006 { 3007 name: "SETGE", 3008 argLen: 1, 3009 asm: x86.ASETGE, 3010 reg: regInfo{ 3011 outputs: []outputInfo{ 3012 {0, 239}, // AX CX DX BX BP SI DI 3013 }, 3014 }, 3015 }, 3016 { 3017 name: "SETB", 3018 argLen: 1, 3019 asm: x86.ASETCS, 3020 reg: regInfo{ 3021 outputs: []outputInfo{ 3022 {0, 239}, // AX CX DX BX BP SI DI 3023 }, 3024 }, 3025 }, 3026 { 3027 name: "SETBE", 3028 argLen: 1, 3029 asm: x86.ASETLS, 3030 reg: regInfo{ 3031 outputs: []outputInfo{ 3032 {0, 239}, // AX CX DX BX BP SI DI 3033 }, 3034 }, 3035 }, 3036 { 3037 name: "SETA", 3038 argLen: 1, 3039 asm: x86.ASETHI, 3040 reg: regInfo{ 3041 outputs: []outputInfo{ 3042 {0, 239}, // AX CX DX BX BP SI DI 3043 }, 3044 }, 3045 }, 3046 { 3047 name: "SETAE", 3048 argLen: 1, 3049 asm: x86.ASETCC, 3050 reg: regInfo{ 3051 outputs: []outputInfo{ 3052 {0, 239}, // AX CX DX BX BP SI DI 3053 }, 3054 }, 3055 }, 3056 { 3057 name: "SETEQF", 3058 argLen: 1, 3059 clobberFlags: true, 3060 asm: x86.ASETEQ, 3061 reg: regInfo{ 3062 clobbers: 1, // AX 3063 outputs: []outputInfo{ 3064 {0, 238}, // CX DX BX BP SI DI 3065 }, 3066 }, 3067 }, 3068 { 3069 name: "SETNEF", 3070 argLen: 1, 3071 clobberFlags: true, 3072 asm: x86.ASETNE, 3073 reg: regInfo{ 3074 clobbers: 1, // AX 3075 outputs: []outputInfo{ 3076 {0, 238}, // CX DX BX BP SI DI 3077 }, 3078 }, 3079 }, 3080 { 3081 name: "SETORD", 3082 argLen: 1, 3083 asm: x86.ASETPC, 3084 reg: regInfo{ 3085 outputs: []outputInfo{ 3086 {0, 239}, // AX CX DX BX BP SI DI 3087 }, 3088 }, 3089 }, 3090 { 3091 name: "SETNAN", 3092 argLen: 1, 3093 asm: x86.ASETPS, 3094 reg: regInfo{ 3095 outputs: []outputInfo{ 3096 {0, 239}, // AX CX DX BX BP SI DI 3097 }, 3098 }, 3099 }, 3100 { 3101 name: "SETGF", 3102 argLen: 1, 3103 asm: x86.ASETHI, 3104 reg: regInfo{ 3105 outputs: []outputInfo{ 3106 {0, 239}, // AX CX DX BX BP SI DI 3107 }, 3108 }, 3109 }, 3110 { 3111 name: "SETGEF", 3112 argLen: 1, 3113 asm: x86.ASETCC, 3114 reg: regInfo{ 3115 outputs: []outputInfo{ 3116 {0, 239}, // AX CX DX BX BP SI DI 3117 }, 3118 }, 3119 }, 3120 { 3121 name: "MOVBLSX", 3122 argLen: 1, 3123 asm: x86.AMOVBLSX, 3124 reg: regInfo{ 3125 inputs: []inputInfo{ 3126 {0, 239}, // AX CX DX BX BP SI DI 3127 }, 3128 outputs: []outputInfo{ 3129 {0, 239}, // AX CX DX BX BP SI DI 3130 }, 3131 }, 3132 }, 3133 { 3134 name: "MOVBLZX", 3135 argLen: 1, 3136 asm: x86.AMOVBLZX, 3137 reg: regInfo{ 3138 inputs: []inputInfo{ 3139 {0, 239}, // AX CX DX BX BP SI DI 3140 }, 3141 outputs: []outputInfo{ 3142 {0, 239}, // AX CX DX BX BP SI DI 3143 }, 3144 }, 3145 }, 3146 { 3147 name: "MOVWLSX", 3148 argLen: 1, 3149 asm: x86.AMOVWLSX, 3150 reg: regInfo{ 3151 inputs: []inputInfo{ 3152 {0, 239}, // AX CX DX BX BP SI DI 3153 }, 3154 outputs: []outputInfo{ 3155 {0, 239}, // AX CX DX BX BP SI DI 3156 }, 3157 }, 3158 }, 3159 { 3160 name: "MOVWLZX", 3161 argLen: 1, 3162 asm: x86.AMOVWLZX, 3163 reg: regInfo{ 3164 inputs: []inputInfo{ 3165 {0, 239}, // AX CX DX BX BP SI DI 3166 }, 3167 outputs: []outputInfo{ 3168 {0, 239}, // AX CX DX BX BP SI DI 3169 }, 3170 }, 3171 }, 3172 { 3173 name: "MOVLconst", 3174 auxType: auxInt32, 3175 argLen: 0, 3176 rematerializeable: true, 3177 asm: x86.AMOVL, 3178 reg: regInfo{ 3179 outputs: []outputInfo{ 3180 {0, 239}, // AX CX DX BX BP SI DI 3181 }, 3182 }, 3183 }, 3184 { 3185 name: "CVTTSD2SL", 3186 argLen: 1, 3187 asm: x86.ACVTTSD2SL, 3188 reg: regInfo{ 3189 inputs: []inputInfo{ 3190 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3191 }, 3192 outputs: []outputInfo{ 3193 {0, 239}, // AX CX DX BX BP SI DI 3194 }, 3195 }, 3196 }, 3197 { 3198 name: "CVTTSS2SL", 3199 argLen: 1, 3200 asm: x86.ACVTTSS2SL, 3201 reg: regInfo{ 3202 inputs: []inputInfo{ 3203 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3204 }, 3205 outputs: []outputInfo{ 3206 {0, 239}, // AX CX DX BX BP SI DI 3207 }, 3208 }, 3209 }, 3210 { 3211 name: "CVTSL2SS", 3212 argLen: 1, 3213 asm: x86.ACVTSL2SS, 3214 reg: regInfo{ 3215 inputs: []inputInfo{ 3216 {0, 239}, // AX CX DX BX BP SI DI 3217 }, 3218 outputs: []outputInfo{ 3219 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3220 }, 3221 }, 3222 }, 3223 { 3224 name: "CVTSL2SD", 3225 argLen: 1, 3226 asm: x86.ACVTSL2SD, 3227 reg: regInfo{ 3228 inputs: []inputInfo{ 3229 {0, 239}, // AX CX DX BX BP SI DI 3230 }, 3231 outputs: []outputInfo{ 3232 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3233 }, 3234 }, 3235 }, 3236 { 3237 name: "CVTSD2SS", 3238 argLen: 1, 3239 asm: x86.ACVTSD2SS, 3240 reg: regInfo{ 3241 inputs: []inputInfo{ 3242 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3243 }, 3244 outputs: []outputInfo{ 3245 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3246 }, 3247 }, 3248 }, 3249 { 3250 name: "CVTSS2SD", 3251 argLen: 1, 3252 asm: x86.ACVTSS2SD, 3253 reg: regInfo{ 3254 inputs: []inputInfo{ 3255 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3256 }, 3257 outputs: []outputInfo{ 3258 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3259 }, 3260 }, 3261 }, 3262 { 3263 name: "PXOR", 3264 argLen: 2, 3265 commutative: true, 3266 resultInArg0: true, 3267 asm: x86.APXOR, 3268 reg: regInfo{ 3269 inputs: []inputInfo{ 3270 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3271 {1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3272 }, 3273 outputs: []outputInfo{ 3274 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3275 }, 3276 }, 3277 }, 3278 { 3279 name: "LEAL", 3280 auxType: auxSymOff, 3281 argLen: 1, 3282 rematerializeable: true, 3283 reg: regInfo{ 3284 inputs: []inputInfo{ 3285 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3286 }, 3287 outputs: []outputInfo{ 3288 {0, 239}, // AX CX DX BX BP SI DI 3289 }, 3290 }, 3291 }, 3292 { 3293 name: "LEAL1", 3294 auxType: auxSymOff, 3295 argLen: 2, 3296 reg: regInfo{ 3297 inputs: []inputInfo{ 3298 {1, 255}, // AX CX DX BX SP BP SI DI 3299 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3300 }, 3301 outputs: []outputInfo{ 3302 {0, 239}, // AX CX DX BX BP SI DI 3303 }, 3304 }, 3305 }, 3306 { 3307 name: "LEAL2", 3308 auxType: auxSymOff, 3309 argLen: 2, 3310 reg: regInfo{ 3311 inputs: []inputInfo{ 3312 {1, 255}, // AX CX DX BX SP BP SI DI 3313 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3314 }, 3315 outputs: []outputInfo{ 3316 {0, 239}, // AX CX DX BX BP SI DI 3317 }, 3318 }, 3319 }, 3320 { 3321 name: "LEAL4", 3322 auxType: auxSymOff, 3323 argLen: 2, 3324 reg: regInfo{ 3325 inputs: []inputInfo{ 3326 {1, 255}, // AX CX DX BX SP BP SI DI 3327 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3328 }, 3329 outputs: []outputInfo{ 3330 {0, 239}, // AX CX DX BX BP SI DI 3331 }, 3332 }, 3333 }, 3334 { 3335 name: "LEAL8", 3336 auxType: auxSymOff, 3337 argLen: 2, 3338 reg: regInfo{ 3339 inputs: []inputInfo{ 3340 {1, 255}, // AX CX DX BX SP BP SI DI 3341 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3342 }, 3343 outputs: []outputInfo{ 3344 {0, 239}, // AX CX DX BX BP SI DI 3345 }, 3346 }, 3347 }, 3348 { 3349 name: "MOVBload", 3350 auxType: auxSymOff, 3351 argLen: 2, 3352 asm: x86.AMOVBLZX, 3353 reg: regInfo{ 3354 inputs: []inputInfo{ 3355 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3356 }, 3357 outputs: []outputInfo{ 3358 {0, 239}, // AX CX DX BX BP SI DI 3359 }, 3360 }, 3361 }, 3362 { 3363 name: "MOVBLSXload", 3364 auxType: auxSymOff, 3365 argLen: 2, 3366 asm: x86.AMOVBLSX, 3367 reg: regInfo{ 3368 inputs: []inputInfo{ 3369 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3370 }, 3371 outputs: []outputInfo{ 3372 {0, 239}, // AX CX DX BX BP SI DI 3373 }, 3374 }, 3375 }, 3376 { 3377 name: "MOVWload", 3378 auxType: auxSymOff, 3379 argLen: 2, 3380 asm: x86.AMOVWLZX, 3381 reg: regInfo{ 3382 inputs: []inputInfo{ 3383 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3384 }, 3385 outputs: []outputInfo{ 3386 {0, 239}, // AX CX DX BX BP SI DI 3387 }, 3388 }, 3389 }, 3390 { 3391 name: "MOVWLSXload", 3392 auxType: auxSymOff, 3393 argLen: 2, 3394 asm: x86.AMOVWLSX, 3395 reg: regInfo{ 3396 inputs: []inputInfo{ 3397 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3398 }, 3399 outputs: []outputInfo{ 3400 {0, 239}, // AX CX DX BX BP SI DI 3401 }, 3402 }, 3403 }, 3404 { 3405 name: "MOVLload", 3406 auxType: auxSymOff, 3407 argLen: 2, 3408 asm: x86.AMOVL, 3409 reg: regInfo{ 3410 inputs: []inputInfo{ 3411 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3412 }, 3413 outputs: []outputInfo{ 3414 {0, 239}, // AX CX DX BX BP SI DI 3415 }, 3416 }, 3417 }, 3418 { 3419 name: "MOVBstore", 3420 auxType: auxSymOff, 3421 argLen: 3, 3422 asm: x86.AMOVB, 3423 reg: regInfo{ 3424 inputs: []inputInfo{ 3425 {1, 255}, // AX CX DX BX SP BP SI DI 3426 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3427 }, 3428 }, 3429 }, 3430 { 3431 name: "MOVWstore", 3432 auxType: auxSymOff, 3433 argLen: 3, 3434 asm: x86.AMOVW, 3435 reg: regInfo{ 3436 inputs: []inputInfo{ 3437 {1, 255}, // AX CX DX BX SP BP SI DI 3438 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3439 }, 3440 }, 3441 }, 3442 { 3443 name: "MOVLstore", 3444 auxType: auxSymOff, 3445 argLen: 3, 3446 asm: x86.AMOVL, 3447 reg: regInfo{ 3448 inputs: []inputInfo{ 3449 {1, 255}, // AX CX DX BX SP BP SI DI 3450 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3451 }, 3452 }, 3453 }, 3454 { 3455 name: "MOVBloadidx1", 3456 auxType: auxSymOff, 3457 argLen: 3, 3458 asm: x86.AMOVBLZX, 3459 reg: regInfo{ 3460 inputs: []inputInfo{ 3461 {1, 255}, // AX CX DX BX SP BP SI DI 3462 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3463 }, 3464 outputs: []outputInfo{ 3465 {0, 239}, // AX CX DX BX BP SI DI 3466 }, 3467 }, 3468 }, 3469 { 3470 name: "MOVWloadidx1", 3471 auxType: auxSymOff, 3472 argLen: 3, 3473 asm: x86.AMOVWLZX, 3474 reg: regInfo{ 3475 inputs: []inputInfo{ 3476 {1, 255}, // AX CX DX BX SP BP SI DI 3477 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3478 }, 3479 outputs: []outputInfo{ 3480 {0, 239}, // AX CX DX BX BP SI DI 3481 }, 3482 }, 3483 }, 3484 { 3485 name: "MOVWloadidx2", 3486 auxType: auxSymOff, 3487 argLen: 3, 3488 asm: x86.AMOVWLZX, 3489 reg: regInfo{ 3490 inputs: []inputInfo{ 3491 {1, 255}, // AX CX DX BX SP BP SI DI 3492 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3493 }, 3494 outputs: []outputInfo{ 3495 {0, 239}, // AX CX DX BX BP SI DI 3496 }, 3497 }, 3498 }, 3499 { 3500 name: "MOVLloadidx1", 3501 auxType: auxSymOff, 3502 argLen: 3, 3503 asm: x86.AMOVL, 3504 reg: regInfo{ 3505 inputs: []inputInfo{ 3506 {1, 255}, // AX CX DX BX SP BP SI DI 3507 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3508 }, 3509 outputs: []outputInfo{ 3510 {0, 239}, // AX CX DX BX BP SI DI 3511 }, 3512 }, 3513 }, 3514 { 3515 name: "MOVLloadidx4", 3516 auxType: auxSymOff, 3517 argLen: 3, 3518 asm: x86.AMOVL, 3519 reg: regInfo{ 3520 inputs: []inputInfo{ 3521 {1, 255}, // AX CX DX BX SP BP SI DI 3522 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3523 }, 3524 outputs: []outputInfo{ 3525 {0, 239}, // AX CX DX BX BP SI DI 3526 }, 3527 }, 3528 }, 3529 { 3530 name: "MOVBstoreidx1", 3531 auxType: auxSymOff, 3532 argLen: 4, 3533 asm: x86.AMOVB, 3534 reg: regInfo{ 3535 inputs: []inputInfo{ 3536 {1, 255}, // AX CX DX BX SP BP SI DI 3537 {2, 255}, // AX CX DX BX SP BP SI DI 3538 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3539 }, 3540 }, 3541 }, 3542 { 3543 name: "MOVWstoreidx1", 3544 auxType: auxSymOff, 3545 argLen: 4, 3546 asm: x86.AMOVW, 3547 reg: regInfo{ 3548 inputs: []inputInfo{ 3549 {1, 255}, // AX CX DX BX SP BP SI DI 3550 {2, 255}, // AX CX DX BX SP BP SI DI 3551 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3552 }, 3553 }, 3554 }, 3555 { 3556 name: "MOVWstoreidx2", 3557 auxType: auxSymOff, 3558 argLen: 4, 3559 asm: x86.AMOVW, 3560 reg: regInfo{ 3561 inputs: []inputInfo{ 3562 {1, 255}, // AX CX DX BX SP BP SI DI 3563 {2, 255}, // AX CX DX BX SP BP SI DI 3564 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3565 }, 3566 }, 3567 }, 3568 { 3569 name: "MOVLstoreidx1", 3570 auxType: auxSymOff, 3571 argLen: 4, 3572 asm: x86.AMOVL, 3573 reg: regInfo{ 3574 inputs: []inputInfo{ 3575 {1, 255}, // AX CX DX BX SP BP SI DI 3576 {2, 255}, // AX CX DX BX SP BP SI DI 3577 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3578 }, 3579 }, 3580 }, 3581 { 3582 name: "MOVLstoreidx4", 3583 auxType: auxSymOff, 3584 argLen: 4, 3585 asm: x86.AMOVL, 3586 reg: regInfo{ 3587 inputs: []inputInfo{ 3588 {1, 255}, // AX CX DX BX SP BP SI DI 3589 {2, 255}, // AX CX DX BX SP BP SI DI 3590 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3591 }, 3592 }, 3593 }, 3594 { 3595 name: "MOVBstoreconst", 3596 auxType: auxSymValAndOff, 3597 argLen: 2, 3598 asm: x86.AMOVB, 3599 reg: regInfo{ 3600 inputs: []inputInfo{ 3601 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3602 }, 3603 }, 3604 }, 3605 { 3606 name: "MOVWstoreconst", 3607 auxType: auxSymValAndOff, 3608 argLen: 2, 3609 asm: x86.AMOVW, 3610 reg: regInfo{ 3611 inputs: []inputInfo{ 3612 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3613 }, 3614 }, 3615 }, 3616 { 3617 name: "MOVLstoreconst", 3618 auxType: auxSymValAndOff, 3619 argLen: 2, 3620 asm: x86.AMOVL, 3621 reg: regInfo{ 3622 inputs: []inputInfo{ 3623 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3624 }, 3625 }, 3626 }, 3627 { 3628 name: "MOVBstoreconstidx1", 3629 auxType: auxSymValAndOff, 3630 argLen: 3, 3631 asm: x86.AMOVB, 3632 reg: regInfo{ 3633 inputs: []inputInfo{ 3634 {1, 255}, // AX CX DX BX SP BP SI DI 3635 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3636 }, 3637 }, 3638 }, 3639 { 3640 name: "MOVWstoreconstidx1", 3641 auxType: auxSymValAndOff, 3642 argLen: 3, 3643 asm: x86.AMOVW, 3644 reg: regInfo{ 3645 inputs: []inputInfo{ 3646 {1, 255}, // AX CX DX BX SP BP SI DI 3647 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3648 }, 3649 }, 3650 }, 3651 { 3652 name: "MOVWstoreconstidx2", 3653 auxType: auxSymValAndOff, 3654 argLen: 3, 3655 asm: x86.AMOVW, 3656 reg: regInfo{ 3657 inputs: []inputInfo{ 3658 {1, 255}, // AX CX DX BX SP BP SI DI 3659 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3660 }, 3661 }, 3662 }, 3663 { 3664 name: "MOVLstoreconstidx1", 3665 auxType: auxSymValAndOff, 3666 argLen: 3, 3667 asm: x86.AMOVL, 3668 reg: regInfo{ 3669 inputs: []inputInfo{ 3670 {1, 255}, // AX CX DX BX SP BP SI DI 3671 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3672 }, 3673 }, 3674 }, 3675 { 3676 name: "MOVLstoreconstidx4", 3677 auxType: auxSymValAndOff, 3678 argLen: 3, 3679 asm: x86.AMOVL, 3680 reg: regInfo{ 3681 inputs: []inputInfo{ 3682 {1, 255}, // AX CX DX BX SP BP SI DI 3683 {0, 65791}, // AX CX DX BX SP BP SI DI SB 3684 }, 3685 }, 3686 }, 3687 { 3688 name: "DUFFZERO", 3689 auxType: auxInt64, 3690 argLen: 3, 3691 reg: regInfo{ 3692 inputs: []inputInfo{ 3693 {0, 128}, // DI 3694 {1, 1}, // AX 3695 }, 3696 clobbers: 130, // CX DI 3697 }, 3698 }, 3699 { 3700 name: "REPSTOSL", 3701 argLen: 4, 3702 reg: regInfo{ 3703 inputs: []inputInfo{ 3704 {0, 128}, // DI 3705 {1, 2}, // CX 3706 {2, 1}, // AX 3707 }, 3708 clobbers: 130, // CX DI 3709 }, 3710 }, 3711 { 3712 name: "CALLstatic", 3713 auxType: auxSymOff, 3714 argLen: 1, 3715 clobberFlags: true, 3716 reg: regInfo{ 3717 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3718 }, 3719 }, 3720 { 3721 name: "CALLclosure", 3722 auxType: auxInt64, 3723 argLen: 3, 3724 clobberFlags: true, 3725 reg: regInfo{ 3726 inputs: []inputInfo{ 3727 {1, 4}, // DX 3728 {0, 255}, // AX CX DX BX SP BP SI DI 3729 }, 3730 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3731 }, 3732 }, 3733 { 3734 name: "CALLdefer", 3735 auxType: auxInt64, 3736 argLen: 1, 3737 clobberFlags: true, 3738 reg: regInfo{ 3739 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3740 }, 3741 }, 3742 { 3743 name: "CALLgo", 3744 auxType: auxInt64, 3745 argLen: 1, 3746 clobberFlags: true, 3747 reg: regInfo{ 3748 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3749 }, 3750 }, 3751 { 3752 name: "CALLinter", 3753 auxType: auxInt64, 3754 argLen: 2, 3755 clobberFlags: true, 3756 reg: regInfo{ 3757 inputs: []inputInfo{ 3758 {0, 239}, // AX CX DX BX BP SI DI 3759 }, 3760 clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7 3761 }, 3762 }, 3763 { 3764 name: "DUFFCOPY", 3765 auxType: auxInt64, 3766 argLen: 3, 3767 clobberFlags: true, 3768 reg: regInfo{ 3769 inputs: []inputInfo{ 3770 {0, 128}, // DI 3771 {1, 64}, // SI 3772 }, 3773 clobbers: 194, // CX SI DI 3774 }, 3775 }, 3776 { 3777 name: "REPMOVSL", 3778 argLen: 4, 3779 reg: regInfo{ 3780 inputs: []inputInfo{ 3781 {0, 128}, // DI 3782 {1, 64}, // SI 3783 {2, 2}, // CX 3784 }, 3785 clobbers: 194, // CX SI DI 3786 }, 3787 }, 3788 { 3789 name: "InvertFlags", 3790 argLen: 1, 3791 reg: regInfo{}, 3792 }, 3793 { 3794 name: "LoweredGetG", 3795 argLen: 1, 3796 reg: regInfo{ 3797 outputs: []outputInfo{ 3798 {0, 239}, // AX CX DX BX BP SI DI 3799 }, 3800 }, 3801 }, 3802 { 3803 name: "LoweredGetClosurePtr", 3804 argLen: 0, 3805 reg: regInfo{ 3806 outputs: []outputInfo{ 3807 {0, 4}, // DX 3808 }, 3809 }, 3810 }, 3811 { 3812 name: "LoweredNilCheck", 3813 argLen: 2, 3814 clobberFlags: true, 3815 reg: regInfo{ 3816 inputs: []inputInfo{ 3817 {0, 255}, // AX CX DX BX SP BP SI DI 3818 }, 3819 }, 3820 }, 3821 { 3822 name: "MOVLconvert", 3823 argLen: 2, 3824 asm: x86.AMOVL, 3825 reg: regInfo{ 3826 inputs: []inputInfo{ 3827 {0, 239}, // AX CX DX BX BP SI DI 3828 }, 3829 outputs: []outputInfo{ 3830 {0, 239}, // AX CX DX BX BP SI DI 3831 }, 3832 }, 3833 }, 3834 { 3835 name: "FlagEQ", 3836 argLen: 0, 3837 reg: regInfo{}, 3838 }, 3839 { 3840 name: "FlagLT_ULT", 3841 argLen: 0, 3842 reg: regInfo{}, 3843 }, 3844 { 3845 name: "FlagLT_UGT", 3846 argLen: 0, 3847 reg: regInfo{}, 3848 }, 3849 { 3850 name: "FlagGT_UGT", 3851 argLen: 0, 3852 reg: regInfo{}, 3853 }, 3854 { 3855 name: "FlagGT_ULT", 3856 argLen: 0, 3857 reg: regInfo{}, 3858 }, 3859 { 3860 name: "FCHS", 3861 argLen: 1, 3862 reg: regInfo{ 3863 inputs: []inputInfo{ 3864 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3865 }, 3866 outputs: []outputInfo{ 3867 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3868 }, 3869 }, 3870 }, 3871 { 3872 name: "MOVSSconst1", 3873 auxType: auxFloat32, 3874 argLen: 0, 3875 reg: regInfo{ 3876 outputs: []outputInfo{ 3877 {0, 239}, // AX CX DX BX BP SI DI 3878 }, 3879 }, 3880 }, 3881 { 3882 name: "MOVSDconst1", 3883 auxType: auxFloat64, 3884 argLen: 0, 3885 reg: regInfo{ 3886 outputs: []outputInfo{ 3887 {0, 239}, // AX CX DX BX BP SI DI 3888 }, 3889 }, 3890 }, 3891 { 3892 name: "MOVSSconst2", 3893 argLen: 1, 3894 asm: x86.AMOVSS, 3895 reg: regInfo{ 3896 inputs: []inputInfo{ 3897 {0, 239}, // AX CX DX BX BP SI DI 3898 }, 3899 outputs: []outputInfo{ 3900 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3901 }, 3902 }, 3903 }, 3904 { 3905 name: "MOVSDconst2", 3906 argLen: 1, 3907 asm: x86.AMOVSD, 3908 reg: regInfo{ 3909 inputs: []inputInfo{ 3910 {0, 239}, // AX CX DX BX BP SI DI 3911 }, 3912 outputs: []outputInfo{ 3913 {0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7 3914 }, 3915 }, 3916 }, 3917 3918 { 3919 name: "ADDSS", 3920 argLen: 2, 3921 commutative: true, 3922 resultInArg0: true, 3923 asm: x86.AADDSS, 3924 reg: regInfo{ 3925 inputs: []inputInfo{ 3926 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3927 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3928 }, 3929 outputs: []outputInfo{ 3930 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3931 }, 3932 }, 3933 }, 3934 { 3935 name: "ADDSD", 3936 argLen: 2, 3937 commutative: true, 3938 resultInArg0: true, 3939 asm: x86.AADDSD, 3940 reg: regInfo{ 3941 inputs: []inputInfo{ 3942 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3943 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3944 }, 3945 outputs: []outputInfo{ 3946 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3947 }, 3948 }, 3949 }, 3950 { 3951 name: "SUBSS", 3952 argLen: 2, 3953 resultInArg0: true, 3954 asm: x86.ASUBSS, 3955 reg: regInfo{ 3956 inputs: []inputInfo{ 3957 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3958 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3959 }, 3960 clobbers: 2147483648, // X15 3961 outputs: []outputInfo{ 3962 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3963 }, 3964 }, 3965 }, 3966 { 3967 name: "SUBSD", 3968 argLen: 2, 3969 resultInArg0: true, 3970 asm: x86.ASUBSD, 3971 reg: regInfo{ 3972 inputs: []inputInfo{ 3973 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3974 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3975 }, 3976 clobbers: 2147483648, // X15 3977 outputs: []outputInfo{ 3978 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 3979 }, 3980 }, 3981 }, 3982 { 3983 name: "MULSS", 3984 argLen: 2, 3985 commutative: true, 3986 resultInArg0: true, 3987 asm: x86.AMULSS, 3988 reg: regInfo{ 3989 inputs: []inputInfo{ 3990 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3991 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3992 }, 3993 outputs: []outputInfo{ 3994 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 3995 }, 3996 }, 3997 }, 3998 { 3999 name: "MULSD", 4000 argLen: 2, 4001 commutative: true, 4002 resultInArg0: true, 4003 asm: x86.AMULSD, 4004 reg: regInfo{ 4005 inputs: []inputInfo{ 4006 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4007 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4008 }, 4009 outputs: []outputInfo{ 4010 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4011 }, 4012 }, 4013 }, 4014 { 4015 name: "DIVSS", 4016 argLen: 2, 4017 resultInArg0: true, 4018 asm: x86.ADIVSS, 4019 reg: regInfo{ 4020 inputs: []inputInfo{ 4021 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4022 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4023 }, 4024 clobbers: 2147483648, // X15 4025 outputs: []outputInfo{ 4026 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4027 }, 4028 }, 4029 }, 4030 { 4031 name: "DIVSD", 4032 argLen: 2, 4033 resultInArg0: true, 4034 asm: x86.ADIVSD, 4035 reg: regInfo{ 4036 inputs: []inputInfo{ 4037 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4038 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4039 }, 4040 clobbers: 2147483648, // X15 4041 outputs: []outputInfo{ 4042 {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 4043 }, 4044 }, 4045 }, 4046 { 4047 name: "MOVSSload", 4048 auxType: auxSymOff, 4049 argLen: 2, 4050 asm: x86.AMOVSS, 4051 reg: regInfo{ 4052 inputs: []inputInfo{ 4053 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4054 }, 4055 outputs: []outputInfo{ 4056 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4057 }, 4058 }, 4059 }, 4060 { 4061 name: "MOVSDload", 4062 auxType: auxSymOff, 4063 argLen: 2, 4064 asm: x86.AMOVSD, 4065 reg: regInfo{ 4066 inputs: []inputInfo{ 4067 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4068 }, 4069 outputs: []outputInfo{ 4070 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4071 }, 4072 }, 4073 }, 4074 { 4075 name: "MOVSSconst", 4076 auxType: auxFloat32, 4077 argLen: 0, 4078 rematerializeable: true, 4079 asm: x86.AMOVSS, 4080 reg: regInfo{ 4081 outputs: []outputInfo{ 4082 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4083 }, 4084 }, 4085 }, 4086 { 4087 name: "MOVSDconst", 4088 auxType: auxFloat64, 4089 argLen: 0, 4090 rematerializeable: true, 4091 asm: x86.AMOVSD, 4092 reg: regInfo{ 4093 outputs: []outputInfo{ 4094 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4095 }, 4096 }, 4097 }, 4098 { 4099 name: "MOVSSloadidx1", 4100 auxType: auxSymOff, 4101 argLen: 3, 4102 asm: x86.AMOVSS, 4103 reg: regInfo{ 4104 inputs: []inputInfo{ 4105 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4106 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4107 }, 4108 outputs: []outputInfo{ 4109 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4110 }, 4111 }, 4112 }, 4113 { 4114 name: "MOVSSloadidx4", 4115 auxType: auxSymOff, 4116 argLen: 3, 4117 asm: x86.AMOVSS, 4118 reg: regInfo{ 4119 inputs: []inputInfo{ 4120 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4121 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4122 }, 4123 outputs: []outputInfo{ 4124 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4125 }, 4126 }, 4127 }, 4128 { 4129 name: "MOVSDloadidx1", 4130 auxType: auxSymOff, 4131 argLen: 3, 4132 asm: x86.AMOVSD, 4133 reg: regInfo{ 4134 inputs: []inputInfo{ 4135 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4136 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4137 }, 4138 outputs: []outputInfo{ 4139 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4140 }, 4141 }, 4142 }, 4143 { 4144 name: "MOVSDloadidx8", 4145 auxType: auxSymOff, 4146 argLen: 3, 4147 asm: x86.AMOVSD, 4148 reg: regInfo{ 4149 inputs: []inputInfo{ 4150 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4151 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4152 }, 4153 outputs: []outputInfo{ 4154 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4155 }, 4156 }, 4157 }, 4158 { 4159 name: "MOVSSstore", 4160 auxType: auxSymOff, 4161 argLen: 3, 4162 asm: x86.AMOVSS, 4163 reg: regInfo{ 4164 inputs: []inputInfo{ 4165 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4166 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4167 }, 4168 }, 4169 }, 4170 { 4171 name: "MOVSDstore", 4172 auxType: auxSymOff, 4173 argLen: 3, 4174 asm: x86.AMOVSD, 4175 reg: regInfo{ 4176 inputs: []inputInfo{ 4177 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4178 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4179 }, 4180 }, 4181 }, 4182 { 4183 name: "MOVSSstoreidx1", 4184 auxType: auxSymOff, 4185 argLen: 4, 4186 asm: x86.AMOVSS, 4187 reg: regInfo{ 4188 inputs: []inputInfo{ 4189 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4190 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4191 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4192 }, 4193 }, 4194 }, 4195 { 4196 name: "MOVSSstoreidx4", 4197 auxType: auxSymOff, 4198 argLen: 4, 4199 asm: x86.AMOVSS, 4200 reg: regInfo{ 4201 inputs: []inputInfo{ 4202 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4203 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4204 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4205 }, 4206 }, 4207 }, 4208 { 4209 name: "MOVSDstoreidx1", 4210 auxType: auxSymOff, 4211 argLen: 4, 4212 asm: x86.AMOVSD, 4213 reg: regInfo{ 4214 inputs: []inputInfo{ 4215 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4216 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4217 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4218 }, 4219 }, 4220 }, 4221 { 4222 name: "MOVSDstoreidx8", 4223 auxType: auxSymOff, 4224 argLen: 4, 4225 asm: x86.AMOVSD, 4226 reg: regInfo{ 4227 inputs: []inputInfo{ 4228 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4229 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4230 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 4231 }, 4232 }, 4233 }, 4234 { 4235 name: "ADDQ", 4236 argLen: 2, 4237 commutative: true, 4238 clobberFlags: true, 4239 asm: x86.AADDQ, 4240 reg: regInfo{ 4241 inputs: []inputInfo{ 4242 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4243 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4244 }, 4245 outputs: []outputInfo{ 4246 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4247 }, 4248 }, 4249 }, 4250 { 4251 name: "ADDL", 4252 argLen: 2, 4253 commutative: true, 4254 clobberFlags: true, 4255 asm: x86.AADDL, 4256 reg: regInfo{ 4257 inputs: []inputInfo{ 4258 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4259 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4260 }, 4261 outputs: []outputInfo{ 4262 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4263 }, 4264 }, 4265 }, 4266 { 4267 name: "ADDQconst", 4268 auxType: auxInt64, 4269 argLen: 1, 4270 clobberFlags: true, 4271 asm: x86.AADDQ, 4272 reg: regInfo{ 4273 inputs: []inputInfo{ 4274 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4275 }, 4276 outputs: []outputInfo{ 4277 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4278 }, 4279 }, 4280 }, 4281 { 4282 name: "ADDLconst", 4283 auxType: auxInt32, 4284 argLen: 1, 4285 clobberFlags: true, 4286 asm: x86.AADDL, 4287 reg: regInfo{ 4288 inputs: []inputInfo{ 4289 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4290 }, 4291 outputs: []outputInfo{ 4292 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4293 }, 4294 }, 4295 }, 4296 { 4297 name: "SUBQ", 4298 argLen: 2, 4299 resultInArg0: true, 4300 clobberFlags: true, 4301 asm: x86.ASUBQ, 4302 reg: regInfo{ 4303 inputs: []inputInfo{ 4304 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4305 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4306 }, 4307 outputs: []outputInfo{ 4308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4309 }, 4310 }, 4311 }, 4312 { 4313 name: "SUBL", 4314 argLen: 2, 4315 resultInArg0: true, 4316 clobberFlags: true, 4317 asm: x86.ASUBL, 4318 reg: regInfo{ 4319 inputs: []inputInfo{ 4320 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4321 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4322 }, 4323 outputs: []outputInfo{ 4324 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4325 }, 4326 }, 4327 }, 4328 { 4329 name: "SUBQconst", 4330 auxType: auxInt64, 4331 argLen: 1, 4332 resultInArg0: true, 4333 clobberFlags: true, 4334 asm: x86.ASUBQ, 4335 reg: regInfo{ 4336 inputs: []inputInfo{ 4337 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4338 }, 4339 outputs: []outputInfo{ 4340 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4341 }, 4342 }, 4343 }, 4344 { 4345 name: "SUBLconst", 4346 auxType: auxInt32, 4347 argLen: 1, 4348 resultInArg0: true, 4349 clobberFlags: true, 4350 asm: x86.ASUBL, 4351 reg: regInfo{ 4352 inputs: []inputInfo{ 4353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4354 }, 4355 outputs: []outputInfo{ 4356 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4357 }, 4358 }, 4359 }, 4360 { 4361 name: "MULQ", 4362 argLen: 2, 4363 commutative: true, 4364 resultInArg0: true, 4365 clobberFlags: true, 4366 asm: x86.AIMULQ, 4367 reg: regInfo{ 4368 inputs: []inputInfo{ 4369 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4370 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4371 }, 4372 outputs: []outputInfo{ 4373 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4374 }, 4375 }, 4376 }, 4377 { 4378 name: "MULL", 4379 argLen: 2, 4380 commutative: true, 4381 resultInArg0: true, 4382 clobberFlags: true, 4383 asm: x86.AIMULL, 4384 reg: regInfo{ 4385 inputs: []inputInfo{ 4386 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4387 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4388 }, 4389 outputs: []outputInfo{ 4390 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4391 }, 4392 }, 4393 }, 4394 { 4395 name: "MULQconst", 4396 auxType: auxInt64, 4397 argLen: 1, 4398 resultInArg0: true, 4399 clobberFlags: true, 4400 asm: x86.AIMULQ, 4401 reg: regInfo{ 4402 inputs: []inputInfo{ 4403 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4404 }, 4405 outputs: []outputInfo{ 4406 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4407 }, 4408 }, 4409 }, 4410 { 4411 name: "MULLconst", 4412 auxType: auxInt32, 4413 argLen: 1, 4414 resultInArg0: true, 4415 clobberFlags: true, 4416 asm: x86.AIMULL, 4417 reg: regInfo{ 4418 inputs: []inputInfo{ 4419 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4420 }, 4421 outputs: []outputInfo{ 4422 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4423 }, 4424 }, 4425 }, 4426 { 4427 name: "HMULQ", 4428 argLen: 2, 4429 clobberFlags: true, 4430 asm: x86.AIMULQ, 4431 reg: regInfo{ 4432 inputs: []inputInfo{ 4433 {0, 1}, // AX 4434 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4435 }, 4436 clobbers: 1, // AX 4437 outputs: []outputInfo{ 4438 {0, 4}, // DX 4439 }, 4440 }, 4441 }, 4442 { 4443 name: "HMULL", 4444 argLen: 2, 4445 clobberFlags: true, 4446 asm: x86.AIMULL, 4447 reg: regInfo{ 4448 inputs: []inputInfo{ 4449 {0, 1}, // AX 4450 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4451 }, 4452 clobbers: 1, // AX 4453 outputs: []outputInfo{ 4454 {0, 4}, // DX 4455 }, 4456 }, 4457 }, 4458 { 4459 name: "HMULW", 4460 argLen: 2, 4461 clobberFlags: true, 4462 asm: x86.AIMULW, 4463 reg: regInfo{ 4464 inputs: []inputInfo{ 4465 {0, 1}, // AX 4466 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4467 }, 4468 clobbers: 1, // AX 4469 outputs: []outputInfo{ 4470 {0, 4}, // DX 4471 }, 4472 }, 4473 }, 4474 { 4475 name: "HMULB", 4476 argLen: 2, 4477 clobberFlags: true, 4478 asm: x86.AIMULB, 4479 reg: regInfo{ 4480 inputs: []inputInfo{ 4481 {0, 1}, // AX 4482 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4483 }, 4484 clobbers: 1, // AX 4485 outputs: []outputInfo{ 4486 {0, 4}, // DX 4487 }, 4488 }, 4489 }, 4490 { 4491 name: "HMULQU", 4492 argLen: 2, 4493 clobberFlags: true, 4494 asm: x86.AMULQ, 4495 reg: regInfo{ 4496 inputs: []inputInfo{ 4497 {0, 1}, // AX 4498 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4499 }, 4500 clobbers: 1, // AX 4501 outputs: []outputInfo{ 4502 {0, 4}, // DX 4503 }, 4504 }, 4505 }, 4506 { 4507 name: "HMULLU", 4508 argLen: 2, 4509 clobberFlags: true, 4510 asm: x86.AMULL, 4511 reg: regInfo{ 4512 inputs: []inputInfo{ 4513 {0, 1}, // AX 4514 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4515 }, 4516 clobbers: 1, // AX 4517 outputs: []outputInfo{ 4518 {0, 4}, // DX 4519 }, 4520 }, 4521 }, 4522 { 4523 name: "HMULWU", 4524 argLen: 2, 4525 clobberFlags: true, 4526 asm: x86.AMULW, 4527 reg: regInfo{ 4528 inputs: []inputInfo{ 4529 {0, 1}, // AX 4530 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4531 }, 4532 clobbers: 1, // AX 4533 outputs: []outputInfo{ 4534 {0, 4}, // DX 4535 }, 4536 }, 4537 }, 4538 { 4539 name: "HMULBU", 4540 argLen: 2, 4541 clobberFlags: true, 4542 asm: x86.AMULB, 4543 reg: regInfo{ 4544 inputs: []inputInfo{ 4545 {0, 1}, // AX 4546 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4547 }, 4548 clobbers: 1, // AX 4549 outputs: []outputInfo{ 4550 {0, 4}, // DX 4551 }, 4552 }, 4553 }, 4554 { 4555 name: "AVGQU", 4556 argLen: 2, 4557 commutative: true, 4558 resultInArg0: true, 4559 clobberFlags: true, 4560 reg: regInfo{ 4561 inputs: []inputInfo{ 4562 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4563 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4564 }, 4565 outputs: []outputInfo{ 4566 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4567 }, 4568 }, 4569 }, 4570 { 4571 name: "DIVQ", 4572 argLen: 2, 4573 clobberFlags: true, 4574 asm: x86.AIDIVQ, 4575 reg: regInfo{ 4576 inputs: []inputInfo{ 4577 {0, 1}, // AX 4578 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4579 }, 4580 outputs: []outputInfo{ 4581 {0, 1}, // AX 4582 {1, 4}, // DX 4583 }, 4584 }, 4585 }, 4586 { 4587 name: "DIVL", 4588 argLen: 2, 4589 clobberFlags: true, 4590 asm: x86.AIDIVL, 4591 reg: regInfo{ 4592 inputs: []inputInfo{ 4593 {0, 1}, // AX 4594 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4595 }, 4596 outputs: []outputInfo{ 4597 {0, 1}, // AX 4598 {1, 4}, // DX 4599 }, 4600 }, 4601 }, 4602 { 4603 name: "DIVW", 4604 argLen: 2, 4605 clobberFlags: true, 4606 asm: x86.AIDIVW, 4607 reg: regInfo{ 4608 inputs: []inputInfo{ 4609 {0, 1}, // AX 4610 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4611 }, 4612 outputs: []outputInfo{ 4613 {0, 1}, // AX 4614 {1, 4}, // DX 4615 }, 4616 }, 4617 }, 4618 { 4619 name: "DIVQU", 4620 argLen: 2, 4621 clobberFlags: true, 4622 asm: x86.ADIVQ, 4623 reg: regInfo{ 4624 inputs: []inputInfo{ 4625 {0, 1}, // AX 4626 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4627 }, 4628 outputs: []outputInfo{ 4629 {0, 1}, // AX 4630 {1, 4}, // DX 4631 }, 4632 }, 4633 }, 4634 { 4635 name: "DIVLU", 4636 argLen: 2, 4637 clobberFlags: true, 4638 asm: x86.ADIVL, 4639 reg: regInfo{ 4640 inputs: []inputInfo{ 4641 {0, 1}, // AX 4642 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4643 }, 4644 outputs: []outputInfo{ 4645 {0, 1}, // AX 4646 {1, 4}, // DX 4647 }, 4648 }, 4649 }, 4650 { 4651 name: "DIVWU", 4652 argLen: 2, 4653 clobberFlags: true, 4654 asm: x86.ADIVW, 4655 reg: regInfo{ 4656 inputs: []inputInfo{ 4657 {0, 1}, // AX 4658 {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4659 }, 4660 outputs: []outputInfo{ 4661 {0, 1}, // AX 4662 {1, 4}, // DX 4663 }, 4664 }, 4665 }, 4666 { 4667 name: "ANDQ", 4668 argLen: 2, 4669 commutative: true, 4670 resultInArg0: true, 4671 clobberFlags: true, 4672 asm: x86.AANDQ, 4673 reg: regInfo{ 4674 inputs: []inputInfo{ 4675 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4676 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4677 }, 4678 outputs: []outputInfo{ 4679 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4680 }, 4681 }, 4682 }, 4683 { 4684 name: "ANDL", 4685 argLen: 2, 4686 commutative: true, 4687 resultInArg0: true, 4688 clobberFlags: true, 4689 asm: x86.AANDL, 4690 reg: regInfo{ 4691 inputs: []inputInfo{ 4692 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4693 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4694 }, 4695 outputs: []outputInfo{ 4696 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4697 }, 4698 }, 4699 }, 4700 { 4701 name: "ANDQconst", 4702 auxType: auxInt64, 4703 argLen: 1, 4704 resultInArg0: true, 4705 clobberFlags: true, 4706 asm: x86.AANDQ, 4707 reg: regInfo{ 4708 inputs: []inputInfo{ 4709 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4710 }, 4711 outputs: []outputInfo{ 4712 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4713 }, 4714 }, 4715 }, 4716 { 4717 name: "ANDLconst", 4718 auxType: auxInt32, 4719 argLen: 1, 4720 resultInArg0: true, 4721 clobberFlags: true, 4722 asm: x86.AANDL, 4723 reg: regInfo{ 4724 inputs: []inputInfo{ 4725 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4726 }, 4727 outputs: []outputInfo{ 4728 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4729 }, 4730 }, 4731 }, 4732 { 4733 name: "ORQ", 4734 argLen: 2, 4735 commutative: true, 4736 resultInArg0: true, 4737 clobberFlags: true, 4738 asm: x86.AORQ, 4739 reg: regInfo{ 4740 inputs: []inputInfo{ 4741 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4742 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4743 }, 4744 outputs: []outputInfo{ 4745 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4746 }, 4747 }, 4748 }, 4749 { 4750 name: "ORL", 4751 argLen: 2, 4752 commutative: true, 4753 resultInArg0: true, 4754 clobberFlags: true, 4755 asm: x86.AORL, 4756 reg: regInfo{ 4757 inputs: []inputInfo{ 4758 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4759 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4760 }, 4761 outputs: []outputInfo{ 4762 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4763 }, 4764 }, 4765 }, 4766 { 4767 name: "ORQconst", 4768 auxType: auxInt64, 4769 argLen: 1, 4770 resultInArg0: true, 4771 clobberFlags: true, 4772 asm: x86.AORQ, 4773 reg: regInfo{ 4774 inputs: []inputInfo{ 4775 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4776 }, 4777 outputs: []outputInfo{ 4778 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4779 }, 4780 }, 4781 }, 4782 { 4783 name: "ORLconst", 4784 auxType: auxInt32, 4785 argLen: 1, 4786 resultInArg0: true, 4787 clobberFlags: true, 4788 asm: x86.AORL, 4789 reg: regInfo{ 4790 inputs: []inputInfo{ 4791 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4792 }, 4793 outputs: []outputInfo{ 4794 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4795 }, 4796 }, 4797 }, 4798 { 4799 name: "XORQ", 4800 argLen: 2, 4801 commutative: true, 4802 resultInArg0: true, 4803 clobberFlags: true, 4804 asm: x86.AXORQ, 4805 reg: regInfo{ 4806 inputs: []inputInfo{ 4807 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4808 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4809 }, 4810 outputs: []outputInfo{ 4811 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4812 }, 4813 }, 4814 }, 4815 { 4816 name: "XORL", 4817 argLen: 2, 4818 commutative: true, 4819 resultInArg0: true, 4820 clobberFlags: true, 4821 asm: x86.AXORL, 4822 reg: regInfo{ 4823 inputs: []inputInfo{ 4824 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4825 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4826 }, 4827 outputs: []outputInfo{ 4828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4829 }, 4830 }, 4831 }, 4832 { 4833 name: "XORQconst", 4834 auxType: auxInt64, 4835 argLen: 1, 4836 resultInArg0: true, 4837 clobberFlags: true, 4838 asm: x86.AXORQ, 4839 reg: regInfo{ 4840 inputs: []inputInfo{ 4841 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4842 }, 4843 outputs: []outputInfo{ 4844 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4845 }, 4846 }, 4847 }, 4848 { 4849 name: "XORLconst", 4850 auxType: auxInt32, 4851 argLen: 1, 4852 resultInArg0: true, 4853 clobberFlags: true, 4854 asm: x86.AXORL, 4855 reg: regInfo{ 4856 inputs: []inputInfo{ 4857 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4858 }, 4859 outputs: []outputInfo{ 4860 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4861 }, 4862 }, 4863 }, 4864 { 4865 name: "CMPQ", 4866 argLen: 2, 4867 asm: x86.ACMPQ, 4868 reg: regInfo{ 4869 inputs: []inputInfo{ 4870 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4871 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4872 }, 4873 }, 4874 }, 4875 { 4876 name: "CMPL", 4877 argLen: 2, 4878 asm: x86.ACMPL, 4879 reg: regInfo{ 4880 inputs: []inputInfo{ 4881 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4882 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4883 }, 4884 }, 4885 }, 4886 { 4887 name: "CMPW", 4888 argLen: 2, 4889 asm: x86.ACMPW, 4890 reg: regInfo{ 4891 inputs: []inputInfo{ 4892 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4893 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4894 }, 4895 }, 4896 }, 4897 { 4898 name: "CMPB", 4899 argLen: 2, 4900 asm: x86.ACMPB, 4901 reg: regInfo{ 4902 inputs: []inputInfo{ 4903 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4904 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4905 }, 4906 }, 4907 }, 4908 { 4909 name: "CMPQconst", 4910 auxType: auxInt64, 4911 argLen: 1, 4912 asm: x86.ACMPQ, 4913 reg: regInfo{ 4914 inputs: []inputInfo{ 4915 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4916 }, 4917 }, 4918 }, 4919 { 4920 name: "CMPLconst", 4921 auxType: auxInt32, 4922 argLen: 1, 4923 asm: x86.ACMPL, 4924 reg: regInfo{ 4925 inputs: []inputInfo{ 4926 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4927 }, 4928 }, 4929 }, 4930 { 4931 name: "CMPWconst", 4932 auxType: auxInt16, 4933 argLen: 1, 4934 asm: x86.ACMPW, 4935 reg: regInfo{ 4936 inputs: []inputInfo{ 4937 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4938 }, 4939 }, 4940 }, 4941 { 4942 name: "CMPBconst", 4943 auxType: auxInt8, 4944 argLen: 1, 4945 asm: x86.ACMPB, 4946 reg: regInfo{ 4947 inputs: []inputInfo{ 4948 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4949 }, 4950 }, 4951 }, 4952 { 4953 name: "UCOMISS", 4954 argLen: 2, 4955 asm: x86.AUCOMISS, 4956 reg: regInfo{ 4957 inputs: []inputInfo{ 4958 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4959 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4960 }, 4961 }, 4962 }, 4963 { 4964 name: "UCOMISD", 4965 argLen: 2, 4966 asm: x86.AUCOMISD, 4967 reg: regInfo{ 4968 inputs: []inputInfo{ 4969 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4970 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 4971 }, 4972 }, 4973 }, 4974 { 4975 name: "TESTQ", 4976 argLen: 2, 4977 asm: x86.ATESTQ, 4978 reg: regInfo{ 4979 inputs: []inputInfo{ 4980 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4981 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4982 }, 4983 }, 4984 }, 4985 { 4986 name: "TESTL", 4987 argLen: 2, 4988 asm: x86.ATESTL, 4989 reg: regInfo{ 4990 inputs: []inputInfo{ 4991 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4992 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 4993 }, 4994 }, 4995 }, 4996 { 4997 name: "TESTW", 4998 argLen: 2, 4999 asm: x86.ATESTW, 5000 reg: regInfo{ 5001 inputs: []inputInfo{ 5002 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5003 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5004 }, 5005 }, 5006 }, 5007 { 5008 name: "TESTB", 5009 argLen: 2, 5010 asm: x86.ATESTB, 5011 reg: regInfo{ 5012 inputs: []inputInfo{ 5013 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5014 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5015 }, 5016 }, 5017 }, 5018 { 5019 name: "TESTQconst", 5020 auxType: auxInt64, 5021 argLen: 1, 5022 asm: x86.ATESTQ, 5023 reg: regInfo{ 5024 inputs: []inputInfo{ 5025 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5026 }, 5027 }, 5028 }, 5029 { 5030 name: "TESTLconst", 5031 auxType: auxInt32, 5032 argLen: 1, 5033 asm: x86.ATESTL, 5034 reg: regInfo{ 5035 inputs: []inputInfo{ 5036 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5037 }, 5038 }, 5039 }, 5040 { 5041 name: "TESTWconst", 5042 auxType: auxInt16, 5043 argLen: 1, 5044 asm: x86.ATESTW, 5045 reg: regInfo{ 5046 inputs: []inputInfo{ 5047 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5048 }, 5049 }, 5050 }, 5051 { 5052 name: "TESTBconst", 5053 auxType: auxInt8, 5054 argLen: 1, 5055 asm: x86.ATESTB, 5056 reg: regInfo{ 5057 inputs: []inputInfo{ 5058 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5059 }, 5060 }, 5061 }, 5062 { 5063 name: "SHLQ", 5064 argLen: 2, 5065 resultInArg0: true, 5066 clobberFlags: true, 5067 asm: x86.ASHLQ, 5068 reg: regInfo{ 5069 inputs: []inputInfo{ 5070 {1, 2}, // CX 5071 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5072 }, 5073 outputs: []outputInfo{ 5074 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5075 }, 5076 }, 5077 }, 5078 { 5079 name: "SHLL", 5080 argLen: 2, 5081 resultInArg0: true, 5082 clobberFlags: true, 5083 asm: x86.ASHLL, 5084 reg: regInfo{ 5085 inputs: []inputInfo{ 5086 {1, 2}, // CX 5087 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5088 }, 5089 outputs: []outputInfo{ 5090 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5091 }, 5092 }, 5093 }, 5094 { 5095 name: "SHLQconst", 5096 auxType: auxInt64, 5097 argLen: 1, 5098 resultInArg0: true, 5099 clobberFlags: true, 5100 asm: x86.ASHLQ, 5101 reg: regInfo{ 5102 inputs: []inputInfo{ 5103 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5104 }, 5105 outputs: []outputInfo{ 5106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5107 }, 5108 }, 5109 }, 5110 { 5111 name: "SHLLconst", 5112 auxType: auxInt32, 5113 argLen: 1, 5114 resultInArg0: true, 5115 clobberFlags: true, 5116 asm: x86.ASHLL, 5117 reg: regInfo{ 5118 inputs: []inputInfo{ 5119 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5120 }, 5121 outputs: []outputInfo{ 5122 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5123 }, 5124 }, 5125 }, 5126 { 5127 name: "SHRQ", 5128 argLen: 2, 5129 resultInArg0: true, 5130 clobberFlags: true, 5131 asm: x86.ASHRQ, 5132 reg: regInfo{ 5133 inputs: []inputInfo{ 5134 {1, 2}, // CX 5135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5136 }, 5137 outputs: []outputInfo{ 5138 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5139 }, 5140 }, 5141 }, 5142 { 5143 name: "SHRL", 5144 argLen: 2, 5145 resultInArg0: true, 5146 clobberFlags: true, 5147 asm: x86.ASHRL, 5148 reg: regInfo{ 5149 inputs: []inputInfo{ 5150 {1, 2}, // CX 5151 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5152 }, 5153 outputs: []outputInfo{ 5154 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5155 }, 5156 }, 5157 }, 5158 { 5159 name: "SHRW", 5160 argLen: 2, 5161 resultInArg0: true, 5162 clobberFlags: true, 5163 asm: x86.ASHRW, 5164 reg: regInfo{ 5165 inputs: []inputInfo{ 5166 {1, 2}, // CX 5167 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5168 }, 5169 outputs: []outputInfo{ 5170 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5171 }, 5172 }, 5173 }, 5174 { 5175 name: "SHRB", 5176 argLen: 2, 5177 resultInArg0: true, 5178 clobberFlags: true, 5179 asm: x86.ASHRB, 5180 reg: regInfo{ 5181 inputs: []inputInfo{ 5182 {1, 2}, // CX 5183 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5184 }, 5185 outputs: []outputInfo{ 5186 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5187 }, 5188 }, 5189 }, 5190 { 5191 name: "SHRQconst", 5192 auxType: auxInt64, 5193 argLen: 1, 5194 resultInArg0: true, 5195 clobberFlags: true, 5196 asm: x86.ASHRQ, 5197 reg: regInfo{ 5198 inputs: []inputInfo{ 5199 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5200 }, 5201 outputs: []outputInfo{ 5202 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5203 }, 5204 }, 5205 }, 5206 { 5207 name: "SHRLconst", 5208 auxType: auxInt32, 5209 argLen: 1, 5210 resultInArg0: true, 5211 clobberFlags: true, 5212 asm: x86.ASHRL, 5213 reg: regInfo{ 5214 inputs: []inputInfo{ 5215 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5216 }, 5217 outputs: []outputInfo{ 5218 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5219 }, 5220 }, 5221 }, 5222 { 5223 name: "SHRWconst", 5224 auxType: auxInt16, 5225 argLen: 1, 5226 resultInArg0: true, 5227 clobberFlags: true, 5228 asm: x86.ASHRW, 5229 reg: regInfo{ 5230 inputs: []inputInfo{ 5231 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5232 }, 5233 outputs: []outputInfo{ 5234 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5235 }, 5236 }, 5237 }, 5238 { 5239 name: "SHRBconst", 5240 auxType: auxInt8, 5241 argLen: 1, 5242 resultInArg0: true, 5243 clobberFlags: true, 5244 asm: x86.ASHRB, 5245 reg: regInfo{ 5246 inputs: []inputInfo{ 5247 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5248 }, 5249 outputs: []outputInfo{ 5250 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5251 }, 5252 }, 5253 }, 5254 { 5255 name: "SARQ", 5256 argLen: 2, 5257 resultInArg0: true, 5258 clobberFlags: true, 5259 asm: x86.ASARQ, 5260 reg: regInfo{ 5261 inputs: []inputInfo{ 5262 {1, 2}, // CX 5263 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5264 }, 5265 outputs: []outputInfo{ 5266 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5267 }, 5268 }, 5269 }, 5270 { 5271 name: "SARL", 5272 argLen: 2, 5273 resultInArg0: true, 5274 clobberFlags: true, 5275 asm: x86.ASARL, 5276 reg: regInfo{ 5277 inputs: []inputInfo{ 5278 {1, 2}, // CX 5279 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5280 }, 5281 outputs: []outputInfo{ 5282 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5283 }, 5284 }, 5285 }, 5286 { 5287 name: "SARW", 5288 argLen: 2, 5289 resultInArg0: true, 5290 clobberFlags: true, 5291 asm: x86.ASARW, 5292 reg: regInfo{ 5293 inputs: []inputInfo{ 5294 {1, 2}, // CX 5295 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5296 }, 5297 outputs: []outputInfo{ 5298 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5299 }, 5300 }, 5301 }, 5302 { 5303 name: "SARB", 5304 argLen: 2, 5305 resultInArg0: true, 5306 clobberFlags: true, 5307 asm: x86.ASARB, 5308 reg: regInfo{ 5309 inputs: []inputInfo{ 5310 {1, 2}, // CX 5311 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5312 }, 5313 outputs: []outputInfo{ 5314 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5315 }, 5316 }, 5317 }, 5318 { 5319 name: "SARQconst", 5320 auxType: auxInt64, 5321 argLen: 1, 5322 resultInArg0: true, 5323 clobberFlags: true, 5324 asm: x86.ASARQ, 5325 reg: regInfo{ 5326 inputs: []inputInfo{ 5327 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5328 }, 5329 outputs: []outputInfo{ 5330 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5331 }, 5332 }, 5333 }, 5334 { 5335 name: "SARLconst", 5336 auxType: auxInt32, 5337 argLen: 1, 5338 resultInArg0: true, 5339 clobberFlags: true, 5340 asm: x86.ASARL, 5341 reg: regInfo{ 5342 inputs: []inputInfo{ 5343 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5344 }, 5345 outputs: []outputInfo{ 5346 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5347 }, 5348 }, 5349 }, 5350 { 5351 name: "SARWconst", 5352 auxType: auxInt16, 5353 argLen: 1, 5354 resultInArg0: true, 5355 clobberFlags: true, 5356 asm: x86.ASARW, 5357 reg: regInfo{ 5358 inputs: []inputInfo{ 5359 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5360 }, 5361 outputs: []outputInfo{ 5362 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5363 }, 5364 }, 5365 }, 5366 { 5367 name: "SARBconst", 5368 auxType: auxInt8, 5369 argLen: 1, 5370 resultInArg0: true, 5371 clobberFlags: true, 5372 asm: x86.ASARB, 5373 reg: regInfo{ 5374 inputs: []inputInfo{ 5375 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5376 }, 5377 outputs: []outputInfo{ 5378 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5379 }, 5380 }, 5381 }, 5382 { 5383 name: "ROLQconst", 5384 auxType: auxInt64, 5385 argLen: 1, 5386 resultInArg0: true, 5387 clobberFlags: true, 5388 asm: x86.AROLQ, 5389 reg: regInfo{ 5390 inputs: []inputInfo{ 5391 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5392 }, 5393 outputs: []outputInfo{ 5394 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5395 }, 5396 }, 5397 }, 5398 { 5399 name: "ROLLconst", 5400 auxType: auxInt32, 5401 argLen: 1, 5402 resultInArg0: true, 5403 clobberFlags: true, 5404 asm: x86.AROLL, 5405 reg: regInfo{ 5406 inputs: []inputInfo{ 5407 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5408 }, 5409 outputs: []outputInfo{ 5410 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5411 }, 5412 }, 5413 }, 5414 { 5415 name: "ROLWconst", 5416 auxType: auxInt16, 5417 argLen: 1, 5418 resultInArg0: true, 5419 clobberFlags: true, 5420 asm: x86.AROLW, 5421 reg: regInfo{ 5422 inputs: []inputInfo{ 5423 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5424 }, 5425 outputs: []outputInfo{ 5426 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5427 }, 5428 }, 5429 }, 5430 { 5431 name: "ROLBconst", 5432 auxType: auxInt8, 5433 argLen: 1, 5434 resultInArg0: true, 5435 clobberFlags: true, 5436 asm: x86.AROLB, 5437 reg: regInfo{ 5438 inputs: []inputInfo{ 5439 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5440 }, 5441 outputs: []outputInfo{ 5442 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5443 }, 5444 }, 5445 }, 5446 { 5447 name: "NEGQ", 5448 argLen: 1, 5449 resultInArg0: true, 5450 clobberFlags: true, 5451 asm: x86.ANEGQ, 5452 reg: regInfo{ 5453 inputs: []inputInfo{ 5454 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5455 }, 5456 outputs: []outputInfo{ 5457 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5458 }, 5459 }, 5460 }, 5461 { 5462 name: "NEGL", 5463 argLen: 1, 5464 resultInArg0: true, 5465 clobberFlags: true, 5466 asm: x86.ANEGL, 5467 reg: regInfo{ 5468 inputs: []inputInfo{ 5469 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5470 }, 5471 outputs: []outputInfo{ 5472 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5473 }, 5474 }, 5475 }, 5476 { 5477 name: "NOTQ", 5478 argLen: 1, 5479 resultInArg0: true, 5480 clobberFlags: true, 5481 asm: x86.ANOTQ, 5482 reg: regInfo{ 5483 inputs: []inputInfo{ 5484 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5485 }, 5486 outputs: []outputInfo{ 5487 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5488 }, 5489 }, 5490 }, 5491 { 5492 name: "NOTL", 5493 argLen: 1, 5494 resultInArg0: true, 5495 clobberFlags: true, 5496 asm: x86.ANOTL, 5497 reg: regInfo{ 5498 inputs: []inputInfo{ 5499 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5500 }, 5501 outputs: []outputInfo{ 5502 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5503 }, 5504 }, 5505 }, 5506 { 5507 name: "BSFQ", 5508 argLen: 1, 5509 asm: x86.ABSFQ, 5510 reg: regInfo{ 5511 inputs: []inputInfo{ 5512 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5513 }, 5514 outputs: []outputInfo{ 5515 {1, 0}, 5516 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5517 }, 5518 }, 5519 }, 5520 { 5521 name: "BSFL", 5522 argLen: 1, 5523 asm: x86.ABSFL, 5524 reg: regInfo{ 5525 inputs: []inputInfo{ 5526 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5527 }, 5528 outputs: []outputInfo{ 5529 {1, 0}, 5530 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5531 }, 5532 }, 5533 }, 5534 { 5535 name: "CMOVQEQ", 5536 argLen: 3, 5537 resultInArg0: true, 5538 asm: x86.ACMOVQEQ, 5539 reg: regInfo{ 5540 inputs: []inputInfo{ 5541 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5542 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5543 }, 5544 outputs: []outputInfo{ 5545 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5546 }, 5547 }, 5548 }, 5549 { 5550 name: "CMOVLEQ", 5551 argLen: 3, 5552 resultInArg0: true, 5553 asm: x86.ACMOVLEQ, 5554 reg: regInfo{ 5555 inputs: []inputInfo{ 5556 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5557 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5558 }, 5559 outputs: []outputInfo{ 5560 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5561 }, 5562 }, 5563 }, 5564 { 5565 name: "BSWAPQ", 5566 argLen: 1, 5567 resultInArg0: true, 5568 clobberFlags: true, 5569 asm: x86.ABSWAPQ, 5570 reg: regInfo{ 5571 inputs: []inputInfo{ 5572 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5573 }, 5574 outputs: []outputInfo{ 5575 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5576 }, 5577 }, 5578 }, 5579 { 5580 name: "BSWAPL", 5581 argLen: 1, 5582 resultInArg0: true, 5583 clobberFlags: true, 5584 asm: x86.ABSWAPL, 5585 reg: regInfo{ 5586 inputs: []inputInfo{ 5587 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5588 }, 5589 outputs: []outputInfo{ 5590 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5591 }, 5592 }, 5593 }, 5594 { 5595 name: "SQRTSD", 5596 argLen: 1, 5597 asm: x86.ASQRTSD, 5598 reg: regInfo{ 5599 inputs: []inputInfo{ 5600 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5601 }, 5602 outputs: []outputInfo{ 5603 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5604 }, 5605 }, 5606 }, 5607 { 5608 name: "SBBQcarrymask", 5609 argLen: 1, 5610 asm: x86.ASBBQ, 5611 reg: regInfo{ 5612 outputs: []outputInfo{ 5613 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5614 }, 5615 }, 5616 }, 5617 { 5618 name: "SBBLcarrymask", 5619 argLen: 1, 5620 asm: x86.ASBBL, 5621 reg: regInfo{ 5622 outputs: []outputInfo{ 5623 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5624 }, 5625 }, 5626 }, 5627 { 5628 name: "SETEQ", 5629 argLen: 1, 5630 asm: x86.ASETEQ, 5631 reg: regInfo{ 5632 outputs: []outputInfo{ 5633 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5634 }, 5635 }, 5636 }, 5637 { 5638 name: "SETNE", 5639 argLen: 1, 5640 asm: x86.ASETNE, 5641 reg: regInfo{ 5642 outputs: []outputInfo{ 5643 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5644 }, 5645 }, 5646 }, 5647 { 5648 name: "SETL", 5649 argLen: 1, 5650 asm: x86.ASETLT, 5651 reg: regInfo{ 5652 outputs: []outputInfo{ 5653 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5654 }, 5655 }, 5656 }, 5657 { 5658 name: "SETLE", 5659 argLen: 1, 5660 asm: x86.ASETLE, 5661 reg: regInfo{ 5662 outputs: []outputInfo{ 5663 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5664 }, 5665 }, 5666 }, 5667 { 5668 name: "SETG", 5669 argLen: 1, 5670 asm: x86.ASETGT, 5671 reg: regInfo{ 5672 outputs: []outputInfo{ 5673 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5674 }, 5675 }, 5676 }, 5677 { 5678 name: "SETGE", 5679 argLen: 1, 5680 asm: x86.ASETGE, 5681 reg: regInfo{ 5682 outputs: []outputInfo{ 5683 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5684 }, 5685 }, 5686 }, 5687 { 5688 name: "SETB", 5689 argLen: 1, 5690 asm: x86.ASETCS, 5691 reg: regInfo{ 5692 outputs: []outputInfo{ 5693 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5694 }, 5695 }, 5696 }, 5697 { 5698 name: "SETBE", 5699 argLen: 1, 5700 asm: x86.ASETLS, 5701 reg: regInfo{ 5702 outputs: []outputInfo{ 5703 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5704 }, 5705 }, 5706 }, 5707 { 5708 name: "SETA", 5709 argLen: 1, 5710 asm: x86.ASETHI, 5711 reg: regInfo{ 5712 outputs: []outputInfo{ 5713 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5714 }, 5715 }, 5716 }, 5717 { 5718 name: "SETAE", 5719 argLen: 1, 5720 asm: x86.ASETCC, 5721 reg: regInfo{ 5722 outputs: []outputInfo{ 5723 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5724 }, 5725 }, 5726 }, 5727 { 5728 name: "SETEQF", 5729 argLen: 1, 5730 clobberFlags: true, 5731 asm: x86.ASETEQ, 5732 reg: regInfo{ 5733 clobbers: 1, // AX 5734 outputs: []outputInfo{ 5735 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5736 }, 5737 }, 5738 }, 5739 { 5740 name: "SETNEF", 5741 argLen: 1, 5742 clobberFlags: true, 5743 asm: x86.ASETNE, 5744 reg: regInfo{ 5745 clobbers: 1, // AX 5746 outputs: []outputInfo{ 5747 {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5748 }, 5749 }, 5750 }, 5751 { 5752 name: "SETORD", 5753 argLen: 1, 5754 asm: x86.ASETPC, 5755 reg: regInfo{ 5756 outputs: []outputInfo{ 5757 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5758 }, 5759 }, 5760 }, 5761 { 5762 name: "SETNAN", 5763 argLen: 1, 5764 asm: x86.ASETPS, 5765 reg: regInfo{ 5766 outputs: []outputInfo{ 5767 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5768 }, 5769 }, 5770 }, 5771 { 5772 name: "SETGF", 5773 argLen: 1, 5774 asm: x86.ASETHI, 5775 reg: regInfo{ 5776 outputs: []outputInfo{ 5777 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5778 }, 5779 }, 5780 }, 5781 { 5782 name: "SETGEF", 5783 argLen: 1, 5784 asm: x86.ASETCC, 5785 reg: regInfo{ 5786 outputs: []outputInfo{ 5787 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5788 }, 5789 }, 5790 }, 5791 { 5792 name: "MOVBQSX", 5793 argLen: 1, 5794 asm: x86.AMOVBQSX, 5795 reg: regInfo{ 5796 inputs: []inputInfo{ 5797 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5798 }, 5799 outputs: []outputInfo{ 5800 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5801 }, 5802 }, 5803 }, 5804 { 5805 name: "MOVBQZX", 5806 argLen: 1, 5807 asm: x86.AMOVBLZX, 5808 reg: regInfo{ 5809 inputs: []inputInfo{ 5810 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5811 }, 5812 outputs: []outputInfo{ 5813 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5814 }, 5815 }, 5816 }, 5817 { 5818 name: "MOVWQSX", 5819 argLen: 1, 5820 asm: x86.AMOVWQSX, 5821 reg: regInfo{ 5822 inputs: []inputInfo{ 5823 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5824 }, 5825 outputs: []outputInfo{ 5826 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5827 }, 5828 }, 5829 }, 5830 { 5831 name: "MOVWQZX", 5832 argLen: 1, 5833 asm: x86.AMOVWLZX, 5834 reg: regInfo{ 5835 inputs: []inputInfo{ 5836 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5837 }, 5838 outputs: []outputInfo{ 5839 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5840 }, 5841 }, 5842 }, 5843 { 5844 name: "MOVLQSX", 5845 argLen: 1, 5846 asm: x86.AMOVLQSX, 5847 reg: regInfo{ 5848 inputs: []inputInfo{ 5849 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5850 }, 5851 outputs: []outputInfo{ 5852 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5853 }, 5854 }, 5855 }, 5856 { 5857 name: "MOVLQZX", 5858 argLen: 1, 5859 asm: x86.AMOVL, 5860 reg: regInfo{ 5861 inputs: []inputInfo{ 5862 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5863 }, 5864 outputs: []outputInfo{ 5865 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5866 }, 5867 }, 5868 }, 5869 { 5870 name: "MOVLconst", 5871 auxType: auxInt32, 5872 argLen: 0, 5873 rematerializeable: true, 5874 asm: x86.AMOVL, 5875 reg: regInfo{ 5876 outputs: []outputInfo{ 5877 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5878 }, 5879 }, 5880 }, 5881 { 5882 name: "MOVQconst", 5883 auxType: auxInt64, 5884 argLen: 0, 5885 rematerializeable: true, 5886 asm: x86.AMOVQ, 5887 reg: regInfo{ 5888 outputs: []outputInfo{ 5889 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5890 }, 5891 }, 5892 }, 5893 { 5894 name: "CVTTSD2SL", 5895 argLen: 1, 5896 asm: x86.ACVTTSD2SL, 5897 reg: regInfo{ 5898 inputs: []inputInfo{ 5899 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5900 }, 5901 outputs: []outputInfo{ 5902 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5903 }, 5904 }, 5905 }, 5906 { 5907 name: "CVTTSD2SQ", 5908 argLen: 1, 5909 asm: x86.ACVTTSD2SQ, 5910 reg: regInfo{ 5911 inputs: []inputInfo{ 5912 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5913 }, 5914 outputs: []outputInfo{ 5915 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5916 }, 5917 }, 5918 }, 5919 { 5920 name: "CVTTSS2SL", 5921 argLen: 1, 5922 asm: x86.ACVTTSS2SL, 5923 reg: regInfo{ 5924 inputs: []inputInfo{ 5925 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5926 }, 5927 outputs: []outputInfo{ 5928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5929 }, 5930 }, 5931 }, 5932 { 5933 name: "CVTTSS2SQ", 5934 argLen: 1, 5935 asm: x86.ACVTTSS2SQ, 5936 reg: regInfo{ 5937 inputs: []inputInfo{ 5938 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5939 }, 5940 outputs: []outputInfo{ 5941 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5942 }, 5943 }, 5944 }, 5945 { 5946 name: "CVTSL2SS", 5947 argLen: 1, 5948 asm: x86.ACVTSL2SS, 5949 reg: regInfo{ 5950 inputs: []inputInfo{ 5951 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5952 }, 5953 outputs: []outputInfo{ 5954 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5955 }, 5956 }, 5957 }, 5958 { 5959 name: "CVTSL2SD", 5960 argLen: 1, 5961 asm: x86.ACVTSL2SD, 5962 reg: regInfo{ 5963 inputs: []inputInfo{ 5964 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5965 }, 5966 outputs: []outputInfo{ 5967 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5968 }, 5969 }, 5970 }, 5971 { 5972 name: "CVTSQ2SS", 5973 argLen: 1, 5974 asm: x86.ACVTSQ2SS, 5975 reg: regInfo{ 5976 inputs: []inputInfo{ 5977 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5978 }, 5979 outputs: []outputInfo{ 5980 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5981 }, 5982 }, 5983 }, 5984 { 5985 name: "CVTSQ2SD", 5986 argLen: 1, 5987 asm: x86.ACVTSQ2SD, 5988 reg: regInfo{ 5989 inputs: []inputInfo{ 5990 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 5991 }, 5992 outputs: []outputInfo{ 5993 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 5994 }, 5995 }, 5996 }, 5997 { 5998 name: "CVTSD2SS", 5999 argLen: 1, 6000 asm: x86.ACVTSD2SS, 6001 reg: regInfo{ 6002 inputs: []inputInfo{ 6003 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6004 }, 6005 outputs: []outputInfo{ 6006 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6007 }, 6008 }, 6009 }, 6010 { 6011 name: "CVTSS2SD", 6012 argLen: 1, 6013 asm: x86.ACVTSS2SD, 6014 reg: regInfo{ 6015 inputs: []inputInfo{ 6016 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6017 }, 6018 outputs: []outputInfo{ 6019 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6020 }, 6021 }, 6022 }, 6023 { 6024 name: "PXOR", 6025 argLen: 2, 6026 commutative: true, 6027 resultInArg0: true, 6028 asm: x86.APXOR, 6029 reg: regInfo{ 6030 inputs: []inputInfo{ 6031 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6032 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6033 }, 6034 outputs: []outputInfo{ 6035 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6036 }, 6037 }, 6038 }, 6039 { 6040 name: "LEAQ", 6041 auxType: auxSymOff, 6042 argLen: 1, 6043 rematerializeable: true, 6044 asm: x86.ALEAQ, 6045 reg: regInfo{ 6046 inputs: []inputInfo{ 6047 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6048 }, 6049 outputs: []outputInfo{ 6050 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6051 }, 6052 }, 6053 }, 6054 { 6055 name: "LEAQ1", 6056 auxType: auxSymOff, 6057 argLen: 2, 6058 reg: regInfo{ 6059 inputs: []inputInfo{ 6060 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6061 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6062 }, 6063 outputs: []outputInfo{ 6064 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6065 }, 6066 }, 6067 }, 6068 { 6069 name: "LEAQ2", 6070 auxType: auxSymOff, 6071 argLen: 2, 6072 reg: regInfo{ 6073 inputs: []inputInfo{ 6074 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6075 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6076 }, 6077 outputs: []outputInfo{ 6078 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6079 }, 6080 }, 6081 }, 6082 { 6083 name: "LEAQ4", 6084 auxType: auxSymOff, 6085 argLen: 2, 6086 reg: regInfo{ 6087 inputs: []inputInfo{ 6088 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6089 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6090 }, 6091 outputs: []outputInfo{ 6092 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6093 }, 6094 }, 6095 }, 6096 { 6097 name: "LEAQ8", 6098 auxType: auxSymOff, 6099 argLen: 2, 6100 reg: regInfo{ 6101 inputs: []inputInfo{ 6102 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6103 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6104 }, 6105 outputs: []outputInfo{ 6106 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6107 }, 6108 }, 6109 }, 6110 { 6111 name: "LEAL", 6112 auxType: auxSymOff, 6113 argLen: 1, 6114 rematerializeable: true, 6115 asm: x86.ALEAL, 6116 reg: regInfo{ 6117 inputs: []inputInfo{ 6118 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6119 }, 6120 outputs: []outputInfo{ 6121 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6122 }, 6123 }, 6124 }, 6125 { 6126 name: "MOVBload", 6127 auxType: auxSymOff, 6128 argLen: 2, 6129 asm: x86.AMOVBLZX, 6130 reg: regInfo{ 6131 inputs: []inputInfo{ 6132 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6133 }, 6134 outputs: []outputInfo{ 6135 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6136 }, 6137 }, 6138 }, 6139 { 6140 name: "MOVBQSXload", 6141 auxType: auxSymOff, 6142 argLen: 2, 6143 asm: x86.AMOVBQSX, 6144 reg: regInfo{ 6145 inputs: []inputInfo{ 6146 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6147 }, 6148 outputs: []outputInfo{ 6149 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6150 }, 6151 }, 6152 }, 6153 { 6154 name: "MOVWload", 6155 auxType: auxSymOff, 6156 argLen: 2, 6157 asm: x86.AMOVWLZX, 6158 reg: regInfo{ 6159 inputs: []inputInfo{ 6160 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6161 }, 6162 outputs: []outputInfo{ 6163 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6164 }, 6165 }, 6166 }, 6167 { 6168 name: "MOVWQSXload", 6169 auxType: auxSymOff, 6170 argLen: 2, 6171 asm: x86.AMOVWQSX, 6172 reg: regInfo{ 6173 inputs: []inputInfo{ 6174 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6175 }, 6176 outputs: []outputInfo{ 6177 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6178 }, 6179 }, 6180 }, 6181 { 6182 name: "MOVLload", 6183 auxType: auxSymOff, 6184 argLen: 2, 6185 asm: x86.AMOVL, 6186 reg: regInfo{ 6187 inputs: []inputInfo{ 6188 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6189 }, 6190 outputs: []outputInfo{ 6191 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6192 }, 6193 }, 6194 }, 6195 { 6196 name: "MOVLQSXload", 6197 auxType: auxSymOff, 6198 argLen: 2, 6199 asm: x86.AMOVLQSX, 6200 reg: regInfo{ 6201 inputs: []inputInfo{ 6202 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6203 }, 6204 outputs: []outputInfo{ 6205 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6206 }, 6207 }, 6208 }, 6209 { 6210 name: "MOVQload", 6211 auxType: auxSymOff, 6212 argLen: 2, 6213 asm: x86.AMOVQ, 6214 reg: regInfo{ 6215 inputs: []inputInfo{ 6216 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6217 }, 6218 outputs: []outputInfo{ 6219 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6220 }, 6221 }, 6222 }, 6223 { 6224 name: "MOVBstore", 6225 auxType: auxSymOff, 6226 argLen: 3, 6227 asm: x86.AMOVB, 6228 reg: regInfo{ 6229 inputs: []inputInfo{ 6230 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6231 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6232 }, 6233 }, 6234 }, 6235 { 6236 name: "MOVWstore", 6237 auxType: auxSymOff, 6238 argLen: 3, 6239 asm: x86.AMOVW, 6240 reg: regInfo{ 6241 inputs: []inputInfo{ 6242 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6243 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6244 }, 6245 }, 6246 }, 6247 { 6248 name: "MOVLstore", 6249 auxType: auxSymOff, 6250 argLen: 3, 6251 asm: x86.AMOVL, 6252 reg: regInfo{ 6253 inputs: []inputInfo{ 6254 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6255 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6256 }, 6257 }, 6258 }, 6259 { 6260 name: "MOVQstore", 6261 auxType: auxSymOff, 6262 argLen: 3, 6263 asm: x86.AMOVQ, 6264 reg: regInfo{ 6265 inputs: []inputInfo{ 6266 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6267 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6268 }, 6269 }, 6270 }, 6271 { 6272 name: "MOVOload", 6273 auxType: auxSymOff, 6274 argLen: 2, 6275 asm: x86.AMOVUPS, 6276 reg: regInfo{ 6277 inputs: []inputInfo{ 6278 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6279 }, 6280 outputs: []outputInfo{ 6281 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6282 }, 6283 }, 6284 }, 6285 { 6286 name: "MOVOstore", 6287 auxType: auxSymOff, 6288 argLen: 3, 6289 asm: x86.AMOVUPS, 6290 reg: regInfo{ 6291 inputs: []inputInfo{ 6292 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6293 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6294 }, 6295 }, 6296 }, 6297 { 6298 name: "MOVBloadidx1", 6299 auxType: auxSymOff, 6300 argLen: 3, 6301 asm: x86.AMOVBLZX, 6302 reg: regInfo{ 6303 inputs: []inputInfo{ 6304 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6305 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6306 }, 6307 outputs: []outputInfo{ 6308 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6309 }, 6310 }, 6311 }, 6312 { 6313 name: "MOVWloadidx1", 6314 auxType: auxSymOff, 6315 argLen: 3, 6316 asm: x86.AMOVWLZX, 6317 reg: regInfo{ 6318 inputs: []inputInfo{ 6319 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6320 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6321 }, 6322 outputs: []outputInfo{ 6323 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6324 }, 6325 }, 6326 }, 6327 { 6328 name: "MOVWloadidx2", 6329 auxType: auxSymOff, 6330 argLen: 3, 6331 asm: x86.AMOVWLZX, 6332 reg: regInfo{ 6333 inputs: []inputInfo{ 6334 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6335 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6336 }, 6337 outputs: []outputInfo{ 6338 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6339 }, 6340 }, 6341 }, 6342 { 6343 name: "MOVLloadidx1", 6344 auxType: auxSymOff, 6345 argLen: 3, 6346 asm: x86.AMOVL, 6347 reg: regInfo{ 6348 inputs: []inputInfo{ 6349 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6350 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6351 }, 6352 outputs: []outputInfo{ 6353 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6354 }, 6355 }, 6356 }, 6357 { 6358 name: "MOVLloadidx4", 6359 auxType: auxSymOff, 6360 argLen: 3, 6361 asm: x86.AMOVL, 6362 reg: regInfo{ 6363 inputs: []inputInfo{ 6364 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6365 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6366 }, 6367 outputs: []outputInfo{ 6368 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6369 }, 6370 }, 6371 }, 6372 { 6373 name: "MOVQloadidx1", 6374 auxType: auxSymOff, 6375 argLen: 3, 6376 asm: x86.AMOVQ, 6377 reg: regInfo{ 6378 inputs: []inputInfo{ 6379 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6380 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6381 }, 6382 outputs: []outputInfo{ 6383 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6384 }, 6385 }, 6386 }, 6387 { 6388 name: "MOVQloadidx8", 6389 auxType: auxSymOff, 6390 argLen: 3, 6391 asm: x86.AMOVQ, 6392 reg: regInfo{ 6393 inputs: []inputInfo{ 6394 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6395 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6396 }, 6397 outputs: []outputInfo{ 6398 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6399 }, 6400 }, 6401 }, 6402 { 6403 name: "MOVBstoreidx1", 6404 auxType: auxSymOff, 6405 argLen: 4, 6406 asm: x86.AMOVB, 6407 reg: regInfo{ 6408 inputs: []inputInfo{ 6409 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6410 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6411 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6412 }, 6413 }, 6414 }, 6415 { 6416 name: "MOVWstoreidx1", 6417 auxType: auxSymOff, 6418 argLen: 4, 6419 asm: x86.AMOVW, 6420 reg: regInfo{ 6421 inputs: []inputInfo{ 6422 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6423 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6424 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6425 }, 6426 }, 6427 }, 6428 { 6429 name: "MOVWstoreidx2", 6430 auxType: auxSymOff, 6431 argLen: 4, 6432 asm: x86.AMOVW, 6433 reg: regInfo{ 6434 inputs: []inputInfo{ 6435 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6436 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6437 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6438 }, 6439 }, 6440 }, 6441 { 6442 name: "MOVLstoreidx1", 6443 auxType: auxSymOff, 6444 argLen: 4, 6445 asm: x86.AMOVL, 6446 reg: regInfo{ 6447 inputs: []inputInfo{ 6448 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6449 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6450 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6451 }, 6452 }, 6453 }, 6454 { 6455 name: "MOVLstoreidx4", 6456 auxType: auxSymOff, 6457 argLen: 4, 6458 asm: x86.AMOVL, 6459 reg: regInfo{ 6460 inputs: []inputInfo{ 6461 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6462 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6463 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6464 }, 6465 }, 6466 }, 6467 { 6468 name: "MOVQstoreidx1", 6469 auxType: auxSymOff, 6470 argLen: 4, 6471 asm: x86.AMOVQ, 6472 reg: regInfo{ 6473 inputs: []inputInfo{ 6474 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6475 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6476 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6477 }, 6478 }, 6479 }, 6480 { 6481 name: "MOVQstoreidx8", 6482 auxType: auxSymOff, 6483 argLen: 4, 6484 asm: x86.AMOVQ, 6485 reg: regInfo{ 6486 inputs: []inputInfo{ 6487 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6488 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6489 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6490 }, 6491 }, 6492 }, 6493 { 6494 name: "MOVBstoreconst", 6495 auxType: auxSymValAndOff, 6496 argLen: 2, 6497 asm: x86.AMOVB, 6498 reg: regInfo{ 6499 inputs: []inputInfo{ 6500 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6501 }, 6502 }, 6503 }, 6504 { 6505 name: "MOVWstoreconst", 6506 auxType: auxSymValAndOff, 6507 argLen: 2, 6508 asm: x86.AMOVW, 6509 reg: regInfo{ 6510 inputs: []inputInfo{ 6511 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6512 }, 6513 }, 6514 }, 6515 { 6516 name: "MOVLstoreconst", 6517 auxType: auxSymValAndOff, 6518 argLen: 2, 6519 asm: x86.AMOVL, 6520 reg: regInfo{ 6521 inputs: []inputInfo{ 6522 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6523 }, 6524 }, 6525 }, 6526 { 6527 name: "MOVQstoreconst", 6528 auxType: auxSymValAndOff, 6529 argLen: 2, 6530 asm: x86.AMOVQ, 6531 reg: regInfo{ 6532 inputs: []inputInfo{ 6533 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6534 }, 6535 }, 6536 }, 6537 { 6538 name: "MOVBstoreconstidx1", 6539 auxType: auxSymValAndOff, 6540 argLen: 3, 6541 asm: x86.AMOVB, 6542 reg: regInfo{ 6543 inputs: []inputInfo{ 6544 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6545 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6546 }, 6547 }, 6548 }, 6549 { 6550 name: "MOVWstoreconstidx1", 6551 auxType: auxSymValAndOff, 6552 argLen: 3, 6553 asm: x86.AMOVW, 6554 reg: regInfo{ 6555 inputs: []inputInfo{ 6556 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6557 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6558 }, 6559 }, 6560 }, 6561 { 6562 name: "MOVWstoreconstidx2", 6563 auxType: auxSymValAndOff, 6564 argLen: 3, 6565 asm: x86.AMOVW, 6566 reg: regInfo{ 6567 inputs: []inputInfo{ 6568 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6569 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6570 }, 6571 }, 6572 }, 6573 { 6574 name: "MOVLstoreconstidx1", 6575 auxType: auxSymValAndOff, 6576 argLen: 3, 6577 asm: x86.AMOVL, 6578 reg: regInfo{ 6579 inputs: []inputInfo{ 6580 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6581 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6582 }, 6583 }, 6584 }, 6585 { 6586 name: "MOVLstoreconstidx4", 6587 auxType: auxSymValAndOff, 6588 argLen: 3, 6589 asm: x86.AMOVL, 6590 reg: regInfo{ 6591 inputs: []inputInfo{ 6592 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6593 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6594 }, 6595 }, 6596 }, 6597 { 6598 name: "MOVQstoreconstidx1", 6599 auxType: auxSymValAndOff, 6600 argLen: 3, 6601 asm: x86.AMOVQ, 6602 reg: regInfo{ 6603 inputs: []inputInfo{ 6604 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6605 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6606 }, 6607 }, 6608 }, 6609 { 6610 name: "MOVQstoreconstidx8", 6611 auxType: auxSymValAndOff, 6612 argLen: 3, 6613 asm: x86.AMOVQ, 6614 reg: regInfo{ 6615 inputs: []inputInfo{ 6616 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6617 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6618 }, 6619 }, 6620 }, 6621 { 6622 name: "DUFFZERO", 6623 auxType: auxInt64, 6624 argLen: 3, 6625 clobberFlags: true, 6626 reg: regInfo{ 6627 inputs: []inputInfo{ 6628 {0, 128}, // DI 6629 {1, 65536}, // X0 6630 }, 6631 clobbers: 128, // DI 6632 }, 6633 }, 6634 { 6635 name: "MOVOconst", 6636 auxType: auxInt128, 6637 argLen: 0, 6638 rematerializeable: true, 6639 reg: regInfo{ 6640 outputs: []outputInfo{ 6641 {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6642 }, 6643 }, 6644 }, 6645 { 6646 name: "REPSTOSQ", 6647 argLen: 4, 6648 reg: regInfo{ 6649 inputs: []inputInfo{ 6650 {0, 128}, // DI 6651 {1, 2}, // CX 6652 {2, 1}, // AX 6653 }, 6654 clobbers: 130, // CX DI 6655 }, 6656 }, 6657 { 6658 name: "CALLstatic", 6659 auxType: auxSymOff, 6660 argLen: 1, 6661 clobberFlags: true, 6662 reg: regInfo{ 6663 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6664 }, 6665 }, 6666 { 6667 name: "CALLclosure", 6668 auxType: auxInt64, 6669 argLen: 3, 6670 clobberFlags: true, 6671 reg: regInfo{ 6672 inputs: []inputInfo{ 6673 {1, 4}, // DX 6674 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6675 }, 6676 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6677 }, 6678 }, 6679 { 6680 name: "CALLdefer", 6681 auxType: auxInt64, 6682 argLen: 1, 6683 clobberFlags: true, 6684 reg: regInfo{ 6685 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6686 }, 6687 }, 6688 { 6689 name: "CALLgo", 6690 auxType: auxInt64, 6691 argLen: 1, 6692 clobberFlags: true, 6693 reg: regInfo{ 6694 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6695 }, 6696 }, 6697 { 6698 name: "CALLinter", 6699 auxType: auxInt64, 6700 argLen: 2, 6701 clobberFlags: true, 6702 reg: regInfo{ 6703 inputs: []inputInfo{ 6704 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6705 }, 6706 clobbers: 4294967279, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 6707 }, 6708 }, 6709 { 6710 name: "DUFFCOPY", 6711 auxType: auxInt64, 6712 argLen: 3, 6713 clobberFlags: true, 6714 reg: regInfo{ 6715 inputs: []inputInfo{ 6716 {0, 128}, // DI 6717 {1, 64}, // SI 6718 }, 6719 clobbers: 65728, // SI DI X0 6720 }, 6721 }, 6722 { 6723 name: "REPMOVSQ", 6724 argLen: 4, 6725 reg: regInfo{ 6726 inputs: []inputInfo{ 6727 {0, 128}, // DI 6728 {1, 64}, // SI 6729 {2, 2}, // CX 6730 }, 6731 clobbers: 194, // CX SI DI 6732 }, 6733 }, 6734 { 6735 name: "InvertFlags", 6736 argLen: 1, 6737 reg: regInfo{}, 6738 }, 6739 { 6740 name: "LoweredGetG", 6741 argLen: 1, 6742 reg: regInfo{ 6743 outputs: []outputInfo{ 6744 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6745 }, 6746 }, 6747 }, 6748 { 6749 name: "LoweredGetClosurePtr", 6750 argLen: 0, 6751 reg: regInfo{ 6752 outputs: []outputInfo{ 6753 {0, 4}, // DX 6754 }, 6755 }, 6756 }, 6757 { 6758 name: "LoweredNilCheck", 6759 argLen: 2, 6760 clobberFlags: true, 6761 reg: regInfo{ 6762 inputs: []inputInfo{ 6763 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6764 }, 6765 }, 6766 }, 6767 { 6768 name: "MOVQconvert", 6769 argLen: 2, 6770 asm: x86.AMOVQ, 6771 reg: regInfo{ 6772 inputs: []inputInfo{ 6773 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6774 }, 6775 outputs: []outputInfo{ 6776 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6777 }, 6778 }, 6779 }, 6780 { 6781 name: "MOVLconvert", 6782 argLen: 2, 6783 asm: x86.AMOVL, 6784 reg: regInfo{ 6785 inputs: []inputInfo{ 6786 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6787 }, 6788 outputs: []outputInfo{ 6789 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6790 }, 6791 }, 6792 }, 6793 { 6794 name: "FlagEQ", 6795 argLen: 0, 6796 reg: regInfo{}, 6797 }, 6798 { 6799 name: "FlagLT_ULT", 6800 argLen: 0, 6801 reg: regInfo{}, 6802 }, 6803 { 6804 name: "FlagLT_UGT", 6805 argLen: 0, 6806 reg: regInfo{}, 6807 }, 6808 { 6809 name: "FlagGT_UGT", 6810 argLen: 0, 6811 reg: regInfo{}, 6812 }, 6813 { 6814 name: "FlagGT_ULT", 6815 argLen: 0, 6816 reg: regInfo{}, 6817 }, 6818 { 6819 name: "MOVLatomicload", 6820 auxType: auxSymOff, 6821 argLen: 2, 6822 asm: x86.AMOVL, 6823 reg: regInfo{ 6824 inputs: []inputInfo{ 6825 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6826 }, 6827 outputs: []outputInfo{ 6828 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6829 }, 6830 }, 6831 }, 6832 { 6833 name: "MOVQatomicload", 6834 auxType: auxSymOff, 6835 argLen: 2, 6836 asm: x86.AMOVQ, 6837 reg: regInfo{ 6838 inputs: []inputInfo{ 6839 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6840 }, 6841 outputs: []outputInfo{ 6842 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6843 }, 6844 }, 6845 }, 6846 { 6847 name: "XCHGL", 6848 auxType: auxSymOff, 6849 argLen: 3, 6850 resultInArg0: true, 6851 asm: x86.AXCHGL, 6852 reg: regInfo{ 6853 inputs: []inputInfo{ 6854 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6855 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6856 }, 6857 outputs: []outputInfo{ 6858 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6859 }, 6860 }, 6861 }, 6862 { 6863 name: "XCHGQ", 6864 auxType: auxSymOff, 6865 argLen: 3, 6866 resultInArg0: true, 6867 asm: x86.AXCHGQ, 6868 reg: regInfo{ 6869 inputs: []inputInfo{ 6870 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6871 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6872 }, 6873 outputs: []outputInfo{ 6874 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6875 }, 6876 }, 6877 }, 6878 { 6879 name: "XADDLlock", 6880 auxType: auxSymOff, 6881 argLen: 3, 6882 resultInArg0: true, 6883 asm: x86.AXADDL, 6884 reg: regInfo{ 6885 inputs: []inputInfo{ 6886 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6887 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6888 }, 6889 outputs: []outputInfo{ 6890 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6891 }, 6892 }, 6893 }, 6894 { 6895 name: "XADDQlock", 6896 auxType: auxSymOff, 6897 argLen: 3, 6898 resultInArg0: true, 6899 asm: x86.AXADDQ, 6900 reg: regInfo{ 6901 inputs: []inputInfo{ 6902 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6903 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6904 }, 6905 outputs: []outputInfo{ 6906 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6907 }, 6908 }, 6909 }, 6910 { 6911 name: "AddTupleFirst32", 6912 argLen: 2, 6913 reg: regInfo{}, 6914 }, 6915 { 6916 name: "AddTupleFirst64", 6917 argLen: 2, 6918 reg: regInfo{}, 6919 }, 6920 { 6921 name: "CMPXCHGLlock", 6922 auxType: auxSymOff, 6923 argLen: 4, 6924 asm: x86.ACMPXCHGL, 6925 reg: regInfo{ 6926 inputs: []inputInfo{ 6927 {1, 1}, // AX 6928 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6929 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6930 }, 6931 clobbers: 1, // AX 6932 outputs: []outputInfo{ 6933 {1, 0}, 6934 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6935 }, 6936 }, 6937 }, 6938 { 6939 name: "CMPXCHGQlock", 6940 auxType: auxSymOff, 6941 argLen: 4, 6942 asm: x86.ACMPXCHGQ, 6943 reg: regInfo{ 6944 inputs: []inputInfo{ 6945 {1, 1}, // AX 6946 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6947 {2, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6948 }, 6949 clobbers: 1, // AX 6950 outputs: []outputInfo{ 6951 {1, 0}, 6952 {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6953 }, 6954 }, 6955 }, 6956 { 6957 name: "ANDBlock", 6958 auxType: auxSymOff, 6959 argLen: 3, 6960 asm: x86.AANDB, 6961 reg: regInfo{ 6962 inputs: []inputInfo{ 6963 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6964 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6965 }, 6966 }, 6967 }, 6968 { 6969 name: "ORBlock", 6970 auxType: auxSymOff, 6971 argLen: 3, 6972 asm: x86.AORB, 6973 reg: regInfo{ 6974 inputs: []inputInfo{ 6975 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 6976 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB 6977 }, 6978 }, 6979 }, 6980 6981 { 6982 name: "ADD", 6983 argLen: 2, 6984 commutative: true, 6985 asm: arm.AADD, 6986 reg: regInfo{ 6987 inputs: []inputInfo{ 6988 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6989 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 6990 }, 6991 outputs: []outputInfo{ 6992 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 6993 }, 6994 }, 6995 }, 6996 { 6997 name: "ADDconst", 6998 auxType: auxInt32, 6999 argLen: 1, 7000 asm: arm.AADD, 7001 reg: regInfo{ 7002 inputs: []inputInfo{ 7003 {0, 14335}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP 7004 }, 7005 outputs: []outputInfo{ 7006 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7007 }, 7008 }, 7009 }, 7010 { 7011 name: "SUB", 7012 argLen: 2, 7013 asm: arm.ASUB, 7014 reg: regInfo{ 7015 inputs: []inputInfo{ 7016 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7017 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7018 }, 7019 outputs: []outputInfo{ 7020 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7021 }, 7022 }, 7023 }, 7024 { 7025 name: "SUBconst", 7026 auxType: auxInt32, 7027 argLen: 1, 7028 asm: arm.ASUB, 7029 reg: regInfo{ 7030 inputs: []inputInfo{ 7031 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7032 }, 7033 outputs: []outputInfo{ 7034 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7035 }, 7036 }, 7037 }, 7038 { 7039 name: "RSB", 7040 argLen: 2, 7041 asm: arm.ARSB, 7042 reg: regInfo{ 7043 inputs: []inputInfo{ 7044 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7045 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7046 }, 7047 outputs: []outputInfo{ 7048 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7049 }, 7050 }, 7051 }, 7052 { 7053 name: "RSBconst", 7054 auxType: auxInt32, 7055 argLen: 1, 7056 asm: arm.ARSB, 7057 reg: regInfo{ 7058 inputs: []inputInfo{ 7059 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7060 }, 7061 outputs: []outputInfo{ 7062 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7063 }, 7064 }, 7065 }, 7066 { 7067 name: "MUL", 7068 argLen: 2, 7069 commutative: true, 7070 asm: arm.AMUL, 7071 reg: regInfo{ 7072 inputs: []inputInfo{ 7073 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7074 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7075 }, 7076 outputs: []outputInfo{ 7077 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7078 }, 7079 }, 7080 }, 7081 { 7082 name: "HMUL", 7083 argLen: 2, 7084 commutative: true, 7085 asm: arm.AMULL, 7086 reg: regInfo{ 7087 inputs: []inputInfo{ 7088 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7089 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7090 }, 7091 outputs: []outputInfo{ 7092 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7093 }, 7094 }, 7095 }, 7096 { 7097 name: "HMULU", 7098 argLen: 2, 7099 commutative: true, 7100 asm: arm.AMULLU, 7101 reg: regInfo{ 7102 inputs: []inputInfo{ 7103 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7104 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7105 }, 7106 outputs: []outputInfo{ 7107 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7108 }, 7109 }, 7110 }, 7111 { 7112 name: "DIV", 7113 argLen: 2, 7114 clobberFlags: true, 7115 asm: arm.ADIV, 7116 reg: regInfo{ 7117 inputs: []inputInfo{ 7118 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7119 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7120 }, 7121 outputs: []outputInfo{ 7122 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7123 }, 7124 }, 7125 }, 7126 { 7127 name: "DIVU", 7128 argLen: 2, 7129 clobberFlags: true, 7130 asm: arm.ADIVU, 7131 reg: regInfo{ 7132 inputs: []inputInfo{ 7133 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7134 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7135 }, 7136 outputs: []outputInfo{ 7137 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7138 }, 7139 }, 7140 }, 7141 { 7142 name: "MOD", 7143 argLen: 2, 7144 clobberFlags: true, 7145 asm: arm.AMOD, 7146 reg: regInfo{ 7147 inputs: []inputInfo{ 7148 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7149 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7150 }, 7151 outputs: []outputInfo{ 7152 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7153 }, 7154 }, 7155 }, 7156 { 7157 name: "MODU", 7158 argLen: 2, 7159 clobberFlags: true, 7160 asm: arm.AMODU, 7161 reg: regInfo{ 7162 inputs: []inputInfo{ 7163 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7164 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7165 }, 7166 outputs: []outputInfo{ 7167 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7168 }, 7169 }, 7170 }, 7171 { 7172 name: "ADDS", 7173 argLen: 2, 7174 commutative: true, 7175 asm: arm.AADD, 7176 reg: regInfo{ 7177 inputs: []inputInfo{ 7178 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7179 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7180 }, 7181 outputs: []outputInfo{ 7182 {1, 0}, 7183 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7184 }, 7185 }, 7186 }, 7187 { 7188 name: "ADDSconst", 7189 auxType: auxInt32, 7190 argLen: 1, 7191 asm: arm.AADD, 7192 reg: regInfo{ 7193 inputs: []inputInfo{ 7194 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7195 }, 7196 outputs: []outputInfo{ 7197 {1, 0}, 7198 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7199 }, 7200 }, 7201 }, 7202 { 7203 name: "ADC", 7204 argLen: 3, 7205 commutative: true, 7206 asm: arm.AADC, 7207 reg: regInfo{ 7208 inputs: []inputInfo{ 7209 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7210 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7211 }, 7212 outputs: []outputInfo{ 7213 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7214 }, 7215 }, 7216 }, 7217 { 7218 name: "ADCconst", 7219 auxType: auxInt32, 7220 argLen: 2, 7221 asm: arm.AADC, 7222 reg: regInfo{ 7223 inputs: []inputInfo{ 7224 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7225 }, 7226 outputs: []outputInfo{ 7227 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7228 }, 7229 }, 7230 }, 7231 { 7232 name: "SUBS", 7233 argLen: 2, 7234 asm: arm.ASUB, 7235 reg: regInfo{ 7236 inputs: []inputInfo{ 7237 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7238 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7239 }, 7240 outputs: []outputInfo{ 7241 {1, 0}, 7242 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7243 }, 7244 }, 7245 }, 7246 { 7247 name: "SUBSconst", 7248 auxType: auxInt32, 7249 argLen: 1, 7250 asm: arm.ASUB, 7251 reg: regInfo{ 7252 inputs: []inputInfo{ 7253 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7254 }, 7255 outputs: []outputInfo{ 7256 {1, 0}, 7257 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7258 }, 7259 }, 7260 }, 7261 { 7262 name: "RSBSconst", 7263 auxType: auxInt32, 7264 argLen: 1, 7265 asm: arm.ARSB, 7266 reg: regInfo{ 7267 inputs: []inputInfo{ 7268 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7269 }, 7270 outputs: []outputInfo{ 7271 {1, 0}, 7272 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7273 }, 7274 }, 7275 }, 7276 { 7277 name: "SBC", 7278 argLen: 3, 7279 asm: arm.ASBC, 7280 reg: regInfo{ 7281 inputs: []inputInfo{ 7282 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7283 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7284 }, 7285 outputs: []outputInfo{ 7286 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7287 }, 7288 }, 7289 }, 7290 { 7291 name: "SBCconst", 7292 auxType: auxInt32, 7293 argLen: 2, 7294 asm: arm.ASBC, 7295 reg: regInfo{ 7296 inputs: []inputInfo{ 7297 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7298 }, 7299 outputs: []outputInfo{ 7300 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7301 }, 7302 }, 7303 }, 7304 { 7305 name: "RSCconst", 7306 auxType: auxInt32, 7307 argLen: 2, 7308 asm: arm.ARSC, 7309 reg: regInfo{ 7310 inputs: []inputInfo{ 7311 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7312 }, 7313 outputs: []outputInfo{ 7314 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7315 }, 7316 }, 7317 }, 7318 { 7319 name: "MULLU", 7320 argLen: 2, 7321 commutative: true, 7322 asm: arm.AMULLU, 7323 reg: regInfo{ 7324 inputs: []inputInfo{ 7325 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7326 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7327 }, 7328 outputs: []outputInfo{ 7329 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7330 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7331 }, 7332 }, 7333 }, 7334 { 7335 name: "MULA", 7336 argLen: 3, 7337 asm: arm.AMULA, 7338 reg: regInfo{ 7339 inputs: []inputInfo{ 7340 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7341 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7342 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7343 }, 7344 outputs: []outputInfo{ 7345 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7346 }, 7347 }, 7348 }, 7349 { 7350 name: "ADDF", 7351 argLen: 2, 7352 commutative: true, 7353 asm: arm.AADDF, 7354 reg: regInfo{ 7355 inputs: []inputInfo{ 7356 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7357 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7358 }, 7359 outputs: []outputInfo{ 7360 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7361 }, 7362 }, 7363 }, 7364 { 7365 name: "ADDD", 7366 argLen: 2, 7367 commutative: true, 7368 asm: arm.AADDD, 7369 reg: regInfo{ 7370 inputs: []inputInfo{ 7371 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7372 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7373 }, 7374 outputs: []outputInfo{ 7375 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7376 }, 7377 }, 7378 }, 7379 { 7380 name: "SUBF", 7381 argLen: 2, 7382 asm: arm.ASUBF, 7383 reg: regInfo{ 7384 inputs: []inputInfo{ 7385 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7386 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7387 }, 7388 outputs: []outputInfo{ 7389 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7390 }, 7391 }, 7392 }, 7393 { 7394 name: "SUBD", 7395 argLen: 2, 7396 asm: arm.ASUBD, 7397 reg: regInfo{ 7398 inputs: []inputInfo{ 7399 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7400 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7401 }, 7402 outputs: []outputInfo{ 7403 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7404 }, 7405 }, 7406 }, 7407 { 7408 name: "MULF", 7409 argLen: 2, 7410 commutative: true, 7411 asm: arm.AMULF, 7412 reg: regInfo{ 7413 inputs: []inputInfo{ 7414 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7415 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7416 }, 7417 outputs: []outputInfo{ 7418 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7419 }, 7420 }, 7421 }, 7422 { 7423 name: "MULD", 7424 argLen: 2, 7425 commutative: true, 7426 asm: arm.AMULD, 7427 reg: regInfo{ 7428 inputs: []inputInfo{ 7429 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7430 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7431 }, 7432 outputs: []outputInfo{ 7433 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7434 }, 7435 }, 7436 }, 7437 { 7438 name: "DIVF", 7439 argLen: 2, 7440 asm: arm.ADIVF, 7441 reg: regInfo{ 7442 inputs: []inputInfo{ 7443 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7444 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7445 }, 7446 outputs: []outputInfo{ 7447 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7448 }, 7449 }, 7450 }, 7451 { 7452 name: "DIVD", 7453 argLen: 2, 7454 asm: arm.ADIVD, 7455 reg: regInfo{ 7456 inputs: []inputInfo{ 7457 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7458 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7459 }, 7460 outputs: []outputInfo{ 7461 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7462 }, 7463 }, 7464 }, 7465 { 7466 name: "AND", 7467 argLen: 2, 7468 commutative: true, 7469 asm: arm.AAND, 7470 reg: regInfo{ 7471 inputs: []inputInfo{ 7472 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7473 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7474 }, 7475 outputs: []outputInfo{ 7476 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7477 }, 7478 }, 7479 }, 7480 { 7481 name: "ANDconst", 7482 auxType: auxInt32, 7483 argLen: 1, 7484 asm: arm.AAND, 7485 reg: regInfo{ 7486 inputs: []inputInfo{ 7487 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7488 }, 7489 outputs: []outputInfo{ 7490 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7491 }, 7492 }, 7493 }, 7494 { 7495 name: "OR", 7496 argLen: 2, 7497 commutative: true, 7498 asm: arm.AORR, 7499 reg: regInfo{ 7500 inputs: []inputInfo{ 7501 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7502 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7503 }, 7504 outputs: []outputInfo{ 7505 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7506 }, 7507 }, 7508 }, 7509 { 7510 name: "ORconst", 7511 auxType: auxInt32, 7512 argLen: 1, 7513 asm: arm.AORR, 7514 reg: regInfo{ 7515 inputs: []inputInfo{ 7516 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7517 }, 7518 outputs: []outputInfo{ 7519 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7520 }, 7521 }, 7522 }, 7523 { 7524 name: "XOR", 7525 argLen: 2, 7526 commutative: true, 7527 asm: arm.AEOR, 7528 reg: regInfo{ 7529 inputs: []inputInfo{ 7530 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7531 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7532 }, 7533 outputs: []outputInfo{ 7534 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7535 }, 7536 }, 7537 }, 7538 { 7539 name: "XORconst", 7540 auxType: auxInt32, 7541 argLen: 1, 7542 asm: arm.AEOR, 7543 reg: regInfo{ 7544 inputs: []inputInfo{ 7545 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7546 }, 7547 outputs: []outputInfo{ 7548 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7549 }, 7550 }, 7551 }, 7552 { 7553 name: "BIC", 7554 argLen: 2, 7555 asm: arm.ABIC, 7556 reg: regInfo{ 7557 inputs: []inputInfo{ 7558 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7559 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7560 }, 7561 outputs: []outputInfo{ 7562 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7563 }, 7564 }, 7565 }, 7566 { 7567 name: "BICconst", 7568 auxType: auxInt32, 7569 argLen: 1, 7570 asm: arm.ABIC, 7571 reg: regInfo{ 7572 inputs: []inputInfo{ 7573 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7574 }, 7575 outputs: []outputInfo{ 7576 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7577 }, 7578 }, 7579 }, 7580 { 7581 name: "MVN", 7582 argLen: 1, 7583 asm: arm.AMVN, 7584 reg: regInfo{ 7585 inputs: []inputInfo{ 7586 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7587 }, 7588 outputs: []outputInfo{ 7589 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7590 }, 7591 }, 7592 }, 7593 { 7594 name: "NEGF", 7595 argLen: 1, 7596 asm: arm.ANEGF, 7597 reg: regInfo{ 7598 inputs: []inputInfo{ 7599 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7600 }, 7601 outputs: []outputInfo{ 7602 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7603 }, 7604 }, 7605 }, 7606 { 7607 name: "NEGD", 7608 argLen: 1, 7609 asm: arm.ANEGD, 7610 reg: regInfo{ 7611 inputs: []inputInfo{ 7612 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7613 }, 7614 outputs: []outputInfo{ 7615 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7616 }, 7617 }, 7618 }, 7619 { 7620 name: "SQRTD", 7621 argLen: 1, 7622 asm: arm.ASQRTD, 7623 reg: regInfo{ 7624 inputs: []inputInfo{ 7625 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7626 }, 7627 outputs: []outputInfo{ 7628 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 7629 }, 7630 }, 7631 }, 7632 { 7633 name: "SLL", 7634 argLen: 2, 7635 asm: arm.ASLL, 7636 reg: regInfo{ 7637 inputs: []inputInfo{ 7638 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7639 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7640 }, 7641 outputs: []outputInfo{ 7642 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7643 }, 7644 }, 7645 }, 7646 { 7647 name: "SLLconst", 7648 auxType: auxInt32, 7649 argLen: 1, 7650 asm: arm.ASLL, 7651 reg: regInfo{ 7652 inputs: []inputInfo{ 7653 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7654 }, 7655 outputs: []outputInfo{ 7656 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7657 }, 7658 }, 7659 }, 7660 { 7661 name: "SRL", 7662 argLen: 2, 7663 asm: arm.ASRL, 7664 reg: regInfo{ 7665 inputs: []inputInfo{ 7666 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7667 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7668 }, 7669 outputs: []outputInfo{ 7670 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7671 }, 7672 }, 7673 }, 7674 { 7675 name: "SRLconst", 7676 auxType: auxInt32, 7677 argLen: 1, 7678 asm: arm.ASRL, 7679 reg: regInfo{ 7680 inputs: []inputInfo{ 7681 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7682 }, 7683 outputs: []outputInfo{ 7684 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7685 }, 7686 }, 7687 }, 7688 { 7689 name: "SRA", 7690 argLen: 2, 7691 asm: arm.ASRA, 7692 reg: regInfo{ 7693 inputs: []inputInfo{ 7694 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7695 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7696 }, 7697 outputs: []outputInfo{ 7698 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7699 }, 7700 }, 7701 }, 7702 { 7703 name: "SRAconst", 7704 auxType: auxInt32, 7705 argLen: 1, 7706 asm: arm.ASRA, 7707 reg: regInfo{ 7708 inputs: []inputInfo{ 7709 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7710 }, 7711 outputs: []outputInfo{ 7712 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7713 }, 7714 }, 7715 }, 7716 { 7717 name: "SRRconst", 7718 auxType: auxInt32, 7719 argLen: 1, 7720 reg: regInfo{ 7721 inputs: []inputInfo{ 7722 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7723 }, 7724 outputs: []outputInfo{ 7725 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7726 }, 7727 }, 7728 }, 7729 { 7730 name: "ADDshiftLL", 7731 auxType: auxInt32, 7732 argLen: 2, 7733 asm: arm.AADD, 7734 reg: regInfo{ 7735 inputs: []inputInfo{ 7736 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7737 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7738 }, 7739 outputs: []outputInfo{ 7740 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7741 }, 7742 }, 7743 }, 7744 { 7745 name: "ADDshiftRL", 7746 auxType: auxInt32, 7747 argLen: 2, 7748 asm: arm.AADD, 7749 reg: regInfo{ 7750 inputs: []inputInfo{ 7751 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7752 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7753 }, 7754 outputs: []outputInfo{ 7755 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7756 }, 7757 }, 7758 }, 7759 { 7760 name: "ADDshiftRA", 7761 auxType: auxInt32, 7762 argLen: 2, 7763 asm: arm.AADD, 7764 reg: regInfo{ 7765 inputs: []inputInfo{ 7766 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7767 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7768 }, 7769 outputs: []outputInfo{ 7770 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7771 }, 7772 }, 7773 }, 7774 { 7775 name: "SUBshiftLL", 7776 auxType: auxInt32, 7777 argLen: 2, 7778 asm: arm.ASUB, 7779 reg: regInfo{ 7780 inputs: []inputInfo{ 7781 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7782 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7783 }, 7784 outputs: []outputInfo{ 7785 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7786 }, 7787 }, 7788 }, 7789 { 7790 name: "SUBshiftRL", 7791 auxType: auxInt32, 7792 argLen: 2, 7793 asm: arm.ASUB, 7794 reg: regInfo{ 7795 inputs: []inputInfo{ 7796 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7797 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7798 }, 7799 outputs: []outputInfo{ 7800 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7801 }, 7802 }, 7803 }, 7804 { 7805 name: "SUBshiftRA", 7806 auxType: auxInt32, 7807 argLen: 2, 7808 asm: arm.ASUB, 7809 reg: regInfo{ 7810 inputs: []inputInfo{ 7811 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7812 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7813 }, 7814 outputs: []outputInfo{ 7815 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7816 }, 7817 }, 7818 }, 7819 { 7820 name: "RSBshiftLL", 7821 auxType: auxInt32, 7822 argLen: 2, 7823 asm: arm.ARSB, 7824 reg: regInfo{ 7825 inputs: []inputInfo{ 7826 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7827 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7828 }, 7829 outputs: []outputInfo{ 7830 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7831 }, 7832 }, 7833 }, 7834 { 7835 name: "RSBshiftRL", 7836 auxType: auxInt32, 7837 argLen: 2, 7838 asm: arm.ARSB, 7839 reg: regInfo{ 7840 inputs: []inputInfo{ 7841 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7842 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7843 }, 7844 outputs: []outputInfo{ 7845 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7846 }, 7847 }, 7848 }, 7849 { 7850 name: "RSBshiftRA", 7851 auxType: auxInt32, 7852 argLen: 2, 7853 asm: arm.ARSB, 7854 reg: regInfo{ 7855 inputs: []inputInfo{ 7856 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7857 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7858 }, 7859 outputs: []outputInfo{ 7860 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7861 }, 7862 }, 7863 }, 7864 { 7865 name: "ANDshiftLL", 7866 auxType: auxInt32, 7867 argLen: 2, 7868 asm: arm.AAND, 7869 reg: regInfo{ 7870 inputs: []inputInfo{ 7871 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7872 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7873 }, 7874 outputs: []outputInfo{ 7875 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7876 }, 7877 }, 7878 }, 7879 { 7880 name: "ANDshiftRL", 7881 auxType: auxInt32, 7882 argLen: 2, 7883 asm: arm.AAND, 7884 reg: regInfo{ 7885 inputs: []inputInfo{ 7886 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7887 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7888 }, 7889 outputs: []outputInfo{ 7890 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7891 }, 7892 }, 7893 }, 7894 { 7895 name: "ANDshiftRA", 7896 auxType: auxInt32, 7897 argLen: 2, 7898 asm: arm.AAND, 7899 reg: regInfo{ 7900 inputs: []inputInfo{ 7901 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7902 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7903 }, 7904 outputs: []outputInfo{ 7905 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7906 }, 7907 }, 7908 }, 7909 { 7910 name: "ORshiftLL", 7911 auxType: auxInt32, 7912 argLen: 2, 7913 asm: arm.AORR, 7914 reg: regInfo{ 7915 inputs: []inputInfo{ 7916 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7917 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7918 }, 7919 outputs: []outputInfo{ 7920 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7921 }, 7922 }, 7923 }, 7924 { 7925 name: "ORshiftRL", 7926 auxType: auxInt32, 7927 argLen: 2, 7928 asm: arm.AORR, 7929 reg: regInfo{ 7930 inputs: []inputInfo{ 7931 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7932 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7933 }, 7934 outputs: []outputInfo{ 7935 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7936 }, 7937 }, 7938 }, 7939 { 7940 name: "ORshiftRA", 7941 auxType: auxInt32, 7942 argLen: 2, 7943 asm: arm.AORR, 7944 reg: regInfo{ 7945 inputs: []inputInfo{ 7946 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7947 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7948 }, 7949 outputs: []outputInfo{ 7950 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7951 }, 7952 }, 7953 }, 7954 { 7955 name: "XORshiftLL", 7956 auxType: auxInt32, 7957 argLen: 2, 7958 asm: arm.AEOR, 7959 reg: regInfo{ 7960 inputs: []inputInfo{ 7961 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7962 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7963 }, 7964 outputs: []outputInfo{ 7965 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7966 }, 7967 }, 7968 }, 7969 { 7970 name: "XORshiftRL", 7971 auxType: auxInt32, 7972 argLen: 2, 7973 asm: arm.AEOR, 7974 reg: regInfo{ 7975 inputs: []inputInfo{ 7976 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7977 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7978 }, 7979 outputs: []outputInfo{ 7980 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7981 }, 7982 }, 7983 }, 7984 { 7985 name: "XORshiftRA", 7986 auxType: auxInt32, 7987 argLen: 2, 7988 asm: arm.AEOR, 7989 reg: regInfo{ 7990 inputs: []inputInfo{ 7991 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7992 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 7993 }, 7994 outputs: []outputInfo{ 7995 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 7996 }, 7997 }, 7998 }, 7999 { 8000 name: "BICshiftLL", 8001 auxType: auxInt32, 8002 argLen: 2, 8003 asm: arm.ABIC, 8004 reg: regInfo{ 8005 inputs: []inputInfo{ 8006 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8007 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8008 }, 8009 outputs: []outputInfo{ 8010 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8011 }, 8012 }, 8013 }, 8014 { 8015 name: "BICshiftRL", 8016 auxType: auxInt32, 8017 argLen: 2, 8018 asm: arm.ABIC, 8019 reg: regInfo{ 8020 inputs: []inputInfo{ 8021 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8022 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8023 }, 8024 outputs: []outputInfo{ 8025 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8026 }, 8027 }, 8028 }, 8029 { 8030 name: "BICshiftRA", 8031 auxType: auxInt32, 8032 argLen: 2, 8033 asm: arm.ABIC, 8034 reg: regInfo{ 8035 inputs: []inputInfo{ 8036 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8037 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8038 }, 8039 outputs: []outputInfo{ 8040 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8041 }, 8042 }, 8043 }, 8044 { 8045 name: "MVNshiftLL", 8046 auxType: auxInt32, 8047 argLen: 1, 8048 asm: arm.AMVN, 8049 reg: regInfo{ 8050 inputs: []inputInfo{ 8051 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8052 }, 8053 outputs: []outputInfo{ 8054 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8055 }, 8056 }, 8057 }, 8058 { 8059 name: "MVNshiftRL", 8060 auxType: auxInt32, 8061 argLen: 1, 8062 asm: arm.AMVN, 8063 reg: regInfo{ 8064 inputs: []inputInfo{ 8065 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8066 }, 8067 outputs: []outputInfo{ 8068 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8069 }, 8070 }, 8071 }, 8072 { 8073 name: "MVNshiftRA", 8074 auxType: auxInt32, 8075 argLen: 1, 8076 asm: arm.AMVN, 8077 reg: regInfo{ 8078 inputs: []inputInfo{ 8079 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8080 }, 8081 outputs: []outputInfo{ 8082 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8083 }, 8084 }, 8085 }, 8086 { 8087 name: "ADCshiftLL", 8088 auxType: auxInt32, 8089 argLen: 3, 8090 asm: arm.AADC, 8091 reg: regInfo{ 8092 inputs: []inputInfo{ 8093 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8094 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8095 }, 8096 outputs: []outputInfo{ 8097 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8098 }, 8099 }, 8100 }, 8101 { 8102 name: "ADCshiftRL", 8103 auxType: auxInt32, 8104 argLen: 3, 8105 asm: arm.AADC, 8106 reg: regInfo{ 8107 inputs: []inputInfo{ 8108 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8109 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8110 }, 8111 outputs: []outputInfo{ 8112 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8113 }, 8114 }, 8115 }, 8116 { 8117 name: "ADCshiftRA", 8118 auxType: auxInt32, 8119 argLen: 3, 8120 asm: arm.AADC, 8121 reg: regInfo{ 8122 inputs: []inputInfo{ 8123 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8124 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8125 }, 8126 outputs: []outputInfo{ 8127 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8128 }, 8129 }, 8130 }, 8131 { 8132 name: "SBCshiftLL", 8133 auxType: auxInt32, 8134 argLen: 3, 8135 asm: arm.ASBC, 8136 reg: regInfo{ 8137 inputs: []inputInfo{ 8138 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8139 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8140 }, 8141 outputs: []outputInfo{ 8142 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8143 }, 8144 }, 8145 }, 8146 { 8147 name: "SBCshiftRL", 8148 auxType: auxInt32, 8149 argLen: 3, 8150 asm: arm.ASBC, 8151 reg: regInfo{ 8152 inputs: []inputInfo{ 8153 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8154 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8155 }, 8156 outputs: []outputInfo{ 8157 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8158 }, 8159 }, 8160 }, 8161 { 8162 name: "SBCshiftRA", 8163 auxType: auxInt32, 8164 argLen: 3, 8165 asm: arm.ASBC, 8166 reg: regInfo{ 8167 inputs: []inputInfo{ 8168 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8169 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8170 }, 8171 outputs: []outputInfo{ 8172 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8173 }, 8174 }, 8175 }, 8176 { 8177 name: "RSCshiftLL", 8178 auxType: auxInt32, 8179 argLen: 3, 8180 asm: arm.ARSC, 8181 reg: regInfo{ 8182 inputs: []inputInfo{ 8183 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8184 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8185 }, 8186 outputs: []outputInfo{ 8187 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8188 }, 8189 }, 8190 }, 8191 { 8192 name: "RSCshiftRL", 8193 auxType: auxInt32, 8194 argLen: 3, 8195 asm: arm.ARSC, 8196 reg: regInfo{ 8197 inputs: []inputInfo{ 8198 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8199 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8200 }, 8201 outputs: []outputInfo{ 8202 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8203 }, 8204 }, 8205 }, 8206 { 8207 name: "RSCshiftRA", 8208 auxType: auxInt32, 8209 argLen: 3, 8210 asm: arm.ARSC, 8211 reg: regInfo{ 8212 inputs: []inputInfo{ 8213 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8214 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8215 }, 8216 outputs: []outputInfo{ 8217 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8218 }, 8219 }, 8220 }, 8221 { 8222 name: "ADDSshiftLL", 8223 auxType: auxInt32, 8224 argLen: 2, 8225 asm: arm.AADD, 8226 reg: regInfo{ 8227 inputs: []inputInfo{ 8228 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8229 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8230 }, 8231 outputs: []outputInfo{ 8232 {1, 0}, 8233 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8234 }, 8235 }, 8236 }, 8237 { 8238 name: "ADDSshiftRL", 8239 auxType: auxInt32, 8240 argLen: 2, 8241 asm: arm.AADD, 8242 reg: regInfo{ 8243 inputs: []inputInfo{ 8244 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8245 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8246 }, 8247 outputs: []outputInfo{ 8248 {1, 0}, 8249 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8250 }, 8251 }, 8252 }, 8253 { 8254 name: "ADDSshiftRA", 8255 auxType: auxInt32, 8256 argLen: 2, 8257 asm: arm.AADD, 8258 reg: regInfo{ 8259 inputs: []inputInfo{ 8260 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8261 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8262 }, 8263 outputs: []outputInfo{ 8264 {1, 0}, 8265 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8266 }, 8267 }, 8268 }, 8269 { 8270 name: "SUBSshiftLL", 8271 auxType: auxInt32, 8272 argLen: 2, 8273 asm: arm.ASUB, 8274 reg: regInfo{ 8275 inputs: []inputInfo{ 8276 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8277 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8278 }, 8279 outputs: []outputInfo{ 8280 {1, 0}, 8281 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8282 }, 8283 }, 8284 }, 8285 { 8286 name: "SUBSshiftRL", 8287 auxType: auxInt32, 8288 argLen: 2, 8289 asm: arm.ASUB, 8290 reg: regInfo{ 8291 inputs: []inputInfo{ 8292 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8293 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8294 }, 8295 outputs: []outputInfo{ 8296 {1, 0}, 8297 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8298 }, 8299 }, 8300 }, 8301 { 8302 name: "SUBSshiftRA", 8303 auxType: auxInt32, 8304 argLen: 2, 8305 asm: arm.ASUB, 8306 reg: regInfo{ 8307 inputs: []inputInfo{ 8308 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8309 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8310 }, 8311 outputs: []outputInfo{ 8312 {1, 0}, 8313 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8314 }, 8315 }, 8316 }, 8317 { 8318 name: "RSBSshiftLL", 8319 auxType: auxInt32, 8320 argLen: 2, 8321 asm: arm.ARSB, 8322 reg: regInfo{ 8323 inputs: []inputInfo{ 8324 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8325 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8326 }, 8327 outputs: []outputInfo{ 8328 {1, 0}, 8329 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8330 }, 8331 }, 8332 }, 8333 { 8334 name: "RSBSshiftRL", 8335 auxType: auxInt32, 8336 argLen: 2, 8337 asm: arm.ARSB, 8338 reg: regInfo{ 8339 inputs: []inputInfo{ 8340 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8341 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8342 }, 8343 outputs: []outputInfo{ 8344 {1, 0}, 8345 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8346 }, 8347 }, 8348 }, 8349 { 8350 name: "RSBSshiftRA", 8351 auxType: auxInt32, 8352 argLen: 2, 8353 asm: arm.ARSB, 8354 reg: regInfo{ 8355 inputs: []inputInfo{ 8356 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8357 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8358 }, 8359 outputs: []outputInfo{ 8360 {1, 0}, 8361 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8362 }, 8363 }, 8364 }, 8365 { 8366 name: "ADDshiftLLreg", 8367 argLen: 3, 8368 asm: arm.AADD, 8369 reg: regInfo{ 8370 inputs: []inputInfo{ 8371 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8372 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8373 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8374 }, 8375 outputs: []outputInfo{ 8376 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8377 }, 8378 }, 8379 }, 8380 { 8381 name: "ADDshiftRLreg", 8382 argLen: 3, 8383 asm: arm.AADD, 8384 reg: regInfo{ 8385 inputs: []inputInfo{ 8386 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8387 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8388 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8389 }, 8390 outputs: []outputInfo{ 8391 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8392 }, 8393 }, 8394 }, 8395 { 8396 name: "ADDshiftRAreg", 8397 argLen: 3, 8398 asm: arm.AADD, 8399 reg: regInfo{ 8400 inputs: []inputInfo{ 8401 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8402 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8403 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8404 }, 8405 outputs: []outputInfo{ 8406 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8407 }, 8408 }, 8409 }, 8410 { 8411 name: "SUBshiftLLreg", 8412 argLen: 3, 8413 asm: arm.ASUB, 8414 reg: regInfo{ 8415 inputs: []inputInfo{ 8416 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8417 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8418 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8419 }, 8420 outputs: []outputInfo{ 8421 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8422 }, 8423 }, 8424 }, 8425 { 8426 name: "SUBshiftRLreg", 8427 argLen: 3, 8428 asm: arm.ASUB, 8429 reg: regInfo{ 8430 inputs: []inputInfo{ 8431 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8432 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8433 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8434 }, 8435 outputs: []outputInfo{ 8436 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8437 }, 8438 }, 8439 }, 8440 { 8441 name: "SUBshiftRAreg", 8442 argLen: 3, 8443 asm: arm.ASUB, 8444 reg: regInfo{ 8445 inputs: []inputInfo{ 8446 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8447 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8448 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8449 }, 8450 outputs: []outputInfo{ 8451 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8452 }, 8453 }, 8454 }, 8455 { 8456 name: "RSBshiftLLreg", 8457 argLen: 3, 8458 asm: arm.ARSB, 8459 reg: regInfo{ 8460 inputs: []inputInfo{ 8461 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8462 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8463 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8464 }, 8465 outputs: []outputInfo{ 8466 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8467 }, 8468 }, 8469 }, 8470 { 8471 name: "RSBshiftRLreg", 8472 argLen: 3, 8473 asm: arm.ARSB, 8474 reg: regInfo{ 8475 inputs: []inputInfo{ 8476 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8477 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8478 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8479 }, 8480 outputs: []outputInfo{ 8481 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8482 }, 8483 }, 8484 }, 8485 { 8486 name: "RSBshiftRAreg", 8487 argLen: 3, 8488 asm: arm.ARSB, 8489 reg: regInfo{ 8490 inputs: []inputInfo{ 8491 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8492 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8493 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8494 }, 8495 outputs: []outputInfo{ 8496 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8497 }, 8498 }, 8499 }, 8500 { 8501 name: "ANDshiftLLreg", 8502 argLen: 3, 8503 asm: arm.AAND, 8504 reg: regInfo{ 8505 inputs: []inputInfo{ 8506 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8507 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8508 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8509 }, 8510 outputs: []outputInfo{ 8511 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8512 }, 8513 }, 8514 }, 8515 { 8516 name: "ANDshiftRLreg", 8517 argLen: 3, 8518 asm: arm.AAND, 8519 reg: regInfo{ 8520 inputs: []inputInfo{ 8521 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8522 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8523 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8524 }, 8525 outputs: []outputInfo{ 8526 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8527 }, 8528 }, 8529 }, 8530 { 8531 name: "ANDshiftRAreg", 8532 argLen: 3, 8533 asm: arm.AAND, 8534 reg: regInfo{ 8535 inputs: []inputInfo{ 8536 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8537 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8538 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8539 }, 8540 outputs: []outputInfo{ 8541 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8542 }, 8543 }, 8544 }, 8545 { 8546 name: "ORshiftLLreg", 8547 argLen: 3, 8548 asm: arm.AORR, 8549 reg: regInfo{ 8550 inputs: []inputInfo{ 8551 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8552 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8553 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8554 }, 8555 outputs: []outputInfo{ 8556 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8557 }, 8558 }, 8559 }, 8560 { 8561 name: "ORshiftRLreg", 8562 argLen: 3, 8563 asm: arm.AORR, 8564 reg: regInfo{ 8565 inputs: []inputInfo{ 8566 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8567 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8568 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8569 }, 8570 outputs: []outputInfo{ 8571 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8572 }, 8573 }, 8574 }, 8575 { 8576 name: "ORshiftRAreg", 8577 argLen: 3, 8578 asm: arm.AORR, 8579 reg: regInfo{ 8580 inputs: []inputInfo{ 8581 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8582 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8583 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8584 }, 8585 outputs: []outputInfo{ 8586 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8587 }, 8588 }, 8589 }, 8590 { 8591 name: "XORshiftLLreg", 8592 argLen: 3, 8593 asm: arm.AEOR, 8594 reg: regInfo{ 8595 inputs: []inputInfo{ 8596 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8597 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8598 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8599 }, 8600 outputs: []outputInfo{ 8601 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8602 }, 8603 }, 8604 }, 8605 { 8606 name: "XORshiftRLreg", 8607 argLen: 3, 8608 asm: arm.AEOR, 8609 reg: regInfo{ 8610 inputs: []inputInfo{ 8611 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8612 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8613 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8614 }, 8615 outputs: []outputInfo{ 8616 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8617 }, 8618 }, 8619 }, 8620 { 8621 name: "XORshiftRAreg", 8622 argLen: 3, 8623 asm: arm.AEOR, 8624 reg: regInfo{ 8625 inputs: []inputInfo{ 8626 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8627 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8628 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8629 }, 8630 outputs: []outputInfo{ 8631 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8632 }, 8633 }, 8634 }, 8635 { 8636 name: "BICshiftLLreg", 8637 argLen: 3, 8638 asm: arm.ABIC, 8639 reg: regInfo{ 8640 inputs: []inputInfo{ 8641 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8642 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8643 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8644 }, 8645 outputs: []outputInfo{ 8646 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8647 }, 8648 }, 8649 }, 8650 { 8651 name: "BICshiftRLreg", 8652 argLen: 3, 8653 asm: arm.ABIC, 8654 reg: regInfo{ 8655 inputs: []inputInfo{ 8656 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8657 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8658 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8659 }, 8660 outputs: []outputInfo{ 8661 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8662 }, 8663 }, 8664 }, 8665 { 8666 name: "BICshiftRAreg", 8667 argLen: 3, 8668 asm: arm.ABIC, 8669 reg: regInfo{ 8670 inputs: []inputInfo{ 8671 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8672 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8673 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8674 }, 8675 outputs: []outputInfo{ 8676 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8677 }, 8678 }, 8679 }, 8680 { 8681 name: "MVNshiftLLreg", 8682 argLen: 2, 8683 asm: arm.AMVN, 8684 reg: regInfo{ 8685 inputs: []inputInfo{ 8686 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8687 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8688 }, 8689 outputs: []outputInfo{ 8690 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8691 }, 8692 }, 8693 }, 8694 { 8695 name: "MVNshiftRLreg", 8696 argLen: 2, 8697 asm: arm.AMVN, 8698 reg: regInfo{ 8699 inputs: []inputInfo{ 8700 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8701 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8702 }, 8703 outputs: []outputInfo{ 8704 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8705 }, 8706 }, 8707 }, 8708 { 8709 name: "MVNshiftRAreg", 8710 argLen: 2, 8711 asm: arm.AMVN, 8712 reg: regInfo{ 8713 inputs: []inputInfo{ 8714 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8715 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 8716 }, 8717 outputs: []outputInfo{ 8718 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8719 }, 8720 }, 8721 }, 8722 { 8723 name: "ADCshiftLLreg", 8724 argLen: 4, 8725 asm: arm.AADC, 8726 reg: regInfo{ 8727 inputs: []inputInfo{ 8728 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8729 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8730 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8731 }, 8732 outputs: []outputInfo{ 8733 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8734 }, 8735 }, 8736 }, 8737 { 8738 name: "ADCshiftRLreg", 8739 argLen: 4, 8740 asm: arm.AADC, 8741 reg: regInfo{ 8742 inputs: []inputInfo{ 8743 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8744 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8745 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8746 }, 8747 outputs: []outputInfo{ 8748 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8749 }, 8750 }, 8751 }, 8752 { 8753 name: "ADCshiftRAreg", 8754 argLen: 4, 8755 asm: arm.AADC, 8756 reg: regInfo{ 8757 inputs: []inputInfo{ 8758 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8759 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8760 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8761 }, 8762 outputs: []outputInfo{ 8763 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8764 }, 8765 }, 8766 }, 8767 { 8768 name: "SBCshiftLLreg", 8769 argLen: 4, 8770 asm: arm.ASBC, 8771 reg: regInfo{ 8772 inputs: []inputInfo{ 8773 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8774 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8775 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8776 }, 8777 outputs: []outputInfo{ 8778 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8779 }, 8780 }, 8781 }, 8782 { 8783 name: "SBCshiftRLreg", 8784 argLen: 4, 8785 asm: arm.ASBC, 8786 reg: regInfo{ 8787 inputs: []inputInfo{ 8788 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8789 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8790 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8791 }, 8792 outputs: []outputInfo{ 8793 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8794 }, 8795 }, 8796 }, 8797 { 8798 name: "SBCshiftRAreg", 8799 argLen: 4, 8800 asm: arm.ASBC, 8801 reg: regInfo{ 8802 inputs: []inputInfo{ 8803 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8804 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8805 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8806 }, 8807 outputs: []outputInfo{ 8808 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8809 }, 8810 }, 8811 }, 8812 { 8813 name: "RSCshiftLLreg", 8814 argLen: 4, 8815 asm: arm.ARSC, 8816 reg: regInfo{ 8817 inputs: []inputInfo{ 8818 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8819 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8820 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8821 }, 8822 outputs: []outputInfo{ 8823 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8824 }, 8825 }, 8826 }, 8827 { 8828 name: "RSCshiftRLreg", 8829 argLen: 4, 8830 asm: arm.ARSC, 8831 reg: regInfo{ 8832 inputs: []inputInfo{ 8833 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8834 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8835 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8836 }, 8837 outputs: []outputInfo{ 8838 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8839 }, 8840 }, 8841 }, 8842 { 8843 name: "RSCshiftRAreg", 8844 argLen: 4, 8845 asm: arm.ARSC, 8846 reg: regInfo{ 8847 inputs: []inputInfo{ 8848 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8849 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8850 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8851 }, 8852 outputs: []outputInfo{ 8853 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8854 }, 8855 }, 8856 }, 8857 { 8858 name: "ADDSshiftLLreg", 8859 argLen: 3, 8860 asm: arm.AADD, 8861 reg: regInfo{ 8862 inputs: []inputInfo{ 8863 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8864 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8865 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8866 }, 8867 outputs: []outputInfo{ 8868 {1, 0}, 8869 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8870 }, 8871 }, 8872 }, 8873 { 8874 name: "ADDSshiftRLreg", 8875 argLen: 3, 8876 asm: arm.AADD, 8877 reg: regInfo{ 8878 inputs: []inputInfo{ 8879 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8880 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8881 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8882 }, 8883 outputs: []outputInfo{ 8884 {1, 0}, 8885 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8886 }, 8887 }, 8888 }, 8889 { 8890 name: "ADDSshiftRAreg", 8891 argLen: 3, 8892 asm: arm.AADD, 8893 reg: regInfo{ 8894 inputs: []inputInfo{ 8895 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8896 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8897 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8898 }, 8899 outputs: []outputInfo{ 8900 {1, 0}, 8901 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8902 }, 8903 }, 8904 }, 8905 { 8906 name: "SUBSshiftLLreg", 8907 argLen: 3, 8908 asm: arm.ASUB, 8909 reg: regInfo{ 8910 inputs: []inputInfo{ 8911 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8912 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8913 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8914 }, 8915 outputs: []outputInfo{ 8916 {1, 0}, 8917 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8918 }, 8919 }, 8920 }, 8921 { 8922 name: "SUBSshiftRLreg", 8923 argLen: 3, 8924 asm: arm.ASUB, 8925 reg: regInfo{ 8926 inputs: []inputInfo{ 8927 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8928 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8929 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8930 }, 8931 outputs: []outputInfo{ 8932 {1, 0}, 8933 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8934 }, 8935 }, 8936 }, 8937 { 8938 name: "SUBSshiftRAreg", 8939 argLen: 3, 8940 asm: arm.ASUB, 8941 reg: regInfo{ 8942 inputs: []inputInfo{ 8943 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8944 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8945 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8946 }, 8947 outputs: []outputInfo{ 8948 {1, 0}, 8949 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8950 }, 8951 }, 8952 }, 8953 { 8954 name: "RSBSshiftLLreg", 8955 argLen: 3, 8956 asm: arm.ARSB, 8957 reg: regInfo{ 8958 inputs: []inputInfo{ 8959 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8960 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8961 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8962 }, 8963 outputs: []outputInfo{ 8964 {1, 0}, 8965 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8966 }, 8967 }, 8968 }, 8969 { 8970 name: "RSBSshiftRLreg", 8971 argLen: 3, 8972 asm: arm.ARSB, 8973 reg: regInfo{ 8974 inputs: []inputInfo{ 8975 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8976 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8977 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8978 }, 8979 outputs: []outputInfo{ 8980 {1, 0}, 8981 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8982 }, 8983 }, 8984 }, 8985 { 8986 name: "RSBSshiftRAreg", 8987 argLen: 3, 8988 asm: arm.ARSB, 8989 reg: regInfo{ 8990 inputs: []inputInfo{ 8991 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8992 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8993 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8994 }, 8995 outputs: []outputInfo{ 8996 {1, 0}, 8997 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 8998 }, 8999 }, 9000 }, 9001 { 9002 name: "CMP", 9003 argLen: 2, 9004 asm: arm.ACMP, 9005 reg: regInfo{ 9006 inputs: []inputInfo{ 9007 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9008 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9009 }, 9010 }, 9011 }, 9012 { 9013 name: "CMPconst", 9014 auxType: auxInt32, 9015 argLen: 1, 9016 asm: arm.ACMP, 9017 reg: regInfo{ 9018 inputs: []inputInfo{ 9019 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9020 }, 9021 }, 9022 }, 9023 { 9024 name: "CMN", 9025 argLen: 2, 9026 asm: arm.ACMN, 9027 reg: regInfo{ 9028 inputs: []inputInfo{ 9029 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9030 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9031 }, 9032 }, 9033 }, 9034 { 9035 name: "CMNconst", 9036 auxType: auxInt32, 9037 argLen: 1, 9038 asm: arm.ACMN, 9039 reg: regInfo{ 9040 inputs: []inputInfo{ 9041 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9042 }, 9043 }, 9044 }, 9045 { 9046 name: "TST", 9047 argLen: 2, 9048 commutative: true, 9049 asm: arm.ATST, 9050 reg: regInfo{ 9051 inputs: []inputInfo{ 9052 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9053 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9054 }, 9055 }, 9056 }, 9057 { 9058 name: "TSTconst", 9059 auxType: auxInt32, 9060 argLen: 1, 9061 asm: arm.ATST, 9062 reg: regInfo{ 9063 inputs: []inputInfo{ 9064 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9065 }, 9066 }, 9067 }, 9068 { 9069 name: "TEQ", 9070 argLen: 2, 9071 commutative: true, 9072 asm: arm.ATEQ, 9073 reg: regInfo{ 9074 inputs: []inputInfo{ 9075 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9076 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9077 }, 9078 }, 9079 }, 9080 { 9081 name: "TEQconst", 9082 auxType: auxInt32, 9083 argLen: 1, 9084 asm: arm.ATEQ, 9085 reg: regInfo{ 9086 inputs: []inputInfo{ 9087 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9088 }, 9089 }, 9090 }, 9091 { 9092 name: "CMPF", 9093 argLen: 2, 9094 asm: arm.ACMPF, 9095 reg: regInfo{ 9096 inputs: []inputInfo{ 9097 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9098 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9099 }, 9100 }, 9101 }, 9102 { 9103 name: "CMPD", 9104 argLen: 2, 9105 asm: arm.ACMPD, 9106 reg: regInfo{ 9107 inputs: []inputInfo{ 9108 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9109 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9110 }, 9111 }, 9112 }, 9113 { 9114 name: "CMPshiftLL", 9115 auxType: auxInt32, 9116 argLen: 2, 9117 asm: arm.ACMP, 9118 reg: regInfo{ 9119 inputs: []inputInfo{ 9120 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9121 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9122 }, 9123 }, 9124 }, 9125 { 9126 name: "CMPshiftRL", 9127 auxType: auxInt32, 9128 argLen: 2, 9129 asm: arm.ACMP, 9130 reg: regInfo{ 9131 inputs: []inputInfo{ 9132 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9133 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9134 }, 9135 }, 9136 }, 9137 { 9138 name: "CMPshiftRA", 9139 auxType: auxInt32, 9140 argLen: 2, 9141 asm: arm.ACMP, 9142 reg: regInfo{ 9143 inputs: []inputInfo{ 9144 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9145 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9146 }, 9147 }, 9148 }, 9149 { 9150 name: "CMPshiftLLreg", 9151 argLen: 3, 9152 asm: arm.ACMP, 9153 reg: regInfo{ 9154 inputs: []inputInfo{ 9155 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9156 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9157 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9158 }, 9159 }, 9160 }, 9161 { 9162 name: "CMPshiftRLreg", 9163 argLen: 3, 9164 asm: arm.ACMP, 9165 reg: regInfo{ 9166 inputs: []inputInfo{ 9167 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9168 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9169 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9170 }, 9171 }, 9172 }, 9173 { 9174 name: "CMPshiftRAreg", 9175 argLen: 3, 9176 asm: arm.ACMP, 9177 reg: regInfo{ 9178 inputs: []inputInfo{ 9179 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9180 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9181 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9182 }, 9183 }, 9184 }, 9185 { 9186 name: "CMPF0", 9187 argLen: 1, 9188 asm: arm.ACMPF, 9189 reg: regInfo{ 9190 inputs: []inputInfo{ 9191 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9192 }, 9193 }, 9194 }, 9195 { 9196 name: "CMPD0", 9197 argLen: 1, 9198 asm: arm.ACMPD, 9199 reg: regInfo{ 9200 inputs: []inputInfo{ 9201 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9202 }, 9203 }, 9204 }, 9205 { 9206 name: "MOVWconst", 9207 auxType: auxInt32, 9208 argLen: 0, 9209 rematerializeable: true, 9210 asm: arm.AMOVW, 9211 reg: regInfo{ 9212 outputs: []outputInfo{ 9213 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9214 }, 9215 }, 9216 }, 9217 { 9218 name: "MOVFconst", 9219 auxType: auxFloat64, 9220 argLen: 0, 9221 rematerializeable: true, 9222 asm: arm.AMOVF, 9223 reg: regInfo{ 9224 outputs: []outputInfo{ 9225 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9226 }, 9227 }, 9228 }, 9229 { 9230 name: "MOVDconst", 9231 auxType: auxFloat64, 9232 argLen: 0, 9233 rematerializeable: true, 9234 asm: arm.AMOVD, 9235 reg: regInfo{ 9236 outputs: []outputInfo{ 9237 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9238 }, 9239 }, 9240 }, 9241 { 9242 name: "MOVWaddr", 9243 auxType: auxSymOff, 9244 argLen: 1, 9245 rematerializeable: true, 9246 asm: arm.AMOVW, 9247 reg: regInfo{ 9248 inputs: []inputInfo{ 9249 {0, 4294975488}, // SP SB 9250 }, 9251 outputs: []outputInfo{ 9252 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9253 }, 9254 }, 9255 }, 9256 { 9257 name: "MOVBload", 9258 auxType: auxSymOff, 9259 argLen: 2, 9260 asm: arm.AMOVB, 9261 reg: regInfo{ 9262 inputs: []inputInfo{ 9263 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9264 }, 9265 outputs: []outputInfo{ 9266 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9267 }, 9268 }, 9269 }, 9270 { 9271 name: "MOVBUload", 9272 auxType: auxSymOff, 9273 argLen: 2, 9274 asm: arm.AMOVBU, 9275 reg: regInfo{ 9276 inputs: []inputInfo{ 9277 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9278 }, 9279 outputs: []outputInfo{ 9280 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9281 }, 9282 }, 9283 }, 9284 { 9285 name: "MOVHload", 9286 auxType: auxSymOff, 9287 argLen: 2, 9288 asm: arm.AMOVH, 9289 reg: regInfo{ 9290 inputs: []inputInfo{ 9291 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9292 }, 9293 outputs: []outputInfo{ 9294 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9295 }, 9296 }, 9297 }, 9298 { 9299 name: "MOVHUload", 9300 auxType: auxSymOff, 9301 argLen: 2, 9302 asm: arm.AMOVHU, 9303 reg: regInfo{ 9304 inputs: []inputInfo{ 9305 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9306 }, 9307 outputs: []outputInfo{ 9308 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9309 }, 9310 }, 9311 }, 9312 { 9313 name: "MOVWload", 9314 auxType: auxSymOff, 9315 argLen: 2, 9316 asm: arm.AMOVW, 9317 reg: regInfo{ 9318 inputs: []inputInfo{ 9319 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9320 }, 9321 outputs: []outputInfo{ 9322 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9323 }, 9324 }, 9325 }, 9326 { 9327 name: "MOVFload", 9328 auxType: auxSymOff, 9329 argLen: 2, 9330 asm: arm.AMOVF, 9331 reg: regInfo{ 9332 inputs: []inputInfo{ 9333 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9334 }, 9335 outputs: []outputInfo{ 9336 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9337 }, 9338 }, 9339 }, 9340 { 9341 name: "MOVDload", 9342 auxType: auxSymOff, 9343 argLen: 2, 9344 asm: arm.AMOVD, 9345 reg: regInfo{ 9346 inputs: []inputInfo{ 9347 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9348 }, 9349 outputs: []outputInfo{ 9350 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9351 }, 9352 }, 9353 }, 9354 { 9355 name: "MOVBstore", 9356 auxType: auxSymOff, 9357 argLen: 3, 9358 asm: arm.AMOVB, 9359 reg: regInfo{ 9360 inputs: []inputInfo{ 9361 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9362 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9363 }, 9364 }, 9365 }, 9366 { 9367 name: "MOVHstore", 9368 auxType: auxSymOff, 9369 argLen: 3, 9370 asm: arm.AMOVH, 9371 reg: regInfo{ 9372 inputs: []inputInfo{ 9373 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9374 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9375 }, 9376 }, 9377 }, 9378 { 9379 name: "MOVWstore", 9380 auxType: auxSymOff, 9381 argLen: 3, 9382 asm: arm.AMOVW, 9383 reg: regInfo{ 9384 inputs: []inputInfo{ 9385 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9386 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9387 }, 9388 }, 9389 }, 9390 { 9391 name: "MOVFstore", 9392 auxType: auxSymOff, 9393 argLen: 3, 9394 asm: arm.AMOVF, 9395 reg: regInfo{ 9396 inputs: []inputInfo{ 9397 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9398 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9399 }, 9400 }, 9401 }, 9402 { 9403 name: "MOVDstore", 9404 auxType: auxSymOff, 9405 argLen: 3, 9406 asm: arm.AMOVD, 9407 reg: regInfo{ 9408 inputs: []inputInfo{ 9409 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9410 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9411 }, 9412 }, 9413 }, 9414 { 9415 name: "MOVWloadidx", 9416 argLen: 3, 9417 asm: arm.AMOVW, 9418 reg: regInfo{ 9419 inputs: []inputInfo{ 9420 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9421 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9422 }, 9423 outputs: []outputInfo{ 9424 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9425 }, 9426 }, 9427 }, 9428 { 9429 name: "MOVWloadshiftLL", 9430 auxType: auxInt32, 9431 argLen: 3, 9432 asm: arm.AMOVW, 9433 reg: regInfo{ 9434 inputs: []inputInfo{ 9435 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9436 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9437 }, 9438 outputs: []outputInfo{ 9439 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9440 }, 9441 }, 9442 }, 9443 { 9444 name: "MOVWloadshiftRL", 9445 auxType: auxInt32, 9446 argLen: 3, 9447 asm: arm.AMOVW, 9448 reg: regInfo{ 9449 inputs: []inputInfo{ 9450 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9451 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9452 }, 9453 outputs: []outputInfo{ 9454 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9455 }, 9456 }, 9457 }, 9458 { 9459 name: "MOVWloadshiftRA", 9460 auxType: auxInt32, 9461 argLen: 3, 9462 asm: arm.AMOVW, 9463 reg: regInfo{ 9464 inputs: []inputInfo{ 9465 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9466 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9467 }, 9468 outputs: []outputInfo{ 9469 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9470 }, 9471 }, 9472 }, 9473 { 9474 name: "MOVWstoreidx", 9475 argLen: 4, 9476 asm: arm.AMOVW, 9477 reg: regInfo{ 9478 inputs: []inputInfo{ 9479 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9480 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9481 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9482 }, 9483 }, 9484 }, 9485 { 9486 name: "MOVWstoreshiftLL", 9487 auxType: auxInt32, 9488 argLen: 4, 9489 asm: arm.AMOVW, 9490 reg: regInfo{ 9491 inputs: []inputInfo{ 9492 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9493 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9494 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9495 }, 9496 }, 9497 }, 9498 { 9499 name: "MOVWstoreshiftRL", 9500 auxType: auxInt32, 9501 argLen: 4, 9502 asm: arm.AMOVW, 9503 reg: regInfo{ 9504 inputs: []inputInfo{ 9505 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9506 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9507 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9508 }, 9509 }, 9510 }, 9511 { 9512 name: "MOVWstoreshiftRA", 9513 auxType: auxInt32, 9514 argLen: 4, 9515 asm: arm.AMOVW, 9516 reg: regInfo{ 9517 inputs: []inputInfo{ 9518 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9519 {2, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9520 {0, 4294981631}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB 9521 }, 9522 }, 9523 }, 9524 { 9525 name: "MOVBreg", 9526 argLen: 1, 9527 asm: arm.AMOVBS, 9528 reg: regInfo{ 9529 inputs: []inputInfo{ 9530 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9531 }, 9532 outputs: []outputInfo{ 9533 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9534 }, 9535 }, 9536 }, 9537 { 9538 name: "MOVBUreg", 9539 argLen: 1, 9540 asm: arm.AMOVBU, 9541 reg: regInfo{ 9542 inputs: []inputInfo{ 9543 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9544 }, 9545 outputs: []outputInfo{ 9546 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9547 }, 9548 }, 9549 }, 9550 { 9551 name: "MOVHreg", 9552 argLen: 1, 9553 asm: arm.AMOVHS, 9554 reg: regInfo{ 9555 inputs: []inputInfo{ 9556 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9557 }, 9558 outputs: []outputInfo{ 9559 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9560 }, 9561 }, 9562 }, 9563 { 9564 name: "MOVHUreg", 9565 argLen: 1, 9566 asm: arm.AMOVHU, 9567 reg: regInfo{ 9568 inputs: []inputInfo{ 9569 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9570 }, 9571 outputs: []outputInfo{ 9572 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9573 }, 9574 }, 9575 }, 9576 { 9577 name: "MOVWreg", 9578 argLen: 1, 9579 asm: arm.AMOVW, 9580 reg: regInfo{ 9581 inputs: []inputInfo{ 9582 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9583 }, 9584 outputs: []outputInfo{ 9585 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9586 }, 9587 }, 9588 }, 9589 { 9590 name: "MOVWnop", 9591 argLen: 1, 9592 resultInArg0: true, 9593 reg: regInfo{ 9594 inputs: []inputInfo{ 9595 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9596 }, 9597 outputs: []outputInfo{ 9598 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9599 }, 9600 }, 9601 }, 9602 { 9603 name: "MOVWF", 9604 argLen: 1, 9605 asm: arm.AMOVWF, 9606 reg: regInfo{ 9607 inputs: []inputInfo{ 9608 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9609 }, 9610 outputs: []outputInfo{ 9611 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9612 }, 9613 }, 9614 }, 9615 { 9616 name: "MOVWD", 9617 argLen: 1, 9618 asm: arm.AMOVWD, 9619 reg: regInfo{ 9620 inputs: []inputInfo{ 9621 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9622 }, 9623 outputs: []outputInfo{ 9624 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9625 }, 9626 }, 9627 }, 9628 { 9629 name: "MOVWUF", 9630 argLen: 1, 9631 asm: arm.AMOVWF, 9632 reg: regInfo{ 9633 inputs: []inputInfo{ 9634 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9635 }, 9636 outputs: []outputInfo{ 9637 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9638 }, 9639 }, 9640 }, 9641 { 9642 name: "MOVWUD", 9643 argLen: 1, 9644 asm: arm.AMOVWD, 9645 reg: regInfo{ 9646 inputs: []inputInfo{ 9647 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9648 }, 9649 outputs: []outputInfo{ 9650 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9651 }, 9652 }, 9653 }, 9654 { 9655 name: "MOVFW", 9656 argLen: 1, 9657 asm: arm.AMOVFW, 9658 reg: regInfo{ 9659 inputs: []inputInfo{ 9660 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9661 }, 9662 outputs: []outputInfo{ 9663 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9664 }, 9665 }, 9666 }, 9667 { 9668 name: "MOVDW", 9669 argLen: 1, 9670 asm: arm.AMOVDW, 9671 reg: regInfo{ 9672 inputs: []inputInfo{ 9673 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9674 }, 9675 outputs: []outputInfo{ 9676 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9677 }, 9678 }, 9679 }, 9680 { 9681 name: "MOVFWU", 9682 argLen: 1, 9683 asm: arm.AMOVFW, 9684 reg: regInfo{ 9685 inputs: []inputInfo{ 9686 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9687 }, 9688 outputs: []outputInfo{ 9689 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9690 }, 9691 }, 9692 }, 9693 { 9694 name: "MOVDWU", 9695 argLen: 1, 9696 asm: arm.AMOVDW, 9697 reg: regInfo{ 9698 inputs: []inputInfo{ 9699 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9700 }, 9701 outputs: []outputInfo{ 9702 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9703 }, 9704 }, 9705 }, 9706 { 9707 name: "MOVFD", 9708 argLen: 1, 9709 asm: arm.AMOVFD, 9710 reg: regInfo{ 9711 inputs: []inputInfo{ 9712 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9713 }, 9714 outputs: []outputInfo{ 9715 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9716 }, 9717 }, 9718 }, 9719 { 9720 name: "MOVDF", 9721 argLen: 1, 9722 asm: arm.AMOVDF, 9723 reg: regInfo{ 9724 inputs: []inputInfo{ 9725 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9726 }, 9727 outputs: []outputInfo{ 9728 {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9729 }, 9730 }, 9731 }, 9732 { 9733 name: "CMOVWHSconst", 9734 auxType: auxInt32, 9735 argLen: 2, 9736 resultInArg0: true, 9737 asm: arm.AMOVW, 9738 reg: regInfo{ 9739 inputs: []inputInfo{ 9740 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9741 }, 9742 outputs: []outputInfo{ 9743 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9744 }, 9745 }, 9746 }, 9747 { 9748 name: "CMOVWLSconst", 9749 auxType: auxInt32, 9750 argLen: 2, 9751 resultInArg0: true, 9752 asm: arm.AMOVW, 9753 reg: regInfo{ 9754 inputs: []inputInfo{ 9755 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9756 }, 9757 outputs: []outputInfo{ 9758 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9759 }, 9760 }, 9761 }, 9762 { 9763 name: "SRAcond", 9764 argLen: 3, 9765 asm: arm.ASRA, 9766 reg: regInfo{ 9767 inputs: []inputInfo{ 9768 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9769 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9770 }, 9771 outputs: []outputInfo{ 9772 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9773 }, 9774 }, 9775 }, 9776 { 9777 name: "CALLstatic", 9778 auxType: auxSymOff, 9779 argLen: 1, 9780 clobberFlags: true, 9781 reg: regInfo{ 9782 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9783 }, 9784 }, 9785 { 9786 name: "CALLclosure", 9787 auxType: auxInt64, 9788 argLen: 3, 9789 clobberFlags: true, 9790 reg: regInfo{ 9791 inputs: []inputInfo{ 9792 {1, 128}, // R7 9793 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP 9794 }, 9795 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9796 }, 9797 }, 9798 { 9799 name: "CALLdefer", 9800 auxType: auxInt64, 9801 argLen: 1, 9802 clobberFlags: true, 9803 reg: regInfo{ 9804 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9805 }, 9806 }, 9807 { 9808 name: "CALLgo", 9809 auxType: auxInt64, 9810 argLen: 1, 9811 clobberFlags: true, 9812 reg: regInfo{ 9813 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9814 }, 9815 }, 9816 { 9817 name: "CALLinter", 9818 auxType: auxInt64, 9819 argLen: 2, 9820 clobberFlags: true, 9821 reg: regInfo{ 9822 inputs: []inputInfo{ 9823 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9824 }, 9825 clobbers: 4294907903, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 9826 }, 9827 }, 9828 { 9829 name: "LoweredNilCheck", 9830 argLen: 2, 9831 reg: regInfo{ 9832 inputs: []inputInfo{ 9833 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9834 }, 9835 }, 9836 }, 9837 { 9838 name: "Equal", 9839 argLen: 1, 9840 reg: regInfo{ 9841 outputs: []outputInfo{ 9842 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9843 }, 9844 }, 9845 }, 9846 { 9847 name: "NotEqual", 9848 argLen: 1, 9849 reg: regInfo{ 9850 outputs: []outputInfo{ 9851 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9852 }, 9853 }, 9854 }, 9855 { 9856 name: "LessThan", 9857 argLen: 1, 9858 reg: regInfo{ 9859 outputs: []outputInfo{ 9860 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9861 }, 9862 }, 9863 }, 9864 { 9865 name: "LessEqual", 9866 argLen: 1, 9867 reg: regInfo{ 9868 outputs: []outputInfo{ 9869 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9870 }, 9871 }, 9872 }, 9873 { 9874 name: "GreaterThan", 9875 argLen: 1, 9876 reg: regInfo{ 9877 outputs: []outputInfo{ 9878 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9879 }, 9880 }, 9881 }, 9882 { 9883 name: "GreaterEqual", 9884 argLen: 1, 9885 reg: regInfo{ 9886 outputs: []outputInfo{ 9887 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9888 }, 9889 }, 9890 }, 9891 { 9892 name: "LessThanU", 9893 argLen: 1, 9894 reg: regInfo{ 9895 outputs: []outputInfo{ 9896 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9897 }, 9898 }, 9899 }, 9900 { 9901 name: "LessEqualU", 9902 argLen: 1, 9903 reg: regInfo{ 9904 outputs: []outputInfo{ 9905 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9906 }, 9907 }, 9908 }, 9909 { 9910 name: "GreaterThanU", 9911 argLen: 1, 9912 reg: regInfo{ 9913 outputs: []outputInfo{ 9914 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9915 }, 9916 }, 9917 }, 9918 { 9919 name: "GreaterEqualU", 9920 argLen: 1, 9921 reg: regInfo{ 9922 outputs: []outputInfo{ 9923 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9924 }, 9925 }, 9926 }, 9927 { 9928 name: "DUFFZERO", 9929 auxType: auxInt64, 9930 argLen: 3, 9931 reg: regInfo{ 9932 inputs: []inputInfo{ 9933 {0, 2}, // R1 9934 {1, 1}, // R0 9935 }, 9936 clobbers: 2, // R1 9937 }, 9938 }, 9939 { 9940 name: "DUFFCOPY", 9941 auxType: auxInt64, 9942 argLen: 3, 9943 reg: regInfo{ 9944 inputs: []inputInfo{ 9945 {0, 4}, // R2 9946 {1, 2}, // R1 9947 }, 9948 clobbers: 7, // R0 R1 R2 9949 }, 9950 }, 9951 { 9952 name: "LoweredZero", 9953 auxType: auxInt64, 9954 argLen: 4, 9955 clobberFlags: true, 9956 reg: regInfo{ 9957 inputs: []inputInfo{ 9958 {0, 2}, // R1 9959 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9960 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9961 }, 9962 clobbers: 2, // R1 9963 }, 9964 }, 9965 { 9966 name: "LoweredMove", 9967 auxType: auxInt64, 9968 argLen: 4, 9969 clobberFlags: true, 9970 reg: regInfo{ 9971 inputs: []inputInfo{ 9972 {0, 4}, // R2 9973 {1, 2}, // R1 9974 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9975 }, 9976 clobbers: 6, // R1 R2 9977 }, 9978 }, 9979 { 9980 name: "LoweredGetClosurePtr", 9981 argLen: 0, 9982 reg: regInfo{ 9983 outputs: []outputInfo{ 9984 {0, 128}, // R7 9985 }, 9986 }, 9987 }, 9988 { 9989 name: "MOVWconvert", 9990 argLen: 2, 9991 asm: arm.AMOVW, 9992 reg: regInfo{ 9993 inputs: []inputInfo{ 9994 {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 9995 }, 9996 outputs: []outputInfo{ 9997 {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 9998 }, 9999 }, 10000 }, 10001 { 10002 name: "FlagEQ", 10003 argLen: 0, 10004 reg: regInfo{}, 10005 }, 10006 { 10007 name: "FlagLT_ULT", 10008 argLen: 0, 10009 reg: regInfo{}, 10010 }, 10011 { 10012 name: "FlagLT_UGT", 10013 argLen: 0, 10014 reg: regInfo{}, 10015 }, 10016 { 10017 name: "FlagGT_UGT", 10018 argLen: 0, 10019 reg: regInfo{}, 10020 }, 10021 { 10022 name: "FlagGT_ULT", 10023 argLen: 0, 10024 reg: regInfo{}, 10025 }, 10026 { 10027 name: "InvertFlags", 10028 argLen: 1, 10029 reg: regInfo{}, 10030 }, 10031 10032 { 10033 name: "ADD", 10034 argLen: 2, 10035 commutative: true, 10036 asm: arm64.AADD, 10037 reg: regInfo{ 10038 inputs: []inputInfo{ 10039 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10040 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10041 }, 10042 outputs: []outputInfo{ 10043 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10044 }, 10045 }, 10046 }, 10047 { 10048 name: "ADDconst", 10049 auxType: auxInt64, 10050 argLen: 1, 10051 asm: arm64.AADD, 10052 reg: regInfo{ 10053 inputs: []inputInfo{ 10054 {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP 10055 }, 10056 outputs: []outputInfo{ 10057 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10058 }, 10059 }, 10060 }, 10061 { 10062 name: "SUB", 10063 argLen: 2, 10064 asm: arm64.ASUB, 10065 reg: regInfo{ 10066 inputs: []inputInfo{ 10067 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10068 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10069 }, 10070 outputs: []outputInfo{ 10071 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10072 }, 10073 }, 10074 }, 10075 { 10076 name: "SUBconst", 10077 auxType: auxInt64, 10078 argLen: 1, 10079 asm: arm64.ASUB, 10080 reg: regInfo{ 10081 inputs: []inputInfo{ 10082 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10083 }, 10084 outputs: []outputInfo{ 10085 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10086 }, 10087 }, 10088 }, 10089 { 10090 name: "MUL", 10091 argLen: 2, 10092 commutative: true, 10093 asm: arm64.AMUL, 10094 reg: regInfo{ 10095 inputs: []inputInfo{ 10096 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10097 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10098 }, 10099 outputs: []outputInfo{ 10100 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10101 }, 10102 }, 10103 }, 10104 { 10105 name: "MULW", 10106 argLen: 2, 10107 commutative: true, 10108 asm: arm64.AMULW, 10109 reg: regInfo{ 10110 inputs: []inputInfo{ 10111 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10112 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10113 }, 10114 outputs: []outputInfo{ 10115 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10116 }, 10117 }, 10118 }, 10119 { 10120 name: "MULH", 10121 argLen: 2, 10122 commutative: true, 10123 asm: arm64.ASMULH, 10124 reg: regInfo{ 10125 inputs: []inputInfo{ 10126 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10127 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10128 }, 10129 outputs: []outputInfo{ 10130 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10131 }, 10132 }, 10133 }, 10134 { 10135 name: "UMULH", 10136 argLen: 2, 10137 commutative: true, 10138 asm: arm64.AUMULH, 10139 reg: regInfo{ 10140 inputs: []inputInfo{ 10141 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10142 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10143 }, 10144 outputs: []outputInfo{ 10145 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10146 }, 10147 }, 10148 }, 10149 { 10150 name: "MULL", 10151 argLen: 2, 10152 commutative: true, 10153 asm: arm64.ASMULL, 10154 reg: regInfo{ 10155 inputs: []inputInfo{ 10156 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10157 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10158 }, 10159 outputs: []outputInfo{ 10160 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10161 }, 10162 }, 10163 }, 10164 { 10165 name: "UMULL", 10166 argLen: 2, 10167 commutative: true, 10168 asm: arm64.AUMULL, 10169 reg: regInfo{ 10170 inputs: []inputInfo{ 10171 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10172 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10173 }, 10174 outputs: []outputInfo{ 10175 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10176 }, 10177 }, 10178 }, 10179 { 10180 name: "DIV", 10181 argLen: 2, 10182 asm: arm64.ASDIV, 10183 reg: regInfo{ 10184 inputs: []inputInfo{ 10185 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10186 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10187 }, 10188 outputs: []outputInfo{ 10189 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10190 }, 10191 }, 10192 }, 10193 { 10194 name: "UDIV", 10195 argLen: 2, 10196 asm: arm64.AUDIV, 10197 reg: regInfo{ 10198 inputs: []inputInfo{ 10199 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10200 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10201 }, 10202 outputs: []outputInfo{ 10203 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10204 }, 10205 }, 10206 }, 10207 { 10208 name: "DIVW", 10209 argLen: 2, 10210 asm: arm64.ASDIVW, 10211 reg: regInfo{ 10212 inputs: []inputInfo{ 10213 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10214 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10215 }, 10216 outputs: []outputInfo{ 10217 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10218 }, 10219 }, 10220 }, 10221 { 10222 name: "UDIVW", 10223 argLen: 2, 10224 asm: arm64.AUDIVW, 10225 reg: regInfo{ 10226 inputs: []inputInfo{ 10227 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10228 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10229 }, 10230 outputs: []outputInfo{ 10231 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10232 }, 10233 }, 10234 }, 10235 { 10236 name: "MOD", 10237 argLen: 2, 10238 asm: arm64.AREM, 10239 reg: regInfo{ 10240 inputs: []inputInfo{ 10241 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10242 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10243 }, 10244 outputs: []outputInfo{ 10245 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10246 }, 10247 }, 10248 }, 10249 { 10250 name: "UMOD", 10251 argLen: 2, 10252 asm: arm64.AUREM, 10253 reg: regInfo{ 10254 inputs: []inputInfo{ 10255 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10256 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10257 }, 10258 outputs: []outputInfo{ 10259 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10260 }, 10261 }, 10262 }, 10263 { 10264 name: "MODW", 10265 argLen: 2, 10266 asm: arm64.AREMW, 10267 reg: regInfo{ 10268 inputs: []inputInfo{ 10269 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10270 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10271 }, 10272 outputs: []outputInfo{ 10273 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10274 }, 10275 }, 10276 }, 10277 { 10278 name: "UMODW", 10279 argLen: 2, 10280 asm: arm64.AUREMW, 10281 reg: regInfo{ 10282 inputs: []inputInfo{ 10283 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10284 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10285 }, 10286 outputs: []outputInfo{ 10287 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10288 }, 10289 }, 10290 }, 10291 { 10292 name: "FADDS", 10293 argLen: 2, 10294 commutative: true, 10295 asm: arm64.AFADDS, 10296 reg: regInfo{ 10297 inputs: []inputInfo{ 10298 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10299 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10300 }, 10301 outputs: []outputInfo{ 10302 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10303 }, 10304 }, 10305 }, 10306 { 10307 name: "FADDD", 10308 argLen: 2, 10309 commutative: true, 10310 asm: arm64.AFADDD, 10311 reg: regInfo{ 10312 inputs: []inputInfo{ 10313 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10314 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10315 }, 10316 outputs: []outputInfo{ 10317 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10318 }, 10319 }, 10320 }, 10321 { 10322 name: "FSUBS", 10323 argLen: 2, 10324 asm: arm64.AFSUBS, 10325 reg: regInfo{ 10326 inputs: []inputInfo{ 10327 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10328 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10329 }, 10330 outputs: []outputInfo{ 10331 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10332 }, 10333 }, 10334 }, 10335 { 10336 name: "FSUBD", 10337 argLen: 2, 10338 asm: arm64.AFSUBD, 10339 reg: regInfo{ 10340 inputs: []inputInfo{ 10341 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10342 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10343 }, 10344 outputs: []outputInfo{ 10345 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10346 }, 10347 }, 10348 }, 10349 { 10350 name: "FMULS", 10351 argLen: 2, 10352 commutative: true, 10353 asm: arm64.AFMULS, 10354 reg: regInfo{ 10355 inputs: []inputInfo{ 10356 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10357 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10358 }, 10359 outputs: []outputInfo{ 10360 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10361 }, 10362 }, 10363 }, 10364 { 10365 name: "FMULD", 10366 argLen: 2, 10367 commutative: true, 10368 asm: arm64.AFMULD, 10369 reg: regInfo{ 10370 inputs: []inputInfo{ 10371 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10372 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10373 }, 10374 outputs: []outputInfo{ 10375 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10376 }, 10377 }, 10378 }, 10379 { 10380 name: "FDIVS", 10381 argLen: 2, 10382 asm: arm64.AFDIVS, 10383 reg: regInfo{ 10384 inputs: []inputInfo{ 10385 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10386 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10387 }, 10388 outputs: []outputInfo{ 10389 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10390 }, 10391 }, 10392 }, 10393 { 10394 name: "FDIVD", 10395 argLen: 2, 10396 asm: arm64.AFDIVD, 10397 reg: regInfo{ 10398 inputs: []inputInfo{ 10399 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10400 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10401 }, 10402 outputs: []outputInfo{ 10403 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10404 }, 10405 }, 10406 }, 10407 { 10408 name: "AND", 10409 argLen: 2, 10410 commutative: true, 10411 asm: arm64.AAND, 10412 reg: regInfo{ 10413 inputs: []inputInfo{ 10414 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10415 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10416 }, 10417 outputs: []outputInfo{ 10418 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10419 }, 10420 }, 10421 }, 10422 { 10423 name: "ANDconst", 10424 auxType: auxInt64, 10425 argLen: 1, 10426 asm: arm64.AAND, 10427 reg: regInfo{ 10428 inputs: []inputInfo{ 10429 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10430 }, 10431 outputs: []outputInfo{ 10432 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10433 }, 10434 }, 10435 }, 10436 { 10437 name: "OR", 10438 argLen: 2, 10439 commutative: true, 10440 asm: arm64.AORR, 10441 reg: regInfo{ 10442 inputs: []inputInfo{ 10443 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10444 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10445 }, 10446 outputs: []outputInfo{ 10447 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10448 }, 10449 }, 10450 }, 10451 { 10452 name: "ORconst", 10453 auxType: auxInt64, 10454 argLen: 1, 10455 asm: arm64.AORR, 10456 reg: regInfo{ 10457 inputs: []inputInfo{ 10458 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10459 }, 10460 outputs: []outputInfo{ 10461 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10462 }, 10463 }, 10464 }, 10465 { 10466 name: "XOR", 10467 argLen: 2, 10468 commutative: true, 10469 asm: arm64.AEOR, 10470 reg: regInfo{ 10471 inputs: []inputInfo{ 10472 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10473 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10474 }, 10475 outputs: []outputInfo{ 10476 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10477 }, 10478 }, 10479 }, 10480 { 10481 name: "XORconst", 10482 auxType: auxInt64, 10483 argLen: 1, 10484 asm: arm64.AEOR, 10485 reg: regInfo{ 10486 inputs: []inputInfo{ 10487 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10488 }, 10489 outputs: []outputInfo{ 10490 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10491 }, 10492 }, 10493 }, 10494 { 10495 name: "BIC", 10496 argLen: 2, 10497 asm: arm64.ABIC, 10498 reg: regInfo{ 10499 inputs: []inputInfo{ 10500 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10501 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10502 }, 10503 outputs: []outputInfo{ 10504 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10505 }, 10506 }, 10507 }, 10508 { 10509 name: "BICconst", 10510 auxType: auxInt64, 10511 argLen: 1, 10512 asm: arm64.ABIC, 10513 reg: regInfo{ 10514 inputs: []inputInfo{ 10515 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10516 }, 10517 outputs: []outputInfo{ 10518 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10519 }, 10520 }, 10521 }, 10522 { 10523 name: "MVN", 10524 argLen: 1, 10525 asm: arm64.AMVN, 10526 reg: regInfo{ 10527 inputs: []inputInfo{ 10528 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10529 }, 10530 outputs: []outputInfo{ 10531 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10532 }, 10533 }, 10534 }, 10535 { 10536 name: "NEG", 10537 argLen: 1, 10538 asm: arm64.ANEG, 10539 reg: regInfo{ 10540 inputs: []inputInfo{ 10541 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10542 }, 10543 outputs: []outputInfo{ 10544 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10545 }, 10546 }, 10547 }, 10548 { 10549 name: "FNEGS", 10550 argLen: 1, 10551 asm: arm64.AFNEGS, 10552 reg: regInfo{ 10553 inputs: []inputInfo{ 10554 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10555 }, 10556 outputs: []outputInfo{ 10557 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10558 }, 10559 }, 10560 }, 10561 { 10562 name: "FNEGD", 10563 argLen: 1, 10564 asm: arm64.AFNEGD, 10565 reg: regInfo{ 10566 inputs: []inputInfo{ 10567 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10568 }, 10569 outputs: []outputInfo{ 10570 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10571 }, 10572 }, 10573 }, 10574 { 10575 name: "FSQRTD", 10576 argLen: 1, 10577 asm: arm64.AFSQRTD, 10578 reg: regInfo{ 10579 inputs: []inputInfo{ 10580 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10581 }, 10582 outputs: []outputInfo{ 10583 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10584 }, 10585 }, 10586 }, 10587 { 10588 name: "REV", 10589 argLen: 1, 10590 asm: arm64.AREV, 10591 reg: regInfo{ 10592 inputs: []inputInfo{ 10593 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10594 }, 10595 outputs: []outputInfo{ 10596 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10597 }, 10598 }, 10599 }, 10600 { 10601 name: "REVW", 10602 argLen: 1, 10603 asm: arm64.AREVW, 10604 reg: regInfo{ 10605 inputs: []inputInfo{ 10606 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10607 }, 10608 outputs: []outputInfo{ 10609 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10610 }, 10611 }, 10612 }, 10613 { 10614 name: "REV16W", 10615 argLen: 1, 10616 asm: arm64.AREV16W, 10617 reg: regInfo{ 10618 inputs: []inputInfo{ 10619 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10620 }, 10621 outputs: []outputInfo{ 10622 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10623 }, 10624 }, 10625 }, 10626 { 10627 name: "SLL", 10628 argLen: 2, 10629 asm: arm64.ALSL, 10630 reg: regInfo{ 10631 inputs: []inputInfo{ 10632 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10633 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10634 }, 10635 outputs: []outputInfo{ 10636 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10637 }, 10638 }, 10639 }, 10640 { 10641 name: "SLLconst", 10642 auxType: auxInt64, 10643 argLen: 1, 10644 asm: arm64.ALSL, 10645 reg: regInfo{ 10646 inputs: []inputInfo{ 10647 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10648 }, 10649 outputs: []outputInfo{ 10650 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10651 }, 10652 }, 10653 }, 10654 { 10655 name: "SRL", 10656 argLen: 2, 10657 asm: arm64.ALSR, 10658 reg: regInfo{ 10659 inputs: []inputInfo{ 10660 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10661 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10662 }, 10663 outputs: []outputInfo{ 10664 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10665 }, 10666 }, 10667 }, 10668 { 10669 name: "SRLconst", 10670 auxType: auxInt64, 10671 argLen: 1, 10672 asm: arm64.ALSR, 10673 reg: regInfo{ 10674 inputs: []inputInfo{ 10675 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10676 }, 10677 outputs: []outputInfo{ 10678 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10679 }, 10680 }, 10681 }, 10682 { 10683 name: "SRA", 10684 argLen: 2, 10685 asm: arm64.AASR, 10686 reg: regInfo{ 10687 inputs: []inputInfo{ 10688 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10689 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10690 }, 10691 outputs: []outputInfo{ 10692 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10693 }, 10694 }, 10695 }, 10696 { 10697 name: "SRAconst", 10698 auxType: auxInt64, 10699 argLen: 1, 10700 asm: arm64.AASR, 10701 reg: regInfo{ 10702 inputs: []inputInfo{ 10703 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10704 }, 10705 outputs: []outputInfo{ 10706 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10707 }, 10708 }, 10709 }, 10710 { 10711 name: "RORconst", 10712 auxType: auxInt64, 10713 argLen: 1, 10714 asm: arm64.AROR, 10715 reg: regInfo{ 10716 inputs: []inputInfo{ 10717 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10718 }, 10719 outputs: []outputInfo{ 10720 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10721 }, 10722 }, 10723 }, 10724 { 10725 name: "RORWconst", 10726 auxType: auxInt64, 10727 argLen: 1, 10728 asm: arm64.ARORW, 10729 reg: regInfo{ 10730 inputs: []inputInfo{ 10731 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10732 }, 10733 outputs: []outputInfo{ 10734 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10735 }, 10736 }, 10737 }, 10738 { 10739 name: "CMP", 10740 argLen: 2, 10741 asm: arm64.ACMP, 10742 reg: regInfo{ 10743 inputs: []inputInfo{ 10744 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10745 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10746 }, 10747 }, 10748 }, 10749 { 10750 name: "CMPconst", 10751 auxType: auxInt64, 10752 argLen: 1, 10753 asm: arm64.ACMP, 10754 reg: regInfo{ 10755 inputs: []inputInfo{ 10756 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10757 }, 10758 }, 10759 }, 10760 { 10761 name: "CMPW", 10762 argLen: 2, 10763 asm: arm64.ACMPW, 10764 reg: regInfo{ 10765 inputs: []inputInfo{ 10766 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10767 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10768 }, 10769 }, 10770 }, 10771 { 10772 name: "CMPWconst", 10773 auxType: auxInt32, 10774 argLen: 1, 10775 asm: arm64.ACMPW, 10776 reg: regInfo{ 10777 inputs: []inputInfo{ 10778 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10779 }, 10780 }, 10781 }, 10782 { 10783 name: "CMN", 10784 argLen: 2, 10785 asm: arm64.ACMN, 10786 reg: regInfo{ 10787 inputs: []inputInfo{ 10788 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10789 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10790 }, 10791 }, 10792 }, 10793 { 10794 name: "CMNconst", 10795 auxType: auxInt64, 10796 argLen: 1, 10797 asm: arm64.ACMN, 10798 reg: regInfo{ 10799 inputs: []inputInfo{ 10800 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10801 }, 10802 }, 10803 }, 10804 { 10805 name: "CMNW", 10806 argLen: 2, 10807 asm: arm64.ACMNW, 10808 reg: regInfo{ 10809 inputs: []inputInfo{ 10810 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10811 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10812 }, 10813 }, 10814 }, 10815 { 10816 name: "CMNWconst", 10817 auxType: auxInt32, 10818 argLen: 1, 10819 asm: arm64.ACMNW, 10820 reg: regInfo{ 10821 inputs: []inputInfo{ 10822 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10823 }, 10824 }, 10825 }, 10826 { 10827 name: "FCMPS", 10828 argLen: 2, 10829 asm: arm64.AFCMPS, 10830 reg: regInfo{ 10831 inputs: []inputInfo{ 10832 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10833 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10834 }, 10835 }, 10836 }, 10837 { 10838 name: "FCMPD", 10839 argLen: 2, 10840 asm: arm64.AFCMPD, 10841 reg: regInfo{ 10842 inputs: []inputInfo{ 10843 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10844 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 10845 }, 10846 }, 10847 }, 10848 { 10849 name: "ADDshiftLL", 10850 auxType: auxInt64, 10851 argLen: 2, 10852 asm: arm64.AADD, 10853 reg: regInfo{ 10854 inputs: []inputInfo{ 10855 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10856 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10857 }, 10858 outputs: []outputInfo{ 10859 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10860 }, 10861 }, 10862 }, 10863 { 10864 name: "ADDshiftRL", 10865 auxType: auxInt64, 10866 argLen: 2, 10867 asm: arm64.AADD, 10868 reg: regInfo{ 10869 inputs: []inputInfo{ 10870 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10871 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10872 }, 10873 outputs: []outputInfo{ 10874 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10875 }, 10876 }, 10877 }, 10878 { 10879 name: "ADDshiftRA", 10880 auxType: auxInt64, 10881 argLen: 2, 10882 asm: arm64.AADD, 10883 reg: regInfo{ 10884 inputs: []inputInfo{ 10885 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10886 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10887 }, 10888 outputs: []outputInfo{ 10889 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10890 }, 10891 }, 10892 }, 10893 { 10894 name: "SUBshiftLL", 10895 auxType: auxInt64, 10896 argLen: 2, 10897 asm: arm64.ASUB, 10898 reg: regInfo{ 10899 inputs: []inputInfo{ 10900 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10901 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10902 }, 10903 outputs: []outputInfo{ 10904 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10905 }, 10906 }, 10907 }, 10908 { 10909 name: "SUBshiftRL", 10910 auxType: auxInt64, 10911 argLen: 2, 10912 asm: arm64.ASUB, 10913 reg: regInfo{ 10914 inputs: []inputInfo{ 10915 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10916 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10917 }, 10918 outputs: []outputInfo{ 10919 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10920 }, 10921 }, 10922 }, 10923 { 10924 name: "SUBshiftRA", 10925 auxType: auxInt64, 10926 argLen: 2, 10927 asm: arm64.ASUB, 10928 reg: regInfo{ 10929 inputs: []inputInfo{ 10930 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10931 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10932 }, 10933 outputs: []outputInfo{ 10934 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10935 }, 10936 }, 10937 }, 10938 { 10939 name: "ANDshiftLL", 10940 auxType: auxInt64, 10941 argLen: 2, 10942 asm: arm64.AAND, 10943 reg: regInfo{ 10944 inputs: []inputInfo{ 10945 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10946 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10947 }, 10948 outputs: []outputInfo{ 10949 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10950 }, 10951 }, 10952 }, 10953 { 10954 name: "ANDshiftRL", 10955 auxType: auxInt64, 10956 argLen: 2, 10957 asm: arm64.AAND, 10958 reg: regInfo{ 10959 inputs: []inputInfo{ 10960 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10961 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10962 }, 10963 outputs: []outputInfo{ 10964 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10965 }, 10966 }, 10967 }, 10968 { 10969 name: "ANDshiftRA", 10970 auxType: auxInt64, 10971 argLen: 2, 10972 asm: arm64.AAND, 10973 reg: regInfo{ 10974 inputs: []inputInfo{ 10975 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10976 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10977 }, 10978 outputs: []outputInfo{ 10979 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10980 }, 10981 }, 10982 }, 10983 { 10984 name: "ORshiftLL", 10985 auxType: auxInt64, 10986 argLen: 2, 10987 asm: arm64.AORR, 10988 reg: regInfo{ 10989 inputs: []inputInfo{ 10990 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10991 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 10992 }, 10993 outputs: []outputInfo{ 10994 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 10995 }, 10996 }, 10997 }, 10998 { 10999 name: "ORshiftRL", 11000 auxType: auxInt64, 11001 argLen: 2, 11002 asm: arm64.AORR, 11003 reg: regInfo{ 11004 inputs: []inputInfo{ 11005 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11006 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11007 }, 11008 outputs: []outputInfo{ 11009 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11010 }, 11011 }, 11012 }, 11013 { 11014 name: "ORshiftRA", 11015 auxType: auxInt64, 11016 argLen: 2, 11017 asm: arm64.AORR, 11018 reg: regInfo{ 11019 inputs: []inputInfo{ 11020 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11021 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11022 }, 11023 outputs: []outputInfo{ 11024 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11025 }, 11026 }, 11027 }, 11028 { 11029 name: "XORshiftLL", 11030 auxType: auxInt64, 11031 argLen: 2, 11032 asm: arm64.AEOR, 11033 reg: regInfo{ 11034 inputs: []inputInfo{ 11035 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11036 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11037 }, 11038 outputs: []outputInfo{ 11039 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11040 }, 11041 }, 11042 }, 11043 { 11044 name: "XORshiftRL", 11045 auxType: auxInt64, 11046 argLen: 2, 11047 asm: arm64.AEOR, 11048 reg: regInfo{ 11049 inputs: []inputInfo{ 11050 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11051 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11052 }, 11053 outputs: []outputInfo{ 11054 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11055 }, 11056 }, 11057 }, 11058 { 11059 name: "XORshiftRA", 11060 auxType: auxInt64, 11061 argLen: 2, 11062 asm: arm64.AEOR, 11063 reg: regInfo{ 11064 inputs: []inputInfo{ 11065 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11066 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11067 }, 11068 outputs: []outputInfo{ 11069 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11070 }, 11071 }, 11072 }, 11073 { 11074 name: "BICshiftLL", 11075 auxType: auxInt64, 11076 argLen: 2, 11077 asm: arm64.ABIC, 11078 reg: regInfo{ 11079 inputs: []inputInfo{ 11080 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11081 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11082 }, 11083 outputs: []outputInfo{ 11084 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11085 }, 11086 }, 11087 }, 11088 { 11089 name: "BICshiftRL", 11090 auxType: auxInt64, 11091 argLen: 2, 11092 asm: arm64.ABIC, 11093 reg: regInfo{ 11094 inputs: []inputInfo{ 11095 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11096 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11097 }, 11098 outputs: []outputInfo{ 11099 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11100 }, 11101 }, 11102 }, 11103 { 11104 name: "BICshiftRA", 11105 auxType: auxInt64, 11106 argLen: 2, 11107 asm: arm64.ABIC, 11108 reg: regInfo{ 11109 inputs: []inputInfo{ 11110 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11111 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11112 }, 11113 outputs: []outputInfo{ 11114 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11115 }, 11116 }, 11117 }, 11118 { 11119 name: "CMPshiftLL", 11120 auxType: auxInt64, 11121 argLen: 2, 11122 asm: arm64.ACMP, 11123 reg: regInfo{ 11124 inputs: []inputInfo{ 11125 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11126 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11127 }, 11128 }, 11129 }, 11130 { 11131 name: "CMPshiftRL", 11132 auxType: auxInt64, 11133 argLen: 2, 11134 asm: arm64.ACMP, 11135 reg: regInfo{ 11136 inputs: []inputInfo{ 11137 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11138 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11139 }, 11140 }, 11141 }, 11142 { 11143 name: "CMPshiftRA", 11144 auxType: auxInt64, 11145 argLen: 2, 11146 asm: arm64.ACMP, 11147 reg: regInfo{ 11148 inputs: []inputInfo{ 11149 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11150 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11151 }, 11152 }, 11153 }, 11154 { 11155 name: "MOVDconst", 11156 auxType: auxInt64, 11157 argLen: 0, 11158 rematerializeable: true, 11159 asm: arm64.AMOVD, 11160 reg: regInfo{ 11161 outputs: []outputInfo{ 11162 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11163 }, 11164 }, 11165 }, 11166 { 11167 name: "FMOVSconst", 11168 auxType: auxFloat64, 11169 argLen: 0, 11170 rematerializeable: true, 11171 asm: arm64.AFMOVS, 11172 reg: regInfo{ 11173 outputs: []outputInfo{ 11174 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11175 }, 11176 }, 11177 }, 11178 { 11179 name: "FMOVDconst", 11180 auxType: auxFloat64, 11181 argLen: 0, 11182 rematerializeable: true, 11183 asm: arm64.AFMOVD, 11184 reg: regInfo{ 11185 outputs: []outputInfo{ 11186 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11187 }, 11188 }, 11189 }, 11190 { 11191 name: "MOVDaddr", 11192 auxType: auxSymOff, 11193 argLen: 1, 11194 rematerializeable: true, 11195 asm: arm64.AMOVD, 11196 reg: regInfo{ 11197 inputs: []inputInfo{ 11198 {0, 4611686018964258816}, // SP SB 11199 }, 11200 outputs: []outputInfo{ 11201 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11202 }, 11203 }, 11204 }, 11205 { 11206 name: "MOVBload", 11207 auxType: auxSymOff, 11208 argLen: 2, 11209 asm: arm64.AMOVB, 11210 reg: regInfo{ 11211 inputs: []inputInfo{ 11212 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11213 }, 11214 outputs: []outputInfo{ 11215 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11216 }, 11217 }, 11218 }, 11219 { 11220 name: "MOVBUload", 11221 auxType: auxSymOff, 11222 argLen: 2, 11223 asm: arm64.AMOVBU, 11224 reg: regInfo{ 11225 inputs: []inputInfo{ 11226 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11227 }, 11228 outputs: []outputInfo{ 11229 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11230 }, 11231 }, 11232 }, 11233 { 11234 name: "MOVHload", 11235 auxType: auxSymOff, 11236 argLen: 2, 11237 asm: arm64.AMOVH, 11238 reg: regInfo{ 11239 inputs: []inputInfo{ 11240 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11241 }, 11242 outputs: []outputInfo{ 11243 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11244 }, 11245 }, 11246 }, 11247 { 11248 name: "MOVHUload", 11249 auxType: auxSymOff, 11250 argLen: 2, 11251 asm: arm64.AMOVHU, 11252 reg: regInfo{ 11253 inputs: []inputInfo{ 11254 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11255 }, 11256 outputs: []outputInfo{ 11257 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11258 }, 11259 }, 11260 }, 11261 { 11262 name: "MOVWload", 11263 auxType: auxSymOff, 11264 argLen: 2, 11265 asm: arm64.AMOVW, 11266 reg: regInfo{ 11267 inputs: []inputInfo{ 11268 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11269 }, 11270 outputs: []outputInfo{ 11271 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11272 }, 11273 }, 11274 }, 11275 { 11276 name: "MOVWUload", 11277 auxType: auxSymOff, 11278 argLen: 2, 11279 asm: arm64.AMOVWU, 11280 reg: regInfo{ 11281 inputs: []inputInfo{ 11282 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11283 }, 11284 outputs: []outputInfo{ 11285 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11286 }, 11287 }, 11288 }, 11289 { 11290 name: "MOVDload", 11291 auxType: auxSymOff, 11292 argLen: 2, 11293 asm: arm64.AMOVD, 11294 reg: regInfo{ 11295 inputs: []inputInfo{ 11296 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11297 }, 11298 outputs: []outputInfo{ 11299 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11300 }, 11301 }, 11302 }, 11303 { 11304 name: "FMOVSload", 11305 auxType: auxSymOff, 11306 argLen: 2, 11307 asm: arm64.AFMOVS, 11308 reg: regInfo{ 11309 inputs: []inputInfo{ 11310 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11311 }, 11312 outputs: []outputInfo{ 11313 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11314 }, 11315 }, 11316 }, 11317 { 11318 name: "FMOVDload", 11319 auxType: auxSymOff, 11320 argLen: 2, 11321 asm: arm64.AFMOVD, 11322 reg: regInfo{ 11323 inputs: []inputInfo{ 11324 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11325 }, 11326 outputs: []outputInfo{ 11327 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11328 }, 11329 }, 11330 }, 11331 { 11332 name: "MOVBstore", 11333 auxType: auxSymOff, 11334 argLen: 3, 11335 asm: arm64.AMOVB, 11336 reg: regInfo{ 11337 inputs: []inputInfo{ 11338 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11339 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11340 }, 11341 }, 11342 }, 11343 { 11344 name: "MOVHstore", 11345 auxType: auxSymOff, 11346 argLen: 3, 11347 asm: arm64.AMOVH, 11348 reg: regInfo{ 11349 inputs: []inputInfo{ 11350 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11351 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11352 }, 11353 }, 11354 }, 11355 { 11356 name: "MOVWstore", 11357 auxType: auxSymOff, 11358 argLen: 3, 11359 asm: arm64.AMOVW, 11360 reg: regInfo{ 11361 inputs: []inputInfo{ 11362 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11363 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11364 }, 11365 }, 11366 }, 11367 { 11368 name: "MOVDstore", 11369 auxType: auxSymOff, 11370 argLen: 3, 11371 asm: arm64.AMOVD, 11372 reg: regInfo{ 11373 inputs: []inputInfo{ 11374 {1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11375 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11376 }, 11377 }, 11378 }, 11379 { 11380 name: "FMOVSstore", 11381 auxType: auxSymOff, 11382 argLen: 3, 11383 asm: arm64.AFMOVS, 11384 reg: regInfo{ 11385 inputs: []inputInfo{ 11386 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11387 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11388 }, 11389 }, 11390 }, 11391 { 11392 name: "FMOVDstore", 11393 auxType: auxSymOff, 11394 argLen: 3, 11395 asm: arm64.AFMOVD, 11396 reg: regInfo{ 11397 inputs: []inputInfo{ 11398 {1, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11399 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11400 }, 11401 }, 11402 }, 11403 { 11404 name: "MOVBstorezero", 11405 auxType: auxSymOff, 11406 argLen: 2, 11407 asm: arm64.AMOVB, 11408 reg: regInfo{ 11409 inputs: []inputInfo{ 11410 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11411 }, 11412 }, 11413 }, 11414 { 11415 name: "MOVHstorezero", 11416 auxType: auxSymOff, 11417 argLen: 2, 11418 asm: arm64.AMOVH, 11419 reg: regInfo{ 11420 inputs: []inputInfo{ 11421 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11422 }, 11423 }, 11424 }, 11425 { 11426 name: "MOVWstorezero", 11427 auxType: auxSymOff, 11428 argLen: 2, 11429 asm: arm64.AMOVW, 11430 reg: regInfo{ 11431 inputs: []inputInfo{ 11432 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11433 }, 11434 }, 11435 }, 11436 { 11437 name: "MOVDstorezero", 11438 auxType: auxSymOff, 11439 argLen: 2, 11440 asm: arm64.AMOVD, 11441 reg: regInfo{ 11442 inputs: []inputInfo{ 11443 {0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB 11444 }, 11445 }, 11446 }, 11447 { 11448 name: "MOVBreg", 11449 argLen: 1, 11450 asm: arm64.AMOVB, 11451 reg: regInfo{ 11452 inputs: []inputInfo{ 11453 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11454 }, 11455 outputs: []outputInfo{ 11456 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11457 }, 11458 }, 11459 }, 11460 { 11461 name: "MOVBUreg", 11462 argLen: 1, 11463 asm: arm64.AMOVBU, 11464 reg: regInfo{ 11465 inputs: []inputInfo{ 11466 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11467 }, 11468 outputs: []outputInfo{ 11469 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11470 }, 11471 }, 11472 }, 11473 { 11474 name: "MOVHreg", 11475 argLen: 1, 11476 asm: arm64.AMOVH, 11477 reg: regInfo{ 11478 inputs: []inputInfo{ 11479 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11480 }, 11481 outputs: []outputInfo{ 11482 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11483 }, 11484 }, 11485 }, 11486 { 11487 name: "MOVHUreg", 11488 argLen: 1, 11489 asm: arm64.AMOVHU, 11490 reg: regInfo{ 11491 inputs: []inputInfo{ 11492 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11493 }, 11494 outputs: []outputInfo{ 11495 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11496 }, 11497 }, 11498 }, 11499 { 11500 name: "MOVWreg", 11501 argLen: 1, 11502 asm: arm64.AMOVW, 11503 reg: regInfo{ 11504 inputs: []inputInfo{ 11505 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11506 }, 11507 outputs: []outputInfo{ 11508 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11509 }, 11510 }, 11511 }, 11512 { 11513 name: "MOVWUreg", 11514 argLen: 1, 11515 asm: arm64.AMOVWU, 11516 reg: regInfo{ 11517 inputs: []inputInfo{ 11518 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11519 }, 11520 outputs: []outputInfo{ 11521 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11522 }, 11523 }, 11524 }, 11525 { 11526 name: "MOVDreg", 11527 argLen: 1, 11528 asm: arm64.AMOVD, 11529 reg: regInfo{ 11530 inputs: []inputInfo{ 11531 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11532 }, 11533 outputs: []outputInfo{ 11534 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11535 }, 11536 }, 11537 }, 11538 { 11539 name: "MOVDnop", 11540 argLen: 1, 11541 resultInArg0: true, 11542 reg: regInfo{ 11543 inputs: []inputInfo{ 11544 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11545 }, 11546 outputs: []outputInfo{ 11547 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11548 }, 11549 }, 11550 }, 11551 { 11552 name: "SCVTFWS", 11553 argLen: 1, 11554 asm: arm64.ASCVTFWS, 11555 reg: regInfo{ 11556 inputs: []inputInfo{ 11557 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11558 }, 11559 outputs: []outputInfo{ 11560 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11561 }, 11562 }, 11563 }, 11564 { 11565 name: "SCVTFWD", 11566 argLen: 1, 11567 asm: arm64.ASCVTFWD, 11568 reg: regInfo{ 11569 inputs: []inputInfo{ 11570 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11571 }, 11572 outputs: []outputInfo{ 11573 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11574 }, 11575 }, 11576 }, 11577 { 11578 name: "UCVTFWS", 11579 argLen: 1, 11580 asm: arm64.AUCVTFWS, 11581 reg: regInfo{ 11582 inputs: []inputInfo{ 11583 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11584 }, 11585 outputs: []outputInfo{ 11586 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11587 }, 11588 }, 11589 }, 11590 { 11591 name: "UCVTFWD", 11592 argLen: 1, 11593 asm: arm64.AUCVTFWD, 11594 reg: regInfo{ 11595 inputs: []inputInfo{ 11596 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11597 }, 11598 outputs: []outputInfo{ 11599 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11600 }, 11601 }, 11602 }, 11603 { 11604 name: "SCVTFS", 11605 argLen: 1, 11606 asm: arm64.ASCVTFS, 11607 reg: regInfo{ 11608 inputs: []inputInfo{ 11609 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11610 }, 11611 outputs: []outputInfo{ 11612 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11613 }, 11614 }, 11615 }, 11616 { 11617 name: "SCVTFD", 11618 argLen: 1, 11619 asm: arm64.ASCVTFD, 11620 reg: regInfo{ 11621 inputs: []inputInfo{ 11622 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11623 }, 11624 outputs: []outputInfo{ 11625 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11626 }, 11627 }, 11628 }, 11629 { 11630 name: "UCVTFS", 11631 argLen: 1, 11632 asm: arm64.AUCVTFS, 11633 reg: regInfo{ 11634 inputs: []inputInfo{ 11635 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11636 }, 11637 outputs: []outputInfo{ 11638 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11639 }, 11640 }, 11641 }, 11642 { 11643 name: "UCVTFD", 11644 argLen: 1, 11645 asm: arm64.AUCVTFD, 11646 reg: regInfo{ 11647 inputs: []inputInfo{ 11648 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11649 }, 11650 outputs: []outputInfo{ 11651 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11652 }, 11653 }, 11654 }, 11655 { 11656 name: "FCVTZSSW", 11657 argLen: 1, 11658 asm: arm64.AFCVTZSSW, 11659 reg: regInfo{ 11660 inputs: []inputInfo{ 11661 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11662 }, 11663 outputs: []outputInfo{ 11664 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11665 }, 11666 }, 11667 }, 11668 { 11669 name: "FCVTZSDW", 11670 argLen: 1, 11671 asm: arm64.AFCVTZSDW, 11672 reg: regInfo{ 11673 inputs: []inputInfo{ 11674 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11675 }, 11676 outputs: []outputInfo{ 11677 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11678 }, 11679 }, 11680 }, 11681 { 11682 name: "FCVTZUSW", 11683 argLen: 1, 11684 asm: arm64.AFCVTZUSW, 11685 reg: regInfo{ 11686 inputs: []inputInfo{ 11687 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11688 }, 11689 outputs: []outputInfo{ 11690 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11691 }, 11692 }, 11693 }, 11694 { 11695 name: "FCVTZUDW", 11696 argLen: 1, 11697 asm: arm64.AFCVTZUDW, 11698 reg: regInfo{ 11699 inputs: []inputInfo{ 11700 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11701 }, 11702 outputs: []outputInfo{ 11703 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11704 }, 11705 }, 11706 }, 11707 { 11708 name: "FCVTZSS", 11709 argLen: 1, 11710 asm: arm64.AFCVTZSS, 11711 reg: regInfo{ 11712 inputs: []inputInfo{ 11713 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11714 }, 11715 outputs: []outputInfo{ 11716 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11717 }, 11718 }, 11719 }, 11720 { 11721 name: "FCVTZSD", 11722 argLen: 1, 11723 asm: arm64.AFCVTZSD, 11724 reg: regInfo{ 11725 inputs: []inputInfo{ 11726 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11727 }, 11728 outputs: []outputInfo{ 11729 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11730 }, 11731 }, 11732 }, 11733 { 11734 name: "FCVTZUS", 11735 argLen: 1, 11736 asm: arm64.AFCVTZUS, 11737 reg: regInfo{ 11738 inputs: []inputInfo{ 11739 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11740 }, 11741 outputs: []outputInfo{ 11742 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11743 }, 11744 }, 11745 }, 11746 { 11747 name: "FCVTZUD", 11748 argLen: 1, 11749 asm: arm64.AFCVTZUD, 11750 reg: regInfo{ 11751 inputs: []inputInfo{ 11752 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11753 }, 11754 outputs: []outputInfo{ 11755 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11756 }, 11757 }, 11758 }, 11759 { 11760 name: "FCVTSD", 11761 argLen: 1, 11762 asm: arm64.AFCVTSD, 11763 reg: regInfo{ 11764 inputs: []inputInfo{ 11765 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11766 }, 11767 outputs: []outputInfo{ 11768 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11769 }, 11770 }, 11771 }, 11772 { 11773 name: "FCVTDS", 11774 argLen: 1, 11775 asm: arm64.AFCVTDS, 11776 reg: regInfo{ 11777 inputs: []inputInfo{ 11778 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11779 }, 11780 outputs: []outputInfo{ 11781 {0, 288230375077969920}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11782 }, 11783 }, 11784 }, 11785 { 11786 name: "CSELULT", 11787 argLen: 3, 11788 asm: arm64.ACSEL, 11789 reg: regInfo{ 11790 inputs: []inputInfo{ 11791 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11792 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11793 }, 11794 outputs: []outputInfo{ 11795 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11796 }, 11797 }, 11798 }, 11799 { 11800 name: "CSELULT0", 11801 argLen: 2, 11802 asm: arm64.ACSEL, 11803 reg: regInfo{ 11804 inputs: []inputInfo{ 11805 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11806 }, 11807 outputs: []outputInfo{ 11808 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11809 }, 11810 }, 11811 }, 11812 { 11813 name: "CALLstatic", 11814 auxType: auxSymOff, 11815 argLen: 1, 11816 clobberFlags: true, 11817 reg: regInfo{ 11818 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11819 }, 11820 }, 11821 { 11822 name: "CALLclosure", 11823 auxType: auxInt64, 11824 argLen: 3, 11825 clobberFlags: true, 11826 reg: regInfo{ 11827 inputs: []inputInfo{ 11828 {1, 67108864}, // R26 11829 {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 SP 11830 }, 11831 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11832 }, 11833 }, 11834 { 11835 name: "CALLdefer", 11836 auxType: auxInt64, 11837 argLen: 1, 11838 clobberFlags: true, 11839 reg: regInfo{ 11840 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11841 }, 11842 }, 11843 { 11844 name: "CALLgo", 11845 auxType: auxInt64, 11846 argLen: 1, 11847 clobberFlags: true, 11848 reg: regInfo{ 11849 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11850 }, 11851 }, 11852 { 11853 name: "CALLinter", 11854 auxType: auxInt64, 11855 argLen: 2, 11856 clobberFlags: true, 11857 reg: regInfo{ 11858 inputs: []inputInfo{ 11859 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11860 }, 11861 clobbers: 288230375346143231, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 11862 }, 11863 }, 11864 { 11865 name: "LoweredNilCheck", 11866 argLen: 2, 11867 reg: regInfo{ 11868 inputs: []inputInfo{ 11869 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 11870 }, 11871 }, 11872 }, 11873 { 11874 name: "Equal", 11875 argLen: 1, 11876 reg: regInfo{ 11877 outputs: []outputInfo{ 11878 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11879 }, 11880 }, 11881 }, 11882 { 11883 name: "NotEqual", 11884 argLen: 1, 11885 reg: regInfo{ 11886 outputs: []outputInfo{ 11887 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11888 }, 11889 }, 11890 }, 11891 { 11892 name: "LessThan", 11893 argLen: 1, 11894 reg: regInfo{ 11895 outputs: []outputInfo{ 11896 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11897 }, 11898 }, 11899 }, 11900 { 11901 name: "LessEqual", 11902 argLen: 1, 11903 reg: regInfo{ 11904 outputs: []outputInfo{ 11905 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11906 }, 11907 }, 11908 }, 11909 { 11910 name: "GreaterThan", 11911 argLen: 1, 11912 reg: regInfo{ 11913 outputs: []outputInfo{ 11914 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11915 }, 11916 }, 11917 }, 11918 { 11919 name: "GreaterEqual", 11920 argLen: 1, 11921 reg: regInfo{ 11922 outputs: []outputInfo{ 11923 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11924 }, 11925 }, 11926 }, 11927 { 11928 name: "LessThanU", 11929 argLen: 1, 11930 reg: regInfo{ 11931 outputs: []outputInfo{ 11932 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11933 }, 11934 }, 11935 }, 11936 { 11937 name: "LessEqualU", 11938 argLen: 1, 11939 reg: regInfo{ 11940 outputs: []outputInfo{ 11941 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11942 }, 11943 }, 11944 }, 11945 { 11946 name: "GreaterThanU", 11947 argLen: 1, 11948 reg: regInfo{ 11949 outputs: []outputInfo{ 11950 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11951 }, 11952 }, 11953 }, 11954 { 11955 name: "GreaterEqualU", 11956 argLen: 1, 11957 reg: regInfo{ 11958 outputs: []outputInfo{ 11959 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11960 }, 11961 }, 11962 }, 11963 { 11964 name: "DUFFZERO", 11965 auxType: auxInt64, 11966 argLen: 2, 11967 reg: regInfo{ 11968 inputs: []inputInfo{ 11969 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11970 }, 11971 clobbers: 65536, // R16 11972 }, 11973 }, 11974 { 11975 name: "LoweredZero", 11976 argLen: 3, 11977 clobberFlags: true, 11978 reg: regInfo{ 11979 inputs: []inputInfo{ 11980 {0, 65536}, // R16 11981 {1, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11982 }, 11983 clobbers: 65536, // R16 11984 }, 11985 }, 11986 { 11987 name: "LoweredMove", 11988 argLen: 4, 11989 clobberFlags: true, 11990 reg: regInfo{ 11991 inputs: []inputInfo{ 11992 {0, 131072}, // R17 11993 {1, 65536}, // R16 11994 {2, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 11995 }, 11996 clobbers: 196608, // R16 R17 11997 }, 11998 }, 11999 { 12000 name: "LoweredGetClosurePtr", 12001 argLen: 0, 12002 reg: regInfo{ 12003 outputs: []outputInfo{ 12004 {0, 67108864}, // R26 12005 }, 12006 }, 12007 }, 12008 { 12009 name: "MOVDconvert", 12010 argLen: 2, 12011 asm: arm64.AMOVD, 12012 reg: regInfo{ 12013 inputs: []inputInfo{ 12014 {0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g 12015 }, 12016 outputs: []outputInfo{ 12017 {0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 12018 }, 12019 }, 12020 }, 12021 { 12022 name: "FlagEQ", 12023 argLen: 0, 12024 reg: regInfo{}, 12025 }, 12026 { 12027 name: "FlagLT_ULT", 12028 argLen: 0, 12029 reg: regInfo{}, 12030 }, 12031 { 12032 name: "FlagLT_UGT", 12033 argLen: 0, 12034 reg: regInfo{}, 12035 }, 12036 { 12037 name: "FlagGT_UGT", 12038 argLen: 0, 12039 reg: regInfo{}, 12040 }, 12041 { 12042 name: "FlagGT_ULT", 12043 argLen: 0, 12044 reg: regInfo{}, 12045 }, 12046 { 12047 name: "InvertFlags", 12048 argLen: 1, 12049 reg: regInfo{}, 12050 }, 12051 12052 { 12053 name: "ADDV", 12054 argLen: 2, 12055 commutative: true, 12056 asm: mips.AADDVU, 12057 reg: regInfo{ 12058 inputs: []inputInfo{ 12059 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12060 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12061 }, 12062 outputs: []outputInfo{ 12063 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12064 }, 12065 }, 12066 }, 12067 { 12068 name: "ADDVconst", 12069 auxType: auxInt64, 12070 argLen: 1, 12071 asm: mips.AADDVU, 12072 reg: regInfo{ 12073 inputs: []inputInfo{ 12074 {0, 134217726}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g 12075 }, 12076 outputs: []outputInfo{ 12077 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12078 }, 12079 }, 12080 }, 12081 { 12082 name: "SUBV", 12083 argLen: 2, 12084 asm: mips.ASUBVU, 12085 reg: regInfo{ 12086 inputs: []inputInfo{ 12087 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12088 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12089 }, 12090 outputs: []outputInfo{ 12091 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12092 }, 12093 }, 12094 }, 12095 { 12096 name: "SUBVconst", 12097 auxType: auxInt64, 12098 argLen: 1, 12099 asm: mips.ASUBVU, 12100 reg: regInfo{ 12101 inputs: []inputInfo{ 12102 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12103 }, 12104 outputs: []outputInfo{ 12105 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12106 }, 12107 }, 12108 }, 12109 { 12110 name: "MULV", 12111 argLen: 2, 12112 commutative: true, 12113 asm: mips.AMULV, 12114 reg: regInfo{ 12115 inputs: []inputInfo{ 12116 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12117 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12118 }, 12119 outputs: []outputInfo{ 12120 {0, 576460752303423488}, // HI 12121 {1, 1152921504606846976}, // LO 12122 }, 12123 }, 12124 }, 12125 { 12126 name: "MULVU", 12127 argLen: 2, 12128 commutative: true, 12129 asm: mips.AMULVU, 12130 reg: regInfo{ 12131 inputs: []inputInfo{ 12132 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12133 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12134 }, 12135 outputs: []outputInfo{ 12136 {0, 576460752303423488}, // HI 12137 {1, 1152921504606846976}, // LO 12138 }, 12139 }, 12140 }, 12141 { 12142 name: "DIVV", 12143 argLen: 2, 12144 asm: mips.ADIVV, 12145 reg: regInfo{ 12146 inputs: []inputInfo{ 12147 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12148 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12149 }, 12150 outputs: []outputInfo{ 12151 {0, 576460752303423488}, // HI 12152 {1, 1152921504606846976}, // LO 12153 }, 12154 }, 12155 }, 12156 { 12157 name: "DIVVU", 12158 argLen: 2, 12159 asm: mips.ADIVVU, 12160 reg: regInfo{ 12161 inputs: []inputInfo{ 12162 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12163 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12164 }, 12165 outputs: []outputInfo{ 12166 {0, 576460752303423488}, // HI 12167 {1, 1152921504606846976}, // LO 12168 }, 12169 }, 12170 }, 12171 { 12172 name: "ADDF", 12173 argLen: 2, 12174 commutative: true, 12175 asm: mips.AADDF, 12176 reg: regInfo{ 12177 inputs: []inputInfo{ 12178 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12179 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12180 }, 12181 outputs: []outputInfo{ 12182 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12183 }, 12184 }, 12185 }, 12186 { 12187 name: "ADDD", 12188 argLen: 2, 12189 commutative: true, 12190 asm: mips.AADDD, 12191 reg: regInfo{ 12192 inputs: []inputInfo{ 12193 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12194 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12195 }, 12196 outputs: []outputInfo{ 12197 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12198 }, 12199 }, 12200 }, 12201 { 12202 name: "SUBF", 12203 argLen: 2, 12204 asm: mips.ASUBF, 12205 reg: regInfo{ 12206 inputs: []inputInfo{ 12207 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12208 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12209 }, 12210 outputs: []outputInfo{ 12211 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12212 }, 12213 }, 12214 }, 12215 { 12216 name: "SUBD", 12217 argLen: 2, 12218 asm: mips.ASUBD, 12219 reg: regInfo{ 12220 inputs: []inputInfo{ 12221 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12222 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12223 }, 12224 outputs: []outputInfo{ 12225 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12226 }, 12227 }, 12228 }, 12229 { 12230 name: "MULF", 12231 argLen: 2, 12232 commutative: true, 12233 asm: mips.AMULF, 12234 reg: regInfo{ 12235 inputs: []inputInfo{ 12236 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12237 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12238 }, 12239 outputs: []outputInfo{ 12240 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12241 }, 12242 }, 12243 }, 12244 { 12245 name: "MULD", 12246 argLen: 2, 12247 commutative: true, 12248 asm: mips.AMULD, 12249 reg: regInfo{ 12250 inputs: []inputInfo{ 12251 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12252 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12253 }, 12254 outputs: []outputInfo{ 12255 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12256 }, 12257 }, 12258 }, 12259 { 12260 name: "DIVF", 12261 argLen: 2, 12262 asm: mips.ADIVF, 12263 reg: regInfo{ 12264 inputs: []inputInfo{ 12265 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12266 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12267 }, 12268 outputs: []outputInfo{ 12269 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12270 }, 12271 }, 12272 }, 12273 { 12274 name: "DIVD", 12275 argLen: 2, 12276 asm: mips.ADIVD, 12277 reg: regInfo{ 12278 inputs: []inputInfo{ 12279 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12280 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12281 }, 12282 outputs: []outputInfo{ 12283 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12284 }, 12285 }, 12286 }, 12287 { 12288 name: "AND", 12289 argLen: 2, 12290 commutative: true, 12291 asm: mips.AAND, 12292 reg: regInfo{ 12293 inputs: []inputInfo{ 12294 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12295 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12296 }, 12297 outputs: []outputInfo{ 12298 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12299 }, 12300 }, 12301 }, 12302 { 12303 name: "ANDconst", 12304 auxType: auxInt64, 12305 argLen: 1, 12306 asm: mips.AAND, 12307 reg: regInfo{ 12308 inputs: []inputInfo{ 12309 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12310 }, 12311 outputs: []outputInfo{ 12312 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12313 }, 12314 }, 12315 }, 12316 { 12317 name: "OR", 12318 argLen: 2, 12319 commutative: true, 12320 asm: mips.AOR, 12321 reg: regInfo{ 12322 inputs: []inputInfo{ 12323 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12324 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12325 }, 12326 outputs: []outputInfo{ 12327 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12328 }, 12329 }, 12330 }, 12331 { 12332 name: "ORconst", 12333 auxType: auxInt64, 12334 argLen: 1, 12335 asm: mips.AOR, 12336 reg: regInfo{ 12337 inputs: []inputInfo{ 12338 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12339 }, 12340 outputs: []outputInfo{ 12341 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12342 }, 12343 }, 12344 }, 12345 { 12346 name: "XOR", 12347 argLen: 2, 12348 commutative: true, 12349 asm: mips.AXOR, 12350 reg: regInfo{ 12351 inputs: []inputInfo{ 12352 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12353 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12354 }, 12355 outputs: []outputInfo{ 12356 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12357 }, 12358 }, 12359 }, 12360 { 12361 name: "XORconst", 12362 auxType: auxInt64, 12363 argLen: 1, 12364 asm: mips.AXOR, 12365 reg: regInfo{ 12366 inputs: []inputInfo{ 12367 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12368 }, 12369 outputs: []outputInfo{ 12370 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12371 }, 12372 }, 12373 }, 12374 { 12375 name: "NOR", 12376 argLen: 2, 12377 commutative: true, 12378 asm: mips.ANOR, 12379 reg: regInfo{ 12380 inputs: []inputInfo{ 12381 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12382 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12383 }, 12384 outputs: []outputInfo{ 12385 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12386 }, 12387 }, 12388 }, 12389 { 12390 name: "NORconst", 12391 auxType: auxInt64, 12392 argLen: 1, 12393 asm: mips.ANOR, 12394 reg: regInfo{ 12395 inputs: []inputInfo{ 12396 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12397 }, 12398 outputs: []outputInfo{ 12399 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12400 }, 12401 }, 12402 }, 12403 { 12404 name: "NEGV", 12405 argLen: 1, 12406 reg: regInfo{ 12407 inputs: []inputInfo{ 12408 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12409 }, 12410 outputs: []outputInfo{ 12411 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12412 }, 12413 }, 12414 }, 12415 { 12416 name: "NEGF", 12417 argLen: 1, 12418 asm: mips.ANEGF, 12419 reg: regInfo{ 12420 inputs: []inputInfo{ 12421 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12422 }, 12423 outputs: []outputInfo{ 12424 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12425 }, 12426 }, 12427 }, 12428 { 12429 name: "NEGD", 12430 argLen: 1, 12431 asm: mips.ANEGD, 12432 reg: regInfo{ 12433 inputs: []inputInfo{ 12434 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12435 }, 12436 outputs: []outputInfo{ 12437 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12438 }, 12439 }, 12440 }, 12441 { 12442 name: "SLLV", 12443 argLen: 2, 12444 asm: mips.ASLLV, 12445 reg: regInfo{ 12446 inputs: []inputInfo{ 12447 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12448 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12449 }, 12450 outputs: []outputInfo{ 12451 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12452 }, 12453 }, 12454 }, 12455 { 12456 name: "SLLVconst", 12457 auxType: auxInt64, 12458 argLen: 1, 12459 asm: mips.ASLLV, 12460 reg: regInfo{ 12461 inputs: []inputInfo{ 12462 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12463 }, 12464 outputs: []outputInfo{ 12465 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12466 }, 12467 }, 12468 }, 12469 { 12470 name: "SRLV", 12471 argLen: 2, 12472 asm: mips.ASRLV, 12473 reg: regInfo{ 12474 inputs: []inputInfo{ 12475 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12476 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12477 }, 12478 outputs: []outputInfo{ 12479 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12480 }, 12481 }, 12482 }, 12483 { 12484 name: "SRLVconst", 12485 auxType: auxInt64, 12486 argLen: 1, 12487 asm: mips.ASRLV, 12488 reg: regInfo{ 12489 inputs: []inputInfo{ 12490 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12491 }, 12492 outputs: []outputInfo{ 12493 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12494 }, 12495 }, 12496 }, 12497 { 12498 name: "SRAV", 12499 argLen: 2, 12500 asm: mips.ASRAV, 12501 reg: regInfo{ 12502 inputs: []inputInfo{ 12503 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12504 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12505 }, 12506 outputs: []outputInfo{ 12507 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12508 }, 12509 }, 12510 }, 12511 { 12512 name: "SRAVconst", 12513 auxType: auxInt64, 12514 argLen: 1, 12515 asm: mips.ASRAV, 12516 reg: regInfo{ 12517 inputs: []inputInfo{ 12518 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12519 }, 12520 outputs: []outputInfo{ 12521 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12522 }, 12523 }, 12524 }, 12525 { 12526 name: "SGT", 12527 argLen: 2, 12528 asm: mips.ASGT, 12529 reg: regInfo{ 12530 inputs: []inputInfo{ 12531 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12532 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12533 }, 12534 outputs: []outputInfo{ 12535 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12536 }, 12537 }, 12538 }, 12539 { 12540 name: "SGTconst", 12541 auxType: auxInt64, 12542 argLen: 1, 12543 asm: mips.ASGT, 12544 reg: regInfo{ 12545 inputs: []inputInfo{ 12546 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12547 }, 12548 outputs: []outputInfo{ 12549 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12550 }, 12551 }, 12552 }, 12553 { 12554 name: "SGTU", 12555 argLen: 2, 12556 asm: mips.ASGTU, 12557 reg: regInfo{ 12558 inputs: []inputInfo{ 12559 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12560 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12561 }, 12562 outputs: []outputInfo{ 12563 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12564 }, 12565 }, 12566 }, 12567 { 12568 name: "SGTUconst", 12569 auxType: auxInt64, 12570 argLen: 1, 12571 asm: mips.ASGTU, 12572 reg: regInfo{ 12573 inputs: []inputInfo{ 12574 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12575 }, 12576 outputs: []outputInfo{ 12577 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12578 }, 12579 }, 12580 }, 12581 { 12582 name: "CMPEQF", 12583 argLen: 2, 12584 asm: mips.ACMPEQF, 12585 reg: regInfo{ 12586 inputs: []inputInfo{ 12587 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12588 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12589 }, 12590 }, 12591 }, 12592 { 12593 name: "CMPEQD", 12594 argLen: 2, 12595 asm: mips.ACMPEQD, 12596 reg: regInfo{ 12597 inputs: []inputInfo{ 12598 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12599 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12600 }, 12601 }, 12602 }, 12603 { 12604 name: "CMPGEF", 12605 argLen: 2, 12606 asm: mips.ACMPGEF, 12607 reg: regInfo{ 12608 inputs: []inputInfo{ 12609 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12610 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12611 }, 12612 }, 12613 }, 12614 { 12615 name: "CMPGED", 12616 argLen: 2, 12617 asm: mips.ACMPGED, 12618 reg: regInfo{ 12619 inputs: []inputInfo{ 12620 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12621 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12622 }, 12623 }, 12624 }, 12625 { 12626 name: "CMPGTF", 12627 argLen: 2, 12628 asm: mips.ACMPGTF, 12629 reg: regInfo{ 12630 inputs: []inputInfo{ 12631 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12632 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12633 }, 12634 }, 12635 }, 12636 { 12637 name: "CMPGTD", 12638 argLen: 2, 12639 asm: mips.ACMPGTD, 12640 reg: regInfo{ 12641 inputs: []inputInfo{ 12642 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12643 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12644 }, 12645 }, 12646 }, 12647 { 12648 name: "MOVVconst", 12649 auxType: auxInt64, 12650 argLen: 0, 12651 rematerializeable: true, 12652 asm: mips.AMOVV, 12653 reg: regInfo{ 12654 outputs: []outputInfo{ 12655 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12656 }, 12657 }, 12658 }, 12659 { 12660 name: "MOVFconst", 12661 auxType: auxFloat64, 12662 argLen: 0, 12663 rematerializeable: true, 12664 asm: mips.AMOVF, 12665 reg: regInfo{ 12666 outputs: []outputInfo{ 12667 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12668 }, 12669 }, 12670 }, 12671 { 12672 name: "MOVDconst", 12673 auxType: auxFloat64, 12674 argLen: 0, 12675 rematerializeable: true, 12676 asm: mips.AMOVD, 12677 reg: regInfo{ 12678 outputs: []outputInfo{ 12679 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12680 }, 12681 }, 12682 }, 12683 { 12684 name: "MOVVaddr", 12685 auxType: auxSymOff, 12686 argLen: 1, 12687 rematerializeable: true, 12688 asm: mips.AMOVV, 12689 reg: regInfo{ 12690 inputs: []inputInfo{ 12691 {0, 2305843009247248384}, // SP SB 12692 }, 12693 outputs: []outputInfo{ 12694 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12695 }, 12696 }, 12697 }, 12698 { 12699 name: "MOVBload", 12700 auxType: auxSymOff, 12701 argLen: 2, 12702 asm: mips.AMOVB, 12703 reg: regInfo{ 12704 inputs: []inputInfo{ 12705 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12706 }, 12707 outputs: []outputInfo{ 12708 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12709 }, 12710 }, 12711 }, 12712 { 12713 name: "MOVBUload", 12714 auxType: auxSymOff, 12715 argLen: 2, 12716 asm: mips.AMOVBU, 12717 reg: regInfo{ 12718 inputs: []inputInfo{ 12719 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12720 }, 12721 outputs: []outputInfo{ 12722 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12723 }, 12724 }, 12725 }, 12726 { 12727 name: "MOVHload", 12728 auxType: auxSymOff, 12729 argLen: 2, 12730 asm: mips.AMOVH, 12731 reg: regInfo{ 12732 inputs: []inputInfo{ 12733 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12734 }, 12735 outputs: []outputInfo{ 12736 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12737 }, 12738 }, 12739 }, 12740 { 12741 name: "MOVHUload", 12742 auxType: auxSymOff, 12743 argLen: 2, 12744 asm: mips.AMOVHU, 12745 reg: regInfo{ 12746 inputs: []inputInfo{ 12747 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12748 }, 12749 outputs: []outputInfo{ 12750 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12751 }, 12752 }, 12753 }, 12754 { 12755 name: "MOVWload", 12756 auxType: auxSymOff, 12757 argLen: 2, 12758 asm: mips.AMOVW, 12759 reg: regInfo{ 12760 inputs: []inputInfo{ 12761 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12762 }, 12763 outputs: []outputInfo{ 12764 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12765 }, 12766 }, 12767 }, 12768 { 12769 name: "MOVWUload", 12770 auxType: auxSymOff, 12771 argLen: 2, 12772 asm: mips.AMOVWU, 12773 reg: regInfo{ 12774 inputs: []inputInfo{ 12775 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12776 }, 12777 outputs: []outputInfo{ 12778 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12779 }, 12780 }, 12781 }, 12782 { 12783 name: "MOVVload", 12784 auxType: auxSymOff, 12785 argLen: 2, 12786 asm: mips.AMOVV, 12787 reg: regInfo{ 12788 inputs: []inputInfo{ 12789 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12790 }, 12791 outputs: []outputInfo{ 12792 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12793 }, 12794 }, 12795 }, 12796 { 12797 name: "MOVFload", 12798 auxType: auxSymOff, 12799 argLen: 2, 12800 asm: mips.AMOVF, 12801 reg: regInfo{ 12802 inputs: []inputInfo{ 12803 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12804 }, 12805 outputs: []outputInfo{ 12806 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12807 }, 12808 }, 12809 }, 12810 { 12811 name: "MOVDload", 12812 auxType: auxSymOff, 12813 argLen: 2, 12814 asm: mips.AMOVD, 12815 reg: regInfo{ 12816 inputs: []inputInfo{ 12817 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12818 }, 12819 outputs: []outputInfo{ 12820 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12821 }, 12822 }, 12823 }, 12824 { 12825 name: "MOVBstore", 12826 auxType: auxSymOff, 12827 argLen: 3, 12828 asm: mips.AMOVB, 12829 reg: regInfo{ 12830 inputs: []inputInfo{ 12831 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12832 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12833 }, 12834 }, 12835 }, 12836 { 12837 name: "MOVHstore", 12838 auxType: auxSymOff, 12839 argLen: 3, 12840 asm: mips.AMOVH, 12841 reg: regInfo{ 12842 inputs: []inputInfo{ 12843 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12844 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12845 }, 12846 }, 12847 }, 12848 { 12849 name: "MOVWstore", 12850 auxType: auxSymOff, 12851 argLen: 3, 12852 asm: mips.AMOVW, 12853 reg: regInfo{ 12854 inputs: []inputInfo{ 12855 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12856 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12857 }, 12858 }, 12859 }, 12860 { 12861 name: "MOVVstore", 12862 auxType: auxSymOff, 12863 argLen: 3, 12864 asm: mips.AMOVV, 12865 reg: regInfo{ 12866 inputs: []inputInfo{ 12867 {1, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12868 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12869 }, 12870 }, 12871 }, 12872 { 12873 name: "MOVFstore", 12874 auxType: auxSymOff, 12875 argLen: 3, 12876 asm: mips.AMOVF, 12877 reg: regInfo{ 12878 inputs: []inputInfo{ 12879 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12880 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12881 }, 12882 }, 12883 }, 12884 { 12885 name: "MOVDstore", 12886 auxType: auxSymOff, 12887 argLen: 3, 12888 asm: mips.AMOVD, 12889 reg: regInfo{ 12890 inputs: []inputInfo{ 12891 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12892 {1, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 12893 }, 12894 }, 12895 }, 12896 { 12897 name: "MOVBstorezero", 12898 auxType: auxSymOff, 12899 argLen: 2, 12900 asm: mips.AMOVB, 12901 reg: regInfo{ 12902 inputs: []inputInfo{ 12903 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12904 }, 12905 }, 12906 }, 12907 { 12908 name: "MOVHstorezero", 12909 auxType: auxSymOff, 12910 argLen: 2, 12911 asm: mips.AMOVH, 12912 reg: regInfo{ 12913 inputs: []inputInfo{ 12914 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12915 }, 12916 }, 12917 }, 12918 { 12919 name: "MOVWstorezero", 12920 auxType: auxSymOff, 12921 argLen: 2, 12922 asm: mips.AMOVW, 12923 reg: regInfo{ 12924 inputs: []inputInfo{ 12925 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12926 }, 12927 }, 12928 }, 12929 { 12930 name: "MOVVstorezero", 12931 auxType: auxSymOff, 12932 argLen: 2, 12933 asm: mips.AMOVV, 12934 reg: regInfo{ 12935 inputs: []inputInfo{ 12936 {0, 2305843009347911678}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g SB 12937 }, 12938 }, 12939 }, 12940 { 12941 name: "MOVBreg", 12942 argLen: 1, 12943 asm: mips.AMOVB, 12944 reg: regInfo{ 12945 inputs: []inputInfo{ 12946 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12947 }, 12948 outputs: []outputInfo{ 12949 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12950 }, 12951 }, 12952 }, 12953 { 12954 name: "MOVBUreg", 12955 argLen: 1, 12956 asm: mips.AMOVBU, 12957 reg: regInfo{ 12958 inputs: []inputInfo{ 12959 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12960 }, 12961 outputs: []outputInfo{ 12962 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12963 }, 12964 }, 12965 }, 12966 { 12967 name: "MOVHreg", 12968 argLen: 1, 12969 asm: mips.AMOVH, 12970 reg: regInfo{ 12971 inputs: []inputInfo{ 12972 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12973 }, 12974 outputs: []outputInfo{ 12975 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12976 }, 12977 }, 12978 }, 12979 { 12980 name: "MOVHUreg", 12981 argLen: 1, 12982 asm: mips.AMOVHU, 12983 reg: regInfo{ 12984 inputs: []inputInfo{ 12985 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12986 }, 12987 outputs: []outputInfo{ 12988 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 12989 }, 12990 }, 12991 }, 12992 { 12993 name: "MOVWreg", 12994 argLen: 1, 12995 asm: mips.AMOVW, 12996 reg: regInfo{ 12997 inputs: []inputInfo{ 12998 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 12999 }, 13000 outputs: []outputInfo{ 13001 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13002 }, 13003 }, 13004 }, 13005 { 13006 name: "MOVWUreg", 13007 argLen: 1, 13008 asm: mips.AMOVWU, 13009 reg: regInfo{ 13010 inputs: []inputInfo{ 13011 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13012 }, 13013 outputs: []outputInfo{ 13014 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13015 }, 13016 }, 13017 }, 13018 { 13019 name: "MOVVreg", 13020 argLen: 1, 13021 asm: mips.AMOVV, 13022 reg: regInfo{ 13023 inputs: []inputInfo{ 13024 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13025 }, 13026 outputs: []outputInfo{ 13027 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13028 }, 13029 }, 13030 }, 13031 { 13032 name: "MOVVnop", 13033 argLen: 1, 13034 resultInArg0: true, 13035 reg: regInfo{ 13036 inputs: []inputInfo{ 13037 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13038 }, 13039 outputs: []outputInfo{ 13040 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13041 }, 13042 }, 13043 }, 13044 { 13045 name: "MOVWF", 13046 argLen: 1, 13047 asm: mips.AMOVWF, 13048 reg: regInfo{ 13049 inputs: []inputInfo{ 13050 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13051 }, 13052 outputs: []outputInfo{ 13053 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13054 }, 13055 }, 13056 }, 13057 { 13058 name: "MOVWD", 13059 argLen: 1, 13060 asm: mips.AMOVWD, 13061 reg: regInfo{ 13062 inputs: []inputInfo{ 13063 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13064 }, 13065 outputs: []outputInfo{ 13066 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13067 }, 13068 }, 13069 }, 13070 { 13071 name: "MOVVF", 13072 argLen: 1, 13073 asm: mips.AMOVVF, 13074 reg: regInfo{ 13075 inputs: []inputInfo{ 13076 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13077 }, 13078 outputs: []outputInfo{ 13079 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13080 }, 13081 }, 13082 }, 13083 { 13084 name: "MOVVD", 13085 argLen: 1, 13086 asm: mips.AMOVVD, 13087 reg: regInfo{ 13088 inputs: []inputInfo{ 13089 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13090 }, 13091 outputs: []outputInfo{ 13092 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13093 }, 13094 }, 13095 }, 13096 { 13097 name: "TRUNCFW", 13098 argLen: 1, 13099 asm: mips.ATRUNCFW, 13100 reg: regInfo{ 13101 inputs: []inputInfo{ 13102 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13103 }, 13104 outputs: []outputInfo{ 13105 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13106 }, 13107 }, 13108 }, 13109 { 13110 name: "TRUNCDW", 13111 argLen: 1, 13112 asm: mips.ATRUNCDW, 13113 reg: regInfo{ 13114 inputs: []inputInfo{ 13115 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13116 }, 13117 outputs: []outputInfo{ 13118 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13119 }, 13120 }, 13121 }, 13122 { 13123 name: "TRUNCFV", 13124 argLen: 1, 13125 asm: mips.ATRUNCFV, 13126 reg: regInfo{ 13127 inputs: []inputInfo{ 13128 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13129 }, 13130 outputs: []outputInfo{ 13131 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13132 }, 13133 }, 13134 }, 13135 { 13136 name: "TRUNCDV", 13137 argLen: 1, 13138 asm: mips.ATRUNCDV, 13139 reg: regInfo{ 13140 inputs: []inputInfo{ 13141 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13142 }, 13143 outputs: []outputInfo{ 13144 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13145 }, 13146 }, 13147 }, 13148 { 13149 name: "MOVFD", 13150 argLen: 1, 13151 asm: mips.AMOVFD, 13152 reg: regInfo{ 13153 inputs: []inputInfo{ 13154 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13155 }, 13156 outputs: []outputInfo{ 13157 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13158 }, 13159 }, 13160 }, 13161 { 13162 name: "MOVDF", 13163 argLen: 1, 13164 asm: mips.AMOVDF, 13165 reg: regInfo{ 13166 inputs: []inputInfo{ 13167 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13168 }, 13169 outputs: []outputInfo{ 13170 {0, 385057768005959680}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 13171 }, 13172 }, 13173 }, 13174 { 13175 name: "CALLstatic", 13176 auxType: auxSymOff, 13177 argLen: 1, 13178 clobberFlags: true, 13179 reg: regInfo{ 13180 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13181 }, 13182 }, 13183 { 13184 name: "CALLclosure", 13185 auxType: auxInt64, 13186 argLen: 3, 13187 clobberFlags: true, 13188 reg: regInfo{ 13189 inputs: []inputInfo{ 13190 {1, 4194304}, // R22 13191 {0, 67108862}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP 13192 }, 13193 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13194 }, 13195 }, 13196 { 13197 name: "CALLdefer", 13198 auxType: auxInt64, 13199 argLen: 1, 13200 clobberFlags: true, 13201 reg: regInfo{ 13202 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13203 }, 13204 }, 13205 { 13206 name: "CALLgo", 13207 auxType: auxInt64, 13208 argLen: 1, 13209 clobberFlags: true, 13210 reg: regInfo{ 13211 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13212 }, 13213 }, 13214 { 13215 name: "CALLinter", 13216 auxType: auxInt64, 13217 argLen: 2, 13218 clobberFlags: true, 13219 reg: regInfo{ 13220 inputs: []inputInfo{ 13221 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13222 }, 13223 clobbers: 2114440025016893438, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F25 F27 F29 F31 HI LO 13224 }, 13225 }, 13226 { 13227 name: "DUFFZERO", 13228 auxType: auxInt64, 13229 argLen: 2, 13230 reg: regInfo{ 13231 inputs: []inputInfo{ 13232 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13233 }, 13234 clobbers: 2, // R1 13235 }, 13236 }, 13237 { 13238 name: "LoweredZero", 13239 auxType: auxInt64, 13240 argLen: 3, 13241 clobberFlags: true, 13242 reg: regInfo{ 13243 inputs: []inputInfo{ 13244 {0, 2}, // R1 13245 {1, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13246 }, 13247 clobbers: 2, // R1 13248 }, 13249 }, 13250 { 13251 name: "LoweredMove", 13252 auxType: auxInt64, 13253 argLen: 4, 13254 clobberFlags: true, 13255 reg: regInfo{ 13256 inputs: []inputInfo{ 13257 {0, 4}, // R2 13258 {1, 2}, // R1 13259 {2, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13260 }, 13261 clobbers: 6, // R1 R2 13262 }, 13263 }, 13264 { 13265 name: "LoweredNilCheck", 13266 argLen: 2, 13267 reg: regInfo{ 13268 inputs: []inputInfo{ 13269 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13270 }, 13271 }, 13272 }, 13273 { 13274 name: "FPFlagTrue", 13275 argLen: 1, 13276 reg: regInfo{ 13277 outputs: []outputInfo{ 13278 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13279 }, 13280 }, 13281 }, 13282 { 13283 name: "FPFlagFalse", 13284 argLen: 1, 13285 reg: regInfo{ 13286 outputs: []outputInfo{ 13287 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13288 }, 13289 }, 13290 }, 13291 { 13292 name: "LoweredGetClosurePtr", 13293 argLen: 0, 13294 reg: regInfo{ 13295 outputs: []outputInfo{ 13296 {0, 4194304}, // R22 13297 }, 13298 }, 13299 }, 13300 { 13301 name: "MOVVconvert", 13302 argLen: 2, 13303 asm: mips.AMOVV, 13304 reg: regInfo{ 13305 inputs: []inputInfo{ 13306 {0, 100663294}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g 13307 }, 13308 outputs: []outputInfo{ 13309 {0, 33554430}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 13310 }, 13311 }, 13312 }, 13313 13314 { 13315 name: "ADD", 13316 argLen: 2, 13317 commutative: true, 13318 asm: ppc64.AADD, 13319 reg: regInfo{ 13320 inputs: []inputInfo{ 13321 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13322 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13323 }, 13324 outputs: []outputInfo{ 13325 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13326 }, 13327 }, 13328 }, 13329 { 13330 name: "ADDconst", 13331 auxType: auxSymOff, 13332 argLen: 1, 13333 asm: ppc64.AADD, 13334 reg: regInfo{ 13335 inputs: []inputInfo{ 13336 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13337 }, 13338 outputs: []outputInfo{ 13339 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13340 }, 13341 }, 13342 }, 13343 { 13344 name: "FADD", 13345 argLen: 2, 13346 commutative: true, 13347 asm: ppc64.AFADD, 13348 reg: regInfo{ 13349 inputs: []inputInfo{ 13350 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13351 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13352 }, 13353 outputs: []outputInfo{ 13354 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13355 }, 13356 }, 13357 }, 13358 { 13359 name: "FADDS", 13360 argLen: 2, 13361 commutative: true, 13362 asm: ppc64.AFADDS, 13363 reg: regInfo{ 13364 inputs: []inputInfo{ 13365 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13366 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13367 }, 13368 outputs: []outputInfo{ 13369 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13370 }, 13371 }, 13372 }, 13373 { 13374 name: "SUB", 13375 argLen: 2, 13376 asm: ppc64.ASUB, 13377 reg: regInfo{ 13378 inputs: []inputInfo{ 13379 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13380 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13381 }, 13382 outputs: []outputInfo{ 13383 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13384 }, 13385 }, 13386 }, 13387 { 13388 name: "FSUB", 13389 argLen: 2, 13390 asm: ppc64.AFSUB, 13391 reg: regInfo{ 13392 inputs: []inputInfo{ 13393 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13394 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13395 }, 13396 outputs: []outputInfo{ 13397 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13398 }, 13399 }, 13400 }, 13401 { 13402 name: "FSUBS", 13403 argLen: 2, 13404 asm: ppc64.AFSUBS, 13405 reg: regInfo{ 13406 inputs: []inputInfo{ 13407 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13408 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13409 }, 13410 outputs: []outputInfo{ 13411 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13412 }, 13413 }, 13414 }, 13415 { 13416 name: "MULLD", 13417 argLen: 2, 13418 commutative: true, 13419 asm: ppc64.AMULLD, 13420 reg: regInfo{ 13421 inputs: []inputInfo{ 13422 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13423 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13424 }, 13425 outputs: []outputInfo{ 13426 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13427 }, 13428 }, 13429 }, 13430 { 13431 name: "MULLW", 13432 argLen: 2, 13433 commutative: true, 13434 asm: ppc64.AMULLW, 13435 reg: regInfo{ 13436 inputs: []inputInfo{ 13437 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13438 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13439 }, 13440 outputs: []outputInfo{ 13441 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13442 }, 13443 }, 13444 }, 13445 { 13446 name: "MULHD", 13447 argLen: 2, 13448 commutative: true, 13449 asm: ppc64.AMULHD, 13450 reg: regInfo{ 13451 inputs: []inputInfo{ 13452 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13453 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13454 }, 13455 outputs: []outputInfo{ 13456 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13457 }, 13458 }, 13459 }, 13460 { 13461 name: "MULHW", 13462 argLen: 2, 13463 commutative: true, 13464 asm: ppc64.AMULHW, 13465 reg: regInfo{ 13466 inputs: []inputInfo{ 13467 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13468 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13469 }, 13470 outputs: []outputInfo{ 13471 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13472 }, 13473 }, 13474 }, 13475 { 13476 name: "MULHDU", 13477 argLen: 2, 13478 commutative: true, 13479 asm: ppc64.AMULHDU, 13480 reg: regInfo{ 13481 inputs: []inputInfo{ 13482 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13483 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13484 }, 13485 outputs: []outputInfo{ 13486 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13487 }, 13488 }, 13489 }, 13490 { 13491 name: "MULHWU", 13492 argLen: 2, 13493 commutative: true, 13494 asm: ppc64.AMULHWU, 13495 reg: regInfo{ 13496 inputs: []inputInfo{ 13497 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13498 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13499 }, 13500 outputs: []outputInfo{ 13501 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13502 }, 13503 }, 13504 }, 13505 { 13506 name: "FMUL", 13507 argLen: 2, 13508 commutative: true, 13509 asm: ppc64.AFMUL, 13510 reg: regInfo{ 13511 inputs: []inputInfo{ 13512 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13513 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13514 }, 13515 outputs: []outputInfo{ 13516 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13517 }, 13518 }, 13519 }, 13520 { 13521 name: "FMULS", 13522 argLen: 2, 13523 commutative: true, 13524 asm: ppc64.AFMULS, 13525 reg: regInfo{ 13526 inputs: []inputInfo{ 13527 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13528 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13529 }, 13530 outputs: []outputInfo{ 13531 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13532 }, 13533 }, 13534 }, 13535 { 13536 name: "SRAD", 13537 argLen: 2, 13538 asm: ppc64.ASRAD, 13539 reg: regInfo{ 13540 inputs: []inputInfo{ 13541 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13542 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13543 }, 13544 outputs: []outputInfo{ 13545 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13546 }, 13547 }, 13548 }, 13549 { 13550 name: "SRAW", 13551 argLen: 2, 13552 asm: ppc64.ASRAW, 13553 reg: regInfo{ 13554 inputs: []inputInfo{ 13555 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13556 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13557 }, 13558 outputs: []outputInfo{ 13559 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13560 }, 13561 }, 13562 }, 13563 { 13564 name: "SRD", 13565 argLen: 2, 13566 asm: ppc64.ASRD, 13567 reg: regInfo{ 13568 inputs: []inputInfo{ 13569 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13570 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13571 }, 13572 outputs: []outputInfo{ 13573 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13574 }, 13575 }, 13576 }, 13577 { 13578 name: "SRW", 13579 argLen: 2, 13580 asm: ppc64.ASRW, 13581 reg: regInfo{ 13582 inputs: []inputInfo{ 13583 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13584 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13585 }, 13586 outputs: []outputInfo{ 13587 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13588 }, 13589 }, 13590 }, 13591 { 13592 name: "SLD", 13593 argLen: 2, 13594 asm: ppc64.ASLD, 13595 reg: regInfo{ 13596 inputs: []inputInfo{ 13597 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13598 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13599 }, 13600 outputs: []outputInfo{ 13601 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13602 }, 13603 }, 13604 }, 13605 { 13606 name: "SLW", 13607 argLen: 2, 13608 asm: ppc64.ASLW, 13609 reg: regInfo{ 13610 inputs: []inputInfo{ 13611 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13612 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13613 }, 13614 outputs: []outputInfo{ 13615 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13616 }, 13617 }, 13618 }, 13619 { 13620 name: "ADDconstForCarry", 13621 auxType: auxInt16, 13622 argLen: 1, 13623 asm: ppc64.AADDC, 13624 reg: regInfo{ 13625 inputs: []inputInfo{ 13626 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13627 }, 13628 clobbers: 1073741824, // R31 13629 }, 13630 }, 13631 { 13632 name: "MaskIfNotCarry", 13633 argLen: 1, 13634 asm: ppc64.AADDME, 13635 reg: regInfo{ 13636 outputs: []outputInfo{ 13637 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13638 }, 13639 }, 13640 }, 13641 { 13642 name: "SRADconst", 13643 auxType: auxInt64, 13644 argLen: 1, 13645 asm: ppc64.ASRAD, 13646 reg: regInfo{ 13647 inputs: []inputInfo{ 13648 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13649 }, 13650 outputs: []outputInfo{ 13651 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13652 }, 13653 }, 13654 }, 13655 { 13656 name: "SRAWconst", 13657 auxType: auxInt64, 13658 argLen: 1, 13659 asm: ppc64.ASRAW, 13660 reg: regInfo{ 13661 inputs: []inputInfo{ 13662 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13663 }, 13664 outputs: []outputInfo{ 13665 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13666 }, 13667 }, 13668 }, 13669 { 13670 name: "SRDconst", 13671 auxType: auxInt64, 13672 argLen: 1, 13673 asm: ppc64.ASRD, 13674 reg: regInfo{ 13675 inputs: []inputInfo{ 13676 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13677 }, 13678 outputs: []outputInfo{ 13679 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13680 }, 13681 }, 13682 }, 13683 { 13684 name: "SRWconst", 13685 auxType: auxInt64, 13686 argLen: 1, 13687 asm: ppc64.ASRW, 13688 reg: regInfo{ 13689 inputs: []inputInfo{ 13690 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13691 }, 13692 outputs: []outputInfo{ 13693 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13694 }, 13695 }, 13696 }, 13697 { 13698 name: "SLDconst", 13699 auxType: auxInt64, 13700 argLen: 1, 13701 asm: ppc64.ASLD, 13702 reg: regInfo{ 13703 inputs: []inputInfo{ 13704 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13705 }, 13706 outputs: []outputInfo{ 13707 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13708 }, 13709 }, 13710 }, 13711 { 13712 name: "SLWconst", 13713 auxType: auxInt64, 13714 argLen: 1, 13715 asm: ppc64.ASLW, 13716 reg: regInfo{ 13717 inputs: []inputInfo{ 13718 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13719 }, 13720 outputs: []outputInfo{ 13721 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13722 }, 13723 }, 13724 }, 13725 { 13726 name: "FDIV", 13727 argLen: 2, 13728 asm: ppc64.AFDIV, 13729 reg: regInfo{ 13730 inputs: []inputInfo{ 13731 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13732 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13733 }, 13734 outputs: []outputInfo{ 13735 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13736 }, 13737 }, 13738 }, 13739 { 13740 name: "FDIVS", 13741 argLen: 2, 13742 asm: ppc64.AFDIVS, 13743 reg: regInfo{ 13744 inputs: []inputInfo{ 13745 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13746 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13747 }, 13748 outputs: []outputInfo{ 13749 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13750 }, 13751 }, 13752 }, 13753 { 13754 name: "DIVD", 13755 argLen: 2, 13756 asm: ppc64.ADIVD, 13757 reg: regInfo{ 13758 inputs: []inputInfo{ 13759 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13760 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13761 }, 13762 outputs: []outputInfo{ 13763 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13764 }, 13765 }, 13766 }, 13767 { 13768 name: "DIVW", 13769 argLen: 2, 13770 asm: ppc64.ADIVW, 13771 reg: regInfo{ 13772 inputs: []inputInfo{ 13773 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13774 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13775 }, 13776 outputs: []outputInfo{ 13777 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13778 }, 13779 }, 13780 }, 13781 { 13782 name: "DIVDU", 13783 argLen: 2, 13784 asm: ppc64.ADIVDU, 13785 reg: regInfo{ 13786 inputs: []inputInfo{ 13787 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13788 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13789 }, 13790 outputs: []outputInfo{ 13791 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13792 }, 13793 }, 13794 }, 13795 { 13796 name: "DIVWU", 13797 argLen: 2, 13798 asm: ppc64.ADIVWU, 13799 reg: regInfo{ 13800 inputs: []inputInfo{ 13801 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13802 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13803 }, 13804 outputs: []outputInfo{ 13805 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13806 }, 13807 }, 13808 }, 13809 { 13810 name: "FCTIDZ", 13811 argLen: 1, 13812 asm: ppc64.AFCTIDZ, 13813 reg: regInfo{ 13814 inputs: []inputInfo{ 13815 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13816 }, 13817 outputs: []outputInfo{ 13818 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13819 }, 13820 }, 13821 }, 13822 { 13823 name: "FCTIWZ", 13824 argLen: 1, 13825 asm: ppc64.AFCTIWZ, 13826 reg: regInfo{ 13827 inputs: []inputInfo{ 13828 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13829 }, 13830 outputs: []outputInfo{ 13831 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13832 }, 13833 }, 13834 }, 13835 { 13836 name: "FCFID", 13837 argLen: 1, 13838 asm: ppc64.AFCFID, 13839 reg: regInfo{ 13840 inputs: []inputInfo{ 13841 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13842 }, 13843 outputs: []outputInfo{ 13844 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13845 }, 13846 }, 13847 }, 13848 { 13849 name: "FRSP", 13850 argLen: 1, 13851 asm: ppc64.AFRSP, 13852 reg: regInfo{ 13853 inputs: []inputInfo{ 13854 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13855 }, 13856 outputs: []outputInfo{ 13857 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13858 }, 13859 }, 13860 }, 13861 { 13862 name: "Xf2i64", 13863 argLen: 1, 13864 reg: regInfo{ 13865 inputs: []inputInfo{ 13866 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13867 }, 13868 outputs: []outputInfo{ 13869 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13870 }, 13871 }, 13872 }, 13873 { 13874 name: "Xi2f64", 13875 argLen: 1, 13876 reg: regInfo{ 13877 inputs: []inputInfo{ 13878 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13879 }, 13880 outputs: []outputInfo{ 13881 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13882 }, 13883 }, 13884 }, 13885 { 13886 name: "AND", 13887 argLen: 2, 13888 commutative: true, 13889 asm: ppc64.AAND, 13890 reg: regInfo{ 13891 inputs: []inputInfo{ 13892 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13893 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13894 }, 13895 outputs: []outputInfo{ 13896 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13897 }, 13898 }, 13899 }, 13900 { 13901 name: "ANDN", 13902 argLen: 2, 13903 asm: ppc64.AANDN, 13904 reg: regInfo{ 13905 inputs: []inputInfo{ 13906 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13907 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13908 }, 13909 outputs: []outputInfo{ 13910 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13911 }, 13912 }, 13913 }, 13914 { 13915 name: "OR", 13916 argLen: 2, 13917 commutative: true, 13918 asm: ppc64.AOR, 13919 reg: regInfo{ 13920 inputs: []inputInfo{ 13921 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13922 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13923 }, 13924 outputs: []outputInfo{ 13925 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13926 }, 13927 }, 13928 }, 13929 { 13930 name: "ORN", 13931 argLen: 2, 13932 asm: ppc64.AORN, 13933 reg: regInfo{ 13934 inputs: []inputInfo{ 13935 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13936 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13937 }, 13938 outputs: []outputInfo{ 13939 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13940 }, 13941 }, 13942 }, 13943 { 13944 name: "XOR", 13945 argLen: 2, 13946 commutative: true, 13947 asm: ppc64.AXOR, 13948 reg: regInfo{ 13949 inputs: []inputInfo{ 13950 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13951 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13952 }, 13953 outputs: []outputInfo{ 13954 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13955 }, 13956 }, 13957 }, 13958 { 13959 name: "EQV", 13960 argLen: 2, 13961 commutative: true, 13962 asm: ppc64.AEQV, 13963 reg: regInfo{ 13964 inputs: []inputInfo{ 13965 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13966 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13967 }, 13968 outputs: []outputInfo{ 13969 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13970 }, 13971 }, 13972 }, 13973 { 13974 name: "NEG", 13975 argLen: 1, 13976 asm: ppc64.ANEG, 13977 reg: regInfo{ 13978 inputs: []inputInfo{ 13979 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13980 }, 13981 outputs: []outputInfo{ 13982 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 13983 }, 13984 }, 13985 }, 13986 { 13987 name: "FNEG", 13988 argLen: 1, 13989 asm: ppc64.AFNEG, 13990 reg: regInfo{ 13991 inputs: []inputInfo{ 13992 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13993 }, 13994 outputs: []outputInfo{ 13995 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 13996 }, 13997 }, 13998 }, 13999 { 14000 name: "FSQRT", 14001 argLen: 1, 14002 asm: ppc64.AFSQRT, 14003 reg: regInfo{ 14004 inputs: []inputInfo{ 14005 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14006 }, 14007 outputs: []outputInfo{ 14008 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14009 }, 14010 }, 14011 }, 14012 { 14013 name: "FSQRTS", 14014 argLen: 1, 14015 asm: ppc64.AFSQRTS, 14016 reg: regInfo{ 14017 inputs: []inputInfo{ 14018 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14019 }, 14020 outputs: []outputInfo{ 14021 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14022 }, 14023 }, 14024 }, 14025 { 14026 name: "ORconst", 14027 auxType: auxInt64, 14028 argLen: 1, 14029 asm: ppc64.AOR, 14030 reg: regInfo{ 14031 inputs: []inputInfo{ 14032 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14033 }, 14034 outputs: []outputInfo{ 14035 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14036 }, 14037 }, 14038 }, 14039 { 14040 name: "XORconst", 14041 auxType: auxInt64, 14042 argLen: 1, 14043 asm: ppc64.AXOR, 14044 reg: regInfo{ 14045 inputs: []inputInfo{ 14046 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14047 }, 14048 outputs: []outputInfo{ 14049 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14050 }, 14051 }, 14052 }, 14053 { 14054 name: "ANDconst", 14055 auxType: auxInt64, 14056 argLen: 1, 14057 clobberFlags: true, 14058 asm: ppc64.AANDCC, 14059 reg: regInfo{ 14060 inputs: []inputInfo{ 14061 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14062 }, 14063 outputs: []outputInfo{ 14064 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14065 }, 14066 }, 14067 }, 14068 { 14069 name: "MOVBreg", 14070 argLen: 1, 14071 asm: ppc64.AMOVB, 14072 reg: regInfo{ 14073 inputs: []inputInfo{ 14074 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14075 }, 14076 outputs: []outputInfo{ 14077 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14078 }, 14079 }, 14080 }, 14081 { 14082 name: "MOVBZreg", 14083 argLen: 1, 14084 asm: ppc64.AMOVBZ, 14085 reg: regInfo{ 14086 inputs: []inputInfo{ 14087 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14088 }, 14089 outputs: []outputInfo{ 14090 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14091 }, 14092 }, 14093 }, 14094 { 14095 name: "MOVHreg", 14096 argLen: 1, 14097 asm: ppc64.AMOVH, 14098 reg: regInfo{ 14099 inputs: []inputInfo{ 14100 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14101 }, 14102 outputs: []outputInfo{ 14103 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14104 }, 14105 }, 14106 }, 14107 { 14108 name: "MOVHZreg", 14109 argLen: 1, 14110 asm: ppc64.AMOVHZ, 14111 reg: regInfo{ 14112 inputs: []inputInfo{ 14113 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14114 }, 14115 outputs: []outputInfo{ 14116 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14117 }, 14118 }, 14119 }, 14120 { 14121 name: "MOVWreg", 14122 argLen: 1, 14123 asm: ppc64.AMOVW, 14124 reg: regInfo{ 14125 inputs: []inputInfo{ 14126 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14127 }, 14128 outputs: []outputInfo{ 14129 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14130 }, 14131 }, 14132 }, 14133 { 14134 name: "MOVWZreg", 14135 argLen: 1, 14136 asm: ppc64.AMOVWZ, 14137 reg: regInfo{ 14138 inputs: []inputInfo{ 14139 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14140 }, 14141 outputs: []outputInfo{ 14142 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14143 }, 14144 }, 14145 }, 14146 { 14147 name: "MOVBload", 14148 auxType: auxSymOff, 14149 argLen: 2, 14150 asm: ppc64.AMOVB, 14151 reg: regInfo{ 14152 inputs: []inputInfo{ 14153 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14154 }, 14155 outputs: []outputInfo{ 14156 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14157 }, 14158 }, 14159 }, 14160 { 14161 name: "MOVBZload", 14162 auxType: auxSymOff, 14163 argLen: 2, 14164 asm: ppc64.AMOVBZ, 14165 reg: regInfo{ 14166 inputs: []inputInfo{ 14167 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14168 }, 14169 outputs: []outputInfo{ 14170 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14171 }, 14172 }, 14173 }, 14174 { 14175 name: "MOVHload", 14176 auxType: auxSymOff, 14177 argLen: 2, 14178 asm: ppc64.AMOVH, 14179 reg: regInfo{ 14180 inputs: []inputInfo{ 14181 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14182 }, 14183 outputs: []outputInfo{ 14184 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14185 }, 14186 }, 14187 }, 14188 { 14189 name: "MOVHZload", 14190 auxType: auxSymOff, 14191 argLen: 2, 14192 asm: ppc64.AMOVHZ, 14193 reg: regInfo{ 14194 inputs: []inputInfo{ 14195 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14196 }, 14197 outputs: []outputInfo{ 14198 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14199 }, 14200 }, 14201 }, 14202 { 14203 name: "MOVWload", 14204 auxType: auxSymOff, 14205 argLen: 2, 14206 asm: ppc64.AMOVW, 14207 reg: regInfo{ 14208 inputs: []inputInfo{ 14209 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14210 }, 14211 outputs: []outputInfo{ 14212 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14213 }, 14214 }, 14215 }, 14216 { 14217 name: "MOVWZload", 14218 auxType: auxSymOff, 14219 argLen: 2, 14220 asm: ppc64.AMOVWZ, 14221 reg: regInfo{ 14222 inputs: []inputInfo{ 14223 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14224 }, 14225 outputs: []outputInfo{ 14226 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14227 }, 14228 }, 14229 }, 14230 { 14231 name: "MOVDload", 14232 auxType: auxSymOff, 14233 argLen: 2, 14234 asm: ppc64.AMOVD, 14235 reg: regInfo{ 14236 inputs: []inputInfo{ 14237 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14238 }, 14239 outputs: []outputInfo{ 14240 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14241 }, 14242 }, 14243 }, 14244 { 14245 name: "FMOVDload", 14246 auxType: auxSymOff, 14247 argLen: 2, 14248 asm: ppc64.AFMOVD, 14249 reg: regInfo{ 14250 inputs: []inputInfo{ 14251 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14252 }, 14253 outputs: []outputInfo{ 14254 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14255 }, 14256 }, 14257 }, 14258 { 14259 name: "FMOVSload", 14260 auxType: auxSymOff, 14261 argLen: 2, 14262 asm: ppc64.AFMOVS, 14263 reg: regInfo{ 14264 inputs: []inputInfo{ 14265 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14266 }, 14267 outputs: []outputInfo{ 14268 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14269 }, 14270 }, 14271 }, 14272 { 14273 name: "MOVBstore", 14274 auxType: auxSymOff, 14275 argLen: 3, 14276 asm: ppc64.AMOVB, 14277 reg: regInfo{ 14278 inputs: []inputInfo{ 14279 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14280 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14281 }, 14282 }, 14283 }, 14284 { 14285 name: "MOVHstore", 14286 auxType: auxSymOff, 14287 argLen: 3, 14288 asm: ppc64.AMOVH, 14289 reg: regInfo{ 14290 inputs: []inputInfo{ 14291 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14292 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14293 }, 14294 }, 14295 }, 14296 { 14297 name: "MOVWstore", 14298 auxType: auxSymOff, 14299 argLen: 3, 14300 asm: ppc64.AMOVW, 14301 reg: regInfo{ 14302 inputs: []inputInfo{ 14303 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14304 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14305 }, 14306 }, 14307 }, 14308 { 14309 name: "MOVDstore", 14310 auxType: auxSymOff, 14311 argLen: 3, 14312 asm: ppc64.AMOVD, 14313 reg: regInfo{ 14314 inputs: []inputInfo{ 14315 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14316 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14317 }, 14318 }, 14319 }, 14320 { 14321 name: "FMOVDstore", 14322 auxType: auxSymOff, 14323 argLen: 3, 14324 asm: ppc64.AFMOVD, 14325 reg: regInfo{ 14326 inputs: []inputInfo{ 14327 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14328 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14329 }, 14330 }, 14331 }, 14332 { 14333 name: "FMOVSstore", 14334 auxType: auxSymOff, 14335 argLen: 3, 14336 asm: ppc64.AFMOVS, 14337 reg: regInfo{ 14338 inputs: []inputInfo{ 14339 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14340 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14341 }, 14342 }, 14343 }, 14344 { 14345 name: "MOVBstorezero", 14346 auxType: auxSymOff, 14347 argLen: 2, 14348 asm: ppc64.AMOVB, 14349 reg: regInfo{ 14350 inputs: []inputInfo{ 14351 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14352 }, 14353 }, 14354 }, 14355 { 14356 name: "MOVHstorezero", 14357 auxType: auxSymOff, 14358 argLen: 2, 14359 asm: ppc64.AMOVH, 14360 reg: regInfo{ 14361 inputs: []inputInfo{ 14362 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14363 }, 14364 }, 14365 }, 14366 { 14367 name: "MOVWstorezero", 14368 auxType: auxSymOff, 14369 argLen: 2, 14370 asm: ppc64.AMOVW, 14371 reg: regInfo{ 14372 inputs: []inputInfo{ 14373 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14374 }, 14375 }, 14376 }, 14377 { 14378 name: "MOVDstorezero", 14379 auxType: auxSymOff, 14380 argLen: 2, 14381 asm: ppc64.AMOVD, 14382 reg: regInfo{ 14383 inputs: []inputInfo{ 14384 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14385 }, 14386 }, 14387 }, 14388 { 14389 name: "MOVDaddr", 14390 auxType: auxSymOff, 14391 argLen: 1, 14392 rematerializeable: true, 14393 asm: ppc64.AMOVD, 14394 reg: regInfo{ 14395 inputs: []inputInfo{ 14396 {0, 3}, // SP SB 14397 }, 14398 outputs: []outputInfo{ 14399 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14400 }, 14401 }, 14402 }, 14403 { 14404 name: "MOVDconst", 14405 auxType: auxInt64, 14406 argLen: 0, 14407 rematerializeable: true, 14408 asm: ppc64.AMOVD, 14409 reg: regInfo{ 14410 outputs: []outputInfo{ 14411 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14412 }, 14413 }, 14414 }, 14415 { 14416 name: "MOVWconst", 14417 auxType: auxInt32, 14418 argLen: 0, 14419 rematerializeable: true, 14420 asm: ppc64.AMOVW, 14421 reg: regInfo{ 14422 outputs: []outputInfo{ 14423 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14424 }, 14425 }, 14426 }, 14427 { 14428 name: "FMOVDconst", 14429 auxType: auxFloat64, 14430 argLen: 0, 14431 rematerializeable: true, 14432 asm: ppc64.AFMOVD, 14433 reg: regInfo{ 14434 outputs: []outputInfo{ 14435 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14436 }, 14437 }, 14438 }, 14439 { 14440 name: "FMOVSconst", 14441 auxType: auxFloat32, 14442 argLen: 0, 14443 rematerializeable: true, 14444 asm: ppc64.AFMOVS, 14445 reg: regInfo{ 14446 outputs: []outputInfo{ 14447 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14448 }, 14449 }, 14450 }, 14451 { 14452 name: "FCMPU", 14453 argLen: 2, 14454 asm: ppc64.AFCMPU, 14455 reg: regInfo{ 14456 inputs: []inputInfo{ 14457 {0, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14458 {1, 288230371856744448}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14459 }, 14460 }, 14461 }, 14462 { 14463 name: "CMP", 14464 argLen: 2, 14465 asm: ppc64.ACMP, 14466 reg: regInfo{ 14467 inputs: []inputInfo{ 14468 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14469 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14470 }, 14471 }, 14472 }, 14473 { 14474 name: "CMPU", 14475 argLen: 2, 14476 asm: ppc64.ACMPU, 14477 reg: regInfo{ 14478 inputs: []inputInfo{ 14479 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14480 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14481 }, 14482 }, 14483 }, 14484 { 14485 name: "CMPW", 14486 argLen: 2, 14487 asm: ppc64.ACMPW, 14488 reg: regInfo{ 14489 inputs: []inputInfo{ 14490 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14491 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14492 }, 14493 }, 14494 }, 14495 { 14496 name: "CMPWU", 14497 argLen: 2, 14498 asm: ppc64.ACMPWU, 14499 reg: regInfo{ 14500 inputs: []inputInfo{ 14501 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14502 {1, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14503 }, 14504 }, 14505 }, 14506 { 14507 name: "CMPconst", 14508 auxType: auxInt64, 14509 argLen: 1, 14510 asm: ppc64.ACMP, 14511 reg: regInfo{ 14512 inputs: []inputInfo{ 14513 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14514 }, 14515 }, 14516 }, 14517 { 14518 name: "CMPUconst", 14519 auxType: auxInt64, 14520 argLen: 1, 14521 asm: ppc64.ACMPU, 14522 reg: regInfo{ 14523 inputs: []inputInfo{ 14524 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14525 }, 14526 }, 14527 }, 14528 { 14529 name: "CMPWconst", 14530 auxType: auxInt32, 14531 argLen: 1, 14532 asm: ppc64.ACMPW, 14533 reg: regInfo{ 14534 inputs: []inputInfo{ 14535 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14536 }, 14537 }, 14538 }, 14539 { 14540 name: "CMPWUconst", 14541 auxType: auxInt32, 14542 argLen: 1, 14543 asm: ppc64.ACMPWU, 14544 reg: regInfo{ 14545 inputs: []inputInfo{ 14546 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14547 }, 14548 }, 14549 }, 14550 { 14551 name: "Equal", 14552 argLen: 1, 14553 reg: regInfo{ 14554 outputs: []outputInfo{ 14555 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14556 }, 14557 }, 14558 }, 14559 { 14560 name: "NotEqual", 14561 argLen: 1, 14562 reg: regInfo{ 14563 outputs: []outputInfo{ 14564 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14565 }, 14566 }, 14567 }, 14568 { 14569 name: "LessThan", 14570 argLen: 1, 14571 reg: regInfo{ 14572 outputs: []outputInfo{ 14573 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14574 }, 14575 }, 14576 }, 14577 { 14578 name: "FLessThan", 14579 argLen: 1, 14580 reg: regInfo{ 14581 outputs: []outputInfo{ 14582 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14583 }, 14584 }, 14585 }, 14586 { 14587 name: "LessEqual", 14588 argLen: 1, 14589 reg: regInfo{ 14590 outputs: []outputInfo{ 14591 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14592 }, 14593 }, 14594 }, 14595 { 14596 name: "FLessEqual", 14597 argLen: 1, 14598 reg: regInfo{ 14599 outputs: []outputInfo{ 14600 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14601 }, 14602 }, 14603 }, 14604 { 14605 name: "GreaterThan", 14606 argLen: 1, 14607 reg: regInfo{ 14608 outputs: []outputInfo{ 14609 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14610 }, 14611 }, 14612 }, 14613 { 14614 name: "FGreaterThan", 14615 argLen: 1, 14616 reg: regInfo{ 14617 outputs: []outputInfo{ 14618 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14619 }, 14620 }, 14621 }, 14622 { 14623 name: "GreaterEqual", 14624 argLen: 1, 14625 reg: regInfo{ 14626 outputs: []outputInfo{ 14627 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14628 }, 14629 }, 14630 }, 14631 { 14632 name: "FGreaterEqual", 14633 argLen: 1, 14634 reg: regInfo{ 14635 outputs: []outputInfo{ 14636 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14637 }, 14638 }, 14639 }, 14640 { 14641 name: "LoweredGetClosurePtr", 14642 argLen: 0, 14643 reg: regInfo{ 14644 outputs: []outputInfo{ 14645 {0, 1024}, // R11 14646 }, 14647 }, 14648 }, 14649 { 14650 name: "LoweredNilCheck", 14651 argLen: 2, 14652 clobberFlags: true, 14653 reg: regInfo{ 14654 inputs: []inputInfo{ 14655 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14656 }, 14657 clobbers: 1073741824, // R31 14658 }, 14659 }, 14660 { 14661 name: "MOVDconvert", 14662 argLen: 2, 14663 asm: ppc64.AMOVD, 14664 reg: regInfo{ 14665 inputs: []inputInfo{ 14666 {0, 536866815}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14667 }, 14668 outputs: []outputInfo{ 14669 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14670 }, 14671 }, 14672 }, 14673 { 14674 name: "CALLstatic", 14675 auxType: auxSymOff, 14676 argLen: 1, 14677 clobberFlags: true, 14678 reg: regInfo{ 14679 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14680 }, 14681 }, 14682 { 14683 name: "CALLclosure", 14684 auxType: auxInt64, 14685 argLen: 3, 14686 clobberFlags: true, 14687 reg: regInfo{ 14688 inputs: []inputInfo{ 14689 {1, 1024}, // R11 14690 {0, 536866813}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14691 }, 14692 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14693 }, 14694 }, 14695 { 14696 name: "CALLdefer", 14697 auxType: auxInt64, 14698 argLen: 1, 14699 clobberFlags: true, 14700 reg: regInfo{ 14701 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14702 }, 14703 }, 14704 { 14705 name: "CALLgo", 14706 auxType: auxInt64, 14707 argLen: 1, 14708 clobberFlags: true, 14709 reg: regInfo{ 14710 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14711 }, 14712 }, 14713 { 14714 name: "CALLinter", 14715 auxType: auxInt64, 14716 argLen: 2, 14717 clobberFlags: true, 14718 reg: regInfo{ 14719 inputs: []inputInfo{ 14720 {0, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14721 }, 14722 clobbers: 288230372930482172, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 14723 }, 14724 }, 14725 { 14726 name: "LoweredZero", 14727 auxType: auxInt64, 14728 argLen: 3, 14729 clobberFlags: true, 14730 reg: regInfo{ 14731 inputs: []inputInfo{ 14732 {0, 4}, // R3 14733 {1, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14734 }, 14735 clobbers: 4, // R3 14736 }, 14737 }, 14738 { 14739 name: "LoweredMove", 14740 auxType: auxInt64, 14741 argLen: 4, 14742 clobberFlags: true, 14743 reg: regInfo{ 14744 inputs: []inputInfo{ 14745 {0, 4}, // R3 14746 {1, 8}, // R4 14747 {2, 536866812}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 14748 }, 14749 clobbers: 12, // R3 R4 14750 }, 14751 }, 14752 { 14753 name: "InvertFlags", 14754 argLen: 1, 14755 reg: regInfo{}, 14756 }, 14757 { 14758 name: "FlagEQ", 14759 argLen: 0, 14760 reg: regInfo{}, 14761 }, 14762 { 14763 name: "FlagLT", 14764 argLen: 0, 14765 reg: regInfo{}, 14766 }, 14767 { 14768 name: "FlagGT", 14769 argLen: 0, 14770 reg: regInfo{}, 14771 }, 14772 14773 { 14774 name: "Add8", 14775 argLen: 2, 14776 commutative: true, 14777 generic: true, 14778 }, 14779 { 14780 name: "Add16", 14781 argLen: 2, 14782 commutative: true, 14783 generic: true, 14784 }, 14785 { 14786 name: "Add32", 14787 argLen: 2, 14788 commutative: true, 14789 generic: true, 14790 }, 14791 { 14792 name: "Add64", 14793 argLen: 2, 14794 commutative: true, 14795 generic: true, 14796 }, 14797 { 14798 name: "AddPtr", 14799 argLen: 2, 14800 generic: true, 14801 }, 14802 { 14803 name: "Add32F", 14804 argLen: 2, 14805 generic: true, 14806 }, 14807 { 14808 name: "Add64F", 14809 argLen: 2, 14810 generic: true, 14811 }, 14812 { 14813 name: "Sub8", 14814 argLen: 2, 14815 generic: true, 14816 }, 14817 { 14818 name: "Sub16", 14819 argLen: 2, 14820 generic: true, 14821 }, 14822 { 14823 name: "Sub32", 14824 argLen: 2, 14825 generic: true, 14826 }, 14827 { 14828 name: "Sub64", 14829 argLen: 2, 14830 generic: true, 14831 }, 14832 { 14833 name: "SubPtr", 14834 argLen: 2, 14835 generic: true, 14836 }, 14837 { 14838 name: "Sub32F", 14839 argLen: 2, 14840 generic: true, 14841 }, 14842 { 14843 name: "Sub64F", 14844 argLen: 2, 14845 generic: true, 14846 }, 14847 { 14848 name: "Mul8", 14849 argLen: 2, 14850 commutative: true, 14851 generic: true, 14852 }, 14853 { 14854 name: "Mul16", 14855 argLen: 2, 14856 commutative: true, 14857 generic: true, 14858 }, 14859 { 14860 name: "Mul32", 14861 argLen: 2, 14862 commutative: true, 14863 generic: true, 14864 }, 14865 { 14866 name: "Mul64", 14867 argLen: 2, 14868 commutative: true, 14869 generic: true, 14870 }, 14871 { 14872 name: "Mul32F", 14873 argLen: 2, 14874 generic: true, 14875 }, 14876 { 14877 name: "Mul64F", 14878 argLen: 2, 14879 generic: true, 14880 }, 14881 { 14882 name: "Div32F", 14883 argLen: 2, 14884 generic: true, 14885 }, 14886 { 14887 name: "Div64F", 14888 argLen: 2, 14889 generic: true, 14890 }, 14891 { 14892 name: "Hmul8", 14893 argLen: 2, 14894 generic: true, 14895 }, 14896 { 14897 name: "Hmul8u", 14898 argLen: 2, 14899 generic: true, 14900 }, 14901 { 14902 name: "Hmul16", 14903 argLen: 2, 14904 generic: true, 14905 }, 14906 { 14907 name: "Hmul16u", 14908 argLen: 2, 14909 generic: true, 14910 }, 14911 { 14912 name: "Hmul32", 14913 argLen: 2, 14914 generic: true, 14915 }, 14916 { 14917 name: "Hmul32u", 14918 argLen: 2, 14919 generic: true, 14920 }, 14921 { 14922 name: "Hmul64", 14923 argLen: 2, 14924 generic: true, 14925 }, 14926 { 14927 name: "Hmul64u", 14928 argLen: 2, 14929 generic: true, 14930 }, 14931 { 14932 name: "Avg64u", 14933 argLen: 2, 14934 generic: true, 14935 }, 14936 { 14937 name: "Div8", 14938 argLen: 2, 14939 generic: true, 14940 }, 14941 { 14942 name: "Div8u", 14943 argLen: 2, 14944 generic: true, 14945 }, 14946 { 14947 name: "Div16", 14948 argLen: 2, 14949 generic: true, 14950 }, 14951 { 14952 name: "Div16u", 14953 argLen: 2, 14954 generic: true, 14955 }, 14956 { 14957 name: "Div32", 14958 argLen: 2, 14959 generic: true, 14960 }, 14961 { 14962 name: "Div32u", 14963 argLen: 2, 14964 generic: true, 14965 }, 14966 { 14967 name: "Div64", 14968 argLen: 2, 14969 generic: true, 14970 }, 14971 { 14972 name: "Div64u", 14973 argLen: 2, 14974 generic: true, 14975 }, 14976 { 14977 name: "Mod8", 14978 argLen: 2, 14979 generic: true, 14980 }, 14981 { 14982 name: "Mod8u", 14983 argLen: 2, 14984 generic: true, 14985 }, 14986 { 14987 name: "Mod16", 14988 argLen: 2, 14989 generic: true, 14990 }, 14991 { 14992 name: "Mod16u", 14993 argLen: 2, 14994 generic: true, 14995 }, 14996 { 14997 name: "Mod32", 14998 argLen: 2, 14999 generic: true, 15000 }, 15001 { 15002 name: "Mod32u", 15003 argLen: 2, 15004 generic: true, 15005 }, 15006 { 15007 name: "Mod64", 15008 argLen: 2, 15009 generic: true, 15010 }, 15011 { 15012 name: "Mod64u", 15013 argLen: 2, 15014 generic: true, 15015 }, 15016 { 15017 name: "And8", 15018 argLen: 2, 15019 commutative: true, 15020 generic: true, 15021 }, 15022 { 15023 name: "And16", 15024 argLen: 2, 15025 commutative: true, 15026 generic: true, 15027 }, 15028 { 15029 name: "And32", 15030 argLen: 2, 15031 commutative: true, 15032 generic: true, 15033 }, 15034 { 15035 name: "And64", 15036 argLen: 2, 15037 commutative: true, 15038 generic: true, 15039 }, 15040 { 15041 name: "Or8", 15042 argLen: 2, 15043 commutative: true, 15044 generic: true, 15045 }, 15046 { 15047 name: "Or16", 15048 argLen: 2, 15049 commutative: true, 15050 generic: true, 15051 }, 15052 { 15053 name: "Or32", 15054 argLen: 2, 15055 commutative: true, 15056 generic: true, 15057 }, 15058 { 15059 name: "Or64", 15060 argLen: 2, 15061 commutative: true, 15062 generic: true, 15063 }, 15064 { 15065 name: "Xor8", 15066 argLen: 2, 15067 commutative: true, 15068 generic: true, 15069 }, 15070 { 15071 name: "Xor16", 15072 argLen: 2, 15073 commutative: true, 15074 generic: true, 15075 }, 15076 { 15077 name: "Xor32", 15078 argLen: 2, 15079 commutative: true, 15080 generic: true, 15081 }, 15082 { 15083 name: "Xor64", 15084 argLen: 2, 15085 commutative: true, 15086 generic: true, 15087 }, 15088 { 15089 name: "Lsh8x8", 15090 argLen: 2, 15091 generic: true, 15092 }, 15093 { 15094 name: "Lsh8x16", 15095 argLen: 2, 15096 generic: true, 15097 }, 15098 { 15099 name: "Lsh8x32", 15100 argLen: 2, 15101 generic: true, 15102 }, 15103 { 15104 name: "Lsh8x64", 15105 argLen: 2, 15106 generic: true, 15107 }, 15108 { 15109 name: "Lsh16x8", 15110 argLen: 2, 15111 generic: true, 15112 }, 15113 { 15114 name: "Lsh16x16", 15115 argLen: 2, 15116 generic: true, 15117 }, 15118 { 15119 name: "Lsh16x32", 15120 argLen: 2, 15121 generic: true, 15122 }, 15123 { 15124 name: "Lsh16x64", 15125 argLen: 2, 15126 generic: true, 15127 }, 15128 { 15129 name: "Lsh32x8", 15130 argLen: 2, 15131 generic: true, 15132 }, 15133 { 15134 name: "Lsh32x16", 15135 argLen: 2, 15136 generic: true, 15137 }, 15138 { 15139 name: "Lsh32x32", 15140 argLen: 2, 15141 generic: true, 15142 }, 15143 { 15144 name: "Lsh32x64", 15145 argLen: 2, 15146 generic: true, 15147 }, 15148 { 15149 name: "Lsh64x8", 15150 argLen: 2, 15151 generic: true, 15152 }, 15153 { 15154 name: "Lsh64x16", 15155 argLen: 2, 15156 generic: true, 15157 }, 15158 { 15159 name: "Lsh64x32", 15160 argLen: 2, 15161 generic: true, 15162 }, 15163 { 15164 name: "Lsh64x64", 15165 argLen: 2, 15166 generic: true, 15167 }, 15168 { 15169 name: "Rsh8x8", 15170 argLen: 2, 15171 generic: true, 15172 }, 15173 { 15174 name: "Rsh8x16", 15175 argLen: 2, 15176 generic: true, 15177 }, 15178 { 15179 name: "Rsh8x32", 15180 argLen: 2, 15181 generic: true, 15182 }, 15183 { 15184 name: "Rsh8x64", 15185 argLen: 2, 15186 generic: true, 15187 }, 15188 { 15189 name: "Rsh16x8", 15190 argLen: 2, 15191 generic: true, 15192 }, 15193 { 15194 name: "Rsh16x16", 15195 argLen: 2, 15196 generic: true, 15197 }, 15198 { 15199 name: "Rsh16x32", 15200 argLen: 2, 15201 generic: true, 15202 }, 15203 { 15204 name: "Rsh16x64", 15205 argLen: 2, 15206 generic: true, 15207 }, 15208 { 15209 name: "Rsh32x8", 15210 argLen: 2, 15211 generic: true, 15212 }, 15213 { 15214 name: "Rsh32x16", 15215 argLen: 2, 15216 generic: true, 15217 }, 15218 { 15219 name: "Rsh32x32", 15220 argLen: 2, 15221 generic: true, 15222 }, 15223 { 15224 name: "Rsh32x64", 15225 argLen: 2, 15226 generic: true, 15227 }, 15228 { 15229 name: "Rsh64x8", 15230 argLen: 2, 15231 generic: true, 15232 }, 15233 { 15234 name: "Rsh64x16", 15235 argLen: 2, 15236 generic: true, 15237 }, 15238 { 15239 name: "Rsh64x32", 15240 argLen: 2, 15241 generic: true, 15242 }, 15243 { 15244 name: "Rsh64x64", 15245 argLen: 2, 15246 generic: true, 15247 }, 15248 { 15249 name: "Rsh8Ux8", 15250 argLen: 2, 15251 generic: true, 15252 }, 15253 { 15254 name: "Rsh8Ux16", 15255 argLen: 2, 15256 generic: true, 15257 }, 15258 { 15259 name: "Rsh8Ux32", 15260 argLen: 2, 15261 generic: true, 15262 }, 15263 { 15264 name: "Rsh8Ux64", 15265 argLen: 2, 15266 generic: true, 15267 }, 15268 { 15269 name: "Rsh16Ux8", 15270 argLen: 2, 15271 generic: true, 15272 }, 15273 { 15274 name: "Rsh16Ux16", 15275 argLen: 2, 15276 generic: true, 15277 }, 15278 { 15279 name: "Rsh16Ux32", 15280 argLen: 2, 15281 generic: true, 15282 }, 15283 { 15284 name: "Rsh16Ux64", 15285 argLen: 2, 15286 generic: true, 15287 }, 15288 { 15289 name: "Rsh32Ux8", 15290 argLen: 2, 15291 generic: true, 15292 }, 15293 { 15294 name: "Rsh32Ux16", 15295 argLen: 2, 15296 generic: true, 15297 }, 15298 { 15299 name: "Rsh32Ux32", 15300 argLen: 2, 15301 generic: true, 15302 }, 15303 { 15304 name: "Rsh32Ux64", 15305 argLen: 2, 15306 generic: true, 15307 }, 15308 { 15309 name: "Rsh64Ux8", 15310 argLen: 2, 15311 generic: true, 15312 }, 15313 { 15314 name: "Rsh64Ux16", 15315 argLen: 2, 15316 generic: true, 15317 }, 15318 { 15319 name: "Rsh64Ux32", 15320 argLen: 2, 15321 generic: true, 15322 }, 15323 { 15324 name: "Rsh64Ux64", 15325 argLen: 2, 15326 generic: true, 15327 }, 15328 { 15329 name: "Lrot8", 15330 auxType: auxInt64, 15331 argLen: 1, 15332 generic: true, 15333 }, 15334 { 15335 name: "Lrot16", 15336 auxType: auxInt64, 15337 argLen: 1, 15338 generic: true, 15339 }, 15340 { 15341 name: "Lrot32", 15342 auxType: auxInt64, 15343 argLen: 1, 15344 generic: true, 15345 }, 15346 { 15347 name: "Lrot64", 15348 auxType: auxInt64, 15349 argLen: 1, 15350 generic: true, 15351 }, 15352 { 15353 name: "Eq8", 15354 argLen: 2, 15355 commutative: true, 15356 generic: true, 15357 }, 15358 { 15359 name: "Eq16", 15360 argLen: 2, 15361 commutative: true, 15362 generic: true, 15363 }, 15364 { 15365 name: "Eq32", 15366 argLen: 2, 15367 commutative: true, 15368 generic: true, 15369 }, 15370 { 15371 name: "Eq64", 15372 argLen: 2, 15373 commutative: true, 15374 generic: true, 15375 }, 15376 { 15377 name: "EqPtr", 15378 argLen: 2, 15379 commutative: true, 15380 generic: true, 15381 }, 15382 { 15383 name: "EqInter", 15384 argLen: 2, 15385 generic: true, 15386 }, 15387 { 15388 name: "EqSlice", 15389 argLen: 2, 15390 generic: true, 15391 }, 15392 { 15393 name: "Eq32F", 15394 argLen: 2, 15395 generic: true, 15396 }, 15397 { 15398 name: "Eq64F", 15399 argLen: 2, 15400 generic: true, 15401 }, 15402 { 15403 name: "Neq8", 15404 argLen: 2, 15405 commutative: true, 15406 generic: true, 15407 }, 15408 { 15409 name: "Neq16", 15410 argLen: 2, 15411 commutative: true, 15412 generic: true, 15413 }, 15414 { 15415 name: "Neq32", 15416 argLen: 2, 15417 commutative: true, 15418 generic: true, 15419 }, 15420 { 15421 name: "Neq64", 15422 argLen: 2, 15423 commutative: true, 15424 generic: true, 15425 }, 15426 { 15427 name: "NeqPtr", 15428 argLen: 2, 15429 commutative: true, 15430 generic: true, 15431 }, 15432 { 15433 name: "NeqInter", 15434 argLen: 2, 15435 generic: true, 15436 }, 15437 { 15438 name: "NeqSlice", 15439 argLen: 2, 15440 generic: true, 15441 }, 15442 { 15443 name: "Neq32F", 15444 argLen: 2, 15445 generic: true, 15446 }, 15447 { 15448 name: "Neq64F", 15449 argLen: 2, 15450 generic: true, 15451 }, 15452 { 15453 name: "Less8", 15454 argLen: 2, 15455 generic: true, 15456 }, 15457 { 15458 name: "Less8U", 15459 argLen: 2, 15460 generic: true, 15461 }, 15462 { 15463 name: "Less16", 15464 argLen: 2, 15465 generic: true, 15466 }, 15467 { 15468 name: "Less16U", 15469 argLen: 2, 15470 generic: true, 15471 }, 15472 { 15473 name: "Less32", 15474 argLen: 2, 15475 generic: true, 15476 }, 15477 { 15478 name: "Less32U", 15479 argLen: 2, 15480 generic: true, 15481 }, 15482 { 15483 name: "Less64", 15484 argLen: 2, 15485 generic: true, 15486 }, 15487 { 15488 name: "Less64U", 15489 argLen: 2, 15490 generic: true, 15491 }, 15492 { 15493 name: "Less32F", 15494 argLen: 2, 15495 generic: true, 15496 }, 15497 { 15498 name: "Less64F", 15499 argLen: 2, 15500 generic: true, 15501 }, 15502 { 15503 name: "Leq8", 15504 argLen: 2, 15505 generic: true, 15506 }, 15507 { 15508 name: "Leq8U", 15509 argLen: 2, 15510 generic: true, 15511 }, 15512 { 15513 name: "Leq16", 15514 argLen: 2, 15515 generic: true, 15516 }, 15517 { 15518 name: "Leq16U", 15519 argLen: 2, 15520 generic: true, 15521 }, 15522 { 15523 name: "Leq32", 15524 argLen: 2, 15525 generic: true, 15526 }, 15527 { 15528 name: "Leq32U", 15529 argLen: 2, 15530 generic: true, 15531 }, 15532 { 15533 name: "Leq64", 15534 argLen: 2, 15535 generic: true, 15536 }, 15537 { 15538 name: "Leq64U", 15539 argLen: 2, 15540 generic: true, 15541 }, 15542 { 15543 name: "Leq32F", 15544 argLen: 2, 15545 generic: true, 15546 }, 15547 { 15548 name: "Leq64F", 15549 argLen: 2, 15550 generic: true, 15551 }, 15552 { 15553 name: "Greater8", 15554 argLen: 2, 15555 generic: true, 15556 }, 15557 { 15558 name: "Greater8U", 15559 argLen: 2, 15560 generic: true, 15561 }, 15562 { 15563 name: "Greater16", 15564 argLen: 2, 15565 generic: true, 15566 }, 15567 { 15568 name: "Greater16U", 15569 argLen: 2, 15570 generic: true, 15571 }, 15572 { 15573 name: "Greater32", 15574 argLen: 2, 15575 generic: true, 15576 }, 15577 { 15578 name: "Greater32U", 15579 argLen: 2, 15580 generic: true, 15581 }, 15582 { 15583 name: "Greater64", 15584 argLen: 2, 15585 generic: true, 15586 }, 15587 { 15588 name: "Greater64U", 15589 argLen: 2, 15590 generic: true, 15591 }, 15592 { 15593 name: "Greater32F", 15594 argLen: 2, 15595 generic: true, 15596 }, 15597 { 15598 name: "Greater64F", 15599 argLen: 2, 15600 generic: true, 15601 }, 15602 { 15603 name: "Geq8", 15604 argLen: 2, 15605 generic: true, 15606 }, 15607 { 15608 name: "Geq8U", 15609 argLen: 2, 15610 generic: true, 15611 }, 15612 { 15613 name: "Geq16", 15614 argLen: 2, 15615 generic: true, 15616 }, 15617 { 15618 name: "Geq16U", 15619 argLen: 2, 15620 generic: true, 15621 }, 15622 { 15623 name: "Geq32", 15624 argLen: 2, 15625 generic: true, 15626 }, 15627 { 15628 name: "Geq32U", 15629 argLen: 2, 15630 generic: true, 15631 }, 15632 { 15633 name: "Geq64", 15634 argLen: 2, 15635 generic: true, 15636 }, 15637 { 15638 name: "Geq64U", 15639 argLen: 2, 15640 generic: true, 15641 }, 15642 { 15643 name: "Geq32F", 15644 argLen: 2, 15645 generic: true, 15646 }, 15647 { 15648 name: "Geq64F", 15649 argLen: 2, 15650 generic: true, 15651 }, 15652 { 15653 name: "AndB", 15654 argLen: 2, 15655 generic: true, 15656 }, 15657 { 15658 name: "OrB", 15659 argLen: 2, 15660 generic: true, 15661 }, 15662 { 15663 name: "EqB", 15664 argLen: 2, 15665 generic: true, 15666 }, 15667 { 15668 name: "NeqB", 15669 argLen: 2, 15670 generic: true, 15671 }, 15672 { 15673 name: "Not", 15674 argLen: 1, 15675 generic: true, 15676 }, 15677 { 15678 name: "Neg8", 15679 argLen: 1, 15680 generic: true, 15681 }, 15682 { 15683 name: "Neg16", 15684 argLen: 1, 15685 generic: true, 15686 }, 15687 { 15688 name: "Neg32", 15689 argLen: 1, 15690 generic: true, 15691 }, 15692 { 15693 name: "Neg64", 15694 argLen: 1, 15695 generic: true, 15696 }, 15697 { 15698 name: "Neg32F", 15699 argLen: 1, 15700 generic: true, 15701 }, 15702 { 15703 name: "Neg64F", 15704 argLen: 1, 15705 generic: true, 15706 }, 15707 { 15708 name: "Com8", 15709 argLen: 1, 15710 generic: true, 15711 }, 15712 { 15713 name: "Com16", 15714 argLen: 1, 15715 generic: true, 15716 }, 15717 { 15718 name: "Com32", 15719 argLen: 1, 15720 generic: true, 15721 }, 15722 { 15723 name: "Com64", 15724 argLen: 1, 15725 generic: true, 15726 }, 15727 { 15728 name: "Ctz32", 15729 argLen: 1, 15730 generic: true, 15731 }, 15732 { 15733 name: "Ctz64", 15734 argLen: 1, 15735 generic: true, 15736 }, 15737 { 15738 name: "Bswap32", 15739 argLen: 1, 15740 generic: true, 15741 }, 15742 { 15743 name: "Bswap64", 15744 argLen: 1, 15745 generic: true, 15746 }, 15747 { 15748 name: "Sqrt", 15749 argLen: 1, 15750 generic: true, 15751 }, 15752 { 15753 name: "Phi", 15754 argLen: -1, 15755 generic: true, 15756 }, 15757 { 15758 name: "Copy", 15759 argLen: 1, 15760 generic: true, 15761 }, 15762 { 15763 name: "Convert", 15764 argLen: 2, 15765 generic: true, 15766 }, 15767 { 15768 name: "ConstBool", 15769 auxType: auxBool, 15770 argLen: 0, 15771 generic: true, 15772 }, 15773 { 15774 name: "ConstString", 15775 auxType: auxString, 15776 argLen: 0, 15777 generic: true, 15778 }, 15779 { 15780 name: "ConstNil", 15781 argLen: 0, 15782 generic: true, 15783 }, 15784 { 15785 name: "Const8", 15786 auxType: auxInt8, 15787 argLen: 0, 15788 generic: true, 15789 }, 15790 { 15791 name: "Const16", 15792 auxType: auxInt16, 15793 argLen: 0, 15794 generic: true, 15795 }, 15796 { 15797 name: "Const32", 15798 auxType: auxInt32, 15799 argLen: 0, 15800 generic: true, 15801 }, 15802 { 15803 name: "Const64", 15804 auxType: auxInt64, 15805 argLen: 0, 15806 generic: true, 15807 }, 15808 { 15809 name: "Const32F", 15810 auxType: auxFloat32, 15811 argLen: 0, 15812 generic: true, 15813 }, 15814 { 15815 name: "Const64F", 15816 auxType: auxFloat64, 15817 argLen: 0, 15818 generic: true, 15819 }, 15820 { 15821 name: "ConstInterface", 15822 argLen: 0, 15823 generic: true, 15824 }, 15825 { 15826 name: "ConstSlice", 15827 argLen: 0, 15828 generic: true, 15829 }, 15830 { 15831 name: "InitMem", 15832 argLen: 0, 15833 generic: true, 15834 }, 15835 { 15836 name: "Arg", 15837 auxType: auxSymOff, 15838 argLen: 0, 15839 generic: true, 15840 }, 15841 { 15842 name: "Addr", 15843 auxType: auxSym, 15844 argLen: 1, 15845 generic: true, 15846 }, 15847 { 15848 name: "SP", 15849 argLen: 0, 15850 generic: true, 15851 }, 15852 { 15853 name: "SB", 15854 argLen: 0, 15855 generic: true, 15856 }, 15857 { 15858 name: "Func", 15859 auxType: auxSym, 15860 argLen: 0, 15861 generic: true, 15862 }, 15863 { 15864 name: "Load", 15865 argLen: 2, 15866 generic: true, 15867 }, 15868 { 15869 name: "Store", 15870 auxType: auxInt64, 15871 argLen: 3, 15872 generic: true, 15873 }, 15874 { 15875 name: "Move", 15876 auxType: auxInt64, 15877 argLen: 3, 15878 generic: true, 15879 }, 15880 { 15881 name: "Zero", 15882 auxType: auxInt64, 15883 argLen: 2, 15884 generic: true, 15885 }, 15886 { 15887 name: "ClosureCall", 15888 auxType: auxInt64, 15889 argLen: 3, 15890 generic: true, 15891 }, 15892 { 15893 name: "StaticCall", 15894 auxType: auxSymOff, 15895 argLen: 1, 15896 generic: true, 15897 }, 15898 { 15899 name: "DeferCall", 15900 auxType: auxInt64, 15901 argLen: 1, 15902 generic: true, 15903 }, 15904 { 15905 name: "GoCall", 15906 auxType: auxInt64, 15907 argLen: 1, 15908 generic: true, 15909 }, 15910 { 15911 name: "InterCall", 15912 auxType: auxInt64, 15913 argLen: 2, 15914 generic: true, 15915 }, 15916 { 15917 name: "SignExt8to16", 15918 argLen: 1, 15919 generic: true, 15920 }, 15921 { 15922 name: "SignExt8to32", 15923 argLen: 1, 15924 generic: true, 15925 }, 15926 { 15927 name: "SignExt8to64", 15928 argLen: 1, 15929 generic: true, 15930 }, 15931 { 15932 name: "SignExt16to32", 15933 argLen: 1, 15934 generic: true, 15935 }, 15936 { 15937 name: "SignExt16to64", 15938 argLen: 1, 15939 generic: true, 15940 }, 15941 { 15942 name: "SignExt32to64", 15943 argLen: 1, 15944 generic: true, 15945 }, 15946 { 15947 name: "ZeroExt8to16", 15948 argLen: 1, 15949 generic: true, 15950 }, 15951 { 15952 name: "ZeroExt8to32", 15953 argLen: 1, 15954 generic: true, 15955 }, 15956 { 15957 name: "ZeroExt8to64", 15958 argLen: 1, 15959 generic: true, 15960 }, 15961 { 15962 name: "ZeroExt16to32", 15963 argLen: 1, 15964 generic: true, 15965 }, 15966 { 15967 name: "ZeroExt16to64", 15968 argLen: 1, 15969 generic: true, 15970 }, 15971 { 15972 name: "ZeroExt32to64", 15973 argLen: 1, 15974 generic: true, 15975 }, 15976 { 15977 name: "Trunc16to8", 15978 argLen: 1, 15979 generic: true, 15980 }, 15981 { 15982 name: "Trunc32to8", 15983 argLen: 1, 15984 generic: true, 15985 }, 15986 { 15987 name: "Trunc32to16", 15988 argLen: 1, 15989 generic: true, 15990 }, 15991 { 15992 name: "Trunc64to8", 15993 argLen: 1, 15994 generic: true, 15995 }, 15996 { 15997 name: "Trunc64to16", 15998 argLen: 1, 15999 generic: true, 16000 }, 16001 { 16002 name: "Trunc64to32", 16003 argLen: 1, 16004 generic: true, 16005 }, 16006 { 16007 name: "Cvt32to32F", 16008 argLen: 1, 16009 generic: true, 16010 }, 16011 { 16012 name: "Cvt32to64F", 16013 argLen: 1, 16014 generic: true, 16015 }, 16016 { 16017 name: "Cvt64to32F", 16018 argLen: 1, 16019 generic: true, 16020 }, 16021 { 16022 name: "Cvt64to64F", 16023 argLen: 1, 16024 generic: true, 16025 }, 16026 { 16027 name: "Cvt32Fto32", 16028 argLen: 1, 16029 generic: true, 16030 }, 16031 { 16032 name: "Cvt32Fto64", 16033 argLen: 1, 16034 generic: true, 16035 }, 16036 { 16037 name: "Cvt64Fto32", 16038 argLen: 1, 16039 generic: true, 16040 }, 16041 { 16042 name: "Cvt64Fto64", 16043 argLen: 1, 16044 generic: true, 16045 }, 16046 { 16047 name: "Cvt32Fto64F", 16048 argLen: 1, 16049 generic: true, 16050 }, 16051 { 16052 name: "Cvt64Fto32F", 16053 argLen: 1, 16054 generic: true, 16055 }, 16056 { 16057 name: "IsNonNil", 16058 argLen: 1, 16059 generic: true, 16060 }, 16061 { 16062 name: "IsInBounds", 16063 argLen: 2, 16064 generic: true, 16065 }, 16066 { 16067 name: "IsSliceInBounds", 16068 argLen: 2, 16069 generic: true, 16070 }, 16071 { 16072 name: "NilCheck", 16073 argLen: 2, 16074 generic: true, 16075 }, 16076 { 16077 name: "GetG", 16078 argLen: 1, 16079 generic: true, 16080 }, 16081 { 16082 name: "GetClosurePtr", 16083 argLen: 0, 16084 generic: true, 16085 }, 16086 { 16087 name: "ArrayIndex", 16088 auxType: auxInt64, 16089 argLen: 1, 16090 generic: true, 16091 }, 16092 { 16093 name: "PtrIndex", 16094 argLen: 2, 16095 generic: true, 16096 }, 16097 { 16098 name: "OffPtr", 16099 auxType: auxInt64, 16100 argLen: 1, 16101 generic: true, 16102 }, 16103 { 16104 name: "SliceMake", 16105 argLen: 3, 16106 generic: true, 16107 }, 16108 { 16109 name: "SlicePtr", 16110 argLen: 1, 16111 generic: true, 16112 }, 16113 { 16114 name: "SliceLen", 16115 argLen: 1, 16116 generic: true, 16117 }, 16118 { 16119 name: "SliceCap", 16120 argLen: 1, 16121 generic: true, 16122 }, 16123 { 16124 name: "ComplexMake", 16125 argLen: 2, 16126 generic: true, 16127 }, 16128 { 16129 name: "ComplexReal", 16130 argLen: 1, 16131 generic: true, 16132 }, 16133 { 16134 name: "ComplexImag", 16135 argLen: 1, 16136 generic: true, 16137 }, 16138 { 16139 name: "StringMake", 16140 argLen: 2, 16141 generic: true, 16142 }, 16143 { 16144 name: "StringPtr", 16145 argLen: 1, 16146 generic: true, 16147 }, 16148 { 16149 name: "StringLen", 16150 argLen: 1, 16151 generic: true, 16152 }, 16153 { 16154 name: "IMake", 16155 argLen: 2, 16156 generic: true, 16157 }, 16158 { 16159 name: "ITab", 16160 argLen: 1, 16161 generic: true, 16162 }, 16163 { 16164 name: "IData", 16165 argLen: 1, 16166 generic: true, 16167 }, 16168 { 16169 name: "StructMake0", 16170 argLen: 0, 16171 generic: true, 16172 }, 16173 { 16174 name: "StructMake1", 16175 argLen: 1, 16176 generic: true, 16177 }, 16178 { 16179 name: "StructMake2", 16180 argLen: 2, 16181 generic: true, 16182 }, 16183 { 16184 name: "StructMake3", 16185 argLen: 3, 16186 generic: true, 16187 }, 16188 { 16189 name: "StructMake4", 16190 argLen: 4, 16191 generic: true, 16192 }, 16193 { 16194 name: "StructSelect", 16195 auxType: auxInt64, 16196 argLen: 1, 16197 generic: true, 16198 }, 16199 { 16200 name: "StoreReg", 16201 argLen: 1, 16202 generic: true, 16203 }, 16204 { 16205 name: "LoadReg", 16206 argLen: 1, 16207 generic: true, 16208 }, 16209 { 16210 name: "FwdRef", 16211 auxType: auxSym, 16212 argLen: 0, 16213 generic: true, 16214 }, 16215 { 16216 name: "Unknown", 16217 argLen: 0, 16218 generic: true, 16219 }, 16220 { 16221 name: "VarDef", 16222 auxType: auxSym, 16223 argLen: 1, 16224 generic: true, 16225 }, 16226 { 16227 name: "VarKill", 16228 auxType: auxSym, 16229 argLen: 1, 16230 generic: true, 16231 }, 16232 { 16233 name: "VarLive", 16234 auxType: auxSym, 16235 argLen: 1, 16236 generic: true, 16237 }, 16238 { 16239 name: "KeepAlive", 16240 argLen: 2, 16241 generic: true, 16242 }, 16243 { 16244 name: "Int64Make", 16245 argLen: 2, 16246 generic: true, 16247 }, 16248 { 16249 name: "Int64Hi", 16250 argLen: 1, 16251 generic: true, 16252 }, 16253 { 16254 name: "Int64Lo", 16255 argLen: 1, 16256 generic: true, 16257 }, 16258 { 16259 name: "Add32carry", 16260 argLen: 2, 16261 commutative: true, 16262 generic: true, 16263 }, 16264 { 16265 name: "Add32withcarry", 16266 argLen: 3, 16267 commutative: true, 16268 generic: true, 16269 }, 16270 { 16271 name: "Sub32carry", 16272 argLen: 2, 16273 generic: true, 16274 }, 16275 { 16276 name: "Sub32withcarry", 16277 argLen: 3, 16278 generic: true, 16279 }, 16280 { 16281 name: "Mul32uhilo", 16282 argLen: 2, 16283 generic: true, 16284 }, 16285 { 16286 name: "Signmask", 16287 argLen: 1, 16288 generic: true, 16289 }, 16290 { 16291 name: "Zeromask", 16292 argLen: 1, 16293 generic: true, 16294 }, 16295 { 16296 name: "Cvt32Uto32F", 16297 argLen: 1, 16298 generic: true, 16299 }, 16300 { 16301 name: "Cvt32Uto64F", 16302 argLen: 1, 16303 generic: true, 16304 }, 16305 { 16306 name: "Cvt32Fto32U", 16307 argLen: 1, 16308 generic: true, 16309 }, 16310 { 16311 name: "Cvt64Fto32U", 16312 argLen: 1, 16313 generic: true, 16314 }, 16315 { 16316 name: "Cvt64Uto32F", 16317 argLen: 1, 16318 generic: true, 16319 }, 16320 { 16321 name: "Cvt64Uto64F", 16322 argLen: 1, 16323 generic: true, 16324 }, 16325 { 16326 name: "Cvt32Fto64U", 16327 argLen: 1, 16328 generic: true, 16329 }, 16330 { 16331 name: "Cvt64Fto64U", 16332 argLen: 1, 16333 generic: true, 16334 }, 16335 { 16336 name: "Select0", 16337 argLen: 1, 16338 generic: true, 16339 }, 16340 { 16341 name: "Select1", 16342 argLen: 1, 16343 generic: true, 16344 }, 16345 { 16346 name: "AtomicLoad32", 16347 argLen: 2, 16348 generic: true, 16349 }, 16350 { 16351 name: "AtomicLoad64", 16352 argLen: 2, 16353 generic: true, 16354 }, 16355 { 16356 name: "AtomicLoadPtr", 16357 argLen: 2, 16358 generic: true, 16359 }, 16360 { 16361 name: "AtomicStore32", 16362 argLen: 3, 16363 generic: true, 16364 }, 16365 { 16366 name: "AtomicStore64", 16367 argLen: 3, 16368 generic: true, 16369 }, 16370 { 16371 name: "AtomicStorePtrNoWB", 16372 argLen: 3, 16373 generic: true, 16374 }, 16375 { 16376 name: "AtomicExchange32", 16377 argLen: 3, 16378 generic: true, 16379 }, 16380 { 16381 name: "AtomicExchange64", 16382 argLen: 3, 16383 generic: true, 16384 }, 16385 { 16386 name: "AtomicAdd32", 16387 argLen: 3, 16388 generic: true, 16389 }, 16390 { 16391 name: "AtomicAdd64", 16392 argLen: 3, 16393 generic: true, 16394 }, 16395 { 16396 name: "AtomicCompareAndSwap32", 16397 argLen: 4, 16398 generic: true, 16399 }, 16400 { 16401 name: "AtomicCompareAndSwap64", 16402 argLen: 4, 16403 generic: true, 16404 }, 16405 { 16406 name: "AtomicAnd8", 16407 argLen: 3, 16408 generic: true, 16409 }, 16410 { 16411 name: "AtomicOr8", 16412 argLen: 3, 16413 generic: true, 16414 }, 16415 } 16416 16417 func (o Op) Asm() obj.As { return opcodeTable[o].asm } 16418 func (o Op) String() string { return opcodeTable[o].name } 16419 16420 var registers386 = [...]Register{ 16421 {0, "AX"}, 16422 {1, "CX"}, 16423 {2, "DX"}, 16424 {3, "BX"}, 16425 {4, "SP"}, 16426 {5, "BP"}, 16427 {6, "SI"}, 16428 {7, "DI"}, 16429 {8, "X0"}, 16430 {9, "X1"}, 16431 {10, "X2"}, 16432 {11, "X3"}, 16433 {12, "X4"}, 16434 {13, "X5"}, 16435 {14, "X6"}, 16436 {15, "X7"}, 16437 {16, "SB"}, 16438 } 16439 var gpRegMask386 = regMask(239) 16440 var fpRegMask386 = regMask(65280) 16441 var specialRegMask386 = regMask(0) 16442 var framepointerReg386 = int8(5) 16443 var registersAMD64 = [...]Register{ 16444 {0, "AX"}, 16445 {1, "CX"}, 16446 {2, "DX"}, 16447 {3, "BX"}, 16448 {4, "SP"}, 16449 {5, "BP"}, 16450 {6, "SI"}, 16451 {7, "DI"}, 16452 {8, "R8"}, 16453 {9, "R9"}, 16454 {10, "R10"}, 16455 {11, "R11"}, 16456 {12, "R12"}, 16457 {13, "R13"}, 16458 {14, "R14"}, 16459 {15, "R15"}, 16460 {16, "X0"}, 16461 {17, "X1"}, 16462 {18, "X2"}, 16463 {19, "X3"}, 16464 {20, "X4"}, 16465 {21, "X5"}, 16466 {22, "X6"}, 16467 {23, "X7"}, 16468 {24, "X8"}, 16469 {25, "X9"}, 16470 {26, "X10"}, 16471 {27, "X11"}, 16472 {28, "X12"}, 16473 {29, "X13"}, 16474 {30, "X14"}, 16475 {31, "X15"}, 16476 {32, "SB"}, 16477 } 16478 var gpRegMaskAMD64 = regMask(65519) 16479 var fpRegMaskAMD64 = regMask(4294901760) 16480 var specialRegMaskAMD64 = regMask(0) 16481 var framepointerRegAMD64 = int8(5) 16482 var registersARM = [...]Register{ 16483 {0, "R0"}, 16484 {1, "R1"}, 16485 {2, "R2"}, 16486 {3, "R3"}, 16487 {4, "R4"}, 16488 {5, "R5"}, 16489 {6, "R6"}, 16490 {7, "R7"}, 16491 {8, "R8"}, 16492 {9, "R9"}, 16493 {10, "g"}, 16494 {11, "R11"}, 16495 {12, "R12"}, 16496 {13, "SP"}, 16497 {14, "R14"}, 16498 {15, "R15"}, 16499 {16, "F0"}, 16500 {17, "F1"}, 16501 {18, "F2"}, 16502 {19, "F3"}, 16503 {20, "F4"}, 16504 {21, "F5"}, 16505 {22, "F6"}, 16506 {23, "F7"}, 16507 {24, "F8"}, 16508 {25, "F9"}, 16509 {26, "F10"}, 16510 {27, "F11"}, 16511 {28, "F12"}, 16512 {29, "F13"}, 16513 {30, "F14"}, 16514 {31, "F15"}, 16515 {32, "SB"}, 16516 } 16517 var gpRegMaskARM = regMask(5119) 16518 var fpRegMaskARM = regMask(4294901760) 16519 var specialRegMaskARM = regMask(0) 16520 var framepointerRegARM = int8(-1) 16521 var registersARM64 = [...]Register{ 16522 {0, "R0"}, 16523 {1, "R1"}, 16524 {2, "R2"}, 16525 {3, "R3"}, 16526 {4, "R4"}, 16527 {5, "R5"}, 16528 {6, "R6"}, 16529 {7, "R7"}, 16530 {8, "R8"}, 16531 {9, "R9"}, 16532 {10, "R10"}, 16533 {11, "R11"}, 16534 {12, "R12"}, 16535 {13, "R13"}, 16536 {14, "R14"}, 16537 {15, "R15"}, 16538 {16, "R16"}, 16539 {17, "R17"}, 16540 {18, "R18"}, 16541 {19, "R19"}, 16542 {20, "R20"}, 16543 {21, "R21"}, 16544 {22, "R22"}, 16545 {23, "R23"}, 16546 {24, "R24"}, 16547 {25, "R25"}, 16548 {26, "R26"}, 16549 {27, "g"}, 16550 {28, "R29"}, 16551 {29, "SP"}, 16552 {30, "F0"}, 16553 {31, "F1"}, 16554 {32, "F2"}, 16555 {33, "F3"}, 16556 {34, "F4"}, 16557 {35, "F5"}, 16558 {36, "F6"}, 16559 {37, "F7"}, 16560 {38, "F8"}, 16561 {39, "F9"}, 16562 {40, "F10"}, 16563 {41, "F11"}, 16564 {42, "F12"}, 16565 {43, "F13"}, 16566 {44, "F14"}, 16567 {45, "F15"}, 16568 {46, "F16"}, 16569 {47, "F17"}, 16570 {48, "F18"}, 16571 {49, "F19"}, 16572 {50, "F20"}, 16573 {51, "F21"}, 16574 {52, "F22"}, 16575 {53, "F23"}, 16576 {54, "F24"}, 16577 {55, "F25"}, 16578 {56, "F26"}, 16579 {57, "F27"}, 16580 {58, "F28"}, 16581 {59, "F29"}, 16582 {60, "F30"}, 16583 {61, "F31"}, 16584 {62, "SB"}, 16585 } 16586 var gpRegMaskARM64 = regMask(133955583) 16587 var fpRegMaskARM64 = regMask(288230375077969920) 16588 var specialRegMaskARM64 = regMask(0) 16589 var framepointerRegARM64 = int8(-1) 16590 var registersMIPS64 = [...]Register{ 16591 {0, "R0"}, 16592 {1, "R1"}, 16593 {2, "R2"}, 16594 {3, "R3"}, 16595 {4, "R4"}, 16596 {5, "R5"}, 16597 {6, "R6"}, 16598 {7, "R7"}, 16599 {8, "R8"}, 16600 {9, "R9"}, 16601 {10, "R10"}, 16602 {11, "R11"}, 16603 {12, "R12"}, 16604 {13, "R13"}, 16605 {14, "R14"}, 16606 {15, "R15"}, 16607 {16, "R16"}, 16608 {17, "R17"}, 16609 {18, "R18"}, 16610 {19, "R19"}, 16611 {20, "R20"}, 16612 {21, "R21"}, 16613 {22, "R22"}, 16614 {23, "R24"}, 16615 {24, "R25"}, 16616 {25, "SP"}, 16617 {26, "g"}, 16618 {27, "F0"}, 16619 {28, "F1"}, 16620 {29, "F2"}, 16621 {30, "F3"}, 16622 {31, "F4"}, 16623 {32, "F5"}, 16624 {33, "F6"}, 16625 {34, "F7"}, 16626 {35, "F8"}, 16627 {36, "F9"}, 16628 {37, "F10"}, 16629 {38, "F11"}, 16630 {39, "F12"}, 16631 {40, "F13"}, 16632 {41, "F14"}, 16633 {42, "F15"}, 16634 {43, "F16"}, 16635 {44, "F17"}, 16636 {45, "F18"}, 16637 {46, "F19"}, 16638 {47, "F20"}, 16639 {48, "F21"}, 16640 {49, "F22"}, 16641 {50, "F23"}, 16642 {51, "F24"}, 16643 {52, "F25"}, 16644 {53, "F26"}, 16645 {54, "F27"}, 16646 {55, "F28"}, 16647 {56, "F29"}, 16648 {57, "F30"}, 16649 {58, "F31"}, 16650 {59, "HI"}, 16651 {60, "LO"}, 16652 {61, "SB"}, 16653 } 16654 var gpRegMaskMIPS64 = regMask(33554430) 16655 var fpRegMaskMIPS64 = regMask(385057768005959680) 16656 var specialRegMaskMIPS64 = regMask(1729382256910270464) 16657 var framepointerRegMIPS64 = int8(-1) 16658 var registersPPC64 = [...]Register{ 16659 {0, "SP"}, 16660 {1, "SB"}, 16661 {2, "R3"}, 16662 {3, "R4"}, 16663 {4, "R5"}, 16664 {5, "R6"}, 16665 {6, "R7"}, 16666 {7, "R8"}, 16667 {8, "R9"}, 16668 {9, "R10"}, 16669 {10, "R11"}, 16670 {11, "R12"}, 16671 {12, "R13"}, 16672 {13, "R14"}, 16673 {14, "R15"}, 16674 {15, "R16"}, 16675 {16, "R17"}, 16676 {17, "R18"}, 16677 {18, "R19"}, 16678 {19, "R20"}, 16679 {20, "R21"}, 16680 {21, "R22"}, 16681 {22, "R23"}, 16682 {23, "R24"}, 16683 {24, "R25"}, 16684 {25, "R26"}, 16685 {26, "R27"}, 16686 {27, "R28"}, 16687 {28, "R29"}, 16688 {29, "g"}, 16689 {30, "R31"}, 16690 {31, "F0"}, 16691 {32, "F1"}, 16692 {33, "F2"}, 16693 {34, "F3"}, 16694 {35, "F4"}, 16695 {36, "F5"}, 16696 {37, "F6"}, 16697 {38, "F7"}, 16698 {39, "F8"}, 16699 {40, "F9"}, 16700 {41, "F10"}, 16701 {42, "F11"}, 16702 {43, "F12"}, 16703 {44, "F13"}, 16704 {45, "F14"}, 16705 {46, "F15"}, 16706 {47, "F16"}, 16707 {48, "F17"}, 16708 {49, "F18"}, 16709 {50, "F19"}, 16710 {51, "F20"}, 16711 {52, "F21"}, 16712 {53, "F22"}, 16713 {54, "F23"}, 16714 {55, "F24"}, 16715 {56, "F25"}, 16716 {57, "F26"}, 16717 } 16718 var gpRegMaskPPC64 = regMask(536866812) 16719 var fpRegMaskPPC64 = regMask(288230371856744448) 16720 var specialRegMaskPPC64 = regMask(0) 16721 var framepointerRegPPC64 = int8(0)