github.com/euank/go@v0.0.0-20160829210321-495514729181/src/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167 ) 168 169 // Not registers, but flags that can be combined with regular register 170 // constants to indicate extended register conversion. When checking, 171 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 172 // indicates extended register, bits 8-10 select the conversion mode. 173 const REG_EXT = obj.RBaseARM64 + 1<<11 174 175 const ( 176 REG_UXTB = REG_EXT + iota<<8 177 REG_UXTH 178 REG_UXTW 179 REG_UXTX 180 REG_SXTB 181 REG_SXTH 182 REG_SXTW 183 REG_SXTX 184 ) 185 186 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 187 // a special register and the low bits select the register. 188 const ( 189 REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota 190 REG_DAIF 191 REG_NZCV 192 REG_FPSR 193 REG_FPCR 194 REG_SPSR_EL1 195 REG_ELR_EL1 196 REG_SPSR_EL2 197 REG_ELR_EL2 198 REG_CurrentEL 199 REG_SP_EL0 200 REG_SPSel 201 REG_DAIFSet 202 REG_DAIFClr 203 ) 204 205 // Register assignments: 206 // 207 // compiler allocates R0 up as temps 208 // compiler allocates register variables R7-R25 209 // compiler allocates external registers R26 down 210 // 211 // compiler allocates register variables F7-F26 212 // compiler allocates external registers F26 down 213 const ( 214 REGMIN = REG_R7 // register variables allocated from here to REGMAX 215 REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy 216 REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy 217 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 218 REGMAX = REG_R25 219 220 REGCTXT = REG_R26 // environment for closures 221 REGTMP = REG_R27 // reserved for liblink 222 REGG = REG_R28 // G 223 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 224 REGLINK = REG_R30 225 226 // ARM64 uses R31 as both stack pointer and zero register, 227 // depending on the instruction. To differentiate RSP from ZR, 228 // we use a different numeric value for REGZERO and REGSP. 229 REGZERO = REG_R31 230 REGSP = REG_RSP 231 232 FREGRET = REG_F0 233 FREGMIN = REG_F7 // first register variable 234 FREGMAX = REG_F26 // last register variable for 7g only 235 FREGEXT = REG_F26 // first external register 236 FREGZERO = REG_F28 // both float and double 237 FREGHALF = REG_F29 // double 238 FREGONE = REG_F30 // double 239 FREGTWO = REG_F31 // double 240 ) 241 242 const ( 243 BIG = 2048 - 8 244 ) 245 246 const ( 247 /* mark flags */ 248 LABEL = 1 << iota 249 LEAF 250 FLOAT 251 BRANCH 252 LOAD 253 FCMP 254 SYNC 255 LIST 256 FOLL 257 NOSCHED 258 ) 259 260 const ( 261 C_NONE = iota 262 C_REG // R0..R30 263 C_RSP // R0..R30, RSP 264 C_FREG // F0..F31 265 C_VREG // V0..V31 266 C_PAIR // (Rn, Rm) 267 C_SHIFT // Rn<<2 268 C_EXTREG // Rn.UXTB<<3 269 C_SPR // REG_NZCV 270 C_COND // EQ, NE, etc 271 272 C_ZCON // $0 or ZR 273 C_ADDCON0 // 12-bit unsigned, unshifted 274 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 275 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 276 C_BITCON // bitfield and logical immediate masks 277 C_ABCON0 // could be C_ADDCON0 or C_BITCON 278 C_ABCON // could be C_ADDCON or C_BITCON 279 C_MBCON // could be C_MOVCON or C_BITCON 280 C_LCON // 32-bit constant 281 C_VCON // 64-bit constant 282 C_FCON // floating-point constant 283 C_VCONADDR // 64-bit memory address 284 285 C_AACON // ADDCON offset in auto constant $a(FP) 286 C_LACON // 32-bit offset in auto constant $a(FP) 287 C_AECON // ADDCON offset in extern constant $e(SB) 288 289 // TODO(aram): only one branch class should be enough 290 C_SBRA // for TYPE_BRANCH 291 C_LBRA 292 293 C_NPAUTO // -512 <= x < 0, 0 mod 8 294 C_NSAUTO // -256 <= x < 0 295 C_PSAUTO // 0 to 255 296 C_PPAUTO // 0 to 504, 0 mod 8 297 C_UAUTO4K // 0 to 4095 298 C_UAUTO8K // 0 to 8190, 0 mod 2 299 C_UAUTO16K // 0 to 16380, 0 mod 4 300 C_UAUTO32K // 0 to 32760, 0 mod 8 301 C_UAUTO64K // 0 to 65520, 0 mod 16 302 C_LAUTO // any other 32-bit constant 303 304 C_SEXT1 // 0 to 4095, direct 305 C_SEXT2 // 0 to 8190 306 C_SEXT4 // 0 to 16380 307 C_SEXT8 // 0 to 32760 308 C_SEXT16 // 0 to 65520 309 C_LEXT 310 311 // TODO(aram): s/AUTO/INDIR/ 312 C_ZOREG // 0(R) 313 C_NPOREG // mirror NPAUTO, etc 314 C_NSOREG 315 C_PSOREG 316 C_PPOREG 317 C_UOREG4K 318 C_UOREG8K 319 C_UOREG16K 320 C_UOREG32K 321 C_UOREG64K 322 C_LOREG 323 324 C_ADDR // TODO(aram): explain difference from C_VCONADDR 325 326 // The GOT slot for a symbol in -dynlink mode. 327 C_GOTADDR 328 329 // TLS "var" in local exec mode: will become a constant offset from 330 // thread local base that is ultimately chosen by the program linker. 331 C_TLS_LE 332 333 // TLS "var" in initial exec mode: will become a memory address (chosen 334 // by the program linker) that the dynamic linker will fill with the 335 // offset from the thread local base. 336 C_TLS_IE 337 338 C_ROFF // register offset (including register extended) 339 340 C_GOK 341 C_TEXTSIZE 342 C_NCLASS // must be last 343 ) 344 345 const ( 346 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 347 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 348 ) 349 350 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 351 352 const ( 353 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 354 AADCS 355 AADCSW 356 AADCW 357 AADD 358 AADDS 359 AADDSW 360 AADDW 361 AADR 362 AADRP 363 AAND 364 AANDS 365 AANDSW 366 AANDW 367 AASR 368 AASRW 369 AAT 370 ABFI 371 ABFIW 372 ABFM 373 ABFMW 374 ABFXIL 375 ABFXILW 376 ABIC 377 ABICS 378 ABICSW 379 ABICW 380 ABRK 381 ACBNZ 382 ACBNZW 383 ACBZ 384 ACBZW 385 ACCMN 386 ACCMNW 387 ACCMP 388 ACCMPW 389 ACINC 390 ACINCW 391 ACINV 392 ACINVW 393 ACLREX 394 ACLS 395 ACLSW 396 ACLZ 397 ACLZW 398 ACMN 399 ACMNW 400 ACMP 401 ACMPW 402 ACNEG 403 ACNEGW 404 ACRC32B 405 ACRC32CB 406 ACRC32CH 407 ACRC32CW 408 ACRC32CX 409 ACRC32H 410 ACRC32W 411 ACRC32X 412 ACSEL 413 ACSELW 414 ACSET 415 ACSETM 416 ACSETMW 417 ACSETW 418 ACSINC 419 ACSINCW 420 ACSINV 421 ACSINVW 422 ACSNEG 423 ACSNEGW 424 ADC 425 ADCPS1 426 ADCPS2 427 ADCPS3 428 ADMB 429 ADRPS 430 ADSB 431 AEON 432 AEONW 433 AEOR 434 AEORW 435 AERET 436 AEXTR 437 AEXTRW 438 AHINT 439 AHLT 440 AHVC 441 AIC 442 AISB 443 ALDAR 444 ALDARB 445 ALDARH 446 ALDARW 447 ALDAXP 448 ALDAXPW 449 ALDAXR 450 ALDAXRB 451 ALDAXRH 452 ALDAXRW 453 ALDP 454 ALDXR 455 ALDXRB 456 ALDXRH 457 ALDXRW 458 ALDXP 459 ALDXPW 460 ALSL 461 ALSLW 462 ALSR 463 ALSRW 464 AMADD 465 AMADDW 466 AMNEG 467 AMNEGW 468 AMOVK 469 AMOVKW 470 AMOVN 471 AMOVNW 472 AMOVZ 473 AMOVZW 474 AMRS 475 AMSR 476 AMSUB 477 AMSUBW 478 AMUL 479 AMULW 480 AMVN 481 AMVNW 482 ANEG 483 ANEGS 484 ANEGSW 485 ANEGW 486 ANGC 487 ANGCS 488 ANGCSW 489 ANGCW 490 AORN 491 AORNW 492 AORR 493 AORRW 494 APRFM 495 APRFUM 496 ARBIT 497 ARBITW 498 AREM 499 AREMW 500 AREV 501 AREV16 502 AREV16W 503 AREV32 504 AREVW 505 AROR 506 ARORW 507 ASBC 508 ASBCS 509 ASBCSW 510 ASBCW 511 ASBFIZ 512 ASBFIZW 513 ASBFM 514 ASBFMW 515 ASBFX 516 ASBFXW 517 ASDIV 518 ASDIVW 519 ASEV 520 ASEVL 521 ASMADDL 522 ASMC 523 ASMNEGL 524 ASMSUBL 525 ASMULH 526 ASMULL 527 ASTXR 528 ASTXRB 529 ASTXRH 530 ASTXP 531 ASTXPW 532 ASTXRW 533 ASTLP 534 ASTLPW 535 ASTLR 536 ASTLRB 537 ASTLRH 538 ASTLRW 539 ASTLXP 540 ASTLXPW 541 ASTLXR 542 ASTLXRB 543 ASTLXRH 544 ASTLXRW 545 ASTP 546 ASUB 547 ASUBS 548 ASUBSW 549 ASUBW 550 ASVC 551 ASXTB 552 ASXTBW 553 ASXTH 554 ASXTHW 555 ASXTW 556 ASYS 557 ASYSL 558 ATBNZ 559 ATBZ 560 ATLBI 561 ATST 562 ATSTW 563 AUBFIZ 564 AUBFIZW 565 AUBFM 566 AUBFMW 567 AUBFX 568 AUBFXW 569 AUDIV 570 AUDIVW 571 AUMADDL 572 AUMNEGL 573 AUMSUBL 574 AUMULH 575 AUMULL 576 AUREM 577 AUREMW 578 AUXTB 579 AUXTH 580 AUXTW 581 AUXTBW 582 AUXTHW 583 AWFE 584 AWFI 585 AYIELD 586 AMOVB 587 AMOVBU 588 AMOVH 589 AMOVHU 590 AMOVW 591 AMOVWU 592 AMOVD 593 AMOVNP 594 AMOVNPW 595 AMOVP 596 AMOVPD 597 AMOVPQ 598 AMOVPS 599 AMOVPSW 600 AMOVPW 601 ABEQ 602 ABNE 603 ABCS 604 ABHS 605 ABCC 606 ABLO 607 ABMI 608 ABPL 609 ABVS 610 ABVC 611 ABHI 612 ABLS 613 ABGE 614 ABLT 615 ABGT 616 ABLE 617 AFABSD 618 AFABSS 619 AFADDD 620 AFADDS 621 AFCCMPD 622 AFCCMPED 623 AFCCMPS 624 AFCCMPES 625 AFCMPD 626 AFCMPED 627 AFCMPES 628 AFCMPS 629 AFCVTSD 630 AFCVTDS 631 AFCVTZSD 632 AFCVTZSDW 633 AFCVTZSS 634 AFCVTZSSW 635 AFCVTZUD 636 AFCVTZUDW 637 AFCVTZUS 638 AFCVTZUSW 639 AFDIVD 640 AFDIVS 641 AFMOVD 642 AFMOVS 643 AFMULD 644 AFMULS 645 AFNEGD 646 AFNEGS 647 AFSQRTD 648 AFSQRTS 649 AFSUBD 650 AFSUBS 651 ASCVTFD 652 ASCVTFS 653 ASCVTFWD 654 ASCVTFWS 655 AUCVTFD 656 AUCVTFS 657 AUCVTFWD 658 AUCVTFWS 659 AWORD 660 ADWORD 661 AFCSELS 662 AFCSELD 663 AFMAXS 664 AFMINS 665 AFMAXD 666 AFMIND 667 AFMAXNMS 668 AFMAXNMD 669 AFNMULS 670 AFNMULD 671 AFRINTNS 672 AFRINTND 673 AFRINTPS 674 AFRINTPD 675 AFRINTMS 676 AFRINTMD 677 AFRINTZS 678 AFRINTZD 679 AFRINTAS 680 AFRINTAD 681 AFRINTXS 682 AFRINTXD 683 AFRINTIS 684 AFRINTID 685 AFMADDS 686 AFMADDD 687 AFMSUBS 688 AFMSUBD 689 AFNMADDS 690 AFNMADDD 691 AFNMSUBS 692 AFNMSUBD 693 AFMINNMS 694 AFMINNMD 695 AFCVTDH 696 AFCVTHS 697 AFCVTHD 698 AFCVTSH 699 AAESD 700 AAESE 701 AAESIMC 702 AAESMC 703 ASHA1C 704 ASHA1H 705 ASHA1M 706 ASHA1P 707 ASHA1SU0 708 ASHA1SU1 709 ASHA256H 710 ASHA256H2 711 ASHA256SU0 712 ASHA256SU1 713 ALAST 714 AB = obj.AJMP 715 ABL = obj.ACALL 716 ) 717 718 const ( 719 // shift types 720 SHIFT_LL = 0 << 22 721 SHIFT_LR = 1 << 22 722 SHIFT_AR = 2 << 22 723 )