github.com/euank/go@v0.0.0-20160829210321-495514729181/src/cmd/internal/obj/s390x/asmz.go (about) 1 // Based on cmd/internal/obj/ppc64/asm9.go. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package s390x 31 32 import ( 33 "cmd/internal/obj" 34 "log" 35 "math" 36 "sort" 37 ) 38 39 // instruction layout. 40 const ( 41 FuncAlign = 16 42 ) 43 44 type Optab struct { 45 as obj.As // opcode 46 a1 uint8 // From 47 a2 uint8 // Reg 48 a3 uint8 // From3 49 a4 uint8 // To 50 type_ int8 51 param int16 // REGSP for auto variables 52 } 53 54 var optab = []Optab{ 55 // instruction, From, Reg, From3, To, type, param 56 Optab{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0}, 57 Optab{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0}, 58 59 // move register 60 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 61 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 62 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 63 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 64 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 65 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 1, 0}, 66 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_REG, 1, 0}, 67 68 // load constant 69 Optab{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 70 Optab{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 71 Optab{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, REGSP}, 72 Optab{AMOVD, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 73 Optab{AMOVW, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 74 Optab{AMOVWZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 75 Optab{AMOVB, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 76 Optab{AMOVBZ, C_DCON, C_NONE, C_NONE, C_REG, 3, 0}, 77 78 // store constant 79 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_ADDR, 73, 0}, 80 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 81 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 82 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 83 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 84 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_ADDR, 73, 0}, 85 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 86 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 87 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 88 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 89 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 90 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LAUTO, 72, REGSP}, 91 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_LOREG, 72, 0}, 92 Optab{AMOVD, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 93 Optab{AMOVW, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 94 Optab{AMOVWZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 95 Optab{AMOVB, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 96 Optab{AMOVBZ, C_LCON, C_NONE, C_NONE, C_LOREG, 72, 0}, 97 98 // store 99 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 100 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 101 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 102 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 103 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 104 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 105 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 106 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 107 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 108 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 109 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 110 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 111 Optab{AMOVDBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 112 Optab{AMOVHBR, C_REG, C_NONE, C_NONE, C_LOREG, 35, 0}, 113 Optab{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 114 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 115 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 116 Optab{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 117 Optab{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 0}, 118 119 // load 120 Optab{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 121 Optab{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 122 Optab{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 123 Optab{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 124 Optab{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 125 Optab{AMOVDBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 126 Optab{AMOVHBR, C_LAUTO, C_NONE, C_NONE, C_REG, 36, REGSP}, 127 Optab{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 128 Optab{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 129 Optab{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 130 Optab{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 131 Optab{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 132 Optab{AMOVDBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 133 Optab{AMOVHBR, C_LOREG, C_NONE, C_NONE, C_REG, 36, 0}, 134 Optab{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 135 Optab{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 136 Optab{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 137 Optab{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 138 Optab{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 75, 0}, 139 140 // interlocked load and op 141 Optab{ALAAG, C_REG, C_REG, C_NONE, C_LOREG, 99, 0}, 142 143 // integer arithmetic 144 Optab{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 145 Optab{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 146 Optab{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 0}, 147 Optab{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 0}, 148 Optab{AMULHD, C_REG, C_NONE, C_NONE, C_REG, 4, 0}, 149 Optab{AMULHD, C_REG, C_REG, C_NONE, C_REG, 4, 0}, 150 Optab{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 151 Optab{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 152 Optab{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 0}, 153 Optab{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 0}, 154 Optab{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 0}, 155 Optab{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 0}, 156 Optab{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 157 Optab{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 0}, 158 Optab{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 0}, 159 160 // integer logical 161 Optab{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 162 Optab{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 163 Optab{AAND, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 164 Optab{AAND, C_LCON, C_REG, C_NONE, C_REG, 23, 0}, 165 Optab{AOR, C_REG, C_REG, C_NONE, C_REG, 6, 0}, 166 Optab{AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 0}, 167 Optab{AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 0}, 168 Optab{AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 0}, 169 Optab{ASLD, C_REG, C_NONE, C_NONE, C_REG, 7, 0}, 170 Optab{ASLD, C_REG, C_REG, C_NONE, C_REG, 7, 0}, 171 Optab{ASLD, C_SCON, C_REG, C_NONE, C_REG, 7, 0}, 172 Optab{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 7, 0}, 173 174 // compare and swap 175 Optab{ACSG, C_REG, C_REG, C_NONE, C_SOREG, 79, 0}, 176 177 // floating point 178 Optab{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 0}, 179 Optab{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 0}, 180 Optab{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 0}, 181 Optab{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 0}, 182 Optab{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 0}, 183 Optab{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 0}, 184 Optab{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 0}, 185 Optab{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, REGSP}, 186 Optab{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 0}, 187 Optab{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 0}, 188 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, REGSP}, 189 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 0}, 190 Optab{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 0}, 191 Optab{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 67, 0}, 192 Optab{ACEFBRA, C_REG, C_NONE, C_NONE, C_FREG, 82, 0}, 193 Optab{ACFEBRA, C_FREG, C_NONE, C_NONE, C_REG, 83, 0}, 194 Optab{AFIEBR, C_SCON, C_FREG, C_NONE, C_FREG, 48, 0}, 195 196 // load symbol address (plus offset) 197 Optab{AMOVD, C_SYMADDR, C_NONE, C_NONE, C_REG, 19, 0}, 198 Optab{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 93, 0}, 199 Optab{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 94, 0}, 200 Optab{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 95, 0}, 201 202 // system call 203 Optab{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 0}, 204 Optab{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 0}, 205 206 // branch 207 Optab{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 0}, 208 Optab{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 0}, 209 Optab{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 16, 0}, 210 Optab{ABR, C_NONE, C_NONE, C_NONE, C_REG, 18, 0}, 211 Optab{ABR, C_REG, C_NONE, C_NONE, C_REG, 18, 0}, 212 Optab{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 213 Optab{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 0}, 214 Optab{ACMPBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 215 Optab{ACMPBEQ, C_REG, C_NONE, C_ADDCON, C_SBRA, 90, 0}, 216 Optab{ACMPBEQ, C_REG, C_NONE, C_SCON, C_SBRA, 90, 0}, 217 Optab{ACMPUBEQ, C_REG, C_REG, C_NONE, C_SBRA, 89, 0}, 218 Optab{ACMPUBEQ, C_REG, C_NONE, C_ANDCON, C_SBRA, 90, 0}, 219 220 // compare 221 Optab{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 222 Optab{ACMP, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 223 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 0}, 224 Optab{ACMPU, C_REG, C_NONE, C_NONE, C_LCON, 71, 0}, 225 Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0}, 226 Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0}, 227 228 // 32-bit access registers 229 Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 230 Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0}, 231 Optab{AMOVW, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 232 Optab{AMOVWZ, C_REG, C_NONE, C_NONE, C_AREG, 69, 0}, 233 234 // macros 235 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LOREG, 96, 0}, 236 Optab{ACLEAR, C_LCON, C_NONE, C_NONE, C_LAUTO, 96, REGSP}, 237 238 // load/store multiple 239 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LOREG, 97, 0}, 240 Optab{ASTMG, C_REG, C_REG, C_NONE, C_LAUTO, 97, REGSP}, 241 Optab{ALMG, C_LOREG, C_REG, C_NONE, C_REG, 98, 0}, 242 Optab{ALMG, C_LAUTO, C_REG, C_NONE, C_REG, 98, REGSP}, 243 244 // bytes 245 Optab{ABYTE, C_SCON, C_NONE, C_NONE, C_NONE, 40, 0}, 246 Optab{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 0}, 247 Optab{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 0}, 248 Optab{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 0}, 249 250 // fast synchronization 251 Optab{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 81, 0}, 252 253 // store clock 254 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SAUTO, 88, REGSP}, 255 Optab{ASTCK, C_NONE, C_NONE, C_NONE, C_SOREG, 88, 0}, 256 257 // storage and storage 258 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LOREG, 84, 0}, 259 Optab{AMVC, C_LOREG, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 260 Optab{AMVC, C_LAUTO, C_NONE, C_SCON, C_LAUTO, 84, REGSP}, 261 262 // address 263 Optab{ALARL, C_LCON, C_NONE, C_NONE, C_REG, 85, 0}, 264 Optab{ALARL, C_SYMADDR, C_NONE, C_NONE, C_REG, 85, 0}, 265 Optab{ALA, C_SOREG, C_NONE, C_NONE, C_REG, 86, 0}, 266 Optab{ALA, C_SAUTO, C_NONE, C_NONE, C_REG, 86, REGSP}, 267 Optab{AEXRL, C_SYMADDR, C_NONE, C_NONE, C_REG, 87, 0}, 268 269 // misc 270 Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 0}, 271 Optab{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0}, 272 Optab{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0}, 273 Optab{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0}, 274 Optab{obj.ANOP, C_SAUTO, C_NONE, C_NONE, C_NONE, 0, 0}, 275 276 // vector instructions 277 278 // VRX store 279 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SOREG, 100, 0}, 280 Optab{AVST, C_VREG, C_NONE, C_NONE, C_SAUTO, 100, REGSP}, 281 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SOREG, 100, 0}, 282 Optab{AVSTEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 100, REGSP}, 283 284 // VRX load 285 Optab{AVL, C_SOREG, C_NONE, C_NONE, C_VREG, 101, 0}, 286 Optab{AVL, C_SAUTO, C_NONE, C_NONE, C_VREG, 101, REGSP}, 287 Optab{AVLEG, C_SOREG, C_NONE, C_SCON, C_VREG, 101, 0}, 288 Optab{AVLEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 101, REGSP}, 289 290 // VRV scatter 291 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SOREG, 102, 0}, 292 Optab{AVSCEG, C_VREG, C_NONE, C_SCON, C_SAUTO, 102, REGSP}, 293 294 // VRV gather 295 Optab{AVGEG, C_SOREG, C_NONE, C_SCON, C_VREG, 103, 0}, 296 Optab{AVGEG, C_SAUTO, C_NONE, C_SCON, C_VREG, 103, REGSP}, 297 298 // VRS element shift/rotate and load gr to/from vr element 299 Optab{AVESLG, C_SCON, C_VREG, C_NONE, C_VREG, 104, 0}, 300 Optab{AVESLG, C_REG, C_VREG, C_NONE, C_VREG, 104, 0}, 301 Optab{AVESLG, C_SCON, C_NONE, C_NONE, C_VREG, 104, 0}, 302 Optab{AVESLG, C_REG, C_NONE, C_NONE, C_VREG, 104, 0}, 303 Optab{AVLGVG, C_SCON, C_VREG, C_NONE, C_REG, 104, 0}, 304 Optab{AVLGVG, C_REG, C_VREG, C_NONE, C_REG, 104, 0}, 305 Optab{AVLVGG, C_SCON, C_REG, C_NONE, C_VREG, 104, 0}, 306 Optab{AVLVGG, C_REG, C_REG, C_NONE, C_VREG, 104, 0}, 307 308 // VRS store multiple 309 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SOREG, 105, 0}, 310 Optab{AVSTM, C_VREG, C_VREG, C_NONE, C_SAUTO, 105, REGSP}, 311 312 // VRS load multiple 313 Optab{AVLM, C_SOREG, C_VREG, C_NONE, C_VREG, 106, 0}, 314 Optab{AVLM, C_SAUTO, C_VREG, C_NONE, C_VREG, 106, REGSP}, 315 316 // VRS store with length 317 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SOREG, 107, 0}, 318 Optab{AVSTL, C_VREG, C_NONE, C_REG, C_SAUTO, 107, REGSP}, 319 320 // VRS load with length 321 Optab{AVLL, C_SOREG, C_NONE, C_REG, C_VREG, 108, 0}, 322 Optab{AVLL, C_SAUTO, C_NONE, C_REG, C_VREG, 108, REGSP}, 323 324 // VRI-a 325 Optab{AVGBM, C_ANDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 326 Optab{AVZERO, C_NONE, C_NONE, C_NONE, C_VREG, 109, 0}, 327 Optab{AVREPIG, C_ADDCON, C_NONE, C_NONE, C_VREG, 109, 0}, 328 Optab{AVREPIG, C_SCON, C_NONE, C_NONE, C_VREG, 109, 0}, 329 Optab{AVLEIG, C_ADDCON, C_NONE, C_SCON, C_VREG, 109, 0}, 330 Optab{AVLEIG, C_SCON, C_NONE, C_SCON, C_VREG, 109, 0}, 331 332 // VRI-b generate mask 333 Optab{AVGMG, C_SCON, C_NONE, C_SCON, C_VREG, 110, 0}, 334 335 // VRI-c replicate 336 Optab{AVREPG, C_UCON, C_VREG, C_NONE, C_VREG, 111, 0}, 337 338 // VRI-d element rotate and insert under mask and 339 // shift left double by byte 340 Optab{AVERIMG, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 341 Optab{AVSLDB, C_VREG, C_VREG, C_SCON, C_VREG, 112, 0}, 342 343 // VRI-d fp test data class immediate 344 Optab{AVFTCIDB, C_SCON, C_VREG, C_NONE, C_VREG, 113, 0}, 345 346 // VRR-a load reg 347 Optab{AVLR, C_VREG, C_NONE, C_NONE, C_VREG, 114, 0}, 348 349 // VRR-a compare 350 Optab{AVECG, C_VREG, C_NONE, C_NONE, C_VREG, 115, 0}, 351 352 // VRR-b 353 Optab{AVCEQG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 354 Optab{AVFAEF, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 355 Optab{AVPKSG, C_VREG, C_VREG, C_NONE, C_VREG, 117, 0}, 356 357 // VRR-c 358 Optab{AVAQ, C_VREG, C_VREG, C_NONE, C_VREG, 118, 0}, 359 Optab{AVAQ, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 360 Optab{AVNOT, C_VREG, C_NONE, C_NONE, C_VREG, 118, 0}, 361 Optab{AVPDI, C_VREG, C_VREG, C_SCON, C_VREG, 123, 0}, 362 363 // VRR-c shifts 364 Optab{AVERLLVG, C_VREG, C_VREG, C_NONE, C_VREG, 119, 0}, 365 Optab{AVERLLVG, C_VREG, C_NONE, C_NONE, C_VREG, 119, 0}, 366 367 // VRR-d 368 // 2 3 1 4 369 Optab{AVACQ, C_VREG, C_VREG, C_VREG, C_VREG, 120, 0}, 370 371 // VRR-e 372 Optab{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 121, 0}, 373 374 // VRR-f 375 Optab{AVLVGP, C_REG, C_REG, C_NONE, C_VREG, 122, 0}, 376 } 377 378 var oprange [ALAST & obj.AMask][]Optab 379 380 var xcmp [C_NCLASS][C_NCLASS]bool 381 382 func spanz(ctxt *obj.Link, cursym *obj.LSym) { 383 p := cursym.Text 384 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 385 return 386 } 387 ctxt.Cursym = cursym 388 ctxt.Autosize = int32(p.To.Offset) 389 390 if oprange[AANDN&obj.AMask] == nil { 391 buildop(ctxt) 392 } 393 394 buffer := make([]byte, 0) 395 changed := true 396 loop := 0 397 for changed { 398 if loop > 10 { 399 ctxt.Diag("stuck in spanz loop") 400 break 401 } 402 changed = false 403 buffer = buffer[:0] 404 ctxt.Cursym.R = make([]obj.Reloc, 0) 405 for p := cursym.Text; p != nil; p = p.Link { 406 pc := int64(len(buffer)) 407 if pc != p.Pc { 408 changed = true 409 } 410 p.Pc = pc 411 ctxt.Pc = p.Pc 412 ctxt.Curp = p 413 asmout(ctxt, &buffer) 414 if pc == int64(len(buffer)) { 415 switch p.As { 416 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT: 417 // ok 418 default: 419 ctxt.Diag("zero-width instruction\n%v", p) 420 } 421 } 422 } 423 loop++ 424 } 425 426 cursym.Size = int64(len(buffer)) 427 if cursym.Size%FuncAlign != 0 { 428 cursym.Size += FuncAlign - (cursym.Size % FuncAlign) 429 } 430 cursym.Grow(cursym.Size) 431 copy(cursym.P, buffer) 432 } 433 434 func isint32(v int64) bool { 435 return int64(int32(v)) == v 436 } 437 438 func isuint32(v uint64) bool { 439 return uint64(uint32(v)) == v 440 } 441 442 func aclass(ctxt *obj.Link, a *obj.Addr) int { 443 switch a.Type { 444 case obj.TYPE_NONE: 445 return C_NONE 446 447 case obj.TYPE_REG: 448 if REG_R0 <= a.Reg && a.Reg <= REG_R15 { 449 return C_REG 450 } 451 if REG_F0 <= a.Reg && a.Reg <= REG_F15 { 452 return C_FREG 453 } 454 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 { 455 return C_AREG 456 } 457 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 458 return C_VREG 459 } 460 return C_GOK 461 462 case obj.TYPE_MEM: 463 switch a.Name { 464 case obj.NAME_EXTERN, 465 obj.NAME_STATIC: 466 if a.Sym == nil { 467 // must have a symbol 468 break 469 } 470 ctxt.Instoffset = a.Offset 471 if a.Sym.Type == obj.STLSBSS { 472 if ctxt.Flag_shared { 473 return C_TLS_IE // initial exec model 474 } 475 return C_TLS_LE // local exec model 476 } 477 return C_ADDR 478 479 case obj.NAME_GOTREF: 480 return C_GOTADDR 481 482 case obj.NAME_AUTO: 483 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 484 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 485 return C_SAUTO 486 } 487 return C_LAUTO 488 489 case obj.NAME_PARAM: 490 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 491 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 492 return C_SAUTO 493 } 494 return C_LAUTO 495 496 case obj.NAME_NONE: 497 ctxt.Instoffset = a.Offset 498 if ctxt.Instoffset == 0 { 499 return C_ZOREG 500 } 501 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 502 return C_SOREG 503 } 504 return C_LOREG 505 } 506 507 return C_GOK 508 509 case obj.TYPE_TEXTSIZE: 510 return C_TEXTSIZE 511 512 case obj.TYPE_FCONST: 513 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 { 514 return C_ZCON 515 } 516 ctxt.Diag("cannot handle the floating point constant %v", a.Val) 517 518 case obj.TYPE_CONST, 519 obj.TYPE_ADDR: 520 switch a.Name { 521 case obj.NAME_NONE: 522 ctxt.Instoffset = a.Offset 523 if a.Reg != 0 { 524 if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG { 525 return C_SACON 526 } 527 if isint32(ctxt.Instoffset) { 528 return C_LACON 529 } 530 return C_DACON 531 } 532 goto consize 533 534 case obj.NAME_EXTERN, 535 obj.NAME_STATIC: 536 s := a.Sym 537 if s == nil { 538 break 539 } 540 ctxt.Instoffset = a.Offset 541 if s.Type == obj.SCONST { 542 goto consize 543 } 544 545 return C_SYMADDR 546 547 case obj.NAME_AUTO: 548 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset 549 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 550 return C_SACON 551 } 552 return C_LACON 553 554 case obj.NAME_PARAM: 555 ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize() 556 if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG { 557 return C_SACON 558 } 559 return C_LACON 560 } 561 562 return C_GOK 563 564 consize: 565 if ctxt.Instoffset == 0 { 566 return C_ZCON 567 } 568 if ctxt.Instoffset >= 0 { 569 if ctxt.Instoffset <= 0x7fff { 570 return C_SCON 571 } 572 if ctxt.Instoffset <= 0xffff { 573 return C_ANDCON 574 } 575 if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 576 return C_UCON 577 } 578 if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) { 579 return C_LCON 580 } 581 return C_DCON 582 } 583 584 if ctxt.Instoffset >= -0x8000 { 585 return C_ADDCON 586 } 587 if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) { 588 return C_UCON 589 } 590 if isint32(ctxt.Instoffset) { 591 return C_LCON 592 } 593 return C_DCON 594 595 case obj.TYPE_BRANCH: 596 return C_SBRA 597 } 598 599 return C_GOK 600 } 601 602 func oplook(ctxt *obj.Link, p *obj.Prog) *Optab { 603 a1 := int(p.Optab) 604 if a1 != 0 { 605 return &optab[a1-1] 606 } 607 a1 = int(p.From.Class) 608 if a1 == 0 { 609 a1 = aclass(ctxt, &p.From) + 1 610 p.From.Class = int8(a1) 611 } 612 613 a1-- 614 a3 := C_NONE + 1 615 if p.From3 != nil { 616 a3 = int(p.From3.Class) 617 if a3 == 0 { 618 a3 = aclass(ctxt, p.From3) + 1 619 p.From3.Class = int8(a3) 620 } 621 } 622 623 a3-- 624 a4 := int(p.To.Class) 625 if a4 == 0 { 626 a4 = aclass(ctxt, &p.To) + 1 627 p.To.Class = int8(a4) 628 } 629 630 a4-- 631 a2 := C_NONE 632 if p.Reg != 0 { 633 if REG_R0 <= p.Reg && p.Reg <= REG_R15 { 634 a2 = C_REG 635 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 636 a2 = C_VREG 637 } else if REG_F0 <= p.Reg && p.Reg <= REG_F15 { 638 a2 = C_FREG 639 } else if REG_AR0 <= p.Reg && p.Reg <= REG_AR15 { 640 a2 = C_AREG 641 } 642 } 643 644 ops := oprange[p.As&obj.AMask] 645 c1 := &xcmp[a1] 646 c2 := &xcmp[a2] 647 c3 := &xcmp[a3] 648 c4 := &xcmp[a4] 649 for i := range ops { 650 op := &ops[i] 651 if (int(op.a2) == a2 || c2[op.a2]) && c4[op.a4] && c1[op.a1] && c3[op.a3] { 652 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 653 return op 654 } 655 } 656 657 // cannot find a case; abort 658 ctxt.Diag("illegal combination %v %v %v %v %v\n", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 659 ctxt.Diag("prog: %v\n", p) 660 return nil 661 } 662 663 func cmp(a int, b int) bool { 664 if a == b { 665 return true 666 } 667 switch a { 668 case C_DCON: 669 if b == C_LCON { 670 return true 671 } 672 fallthrough 673 case C_LCON: 674 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 675 return true 676 } 677 678 case C_ADDCON: 679 if b == C_ZCON || b == C_SCON { 680 return true 681 } 682 683 case C_ANDCON: 684 if b == C_ZCON || b == C_SCON { 685 return true 686 } 687 688 case C_UCON: 689 if b == C_ZCON || b == C_SCON { 690 return true 691 } 692 693 case C_SCON: 694 if b == C_ZCON { 695 return true 696 } 697 698 case C_LACON: 699 if b == C_SACON { 700 return true 701 } 702 703 case C_LBRA: 704 if b == C_SBRA { 705 return true 706 } 707 708 case C_LAUTO: 709 if b == C_SAUTO { 710 return true 711 } 712 713 case C_LOREG: 714 if b == C_ZOREG || b == C_SOREG { 715 return true 716 } 717 718 case C_SOREG: 719 if b == C_ZOREG { 720 return true 721 } 722 723 case C_ANY: 724 return true 725 } 726 727 return false 728 } 729 730 type ocmp []Optab 731 732 func (x ocmp) Len() int { 733 return len(x) 734 } 735 736 func (x ocmp) Swap(i, j int) { 737 x[i], x[j] = x[j], x[i] 738 } 739 740 func (x ocmp) Less(i, j int) bool { 741 p1 := &x[i] 742 p2 := &x[j] 743 n := int(p1.as) - int(p2.as) 744 if n != 0 { 745 return n < 0 746 } 747 n = int(p1.a1) - int(p2.a1) 748 if n != 0 { 749 return n < 0 750 } 751 n = int(p1.a2) - int(p2.a2) 752 if n != 0 { 753 return n < 0 754 } 755 n = int(p1.a3) - int(p2.a3) 756 if n != 0 { 757 return n < 0 758 } 759 n = int(p1.a4) - int(p2.a4) 760 if n != 0 { 761 return n < 0 762 } 763 return false 764 } 765 func opset(a, b obj.As) { 766 oprange[a&obj.AMask] = oprange[b&obj.AMask] 767 } 768 769 func buildop(ctxt *obj.Link) { 770 for i := 0; i < C_NCLASS; i++ { 771 for n := 0; n < C_NCLASS; n++ { 772 if cmp(n, i) { 773 xcmp[i][n] = true 774 } 775 } 776 } 777 sort.Sort(ocmp(optab)) 778 for i := 0; i < len(optab); i++ { 779 r := optab[i].as 780 start := i 781 for ; i+1 < len(optab); i++ { 782 if optab[i+1].as != r { 783 break 784 } 785 } 786 oprange[r&obj.AMask] = optab[start : i+1] 787 788 // opset() aliases optab ranges for similar instructions, to reduce the number of optabs in the array. 789 // oprange[] is used by oplook() to find the Optab entry that applies to a given Prog. 790 switch r { 791 case AADD: 792 opset(AADDC, r) 793 opset(AMULLD, r) 794 opset(AMULLW, r) 795 case ADIVW: 796 opset(AADDE, r) 797 opset(ADIVD, r) 798 opset(ADIVDU, r) 799 opset(ADIVWU, r) 800 case AMULHD: 801 opset(AMULHDU, r) 802 case AMOVBZ: 803 opset(AMOVH, r) 804 opset(AMOVHZ, r) 805 case ALA: 806 opset(ALAY, r) 807 case AMVC: 808 opset(ACLC, r) 809 opset(AXC, r) 810 opset(AOC, r) 811 opset(ANC, r) 812 case ASTCK: 813 opset(ASTCKC, r) 814 opset(ASTCKE, r) 815 opset(ASTCKF, r) 816 case ALAAG: 817 opset(ALAA, r) 818 opset(ALAAL, r) 819 opset(ALAALG, r) 820 opset(ALAN, r) 821 opset(ALANG, r) 822 opset(ALAX, r) 823 opset(ALAXG, r) 824 opset(ALAO, r) 825 opset(ALAOG, r) 826 case ASTMG: 827 opset(ASTMY, r) 828 case ALMG: 829 opset(ALMY, r) 830 case AAND: 831 opset(AANDN, r) 832 opset(ANAND, r) 833 opset(ANOR, r) 834 opset(AORN, r) 835 case AADDME: 836 opset(AADDZE, r) 837 opset(ASUBME, r) 838 opset(ASUBZE, r) 839 case ABEQ: 840 opset(ABGE, r) 841 opset(ABGT, r) 842 opset(ABLE, r) 843 opset(ABLT, r) 844 opset(ABNE, r) 845 opset(ABVC, r) 846 opset(ABVS, r) 847 case ABR: 848 opset(ABL, r) 849 case ABC: 850 opset(ABCL, r) 851 case AFABS: 852 opset(AFNABS, r) 853 opset(AFNEG, r) 854 opset(ALEDBR, r) 855 opset(ALDEBR, r) 856 opset(AFSQRT, r) 857 opset(AFSQRTS, r) 858 case AFADD: 859 opset(AFADDS, r) 860 opset(AFDIV, r) 861 opset(AFDIVS, r) 862 opset(AFSUB, r) 863 opset(AFSUBS, r) 864 case AFMADD: 865 opset(AFMADDS, r) 866 opset(AFMSUB, r) 867 opset(AFMSUBS, r) 868 opset(AFNMADD, r) 869 opset(AFNMADDS, r) 870 opset(AFNMSUB, r) 871 opset(AFNMSUBS, r) 872 case AFMUL: 873 opset(AFMULS, r) 874 case AFCMPO: 875 opset(AFCMPU, r) 876 opset(ACEBR, r) 877 case AOR: 878 opset(AXOR, r) 879 case ASLD: 880 opset(ASRD, r) 881 opset(ASLW, r) 882 opset(ASRW, r) 883 opset(ASRAD, r) 884 opset(ASRAW, r) 885 opset(ARLL, r) 886 opset(ARLLG, r) 887 case ACSG: 888 opset(ACS, r) 889 case ASUB: 890 opset(ASUBC, r) 891 opset(ASUBE, r) 892 case AFMOVD: 893 opset(AFMOVS, r) 894 case AMOVDBR: 895 opset(AMOVWBR, r) 896 case ACMP: 897 opset(ACMPW, r) 898 case ACMPU: 899 opset(ACMPWU, r) 900 case ACEFBRA: 901 opset(ACDFBRA, r) 902 opset(ACEGBRA, r) 903 opset(ACDGBRA, r) 904 opset(ACELFBR, r) 905 opset(ACDLFBR, r) 906 opset(ACELGBR, r) 907 opset(ACDLGBR, r) 908 case ACFEBRA: 909 opset(ACFDBRA, r) 910 opset(ACGEBRA, r) 911 opset(ACGDBRA, r) 912 opset(ACLFEBR, r) 913 opset(ACLFDBR, r) 914 opset(ACLGEBR, r) 915 opset(ACLGDBR, r) 916 case AFIEBR: 917 opset(AFIDBR, r) 918 case ACMPBEQ: 919 opset(ACMPBGE, r) 920 opset(ACMPBGT, r) 921 opset(ACMPBLE, r) 922 opset(ACMPBLT, r) 923 opset(ACMPBNE, r) 924 case ACMPUBEQ: 925 opset(ACMPUBGE, r) 926 opset(ACMPUBGT, r) 927 opset(ACMPUBLE, r) 928 opset(ACMPUBLT, r) 929 opset(ACMPUBNE, r) 930 case AVL: 931 opset(AVLLEZB, r) 932 opset(AVLLEZH, r) 933 opset(AVLLEZF, r) 934 opset(AVLLEZG, r) 935 opset(AVLREPB, r) 936 opset(AVLREPH, r) 937 opset(AVLREPF, r) 938 opset(AVLREPG, r) 939 case AVLEG: 940 opset(AVLBB, r) 941 opset(AVLEB, r) 942 opset(AVLEH, r) 943 opset(AVLEF, r) 944 opset(AVLEG, r) 945 opset(AVLREP, r) 946 case AVSTEG: 947 opset(AVSTEB, r) 948 opset(AVSTEH, r) 949 opset(AVSTEF, r) 950 case AVSCEG: 951 opset(AVSCEF, r) 952 case AVGEG: 953 opset(AVGEF, r) 954 case AVESLG: 955 opset(AVESLB, r) 956 opset(AVESLH, r) 957 opset(AVESLF, r) 958 opset(AVERLLB, r) 959 opset(AVERLLH, r) 960 opset(AVERLLF, r) 961 opset(AVERLLG, r) 962 opset(AVESRAB, r) 963 opset(AVESRAH, r) 964 opset(AVESRAF, r) 965 opset(AVESRAG, r) 966 opset(AVESRLB, r) 967 opset(AVESRLH, r) 968 opset(AVESRLF, r) 969 opset(AVESRLG, r) 970 case AVLGVG: 971 opset(AVLGVB, r) 972 opset(AVLGVH, r) 973 opset(AVLGVF, r) 974 case AVLVGG: 975 opset(AVLVGB, r) 976 opset(AVLVGH, r) 977 opset(AVLVGF, r) 978 case AVZERO: 979 opset(AVONE, r) 980 case AVREPIG: 981 opset(AVREPIB, r) 982 opset(AVREPIH, r) 983 opset(AVREPIF, r) 984 case AVLEIG: 985 opset(AVLEIB, r) 986 opset(AVLEIH, r) 987 opset(AVLEIF, r) 988 case AVGMG: 989 opset(AVGMB, r) 990 opset(AVGMH, r) 991 opset(AVGMF, r) 992 case AVREPG: 993 opset(AVREPB, r) 994 opset(AVREPH, r) 995 opset(AVREPF, r) 996 case AVERIMG: 997 opset(AVERIMB, r) 998 opset(AVERIMH, r) 999 opset(AVERIMF, r) 1000 case AVFTCIDB: 1001 opset(AWFTCIDB, r) 1002 case AVLR: 1003 opset(AVUPHB, r) 1004 opset(AVUPHH, r) 1005 opset(AVUPHF, r) 1006 opset(AVUPLHB, r) 1007 opset(AVUPLHH, r) 1008 opset(AVUPLHF, r) 1009 opset(AVUPLB, r) 1010 opset(AVUPLHW, r) 1011 opset(AVUPLF, r) 1012 opset(AVUPLLB, r) 1013 opset(AVUPLLH, r) 1014 opset(AVUPLLF, r) 1015 opset(AVCLZB, r) 1016 opset(AVCLZH, r) 1017 opset(AVCLZF, r) 1018 opset(AVCLZG, r) 1019 opset(AVCTZB, r) 1020 opset(AVCTZH, r) 1021 opset(AVCTZF, r) 1022 opset(AVCTZG, r) 1023 opset(AVLDEB, r) 1024 opset(AWLDEB, r) 1025 opset(AVFLCDB, r) 1026 opset(AWFLCDB, r) 1027 opset(AVFLNDB, r) 1028 opset(AWFLNDB, r) 1029 opset(AVFLPDB, r) 1030 opset(AWFLPDB, r) 1031 opset(AVFSQDB, r) 1032 opset(AWFSQDB, r) 1033 opset(AVISTRB, r) 1034 opset(AVISTRH, r) 1035 opset(AVISTRF, r) 1036 opset(AVISTRBS, r) 1037 opset(AVISTRHS, r) 1038 opset(AVISTRFS, r) 1039 opset(AVLCB, r) 1040 opset(AVLCH, r) 1041 opset(AVLCF, r) 1042 opset(AVLCG, r) 1043 opset(AVLPB, r) 1044 opset(AVLPH, r) 1045 opset(AVLPF, r) 1046 opset(AVLPG, r) 1047 opset(AVPOPCT, r) 1048 opset(AVSEGB, r) 1049 opset(AVSEGH, r) 1050 opset(AVSEGF, r) 1051 case AVECG: 1052 opset(AVECB, r) 1053 opset(AVECH, r) 1054 opset(AVECF, r) 1055 opset(AVECLB, r) 1056 opset(AVECLH, r) 1057 opset(AVECLF, r) 1058 opset(AVECLG, r) 1059 opset(AWFCDB, r) 1060 opset(AWFKDB, r) 1061 case AVCEQG: 1062 opset(AVCEQB, r) 1063 opset(AVCEQH, r) 1064 opset(AVCEQF, r) 1065 opset(AVCEQBS, r) 1066 opset(AVCEQHS, r) 1067 opset(AVCEQFS, r) 1068 opset(AVCEQGS, r) 1069 opset(AVCHB, r) 1070 opset(AVCHH, r) 1071 opset(AVCHF, r) 1072 opset(AVCHG, r) 1073 opset(AVCHBS, r) 1074 opset(AVCHHS, r) 1075 opset(AVCHFS, r) 1076 opset(AVCHGS, r) 1077 opset(AVCHLB, r) 1078 opset(AVCHLH, r) 1079 opset(AVCHLF, r) 1080 opset(AVCHLG, r) 1081 opset(AVCHLBS, r) 1082 opset(AVCHLHS, r) 1083 opset(AVCHLFS, r) 1084 opset(AVCHLGS, r) 1085 case AVFAEF: 1086 opset(AVFAEB, r) 1087 opset(AVFAEH, r) 1088 opset(AVFAEBS, r) 1089 opset(AVFAEHS, r) 1090 opset(AVFAEFS, r) 1091 opset(AVFAEZB, r) 1092 opset(AVFAEZH, r) 1093 opset(AVFAEZF, r) 1094 opset(AVFAEZBS, r) 1095 opset(AVFAEZHS, r) 1096 opset(AVFAEZFS, r) 1097 opset(AVFEEB, r) 1098 opset(AVFEEH, r) 1099 opset(AVFEEF, r) 1100 opset(AVFEEBS, r) 1101 opset(AVFEEHS, r) 1102 opset(AVFEEFS, r) 1103 opset(AVFEEZB, r) 1104 opset(AVFEEZH, r) 1105 opset(AVFEEZF, r) 1106 opset(AVFEEZBS, r) 1107 opset(AVFEEZHS, r) 1108 opset(AVFEEZFS, r) 1109 opset(AVFENEB, r) 1110 opset(AVFENEH, r) 1111 opset(AVFENEF, r) 1112 opset(AVFENEBS, r) 1113 opset(AVFENEHS, r) 1114 opset(AVFENEFS, r) 1115 opset(AVFENEZB, r) 1116 opset(AVFENEZH, r) 1117 opset(AVFENEZF, r) 1118 opset(AVFENEZBS, r) 1119 opset(AVFENEZHS, r) 1120 opset(AVFENEZFS, r) 1121 case AVPKSG: 1122 opset(AVPKSH, r) 1123 opset(AVPKSF, r) 1124 opset(AVPKSHS, r) 1125 opset(AVPKSFS, r) 1126 opset(AVPKSGS, r) 1127 opset(AVPKLSH, r) 1128 opset(AVPKLSF, r) 1129 opset(AVPKLSG, r) 1130 opset(AVPKLSHS, r) 1131 opset(AVPKLSFS, r) 1132 opset(AVPKLSGS, r) 1133 case AVAQ: 1134 opset(AVAB, r) 1135 opset(AVAH, r) 1136 opset(AVAF, r) 1137 opset(AVAG, r) 1138 opset(AVACCB, r) 1139 opset(AVACCH, r) 1140 opset(AVACCF, r) 1141 opset(AVACCG, r) 1142 opset(AVACCQ, r) 1143 opset(AVN, r) 1144 opset(AVNC, r) 1145 opset(AVAVGB, r) 1146 opset(AVAVGH, r) 1147 opset(AVAVGF, r) 1148 opset(AVAVGG, r) 1149 opset(AVAVGLB, r) 1150 opset(AVAVGLH, r) 1151 opset(AVAVGLF, r) 1152 opset(AVAVGLG, r) 1153 opset(AVCKSM, r) 1154 opset(AVX, r) 1155 opset(AVFADB, r) 1156 opset(AWFADB, r) 1157 opset(AVFCEDB, r) 1158 opset(AVFCEDBS, r) 1159 opset(AWFCEDB, r) 1160 opset(AWFCEDBS, r) 1161 opset(AVFCHDB, r) 1162 opset(AVFCHDBS, r) 1163 opset(AWFCHDB, r) 1164 opset(AWFCHDBS, r) 1165 opset(AVFCHEDB, r) 1166 opset(AVFCHEDBS, r) 1167 opset(AWFCHEDB, r) 1168 opset(AWFCHEDBS, r) 1169 opset(AVFMDB, r) 1170 opset(AWFMDB, r) 1171 opset(AVGFMB, r) 1172 opset(AVGFMH, r) 1173 opset(AVGFMF, r) 1174 opset(AVGFMG, r) 1175 opset(AVMXB, r) 1176 opset(AVMXH, r) 1177 opset(AVMXF, r) 1178 opset(AVMXG, r) 1179 opset(AVMXLB, r) 1180 opset(AVMXLH, r) 1181 opset(AVMXLF, r) 1182 opset(AVMXLG, r) 1183 opset(AVMNB, r) 1184 opset(AVMNH, r) 1185 opset(AVMNF, r) 1186 opset(AVMNG, r) 1187 opset(AVMNLB, r) 1188 opset(AVMNLH, r) 1189 opset(AVMNLF, r) 1190 opset(AVMNLG, r) 1191 opset(AVMRHB, r) 1192 opset(AVMRHH, r) 1193 opset(AVMRHF, r) 1194 opset(AVMRHG, r) 1195 opset(AVMRLB, r) 1196 opset(AVMRLH, r) 1197 opset(AVMRLF, r) 1198 opset(AVMRLG, r) 1199 opset(AVMEB, r) 1200 opset(AVMEH, r) 1201 opset(AVMEF, r) 1202 opset(AVMLEB, r) 1203 opset(AVMLEH, r) 1204 opset(AVMLEF, r) 1205 opset(AVMOB, r) 1206 opset(AVMOH, r) 1207 opset(AVMOF, r) 1208 opset(AVMLOB, r) 1209 opset(AVMLOH, r) 1210 opset(AVMLOF, r) 1211 opset(AVMHB, r) 1212 opset(AVMHH, r) 1213 opset(AVMHF, r) 1214 opset(AVMLHB, r) 1215 opset(AVMLHH, r) 1216 opset(AVMLHF, r) 1217 opset(AVMLH, r) 1218 opset(AVMLHW, r) 1219 opset(AVMLF, r) 1220 opset(AVNO, r) 1221 opset(AVO, r) 1222 opset(AVPKH, r) 1223 opset(AVPKF, r) 1224 opset(AVPKG, r) 1225 opset(AVSUMGH, r) 1226 opset(AVSUMGF, r) 1227 opset(AVSUMQF, r) 1228 opset(AVSUMQG, r) 1229 opset(AVSUMB, r) 1230 opset(AVSUMH, r) 1231 case AVERLLVG: 1232 opset(AVERLLVB, r) 1233 opset(AVERLLVH, r) 1234 opset(AVERLLVF, r) 1235 opset(AVESLVB, r) 1236 opset(AVESLVH, r) 1237 opset(AVESLVF, r) 1238 opset(AVESLVG, r) 1239 opset(AVESRAVB, r) 1240 opset(AVESRAVH, r) 1241 opset(AVESRAVF, r) 1242 opset(AVESRAVG, r) 1243 opset(AVESRLVB, r) 1244 opset(AVESRLVH, r) 1245 opset(AVESRLVF, r) 1246 opset(AVESRLVG, r) 1247 opset(AVFDDB, r) 1248 opset(AWFDDB, r) 1249 opset(AVFSDB, r) 1250 opset(AWFSDB, r) 1251 opset(AVSL, r) 1252 opset(AVSLB, r) 1253 opset(AVSRA, r) 1254 opset(AVSRAB, r) 1255 opset(AVSRL, r) 1256 opset(AVSRLB, r) 1257 opset(AVSF, r) 1258 opset(AVSG, r) 1259 opset(AVSQ, r) 1260 opset(AVSCBIB, r) 1261 opset(AVSCBIH, r) 1262 opset(AVSCBIF, r) 1263 opset(AVSCBIG, r) 1264 opset(AVSCBIQ, r) 1265 case AVACQ: 1266 opset(AVACCCQ, r) 1267 opset(AVGFMAB, r) 1268 opset(AVGFMAH, r) 1269 opset(AVGFMAF, r) 1270 opset(AVGFMAG, r) 1271 opset(AVMALB, r) 1272 opset(AVMALHW, r) 1273 opset(AVMALF, r) 1274 opset(AVMAHB, r) 1275 opset(AVMAHH, r) 1276 opset(AVMAHF, r) 1277 opset(AVMALHB, r) 1278 opset(AVMALHH, r) 1279 opset(AVMALHF, r) 1280 opset(AVMAEB, r) 1281 opset(AVMAEH, r) 1282 opset(AVMAEF, r) 1283 opset(AVMALEB, r) 1284 opset(AVMALEH, r) 1285 opset(AVMALEF, r) 1286 opset(AVMAOB, r) 1287 opset(AVMAOH, r) 1288 opset(AVMAOF, r) 1289 opset(AVMALOB, r) 1290 opset(AVMALOH, r) 1291 opset(AVMALOF, r) 1292 opset(AVSTRCB, r) 1293 opset(AVSTRCH, r) 1294 opset(AVSTRCF, r) 1295 opset(AVSTRCBS, r) 1296 opset(AVSTRCHS, r) 1297 opset(AVSTRCFS, r) 1298 opset(AVSTRCZB, r) 1299 opset(AVSTRCZH, r) 1300 opset(AVSTRCZF, r) 1301 opset(AVSTRCZBS, r) 1302 opset(AVSTRCZHS, r) 1303 opset(AVSTRCZFS, r) 1304 opset(AVSBCBIQ, r) 1305 opset(AVSBIQ, r) 1306 case AVSEL: 1307 opset(AVFMADB, r) 1308 opset(AWFMADB, r) 1309 opset(AVFMSDB, r) 1310 opset(AWFMSDB, r) 1311 opset(AVPERM, r) 1312 } 1313 } 1314 } 1315 1316 const ( 1317 op_A uint32 = 0x5A00 // FORMAT_RX1 ADD (32) 1318 op_AD uint32 = 0x6A00 // FORMAT_RX1 ADD NORMALIZED (long HFP) 1319 op_ADB uint32 = 0xED1A // FORMAT_RXE ADD (long BFP) 1320 op_ADBR uint32 = 0xB31A // FORMAT_RRE ADD (long BFP) 1321 op_ADR uint32 = 0x2A00 // FORMAT_RR ADD NORMALIZED (long HFP) 1322 op_ADTR uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1323 op_ADTRA uint32 = 0xB3D2 // FORMAT_RRF1 ADD (long DFP) 1324 op_AE uint32 = 0x7A00 // FORMAT_RX1 ADD NORMALIZED (short HFP) 1325 op_AEB uint32 = 0xED0A // FORMAT_RXE ADD (short BFP) 1326 op_AEBR uint32 = 0xB30A // FORMAT_RRE ADD (short BFP) 1327 op_AER uint32 = 0x3A00 // FORMAT_RR ADD NORMALIZED (short HFP) 1328 op_AFI uint32 = 0xC209 // FORMAT_RIL1 ADD IMMEDIATE (32) 1329 op_AG uint32 = 0xE308 // FORMAT_RXY1 ADD (64) 1330 op_AGF uint32 = 0xE318 // FORMAT_RXY1 ADD (64<-32) 1331 op_AGFI uint32 = 0xC208 // FORMAT_RIL1 ADD IMMEDIATE (64<-32) 1332 op_AGFR uint32 = 0xB918 // FORMAT_RRE ADD (64<-32) 1333 op_AGHI uint32 = 0xA70B // FORMAT_RI1 ADD HALFWORD IMMEDIATE (64) 1334 op_AGHIK uint32 = 0xECD9 // FORMAT_RIE4 ADD IMMEDIATE (64<-16) 1335 op_AGR uint32 = 0xB908 // FORMAT_RRE ADD (64) 1336 op_AGRK uint32 = 0xB9E8 // FORMAT_RRF1 ADD (64) 1337 op_AGSI uint32 = 0xEB7A // FORMAT_SIY ADD IMMEDIATE (64<-8) 1338 op_AH uint32 = 0x4A00 // FORMAT_RX1 ADD HALFWORD 1339 op_AHHHR uint32 = 0xB9C8 // FORMAT_RRF1 ADD HIGH (32) 1340 op_AHHLR uint32 = 0xB9D8 // FORMAT_RRF1 ADD HIGH (32) 1341 op_AHI uint32 = 0xA70A // FORMAT_RI1 ADD HALFWORD IMMEDIATE (32) 1342 op_AHIK uint32 = 0xECD8 // FORMAT_RIE4 ADD IMMEDIATE (32<-16) 1343 op_AHY uint32 = 0xE37A // FORMAT_RXY1 ADD HALFWORD 1344 op_AIH uint32 = 0xCC08 // FORMAT_RIL1 ADD IMMEDIATE HIGH (32) 1345 op_AL uint32 = 0x5E00 // FORMAT_RX1 ADD LOGICAL (32) 1346 op_ALC uint32 = 0xE398 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (32) 1347 op_ALCG uint32 = 0xE388 // FORMAT_RXY1 ADD LOGICAL WITH CARRY (64) 1348 op_ALCGR uint32 = 0xB988 // FORMAT_RRE ADD LOGICAL WITH CARRY (64) 1349 op_ALCR uint32 = 0xB998 // FORMAT_RRE ADD LOGICAL WITH CARRY (32) 1350 op_ALFI uint32 = 0xC20B // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (32) 1351 op_ALG uint32 = 0xE30A // FORMAT_RXY1 ADD LOGICAL (64) 1352 op_ALGF uint32 = 0xE31A // FORMAT_RXY1 ADD LOGICAL (64<-32) 1353 op_ALGFI uint32 = 0xC20A // FORMAT_RIL1 ADD LOGICAL IMMEDIATE (64<-32) 1354 op_ALGFR uint32 = 0xB91A // FORMAT_RRE ADD LOGICAL (64<-32) 1355 op_ALGHSIK uint32 = 0xECDB // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (64<-16) 1356 op_ALGR uint32 = 0xB90A // FORMAT_RRE ADD LOGICAL (64) 1357 op_ALGRK uint32 = 0xB9EA // FORMAT_RRF1 ADD LOGICAL (64) 1358 op_ALGSI uint32 = 0xEB7E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (64<-8) 1359 op_ALHHHR uint32 = 0xB9CA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1360 op_ALHHLR uint32 = 0xB9DA // FORMAT_RRF1 ADD LOGICAL HIGH (32) 1361 op_ALHSIK uint32 = 0xECDA // FORMAT_RIE4 ADD LOGICAL WITH SIGNED IMMEDIATE (32<-16) 1362 op_ALR uint32 = 0x1E00 // FORMAT_RR ADD LOGICAL (32) 1363 op_ALRK uint32 = 0xB9FA // FORMAT_RRF1 ADD LOGICAL (32) 1364 op_ALSI uint32 = 0xEB6E // FORMAT_SIY ADD LOGICAL WITH SIGNED IMMEDIATE (32<-8) 1365 op_ALSIH uint32 = 0xCC0A // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1366 op_ALSIHN uint32 = 0xCC0B // FORMAT_RIL1 ADD LOGICAL WITH SIGNED IMMEDIATE HIGH (32) 1367 op_ALY uint32 = 0xE35E // FORMAT_RXY1 ADD LOGICAL (32) 1368 op_AP uint32 = 0xFA00 // FORMAT_SS2 ADD DECIMAL 1369 op_AR uint32 = 0x1A00 // FORMAT_RR ADD (32) 1370 op_ARK uint32 = 0xB9F8 // FORMAT_RRF1 ADD (32) 1371 op_ASI uint32 = 0xEB6A // FORMAT_SIY ADD IMMEDIATE (32<-8) 1372 op_AU uint32 = 0x7E00 // FORMAT_RX1 ADD UNNORMALIZED (short HFP) 1373 op_AUR uint32 = 0x3E00 // FORMAT_RR ADD UNNORMALIZED (short HFP) 1374 op_AW uint32 = 0x6E00 // FORMAT_RX1 ADD UNNORMALIZED (long HFP) 1375 op_AWR uint32 = 0x2E00 // FORMAT_RR ADD UNNORMALIZED (long HFP) 1376 op_AXBR uint32 = 0xB34A // FORMAT_RRE ADD (extended BFP) 1377 op_AXR uint32 = 0x3600 // FORMAT_RR ADD NORMALIZED (extended HFP) 1378 op_AXTR uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1379 op_AXTRA uint32 = 0xB3DA // FORMAT_RRF1 ADD (extended DFP) 1380 op_AY uint32 = 0xE35A // FORMAT_RXY1 ADD (32) 1381 op_BAKR uint32 = 0xB240 // FORMAT_RRE BRANCH AND STACK 1382 op_BAL uint32 = 0x4500 // FORMAT_RX1 BRANCH AND LINK 1383 op_BALR uint32 = 0x0500 // FORMAT_RR BRANCH AND LINK 1384 op_BAS uint32 = 0x4D00 // FORMAT_RX1 BRANCH AND SAVE 1385 op_BASR uint32 = 0x0D00 // FORMAT_RR BRANCH AND SAVE 1386 op_BASSM uint32 = 0x0C00 // FORMAT_RR BRANCH AND SAVE AND SET MODE 1387 op_BC uint32 = 0x4700 // FORMAT_RX2 BRANCH ON CONDITION 1388 op_BCR uint32 = 0x0700 // FORMAT_RR BRANCH ON CONDITION 1389 op_BCT uint32 = 0x4600 // FORMAT_RX1 BRANCH ON COUNT (32) 1390 op_BCTG uint32 = 0xE346 // FORMAT_RXY1 BRANCH ON COUNT (64) 1391 op_BCTGR uint32 = 0xB946 // FORMAT_RRE BRANCH ON COUNT (64) 1392 op_BCTR uint32 = 0x0600 // FORMAT_RR BRANCH ON COUNT (32) 1393 op_BPP uint32 = 0xC700 // FORMAT_SMI BRANCH PREDICTION PRELOAD 1394 op_BPRP uint32 = 0xC500 // FORMAT_MII BRANCH PREDICTION RELATIVE PRELOAD 1395 op_BRAS uint32 = 0xA705 // FORMAT_RI2 BRANCH RELATIVE AND SAVE 1396 op_BRASL uint32 = 0xC005 // FORMAT_RIL2 BRANCH RELATIVE AND SAVE LONG 1397 op_BRC uint32 = 0xA704 // FORMAT_RI3 BRANCH RELATIVE ON CONDITION 1398 op_BRCL uint32 = 0xC004 // FORMAT_RIL3 BRANCH RELATIVE ON CONDITION LONG 1399 op_BRCT uint32 = 0xA706 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (32) 1400 op_BRCTG uint32 = 0xA707 // FORMAT_RI2 BRANCH RELATIVE ON COUNT (64) 1401 op_BRCTH uint32 = 0xCC06 // FORMAT_RIL2 BRANCH RELATIVE ON COUNT HIGH (32) 1402 op_BRXH uint32 = 0x8400 // FORMAT_RSI BRANCH RELATIVE ON INDEX HIGH (32) 1403 op_BRXHG uint32 = 0xEC44 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX HIGH (64) 1404 op_BRXLE uint32 = 0x8500 // FORMAT_RSI BRANCH RELATIVE ON INDEX LOW OR EQ. (32) 1405 op_BRXLG uint32 = 0xEC45 // FORMAT_RIE5 BRANCH RELATIVE ON INDEX LOW OR EQ. (64) 1406 op_BSA uint32 = 0xB25A // FORMAT_RRE BRANCH AND SET AUTHORITY 1407 op_BSG uint32 = 0xB258 // FORMAT_RRE BRANCH IN SUBSPACE GROUP 1408 op_BSM uint32 = 0x0B00 // FORMAT_RR BRANCH AND SET MODE 1409 op_BXH uint32 = 0x8600 // FORMAT_RS1 BRANCH ON INDEX HIGH (32) 1410 op_BXHG uint32 = 0xEB44 // FORMAT_RSY1 BRANCH ON INDEX HIGH (64) 1411 op_BXLE uint32 = 0x8700 // FORMAT_RS1 BRANCH ON INDEX LOW OR EQUAL (32) 1412 op_BXLEG uint32 = 0xEB45 // FORMAT_RSY1 BRANCH ON INDEX LOW OR EQUAL (64) 1413 op_C uint32 = 0x5900 // FORMAT_RX1 COMPARE (32) 1414 op_CD uint32 = 0x6900 // FORMAT_RX1 COMPARE (long HFP) 1415 op_CDB uint32 = 0xED19 // FORMAT_RXE COMPARE (long BFP) 1416 op_CDBR uint32 = 0xB319 // FORMAT_RRE COMPARE (long BFP) 1417 op_CDFBR uint32 = 0xB395 // FORMAT_RRE CONVERT FROM FIXED (32 to long BFP) 1418 op_CDFBRA uint32 = 0xB395 // FORMAT_RRF5 CONVERT FROM FIXED (32 to long BFP) 1419 op_CDFR uint32 = 0xB3B5 // FORMAT_RRE CONVERT FROM FIXED (32 to long HFP) 1420 op_CDFTR uint32 = 0xB951 // FORMAT_RRE CONVERT FROM FIXED (32 to long DFP) 1421 op_CDGBR uint32 = 0xB3A5 // FORMAT_RRE CONVERT FROM FIXED (64 to long BFP) 1422 op_CDGBRA uint32 = 0xB3A5 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long BFP) 1423 op_CDGR uint32 = 0xB3C5 // FORMAT_RRE CONVERT FROM FIXED (64 to long HFP) 1424 op_CDGTR uint32 = 0xB3F1 // FORMAT_RRE CONVERT FROM FIXED (64 to long DFP) 1425 op_CDGTRA uint32 = 0xB3F1 // FORMAT_RRF5 CONVERT FROM FIXED (64 to long DFP) 1426 op_CDLFBR uint32 = 0xB391 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long BFP) 1427 op_CDLFTR uint32 = 0xB953 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to long DFP) 1428 op_CDLGBR uint32 = 0xB3A1 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long BFP) 1429 op_CDLGTR uint32 = 0xB952 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to long DFP) 1430 op_CDR uint32 = 0x2900 // FORMAT_RR COMPARE (long HFP) 1431 op_CDS uint32 = 0xBB00 // FORMAT_RS1 COMPARE DOUBLE AND SWAP (32) 1432 op_CDSG uint32 = 0xEB3E // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (64) 1433 op_CDSTR uint32 = 0xB3F3 // FORMAT_RRE CONVERT FROM SIGNED PACKED (64 to long DFP) 1434 op_CDSY uint32 = 0xEB31 // FORMAT_RSY1 COMPARE DOUBLE AND SWAP (32) 1435 op_CDTR uint32 = 0xB3E4 // FORMAT_RRE COMPARE (long DFP) 1436 op_CDUTR uint32 = 0xB3F2 // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (64 to long DFP) 1437 op_CDZT uint32 = 0xEDAA // FORMAT_RSL CONVERT FROM ZONED (to long DFP) 1438 op_CE uint32 = 0x7900 // FORMAT_RX1 COMPARE (short HFP) 1439 op_CEB uint32 = 0xED09 // FORMAT_RXE COMPARE (short BFP) 1440 op_CEBR uint32 = 0xB309 // FORMAT_RRE COMPARE (short BFP) 1441 op_CEDTR uint32 = 0xB3F4 // FORMAT_RRE COMPARE BIASED EXPONENT (long DFP) 1442 op_CEFBR uint32 = 0xB394 // FORMAT_RRE CONVERT FROM FIXED (32 to short BFP) 1443 op_CEFBRA uint32 = 0xB394 // FORMAT_RRF5 CONVERT FROM FIXED (32 to short BFP) 1444 op_CEFR uint32 = 0xB3B4 // FORMAT_RRE CONVERT FROM FIXED (32 to short HFP) 1445 op_CEGBR uint32 = 0xB3A4 // FORMAT_RRE CONVERT FROM FIXED (64 to short BFP) 1446 op_CEGBRA uint32 = 0xB3A4 // FORMAT_RRF5 CONVERT FROM FIXED (64 to short BFP) 1447 op_CEGR uint32 = 0xB3C4 // FORMAT_RRE CONVERT FROM FIXED (64 to short HFP) 1448 op_CELFBR uint32 = 0xB390 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to short BFP) 1449 op_CELGBR uint32 = 0xB3A0 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to short BFP) 1450 op_CER uint32 = 0x3900 // FORMAT_RR COMPARE (short HFP) 1451 op_CEXTR uint32 = 0xB3FC // FORMAT_RRE COMPARE BIASED EXPONENT (extended DFP) 1452 op_CFC uint32 = 0xB21A // FORMAT_S COMPARE AND FORM CODEWORD 1453 op_CFDBR uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1454 op_CFDBRA uint32 = 0xB399 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 32) 1455 op_CFDR uint32 = 0xB3B9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 32) 1456 op_CFDTR uint32 = 0xB941 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 32) 1457 op_CFEBR uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1458 op_CFEBRA uint32 = 0xB398 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 32) 1459 op_CFER uint32 = 0xB3B8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 32) 1460 op_CFI uint32 = 0xC20D // FORMAT_RIL1 COMPARE IMMEDIATE (32) 1461 op_CFXBR uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1462 op_CFXBRA uint32 = 0xB39A // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 32) 1463 op_CFXR uint32 = 0xB3BA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 32) 1464 op_CFXTR uint32 = 0xB949 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 32) 1465 op_CG uint32 = 0xE320 // FORMAT_RXY1 COMPARE (64) 1466 op_CGDBR uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1467 op_CGDBRA uint32 = 0xB3A9 // FORMAT_RRF5 CONVERT TO FIXED (long BFP to 64) 1468 op_CGDR uint32 = 0xB3C9 // FORMAT_RRF5 CONVERT TO FIXED (long HFP to 64) 1469 op_CGDTR uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1470 op_CGDTRA uint32 = 0xB3E1 // FORMAT_RRF5 CONVERT TO FIXED (long DFP to 64) 1471 op_CGEBR uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1472 op_CGEBRA uint32 = 0xB3A8 // FORMAT_RRF5 CONVERT TO FIXED (short BFP to 64) 1473 op_CGER uint32 = 0xB3C8 // FORMAT_RRF5 CONVERT TO FIXED (short HFP to 64) 1474 op_CGF uint32 = 0xE330 // FORMAT_RXY1 COMPARE (64<-32) 1475 op_CGFI uint32 = 0xC20C // FORMAT_RIL1 COMPARE IMMEDIATE (64<-32) 1476 op_CGFR uint32 = 0xB930 // FORMAT_RRE COMPARE (64<-32) 1477 op_CGFRL uint32 = 0xC60C // FORMAT_RIL2 COMPARE RELATIVE LONG (64<-32) 1478 op_CGH uint32 = 0xE334 // FORMAT_RXY1 COMPARE HALFWORD (64<-16) 1479 op_CGHI uint32 = 0xA70F // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (64<-16) 1480 op_CGHRL uint32 = 0xC604 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (64<-16) 1481 op_CGHSI uint32 = 0xE558 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (64<-16) 1482 op_CGIB uint32 = 0xECFC // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (64<-8) 1483 op_CGIJ uint32 = 0xEC7C // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (64<-8) 1484 op_CGIT uint32 = 0xEC70 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (64<-16) 1485 op_CGR uint32 = 0xB920 // FORMAT_RRE COMPARE (64) 1486 op_CGRB uint32 = 0xECE4 // FORMAT_RRS COMPARE AND BRANCH (64) 1487 op_CGRJ uint32 = 0xEC64 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (64) 1488 op_CGRL uint32 = 0xC608 // FORMAT_RIL2 COMPARE RELATIVE LONG (64) 1489 op_CGRT uint32 = 0xB960 // FORMAT_RRF3 COMPARE AND TRAP (64) 1490 op_CGXBR uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1491 op_CGXBRA uint32 = 0xB3AA // FORMAT_RRF5 CONVERT TO FIXED (extended BFP to 64) 1492 op_CGXR uint32 = 0xB3CA // FORMAT_RRF5 CONVERT TO FIXED (extended HFP to 64) 1493 op_CGXTR uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1494 op_CGXTRA uint32 = 0xB3E9 // FORMAT_RRF5 CONVERT TO FIXED (extended DFP to 64) 1495 op_CH uint32 = 0x4900 // FORMAT_RX1 COMPARE HALFWORD (32<-16) 1496 op_CHF uint32 = 0xE3CD // FORMAT_RXY1 COMPARE HIGH (32) 1497 op_CHHR uint32 = 0xB9CD // FORMAT_RRE COMPARE HIGH (32) 1498 op_CHHSI uint32 = 0xE554 // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (16) 1499 op_CHI uint32 = 0xA70E // FORMAT_RI1 COMPARE HALFWORD IMMEDIATE (32<-16) 1500 op_CHLR uint32 = 0xB9DD // FORMAT_RRE COMPARE HIGH (32) 1501 op_CHRL uint32 = 0xC605 // FORMAT_RIL2 COMPARE HALFWORD RELATIVE LONG (32<-16) 1502 op_CHSI uint32 = 0xE55C // FORMAT_SIL COMPARE HALFWORD IMMEDIATE (32<-16) 1503 op_CHY uint32 = 0xE379 // FORMAT_RXY1 COMPARE HALFWORD (32<-16) 1504 op_CIB uint32 = 0xECFE // FORMAT_RIS COMPARE IMMEDIATE AND BRANCH (32<-8) 1505 op_CIH uint32 = 0xCC0D // FORMAT_RIL1 COMPARE IMMEDIATE HIGH (32) 1506 op_CIJ uint32 = 0xEC7E // FORMAT_RIE3 COMPARE IMMEDIATE AND BRANCH RELATIVE (32<-8) 1507 op_CIT uint32 = 0xEC72 // FORMAT_RIE1 COMPARE IMMEDIATE AND TRAP (32<-16) 1508 op_CKSM uint32 = 0xB241 // FORMAT_RRE CHECKSUM 1509 op_CL uint32 = 0x5500 // FORMAT_RX1 COMPARE LOGICAL (32) 1510 op_CLC uint32 = 0xD500 // FORMAT_SS1 COMPARE LOGICAL (character) 1511 op_CLCL uint32 = 0x0F00 // FORMAT_RR COMPARE LOGICAL LONG 1512 op_CLCLE uint32 = 0xA900 // FORMAT_RS1 COMPARE LOGICAL LONG EXTENDED 1513 op_CLCLU uint32 = 0xEB8F // FORMAT_RSY1 COMPARE LOGICAL LONG UNICODE 1514 op_CLFDBR uint32 = 0xB39D // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 32) 1515 op_CLFDTR uint32 = 0xB943 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 32) 1516 op_CLFEBR uint32 = 0xB39C // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 32) 1517 op_CLFHSI uint32 = 0xE55D // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (32<-16) 1518 op_CLFI uint32 = 0xC20F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (32) 1519 op_CLFIT uint32 = 0xEC73 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (32<-16) 1520 op_CLFXBR uint32 = 0xB39E // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 32) 1521 op_CLFXTR uint32 = 0xB94B // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 32) 1522 op_CLG uint32 = 0xE321 // FORMAT_RXY1 COMPARE LOGICAL (64) 1523 op_CLGDBR uint32 = 0xB3AD // FORMAT_RRF5 CONVERT TO LOGICAL (long BFP to 64) 1524 op_CLGDTR uint32 = 0xB942 // FORMAT_RRF5 CONVERT TO LOGICAL (long DFP to 64) 1525 op_CLGEBR uint32 = 0xB3AC // FORMAT_RRF5 CONVERT TO LOGICAL (short BFP to 64) 1526 op_CLGF uint32 = 0xE331 // FORMAT_RXY1 COMPARE LOGICAL (64<-32) 1527 op_CLGFI uint32 = 0xC20E // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE (64<-32) 1528 op_CLGFR uint32 = 0xB931 // FORMAT_RRE COMPARE LOGICAL (64<-32) 1529 op_CLGFRL uint32 = 0xC60E // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-32) 1530 op_CLGHRL uint32 = 0xC606 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64<-16) 1531 op_CLGHSI uint32 = 0xE559 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (64<-16) 1532 op_CLGIB uint32 = 0xECFD // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (64<-8) 1533 op_CLGIJ uint32 = 0xEC7D // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (64<-8) 1534 op_CLGIT uint32 = 0xEC71 // FORMAT_RIE1 COMPARE LOGICAL IMMEDIATE AND TRAP (64<-16) 1535 op_CLGR uint32 = 0xB921 // FORMAT_RRE COMPARE LOGICAL (64) 1536 op_CLGRB uint32 = 0xECE5 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (64) 1537 op_CLGRJ uint32 = 0xEC65 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (64) 1538 op_CLGRL uint32 = 0xC60A // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (64) 1539 op_CLGRT uint32 = 0xB961 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (64) 1540 op_CLGT uint32 = 0xEB2B // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (64) 1541 op_CLGXBR uint32 = 0xB3AE // FORMAT_RRF5 CONVERT TO LOGICAL (extended BFP to 64) 1542 op_CLGXTR uint32 = 0xB94A // FORMAT_RRF5 CONVERT TO LOGICAL (extended DFP to 64) 1543 op_CLHF uint32 = 0xE3CF // FORMAT_RXY1 COMPARE LOGICAL HIGH (32) 1544 op_CLHHR uint32 = 0xB9CF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1545 op_CLHHSI uint32 = 0xE555 // FORMAT_SIL COMPARE LOGICAL IMMEDIATE (16) 1546 op_CLHLR uint32 = 0xB9DF // FORMAT_RRE COMPARE LOGICAL HIGH (32) 1547 op_CLHRL uint32 = 0xC607 // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32<-16) 1548 op_CLI uint32 = 0x9500 // FORMAT_SI COMPARE LOGICAL (immediate) 1549 op_CLIB uint32 = 0xECFF // FORMAT_RIS COMPARE LOGICAL IMMEDIATE AND BRANCH (32<-8) 1550 op_CLIH uint32 = 0xCC0F // FORMAT_RIL1 COMPARE LOGICAL IMMEDIATE HIGH (32) 1551 op_CLIJ uint32 = 0xEC7F // FORMAT_RIE3 COMPARE LOGICAL IMMEDIATE AND BRANCH RELATIVE (32<-8) 1552 op_CLIY uint32 = 0xEB55 // FORMAT_SIY COMPARE LOGICAL (immediate) 1553 op_CLM uint32 = 0xBD00 // FORMAT_RS2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1554 op_CLMH uint32 = 0xEB20 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (high) 1555 op_CLMY uint32 = 0xEB21 // FORMAT_RSY2 COMPARE LOGICAL CHAR. UNDER MASK (low) 1556 op_CLR uint32 = 0x1500 // FORMAT_RR COMPARE LOGICAL (32) 1557 op_CLRB uint32 = 0xECF7 // FORMAT_RRS COMPARE LOGICAL AND BRANCH (32) 1558 op_CLRJ uint32 = 0xEC77 // FORMAT_RIE2 COMPARE LOGICAL AND BRANCH RELATIVE (32) 1559 op_CLRL uint32 = 0xC60F // FORMAT_RIL2 COMPARE LOGICAL RELATIVE LONG (32) 1560 op_CLRT uint32 = 0xB973 // FORMAT_RRF3 COMPARE LOGICAL AND TRAP (32) 1561 op_CLST uint32 = 0xB25D // FORMAT_RRE COMPARE LOGICAL STRING 1562 op_CLT uint32 = 0xEB23 // FORMAT_RSY2 COMPARE LOGICAL AND TRAP (32) 1563 op_CLY uint32 = 0xE355 // FORMAT_RXY1 COMPARE LOGICAL (32) 1564 op_CMPSC uint32 = 0xB263 // FORMAT_RRE COMPRESSION CALL 1565 op_CP uint32 = 0xF900 // FORMAT_SS2 COMPARE DECIMAL 1566 op_CPSDR uint32 = 0xB372 // FORMAT_RRF2 COPY SIGN (long) 1567 op_CPYA uint32 = 0xB24D // FORMAT_RRE COPY ACCESS 1568 op_CR uint32 = 0x1900 // FORMAT_RR COMPARE (32) 1569 op_CRB uint32 = 0xECF6 // FORMAT_RRS COMPARE AND BRANCH (32) 1570 op_CRDTE uint32 = 0xB98F // FORMAT_RRF2 COMPARE AND REPLACE DAT TABLE ENTRY 1571 op_CRJ uint32 = 0xEC76 // FORMAT_RIE2 COMPARE AND BRANCH RELATIVE (32) 1572 op_CRL uint32 = 0xC60D // FORMAT_RIL2 COMPARE RELATIVE LONG (32) 1573 op_CRT uint32 = 0xB972 // FORMAT_RRF3 COMPARE AND TRAP (32) 1574 op_CS uint32 = 0xBA00 // FORMAT_RS1 COMPARE AND SWAP (32) 1575 op_CSCH uint32 = 0xB230 // FORMAT_S CLEAR SUBCHANNEL 1576 op_CSDTR uint32 = 0xB3E3 // FORMAT_RRF4 CONVERT TO SIGNED PACKED (long DFP to 64) 1577 op_CSG uint32 = 0xEB30 // FORMAT_RSY1 COMPARE AND SWAP (64) 1578 op_CSP uint32 = 0xB250 // FORMAT_RRE COMPARE AND SWAP AND PURGE 1579 op_CSPG uint32 = 0xB98A // FORMAT_RRE COMPARE AND SWAP AND PURGE 1580 op_CSST uint32 = 0xC802 // FORMAT_SSF COMPARE AND SWAP AND STORE 1581 op_CSXTR uint32 = 0xB3EB // FORMAT_RRF4 CONVERT TO SIGNED PACKED (extended DFP to 128) 1582 op_CSY uint32 = 0xEB14 // FORMAT_RSY1 COMPARE AND SWAP (32) 1583 op_CU12 uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-16 1584 op_CU14 uint32 = 0xB9B0 // FORMAT_RRF3 CONVERT UTF-8 TO UTF-32 1585 op_CU21 uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-8 1586 op_CU24 uint32 = 0xB9B1 // FORMAT_RRF3 CONVERT UTF-16 TO UTF-32 1587 op_CU41 uint32 = 0xB9B2 // FORMAT_RRE CONVERT UTF-32 TO UTF-8 1588 op_CU42 uint32 = 0xB9B3 // FORMAT_RRE CONVERT UTF-32 TO UTF-16 1589 op_CUDTR uint32 = 0xB3E2 // FORMAT_RRE CONVERT TO UNSIGNED PACKED (long DFP to 64) 1590 op_CUSE uint32 = 0xB257 // FORMAT_RRE COMPARE UNTIL SUBSTRING EQUAL 1591 op_CUTFU uint32 = 0xB2A7 // FORMAT_RRF3 CONVERT UTF-8 TO UNICODE 1592 op_CUUTF uint32 = 0xB2A6 // FORMAT_RRF3 CONVERT UNICODE TO UTF-8 1593 op_CUXTR uint32 = 0xB3EA // FORMAT_RRE CONVERT TO UNSIGNED PACKED (extended DFP to 128) 1594 op_CVB uint32 = 0x4F00 // FORMAT_RX1 CONVERT TO BINARY (32) 1595 op_CVBG uint32 = 0xE30E // FORMAT_RXY1 CONVERT TO BINARY (64) 1596 op_CVBY uint32 = 0xE306 // FORMAT_RXY1 CONVERT TO BINARY (32) 1597 op_CVD uint32 = 0x4E00 // FORMAT_RX1 CONVERT TO DECIMAL (32) 1598 op_CVDG uint32 = 0xE32E // FORMAT_RXY1 CONVERT TO DECIMAL (64) 1599 op_CVDY uint32 = 0xE326 // FORMAT_RXY1 CONVERT TO DECIMAL (32) 1600 op_CXBR uint32 = 0xB349 // FORMAT_RRE COMPARE (extended BFP) 1601 op_CXFBR uint32 = 0xB396 // FORMAT_RRE CONVERT FROM FIXED (32 to extended BFP) 1602 op_CXFBRA uint32 = 0xB396 // FORMAT_RRF5 CONVERT FROM FIXED (32 to extended BFP) 1603 op_CXFR uint32 = 0xB3B6 // FORMAT_RRE CONVERT FROM FIXED (32 to extended HFP) 1604 op_CXFTR uint32 = 0xB959 // FORMAT_RRE CONVERT FROM FIXED (32 to extended DFP) 1605 op_CXGBR uint32 = 0xB3A6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended BFP) 1606 op_CXGBRA uint32 = 0xB3A6 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended BFP) 1607 op_CXGR uint32 = 0xB3C6 // FORMAT_RRE CONVERT FROM FIXED (64 to extended HFP) 1608 op_CXGTR uint32 = 0xB3F9 // FORMAT_RRE CONVERT FROM FIXED (64 to extended DFP) 1609 op_CXGTRA uint32 = 0xB3F9 // FORMAT_RRF5 CONVERT FROM FIXED (64 to extended DFP) 1610 op_CXLFBR uint32 = 0xB392 // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended BFP) 1611 op_CXLFTR uint32 = 0xB95B // FORMAT_RRF5 CONVERT FROM LOGICAL (32 to extended DFP) 1612 op_CXLGBR uint32 = 0xB3A2 // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended BFP) 1613 op_CXLGTR uint32 = 0xB95A // FORMAT_RRF5 CONVERT FROM LOGICAL (64 to extended DFP) 1614 op_CXR uint32 = 0xB369 // FORMAT_RRE COMPARE (extended HFP) 1615 op_CXSTR uint32 = 0xB3FB // FORMAT_RRE CONVERT FROM SIGNED PACKED (128 to extended DFP) 1616 op_CXTR uint32 = 0xB3EC // FORMAT_RRE COMPARE (extended DFP) 1617 op_CXUTR uint32 = 0xB3FA // FORMAT_RRE CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) 1618 op_CXZT uint32 = 0xEDAB // FORMAT_RSL CONVERT FROM ZONED (to extended DFP) 1619 op_CY uint32 = 0xE359 // FORMAT_RXY1 COMPARE (32) 1620 op_CZDT uint32 = 0xEDA8 // FORMAT_RSL CONVERT TO ZONED (from long DFP) 1621 op_CZXT uint32 = 0xEDA9 // FORMAT_RSL CONVERT TO ZONED (from extended DFP) 1622 op_D uint32 = 0x5D00 // FORMAT_RX1 DIVIDE (32<-64) 1623 op_DD uint32 = 0x6D00 // FORMAT_RX1 DIVIDE (long HFP) 1624 op_DDB uint32 = 0xED1D // FORMAT_RXE DIVIDE (long BFP) 1625 op_DDBR uint32 = 0xB31D // FORMAT_RRE DIVIDE (long BFP) 1626 op_DDR uint32 = 0x2D00 // FORMAT_RR DIVIDE (long HFP) 1627 op_DDTR uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1628 op_DDTRA uint32 = 0xB3D1 // FORMAT_RRF1 DIVIDE (long DFP) 1629 op_DE uint32 = 0x7D00 // FORMAT_RX1 DIVIDE (short HFP) 1630 op_DEB uint32 = 0xED0D // FORMAT_RXE DIVIDE (short BFP) 1631 op_DEBR uint32 = 0xB30D // FORMAT_RRE DIVIDE (short BFP) 1632 op_DER uint32 = 0x3D00 // FORMAT_RR DIVIDE (short HFP) 1633 op_DIDBR uint32 = 0xB35B // FORMAT_RRF2 DIVIDE TO INTEGER (long BFP) 1634 op_DIEBR uint32 = 0xB353 // FORMAT_RRF2 DIVIDE TO INTEGER (short BFP) 1635 op_DL uint32 = 0xE397 // FORMAT_RXY1 DIVIDE LOGICAL (32<-64) 1636 op_DLG uint32 = 0xE387 // FORMAT_RXY1 DIVIDE LOGICAL (64<-128) 1637 op_DLGR uint32 = 0xB987 // FORMAT_RRE DIVIDE LOGICAL (64<-128) 1638 op_DLR uint32 = 0xB997 // FORMAT_RRE DIVIDE LOGICAL (32<-64) 1639 op_DP uint32 = 0xFD00 // FORMAT_SS2 DIVIDE DECIMAL 1640 op_DR uint32 = 0x1D00 // FORMAT_RR DIVIDE (32<-64) 1641 op_DSG uint32 = 0xE30D // FORMAT_RXY1 DIVIDE SINGLE (64) 1642 op_DSGF uint32 = 0xE31D // FORMAT_RXY1 DIVIDE SINGLE (64<-32) 1643 op_DSGFR uint32 = 0xB91D // FORMAT_RRE DIVIDE SINGLE (64<-32) 1644 op_DSGR uint32 = 0xB90D // FORMAT_RRE DIVIDE SINGLE (64) 1645 op_DXBR uint32 = 0xB34D // FORMAT_RRE DIVIDE (extended BFP) 1646 op_DXR uint32 = 0xB22D // FORMAT_RRE DIVIDE (extended HFP) 1647 op_DXTR uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1648 op_DXTRA uint32 = 0xB3D9 // FORMAT_RRF1 DIVIDE (extended DFP) 1649 op_EAR uint32 = 0xB24F // FORMAT_RRE EXTRACT ACCESS 1650 op_ECAG uint32 = 0xEB4C // FORMAT_RSY1 EXTRACT CACHE ATTRIBUTE 1651 op_ECTG uint32 = 0xC801 // FORMAT_SSF EXTRACT CPU TIME 1652 op_ED uint32 = 0xDE00 // FORMAT_SS1 EDIT 1653 op_EDMK uint32 = 0xDF00 // FORMAT_SS1 EDIT AND MARK 1654 op_EEDTR uint32 = 0xB3E5 // FORMAT_RRE EXTRACT BIASED EXPONENT (long DFP to 64) 1655 op_EEXTR uint32 = 0xB3ED // FORMAT_RRE EXTRACT BIASED EXPONENT (extended DFP to 64) 1656 op_EFPC uint32 = 0xB38C // FORMAT_RRE EXTRACT FPC 1657 op_EPAIR uint32 = 0xB99A // FORMAT_RRE EXTRACT PRIMARY ASN AND INSTANCE 1658 op_EPAR uint32 = 0xB226 // FORMAT_RRE EXTRACT PRIMARY ASN 1659 op_EPSW uint32 = 0xB98D // FORMAT_RRE EXTRACT PSW 1660 op_EREG uint32 = 0xB249 // FORMAT_RRE EXTRACT STACKED REGISTERS (32) 1661 op_EREGG uint32 = 0xB90E // FORMAT_RRE EXTRACT STACKED REGISTERS (64) 1662 op_ESAIR uint32 = 0xB99B // FORMAT_RRE EXTRACT SECONDARY ASN AND INSTANCE 1663 op_ESAR uint32 = 0xB227 // FORMAT_RRE EXTRACT SECONDARY ASN 1664 op_ESDTR uint32 = 0xB3E7 // FORMAT_RRE EXTRACT SIGNIFICANCE (long DFP) 1665 op_ESEA uint32 = 0xB99D // FORMAT_RRE EXTRACT AND SET EXTENDED AUTHORITY 1666 op_ESTA uint32 = 0xB24A // FORMAT_RRE EXTRACT STACKED STATE 1667 op_ESXTR uint32 = 0xB3EF // FORMAT_RRE EXTRACT SIGNIFICANCE (extended DFP) 1668 op_ETND uint32 = 0xB2EC // FORMAT_RRE EXTRACT TRANSACTION NESTING DEPTH 1669 op_EX uint32 = 0x4400 // FORMAT_RX1 EXECUTE 1670 op_EXRL uint32 = 0xC600 // FORMAT_RIL2 EXECUTE RELATIVE LONG 1671 op_FIDBR uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1672 op_FIDBRA uint32 = 0xB35F // FORMAT_RRF5 LOAD FP INTEGER (long BFP) 1673 op_FIDR uint32 = 0xB37F // FORMAT_RRE LOAD FP INTEGER (long HFP) 1674 op_FIDTR uint32 = 0xB3D7 // FORMAT_RRF5 LOAD FP INTEGER (long DFP) 1675 op_FIEBR uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1676 op_FIEBRA uint32 = 0xB357 // FORMAT_RRF5 LOAD FP INTEGER (short BFP) 1677 op_FIER uint32 = 0xB377 // FORMAT_RRE LOAD FP INTEGER (short HFP) 1678 op_FIXBR uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1679 op_FIXBRA uint32 = 0xB347 // FORMAT_RRF5 LOAD FP INTEGER (extended BFP) 1680 op_FIXR uint32 = 0xB367 // FORMAT_RRE LOAD FP INTEGER (extended HFP) 1681 op_FIXTR uint32 = 0xB3DF // FORMAT_RRF5 LOAD FP INTEGER (extended DFP) 1682 op_FLOGR uint32 = 0xB983 // FORMAT_RRE FIND LEFTMOST ONE 1683 op_HDR uint32 = 0x2400 // FORMAT_RR HALVE (long HFP) 1684 op_HER uint32 = 0x3400 // FORMAT_RR HALVE (short HFP) 1685 op_HSCH uint32 = 0xB231 // FORMAT_S HALT SUBCHANNEL 1686 op_IAC uint32 = 0xB224 // FORMAT_RRE INSERT ADDRESS SPACE CONTROL 1687 op_IC uint32 = 0x4300 // FORMAT_RX1 INSERT CHARACTER 1688 op_ICM uint32 = 0xBF00 // FORMAT_RS2 INSERT CHARACTERS UNDER MASK (low) 1689 op_ICMH uint32 = 0xEB80 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (high) 1690 op_ICMY uint32 = 0xEB81 // FORMAT_RSY2 INSERT CHARACTERS UNDER MASK (low) 1691 op_ICY uint32 = 0xE373 // FORMAT_RXY1 INSERT CHARACTER 1692 op_IDTE uint32 = 0xB98E // FORMAT_RRF2 INVALIDATE DAT TABLE ENTRY 1693 op_IEDTR uint32 = 0xB3F6 // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to long DFP) 1694 op_IEXTR uint32 = 0xB3FE // FORMAT_RRF2 INSERT BIASED EXPONENT (64 to extended DFP) 1695 op_IIHF uint32 = 0xC008 // FORMAT_RIL1 INSERT IMMEDIATE (high) 1696 op_IIHH uint32 = 0xA500 // FORMAT_RI1 INSERT IMMEDIATE (high high) 1697 op_IIHL uint32 = 0xA501 // FORMAT_RI1 INSERT IMMEDIATE (high low) 1698 op_IILF uint32 = 0xC009 // FORMAT_RIL1 INSERT IMMEDIATE (low) 1699 op_IILH uint32 = 0xA502 // FORMAT_RI1 INSERT IMMEDIATE (low high) 1700 op_IILL uint32 = 0xA503 // FORMAT_RI1 INSERT IMMEDIATE (low low) 1701 op_IPK uint32 = 0xB20B // FORMAT_S INSERT PSW KEY 1702 op_IPM uint32 = 0xB222 // FORMAT_RRE INSERT PROGRAM MASK 1703 op_IPTE uint32 = 0xB221 // FORMAT_RRF1 INVALIDATE PAGE TABLE ENTRY 1704 op_ISKE uint32 = 0xB229 // FORMAT_RRE INSERT STORAGE KEY EXTENDED 1705 op_IVSK uint32 = 0xB223 // FORMAT_RRE INSERT VIRTUAL STORAGE KEY 1706 op_KDB uint32 = 0xED18 // FORMAT_RXE COMPARE AND SIGNAL (long BFP) 1707 op_KDBR uint32 = 0xB318 // FORMAT_RRE COMPARE AND SIGNAL (long BFP) 1708 op_KDTR uint32 = 0xB3E0 // FORMAT_RRE COMPARE AND SIGNAL (long DFP) 1709 op_KEB uint32 = 0xED08 // FORMAT_RXE COMPARE AND SIGNAL (short BFP) 1710 op_KEBR uint32 = 0xB308 // FORMAT_RRE COMPARE AND SIGNAL (short BFP) 1711 op_KIMD uint32 = 0xB93E // FORMAT_RRE COMPUTE INTERMEDIATE MESSAGE DIGEST 1712 op_KLMD uint32 = 0xB93F // FORMAT_RRE COMPUTE LAST MESSAGE DIGEST 1713 op_KM uint32 = 0xB92E // FORMAT_RRE CIPHER MESSAGE 1714 op_KMAC uint32 = 0xB91E // FORMAT_RRE COMPUTE MESSAGE AUTHENTICATION CODE 1715 op_KMC uint32 = 0xB92F // FORMAT_RRE CIPHER MESSAGE WITH CHAINING 1716 op_KMCTR uint32 = 0xB92D // FORMAT_RRF2 CIPHER MESSAGE WITH COUNTER 1717 op_KMF uint32 = 0xB92A // FORMAT_RRE CIPHER MESSAGE WITH CFB 1718 op_KMO uint32 = 0xB92B // FORMAT_RRE CIPHER MESSAGE WITH OFB 1719 op_KXBR uint32 = 0xB348 // FORMAT_RRE COMPARE AND SIGNAL (extended BFP) 1720 op_KXTR uint32 = 0xB3E8 // FORMAT_RRE COMPARE AND SIGNAL (extended DFP) 1721 op_L uint32 = 0x5800 // FORMAT_RX1 LOAD (32) 1722 op_LA uint32 = 0x4100 // FORMAT_RX1 LOAD ADDRESS 1723 op_LAA uint32 = 0xEBF8 // FORMAT_RSY1 LOAD AND ADD (32) 1724 op_LAAG uint32 = 0xEBE8 // FORMAT_RSY1 LOAD AND ADD (64) 1725 op_LAAL uint32 = 0xEBFA // FORMAT_RSY1 LOAD AND ADD LOGICAL (32) 1726 op_LAALG uint32 = 0xEBEA // FORMAT_RSY1 LOAD AND ADD LOGICAL (64) 1727 op_LAE uint32 = 0x5100 // FORMAT_RX1 LOAD ADDRESS EXTENDED 1728 op_LAEY uint32 = 0xE375 // FORMAT_RXY1 LOAD ADDRESS EXTENDED 1729 op_LAM uint32 = 0x9A00 // FORMAT_RS1 LOAD ACCESS MULTIPLE 1730 op_LAMY uint32 = 0xEB9A // FORMAT_RSY1 LOAD ACCESS MULTIPLE 1731 op_LAN uint32 = 0xEBF4 // FORMAT_RSY1 LOAD AND AND (32) 1732 op_LANG uint32 = 0xEBE4 // FORMAT_RSY1 LOAD AND AND (64) 1733 op_LAO uint32 = 0xEBF6 // FORMAT_RSY1 LOAD AND OR (32) 1734 op_LAOG uint32 = 0xEBE6 // FORMAT_RSY1 LOAD AND OR (64) 1735 op_LARL uint32 = 0xC000 // FORMAT_RIL2 LOAD ADDRESS RELATIVE LONG 1736 op_LASP uint32 = 0xE500 // FORMAT_SSE LOAD ADDRESS SPACE PARAMETERS 1737 op_LAT uint32 = 0xE39F // FORMAT_RXY1 LOAD AND TRAP (32L<-32) 1738 op_LAX uint32 = 0xEBF7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (32) 1739 op_LAXG uint32 = 0xEBE7 // FORMAT_RSY1 LOAD AND EXCLUSIVE OR (64) 1740 op_LAY uint32 = 0xE371 // FORMAT_RXY1 LOAD ADDRESS 1741 op_LB uint32 = 0xE376 // FORMAT_RXY1 LOAD BYTE (32) 1742 op_LBH uint32 = 0xE3C0 // FORMAT_RXY1 LOAD BYTE HIGH (32<-8) 1743 op_LBR uint32 = 0xB926 // FORMAT_RRE LOAD BYTE (32) 1744 op_LCDBR uint32 = 0xB313 // FORMAT_RRE LOAD COMPLEMENT (long BFP) 1745 op_LCDFR uint32 = 0xB373 // FORMAT_RRE LOAD COMPLEMENT (long) 1746 op_LCDR uint32 = 0x2300 // FORMAT_RR LOAD COMPLEMENT (long HFP) 1747 op_LCEBR uint32 = 0xB303 // FORMAT_RRE LOAD COMPLEMENT (short BFP) 1748 op_LCER uint32 = 0x3300 // FORMAT_RR LOAD COMPLEMENT (short HFP) 1749 op_LCGFR uint32 = 0xB913 // FORMAT_RRE LOAD COMPLEMENT (64<-32) 1750 op_LCGR uint32 = 0xB903 // FORMAT_RRE LOAD COMPLEMENT (64) 1751 op_LCR uint32 = 0x1300 // FORMAT_RR LOAD COMPLEMENT (32) 1752 op_LCTL uint32 = 0xB700 // FORMAT_RS1 LOAD CONTROL (32) 1753 op_LCTLG uint32 = 0xEB2F // FORMAT_RSY1 LOAD CONTROL (64) 1754 op_LCXBR uint32 = 0xB343 // FORMAT_RRE LOAD COMPLEMENT (extended BFP) 1755 op_LCXR uint32 = 0xB363 // FORMAT_RRE LOAD COMPLEMENT (extended HFP) 1756 op_LD uint32 = 0x6800 // FORMAT_RX1 LOAD (long) 1757 op_LDE uint32 = 0xED24 // FORMAT_RXE LOAD LENGTHENED (short to long HFP) 1758 op_LDEB uint32 = 0xED04 // FORMAT_RXE LOAD LENGTHENED (short to long BFP) 1759 op_LDEBR uint32 = 0xB304 // FORMAT_RRE LOAD LENGTHENED (short to long BFP) 1760 op_LDER uint32 = 0xB324 // FORMAT_RRE LOAD LENGTHENED (short to long HFP) 1761 op_LDETR uint32 = 0xB3D4 // FORMAT_RRF4 LOAD LENGTHENED (short to long DFP) 1762 op_LDGR uint32 = 0xB3C1 // FORMAT_RRE LOAD FPR FROM GR (64 to long) 1763 op_LDR uint32 = 0x2800 // FORMAT_RR LOAD (long) 1764 op_LDXBR uint32 = 0xB345 // FORMAT_RRE LOAD ROUNDED (extended to long BFP) 1765 op_LDXBRA uint32 = 0xB345 // FORMAT_RRF5 LOAD ROUNDED (extended to long BFP) 1766 op_LDXR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1767 op_LDXTR uint32 = 0xB3DD // FORMAT_RRF5 LOAD ROUNDED (extended to long DFP) 1768 op_LDY uint32 = 0xED65 // FORMAT_RXY1 LOAD (long) 1769 op_LE uint32 = 0x7800 // FORMAT_RX1 LOAD (short) 1770 op_LEDBR uint32 = 0xB344 // FORMAT_RRE LOAD ROUNDED (long to short BFP) 1771 op_LEDBRA uint32 = 0xB344 // FORMAT_RRF5 LOAD ROUNDED (long to short BFP) 1772 op_LEDR uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1773 op_LEDTR uint32 = 0xB3D5 // FORMAT_RRF5 LOAD ROUNDED (long to short DFP) 1774 op_LER uint32 = 0x3800 // FORMAT_RR LOAD (short) 1775 op_LEXBR uint32 = 0xB346 // FORMAT_RRE LOAD ROUNDED (extended to short BFP) 1776 op_LEXBRA uint32 = 0xB346 // FORMAT_RRF5 LOAD ROUNDED (extended to short BFP) 1777 op_LEXR uint32 = 0xB366 // FORMAT_RRE LOAD ROUNDED (extended to short HFP) 1778 op_LEY uint32 = 0xED64 // FORMAT_RXY1 LOAD (short) 1779 op_LFAS uint32 = 0xB2BD // FORMAT_S LOAD FPC AND SIGNAL 1780 op_LFH uint32 = 0xE3CA // FORMAT_RXY1 LOAD HIGH (32) 1781 op_LFHAT uint32 = 0xE3C8 // FORMAT_RXY1 LOAD HIGH AND TRAP (32H<-32) 1782 op_LFPC uint32 = 0xB29D // FORMAT_S LOAD FPC 1783 op_LG uint32 = 0xE304 // FORMAT_RXY1 LOAD (64) 1784 op_LGAT uint32 = 0xE385 // FORMAT_RXY1 LOAD AND TRAP (64) 1785 op_LGB uint32 = 0xE377 // FORMAT_RXY1 LOAD BYTE (64) 1786 op_LGBR uint32 = 0xB906 // FORMAT_RRE LOAD BYTE (64) 1787 op_LGDR uint32 = 0xB3CD // FORMAT_RRE LOAD GR FROM FPR (long to 64) 1788 op_LGF uint32 = 0xE314 // FORMAT_RXY1 LOAD (64<-32) 1789 op_LGFI uint32 = 0xC001 // FORMAT_RIL1 LOAD IMMEDIATE (64<-32) 1790 op_LGFR uint32 = 0xB914 // FORMAT_RRE LOAD (64<-32) 1791 op_LGFRL uint32 = 0xC40C // FORMAT_RIL2 LOAD RELATIVE LONG (64<-32) 1792 op_LGH uint32 = 0xE315 // FORMAT_RXY1 LOAD HALFWORD (64) 1793 op_LGHI uint32 = 0xA709 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (64) 1794 op_LGHR uint32 = 0xB907 // FORMAT_RRE LOAD HALFWORD (64) 1795 op_LGHRL uint32 = 0xC404 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (64<-16) 1796 op_LGR uint32 = 0xB904 // FORMAT_RRE LOAD (64) 1797 op_LGRL uint32 = 0xC408 // FORMAT_RIL2 LOAD RELATIVE LONG (64) 1798 op_LH uint32 = 0x4800 // FORMAT_RX1 LOAD HALFWORD (32) 1799 op_LHH uint32 = 0xE3C4 // FORMAT_RXY1 LOAD HALFWORD HIGH (32<-16) 1800 op_LHI uint32 = 0xA708 // FORMAT_RI1 LOAD HALFWORD IMMEDIATE (32) 1801 op_LHR uint32 = 0xB927 // FORMAT_RRE LOAD HALFWORD (32) 1802 op_LHRL uint32 = 0xC405 // FORMAT_RIL2 LOAD HALFWORD RELATIVE LONG (32<-16) 1803 op_LHY uint32 = 0xE378 // FORMAT_RXY1 LOAD HALFWORD (32) 1804 op_LLC uint32 = 0xE394 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (32) 1805 op_LLCH uint32 = 0xE3C2 // FORMAT_RXY1 LOAD LOGICAL CHARACTER HIGH (32<-8) 1806 op_LLCR uint32 = 0xB994 // FORMAT_RRE LOAD LOGICAL CHARACTER (32) 1807 op_LLGC uint32 = 0xE390 // FORMAT_RXY1 LOAD LOGICAL CHARACTER (64) 1808 op_LLGCR uint32 = 0xB984 // FORMAT_RRE LOAD LOGICAL CHARACTER (64) 1809 op_LLGF uint32 = 0xE316 // FORMAT_RXY1 LOAD LOGICAL (64<-32) 1810 op_LLGFAT uint32 = 0xE39D // FORMAT_RXY1 LOAD LOGICAL AND TRAP (64<-32) 1811 op_LLGFR uint32 = 0xB916 // FORMAT_RRE LOAD LOGICAL (64<-32) 1812 op_LLGFRL uint32 = 0xC40E // FORMAT_RIL2 LOAD LOGICAL RELATIVE LONG (64<-32) 1813 op_LLGH uint32 = 0xE391 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (64) 1814 op_LLGHR uint32 = 0xB985 // FORMAT_RRE LOAD LOGICAL HALFWORD (64) 1815 op_LLGHRL uint32 = 0xC406 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (64<-16) 1816 op_LLGT uint32 = 0xE317 // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS 1817 op_LLGTAT uint32 = 0xE39C // FORMAT_RXY1 LOAD LOGICAL THIRTY ONE BITS AND TRAP (64<-31) 1818 op_LLGTR uint32 = 0xB917 // FORMAT_RRE LOAD LOGICAL THIRTY ONE BITS 1819 op_LLH uint32 = 0xE395 // FORMAT_RXY1 LOAD LOGICAL HALFWORD (32) 1820 op_LLHH uint32 = 0xE3C6 // FORMAT_RXY1 LOAD LOGICAL HALFWORD HIGH (32<-16) 1821 op_LLHR uint32 = 0xB995 // FORMAT_RRE LOAD LOGICAL HALFWORD (32) 1822 op_LLHRL uint32 = 0xC402 // FORMAT_RIL2 LOAD LOGICAL HALFWORD RELATIVE LONG (32<-16) 1823 op_LLIHF uint32 = 0xC00E // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (high) 1824 op_LLIHH uint32 = 0xA50C // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high high) 1825 op_LLIHL uint32 = 0xA50D // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (high low) 1826 op_LLILF uint32 = 0xC00F // FORMAT_RIL1 LOAD LOGICAL IMMEDIATE (low) 1827 op_LLILH uint32 = 0xA50E // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low high) 1828 op_LLILL uint32 = 0xA50F // FORMAT_RI1 LOAD LOGICAL IMMEDIATE (low low) 1829 op_LM uint32 = 0x9800 // FORMAT_RS1 LOAD MULTIPLE (32) 1830 op_LMD uint32 = 0xEF00 // FORMAT_SS5 LOAD MULTIPLE DISJOINT 1831 op_LMG uint32 = 0xEB04 // FORMAT_RSY1 LOAD MULTIPLE (64) 1832 op_LMH uint32 = 0xEB96 // FORMAT_RSY1 LOAD MULTIPLE HIGH 1833 op_LMY uint32 = 0xEB98 // FORMAT_RSY1 LOAD MULTIPLE (32) 1834 op_LNDBR uint32 = 0xB311 // FORMAT_RRE LOAD NEGATIVE (long BFP) 1835 op_LNDFR uint32 = 0xB371 // FORMAT_RRE LOAD NEGATIVE (long) 1836 op_LNDR uint32 = 0x2100 // FORMAT_RR LOAD NEGATIVE (long HFP) 1837 op_LNEBR uint32 = 0xB301 // FORMAT_RRE LOAD NEGATIVE (short BFP) 1838 op_LNER uint32 = 0x3100 // FORMAT_RR LOAD NEGATIVE (short HFP) 1839 op_LNGFR uint32 = 0xB911 // FORMAT_RRE LOAD NEGATIVE (64<-32) 1840 op_LNGR uint32 = 0xB901 // FORMAT_RRE LOAD NEGATIVE (64) 1841 op_LNR uint32 = 0x1100 // FORMAT_RR LOAD NEGATIVE (32) 1842 op_LNXBR uint32 = 0xB341 // FORMAT_RRE LOAD NEGATIVE (extended BFP) 1843 op_LNXR uint32 = 0xB361 // FORMAT_RRE LOAD NEGATIVE (extended HFP) 1844 op_LOC uint32 = 0xEBF2 // FORMAT_RSY2 LOAD ON CONDITION (32) 1845 op_LOCG uint32 = 0xEBE2 // FORMAT_RSY2 LOAD ON CONDITION (64) 1846 op_LOCGR uint32 = 0xB9E2 // FORMAT_RRF3 LOAD ON CONDITION (64) 1847 op_LOCR uint32 = 0xB9F2 // FORMAT_RRF3 LOAD ON CONDITION (32) 1848 op_LPD uint32 = 0xC804 // FORMAT_SSF LOAD PAIR DISJOINT (32) 1849 op_LPDBR uint32 = 0xB310 // FORMAT_RRE LOAD POSITIVE (long BFP) 1850 op_LPDFR uint32 = 0xB370 // FORMAT_RRE LOAD POSITIVE (long) 1851 op_LPDG uint32 = 0xC805 // FORMAT_SSF LOAD PAIR DISJOINT (64) 1852 op_LPDR uint32 = 0x2000 // FORMAT_RR LOAD POSITIVE (long HFP) 1853 op_LPEBR uint32 = 0xB300 // FORMAT_RRE LOAD POSITIVE (short BFP) 1854 op_LPER uint32 = 0x3000 // FORMAT_RR LOAD POSITIVE (short HFP) 1855 op_LPGFR uint32 = 0xB910 // FORMAT_RRE LOAD POSITIVE (64<-32) 1856 op_LPGR uint32 = 0xB900 // FORMAT_RRE LOAD POSITIVE (64) 1857 op_LPQ uint32 = 0xE38F // FORMAT_RXY1 LOAD PAIR FROM QUADWORD 1858 op_LPR uint32 = 0x1000 // FORMAT_RR LOAD POSITIVE (32) 1859 op_LPSW uint32 = 0x8200 // FORMAT_S LOAD PSW 1860 op_LPSWE uint32 = 0xB2B2 // FORMAT_S LOAD PSW EXTENDED 1861 op_LPTEA uint32 = 0xB9AA // FORMAT_RRF2 LOAD PAGE TABLE ENTRY ADDRESS 1862 op_LPXBR uint32 = 0xB340 // FORMAT_RRE LOAD POSITIVE (extended BFP) 1863 op_LPXR uint32 = 0xB360 // FORMAT_RRE LOAD POSITIVE (extended HFP) 1864 op_LR uint32 = 0x1800 // FORMAT_RR LOAD (32) 1865 op_LRA uint32 = 0xB100 // FORMAT_RX1 LOAD REAL ADDRESS (32) 1866 op_LRAG uint32 = 0xE303 // FORMAT_RXY1 LOAD REAL ADDRESS (64) 1867 op_LRAY uint32 = 0xE313 // FORMAT_RXY1 LOAD REAL ADDRESS (32) 1868 op_LRDR uint32 = 0x2500 // FORMAT_RR LOAD ROUNDED (extended to long HFP) 1869 op_LRER uint32 = 0x3500 // FORMAT_RR LOAD ROUNDED (long to short HFP) 1870 op_LRL uint32 = 0xC40D // FORMAT_RIL2 LOAD RELATIVE LONG (32) 1871 op_LRV uint32 = 0xE31E // FORMAT_RXY1 LOAD REVERSED (32) 1872 op_LRVG uint32 = 0xE30F // FORMAT_RXY1 LOAD REVERSED (64) 1873 op_LRVGR uint32 = 0xB90F // FORMAT_RRE LOAD REVERSED (64) 1874 op_LRVH uint32 = 0xE31F // FORMAT_RXY1 LOAD REVERSED (16) 1875 op_LRVR uint32 = 0xB91F // FORMAT_RRE LOAD REVERSED (32) 1876 op_LT uint32 = 0xE312 // FORMAT_RXY1 LOAD AND TEST (32) 1877 op_LTDBR uint32 = 0xB312 // FORMAT_RRE LOAD AND TEST (long BFP) 1878 op_LTDR uint32 = 0x2200 // FORMAT_RR LOAD AND TEST (long HFP) 1879 op_LTDTR uint32 = 0xB3D6 // FORMAT_RRE LOAD AND TEST (long DFP) 1880 op_LTEBR uint32 = 0xB302 // FORMAT_RRE LOAD AND TEST (short BFP) 1881 op_LTER uint32 = 0x3200 // FORMAT_RR LOAD AND TEST (short HFP) 1882 op_LTG uint32 = 0xE302 // FORMAT_RXY1 LOAD AND TEST (64) 1883 op_LTGF uint32 = 0xE332 // FORMAT_RXY1 LOAD AND TEST (64<-32) 1884 op_LTGFR uint32 = 0xB912 // FORMAT_RRE LOAD AND TEST (64<-32) 1885 op_LTGR uint32 = 0xB902 // FORMAT_RRE LOAD AND TEST (64) 1886 op_LTR uint32 = 0x1200 // FORMAT_RR LOAD AND TEST (32) 1887 op_LTXBR uint32 = 0xB342 // FORMAT_RRE LOAD AND TEST (extended BFP) 1888 op_LTXR uint32 = 0xB362 // FORMAT_RRE LOAD AND TEST (extended HFP) 1889 op_LTXTR uint32 = 0xB3DE // FORMAT_RRE LOAD AND TEST (extended DFP) 1890 op_LURA uint32 = 0xB24B // FORMAT_RRE LOAD USING REAL ADDRESS (32) 1891 op_LURAG uint32 = 0xB905 // FORMAT_RRE LOAD USING REAL ADDRESS (64) 1892 op_LXD uint32 = 0xED25 // FORMAT_RXE LOAD LENGTHENED (long to extended HFP) 1893 op_LXDB uint32 = 0xED05 // FORMAT_RXE LOAD LENGTHENED (long to extended BFP) 1894 op_LXDBR uint32 = 0xB305 // FORMAT_RRE LOAD LENGTHENED (long to extended BFP) 1895 op_LXDR uint32 = 0xB325 // FORMAT_RRE LOAD LENGTHENED (long to extended HFP) 1896 op_LXDTR uint32 = 0xB3DC // FORMAT_RRF4 LOAD LENGTHENED (long to extended DFP) 1897 op_LXE uint32 = 0xED26 // FORMAT_RXE LOAD LENGTHENED (short to extended HFP) 1898 op_LXEB uint32 = 0xED06 // FORMAT_RXE LOAD LENGTHENED (short to extended BFP) 1899 op_LXEBR uint32 = 0xB306 // FORMAT_RRE LOAD LENGTHENED (short to extended BFP) 1900 op_LXER uint32 = 0xB326 // FORMAT_RRE LOAD LENGTHENED (short to extended HFP) 1901 op_LXR uint32 = 0xB365 // FORMAT_RRE LOAD (extended) 1902 op_LY uint32 = 0xE358 // FORMAT_RXY1 LOAD (32) 1903 op_LZDR uint32 = 0xB375 // FORMAT_RRE LOAD ZERO (long) 1904 op_LZER uint32 = 0xB374 // FORMAT_RRE LOAD ZERO (short) 1905 op_LZXR uint32 = 0xB376 // FORMAT_RRE LOAD ZERO (extended) 1906 op_M uint32 = 0x5C00 // FORMAT_RX1 MULTIPLY (64<-32) 1907 op_MAD uint32 = 0xED3E // FORMAT_RXF MULTIPLY AND ADD (long HFP) 1908 op_MADB uint32 = 0xED1E // FORMAT_RXF MULTIPLY AND ADD (long BFP) 1909 op_MADBR uint32 = 0xB31E // FORMAT_RRD MULTIPLY AND ADD (long BFP) 1910 op_MADR uint32 = 0xB33E // FORMAT_RRD MULTIPLY AND ADD (long HFP) 1911 op_MAE uint32 = 0xED2E // FORMAT_RXF MULTIPLY AND ADD (short HFP) 1912 op_MAEB uint32 = 0xED0E // FORMAT_RXF MULTIPLY AND ADD (short BFP) 1913 op_MAEBR uint32 = 0xB30E // FORMAT_RRD MULTIPLY AND ADD (short BFP) 1914 op_MAER uint32 = 0xB32E // FORMAT_RRD MULTIPLY AND ADD (short HFP) 1915 op_MAY uint32 = 0xED3A // FORMAT_RXF MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1916 op_MAYH uint32 = 0xED3C // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1917 op_MAYHR uint32 = 0xB33C // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. high HFP) 1918 op_MAYL uint32 = 0xED38 // FORMAT_RXF MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1919 op_MAYLR uint32 = 0xB338 // FORMAT_RRD MULTIPLY AND ADD UNNRM. (long to ext. low HFP) 1920 op_MAYR uint32 = 0xB33A // FORMAT_RRD MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) 1921 op_MC uint32 = 0xAF00 // FORMAT_SI MONITOR CALL 1922 op_MD uint32 = 0x6C00 // FORMAT_RX1 MULTIPLY (long HFP) 1923 op_MDB uint32 = 0xED1C // FORMAT_RXE MULTIPLY (long BFP) 1924 op_MDBR uint32 = 0xB31C // FORMAT_RRE MULTIPLY (long BFP) 1925 op_MDE uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1926 op_MDEB uint32 = 0xED0C // FORMAT_RXE MULTIPLY (short to long BFP) 1927 op_MDEBR uint32 = 0xB30C // FORMAT_RRE MULTIPLY (short to long BFP) 1928 op_MDER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1929 op_MDR uint32 = 0x2C00 // FORMAT_RR MULTIPLY (long HFP) 1930 op_MDTR uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1931 op_MDTRA uint32 = 0xB3D0 // FORMAT_RRF1 MULTIPLY (long DFP) 1932 op_ME uint32 = 0x7C00 // FORMAT_RX1 MULTIPLY (short to long HFP) 1933 op_MEE uint32 = 0xED37 // FORMAT_RXE MULTIPLY (short HFP) 1934 op_MEEB uint32 = 0xED17 // FORMAT_RXE MULTIPLY (short BFP) 1935 op_MEEBR uint32 = 0xB317 // FORMAT_RRE MULTIPLY (short BFP) 1936 op_MEER uint32 = 0xB337 // FORMAT_RRE MULTIPLY (short HFP) 1937 op_MER uint32 = 0x3C00 // FORMAT_RR MULTIPLY (short to long HFP) 1938 op_MFY uint32 = 0xE35C // FORMAT_RXY1 MULTIPLY (64<-32) 1939 op_MGHI uint32 = 0xA70D // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (64) 1940 op_MH uint32 = 0x4C00 // FORMAT_RX1 MULTIPLY HALFWORD (32) 1941 op_MHI uint32 = 0xA70C // FORMAT_RI1 MULTIPLY HALFWORD IMMEDIATE (32) 1942 op_MHY uint32 = 0xE37C // FORMAT_RXY1 MULTIPLY HALFWORD (32) 1943 op_ML uint32 = 0xE396 // FORMAT_RXY1 MULTIPLY LOGICAL (64<-32) 1944 op_MLG uint32 = 0xE386 // FORMAT_RXY1 MULTIPLY LOGICAL (128<-64) 1945 op_MLGR uint32 = 0xB986 // FORMAT_RRE MULTIPLY LOGICAL (128<-64) 1946 op_MLR uint32 = 0xB996 // FORMAT_RRE MULTIPLY LOGICAL (64<-32) 1947 op_MP uint32 = 0xFC00 // FORMAT_SS2 MULTIPLY DECIMAL 1948 op_MR uint32 = 0x1C00 // FORMAT_RR MULTIPLY (64<-32) 1949 op_MS uint32 = 0x7100 // FORMAT_RX1 MULTIPLY SINGLE (32) 1950 op_MSCH uint32 = 0xB232 // FORMAT_S MODIFY SUBCHANNEL 1951 op_MSD uint32 = 0xED3F // FORMAT_RXF MULTIPLY AND SUBTRACT (long HFP) 1952 op_MSDB uint32 = 0xED1F // FORMAT_RXF MULTIPLY AND SUBTRACT (long BFP) 1953 op_MSDBR uint32 = 0xB31F // FORMAT_RRD MULTIPLY AND SUBTRACT (long BFP) 1954 op_MSDR uint32 = 0xB33F // FORMAT_RRD MULTIPLY AND SUBTRACT (long HFP) 1955 op_MSE uint32 = 0xED2F // FORMAT_RXF MULTIPLY AND SUBTRACT (short HFP) 1956 op_MSEB uint32 = 0xED0F // FORMAT_RXF MULTIPLY AND SUBTRACT (short BFP) 1957 op_MSEBR uint32 = 0xB30F // FORMAT_RRD MULTIPLY AND SUBTRACT (short BFP) 1958 op_MSER uint32 = 0xB32F // FORMAT_RRD MULTIPLY AND SUBTRACT (short HFP) 1959 op_MSFI uint32 = 0xC201 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (32) 1960 op_MSG uint32 = 0xE30C // FORMAT_RXY1 MULTIPLY SINGLE (64) 1961 op_MSGF uint32 = 0xE31C // FORMAT_RXY1 MULTIPLY SINGLE (64<-32) 1962 op_MSGFI uint32 = 0xC200 // FORMAT_RIL1 MULTIPLY SINGLE IMMEDIATE (64<-32) 1963 op_MSGFR uint32 = 0xB91C // FORMAT_RRE MULTIPLY SINGLE (64<-32) 1964 op_MSGR uint32 = 0xB90C // FORMAT_RRE MULTIPLY SINGLE (64) 1965 op_MSR uint32 = 0xB252 // FORMAT_RRE MULTIPLY SINGLE (32) 1966 op_MSTA uint32 = 0xB247 // FORMAT_RRE MODIFY STACKED STATE 1967 op_MSY uint32 = 0xE351 // FORMAT_RXY1 MULTIPLY SINGLE (32) 1968 op_MVC uint32 = 0xD200 // FORMAT_SS1 MOVE (character) 1969 op_MVCDK uint32 = 0xE50F // FORMAT_SSE MOVE WITH DESTINATION KEY 1970 op_MVCIN uint32 = 0xE800 // FORMAT_SS1 MOVE INVERSE 1971 op_MVCK uint32 = 0xD900 // FORMAT_SS4 MOVE WITH KEY 1972 op_MVCL uint32 = 0x0E00 // FORMAT_RR MOVE LONG 1973 op_MVCLE uint32 = 0xA800 // FORMAT_RS1 MOVE LONG EXTENDED 1974 op_MVCLU uint32 = 0xEB8E // FORMAT_RSY1 MOVE LONG UNICODE 1975 op_MVCOS uint32 = 0xC800 // FORMAT_SSF MOVE WITH OPTIONAL SPECIFICATIONS 1976 op_MVCP uint32 = 0xDA00 // FORMAT_SS4 MOVE TO PRIMARY 1977 op_MVCS uint32 = 0xDB00 // FORMAT_SS4 MOVE TO SECONDARY 1978 op_MVCSK uint32 = 0xE50E // FORMAT_SSE MOVE WITH SOURCE KEY 1979 op_MVGHI uint32 = 0xE548 // FORMAT_SIL MOVE (64<-16) 1980 op_MVHHI uint32 = 0xE544 // FORMAT_SIL MOVE (16<-16) 1981 op_MVHI uint32 = 0xE54C // FORMAT_SIL MOVE (32<-16) 1982 op_MVI uint32 = 0x9200 // FORMAT_SI MOVE (immediate) 1983 op_MVIY uint32 = 0xEB52 // FORMAT_SIY MOVE (immediate) 1984 op_MVN uint32 = 0xD100 // FORMAT_SS1 MOVE NUMERICS 1985 op_MVO uint32 = 0xF100 // FORMAT_SS2 MOVE WITH OFFSET 1986 op_MVPG uint32 = 0xB254 // FORMAT_RRE MOVE PAGE 1987 op_MVST uint32 = 0xB255 // FORMAT_RRE MOVE STRING 1988 op_MVZ uint32 = 0xD300 // FORMAT_SS1 MOVE ZONES 1989 op_MXBR uint32 = 0xB34C // FORMAT_RRE MULTIPLY (extended BFP) 1990 op_MXD uint32 = 0x6700 // FORMAT_RX1 MULTIPLY (long to extended HFP) 1991 op_MXDB uint32 = 0xED07 // FORMAT_RXE MULTIPLY (long to extended BFP) 1992 op_MXDBR uint32 = 0xB307 // FORMAT_RRE MULTIPLY (long to extended BFP) 1993 op_MXDR uint32 = 0x2700 // FORMAT_RR MULTIPLY (long to extended HFP) 1994 op_MXR uint32 = 0x2600 // FORMAT_RR MULTIPLY (extended HFP) 1995 op_MXTR uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 1996 op_MXTRA uint32 = 0xB3D8 // FORMAT_RRF1 MULTIPLY (extended DFP) 1997 op_MY uint32 = 0xED3B // FORMAT_RXF MULTIPLY UNNORMALIZED (long to ext. HFP) 1998 op_MYH uint32 = 0xED3D // FORMAT_RXF MULTIPLY UNNORM. (long to ext. high HFP) 1999 op_MYHR uint32 = 0xB33D // FORMAT_RRD MULTIPLY UNNORM. (long to ext. high HFP) 2000 op_MYL uint32 = 0xED39 // FORMAT_RXF MULTIPLY UNNORM. (long to ext. low HFP) 2001 op_MYLR uint32 = 0xB339 // FORMAT_RRD MULTIPLY UNNORM. (long to ext. low HFP) 2002 op_MYR uint32 = 0xB33B // FORMAT_RRD MULTIPLY UNNORMALIZED (long to ext. HFP) 2003 op_N uint32 = 0x5400 // FORMAT_RX1 AND (32) 2004 op_NC uint32 = 0xD400 // FORMAT_SS1 AND (character) 2005 op_NG uint32 = 0xE380 // FORMAT_RXY1 AND (64) 2006 op_NGR uint32 = 0xB980 // FORMAT_RRE AND (64) 2007 op_NGRK uint32 = 0xB9E4 // FORMAT_RRF1 AND (64) 2008 op_NI uint32 = 0x9400 // FORMAT_SI AND (immediate) 2009 op_NIAI uint32 = 0xB2FA // FORMAT_IE NEXT INSTRUCTION ACCESS INTENT 2010 op_NIHF uint32 = 0xC00A // FORMAT_RIL1 AND IMMEDIATE (high) 2011 op_NIHH uint32 = 0xA504 // FORMAT_RI1 AND IMMEDIATE (high high) 2012 op_NIHL uint32 = 0xA505 // FORMAT_RI1 AND IMMEDIATE (high low) 2013 op_NILF uint32 = 0xC00B // FORMAT_RIL1 AND IMMEDIATE (low) 2014 op_NILH uint32 = 0xA506 // FORMAT_RI1 AND IMMEDIATE (low high) 2015 op_NILL uint32 = 0xA507 // FORMAT_RI1 AND IMMEDIATE (low low) 2016 op_NIY uint32 = 0xEB54 // FORMAT_SIY AND (immediate) 2017 op_NR uint32 = 0x1400 // FORMAT_RR AND (32) 2018 op_NRK uint32 = 0xB9F4 // FORMAT_RRF1 AND (32) 2019 op_NTSTG uint32 = 0xE325 // FORMAT_RXY1 NONTRANSACTIONAL STORE 2020 op_NY uint32 = 0xE354 // FORMAT_RXY1 AND (32) 2021 op_O uint32 = 0x5600 // FORMAT_RX1 OR (32) 2022 op_OC uint32 = 0xD600 // FORMAT_SS1 OR (character) 2023 op_OG uint32 = 0xE381 // FORMAT_RXY1 OR (64) 2024 op_OGR uint32 = 0xB981 // FORMAT_RRE OR (64) 2025 op_OGRK uint32 = 0xB9E6 // FORMAT_RRF1 OR (64) 2026 op_OI uint32 = 0x9600 // FORMAT_SI OR (immediate) 2027 op_OIHF uint32 = 0xC00C // FORMAT_RIL1 OR IMMEDIATE (high) 2028 op_OIHH uint32 = 0xA508 // FORMAT_RI1 OR IMMEDIATE (high high) 2029 op_OIHL uint32 = 0xA509 // FORMAT_RI1 OR IMMEDIATE (high low) 2030 op_OILF uint32 = 0xC00D // FORMAT_RIL1 OR IMMEDIATE (low) 2031 op_OILH uint32 = 0xA50A // FORMAT_RI1 OR IMMEDIATE (low high) 2032 op_OILL uint32 = 0xA50B // FORMAT_RI1 OR IMMEDIATE (low low) 2033 op_OIY uint32 = 0xEB56 // FORMAT_SIY OR (immediate) 2034 op_OR uint32 = 0x1600 // FORMAT_RR OR (32) 2035 op_ORK uint32 = 0xB9F6 // FORMAT_RRF1 OR (32) 2036 op_OY uint32 = 0xE356 // FORMAT_RXY1 OR (32) 2037 op_PACK uint32 = 0xF200 // FORMAT_SS2 PACK 2038 op_PALB uint32 = 0xB248 // FORMAT_RRE PURGE ALB 2039 op_PC uint32 = 0xB218 // FORMAT_S PROGRAM CALL 2040 op_PCC uint32 = 0xB92C // FORMAT_RRE PERFORM CRYPTOGRAPHIC COMPUTATION 2041 op_PCKMO uint32 = 0xB928 // FORMAT_RRE PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS 2042 op_PFD uint32 = 0xE336 // FORMAT_RXY2 PREFETCH DATA 2043 op_PFDRL uint32 = 0xC602 // FORMAT_RIL3 PREFETCH DATA RELATIVE LONG 2044 op_PFMF uint32 = 0xB9AF // FORMAT_RRE PERFORM FRAME MANAGEMENT FUNCTION 2045 op_PFPO uint32 = 0x010A // FORMAT_E PERFORM FLOATING-POINT OPERATION 2046 op_PGIN uint32 = 0xB22E // FORMAT_RRE PAGE IN 2047 op_PGOUT uint32 = 0xB22F // FORMAT_RRE PAGE OUT 2048 op_PKA uint32 = 0xE900 // FORMAT_SS6 PACK ASCII 2049 op_PKU uint32 = 0xE100 // FORMAT_SS6 PACK UNICODE 2050 op_PLO uint32 = 0xEE00 // FORMAT_SS5 PERFORM LOCKED OPERATION 2051 op_POPCNT uint32 = 0xB9E1 // FORMAT_RRE POPULATION COUNT 2052 op_PPA uint32 = 0xB2E8 // FORMAT_RRF3 PERFORM PROCESSOR ASSIST 2053 op_PR uint32 = 0x0101 // FORMAT_E PROGRAM RETURN 2054 op_PT uint32 = 0xB228 // FORMAT_RRE PROGRAM TRANSFER 2055 op_PTF uint32 = 0xB9A2 // FORMAT_RRE PERFORM TOPOLOGY FUNCTION 2056 op_PTFF uint32 = 0x0104 // FORMAT_E PERFORM TIMING FACILITY FUNCTION 2057 op_PTI uint32 = 0xB99E // FORMAT_RRE PROGRAM TRANSFER WITH INSTANCE 2058 op_PTLB uint32 = 0xB20D // FORMAT_S PURGE TLB 2059 op_QADTR uint32 = 0xB3F5 // FORMAT_RRF2 QUANTIZE (long DFP) 2060 op_QAXTR uint32 = 0xB3FD // FORMAT_RRF2 QUANTIZE (extended DFP) 2061 op_RCHP uint32 = 0xB23B // FORMAT_S RESET CHANNEL PATH 2062 op_RISBG uint32 = 0xEC55 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2063 op_RISBGN uint32 = 0xEC59 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS 2064 op_RISBHG uint32 = 0xEC5D // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS HIGH 2065 op_RISBLG uint32 = 0xEC51 // FORMAT_RIE6 ROTATE THEN INSERT SELECTED BITS LOW 2066 op_RLL uint32 = 0xEB1D // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (32) 2067 op_RLLG uint32 = 0xEB1C // FORMAT_RSY1 ROTATE LEFT SINGLE LOGICAL (64) 2068 op_RNSBG uint32 = 0xEC54 // FORMAT_RIE6 ROTATE THEN AND SELECTED BITS 2069 op_ROSBG uint32 = 0xEC56 // FORMAT_RIE6 ROTATE THEN OR SELECTED BITS 2070 op_RP uint32 = 0xB277 // FORMAT_S RESUME PROGRAM 2071 op_RRBE uint32 = 0xB22A // FORMAT_RRE RESET REFERENCE BIT EXTENDED 2072 op_RRBM uint32 = 0xB9AE // FORMAT_RRE RESET REFERENCE BITS MULTIPLE 2073 op_RRDTR uint32 = 0xB3F7 // FORMAT_RRF2 REROUND (long DFP) 2074 op_RRXTR uint32 = 0xB3FF // FORMAT_RRF2 REROUND (extended DFP) 2075 op_RSCH uint32 = 0xB238 // FORMAT_S RESUME SUBCHANNEL 2076 op_RXSBG uint32 = 0xEC57 // FORMAT_RIE6 ROTATE THEN EXCLUSIVE OR SELECTED BITS 2077 op_S uint32 = 0x5B00 // FORMAT_RX1 SUBTRACT (32) 2078 op_SAC uint32 = 0xB219 // FORMAT_S SET ADDRESS SPACE CONTROL 2079 op_SACF uint32 = 0xB279 // FORMAT_S SET ADDRESS SPACE CONTROL FAST 2080 op_SAL uint32 = 0xB237 // FORMAT_S SET ADDRESS LIMIT 2081 op_SAM24 uint32 = 0x010C // FORMAT_E SET ADDRESSING MODE (24) 2082 op_SAM31 uint32 = 0x010D // FORMAT_E SET ADDRESSING MODE (31) 2083 op_SAM64 uint32 = 0x010E // FORMAT_E SET ADDRESSING MODE (64) 2084 op_SAR uint32 = 0xB24E // FORMAT_RRE SET ACCESS 2085 op_SCHM uint32 = 0xB23C // FORMAT_S SET CHANNEL MONITOR 2086 op_SCK uint32 = 0xB204 // FORMAT_S SET CLOCK 2087 op_SCKC uint32 = 0xB206 // FORMAT_S SET CLOCK COMPARATOR 2088 op_SCKPF uint32 = 0x0107 // FORMAT_E SET CLOCK PROGRAMMABLE FIELD 2089 op_SD uint32 = 0x6B00 // FORMAT_RX1 SUBTRACT NORMALIZED (long HFP) 2090 op_SDB uint32 = 0xED1B // FORMAT_RXE SUBTRACT (long BFP) 2091 op_SDBR uint32 = 0xB31B // FORMAT_RRE SUBTRACT (long BFP) 2092 op_SDR uint32 = 0x2B00 // FORMAT_RR SUBTRACT NORMALIZED (long HFP) 2093 op_SDTR uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2094 op_SDTRA uint32 = 0xB3D3 // FORMAT_RRF1 SUBTRACT (long DFP) 2095 op_SE uint32 = 0x7B00 // FORMAT_RX1 SUBTRACT NORMALIZED (short HFP) 2096 op_SEB uint32 = 0xED0B // FORMAT_RXE SUBTRACT (short BFP) 2097 op_SEBR uint32 = 0xB30B // FORMAT_RRE SUBTRACT (short BFP) 2098 op_SER uint32 = 0x3B00 // FORMAT_RR SUBTRACT NORMALIZED (short HFP) 2099 op_SFASR uint32 = 0xB385 // FORMAT_RRE SET FPC AND SIGNAL 2100 op_SFPC uint32 = 0xB384 // FORMAT_RRE SET FPC 2101 op_SG uint32 = 0xE309 // FORMAT_RXY1 SUBTRACT (64) 2102 op_SGF uint32 = 0xE319 // FORMAT_RXY1 SUBTRACT (64<-32) 2103 op_SGFR uint32 = 0xB919 // FORMAT_RRE SUBTRACT (64<-32) 2104 op_SGR uint32 = 0xB909 // FORMAT_RRE SUBTRACT (64) 2105 op_SGRK uint32 = 0xB9E9 // FORMAT_RRF1 SUBTRACT (64) 2106 op_SH uint32 = 0x4B00 // FORMAT_RX1 SUBTRACT HALFWORD 2107 op_SHHHR uint32 = 0xB9C9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2108 op_SHHLR uint32 = 0xB9D9 // FORMAT_RRF1 SUBTRACT HIGH (32) 2109 op_SHY uint32 = 0xE37B // FORMAT_RXY1 SUBTRACT HALFWORD 2110 op_SIGP uint32 = 0xAE00 // FORMAT_RS1 SIGNAL PROCESSOR 2111 op_SL uint32 = 0x5F00 // FORMAT_RX1 SUBTRACT LOGICAL (32) 2112 op_SLA uint32 = 0x8B00 // FORMAT_RS1 SHIFT LEFT SINGLE (32) 2113 op_SLAG uint32 = 0xEB0B // FORMAT_RSY1 SHIFT LEFT SINGLE (64) 2114 op_SLAK uint32 = 0xEBDD // FORMAT_RSY1 SHIFT LEFT SINGLE (32) 2115 op_SLB uint32 = 0xE399 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (32) 2116 op_SLBG uint32 = 0xE389 // FORMAT_RXY1 SUBTRACT LOGICAL WITH BORROW (64) 2117 op_SLBGR uint32 = 0xB989 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (64) 2118 op_SLBR uint32 = 0xB999 // FORMAT_RRE SUBTRACT LOGICAL WITH BORROW (32) 2119 op_SLDA uint32 = 0x8F00 // FORMAT_RS1 SHIFT LEFT DOUBLE 2120 op_SLDL uint32 = 0x8D00 // FORMAT_RS1 SHIFT LEFT DOUBLE LOGICAL 2121 op_SLDT uint32 = 0xED40 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (long DFP) 2122 op_SLFI uint32 = 0xC205 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (32) 2123 op_SLG uint32 = 0xE30B // FORMAT_RXY1 SUBTRACT LOGICAL (64) 2124 op_SLGF uint32 = 0xE31B // FORMAT_RXY1 SUBTRACT LOGICAL (64<-32) 2125 op_SLGFI uint32 = 0xC204 // FORMAT_RIL1 SUBTRACT LOGICAL IMMEDIATE (64<-32) 2126 op_SLGFR uint32 = 0xB91B // FORMAT_RRE SUBTRACT LOGICAL (64<-32) 2127 op_SLGR uint32 = 0xB90B // FORMAT_RRE SUBTRACT LOGICAL (64) 2128 op_SLGRK uint32 = 0xB9EB // FORMAT_RRF1 SUBTRACT LOGICAL (64) 2129 op_SLHHHR uint32 = 0xB9CB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2130 op_SLHHLR uint32 = 0xB9DB // FORMAT_RRF1 SUBTRACT LOGICAL HIGH (32) 2131 op_SLL uint32 = 0x8900 // FORMAT_RS1 SHIFT LEFT SINGLE LOGICAL (32) 2132 op_SLLG uint32 = 0xEB0D // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (64) 2133 op_SLLK uint32 = 0xEBDF // FORMAT_RSY1 SHIFT LEFT SINGLE LOGICAL (32) 2134 op_SLR uint32 = 0x1F00 // FORMAT_RR SUBTRACT LOGICAL (32) 2135 op_SLRK uint32 = 0xB9FB // FORMAT_RRF1 SUBTRACT LOGICAL (32) 2136 op_SLXT uint32 = 0xED48 // FORMAT_RXF SHIFT SIGNIFICAND LEFT (extended DFP) 2137 op_SLY uint32 = 0xE35F // FORMAT_RXY1 SUBTRACT LOGICAL (32) 2138 op_SP uint32 = 0xFB00 // FORMAT_SS2 SUBTRACT DECIMAL 2139 op_SPKA uint32 = 0xB20A // FORMAT_S SET PSW KEY FROM ADDRESS 2140 op_SPM uint32 = 0x0400 // FORMAT_RR SET PROGRAM MASK 2141 op_SPT uint32 = 0xB208 // FORMAT_S SET CPU TIMER 2142 op_SPX uint32 = 0xB210 // FORMAT_S SET PREFIX 2143 op_SQD uint32 = 0xED35 // FORMAT_RXE SQUARE ROOT (long HFP) 2144 op_SQDB uint32 = 0xED15 // FORMAT_RXE SQUARE ROOT (long BFP) 2145 op_SQDBR uint32 = 0xB315 // FORMAT_RRE SQUARE ROOT (long BFP) 2146 op_SQDR uint32 = 0xB244 // FORMAT_RRE SQUARE ROOT (long HFP) 2147 op_SQE uint32 = 0xED34 // FORMAT_RXE SQUARE ROOT (short HFP) 2148 op_SQEB uint32 = 0xED14 // FORMAT_RXE SQUARE ROOT (short BFP) 2149 op_SQEBR uint32 = 0xB314 // FORMAT_RRE SQUARE ROOT (short BFP) 2150 op_SQER uint32 = 0xB245 // FORMAT_RRE SQUARE ROOT (short HFP) 2151 op_SQXBR uint32 = 0xB316 // FORMAT_RRE SQUARE ROOT (extended BFP) 2152 op_SQXR uint32 = 0xB336 // FORMAT_RRE SQUARE ROOT (extended HFP) 2153 op_SR uint32 = 0x1B00 // FORMAT_RR SUBTRACT (32) 2154 op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) 2155 op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) 2156 op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) 2157 op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE 2158 op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL 2159 op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP) 2160 op_SRK uint32 = 0xB9F9 // FORMAT_RRF1 SUBTRACT (32) 2161 op_SRL uint32 = 0x8800 // FORMAT_RS1 SHIFT RIGHT SINGLE LOGICAL (32) 2162 op_SRLG uint32 = 0xEB0C // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (64) 2163 op_SRLK uint32 = 0xEBDE // FORMAT_RSY1 SHIFT RIGHT SINGLE LOGICAL (32) 2164 op_SRNM uint32 = 0xB299 // FORMAT_S SET BFP ROUNDING MODE (2 bit) 2165 op_SRNMB uint32 = 0xB2B8 // FORMAT_S SET BFP ROUNDING MODE (3 bit) 2166 op_SRNMT uint32 = 0xB2B9 // FORMAT_S SET DFP ROUNDING MODE 2167 op_SRP uint32 = 0xF000 // FORMAT_SS3 SHIFT AND ROUND DECIMAL 2168 op_SRST uint32 = 0xB25E // FORMAT_RRE SEARCH STRING 2169 op_SRSTU uint32 = 0xB9BE // FORMAT_RRE SEARCH STRING UNICODE 2170 op_SRXT uint32 = 0xED49 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (extended DFP) 2171 op_SSAIR uint32 = 0xB99F // FORMAT_RRE SET SECONDARY ASN WITH INSTANCE 2172 op_SSAR uint32 = 0xB225 // FORMAT_RRE SET SECONDARY ASN 2173 op_SSCH uint32 = 0xB233 // FORMAT_S START SUBCHANNEL 2174 op_SSKE uint32 = 0xB22B // FORMAT_RRF3 SET STORAGE KEY EXTENDED 2175 op_SSM uint32 = 0x8000 // FORMAT_S SET SYSTEM MASK 2176 op_ST uint32 = 0x5000 // FORMAT_RX1 STORE (32) 2177 op_STAM uint32 = 0x9B00 // FORMAT_RS1 STORE ACCESS MULTIPLE 2178 op_STAMY uint32 = 0xEB9B // FORMAT_RSY1 STORE ACCESS MULTIPLE 2179 op_STAP uint32 = 0xB212 // FORMAT_S STORE CPU ADDRESS 2180 op_STC uint32 = 0x4200 // FORMAT_RX1 STORE CHARACTER 2181 op_STCH uint32 = 0xE3C3 // FORMAT_RXY1 STORE CHARACTER HIGH (8) 2182 op_STCK uint32 = 0xB205 // FORMAT_S STORE CLOCK 2183 op_STCKC uint32 = 0xB207 // FORMAT_S STORE CLOCK COMPARATOR 2184 op_STCKE uint32 = 0xB278 // FORMAT_S STORE CLOCK EXTENDED 2185 op_STCKF uint32 = 0xB27C // FORMAT_S STORE CLOCK FAST 2186 op_STCM uint32 = 0xBE00 // FORMAT_RS2 STORE CHARACTERS UNDER MASK (low) 2187 op_STCMH uint32 = 0xEB2C // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (high) 2188 op_STCMY uint32 = 0xEB2D // FORMAT_RSY2 STORE CHARACTERS UNDER MASK (low) 2189 op_STCPS uint32 = 0xB23A // FORMAT_S STORE CHANNEL PATH STATUS 2190 op_STCRW uint32 = 0xB239 // FORMAT_S STORE CHANNEL REPORT WORD 2191 op_STCTG uint32 = 0xEB25 // FORMAT_RSY1 STORE CONTROL (64) 2192 op_STCTL uint32 = 0xB600 // FORMAT_RS1 STORE CONTROL (32) 2193 op_STCY uint32 = 0xE372 // FORMAT_RXY1 STORE CHARACTER 2194 op_STD uint32 = 0x6000 // FORMAT_RX1 STORE (long) 2195 op_STDY uint32 = 0xED67 // FORMAT_RXY1 STORE (long) 2196 op_STE uint32 = 0x7000 // FORMAT_RX1 STORE (short) 2197 op_STEY uint32 = 0xED66 // FORMAT_RXY1 STORE (short) 2198 op_STFH uint32 = 0xE3CB // FORMAT_RXY1 STORE HIGH (32) 2199 op_STFL uint32 = 0xB2B1 // FORMAT_S STORE FACILITY LIST 2200 op_STFLE uint32 = 0xB2B0 // FORMAT_S STORE FACILITY LIST EXTENDED 2201 op_STFPC uint32 = 0xB29C // FORMAT_S STORE FPC 2202 op_STG uint32 = 0xE324 // FORMAT_RXY1 STORE (64) 2203 op_STGRL uint32 = 0xC40B // FORMAT_RIL2 STORE RELATIVE LONG (64) 2204 op_STH uint32 = 0x4000 // FORMAT_RX1 STORE HALFWORD 2205 op_STHH uint32 = 0xE3C7 // FORMAT_RXY1 STORE HALFWORD HIGH (16) 2206 op_STHRL uint32 = 0xC407 // FORMAT_RIL2 STORE HALFWORD RELATIVE LONG 2207 op_STHY uint32 = 0xE370 // FORMAT_RXY1 STORE HALFWORD 2208 op_STIDP uint32 = 0xB202 // FORMAT_S STORE CPU ID 2209 op_STM uint32 = 0x9000 // FORMAT_RS1 STORE MULTIPLE (32) 2210 op_STMG uint32 = 0xEB24 // FORMAT_RSY1 STORE MULTIPLE (64) 2211 op_STMH uint32 = 0xEB26 // FORMAT_RSY1 STORE MULTIPLE HIGH 2212 op_STMY uint32 = 0xEB90 // FORMAT_RSY1 STORE MULTIPLE (32) 2213 op_STNSM uint32 = 0xAC00 // FORMAT_SI STORE THEN AND SYSTEM MASK 2214 op_STOC uint32 = 0xEBF3 // FORMAT_RSY2 STORE ON CONDITION (32) 2215 op_STOCG uint32 = 0xEBE3 // FORMAT_RSY2 STORE ON CONDITION (64) 2216 op_STOSM uint32 = 0xAD00 // FORMAT_SI STORE THEN OR SYSTEM MASK 2217 op_STPQ uint32 = 0xE38E // FORMAT_RXY1 STORE PAIR TO QUADWORD 2218 op_STPT uint32 = 0xB209 // FORMAT_S STORE CPU TIMER 2219 op_STPX uint32 = 0xB211 // FORMAT_S STORE PREFIX 2220 op_STRAG uint32 = 0xE502 // FORMAT_SSE STORE REAL ADDRESS 2221 op_STRL uint32 = 0xC40F // FORMAT_RIL2 STORE RELATIVE LONG (32) 2222 op_STRV uint32 = 0xE33E // FORMAT_RXY1 STORE REVERSED (32) 2223 op_STRVG uint32 = 0xE32F // FORMAT_RXY1 STORE REVERSED (64) 2224 op_STRVH uint32 = 0xE33F // FORMAT_RXY1 STORE REVERSED (16) 2225 op_STSCH uint32 = 0xB234 // FORMAT_S STORE SUBCHANNEL 2226 op_STSI uint32 = 0xB27D // FORMAT_S STORE SYSTEM INFORMATION 2227 op_STURA uint32 = 0xB246 // FORMAT_RRE STORE USING REAL ADDRESS (32) 2228 op_STURG uint32 = 0xB925 // FORMAT_RRE STORE USING REAL ADDRESS (64) 2229 op_STY uint32 = 0xE350 // FORMAT_RXY1 STORE (32) 2230 op_SU uint32 = 0x7F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (short HFP) 2231 op_SUR uint32 = 0x3F00 // FORMAT_RR SUBTRACT UNNORMALIZED (short HFP) 2232 op_SVC uint32 = 0x0A00 // FORMAT_I SUPERVISOR CALL 2233 op_SW uint32 = 0x6F00 // FORMAT_RX1 SUBTRACT UNNORMALIZED (long HFP) 2234 op_SWR uint32 = 0x2F00 // FORMAT_RR SUBTRACT UNNORMALIZED (long HFP) 2235 op_SXBR uint32 = 0xB34B // FORMAT_RRE SUBTRACT (extended BFP) 2236 op_SXR uint32 = 0x3700 // FORMAT_RR SUBTRACT NORMALIZED (extended HFP) 2237 op_SXTR uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2238 op_SXTRA uint32 = 0xB3DB // FORMAT_RRF1 SUBTRACT (extended DFP) 2239 op_SY uint32 = 0xE35B // FORMAT_RXY1 SUBTRACT (32) 2240 op_TABORT uint32 = 0xB2FC // FORMAT_S TRANSACTION ABORT 2241 op_TAM uint32 = 0x010B // FORMAT_E TEST ADDRESSING MODE 2242 op_TAR uint32 = 0xB24C // FORMAT_RRE TEST ACCESS 2243 op_TB uint32 = 0xB22C // FORMAT_RRE TEST BLOCK 2244 op_TBDR uint32 = 0xB351 // FORMAT_RRF5 CONVERT HFP TO BFP (long) 2245 op_TBEDR uint32 = 0xB350 // FORMAT_RRF5 CONVERT HFP TO BFP (long to short) 2246 op_TBEGIN uint32 = 0xE560 // FORMAT_SIL TRANSACTION BEGIN 2247 op_TBEGINC uint32 = 0xE561 // FORMAT_SIL TRANSACTION BEGIN 2248 op_TCDB uint32 = 0xED11 // FORMAT_RXE TEST DATA CLASS (long BFP) 2249 op_TCEB uint32 = 0xED10 // FORMAT_RXE TEST DATA CLASS (short BFP) 2250 op_TCXB uint32 = 0xED12 // FORMAT_RXE TEST DATA CLASS (extended BFP) 2251 op_TDCDT uint32 = 0xED54 // FORMAT_RXE TEST DATA CLASS (long DFP) 2252 op_TDCET uint32 = 0xED50 // FORMAT_RXE TEST DATA CLASS (short DFP) 2253 op_TDCXT uint32 = 0xED58 // FORMAT_RXE TEST DATA CLASS (extended DFP) 2254 op_TDGDT uint32 = 0xED55 // FORMAT_RXE TEST DATA GROUP (long DFP) 2255 op_TDGET uint32 = 0xED51 // FORMAT_RXE TEST DATA GROUP (short DFP) 2256 op_TDGXT uint32 = 0xED59 // FORMAT_RXE TEST DATA GROUP (extended DFP) 2257 op_TEND uint32 = 0xB2F8 // FORMAT_S TRANSACTION END 2258 op_THDER uint32 = 0xB358 // FORMAT_RRE CONVERT BFP TO HFP (short to long) 2259 op_THDR uint32 = 0xB359 // FORMAT_RRE CONVERT BFP TO HFP (long) 2260 op_TM uint32 = 0x9100 // FORMAT_SI TEST UNDER MASK 2261 op_TMH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK HIGH 2262 op_TMHH uint32 = 0xA702 // FORMAT_RI1 TEST UNDER MASK (high high) 2263 op_TMHL uint32 = 0xA703 // FORMAT_RI1 TEST UNDER MASK (high low) 2264 op_TML uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK LOW 2265 op_TMLH uint32 = 0xA700 // FORMAT_RI1 TEST UNDER MASK (low high) 2266 op_TMLL uint32 = 0xA701 // FORMAT_RI1 TEST UNDER MASK (low low) 2267 op_TMY uint32 = 0xEB51 // FORMAT_SIY TEST UNDER MASK 2268 op_TP uint32 = 0xEBC0 // FORMAT_RSL TEST DECIMAL 2269 op_TPI uint32 = 0xB236 // FORMAT_S TEST PENDING INTERRUPTION 2270 op_TPROT uint32 = 0xE501 // FORMAT_SSE TEST PROTECTION 2271 op_TR uint32 = 0xDC00 // FORMAT_SS1 TRANSLATE 2272 op_TRACE uint32 = 0x9900 // FORMAT_RS1 TRACE (32) 2273 op_TRACG uint32 = 0xEB0F // FORMAT_RSY1 TRACE (64) 2274 op_TRAP2 uint32 = 0x01FF // FORMAT_E TRAP 2275 op_TRAP4 uint32 = 0xB2FF // FORMAT_S TRAP 2276 op_TRE uint32 = 0xB2A5 // FORMAT_RRE TRANSLATE EXTENDED 2277 op_TROO uint32 = 0xB993 // FORMAT_RRF3 TRANSLATE ONE TO ONE 2278 op_TROT uint32 = 0xB992 // FORMAT_RRF3 TRANSLATE ONE TO TWO 2279 op_TRT uint32 = 0xDD00 // FORMAT_SS1 TRANSLATE AND TEST 2280 op_TRTE uint32 = 0xB9BF // FORMAT_RRF3 TRANSLATE AND TEST EXTENDED 2281 op_TRTO uint32 = 0xB991 // FORMAT_RRF3 TRANSLATE TWO TO ONE 2282 op_TRTR uint32 = 0xD000 // FORMAT_SS1 TRANSLATE AND TEST REVERSE 2283 op_TRTRE uint32 = 0xB9BD // FORMAT_RRF3 TRANSLATE AND TEST REVERSE EXTENDED 2284 op_TRTT uint32 = 0xB990 // FORMAT_RRF3 TRANSLATE TWO TO TWO 2285 op_TS uint32 = 0x9300 // FORMAT_S TEST AND SET 2286 op_TSCH uint32 = 0xB235 // FORMAT_S TEST SUBCHANNEL 2287 op_UNPK uint32 = 0xF300 // FORMAT_SS2 UNPACK 2288 op_UNPKA uint32 = 0xEA00 // FORMAT_SS1 UNPACK ASCII 2289 op_UNPKU uint32 = 0xE200 // FORMAT_SS1 UNPACK UNICODE 2290 op_UPT uint32 = 0x0102 // FORMAT_E UPDATE TREE 2291 op_X uint32 = 0x5700 // FORMAT_RX1 EXCLUSIVE OR (32) 2292 op_XC uint32 = 0xD700 // FORMAT_SS1 EXCLUSIVE OR (character) 2293 op_XG uint32 = 0xE382 // FORMAT_RXY1 EXCLUSIVE OR (64) 2294 op_XGR uint32 = 0xB982 // FORMAT_RRE EXCLUSIVE OR (64) 2295 op_XGRK uint32 = 0xB9E7 // FORMAT_RRF1 EXCLUSIVE OR (64) 2296 op_XI uint32 = 0x9700 // FORMAT_SI EXCLUSIVE OR (immediate) 2297 op_XIHF uint32 = 0xC006 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (high) 2298 op_XILF uint32 = 0xC007 // FORMAT_RIL1 EXCLUSIVE OR IMMEDIATE (low) 2299 op_XIY uint32 = 0xEB57 // FORMAT_SIY EXCLUSIVE OR (immediate) 2300 op_XR uint32 = 0x1700 // FORMAT_RR EXCLUSIVE OR (32) 2301 op_XRK uint32 = 0xB9F7 // FORMAT_RRF1 EXCLUSIVE OR (32) 2302 op_XSCH uint32 = 0xB276 // FORMAT_S CANCEL SUBCHANNEL 2303 op_XY uint32 = 0xE357 // FORMAT_RXY1 EXCLUSIVE OR (32) 2304 op_ZAP uint32 = 0xF800 // FORMAT_SS2 ZERO AND ADD 2305 2306 // added in z13 2307 op_CXPT uint32 = 0xEDAF // RSL-b CONVERT FROM PACKED (to extended DFP) 2308 op_CDPT uint32 = 0xEDAE // RSL-b CONVERT FROM PACKED (to long DFP) 2309 op_CPXT uint32 = 0xEDAD // RSL-b CONVERT TO PACKED (from extended DFP) 2310 op_CPDT uint32 = 0xEDAC // RSL-b CONVERT TO PACKED (from long DFP) 2311 op_LZRF uint32 = 0xE33B // RXY-a LOAD AND ZERO RIGHTMOST BYTE (32) 2312 op_LZRG uint32 = 0xE32A // RXY-a LOAD AND ZERO RIGHTMOST BYTE (64) 2313 op_LCCB uint32 = 0xE727 // RXE LOAD COUNT TO BLOCK BOUNDARY 2314 op_LOCHHI uint32 = 0xEC4E // RIE-g LOAD HALFWORD HIGH IMMEDIATE ON CONDITION (32←16) 2315 op_LOCHI uint32 = 0xEC42 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (32←16) 2316 op_LOCGHI uint32 = 0xEC46 // RIE-g LOAD HALFWORD IMMEDIATE ON CONDITION (64←16) 2317 op_LOCFH uint32 = 0xEBE0 // RSY-b LOAD HIGH ON CONDITION (32) 2318 op_LOCFHR uint32 = 0xB9E0 // RRF-c LOAD HIGH ON CONDITION (32) 2319 op_LLZRGF uint32 = 0xE33A // RXY-a LOAD LOGICAL AND ZERO RIGHTMOST BYTE (64←32) 2320 op_STOCFH uint32 = 0xEBE1 // RSY-b STORE HIGH ON CONDITION 2321 op_VA uint32 = 0xE7F3 // VRR-c VECTOR ADD 2322 op_VACC uint32 = 0xE7F1 // VRR-c VECTOR ADD COMPUTE CARRY 2323 op_VAC uint32 = 0xE7BB // VRR-d VECTOR ADD WITH CARRY 2324 op_VACCC uint32 = 0xE7B9 // VRR-d VECTOR ADD WITH CARRY COMPUTE CARRY 2325 op_VN uint32 = 0xE768 // VRR-c VECTOR AND 2326 op_VNC uint32 = 0xE769 // VRR-c VECTOR AND WITH COMPLEMENT 2327 op_VAVG uint32 = 0xE7F2 // VRR-c VECTOR AVERAGE 2328 op_VAVGL uint32 = 0xE7F0 // VRR-c VECTOR AVERAGE LOGICAL 2329 op_VCKSM uint32 = 0xE766 // VRR-c VECTOR CHECKSUM 2330 op_VCEQ uint32 = 0xE7F8 // VRR-b VECTOR COMPARE EQUAL 2331 op_VCH uint32 = 0xE7FB // VRR-b VECTOR COMPARE HIGH 2332 op_VCHL uint32 = 0xE7F9 // VRR-b VECTOR COMPARE HIGH LOGICAL 2333 op_VCLZ uint32 = 0xE753 // VRR-a VECTOR COUNT LEADING ZEROS 2334 op_VCTZ uint32 = 0xE752 // VRR-a VECTOR COUNT TRAILING ZEROS 2335 op_VEC uint32 = 0xE7DB // VRR-a VECTOR ELEMENT COMPARE 2336 op_VECL uint32 = 0xE7D9 // VRR-a VECTOR ELEMENT COMPARE LOGICAL 2337 op_VERIM uint32 = 0xE772 // VRI-d VECTOR ELEMENT ROTATE AND INSERT UNDER MASK 2338 op_VERLL uint32 = 0xE733 // VRS-a VECTOR ELEMENT ROTATE LEFT LOGICAL 2339 op_VERLLV uint32 = 0xE773 // VRR-c VECTOR ELEMENT ROTATE LEFT LOGICAL 2340 op_VESLV uint32 = 0xE770 // VRR-c VECTOR ELEMENT SHIFT LEFT 2341 op_VESL uint32 = 0xE730 // VRS-a VECTOR ELEMENT SHIFT LEFT 2342 op_VESRA uint32 = 0xE73A // VRS-a VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2343 op_VESRAV uint32 = 0xE77A // VRR-c VECTOR ELEMENT SHIFT RIGHT ARITHMETIC 2344 op_VESRL uint32 = 0xE738 // VRS-a VECTOR ELEMENT SHIFT RIGHT LOGICAL 2345 op_VESRLV uint32 = 0xE778 // VRR-c VECTOR ELEMENT SHIFT RIGHT LOGICAL 2346 op_VX uint32 = 0xE76D // VRR-c VECTOR EXCLUSIVE OR 2347 op_VFAE uint32 = 0xE782 // VRR-b VECTOR FIND ANY ELEMENT EQUAL 2348 op_VFEE uint32 = 0xE780 // VRR-b VECTOR FIND ELEMENT EQUAL 2349 op_VFENE uint32 = 0xE781 // VRR-b VECTOR FIND ELEMENT NOT EQUAL 2350 op_VFA uint32 = 0xE7E3 // VRR-c VECTOR FP ADD 2351 op_WFK uint32 = 0xE7CA // VRR-a VECTOR FP COMPARE AND SIGNAL SCALAR 2352 op_VFCE uint32 = 0xE7E8 // VRR-c VECTOR FP COMPARE EQUAL 2353 op_VFCH uint32 = 0xE7EB // VRR-c VECTOR FP COMPARE HIGH 2354 op_VFCHE uint32 = 0xE7EA // VRR-c VECTOR FP COMPARE HIGH OR EQUAL 2355 op_WFC uint32 = 0xE7CB // VRR-a VECTOR FP COMPARE SCALAR 2356 op_VCDG uint32 = 0xE7C3 // VRR-a VECTOR FP CONVERT FROM FIXED 64-BIT 2357 op_VCDLG uint32 = 0xE7C1 // VRR-a VECTOR FP CONVERT FROM LOGICAL 64-BIT 2358 op_VCGD uint32 = 0xE7C2 // VRR-a VECTOR FP CONVERT TO FIXED 64-BIT 2359 op_VCLGD uint32 = 0xE7C0 // VRR-a VECTOR FP CONVERT TO LOGICAL 64-BIT 2360 op_VFD uint32 = 0xE7E5 // VRR-c VECTOR FP DIVIDE 2361 op_VLDE uint32 = 0xE7C4 // VRR-a VECTOR FP LOAD LENGTHENED 2362 op_VLED uint32 = 0xE7C5 // VRR-a VECTOR FP LOAD ROUNDED 2363 op_VFM uint32 = 0xE7E7 // VRR-c VECTOR FP MULTIPLY 2364 op_VFMA uint32 = 0xE78F // VRR-e VECTOR FP MULTIPLY AND ADD 2365 op_VFMS uint32 = 0xE78E // VRR-e VECTOR FP MULTIPLY AND SUBTRACT 2366 op_VFPSO uint32 = 0xE7CC // VRR-a VECTOR FP PERFORM SIGN OPERATION 2367 op_VFSQ uint32 = 0xE7CE // VRR-a VECTOR FP SQUARE ROOT 2368 op_VFS uint32 = 0xE7E2 // VRR-c VECTOR FP SUBTRACT 2369 op_VFTCI uint32 = 0xE74A // VRI-e VECTOR FP TEST DATA CLASS IMMEDIATE 2370 op_VGFM uint32 = 0xE7B4 // VRR-c VECTOR GALOIS FIELD MULTIPLY SUM 2371 op_VGFMA uint32 = 0xE7BC // VRR-d VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE 2372 op_VGEF uint32 = 0xE713 // VRV VECTOR GATHER ELEMENT (32) 2373 op_VGEG uint32 = 0xE712 // VRV VECTOR GATHER ELEMENT (64) 2374 op_VGBM uint32 = 0xE744 // VRI-a VECTOR GENERATE BYTE MASK 2375 op_VGM uint32 = 0xE746 // VRI-b VECTOR GENERATE MASK 2376 op_VISTR uint32 = 0xE75C // VRR-a VECTOR ISOLATE STRING 2377 op_VL uint32 = 0xE706 // VRX VECTOR LOAD 2378 op_VLR uint32 = 0xE756 // VRR-a VECTOR LOAD 2379 op_VLREP uint32 = 0xE705 // VRX VECTOR LOAD AND REPLICATE 2380 op_VLC uint32 = 0xE7DE // VRR-a VECTOR LOAD COMPLEMENT 2381 op_VLEH uint32 = 0xE701 // VRX VECTOR LOAD ELEMENT (16) 2382 op_VLEF uint32 = 0xE703 // VRX VECTOR LOAD ELEMENT (32) 2383 op_VLEG uint32 = 0xE702 // VRX VECTOR LOAD ELEMENT (64) 2384 op_VLEB uint32 = 0xE700 // VRX VECTOR LOAD ELEMENT (8) 2385 op_VLEIH uint32 = 0xE741 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (16) 2386 op_VLEIF uint32 = 0xE743 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (32) 2387 op_VLEIG uint32 = 0xE742 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (64) 2388 op_VLEIB uint32 = 0xE740 // VRI-a VECTOR LOAD ELEMENT IMMEDIATE (8) 2389 op_VFI uint32 = 0xE7C7 // VRR-a VECTOR LOAD FP INTEGER 2390 op_VLGV uint32 = 0xE721 // VRS-c VECTOR LOAD GR FROM VR ELEMENT 2391 op_VLLEZ uint32 = 0xE704 // VRX VECTOR LOAD LOGICAL ELEMENT AND ZERO 2392 op_VLM uint32 = 0xE736 // VRS-a VECTOR LOAD MULTIPLE 2393 op_VLP uint32 = 0xE7DF // VRR-a VECTOR LOAD POSITIVE 2394 op_VLBB uint32 = 0xE707 // VRX VECTOR LOAD TO BLOCK BOUNDARY 2395 op_VLVG uint32 = 0xE722 // VRS-b VECTOR LOAD VR ELEMENT FROM GR 2396 op_VLVGP uint32 = 0xE762 // VRR-f VECTOR LOAD VR FROM GRS DISJOINT 2397 op_VLL uint32 = 0xE737 // VRS-b VECTOR LOAD WITH LENGTH 2398 op_VMX uint32 = 0xE7FF // VRR-c VECTOR MAXIMUM 2399 op_VMXL uint32 = 0xE7FD // VRR-c VECTOR MAXIMUM LOGICAL 2400 op_VMRH uint32 = 0xE761 // VRR-c VECTOR MERGE HIGH 2401 op_VMRL uint32 = 0xE760 // VRR-c VECTOR MERGE LOW 2402 op_VMN uint32 = 0xE7FE // VRR-c VECTOR MINIMUM 2403 op_VMNL uint32 = 0xE7FC // VRR-c VECTOR MINIMUM LOGICAL 2404 op_VMAE uint32 = 0xE7AE // VRR-d VECTOR MULTIPLY AND ADD EVEN 2405 op_VMAH uint32 = 0xE7AB // VRR-d VECTOR MULTIPLY AND ADD HIGH 2406 op_VMALE uint32 = 0xE7AC // VRR-d VECTOR MULTIPLY AND ADD LOGICAL EVEN 2407 op_VMALH uint32 = 0xE7A9 // VRR-d VECTOR MULTIPLY AND ADD LOGICAL HIGH 2408 op_VMALO uint32 = 0xE7AD // VRR-d VECTOR MULTIPLY AND ADD LOGICAL ODD 2409 op_VMAL uint32 = 0xE7AA // VRR-d VECTOR MULTIPLY AND ADD LOW 2410 op_VMAO uint32 = 0xE7AF // VRR-d VECTOR MULTIPLY AND ADD ODD 2411 op_VME uint32 = 0xE7A6 // VRR-c VECTOR MULTIPLY EVEN 2412 op_VMH uint32 = 0xE7A3 // VRR-c VECTOR MULTIPLY HIGH 2413 op_VMLE uint32 = 0xE7A4 // VRR-c VECTOR MULTIPLY EVEN LOGICAL 2414 op_VMLH uint32 = 0xE7A1 // VRR-c VECTOR MULTIPLY HIGH LOGICAL 2415 op_VMLO uint32 = 0xE7A5 // VRR-c VECTOR MULTIPLY ODD LOGICAL 2416 op_VML uint32 = 0xE7A2 // VRR-c VECTOR MULTIPLY LOW 2417 op_VMO uint32 = 0xE7A7 // VRR-c VECTOR MULTIPLY ODD 2418 op_VNO uint32 = 0xE76B // VRR-c VECTOR NOR 2419 op_VO uint32 = 0xE76A // VRR-c VECTOR OR 2420 op_VPK uint32 = 0xE794 // VRR-c VECTOR PACK 2421 op_VPKLS uint32 = 0xE795 // VRR-b VECTOR PACK LOGICAL SATURATE 2422 op_VPKS uint32 = 0xE797 // VRR-b VECTOR PACK SATURATE 2423 op_VPERM uint32 = 0xE78C // VRR-e VECTOR PERMUTE 2424 op_VPDI uint32 = 0xE784 // VRR-c VECTOR PERMUTE DOUBLEWORD IMMEDIATE 2425 op_VPOPCT uint32 = 0xE750 // VRR-a VECTOR POPULATION COUNT 2426 op_VREP uint32 = 0xE74D // VRI-c VECTOR REPLICATE 2427 op_VREPI uint32 = 0xE745 // VRI-a VECTOR REPLICATE IMMEDIATE 2428 op_VSCEF uint32 = 0xE71B // VRV VECTOR SCATTER ELEMENT (32) 2429 op_VSCEG uint32 = 0xE71A // VRV VECTOR SCATTER ELEMENT (64) 2430 op_VSEL uint32 = 0xE78D // VRR-e VECTOR SELECT 2431 op_VSL uint32 = 0xE774 // VRR-c VECTOR SHIFT LEFT 2432 op_VSLB uint32 = 0xE775 // VRR-c VECTOR SHIFT LEFT BY BYTE 2433 op_VSLDB uint32 = 0xE777 // VRI-d VECTOR SHIFT LEFT DOUBLE BY BYTE 2434 op_VSRA uint32 = 0xE77E // VRR-c VECTOR SHIFT RIGHT ARITHMETIC 2435 op_VSRAB uint32 = 0xE77F // VRR-c VECTOR SHIFT RIGHT ARITHMETIC BY BYTE 2436 op_VSRL uint32 = 0xE77C // VRR-c VECTOR SHIFT RIGHT LOGICAL 2437 op_VSRLB uint32 = 0xE77D // VRR-c VECTOR SHIFT RIGHT LOGICAL BY BYTE 2438 op_VSEG uint32 = 0xE75F // VRR-a VECTOR SIGN EXTEND TO DOUBLEWORD 2439 op_VST uint32 = 0xE70E // VRX VECTOR STORE 2440 op_VSTEH uint32 = 0xE709 // VRX VECTOR STORE ELEMENT (16) 2441 op_VSTEF uint32 = 0xE70B // VRX VECTOR STORE ELEMENT (32) 2442 op_VSTEG uint32 = 0xE70A // VRX VECTOR STORE ELEMENT (64) 2443 op_VSTEB uint32 = 0xE708 // VRX VECTOR STORE ELEMENT (8) 2444 op_VSTM uint32 = 0xE73E // VRS-a VECTOR STORE MULTIPLE 2445 op_VSTL uint32 = 0xE73F // VRS-b VECTOR STORE WITH LENGTH 2446 op_VSTRC uint32 = 0xE78A // VRR-d VECTOR STRING RANGE COMPARE 2447 op_VS uint32 = 0xE7F7 // VRR-c VECTOR SUBTRACT 2448 op_VSCBI uint32 = 0xE7F5 // VRR-c VECTOR SUBTRACT COMPUTE BORROW INDICATION 2449 op_VSBCBI uint32 = 0xE7BD // VRR-d VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION 2450 op_VSBI uint32 = 0xE7BF // VRR-d VECTOR SUBTRACT WITH BORROW INDICATION 2451 op_VSUMG uint32 = 0xE765 // VRR-c VECTOR SUM ACROSS DOUBLEWORD 2452 op_VSUMQ uint32 = 0xE767 // VRR-c VECTOR SUM ACROSS QUADWORD 2453 op_VSUM uint32 = 0xE764 // VRR-c VECTOR SUM ACROSS WORD 2454 op_VTM uint32 = 0xE7D8 // VRR-a VECTOR TEST UNDER MASK 2455 op_VUPH uint32 = 0xE7D7 // VRR-a VECTOR UNPACK HIGH 2456 op_VUPLH uint32 = 0xE7D5 // VRR-a VECTOR UNPACK LOGICAL HIGH 2457 op_VUPLL uint32 = 0xE7D4 // VRR-a VECTOR UNPACK LOGICAL LOW 2458 op_VUPL uint32 = 0xE7D6 // VRR-a VECTOR UNPACK LOW 2459 ) 2460 2461 func oclass(a *obj.Addr) int { 2462 return int(a.Class) - 1 2463 } 2464 2465 // Add a relocation for the immediate in a RIL style instruction. 2466 // The addend will be adjusted as required. 2467 func addrilreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2468 if sym == nil { 2469 ctxt.Diag("require symbol to apply relocation") 2470 } 2471 offset := int64(2) // relocation offset from start of instruction 2472 rel := obj.Addrel(ctxt.Cursym) 2473 rel.Off = int32(ctxt.Pc + offset) 2474 rel.Siz = 4 2475 rel.Sym = sym 2476 rel.Add = add + offset + int64(rel.Siz) 2477 rel.Type = obj.R_PCRELDBL 2478 return rel 2479 } 2480 2481 func addrilrelocoffset(ctxt *obj.Link, sym *obj.LSym, add, offset int64) *obj.Reloc { 2482 if sym == nil { 2483 ctxt.Diag("require symbol to apply relocation") 2484 } 2485 offset += int64(2) // relocation offset from start of instruction 2486 rel := obj.Addrel(ctxt.Cursym) 2487 rel.Off = int32(ctxt.Pc + offset) 2488 rel.Siz = 4 2489 rel.Sym = sym 2490 rel.Add = add + offset + int64(rel.Siz) 2491 rel.Type = obj.R_PCRELDBL 2492 return rel 2493 } 2494 2495 // Add a CALL relocation for the immediate in a RIL style instruction. 2496 // The addend will be adjusted as required. 2497 func addcallreloc(ctxt *obj.Link, sym *obj.LSym, add int64) *obj.Reloc { 2498 if sym == nil { 2499 ctxt.Diag("require symbol to apply relocation") 2500 } 2501 offset := int64(2) // relocation offset from start of instruction 2502 rel := obj.Addrel(ctxt.Cursym) 2503 rel.Off = int32(ctxt.Pc + offset) 2504 rel.Siz = 4 2505 rel.Sym = sym 2506 rel.Add = add + offset + int64(rel.Siz) 2507 rel.Type = obj.R_CALL 2508 return rel 2509 } 2510 2511 func branchMask(ctxt *obj.Link, p *obj.Prog) uint32 { 2512 switch p.As { 2513 case ABEQ, ACMPBEQ, ACMPUBEQ: 2514 return 0x8 2515 case ABGE, ACMPBGE, ACMPUBGE: 2516 return 0xA 2517 case ABGT, ACMPBGT, ACMPUBGT: 2518 return 0x2 2519 case ABLE, ACMPBLE, ACMPUBLE: 2520 return 0xC 2521 case ABLT, ACMPBLT, ACMPUBLT: 2522 return 0x4 2523 case ABNE, ACMPBNE, ACMPUBNE: 2524 return 0x7 2525 case ABVC: 2526 return 0x0 //needs extra instruction 2527 case ABVS: 2528 return 0x1 2529 } 2530 ctxt.Diag("unknown conditional branch %v", p.As) 2531 return 0xF 2532 } 2533 2534 func asmout(ctxt *obj.Link, asm *[]byte) { 2535 p := ctxt.Curp 2536 o := oplook(ctxt, p) 2537 ctxt.Printp = p 2538 2539 switch o.type_ { 2540 default: 2541 ctxt.Diag("unknown type %d", o.type_) 2542 2543 case 0: // PSEUDO OPS 2544 break 2545 2546 case 1: // mov reg reg 2547 switch p.As { 2548 default: 2549 ctxt.Diag("unhandled operation: %v", p.As) 2550 case AMOVD: 2551 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2552 // sign extend 2553 case AMOVW: 2554 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2555 case AMOVH: 2556 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2557 case AMOVB: 2558 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2559 // zero extend 2560 case AMOVWZ: 2561 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2562 case AMOVHZ: 2563 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2564 case AMOVBZ: 2565 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2566 // reverse bytes 2567 case AMOVDBR: 2568 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2569 case AMOVWBR: 2570 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2571 // floating point 2572 case AFMOVD, AFMOVS: 2573 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2574 } 2575 2576 case 2: // arithmetic op reg [reg] reg 2577 r := int(p.Reg) 2578 if r == 0 { 2579 r = int(p.To.Reg) 2580 } 2581 2582 var opcode uint32 2583 2584 switch p.As { 2585 default: 2586 ctxt.Diag("invalid opcode") 2587 case AADD: 2588 opcode = op_AGRK 2589 case AADDC: 2590 opcode = op_ALGRK 2591 case AADDE: 2592 opcode = op_ALCGR 2593 case AMULLW: 2594 opcode = op_MSGFR 2595 case AMULLD: 2596 opcode = op_MSGR 2597 case ADIVW: 2598 opcode = op_DSGFR 2599 case ADIVWU: 2600 opcode = op_DLR 2601 case ADIVD: 2602 opcode = op_DSGR 2603 case ADIVDU: 2604 opcode = op_DLGR 2605 case AFADD: 2606 opcode = op_ADBR 2607 case AFADDS: 2608 opcode = op_AEBR 2609 case AFSUB: 2610 opcode = op_SDBR 2611 case AFSUBS: 2612 opcode = op_SEBR 2613 case AFDIV: 2614 opcode = op_DDBR 2615 case AFDIVS: 2616 opcode = op_DEBR 2617 } 2618 2619 switch p.As { 2620 default: 2621 2622 case AADD, AADDC: 2623 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2624 2625 case AADDE, AMULLW, AMULLD: 2626 if r == int(p.To.Reg) { 2627 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2628 } else if p.From.Reg == p.To.Reg { 2629 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2630 } else { 2631 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2632 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2633 } 2634 2635 case ADIVW, ADIVWU, ADIVD, ADIVDU: 2636 if p.As == ADIVWU || p.As == ADIVDU { 2637 zRRE(op_LGR, REGTMP, REGZERO, asm) 2638 } 2639 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2640 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm) 2641 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm) 2642 2643 case AFADD, AFADDS: 2644 if r == int(p.To.Reg) { 2645 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2646 } else if p.From.Reg == p.To.Reg { 2647 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 2648 } else { 2649 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2650 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2651 } 2652 2653 case AFSUB, AFSUBS, AFDIV, AFDIVS: 2654 if r == int(p.To.Reg) { 2655 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2656 } else if p.From.Reg == p.To.Reg { 2657 zRRE(op_LGDR, REGTMP, uint32(r), asm) 2658 zRRE(opcode, uint32(r), uint32(p.From.Reg), asm) 2659 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2660 zRRE(op_LDGR, uint32(r), REGTMP, asm) 2661 } else { 2662 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 2663 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2664 } 2665 2666 } 2667 2668 case 3: // mov $constant reg 2669 v := vregoff(ctxt, &p.From) 2670 switch p.As { 2671 case AMOVBZ: 2672 v = int64(uint8(v)) 2673 case AMOVHZ: 2674 v = int64(uint16(v)) 2675 case AMOVWZ: 2676 v = int64(uint32(v)) 2677 case AMOVB: 2678 v = int64(int8(v)) 2679 case AMOVH: 2680 v = int64(int16(v)) 2681 case AMOVW: 2682 v = int64(int32(v)) 2683 } 2684 if v&0xffff == v { 2685 zRI(op_LLILL, uint32(p.To.Reg), uint32(v), asm) 2686 } else if v&0xffff0000 == v { 2687 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm) 2688 } else if v&0xffff00000000 == v { 2689 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm) 2690 } else if uint64(v)&0xffff000000000000 == uint64(v) { 2691 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm) 2692 } else if int64(int16(v)) == v { 2693 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm) 2694 } else if int64(int32(v)) == v { 2695 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) 2696 } else if int64(uint32(v)) == v { 2697 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2698 } else if uint64(v)&0xffffffff00000000 == uint64(v) { 2699 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2700 } else { 2701 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) 2702 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) 2703 } 2704 2705 case 4: // multiply high (a*b)>>64 2706 r := p.Reg 2707 if r == 0 { 2708 r = p.To.Reg 2709 } 2710 zRRE(op_LGR, REGTMP2, uint32(r), asm) 2711 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm) 2712 switch p.As { 2713 case AMULHDU: 2714 // Unsigned: move result into correct register. 2715 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm) 2716 case AMULHD: 2717 // Signed: need to convert result. 2718 // See Hacker's Delight 8-3. 2719 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm) 2720 zRRE(op_NGR, REGTMP2, uint32(r), asm) 2721 zRRE(op_SGR, REGTMP, REGTMP2, asm) 2722 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm) 2723 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm) 2724 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm) 2725 } 2726 2727 case 5: // syscall 2728 zI(op_SVC, 0, asm) 2729 2730 case 6: // logical op reg [reg] reg 2731 if p.To.Reg == 0 { 2732 ctxt.Diag("literal operation on R0\n%v", p) 2733 } 2734 2735 switch p.As { 2736 case AAND, AOR, AXOR: 2737 var opcode1, opcode2 uint32 2738 switch p.As { 2739 default: 2740 case AAND: 2741 opcode1 = op_NGR 2742 opcode2 = op_NGRK 2743 case AOR: 2744 opcode1 = op_OGR 2745 opcode2 = op_OGRK 2746 case AXOR: 2747 opcode1 = op_XGR 2748 opcode2 = op_XGRK 2749 } 2750 2751 r := int(p.Reg) 2752 if r == 0 { 2753 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2754 } else { 2755 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2756 } 2757 2758 case AANDN, AORN: 2759 var opcode1, opcode2 uint32 2760 switch p.As { 2761 default: 2762 case AANDN: 2763 opcode1 = op_NGR 2764 opcode2 = op_NGRK 2765 case AORN: 2766 opcode1 = op_OGR 2767 opcode2 = op_OGRK 2768 } 2769 2770 r := int(p.Reg) 2771 if r == 0 { 2772 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 2773 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2774 } else { 2775 zRRE(op_LCGR, REGTMP, uint32(r), asm) 2776 zRRF(opcode2, REGTMP, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2777 } 2778 2779 case ANAND, ANOR: 2780 var opcode1, opcode2 uint32 2781 switch p.As { 2782 default: 2783 case ANAND: 2784 opcode1 = op_NGR 2785 opcode2 = op_NGRK 2786 case ANOR: 2787 opcode1 = op_OGR 2788 opcode2 = op_OGRK 2789 } 2790 2791 r := int(p.Reg) 2792 if r == 0 { 2793 zRRE(opcode1, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2794 } else { 2795 zRRF(opcode2, uint32(r), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2796 } 2797 2798 zRRE(op_LCGR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 2799 } 2800 2801 case 7: // shift/rotate reg [reg] reg 2802 d2 := vregoff(ctxt, &p.From) 2803 b2 := p.From.Reg 2804 r3 := p.Reg 2805 if r3 == 0 { 2806 r3 = p.To.Reg 2807 } 2808 r1 := p.To.Reg 2809 var opcode uint32 2810 switch p.As { 2811 default: 2812 case ASLD: 2813 opcode = op_SLLG 2814 case ASRD: 2815 opcode = op_SRLG 2816 case ASLW: 2817 opcode = op_SLLK 2818 case ASRW: 2819 opcode = op_SRLK 2820 case ARLL: 2821 opcode = op_RLL 2822 case ARLLG: 2823 opcode = op_RLLG 2824 case ASRAW: 2825 opcode = op_SRAK 2826 case ASRAD: 2827 opcode = op_SRAG 2828 } 2829 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm) 2830 2831 case 10: // subtract reg [reg] reg 2832 r := int(p.Reg) 2833 2834 switch p.As { 2835 default: 2836 case ASUB: 2837 if r == 0 { 2838 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2839 } else { 2840 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2841 } 2842 case ASUBC: 2843 if r == 0 { 2844 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2845 } else { 2846 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm) 2847 } 2848 2849 case ASUBE: 2850 if r == 0 { 2851 r = int(p.To.Reg) 2852 } 2853 if r == int(p.To.Reg) { 2854 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2855 } else if p.From.Reg == p.To.Reg { 2856 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 2857 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2858 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm) 2859 } else { 2860 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2861 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) 2862 } 2863 } 2864 2865 case 11: // br/bl 2866 v := int32(0) 2867 2868 if p.Pcond != nil { 2869 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2870 } 2871 2872 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v { 2873 zRI(op_BRC, 0xF, uint32(v), asm) 2874 } else { 2875 if p.As == ABL { 2876 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm) 2877 } else { 2878 zRIL(_c, op_BRCL, 0xF, uint32(v), asm) 2879 } 2880 if p.To.Sym != nil { 2881 addcallreloc(ctxt, p.To.Sym, p.To.Offset) 2882 } 2883 } 2884 2885 case 15: // br/bl (reg) 2886 r := p.To.Reg 2887 if p.As == ABCL || p.As == ABL { 2888 zRR(op_BASR, uint32(REG_LR), uint32(r), asm) 2889 } else { 2890 zRR(op_BCR, 0xF, uint32(r), asm) 2891 } 2892 2893 case 16: // conditional branch 2894 v := int32(0) 2895 if p.Pcond != nil { 2896 v = int32((p.Pcond.Pc - p.Pc) >> 1) 2897 } 2898 mask := branchMask(ctxt, p) 2899 if p.To.Sym == nil && int32(int16(v)) == v { 2900 zRI(op_BRC, mask, uint32(v), asm) 2901 } else { 2902 zRIL(_c, op_BRCL, mask, uint32(v), asm) 2903 } 2904 if p.To.Sym != nil { 2905 addrilreloc(ctxt, p.To.Sym, p.To.Offset) 2906 } 2907 2908 case 18: // br/bl reg 2909 if p.As == ABL { 2910 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm) 2911 } else { 2912 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm) 2913 } 2914 2915 case 19: // mov $sym+n(SB) reg 2916 d := vregoff(ctxt, &p.From) 2917 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm) 2918 if d&1 != 0 { 2919 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm) 2920 d -= 1 2921 } 2922 addrilreloc(ctxt, p.From.Sym, d) 2923 2924 case 22: // arithmetic op $constant [reg] reg 2925 if p.From.Sym != nil { 2926 ctxt.Diag("%v is not supported", p) 2927 } 2928 v := vregoff(ctxt, &p.From) 2929 r := p.Reg 2930 if r == 0 { 2931 r = p.To.Reg 2932 } 2933 switch p.As { 2934 default: 2935 case AADD: 2936 if r == p.To.Reg { 2937 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm) 2938 } else if int64(int16(v)) == v { 2939 zRIE(_d, op_AGHIK, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm) 2940 } else { 2941 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2942 zRIL(_a, op_AGFI, uint32(p.To.Reg), uint32(v), asm) 2943 } 2944 case AADDC: 2945 if r != p.To.Reg { 2946 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2947 } 2948 zRIL(_a, op_ALGFI, uint32(p.To.Reg), uint32(v), asm) 2949 case AMULLW, AMULLD: 2950 if r != p.To.Reg { 2951 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm) 2952 } 2953 if int64(int16(v)) == v { 2954 zRI(op_MGHI, uint32(p.To.Reg), uint32(v), asm) 2955 } else { 2956 zRIL(_a, op_MSGFI, uint32(p.To.Reg), uint32(v), asm) 2957 } 2958 } 2959 2960 case 23: // logical op $constant [reg] reg 2961 v := vregoff(ctxt, &p.From) 2962 var opcode uint32 2963 r := p.Reg 2964 if r == 0 { 2965 r = p.To.Reg 2966 } 2967 if r == p.To.Reg { 2968 switch p.As { 2969 default: 2970 ctxt.Diag("%v is not supported", p) 2971 case AAND: 2972 if v >= 0 { // needs zero extend 2973 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2974 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm) 2975 } else if int64(int16(v)) == v { 2976 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm) 2977 } else { // r.To.Reg & 0xffffffff00000000 & uint32(v) 2978 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm) 2979 } 2980 case AOR: 2981 if int64(uint32(v)) != v { // needs sign extend 2982 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2983 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm) 2984 } else if int64(uint16(v)) == v { 2985 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm) 2986 } else { 2987 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm) 2988 } 2989 case AXOR: 2990 if int64(uint32(v)) != v { // needs sign extend 2991 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 2992 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm) 2993 } else { 2994 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm) 2995 } 2996 } 2997 } else { 2998 switch p.As { 2999 default: 3000 ctxt.Diag("%v is not supported", p) 3001 case AAND: 3002 opcode = op_NGRK 3003 case AOR: 3004 opcode = op_OGRK 3005 case AXOR: 3006 opcode = op_XGRK 3007 } 3008 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3009 zRRF(opcode, uint32(r), 0, uint32(p.To.Reg), REGTMP, asm) 3010 } 3011 3012 case 26: // mov $addr/sym reg 3013 v := regoff(ctxt, &p.From) 3014 r := p.From.Reg 3015 if r == 0 { 3016 r = o.param 3017 } 3018 if v >= 0 && v < DISP12 { 3019 zRX(op_LA, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm) 3020 } else if v >= -DISP20/2 && v < DISP20/2 { 3021 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), 0, uint32(v), asm) 3022 } else { 3023 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm) 3024 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, 0, asm) 3025 } 3026 3027 case 31: // dword 3028 wd := uint64(vregoff(ctxt, &p.From)) 3029 *asm = append(*asm, 3030 uint8(wd>>56), 3031 uint8(wd>>48), 3032 uint8(wd>>40), 3033 uint8(wd>>32), 3034 uint8(wd>>24), 3035 uint8(wd>>16), 3036 uint8(wd>>8), 3037 uint8(wd)) 3038 3039 case 32: // fmul freg [freg] freg 3040 r := int(p.Reg) 3041 if r == 0 { 3042 r = int(p.To.Reg) 3043 } 3044 3045 var opcode uint32 3046 3047 switch p.As { 3048 default: 3049 ctxt.Diag("invalid opcode") 3050 case AFMUL: 3051 opcode = op_MDBR 3052 case AFMULS: 3053 opcode = op_MEEBR 3054 } 3055 3056 if r == int(p.To.Reg) { 3057 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3058 } else if p.From.Reg == p.To.Reg { 3059 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3060 } else { 3061 zRR(op_LDR, uint32(p.To.Reg), uint32(r), asm) 3062 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3063 } 3064 3065 case 33: // float op [freg] freg 3066 r := p.From.Reg 3067 if oclass(&p.From) == C_NONE { 3068 r = p.To.Reg 3069 } 3070 var opcode uint32 3071 switch p.As { 3072 default: 3073 case AFABS: 3074 opcode = op_LPDBR 3075 case AFNABS: 3076 opcode = op_LNDBR 3077 case AFNEG: 3078 opcode = op_LCDFR 3079 case ALEDBR: 3080 opcode = op_LEDBR 3081 case ALDEBR: 3082 opcode = op_LDEBR 3083 case AFSQRT: 3084 opcode = op_SQDBR 3085 case AFSQRTS: 3086 opcode = op_SQEBR 3087 } 3088 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm) 3089 3090 case 34: // float multiply-add freg freg freg freg 3091 var opcode uint32 3092 3093 switch p.As { 3094 default: 3095 ctxt.Diag("invalid opcode") 3096 case AFMADD: 3097 opcode = op_MADBR 3098 case AFMADDS: 3099 opcode = op_MAEBR 3100 case AFMSUB: 3101 opcode = op_MSDBR 3102 case AFMSUBS: 3103 opcode = op_MSEBR 3104 case AFNMADD: 3105 opcode = op_MADBR 3106 case AFNMADDS: 3107 opcode = op_MAEBR 3108 case AFNMSUB: 3109 opcode = op_MSDBR 3110 case AFNMSUBS: 3111 opcode = op_MSEBR 3112 } 3113 3114 zRR(op_LDR, uint32(p.To.Reg), uint32(p.Reg), asm) 3115 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From3.Reg), asm) 3116 3117 if p.As == AFNMADD || p.As == AFNMADDS || p.As == AFNMSUB || p.As == AFNMSUBS { 3118 zRRE(op_LCDFR, uint32(p.To.Reg), uint32(p.To.Reg), asm) 3119 } 3120 3121 case 35: // mov reg mem (no relocation) 3122 d2 := regoff(ctxt, &p.To) 3123 b2 := p.To.Reg 3124 if b2 == 0 { 3125 b2 = o.param 3126 } 3127 x2 := p.To.Index 3128 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3129 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3130 if x2 != 0 { 3131 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3132 } 3133 x2 = REGTMP 3134 d2 = 0 3135 } 3136 zRXY(zopstore(ctxt, p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3137 3138 case 36: // mov mem reg (no relocation) 3139 d2 := regoff(ctxt, &p.From) 3140 b2 := p.From.Reg 3141 if b2 == 0 { 3142 b2 = o.param 3143 } 3144 x2 := p.From.Index 3145 if d2 < -DISP20/2 || d2 >= DISP20/2 { 3146 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm) 3147 if x2 != 0 { 3148 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm) 3149 } 3150 x2 = REGTMP 3151 d2 = 0 3152 } 3153 zRXY(zopload(ctxt, p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm) 3154 3155 case 40: // word/byte 3156 wd := uint32(regoff(ctxt, &p.From)) 3157 if p.As == AWORD { //WORD 3158 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd)) 3159 } else { //BYTE 3160 *asm = append(*asm, uint8(wd)) 3161 } 3162 3163 case 47: // arithmetic op (carry) reg [reg] reg 3164 switch p.As { 3165 default: 3166 3167 case AADDME: 3168 r := int(p.From.Reg) 3169 if p.To.Reg == p.From.Reg { 3170 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3171 r = REGTMP 3172 } 3173 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1 3174 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm) 3175 3176 case AADDZE: 3177 r := int(p.From.Reg) 3178 if p.To.Reg == p.From.Reg { 3179 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3180 r = REGTMP 3181 } 3182 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0 3183 zRRE(op_ALCGR, uint32(p.To.Reg), uint32(r), asm) 3184 3185 case ASUBME: 3186 r := int(p.From.Reg) 3187 if p.To.Reg == p.From.Reg { 3188 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3189 r = REGTMP 3190 } 3191 zRIL(_a, op_LGFI, uint32(p.To.Reg), 0xffffffff, asm) // p.To.Reg <- -1 3192 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm) 3193 3194 case ASUBZE: 3195 r := int(p.From.Reg) 3196 if p.To.Reg == p.From.Reg { 3197 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm) 3198 r = REGTMP 3199 } 3200 zRRE(op_LGR, uint32(p.To.Reg), REGZERO, asm) // p.To.Reg <- 0 3201 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(r), asm) 3202 3203 case ANEG: 3204 r := int(p.From.Reg) 3205 if r == 0 { 3206 r = int(p.To.Reg) 3207 } 3208 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm) 3209 } 3210 3211 case 48: // floating-point round to integer 3212 m3 := vregoff(ctxt, &p.From) 3213 if 0 > m3 || m3 > 7 { 3214 ctxt.Diag("mask (%v) must be in the range [0, 7]", m3) 3215 } 3216 var opcode uint32 3217 switch p.As { 3218 case AFIEBR: 3219 opcode = op_FIEBR 3220 case AFIDBR: 3221 opcode = op_FIDBR 3222 } 3223 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm) 3224 3225 case 67: // fmov $0 freg 3226 var opcode uint32 3227 switch p.As { 3228 case AFMOVS: 3229 opcode = op_LZER 3230 case AFMOVD: 3231 opcode = op_LZDR 3232 } 3233 zRRE(opcode, uint32(p.To.Reg), 0, asm) 3234 3235 case 68: // movw areg reg 3236 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm) 3237 3238 case 69: // movw reg areg 3239 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm) 3240 3241 case 70: // cmp reg reg 3242 if p.As == ACMPW || p.As == ACMPWU { 3243 zRR(zoprr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3244 } else { 3245 zRRE(zoprre(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm) 3246 } 3247 3248 case 71: // cmp reg $constant 3249 v := vregoff(ctxt, &p.To) 3250 switch p.As { 3251 case ACMP, ACMPW: 3252 if int64(int32(v)) != v { 3253 ctxt.Diag("%v overflows an int32", v) 3254 } 3255 case ACMPU, ACMPWU: 3256 if int64(uint32(v)) != v { 3257 ctxt.Diag("%v overflows a uint32", v) 3258 } 3259 } 3260 zRIL(_a, zopril(ctxt, p.As), uint32(p.From.Reg), uint32(regoff(ctxt, &p.To)), asm) 3261 3262 case 72: // mov $constant/$addr mem 3263 v := regoff(ctxt, &p.From) 3264 d := regoff(ctxt, &p.To) 3265 r := p.To.Reg 3266 x := p.To.Index 3267 if r == 0 { 3268 r = o.param 3269 } 3270 if p.From.Sym != nil { 3271 zRIL(_b, op_LARL, REGTMP, 0, asm) 3272 if v&0x1 != 0 { 3273 v -= 1 3274 zRX(op_LA, REGTMP, REGTMP, 0, 1, asm) 3275 } 3276 addrilreloc(ctxt, p.From.Sym, int64(v)) 3277 if d < -DISP20/2 || d >= DISP20/2 { 3278 zRIL(_a, op_LGFI, REGTMP2, uint32(d), asm) 3279 if x != 0 { 3280 zRRE(op_AGR, REGTMP2, uint32(x), asm) 3281 } 3282 d = 0 3283 x = REGTMP2 3284 } 3285 zRXY(zopstore(ctxt, p.As), REGTMP, uint32(x), uint32(r), uint32(d), asm) 3286 } else if int32(int16(v)) == v && x == 0 { 3287 if d < 0 || d >= DISP12 { 3288 if r == REGTMP || r == REGTMP2 { 3289 zRIL(_a, op_AGFI, uint32(r), uint32(d), asm) 3290 } else { 3291 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3292 zRRE(op_AGR, REGTMP, uint32(r), asm) 3293 r = REGTMP 3294 } 3295 d = 0 3296 } 3297 var opcode uint32 3298 switch p.As { 3299 case AMOVD: 3300 opcode = op_MVGHI 3301 case AMOVW, AMOVWZ: 3302 opcode = op_MVHI 3303 case AMOVH, AMOVHZ: 3304 opcode = op_MVHHI 3305 case AMOVB, AMOVBZ: 3306 opcode = op_MVI 3307 } 3308 if opcode == op_MVI { 3309 zSI(opcode, uint32(v), uint32(r), uint32(d), asm) 3310 } else { 3311 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm) 3312 } 3313 } else { 3314 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3315 if d < -DISP20/2 || d >= DISP20/2 { 3316 if r == REGTMP { 3317 zRIL(_a, op_AGFI, REGTMP, uint32(d), asm) 3318 } else { 3319 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm) 3320 if x != 0 { 3321 zRRE(op_AGR, REGTMP, uint32(x), asm) 3322 } 3323 x = REGTMP 3324 } 3325 d = 0 3326 } 3327 zRXY(zopstore(ctxt, p.As), REGTMP2, uint32(x), uint32(r), uint32(d), asm) 3328 } 3329 3330 case 73: // mov $constant addr (including relocation) 3331 v := regoff(ctxt, &p.From) 3332 d := regoff(ctxt, &p.To) 3333 a := uint32(0) 3334 if d&1 != 0 { 3335 d -= 1 3336 a = 1 3337 } 3338 zRIL(_b, op_LARL, REGTMP, uint32(d), asm) 3339 addrilreloc(ctxt, p.To.Sym, int64(d)) 3340 if p.From.Sym != nil { 3341 zRIL(_b, op_LARL, REGTMP2, 0, asm) 3342 a := uint32(0) 3343 if v&0x1 != 0 { 3344 v -= 1 3345 zRX(op_LA, REGTMP2, REGTMP2, 0, 1, asm) 3346 } 3347 addrilrelocoffset(ctxt, p.From.Sym, int64(v), sizeRIL) 3348 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3349 } else if int32(int16(v)) == v { 3350 var opcode uint32 3351 switch p.As { 3352 case AMOVD: 3353 opcode = op_MVGHI 3354 case AMOVW, AMOVWZ: 3355 opcode = op_MVHI 3356 case AMOVH, AMOVHZ: 3357 opcode = op_MVHHI 3358 case AMOVB, AMOVBZ: 3359 opcode = op_MVI 3360 } 3361 if opcode == op_MVI { 3362 zSI(opcode, uint32(v), REGTMP, a, asm) 3363 } else { 3364 zSIL(opcode, REGTMP, a, uint32(v), asm) 3365 } 3366 } else { 3367 zRIL(_a, op_LGFI, REGTMP2, uint32(v), asm) 3368 zRXY(zopstore(ctxt, p.As), REGTMP2, 0, REGTMP, a, asm) 3369 } 3370 3371 case 74: // mov reg addr (including relocation) 3372 i2 := regoff(ctxt, &p.To) 3373 switch p.As { 3374 case AMOVD: 3375 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm) 3376 case AMOVW, AMOVWZ: // The zero extension doesn't affect store instructions 3377 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm) 3378 case AMOVH, AMOVHZ: // The zero extension doesn't affect store instructions 3379 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm) 3380 case AMOVB, AMOVBZ: // The zero extension doesn't affect store instructions 3381 zRIL(_b, op_LARL, REGTMP, 0, asm) 3382 adj := uint32(0) // adjustment needed for odd addresses 3383 if i2&1 != 0 { 3384 i2 -= 1 3385 adj = 1 3386 } 3387 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm) 3388 case AFMOVD: 3389 zRIL(_b, op_LARL, REGTMP, 0, asm) 3390 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3391 case AFMOVS: 3392 zRIL(_b, op_LARL, REGTMP, 0, asm) 3393 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm) 3394 } 3395 addrilreloc(ctxt, p.To.Sym, int64(i2)) 3396 3397 case 75: // mov addr reg (including relocation) 3398 i2 := regoff(ctxt, &p.From) 3399 switch p.As { 3400 case AMOVD: 3401 if i2&1 != 0 { 3402 zRIL(_b, op_LARL, REGTMP, 0, asm) 3403 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm) 3404 i2 -= 1 3405 } else { 3406 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3407 } 3408 case AMOVW: 3409 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm) 3410 case AMOVWZ: 3411 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm) 3412 case AMOVH: 3413 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm) 3414 case AMOVHZ: 3415 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm) 3416 case AMOVB, AMOVBZ: 3417 zRIL(_b, op_LARL, REGTMP, 0, asm) 3418 adj := uint32(0) // adjustment needed for odd addresses 3419 if i2&1 != 0 { 3420 i2 -= 1 3421 adj = 1 3422 } 3423 switch p.As { 3424 case AMOVB: 3425 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3426 case AMOVBZ: 3427 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm) 3428 } 3429 case AFMOVD: 3430 zRIL(_a, op_LARL, REGTMP, 0, asm) 3431 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3432 case AFMOVS: 3433 zRIL(_a, op_LARL, REGTMP, 0, asm) 3434 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm) 3435 } 3436 addrilreloc(ctxt, p.From.Sym, int64(i2)) 3437 3438 case 77: // syscall $constant 3439 if p.From.Offset > 255 || p.From.Offset < 1 { 3440 ctxt.Diag("illegal system call; system call number out of range: %v", p) 3441 zE(op_TRAP2, asm) // trap always 3442 } else { 3443 zI(op_SVC, uint32(p.From.Offset), asm) 3444 } 3445 3446 case 78: // undef 3447 // "An instruction consisting entirely of binary 0s is guaranteed 3448 // always to be an illegal instruction." 3449 *asm = append(*asm, 0, 0, 0, 0) 3450 3451 case 79: // compare and swap reg reg reg 3452 v := regoff(ctxt, &p.To) 3453 if v < 0 { 3454 v = 0 3455 } 3456 if p.As == ACS { 3457 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3458 } else if p.As == ACSG { 3459 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm) 3460 } 3461 3462 case 81: // sync 3463 zRR(op_BCR, 0xE, 0, asm) 3464 3465 case 82: // fixed to float conversion 3466 var opcode uint32 3467 switch p.As { 3468 default: 3469 log.Fatalf("unexpected opcode %v", p.As) 3470 case ACEFBRA: 3471 opcode = op_CEFBRA 3472 case ACDFBRA: 3473 opcode = op_CDFBRA 3474 case ACEGBRA: 3475 opcode = op_CEGBRA 3476 case ACDGBRA: 3477 opcode = op_CDGBRA 3478 case ACELFBR: 3479 opcode = op_CELFBR 3480 case ACDLFBR: 3481 opcode = op_CDLFBR 3482 case ACELGBR: 3483 opcode = op_CELGBR 3484 case ACDLGBR: 3485 opcode = op_CDLGBR 3486 } 3487 // set immediate operand M3 to 0 to use the default BFP rounding mode 3488 // (usually round to nearest, ties to even) 3489 // TODO(mundaym): should this be fixed at round to nearest, ties to even? 3490 // M4 is reserved and must be 0 3491 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3492 3493 case 83: // float to fixed conversion 3494 var opcode uint32 3495 switch p.As { 3496 default: 3497 log.Fatalf("unexpected opcode %v", p.As) 3498 case ACFEBRA: 3499 opcode = op_CFEBRA 3500 case ACFDBRA: 3501 opcode = op_CFDBRA 3502 case ACGEBRA: 3503 opcode = op_CGEBRA 3504 case ACGDBRA: 3505 opcode = op_CGDBRA 3506 case ACLFEBR: 3507 opcode = op_CLFEBR 3508 case ACLFDBR: 3509 opcode = op_CLFDBR 3510 case ACLGEBR: 3511 opcode = op_CLGEBR 3512 case ACLGDBR: 3513 opcode = op_CLGDBR 3514 } 3515 // set immediate operand M3 to 5 for rounding toward zero (required by Go spec) 3516 // M4 is reserved and must be 0 3517 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm) 3518 3519 case 84: // storage-and-storage operations $length mem mem (length in From3) 3520 l := regoff(ctxt, p.From3) 3521 if l < 1 || l > 256 { 3522 ctxt.Diag("number of bytes (%v) not in range [1,256]", l) 3523 } 3524 if p.From.Index != 0 || p.To.Index != 0 { 3525 ctxt.Diag("cannot use index reg") 3526 } 3527 b1 := p.To.Reg 3528 b2 := p.From.Reg 3529 if b1 == 0 { 3530 b1 = o.param 3531 } 3532 if b2 == 0 { 3533 b2 = o.param 3534 } 3535 d1 := regoff(ctxt, &p.To) 3536 d2 := regoff(ctxt, &p.From) 3537 if d1 < 0 || d1 >= DISP12 { 3538 if b2 == REGTMP { 3539 ctxt.Diag("REGTMP conflict") 3540 } 3541 if b1 != REGTMP { 3542 zRRE(op_LGR, REGTMP, uint32(b1), asm) 3543 } 3544 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm) 3545 if d1 == d2 && b1 == b2 { 3546 d2 = 0 3547 b2 = REGTMP 3548 } 3549 d1 = 0 3550 b1 = REGTMP 3551 } 3552 if d2 < 0 || d2 >= DISP12 { 3553 if b1 == REGTMP2 { 3554 ctxt.Diag("REGTMP2 conflict") 3555 } 3556 if b2 != REGTMP2 { 3557 zRRE(op_LGR, REGTMP2, uint32(b2), asm) 3558 } 3559 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm) 3560 d2 = 0 3561 b2 = REGTMP2 3562 } 3563 var opcode uint32 3564 switch p.As { 3565 default: 3566 ctxt.Diag("unexpected opcode %v", p.As) 3567 case AMVC: 3568 opcode = op_MVC 3569 case ACLC: 3570 opcode = op_CLC 3571 // swap operand order for CLC so that it matches CMP 3572 b1, b2 = b2, b1 3573 d1, d2 = d2, d1 3574 case AXC: 3575 opcode = op_XC 3576 case AOC: 3577 opcode = op_OC 3578 case ANC: 3579 opcode = op_NC 3580 } 3581 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm) 3582 3583 case 85: // load address relative long 3584 v := regoff(ctxt, &p.From) 3585 if p.From.Sym == nil { 3586 if (v & 1) != 0 { 3587 ctxt.Diag("cannot use LARL with odd offset: %v", v) 3588 } 3589 } else { 3590 addrilreloc(ctxt, p.From.Sym, int64(v)) 3591 v = 0 3592 } 3593 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm) 3594 3595 case 86: // load address 3596 d := vregoff(ctxt, &p.From) 3597 x := p.From.Index 3598 b := p.From.Reg 3599 if b == 0 { 3600 b = o.param 3601 } 3602 switch p.As { 3603 case ALA: 3604 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3605 case ALAY: 3606 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm) 3607 } 3608 3609 case 87: // execute relative long 3610 v := vregoff(ctxt, &p.From) 3611 if p.From.Sym == nil { 3612 if v&1 != 0 { 3613 ctxt.Diag("cannot use EXRL with odd offset: %v", v) 3614 } 3615 } else { 3616 addrilreloc(ctxt, p.From.Sym, v) 3617 v = 0 3618 } 3619 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm) 3620 3621 case 88: // store clock 3622 var opcode uint32 3623 switch p.As { 3624 case ASTCK: 3625 opcode = op_STCK 3626 case ASTCKC: 3627 opcode = op_STCKC 3628 case ASTCKE: 3629 opcode = op_STCKE 3630 case ASTCKF: 3631 opcode = op_STCKF 3632 } 3633 v := vregoff(ctxt, &p.To) 3634 r := int(p.To.Reg) 3635 if r == 0 { 3636 r = int(o.param) 3637 } 3638 zS(opcode, uint32(r), uint32(v), asm) 3639 3640 case 89: // compare and branch reg reg 3641 var v int32 3642 if p.Pcond != nil { 3643 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3644 } 3645 var opcode, opcode2 uint32 3646 switch p.As { 3647 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3648 opcode = op_CGRJ 3649 opcode2 = op_CGR 3650 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3651 opcode = op_CLGRJ 3652 opcode2 = op_CLGR 3653 } 3654 mask := branchMask(ctxt, p) 3655 if int32(int16(v)) != v { 3656 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm) 3657 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm) 3658 } else { 3659 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm) 3660 } 3661 3662 case 90: // compare and branch reg $constant 3663 var v int32 3664 if p.Pcond != nil { 3665 v = int32((p.Pcond.Pc - p.Pc) >> 1) 3666 } 3667 var opcode, opcode2 uint32 3668 switch p.As { 3669 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE: 3670 opcode = op_CGIJ 3671 opcode2 = op_CGFI 3672 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE: 3673 opcode = op_CLGIJ 3674 opcode2 = op_CLGFI 3675 } 3676 mask := branchMask(ctxt, p) 3677 if int32(int16(v)) != v { 3678 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(regoff(ctxt, p.From3)), asm) 3679 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm) 3680 } else { 3681 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(regoff(ctxt, p.From3)), asm) 3682 } 3683 3684 case 93: // GOT lookup 3685 v := vregoff(ctxt, &p.To) 3686 if v != 0 { 3687 ctxt.Diag("invalid offset against GOT slot %v", p) 3688 } 3689 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm) 3690 rel := obj.Addrel(ctxt.Cursym) 3691 rel.Off = int32(ctxt.Pc + 2) 3692 rel.Siz = 4 3693 rel.Sym = p.From.Sym 3694 rel.Type = obj.R_GOTPCREL 3695 rel.Add = 2 + int64(rel.Siz) 3696 3697 case 94: // TLS local exec model 3698 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm) 3699 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3700 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm) 3701 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0) 3702 rel := obj.Addrel(ctxt.Cursym) 3703 rel.Off = int32(ctxt.Pc + sizeRIL + sizeRXY + sizeRI) 3704 rel.Siz = 8 3705 rel.Sym = p.From.Sym 3706 rel.Type = obj.R_TLS_LE 3707 rel.Add = 0 3708 3709 case 95: // TLS initial exec model 3710 // Assembly | Relocation symbol | Done Here? 3711 // -------------------------------------------------------------- 3712 // ear %r11, %a0 | | 3713 // sllg %r11, %r11, 32 | | 3714 // ear %r11, %a1 | | 3715 // larl %r10, <var>@indntpoff | R_390_TLS_IEENT | Y 3716 // lg %r10, 0(%r10) | R_390_TLS_LOAD (tag) | Y 3717 // la %r10, 0(%r10, %r11) | | 3718 // -------------------------------------------------------------- 3719 3720 // R_390_TLS_IEENT 3721 zRIL(_b, op_LARL, REGTMP, 0, asm) 3722 ieent := obj.Addrel(ctxt.Cursym) 3723 ieent.Off = int32(ctxt.Pc + 2) 3724 ieent.Siz = 4 3725 ieent.Sym = p.From.Sym 3726 ieent.Type = obj.R_TLS_IE 3727 ieent.Add = 2 + int64(ieent.Siz) 3728 3729 // R_390_TLS_LOAD 3730 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm) 3731 // TODO(mundaym): add R_390_TLS_LOAD relocation here 3732 // not strictly required but might allow the linker to optimize 3733 3734 case 96: // clear macro 3735 length := vregoff(ctxt, &p.From) 3736 offset := vregoff(ctxt, &p.To) 3737 reg := p.To.Reg 3738 if reg == 0 { 3739 reg = o.param 3740 } 3741 if length <= 0 { 3742 ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length) 3743 } 3744 for length > 0 { 3745 if offset < 0 || offset >= DISP12 { 3746 if offset >= -DISP20/2 && offset < DISP20/2 { 3747 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm) 3748 } else { 3749 if reg != REGTMP { 3750 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3751 } 3752 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3753 } 3754 reg = REGTMP 3755 offset = 0 3756 } 3757 size := length 3758 if size > 256 { 3759 size = 256 3760 } 3761 3762 switch size { 3763 case 1: 3764 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm) 3765 case 2: 3766 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm) 3767 case 4: 3768 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm) 3769 case 8: 3770 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm) 3771 default: 3772 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm) 3773 } 3774 3775 length -= size 3776 offset += size 3777 } 3778 3779 case 97: // store multiple 3780 rstart := p.From.Reg 3781 rend := p.Reg 3782 offset := regoff(ctxt, &p.To) 3783 reg := p.To.Reg 3784 if reg == 0 { 3785 reg = o.param 3786 } 3787 if offset < -DISP20/2 || offset >= DISP20/2 { 3788 if reg != REGTMP { 3789 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3790 } 3791 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3792 reg = REGTMP 3793 offset = 0 3794 } 3795 switch p.As { 3796 case ASTMY: 3797 if offset >= 0 && offset < DISP12 { 3798 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3799 } else { 3800 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3801 } 3802 case ASTMG: 3803 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3804 } 3805 3806 case 98: // load multiple 3807 rstart := p.Reg 3808 rend := p.To.Reg 3809 offset := regoff(ctxt, &p.From) 3810 reg := p.From.Reg 3811 if reg == 0 { 3812 reg = o.param 3813 } 3814 if offset < -DISP20/2 || offset >= DISP20/2 { 3815 if reg != REGTMP { 3816 zRRE(op_LGR, REGTMP, uint32(reg), asm) 3817 } 3818 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm) 3819 reg = REGTMP 3820 offset = 0 3821 } 3822 switch p.As { 3823 case ALMY: 3824 if offset >= 0 && offset < DISP12 { 3825 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3826 } else { 3827 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3828 } 3829 case ALMG: 3830 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm) 3831 } 3832 3833 case 99: // interlocked load and op 3834 if p.To.Index != 0 { 3835 ctxt.Diag("cannot use indexed address") 3836 } 3837 offset := regoff(ctxt, &p.To) 3838 if offset < -DISP20/2 || offset >= DISP20/2 { 3839 ctxt.Diag("%v does not fit into 20-bit signed integer", offset) 3840 } 3841 var opcode uint32 3842 switch p.As { 3843 case ALAA: 3844 opcode = op_LAA 3845 case ALAAG: 3846 opcode = op_LAAG 3847 case ALAAL: 3848 opcode = op_LAAL 3849 case ALAALG: 3850 opcode = op_LAALG 3851 case ALAN: 3852 opcode = op_LAN 3853 case ALANG: 3854 opcode = op_LANG 3855 case ALAX: 3856 opcode = op_LAX 3857 case ALAXG: 3858 opcode = op_LAXG 3859 case ALAO: 3860 opcode = op_LAO 3861 case ALAOG: 3862 opcode = op_LAOG 3863 } 3864 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm) 3865 3866 case 100: // VRX STORE 3867 op, m3, _ := vop(p.As) 3868 if p.From3 != nil { 3869 m3 = uint32(vregoff(ctxt, p.From3)) 3870 } 3871 b2 := p.To.Reg 3872 if b2 == 0 { 3873 b2 = o.param 3874 } 3875 d2 := uint32(vregoff(ctxt, &p.To)) 3876 zVRX(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3877 3878 case 101: // VRX LOAD 3879 op, m3, _ := vop(p.As) 3880 if p.From3 != nil { 3881 m3 = uint32(vregoff(ctxt, p.From3)) 3882 } 3883 b2 := p.From.Reg 3884 if b2 == 0 { 3885 b2 = o.param 3886 } 3887 d2 := uint32(vregoff(ctxt, &p.From)) 3888 zVRX(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3889 3890 case 102: // VRV SCATTER 3891 op, m3, _ := vop(p.As) 3892 if p.From3 != nil { 3893 m3 = uint32(vregoff(ctxt, p.From3)) 3894 } 3895 b2 := p.To.Reg 3896 if b2 == 0 { 3897 b2 = o.param 3898 } 3899 d2 := uint32(vregoff(ctxt, &p.To)) 3900 zVRV(op, uint32(p.From.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm) 3901 3902 case 103: // VRV GATHER 3903 op, m3, _ := vop(p.As) 3904 if p.From3 != nil { 3905 m3 = uint32(vregoff(ctxt, p.From3)) 3906 } 3907 b2 := p.From.Reg 3908 if b2 == 0 { 3909 b2 = o.param 3910 } 3911 d2 := uint32(vregoff(ctxt, &p.From)) 3912 zVRV(op, uint32(p.To.Reg), uint32(p.From.Index), uint32(b2), d2, m3, asm) 3913 3914 case 104: // VRS SHIFT/ROTATE and LOAD GR FROM VR ELEMENT 3915 op, m4, _ := vop(p.As) 3916 fr := p.Reg 3917 if fr == 0 { 3918 fr = p.To.Reg 3919 } 3920 bits := uint32(vregoff(ctxt, &p.From)) 3921 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm) 3922 3923 case 105: // VRS STORE MULTIPLE 3924 op, _, _ := vop(p.As) 3925 offset := uint32(vregoff(ctxt, &p.To)) 3926 reg := p.To.Reg 3927 if reg == 0 { 3928 reg = o.param 3929 } 3930 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm) 3931 3932 case 106: // VRS LOAD MULTIPLE 3933 op, _, _ := vop(p.As) 3934 offset := uint32(vregoff(ctxt, &p.From)) 3935 reg := p.From.Reg 3936 if reg == 0 { 3937 reg = o.param 3938 } 3939 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm) 3940 3941 case 107: // VRS STORE WITH LENGTH 3942 op, _, _ := vop(p.As) 3943 offset := uint32(vregoff(ctxt, &p.To)) 3944 reg := p.To.Reg 3945 if reg == 0 { 3946 reg = o.param 3947 } 3948 zVRS(op, uint32(p.From.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3949 3950 case 108: // VRS LOAD WITH LENGTH 3951 op, _, _ := vop(p.As) 3952 offset := uint32(vregoff(ctxt, &p.From)) 3953 reg := p.From.Reg 3954 if reg == 0 { 3955 reg = o.param 3956 } 3957 zVRS(op, uint32(p.To.Reg), uint32(p.From3.Reg), uint32(reg), offset, 0, asm) 3958 3959 case 109: // VRI-a 3960 op, _, _ := vop(p.As) 3961 i2 := uint32(vregoff(ctxt, &p.From)) 3962 switch p.As { 3963 case AVZERO: 3964 i2 = 0 3965 case AVONE: 3966 i2 = 0xffff 3967 } 3968 m3 := uint32(0) 3969 if p.From3 != nil { 3970 m3 = uint32(vregoff(ctxt, p.From3)) 3971 } 3972 zVRIa(op, uint32(p.To.Reg), i2, m3, asm) 3973 3974 case 110: 3975 op, m4, _ := vop(p.As) 3976 i2 := uint32(vregoff(ctxt, p.From3)) 3977 i3 := uint32(vregoff(ctxt, &p.From)) 3978 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm) 3979 3980 case 111: 3981 op, m4, _ := vop(p.As) 3982 i2 := uint32(vregoff(ctxt, &p.From)) 3983 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm) 3984 3985 case 112: 3986 op, m5, _ := vop(p.As) 3987 i4 := uint32(vregoff(ctxt, p.From3)) 3988 zVRId(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), i4, m5, asm) 3989 3990 case 113: 3991 op, m4, _ := vop(p.As) 3992 m5 := singleElementMask(p.As) 3993 i3 := uint32(vregoff(ctxt, &p.From)) 3994 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm) 3995 3996 case 114: // VRR-a 3997 op, m3, m5 := vop(p.As) 3998 m4 := singleElementMask(p.As) 3999 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm) 4000 4001 case 115: // VRR-a COMPARE 4002 op, m3, m5 := vop(p.As) 4003 m4 := singleElementMask(p.As) 4004 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm) 4005 4006 case 116: // VRR-a 4007 4008 case 117: // VRR-b 4009 op, m4, m5 := vop(p.As) 4010 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm) 4011 4012 case 118: // VRR-c 4013 op, m4, m6 := vop(p.As) 4014 m5 := singleElementMask(p.As) 4015 v3 := p.Reg 4016 if v3 == 0 { 4017 v3 = p.To.Reg 4018 } 4019 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm) 4020 4021 case 119: // VRR-c SHIFT/ROTATE/DIVIDE/SUB (rhs value on the left, like SLD, DIV etc.) 4022 op, m4, m6 := vop(p.As) 4023 m5 := singleElementMask(p.As) 4024 v2 := p.Reg 4025 if v2 == 0 { 4026 v2 = p.To.Reg 4027 } 4028 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm) 4029 4030 case 120: // VRR-d 4031 op, m6, _ := vop(p.As) 4032 m5 := singleElementMask(p.As) 4033 v1 := uint32(p.To.Reg) 4034 v2 := uint32(p.From3.Reg) 4035 v3 := uint32(p.From.Reg) 4036 v4 := uint32(p.Reg) 4037 zVRRd(op, v1, v2, v3, m6, m5, v4, asm) 4038 4039 case 121: // VRR-e 4040 op, m6, _ := vop(p.As) 4041 m5 := singleElementMask(p.As) 4042 v1 := uint32(p.To.Reg) 4043 v2 := uint32(p.From3.Reg) 4044 v3 := uint32(p.From.Reg) 4045 v4 := uint32(p.Reg) 4046 zVRRe(op, v1, v2, v3, m5, m6, v4, asm) 4047 4048 case 122: // VRR-f LOAD VRS FROM GRS DISJOINT 4049 op, _, _ := vop(p.As) 4050 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm) 4051 4052 case 123: // VPDI $m4, V2, V3, V1 4053 op, _, _ := vop(p.As) 4054 m4 := regoff(ctxt, p.From3) 4055 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), 0, 0, uint32(m4), asm) 4056 } 4057 } 4058 4059 func vregoff(ctxt *obj.Link, a *obj.Addr) int64 { 4060 ctxt.Instoffset = 0 4061 if a != nil { 4062 aclass(ctxt, a) 4063 } 4064 return ctxt.Instoffset 4065 } 4066 4067 func regoff(ctxt *obj.Link, a *obj.Addr) int32 { 4068 return int32(vregoff(ctxt, a)) 4069 } 4070 4071 // zopload returns the RXY op for the given load 4072 func zopload(ctxt *obj.Link, a obj.As) uint32 { 4073 switch a { 4074 // fixed point load 4075 case AMOVD: 4076 return op_LG 4077 case AMOVW: 4078 return op_LGF 4079 case AMOVWZ: 4080 return op_LLGF 4081 case AMOVH: 4082 return op_LGH 4083 case AMOVHZ: 4084 return op_LLGH 4085 case AMOVB: 4086 return op_LGB 4087 case AMOVBZ: 4088 return op_LLGC 4089 4090 // floating point load 4091 case AFMOVD: 4092 return op_LDY 4093 case AFMOVS: 4094 return op_LEY 4095 4096 // byte reversed load 4097 case AMOVDBR: 4098 return op_LRVG 4099 case AMOVWBR: 4100 return op_LRV 4101 case AMOVHBR: 4102 return op_LRVH 4103 } 4104 4105 ctxt.Diag("unknown store opcode %v", a) 4106 return 0 4107 } 4108 4109 // zopstore returns the RXY op for the given store 4110 func zopstore(ctxt *obj.Link, a obj.As) uint32 { 4111 switch a { 4112 // fixed point store 4113 case AMOVD: 4114 return op_STG 4115 case AMOVW, AMOVWZ: 4116 return op_STY 4117 case AMOVH, AMOVHZ: 4118 return op_STHY 4119 case AMOVB, AMOVBZ: 4120 return op_STCY 4121 4122 // floating point store 4123 case AFMOVD: 4124 return op_STDY 4125 case AFMOVS: 4126 return op_STEY 4127 4128 // byte reversed store 4129 case AMOVDBR: 4130 return op_STRVG 4131 case AMOVWBR: 4132 return op_STRV 4133 case AMOVHBR: 4134 return op_STRVH 4135 } 4136 4137 ctxt.Diag("unknown store opcode %v", a) 4138 return 0 4139 } 4140 4141 // zoprre returns the RRE op for the given a 4142 func zoprre(ctxt *obj.Link, a obj.As) uint32 { 4143 switch a { 4144 case ACMP: 4145 return op_CGR 4146 case ACMPU: 4147 return op_CLGR 4148 case AFCMPO: //ordered 4149 return op_KDBR 4150 case AFCMPU: //unordered 4151 return op_CDBR 4152 case ACEBR: 4153 return op_CEBR 4154 } 4155 ctxt.Diag("unknown rre opcode %v", a) 4156 return 0 4157 } 4158 4159 // zoprr returns the RR op for the given a 4160 func zoprr(ctxt *obj.Link, a obj.As) uint32 { 4161 switch a { 4162 case ACMPW: 4163 return op_CR 4164 case ACMPWU: 4165 return op_CLR 4166 } 4167 ctxt.Diag("unknown rr opcode %v", a) 4168 return 0 4169 } 4170 4171 // zopril returns the RIL op for the given a 4172 func zopril(ctxt *obj.Link, a obj.As) uint32 { 4173 switch a { 4174 case ACMP: 4175 return op_CGFI 4176 case ACMPU: 4177 return op_CLGFI 4178 case ACMPW: 4179 return op_CFI 4180 case ACMPWU: 4181 return op_CLFI 4182 } 4183 ctxt.Diag("unknown ril opcode %v", a) 4184 return 0 4185 } 4186 4187 // z instructions sizes 4188 const ( 4189 sizeE = 2 4190 sizeI = 2 4191 sizeIE = 4 4192 sizeMII = 6 4193 sizeRI = 4 4194 sizeRI1 = 4 4195 sizeRI2 = 4 4196 sizeRI3 = 4 4197 sizeRIE = 6 4198 sizeRIE1 = 6 4199 sizeRIE2 = 6 4200 sizeRIE3 = 6 4201 sizeRIE4 = 6 4202 sizeRIE5 = 6 4203 sizeRIE6 = 6 4204 sizeRIL = 6 4205 sizeRIL1 = 6 4206 sizeRIL2 = 6 4207 sizeRIL3 = 6 4208 sizeRIS = 6 4209 sizeRR = 2 4210 sizeRRD = 4 4211 sizeRRE = 4 4212 sizeRRF = 4 4213 sizeRRF1 = 4 4214 sizeRRF2 = 4 4215 sizeRRF3 = 4 4216 sizeRRF4 = 4 4217 sizeRRF5 = 4 4218 sizeRRR = 2 4219 sizeRRS = 6 4220 sizeRS = 4 4221 sizeRS1 = 4 4222 sizeRS2 = 4 4223 sizeRSI = 4 4224 sizeRSL = 6 4225 sizeRSY = 6 4226 sizeRSY1 = 6 4227 sizeRSY2 = 6 4228 sizeRX = 4 4229 sizeRX1 = 4 4230 sizeRX2 = 4 4231 sizeRXE = 6 4232 sizeRXF = 6 4233 sizeRXY = 6 4234 sizeRXY1 = 6 4235 sizeRXY2 = 6 4236 sizeS = 4 4237 sizeSI = 4 4238 sizeSIL = 6 4239 sizeSIY = 6 4240 sizeSMI = 6 4241 sizeSS = 6 4242 sizeSS1 = 6 4243 sizeSS2 = 6 4244 sizeSS3 = 6 4245 sizeSS4 = 6 4246 sizeSS5 = 6 4247 sizeSS6 = 6 4248 sizeSSE = 6 4249 sizeSSF = 6 4250 ) 4251 4252 // instruction format variations 4253 type form int 4254 4255 const ( 4256 _a form = iota 4257 _b 4258 _c 4259 _d 4260 _e 4261 _f 4262 ) 4263 4264 func zE(op uint32, asm *[]byte) { 4265 *asm = append(*asm, uint8(op>>8), uint8(op)) 4266 } 4267 4268 func zI(op, i1 uint32, asm *[]byte) { 4269 *asm = append(*asm, uint8(op>>8), uint8(i1)) 4270 } 4271 4272 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) { 4273 *asm = append(*asm, 4274 uint8(op>>8), 4275 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F), 4276 uint8(ri2), 4277 uint8(ri3>>16), 4278 uint8(ri3>>8), 4279 uint8(ri3)) 4280 } 4281 4282 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4283 *asm = append(*asm, 4284 uint8(op>>8), 4285 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4286 uint8(i2_ri2>>8), 4287 uint8(i2_ri2)) 4288 } 4289 4290 // Expected argument values for the instruction formats. 4291 // 4292 // Format a1 a2 a3 a4 a5 a6 a7 4293 // ------------------------------------ 4294 // a r1, 0, i2, 0, 0, m3, 0 4295 // b r1, r2, ri4, 0, 0, m3, 0 4296 // c r1, m3, ri4, 0, 0, 0, i2 4297 // d r1, r3, i2, 0, 0, 0, 0 4298 // e r1, r3, ri2, 0, 0, 0, 0 4299 // f r1, r2, 0, i3, i4, 0, i5 4300 // g r1, m3, i2, 0, 0, 0, 0 4301 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) { 4302 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F)) 4303 4304 switch f { 4305 default: 4306 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2)) 4307 case _f: 4308 *asm = append(*asm, uint8(i3), uint8(i4)) 4309 } 4310 4311 switch f { 4312 case _a, _b: 4313 *asm = append(*asm, uint8(m3)<<4) 4314 default: 4315 *asm = append(*asm, uint8(i2_i5)) 4316 } 4317 4318 *asm = append(*asm, uint8(op)) 4319 } 4320 4321 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) { 4322 if f == _a || f == _b { 4323 r1_m1 = r1_m1 - obj.RBaseS390X // this is a register base 4324 } 4325 *asm = append(*asm, 4326 uint8(op>>8), 4327 (uint8(r1_m1)<<4)|(uint8(op)&0x0F), 4328 uint8(i2_ri2>>24), 4329 uint8(i2_ri2>>16), 4330 uint8(i2_ri2>>8), 4331 uint8(i2_ri2)) 4332 } 4333 4334 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) { 4335 *asm = append(*asm, 4336 uint8(op>>8), 4337 (uint8(r1)<<4)|uint8(m3&0x0F), 4338 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F), 4339 uint8(d4), 4340 uint8(i2), 4341 uint8(op)) 4342 } 4343 4344 func zRR(op, r1, r2 uint32, asm *[]byte) { 4345 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F)) 4346 } 4347 4348 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) { 4349 *asm = append(*asm, 4350 uint8(op>>8), 4351 uint8(op), 4352 uint8(r1)<<4, 4353 (uint8(r3)<<4)|uint8(r2&0x0F)) 4354 } 4355 4356 func zRRE(op, r1, r2 uint32, asm *[]byte) { 4357 *asm = append(*asm, 4358 uint8(op>>8), 4359 uint8(op), 4360 0, 4361 (uint8(r1)<<4)|uint8(r2&0x0F)) 4362 } 4363 4364 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) { 4365 *asm = append(*asm, 4366 uint8(op>>8), 4367 uint8(op), 4368 (uint8(r3_m3)<<4)|uint8(m4&0x0F), 4369 (uint8(r1)<<4)|uint8(r2&0x0F)) 4370 } 4371 4372 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) { 4373 *asm = append(*asm, 4374 uint8(op>>8), 4375 (uint8(r1)<<4)|uint8(r2&0x0F), 4376 (uint8(b4)<<4)|uint8((d4>>8)&0x0F), 4377 uint8(d4), 4378 uint8(m3)<<4, 4379 uint8(op)) 4380 } 4381 4382 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4383 *asm = append(*asm, 4384 uint8(op>>8), 4385 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4386 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4387 uint8(d2)) 4388 } 4389 4390 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) { 4391 *asm = append(*asm, 4392 uint8(op>>8), 4393 (uint8(r1)<<4)|uint8(r3&0x0F), 4394 uint8(ri2>>8), 4395 uint8(ri2)) 4396 } 4397 4398 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) { 4399 *asm = append(*asm, 4400 uint8(op>>8), 4401 uint8(l1), 4402 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4403 uint8(d2), 4404 uint8(op)) 4405 } 4406 4407 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) { 4408 dl2 := uint16(d2) & 0x0FFF 4409 *asm = append(*asm, 4410 uint8(op>>8), 4411 (uint8(r1)<<4)|uint8(r3_m3&0x0F), 4412 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4413 uint8(dl2), 4414 uint8(d2>>12), 4415 uint8(op)) 4416 } 4417 4418 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4419 *asm = append(*asm, 4420 uint8(op>>8), 4421 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4422 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4423 uint8(d2)) 4424 } 4425 4426 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) { 4427 *asm = append(*asm, 4428 uint8(op>>8), 4429 (uint8(r1)<<4)|uint8(x2&0x0F), 4430 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4431 uint8(d2), 4432 uint8(m3)<<4, 4433 uint8(op)) 4434 } 4435 4436 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) { 4437 *asm = append(*asm, 4438 uint8(op>>8), 4439 (uint8(r3)<<4)|uint8(x2&0x0F), 4440 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4441 uint8(d2), 4442 uint8(m1)<<4, 4443 uint8(op)) 4444 } 4445 4446 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) { 4447 dl2 := uint16(d2) & 0x0FFF 4448 *asm = append(*asm, 4449 uint8(op>>8), 4450 (uint8(r1_m1)<<4)|uint8(x2&0x0F), 4451 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F), 4452 uint8(dl2), 4453 uint8(d2>>12), 4454 uint8(op)) 4455 } 4456 4457 func zS(op, b2, d2 uint32, asm *[]byte) { 4458 *asm = append(*asm, 4459 uint8(op>>8), 4460 uint8(op), 4461 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4462 uint8(d2)) 4463 } 4464 4465 func zSI(op, i2, b1, d1 uint32, asm *[]byte) { 4466 *asm = append(*asm, 4467 uint8(op>>8), 4468 uint8(i2), 4469 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4470 uint8(d1)) 4471 } 4472 4473 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) { 4474 *asm = append(*asm, 4475 uint8(op>>8), 4476 uint8(op), 4477 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4478 uint8(d1), 4479 uint8(i2>>8), 4480 uint8(i2)) 4481 } 4482 4483 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) { 4484 dl1 := uint16(d1) & 0x0FFF 4485 *asm = append(*asm, 4486 uint8(op>>8), 4487 uint8(i2), 4488 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F), 4489 uint8(dl1), 4490 uint8(d1>>12), 4491 uint8(op)) 4492 } 4493 4494 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) { 4495 *asm = append(*asm, 4496 uint8(op>>8), 4497 uint8(m1)<<4, 4498 (uint8(b3)<<4)|uint8((d3>>8)&0x0F), 4499 uint8(d3), 4500 uint8(ri2>>8), 4501 uint8(ri2)) 4502 } 4503 4504 // Expected argument values for the instruction formats. 4505 // 4506 // Format a1 a2 a3 a4 a5 a6 4507 // ------------------------------- 4508 // a l1, 0, b1, d1, b2, d2 4509 // b l1, l2, b1, d1, b2, d2 4510 // c l1, i3, b1, d1, b2, d2 4511 // d r1, r3, b1, d1, b2, d2 4512 // e r1, r3, b2, d2, b4, d4 4513 // f 0, l2, b1, d1, b2, d2 4514 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) { 4515 *asm = append(*asm, uint8(op>>8)) 4516 4517 switch f { 4518 case _a: 4519 *asm = append(*asm, uint8(l1_r1)) 4520 case _b, _c, _d, _e: 4521 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F)) 4522 case _f: 4523 *asm = append(*asm, uint8(l2_i3_r3)) 4524 } 4525 4526 *asm = append(*asm, 4527 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F), 4528 uint8(d1_d2), 4529 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F), 4530 uint8(d2_d4)) 4531 } 4532 4533 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) { 4534 *asm = append(*asm, 4535 uint8(op>>8), 4536 uint8(op), 4537 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4538 uint8(d1), 4539 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4540 uint8(d2)) 4541 } 4542 4543 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) { 4544 *asm = append(*asm, 4545 uint8(op>>8), 4546 (uint8(r3)<<4)|(uint8(op)&0x0F), 4547 (uint8(b1)<<4)|uint8((d1>>8)&0x0F), 4548 uint8(d1), 4549 (uint8(b2)<<4)|uint8((d2>>8)&0x0F), 4550 uint8(d2)) 4551 } 4552 4553 func rxb(va, vb, vc, vd uint32) uint8 { 4554 mask := uint8(0) 4555 if va >= REG_V16 && va <= REG_V31 { 4556 mask |= 0x8 4557 } 4558 if vb >= REG_V16 && vb <= REG_V31 { 4559 mask |= 0x4 4560 } 4561 if vc >= REG_V16 && vc <= REG_V31 { 4562 mask |= 0x2 4563 } 4564 if vd >= REG_V16 && vd <= REG_V31 { 4565 mask |= 0x1 4566 } 4567 return mask 4568 } 4569 4570 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) { 4571 *asm = append(*asm, 4572 uint8(op>>8), 4573 (uint8(v1)<<4)|(uint8(x2)&0xf), 4574 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4575 uint8(d2), 4576 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4577 uint8(op)) 4578 } 4579 4580 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) { 4581 *asm = append(*asm, 4582 uint8(op>>8), 4583 (uint8(v1)<<4)|(uint8(v2)&0xf), 4584 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4585 uint8(d2), 4586 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4587 uint8(op)) 4588 } 4589 4590 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) { 4591 *asm = append(*asm, 4592 uint8(op>>8), 4593 (uint8(v1)<<4)|(uint8(v3_r3)&0xf), 4594 (uint8(b2)<<4)|(uint8(d2>>8)&0xf), 4595 uint8(d2), 4596 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0), 4597 uint8(op)) 4598 } 4599 4600 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) { 4601 *asm = append(*asm, 4602 uint8(op>>8), 4603 (uint8(v1)<<4)|(uint8(v2)&0xf), 4604 0, 4605 (uint8(m5)<<4)|(uint8(m4)&0xf), 4606 (uint8(m3)<<4)|rxb(v1, v2, 0, 0), 4607 uint8(op)) 4608 } 4609 4610 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) { 4611 *asm = append(*asm, 4612 uint8(op>>8), 4613 (uint8(v1)<<4)|(uint8(v2)&0xf), 4614 uint8(v3)<<4, 4615 uint8(m5)<<4, 4616 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4617 uint8(op)) 4618 } 4619 4620 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) { 4621 *asm = append(*asm, 4622 uint8(op>>8), 4623 (uint8(v1)<<4)|(uint8(v2)&0xf), 4624 uint8(v3)<<4, 4625 (uint8(m6)<<4)|(uint8(m5)&0xf), 4626 (uint8(m4)<<4)|rxb(v1, v2, v3, 0), 4627 uint8(op)) 4628 } 4629 4630 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) { 4631 *asm = append(*asm, 4632 uint8(op>>8), 4633 (uint8(v1)<<4)|(uint8(v2)&0xf), 4634 (uint8(v3)<<4)|(uint8(m5)&0xf), 4635 uint8(m6)<<4, 4636 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4637 uint8(op)) 4638 } 4639 4640 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) { 4641 *asm = append(*asm, 4642 uint8(op>>8), 4643 (uint8(v1)<<4)|(uint8(v2)&0xf), 4644 (uint8(v3)<<4)|(uint8(m6)&0xf), 4645 uint8(m5), 4646 (uint8(v4)<<4)|rxb(v1, v2, v3, v4), 4647 uint8(op)) 4648 } 4649 4650 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) { 4651 *asm = append(*asm, 4652 uint8(op>>8), 4653 (uint8(v1)<<4)|(uint8(r2)&0xf), 4654 uint8(r3)<<4, 4655 0, 4656 rxb(v1, 0, 0, 0), 4657 uint8(op)) 4658 } 4659 4660 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) { 4661 *asm = append(*asm, 4662 uint8(op>>8), 4663 uint8(v1)<<4, 4664 uint8(i2>>8), 4665 uint8(i2), 4666 (uint8(m3)<<4)|rxb(v1, 0, 0, 0), 4667 uint8(op)) 4668 } 4669 4670 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) { 4671 *asm = append(*asm, 4672 uint8(op>>8), 4673 uint8(v1)<<4, 4674 uint8(i2), 4675 uint8(i3), 4676 (uint8(m4)<<4)|rxb(v1, 0, 0, 0), 4677 uint8(op)) 4678 } 4679 4680 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) { 4681 *asm = append(*asm, 4682 uint8(op>>8), 4683 (uint8(v1)<<4)|(uint8(v3)&0xf), 4684 uint8(i2>>8), 4685 uint8(i2), 4686 (uint8(m4)<<4)|rxb(v1, v3, 0, 0), 4687 uint8(op)) 4688 } 4689 4690 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) { 4691 *asm = append(*asm, 4692 uint8(op>>8), 4693 (uint8(v1)<<4)|(uint8(v2)&0xf), 4694 uint8(v3)<<4, 4695 uint8(i4), 4696 (uint8(m5)<<4)|rxb(v1, v2, v3, 0), 4697 uint8(op)) 4698 } 4699 4700 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) { 4701 *asm = append(*asm, 4702 uint8(op>>8), 4703 (uint8(v1)<<4)|(uint8(v2)&0xf), 4704 uint8(i3>>4), 4705 (uint8(i3)<<4)|(uint8(m5)&0xf), 4706 (uint8(m4)<<4)|rxb(v1, v2, 0, 0), 4707 uint8(op)) 4708 }