github.com/f-secure-foundry/tamago@v0.0.0-20220307101044-d73fcdd7f11b/arm/cache.s (about)

     1  // ARM processor support
     2  // https://github.com/f-secure-foundry/tamago
     3  //
     4  // Copyright (c) F-Secure Corporation
     5  // https://foundry.f-secure.com
     6  //
     7  // Use of this source code is governed by the license
     8  // that can be found in the LICENSE file.
     9  
    10  // func read_actlr() uint32
    11  TEXT ·read_actlr(SB),$0-4
    12  	// Cortex™-A7 MPCore® Technical Reference Manual r0p5
    13  	//
    14  	// 4.3.31 Auxiliary Control Register
    15  
    16  	// Invalidate Entire Instruction Cache
    17  	MOVW	$0, R0
    18  	MCR	15, 0, R0, C7, C5, 0
    19  
    20  	MRC	15, 0, R0, C1, C0, 1
    21  	MOVW	R0, ret+0(FP)
    22  
    23  	RET
    24  
    25  // func write_actlr(aux uint32)
    26  TEXT ·write_actlr(SB),$0-4
    27  	// Cortex™-A7 MPCore® Technical Reference Manual r0p5
    28  	//
    29  	// 4.3.31 Auxiliary Control Register
    30  
    31  	// Invalidate Instruction Cache
    32  	MOVW	$0, R1
    33  	MCR	15, 0, R1, C7, C5, 0
    34  
    35  	MOVW	aux+0(FP), R0
    36  	MCR	15, 0, R0, C1, C0, 1
    37  
    38  	RET
    39  
    40  // func cache_disable()
    41  TEXT ·cache_disable(SB),$0
    42  	MRC	15, 0, R1, C1, C0, 0
    43  	BIC	$1<<12, R1			// Disable I-cache
    44  	BIC	$1<<2, R1			// Disable D-cache
    45  	MCR	15, 0, R1, C1, C0, 0
    46  	RET
    47  
    48  // func cache_enable()
    49  TEXT ·cache_enable(SB),$0
    50  	MRC	15, 0, R1, C1, C0, 0
    51  	ORR	$1<<12, R1			// Enable I-cache
    52  	ORR	$1<<2, R1			// Enable D-cache
    53  	MCR	15, 0, R1, C1, C0, 0
    54  	RET
    55  
    56  // Taken from Linux /arch/arm/mm/cache-v7.S
    57  // Using R8 instead of R10 as the latter is g in go runtime.
    58  //
    59  // func cache_flush_data()
    60  TEXT ·cache_flush_data(SB),$0
    61  	WORD	$0xf57ff05f			// DMB SY
    62  	MRC	15, 1, R0, C0, C0, 1		// read CLIDR
    63  	MOVW	R0>>23, R3			// move LoC into position
    64  	AND.S	$7<<1, R3, R3			// extract LoC*2 from clidr
    65  	BEQ	finished			// if loc is 0, then no need to clean
    66  start_flush_levels:
    67  	MOVW	$0x0, R8			// start clean at cache level 0
    68  flush_levels:
    69  	ADD	R8>>1, R8, R2			// work out 3x current cache level
    70  	MOVW	R0>>R2, R1			// extract cache type bits from clidr
    71  	AND	$0x7, R1			// mask of the bits for current cache only
    72  	CMP	$0x2, R1			// see what cache we have at this level
    73  	BLT	skip				// skip if no cache, or just i-cache
    74  	MCR	15, 2, R8, C0, C0, 0		// select current cache level in cssr
    75  	WORD	$0xf57ff06f			// isb to sych the new cssr&csidr
    76  	MRC	15, 1, R1, C0, C0, 0		// read the new csidr
    77  	AND	$0x7, R1, R2			// extract the length of the cache lines
    78  	ADD	$0x4, R2			// add 4 (line length offset)
    79  	MOVW	$0x3ff, R4
    80  	AND.S	R1>>3, R4, R4			// find maximum number on the way size
    81  	CLZ	R4, R5				// find bit position of way size increment
    82  	MOVW	$0x7fff, R7
    83  	AND.S	R1>>13, R7, R7			// extract max number of the index size
    84  loop1:
    85  	MOVW	R7, R9				// create working copy of max index
    86  loop2:
    87  	ORR	R4<<R5, R8, R11			// factor way and cache number into r11
    88  	ORR	R9<<R2, R11, R11		// factor way and cache number into r11
    89  	MCR	15, 0, R11, C7, C14, 2		// clean & invalidate by set/way
    90  	SUB.S	$1, R9, R9			// decrement the index
    91  	BGE	loop2
    92  	SUB.S	$1, R4, R4			// decrement the way
    93  	BGE	loop1
    94  skip:
    95  	ADD	$2, R8				// increment cache number
    96  	CMP	R8, R3
    97  	//WORD	$0xf57ff04f			// DSB SY, CONFIG_ARM_ERRATA_814220, for Cortex-A7, not used in U-Boot
    98  	BGT	flush_levels
    99  finished:
   100  	MOVW	$0, R8				// switch back to cache level 0
   101  	MCR	15, 2, R8, C0, C0, 0		// select current cache level in cssr
   102  	WORD	$0xf57ff04e			// DSB ST
   103  	WORD	$0xf57ff06f			// ISB SY
   104  	RET
   105  
   106  // Taken from Linux /arch/arm/mm/cache-v7.S
   107  // Using R8 instead of R10 as the latter is g in go runtime.
   108  //
   109  // func cache_flush_instruction()
   110  TEXT ·cache_flush_instruction(SB),$0
   111  	MOVW	$0, R0
   112  	MCR	15, 0, R0, C7, C5, 0
   113  	RET