github.com/filosottile/go@v0.0.0-20170906193555-dbed9972d994/src/cmd/compile/internal/ssa/gen/PPC64.rules (about) 1 // Copyright 2016 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Lowering arithmetic 6 (Add64 x y) -> (ADD x y) 7 (AddPtr x y) -> (ADD x y) 8 (Add32 x y) -> (ADD x y) 9 (Add16 x y) -> (ADD x y) 10 (Add8 x y) -> (ADD x y) 11 (Add64F x y) -> (FADD x y) 12 (Add32F x y) -> (FADDS x y) 13 14 (Sub64 x y) -> (SUB x y) 15 (SubPtr x y) -> (SUB x y) 16 (Sub32 x y) -> (SUB x y) 17 (Sub16 x y) -> (SUB x y) 18 (Sub8 x y) -> (SUB x y) 19 (Sub32F x y) -> (FSUBS x y) 20 (Sub64F x y) -> (FSUB x y) 21 22 (Mod16 x y) -> (Mod32 (SignExt16to32 x) (SignExt16to32 y)) 23 (Mod16u x y) -> (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y)) 24 (Mod8 x y) -> (Mod32 (SignExt8to32 x) (SignExt8to32 y)) 25 (Mod8u x y) -> (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y)) 26 (Mod64 x y) -> (SUB x (MULLD y (DIVD x y))) 27 (Mod64u x y) -> (SUB x (MULLD y (DIVDU x y))) 28 (Mod32 x y) -> (SUB x (MULLW y (DIVW x y))) 29 (Mod32u x y) -> (SUB x (MULLW y (DIVWU x y))) 30 31 // (x + y) / 2 with x>=y -> (x - y) / 2 + y 32 (Avg64u <t> x y) -> (ADD (SRDconst <t> (SUB <t> x y) [1]) y) 33 34 (Mul64 x y) -> (MULLD x y) 35 (Mul32 x y) -> (MULLW x y) 36 (Mul16 x y) -> (MULLW x y) 37 (Mul8 x y) -> (MULLW x y) 38 39 (Div64 x y) -> (DIVD x y) 40 (Div64u x y) -> (DIVDU x y) 41 (Div32 x y) -> (DIVW x y) 42 (Div32u x y) -> (DIVWU x y) 43 (Div16 x y) -> (DIVW (SignExt16to32 x) (SignExt16to32 y)) 44 (Div16u x y) -> (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y)) 45 (Div8 x y) -> (DIVW (SignExt8to32 x) (SignExt8to32 y)) 46 (Div8u x y) -> (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y)) 47 48 (Hmul64 x y) -> (MULHD x y) 49 (Hmul64u x y) -> (MULHDU x y) 50 (Hmul32 x y) -> (MULHW x y) 51 (Hmul32u x y) -> (MULHWU x y) 52 53 (Mul32F x y) -> (FMULS x y) 54 (Mul64F x y) -> (FMUL x y) 55 56 (Div32F x y) -> (FDIVS x y) 57 (Div64F x y) -> (FDIV x y) 58 59 // Lowering float <-> int 60 (Cvt32to32F x) -> (FRSP (FCFID (Xi2f64 (SignExt32to64 x)))) 61 (Cvt32to64F x) -> (FCFID (Xi2f64 (SignExt32to64 x))) 62 (Cvt64to32F x) -> (FRSP (FCFID (Xi2f64 x))) 63 (Cvt64to64F x) -> (FCFID (Xi2f64 x)) 64 65 (Cvt32Fto32 x) -> (Xf2i64 (FCTIWZ x)) 66 (Cvt32Fto64 x) -> (Xf2i64 (FCTIDZ x)) 67 (Cvt64Fto32 x) -> (Xf2i64 (FCTIWZ x)) 68 (Cvt64Fto64 x) -> (Xf2i64 (FCTIDZ x)) 69 70 (Cvt32Fto64F x) -> x // Note x will have the wrong type for patterns dependent on Float32/Float64 71 (Cvt64Fto32F x) -> (FRSP x) 72 73 (Round32F x) -> (LoweredRound32F x) 74 (Round64F x) -> (LoweredRound64F x) 75 76 (Sqrt x) -> (FSQRT x) 77 (Floor x) -> (FFLOOR x) 78 (Ceil x) -> (FCEIL x) 79 (Trunc x) -> (FTRUNC x) 80 81 // Lowering constants 82 (Const8 [val]) -> (MOVDconst [val]) 83 (Const16 [val]) -> (MOVDconst [val]) 84 (Const32 [val]) -> (MOVDconst [val]) 85 (Const64 [val]) -> (MOVDconst [val]) 86 (Const32F [val]) -> (FMOVSconst [val]) 87 (Const64F [val]) -> (FMOVDconst [val]) 88 (ConstNil) -> (MOVDconst [0]) 89 (ConstBool [b]) -> (MOVDconst [b]) 90 91 // Rotate generation 92 (ADD (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (ROTLconst [c] x) 93 ( OR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (ROTLconst [c] x) 94 (XOR (SLDconst x [c]) (SRDconst x [d])) && d == 64-c -> (ROTLconst [c] x) 95 96 (ADD (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (ROTLWconst [c] x) 97 ( OR (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (ROTLWconst [c] x) 98 (XOR (SLWconst x [c]) (SRWconst x [d])) && d == 32-c -> (ROTLWconst [c] x) 99 100 (Lsh64x64 x (Const64 [c])) && uint64(c) < 64 -> (SLDconst x [c]) 101 (Rsh64x64 x (Const64 [c])) && uint64(c) < 64 -> (SRADconst x [c]) 102 (Rsh64Ux64 x (Const64 [c])) && uint64(c) < 64 -> (SRDconst x [c]) 103 (Lsh32x64 x (Const64 [c])) && uint64(c) < 32 -> (SLWconst x [c]) 104 (Rsh32x64 x (Const64 [c])) && uint64(c) < 32 -> (SRAWconst x [c]) 105 (Rsh32Ux64 x (Const64 [c])) && uint64(c) < 32 -> (SRWconst x [c]) 106 (Lsh16x64 x (Const64 [c])) && uint64(c) < 16 -> (SLWconst x [c]) 107 (Rsh16x64 x (Const64 [c])) && uint64(c) < 16 -> (SRAWconst (SignExt16to32 x) [c]) 108 (Rsh16Ux64 x (Const64 [c])) && uint64(c) < 16 -> (SRWconst (ZeroExt16to32 x) [c]) 109 (Lsh8x64 x (Const64 [c])) && uint64(c) < 8 -> (SLWconst x [c]) 110 (Rsh8x64 x (Const64 [c])) && uint64(c) < 8 -> (SRAWconst (SignExt8to32 x) [c]) 111 (Rsh8Ux64 x (Const64 [c])) && uint64(c) < 8 -> (SRWconst (ZeroExt8to32 x) [c]) 112 113 (Lsh64x32 x (Const64 [c])) && uint32(c) < 64 -> (SLDconst x [c]) 114 (Rsh64x32 x (Const64 [c])) && uint32(c) < 64 -> (SRADconst x [c]) 115 (Rsh64Ux32 x (Const64 [c])) && uint32(c) < 64 -> (SRDconst x [c]) 116 (Lsh32x32 x (Const64 [c])) && uint32(c) < 32 -> (SLWconst x [c]) 117 (Rsh32x32 x (Const64 [c])) && uint32(c) < 32 -> (SRAWconst x [c]) 118 (Rsh32Ux32 x (Const64 [c])) && uint32(c) < 32 -> (SRWconst x [c]) 119 (Lsh16x32 x (Const64 [c])) && uint32(c) < 16 -> (SLWconst x [c]) 120 (Rsh16x32 x (Const64 [c])) && uint32(c) < 16 -> (SRAWconst (SignExt16to32 x) [c]) 121 (Rsh16Ux32 x (Const64 [c])) && uint32(c) < 16 -> (SRWconst (ZeroExt16to32 x) [c]) 122 (Lsh8x32 x (Const64 [c])) && uint32(c) < 8 -> (SLWconst x [c]) 123 (Rsh8x32 x (Const64 [c])) && uint32(c) < 8 -> (SRAWconst (SignExt8to32 x) [c]) 124 (Rsh8Ux32 x (Const64 [c])) && uint32(c) < 8 -> (SRWconst (ZeroExt8to32 x) [c]) 125 126 // large constant shifts 127 (Lsh64x64 _ (Const64 [c])) && uint64(c) >= 64 -> (MOVDconst [0]) 128 (Rsh64Ux64 _ (Const64 [c])) && uint64(c) >= 64 -> (MOVDconst [0]) 129 (Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 -> (MOVDconst [0]) 130 (Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 -> (MOVDconst [0]) 131 (Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 -> (MOVDconst [0]) 132 (Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 -> (MOVDconst [0]) 133 (Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 -> (MOVDconst [0]) 134 (Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 -> (MOVDconst [0]) 135 136 // large constant signed right shift, we leave the sign bit 137 (Rsh64x64 x (Const64 [c])) && uint64(c) >= 64 -> (SRADconst x [63]) 138 (Rsh32x64 x (Const64 [c])) && uint64(c) >= 32 -> (SRAWconst x [63]) 139 (Rsh16x64 x (Const64 [c])) && uint64(c) >= 16 -> (SRAWconst (SignExt16to32 x) [63]) 140 (Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 -> (SRAWconst (SignExt8to32 x) [63]) 141 142 // constant shifts 143 (Lsh64x64 x (MOVDconst [c])) && uint64(c) < 64 -> (SLDconst x [c]) 144 (Rsh64x64 x (MOVDconst [c])) && uint64(c) < 64 -> (SRADconst x [c]) 145 (Rsh64Ux64 x (MOVDconst [c])) && uint64(c) < 64 -> (SRDconst x [c]) 146 (Lsh32x64 x (MOVDconst [c])) && uint64(c) < 32 -> (SLWconst x [c]) 147 (Rsh32x64 x (MOVDconst [c])) && uint64(c) < 32 -> (SRAWconst x [c]) 148 (Rsh32Ux64 x (MOVDconst [c])) && uint64(c) < 32 -> (SRWconst x [c]) 149 (Lsh16x64 x (MOVDconst [c])) && uint64(c) < 16 -> (SLWconst x [c]) 150 (Rsh16x64 x (MOVDconst [c])) && uint64(c) < 16 -> (SRAWconst (SignExt16to32 x) [c]) 151 (Rsh16Ux64 x (MOVDconst [c])) && uint64(c) < 16 -> (SRWconst (ZeroExt16to32 x) [c]) 152 (Lsh8x64 x (MOVDconst [c])) && uint64(c) < 8 -> (SLWconst x [c]) 153 (Rsh8x64 x (MOVDconst [c])) && uint64(c) < 8 -> (SRAWconst (SignExt8to32 x) [c]) 154 (Rsh8Ux64 x (MOVDconst [c])) && uint64(c) < 8 -> (SRWconst (ZeroExt8to32 x) [c]) 155 156 (Lsh64x32 x (MOVDconst [c])) && uint32(c) < 64 -> (SLDconst x [c]) 157 (Rsh64x32 x (MOVDconst [c])) && uint32(c) < 64 -> (SRADconst x [c]) 158 (Rsh64Ux32 x (MOVDconst [c])) && uint32(c) < 64 -> (SRDconst x [c]) 159 (Lsh32x32 x (MOVDconst [c])) && uint32(c) < 32 -> (SLWconst x [c]) 160 (Rsh32x32 x (MOVDconst [c])) && uint32(c) < 32 -> (SRAWconst x [c]) 161 (Rsh32Ux32 x (MOVDconst [c])) && uint32(c) < 32 -> (SRWconst x [c]) 162 (Lsh16x32 x (MOVDconst [c])) && uint32(c) < 16 -> (SLWconst x [c]) 163 (Rsh16x32 x (MOVDconst [c])) && uint32(c) < 16 -> (SRAWconst (SignExt16to32 x) [c]) 164 (Rsh16Ux32 x (MOVDconst [c])) && uint32(c) < 16 -> (SRWconst (ZeroExt16to32 x) [c]) 165 (Lsh8x32 x (MOVDconst [c])) && uint32(c) < 8 -> (SLWconst x [c]) 166 (Rsh8x32 x (MOVDconst [c])) && uint32(c) < 8 -> (SRAWconst (SignExt8to32 x) [c]) 167 (Rsh8Ux32 x (MOVDconst [c])) && uint32(c) < 8 -> (SRWconst (ZeroExt8to32 x) [c]) 168 169 (Rsh64x64 x y) -> (SRAD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] y)))) 170 (Rsh64Ux64 x y) -> (SRD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] y)))) 171 (Lsh64x64 x y) -> (SLD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] y)))) 172 173 (Rsh32x64 x y) -> (SRAW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] y)))) 174 (Rsh32Ux64 x y) -> (SRW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] y)))) 175 (Lsh32x64 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] y)))) 176 177 (Rsh16x64 x y) -> (SRAW (SignExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] y)))) 178 (Rsh16Ux64 x y) -> (SRW (ZeroExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] y)))) 179 (Lsh16x64 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] y)))) 180 181 (Rsh8x64 x y) -> (SRAW (SignExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] y)))) 182 (Rsh8Ux64 x y) -> (SRW (ZeroExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] y)))) 183 (Lsh8x64 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] y)))) 184 185 186 (Rsh64x32 x y) -> (SRAD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) 187 (Rsh64Ux32 x y) -> (SRD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) 188 (Lsh64x32 x y) -> (SLD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt32to64 y))))) 189 190 (Rsh32x32 x y) -> (SRAW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) 191 (Rsh32Ux32 x y) -> (SRW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) 192 (Lsh32x32 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt32to64 y))))) 193 194 (Rsh16x32 x y) -> (SRAW (SignExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) 195 (Rsh16Ux32 x y) -> (SRW (ZeroExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) 196 (Lsh16x32 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt32to64 y))))) 197 198 (Rsh8x32 x y) -> (SRAW (SignExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) 199 (Rsh8Ux32 x y) -> (SRW (ZeroExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) 200 (Lsh8x32 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt32to64 y))))) 201 202 203 (Rsh64x16 x y) -> (SRAD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) 204 (Rsh64Ux16 x y) -> (SRD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) 205 (Lsh64x16 x y) -> (SLD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt16to64 y))))) 206 207 (Rsh32x16 x y) -> (SRAW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) 208 (Rsh32Ux16 x y) -> (SRW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) 209 (Lsh32x16 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt16to64 y))))) 210 211 (Rsh16x16 x y) -> (SRAW (SignExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) 212 (Rsh16Ux16 x y) -> (SRW (ZeroExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) 213 (Lsh16x16 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt16to64 y))))) 214 215 (Rsh8x16 x y) -> (SRAW (SignExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) 216 (Rsh8Ux16 x y) -> (SRW (ZeroExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) 217 (Lsh8x16 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt16to64 y))))) 218 219 220 (Rsh64x8 x y) -> (SRAD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) 221 (Rsh64Ux8 x y) -> (SRD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) 222 (Lsh64x8 x y) -> (SLD x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-64] (ZeroExt8to64 y))))) 223 224 (Rsh32x8 x y) -> (SRAW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) 225 (Rsh32Ux8 x y) -> (SRW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) 226 (Lsh32x8 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-32] (ZeroExt8to64 y))))) 227 228 (Rsh16x8 x y) -> (SRAW (SignExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) 229 (Rsh16Ux8 x y) -> (SRW (ZeroExt16to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) 230 (Lsh16x8 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-16] (ZeroExt8to64 y))))) 231 232 (Rsh8x8 x y) -> (SRAW (SignExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) 233 (Rsh8Ux8 x y) -> (SRW (ZeroExt8to32 x) (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) 234 (Lsh8x8 x y) -> (SLW x (ORN y <typ.Int64> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y))))) 235 236 // Cleaning up shift ops when input is masked 237 (MaskIfNotCarry (ADDconstForCarry [c] (ANDconst [d] _))) && c < 0 && d > 0 && c + d < 0 -> (MOVDconst [-1]) 238 (ORN x (MOVDconst [-1])) -> x 239 240 // Potentially useful optimizing rewrites. 241 // (ADDconstForCarry [k] c), k < 0 && (c < 0 || k+c >= 0) -> CarrySet 242 // (ADDconstForCarry [k] c), K < 0 && (c >= 0 && k+c < 0) -> CarryClear 243 // (MaskIfNotCarry CarrySet) -> 0 244 // (MaskIfNotCarry CarrySet) -> -1 245 246 (Addr {sym} base) -> (MOVDaddr {sym} base) 247 // (Addr {sym} base) -> (ADDconst {sym} base) 248 (OffPtr [off] ptr) -> (ADD (MOVDconst <typ.Int64> [off]) ptr) 249 250 (Ctz64 x) -> (POPCNTD (ANDN <typ.Int64> (ADDconst <typ.Int64> [-1] x) x)) 251 (Ctz32 x) -> (POPCNTW (MOVWZreg (ANDN <typ.Int> (ADDconst <typ.Int> [-1] x) x))) 252 253 (BitLen64 x) -> (SUB (MOVDconst [64]) (CNTLZD <typ.Int> x)) 254 (BitLen32 x) -> (SUB (MOVDconst [32]) (CNTLZW <typ.Int> x)) 255 256 (PopCount64 x) -> (POPCNTD x) 257 (PopCount32 x) -> (POPCNTW (MOVWZreg x)) 258 (PopCount16 x) -> (POPCNTW (MOVHZreg x)) 259 (PopCount8 x) -> (POPCNTB (MOVBreg x)) 260 261 (And64 x y) -> (AND x y) 262 (And32 x y) -> (AND x y) 263 (And16 x y) -> (AND x y) 264 (And8 x y) -> (AND x y) 265 266 (Or64 x y) -> (OR x y) 267 (Or32 x y) -> (OR x y) 268 (Or16 x y) -> (OR x y) 269 (Or8 x y) -> (OR x y) 270 271 (Xor64 x y) -> (XOR x y) 272 (Xor32 x y) -> (XOR x y) 273 (Xor16 x y) -> (XOR x y) 274 (Xor8 x y) -> (XOR x y) 275 276 (Neg64F x) -> (FNEG x) 277 (Neg32F x) -> (FNEG x) 278 (Neg64 x) -> (NEG x) 279 (Neg32 x) -> (NEG x) 280 (Neg16 x) -> (NEG x) 281 (Neg8 x) -> (NEG x) 282 283 (Com64 x) -> (NOR x x) 284 (Com32 x) -> (NOR x x) 285 (Com16 x) -> (NOR x x) 286 (Com8 x) -> (NOR x x) 287 288 // Lowering boolean ops 289 (AndB x y) -> (AND x y) 290 (OrB x y) -> (OR x y) 291 (Not x) -> (XORconst [1] x) 292 293 // Use ANDN for AND x NOT y 294 (AND x (NOR y y)) -> (ANDN x y) 295 296 // Lowering comparisons 297 (EqB x y) -> (ANDconst [1] (EQV x y)) 298 // Sign extension dependence on operand sign sets up for sign/zero-extension elision later 299 (Eq8 x y) && isSigned(x.Type) && isSigned(y.Type) -> (Equal (CMPW (SignExt8to32 x) (SignExt8to32 y))) 300 (Eq16 x y) && isSigned(x.Type) && isSigned(y.Type) -> (Equal (CMPW (SignExt16to32 x) (SignExt16to32 y))) 301 (Eq8 x y) -> (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 302 (Eq16 x y) -> (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 303 (Eq32 x y) -> (Equal (CMPW x y)) 304 (Eq64 x y) -> (Equal (CMP x y)) 305 (Eq32F x y) -> (Equal (FCMPU x y)) 306 (Eq64F x y) -> (Equal (FCMPU x y)) 307 (EqPtr x y) -> (Equal (CMP x y)) 308 309 (NeqB x y) -> (XOR x y) 310 // Like Eq8 and Eq16, prefer sign extension likely to enable later elision. 311 (Neq8 x y) && isSigned(x.Type) && isSigned(y.Type) -> (NotEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) 312 (Neq16 x y) && isSigned(x.Type) && isSigned(y.Type) -> (NotEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) 313 (Neq8 x y) -> (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y))) 314 (Neq16 x y) -> (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y))) 315 (Neq32 x y) -> (NotEqual (CMPW x y)) 316 (Neq64 x y) -> (NotEqual (CMP x y)) 317 (Neq32F x y) -> (NotEqual (FCMPU x y)) 318 (Neq64F x y) -> (NotEqual (FCMPU x y)) 319 (NeqPtr x y) -> (NotEqual (CMP x y)) 320 321 (Less8 x y) -> (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) 322 (Less16 x y) -> (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) 323 (Less32 x y) -> (LessThan (CMPW x y)) 324 (Less64 x y) -> (LessThan (CMP x y)) 325 (Less32F x y) -> (FLessThan (FCMPU x y)) 326 (Less64F x y) -> (FLessThan (FCMPU x y)) 327 328 (Less8U x y) -> (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) 329 (Less16U x y) -> (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) 330 (Less32U x y) -> (LessThan (CMPWU x y)) 331 (Less64U x y) -> (LessThan (CMPU x y)) 332 333 (Leq8 x y) -> (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) 334 (Leq16 x y) -> (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) 335 (Leq32 x y) -> (LessEqual (CMPW x y)) 336 (Leq64 x y) -> (LessEqual (CMP x y)) 337 (Leq32F x y) -> (FLessEqual (FCMPU x y)) 338 (Leq64F x y) -> (FLessEqual (FCMPU x y)) 339 340 (Leq8U x y) -> (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) 341 (Leq16U x y) -> (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) 342 (Leq32U x y) -> (LessEqual (CMPWU x y)) 343 (Leq64U x y) -> (LessEqual (CMPU x y)) 344 345 (Greater8 x y) -> (GreaterThan (CMPW (SignExt8to32 x) (SignExt8to32 y))) 346 (Greater16 x y) -> (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y))) 347 (Greater32 x y) -> (GreaterThan (CMPW x y)) 348 (Greater64 x y) -> (GreaterThan (CMP x y)) 349 (Greater32F x y) -> (FGreaterThan (FCMPU x y)) 350 (Greater64F x y) -> (FGreaterThan (FCMPU x y)) 351 352 (Greater8U x y) -> (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) 353 (Greater16U x y) -> (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) 354 (Greater32U x y) -> (GreaterThan (CMPWU x y)) 355 (Greater64U x y) -> (GreaterThan (CMPU x y)) 356 357 (Geq8 x y) -> (GreaterEqual (CMPW (SignExt8to32 x) (SignExt8to32 y))) 358 (Geq16 x y) -> (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y))) 359 (Geq32 x y) -> (GreaterEqual (CMPW x y)) 360 (Geq64 x y) -> (GreaterEqual (CMP x y)) 361 (Geq32F x y) -> (FGreaterEqual (FCMPU x y)) 362 (Geq64F x y) -> (FGreaterEqual (FCMPU x y)) 363 364 (Geq8U x y) -> (GreaterEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y))) 365 (Geq16U x y) -> (GreaterEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y))) 366 (Geq32U x y) -> (GreaterEqual (CMPWU x y)) 367 (Geq64U x y) -> (GreaterEqual (CMPU x y)) 368 369 // Absorb pseudo-ops into blocks. 370 (If (Equal cc) yes no) -> (EQ cc yes no) 371 (If (NotEqual cc) yes no) -> (NE cc yes no) 372 (If (LessThan cc) yes no) -> (LT cc yes no) 373 (If (LessEqual cc) yes no) -> (LE cc yes no) 374 (If (GreaterThan cc) yes no) -> (GT cc yes no) 375 (If (GreaterEqual cc) yes no) -> (GE cc yes no) 376 (If (FLessThan cc) yes no) -> (FLT cc yes no) 377 (If (FLessEqual cc) yes no) -> (FLE cc yes no) 378 (If (FGreaterThan cc) yes no) -> (FGT cc yes no) 379 (If (FGreaterEqual cc) yes no) -> (FGE cc yes no) 380 381 (If cond yes no) -> (NE (CMPWconst [0] cond) yes no) 382 383 // Absorb boolean tests into block 384 (NE (CMPWconst [0] (Equal cc)) yes no) -> (EQ cc yes no) 385 (NE (CMPWconst [0] (NotEqual cc)) yes no) -> (NE cc yes no) 386 (NE (CMPWconst [0] (LessThan cc)) yes no) -> (LT cc yes no) 387 (NE (CMPWconst [0] (LessEqual cc)) yes no) -> (LE cc yes no) 388 (NE (CMPWconst [0] (GreaterThan cc)) yes no) -> (GT cc yes no) 389 (NE (CMPWconst [0] (GreaterEqual cc)) yes no) -> (GE cc yes no) 390 (NE (CMPWconst [0] (FLessThan cc)) yes no) -> (FLT cc yes no) 391 (NE (CMPWconst [0] (FLessEqual cc)) yes no) -> (FLE cc yes no) 392 (NE (CMPWconst [0] (FGreaterThan cc)) yes no) -> (FGT cc yes no) 393 (NE (CMPWconst [0] (FGreaterEqual cc)) yes no) -> (FGE cc yes no) 394 395 // Elide compares of bit tests // TODO need to make both CC and result of ANDCC available. 396 (EQ (CMPconst [0] (ANDconst [c] x)) yes no) -> (EQ (ANDCCconst [c] x) yes no) 397 (NE (CMPconst [0] (ANDconst [c] x)) yes no) -> (NE (ANDCCconst [c] x) yes no) 398 (EQ (CMPWconst [0] (ANDconst [c] x)) yes no) -> (EQ (ANDCCconst [c] x) yes no) 399 (NE (CMPWconst [0] (ANDconst [c] x)) yes no) -> (NE (ANDCCconst [c] x) yes no) 400 401 // absorb flag constants into branches 402 (EQ (FlagEQ) yes no) -> (First nil yes no) 403 (EQ (FlagLT) yes no) -> (First nil no yes) 404 (EQ (FlagGT) yes no) -> (First nil no yes) 405 406 (NE (FlagEQ) yes no) -> (First nil no yes) 407 (NE (FlagLT) yes no) -> (First nil yes no) 408 (NE (FlagGT) yes no) -> (First nil yes no) 409 410 (LT (FlagEQ) yes no) -> (First nil no yes) 411 (LT (FlagLT) yes no) -> (First nil yes no) 412 (LT (FlagGT) yes no) -> (First nil no yes) 413 414 (LE (FlagEQ) yes no) -> (First nil yes no) 415 (LE (FlagLT) yes no) -> (First nil yes no) 416 (LE (FlagGT) yes no) -> (First nil no yes) 417 418 (GT (FlagEQ) yes no) -> (First nil no yes) 419 (GT (FlagLT) yes no) -> (First nil no yes) 420 (GT (FlagGT) yes no) -> (First nil yes no) 421 422 (GE (FlagEQ) yes no) -> (First nil yes no) 423 (GE (FlagLT) yes no) -> (First nil no yes) 424 (GE (FlagGT) yes no) -> (First nil yes no) 425 426 // absorb InvertFlags into branches 427 (LT (InvertFlags cmp) yes no) -> (GT cmp yes no) 428 (GT (InvertFlags cmp) yes no) -> (LT cmp yes no) 429 (LE (InvertFlags cmp) yes no) -> (GE cmp yes no) 430 (GE (InvertFlags cmp) yes no) -> (LE cmp yes no) 431 (EQ (InvertFlags cmp) yes no) -> (EQ cmp yes no) 432 (NE (InvertFlags cmp) yes no) -> (NE cmp yes no) 433 434 // constant comparisons 435 (CMPWconst (MOVDconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 436 (CMPWconst (MOVDconst [x]) [y]) && int32(x)<int32(y) -> (FlagLT) 437 (CMPWconst (MOVDconst [x]) [y]) && int32(x)>int32(y) -> (FlagGT) 438 439 (CMPconst (MOVDconst [x]) [y]) && int64(x)==int64(y) -> (FlagEQ) 440 (CMPconst (MOVDconst [x]) [y]) && int64(x)<int64(y) -> (FlagLT) 441 (CMPconst (MOVDconst [x]) [y]) && int64(x)>int64(y) -> (FlagGT) 442 443 (CMPWUconst (MOVDconst [x]) [y]) && int32(x)==int32(y) -> (FlagEQ) 444 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)<uint32(y) -> (FlagLT) 445 (CMPWUconst (MOVDconst [x]) [y]) && uint32(x)>uint32(y) -> (FlagGT) 446 447 (CMPUconst (MOVDconst [x]) [y]) && int64(x)==int64(y) -> (FlagEQ) 448 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)<uint64(y) -> (FlagLT) 449 (CMPUconst (MOVDconst [x]) [y]) && uint64(x)>uint64(y) -> (FlagGT) 450 451 // other known comparisons 452 //(CMPconst (MOVBUreg _) [c]) && 0xff < c -> (FlagLT) 453 //(CMPconst (MOVHUreg _) [c]) && 0xffff < c -> (FlagLT) 454 //(CMPconst (ANDconst _ [m]) [n]) && 0 <= int32(m) && int32(m) < int32(n) -> (FlagLT) 455 //(CMPconst (SRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint32(32-c)) <= uint32(n) -> (FlagLT) 456 457 // absorb flag constants into boolean values 458 (Equal (FlagEQ)) -> (MOVDconst [1]) 459 (Equal (FlagLT)) -> (MOVDconst [0]) 460 (Equal (FlagGT)) -> (MOVDconst [0]) 461 462 (NotEqual (FlagEQ)) -> (MOVDconst [0]) 463 (NotEqual (FlagLT)) -> (MOVDconst [1]) 464 (NotEqual (FlagGT)) -> (MOVDconst [1]) 465 466 (LessThan (FlagEQ)) -> (MOVDconst [0]) 467 (LessThan (FlagLT)) -> (MOVDconst [1]) 468 (LessThan (FlagGT)) -> (MOVDconst [0]) 469 470 (LessEqual (FlagEQ)) -> (MOVDconst [1]) 471 (LessEqual (FlagLT)) -> (MOVDconst [1]) 472 (LessEqual (FlagGT)) -> (MOVDconst [0]) 473 474 (GreaterThan (FlagEQ)) -> (MOVDconst [0]) 475 (GreaterThan (FlagLT)) -> (MOVDconst [0]) 476 (GreaterThan (FlagGT)) -> (MOVDconst [1]) 477 478 (GreaterEqual (FlagEQ)) -> (MOVDconst [1]) 479 (GreaterEqual (FlagLT)) -> (MOVDconst [0]) 480 (GreaterEqual (FlagGT)) -> (MOVDconst [1]) 481 482 // absorb InvertFlags into boolean values 483 (Equal (InvertFlags x)) -> (Equal x) 484 (NotEqual (InvertFlags x)) -> (NotEqual x) 485 (LessThan (InvertFlags x)) -> (GreaterThan x) 486 (GreaterThan (InvertFlags x)) -> (LessThan x) 487 (LessEqual (InvertFlags x)) -> (GreaterEqual x) 488 (GreaterEqual (InvertFlags x)) -> (LessEqual x) 489 490 // Lowering loads 491 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVDload ptr mem) 492 (Load <t> ptr mem) && is32BitInt(t) && isSigned(t) -> (MOVWload ptr mem) 493 (Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) -> (MOVWZload ptr mem) 494 (Load <t> ptr mem) && is16BitInt(t) && isSigned(t) -> (MOVHload ptr mem) 495 (Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem) 496 (Load <t> ptr mem) && t.IsBoolean() -> (MOVBZload ptr mem) 497 (Load <t> ptr mem) && is8BitInt(t) && isSigned(t) -> (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load. 498 (Load <t> ptr mem) && is8BitInt(t) && !isSigned(t) -> (MOVBZload ptr mem) 499 500 (Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem) 501 (Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem) 502 503 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem) 504 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && is32BitFloat(val.Type) -> (FMOVDstore ptr val mem) // glitch from (Cvt32Fto64F x) -> x -- type is wrong 505 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem) 506 (Store {t} ptr val mem) && t.(*types.Type).Size() == 8 && (is64BitInt(val.Type) || isPtr(val.Type)) -> (MOVDstore ptr val mem) 507 (Store {t} ptr val mem) && t.(*types.Type).Size() == 4 && is32BitInt(val.Type) -> (MOVWstore ptr val mem) 508 (Store {t} ptr val mem) && t.(*types.Type).Size() == 2 -> (MOVHstore ptr val mem) 509 (Store {t} ptr val mem) && t.(*types.Type).Size() == 1 -> (MOVBstore ptr val mem) 510 511 // Using Zero instead of LoweredZero allows the 512 // target address to be folded where possible. 513 (Zero [0] _ mem) -> mem 514 (Zero [1] destptr mem) -> (MOVBstorezero destptr mem) 515 (Zero [2] destptr mem) -> 516 (MOVHstorezero destptr mem) 517 (Zero [3] destptr mem) -> 518 (MOVBstorezero [2] destptr 519 (MOVHstorezero destptr mem)) 520 (Zero [4] destptr mem) -> 521 (MOVWstorezero destptr mem) 522 (Zero [5] destptr mem) -> 523 (MOVBstorezero [4] destptr 524 (MOVWstorezero destptr mem)) 525 (Zero [6] destptr mem) -> 526 (MOVHstorezero [4] destptr 527 (MOVWstorezero destptr mem)) 528 (Zero [7] destptr mem) -> 529 (MOVBstorezero [6] destptr 530 (MOVHstorezero [4] destptr 531 (MOVWstorezero destptr mem))) 532 (Zero [8] destptr mem) -> 533 (MOVDstorezero destptr mem) 534 535 // Zero small numbers of words directly. 536 (Zero [12] destptr mem) -> 537 (MOVWstorezero [8] destptr 538 (MOVDstorezero [0] destptr mem)) 539 (Zero [16] destptr mem) -> 540 (MOVDstorezero [8] destptr 541 (MOVDstorezero [0] destptr mem)) 542 (Zero [24] destptr mem) -> 543 (MOVDstorezero [16] destptr 544 (MOVDstorezero [8] destptr 545 (MOVDstorezero [0] destptr mem))) 546 (Zero [32] destptr mem) -> 547 (MOVDstorezero [24] destptr 548 (MOVDstorezero [16] destptr 549 (MOVDstorezero [8] destptr 550 (MOVDstorezero [0] destptr mem)))) 551 552 (Zero [40] destptr mem) -> 553 (MOVDstorezero [32] destptr 554 (MOVDstorezero [24] destptr 555 (MOVDstorezero [16] destptr 556 (MOVDstorezero [8] destptr 557 (MOVDstorezero [0] destptr mem))))) 558 559 (Zero [48] destptr mem) -> 560 (MOVDstorezero [40] destptr 561 (MOVDstorezero [32] destptr 562 (MOVDstorezero [24] destptr 563 (MOVDstorezero [16] destptr 564 (MOVDstorezero [8] destptr 565 (MOVDstorezero [0] destptr mem)))))) 566 567 (Zero [56] destptr mem) -> 568 (MOVDstorezero [48] destptr 569 (MOVDstorezero [40] destptr 570 (MOVDstorezero [32] destptr 571 (MOVDstorezero [24] destptr 572 (MOVDstorezero [16] destptr 573 (MOVDstorezero [8] destptr 574 (MOVDstorezero [0] destptr mem))))))) 575 576 // Handle cases not handled above 577 (Zero [s] ptr mem) -> (LoweredZero [s] ptr mem) 578 579 // moves 580 // Only the MOVD and MOVW instructions require 4 byte 581 // alignment in the offset field. The other MOVx instructions 582 // allow any alignment. 583 (Move [0] _ _ mem) -> mem 584 (Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem) 585 (Move [2] dst src mem) -> 586 (MOVHstore dst (MOVHZload src mem) mem) 587 (Move [4] dst src mem) -> 588 (MOVWstore dst (MOVWZload src mem) mem) 589 // MOVD for load and store must have offsets that are multiple of 4 590 (Move [8] {t} dst src mem) && t.(*types.Type).Alignment()%4 == 0 -> 591 (MOVDstore dst (MOVDload src mem) mem) 592 (Move [8] dst src mem) -> 593 (MOVWstore [4] dst (MOVWZload [4] src mem) 594 (MOVWstore dst (MOVWZload src mem) mem)) 595 (Move [3] dst src mem) -> 596 (MOVBstore [2] dst (MOVBZload [2] src mem) 597 (MOVHstore dst (MOVHload src mem) mem)) 598 (Move [5] dst src mem) -> 599 (MOVBstore [4] dst (MOVBZload [4] src mem) 600 (MOVWstore dst (MOVWZload src mem) mem)) 601 (Move [6] dst src mem) -> 602 (MOVHstore [4] dst (MOVHZload [4] src mem) 603 (MOVWstore dst (MOVWZload src mem) mem)) 604 (Move [7] dst src mem) -> 605 (MOVBstore [6] dst (MOVBZload [6] src mem) 606 (MOVHstore [4] dst (MOVHZload [4] src mem) 607 (MOVWstore dst (MOVWZload src mem) mem))) 608 609 // Large move uses a loop. Since the address is computed and the 610 // offset is zero, any alignment can be used. 611 (Move [s] dst src mem) && s > 8 -> 612 (LoweredMove [s] dst src mem) 613 614 // Calls 615 // Lowering calls 616 (StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem) 617 (ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem) 618 (InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem) 619 620 // Miscellaneous 621 (Convert <t> x mem) -> (MOVDconvert <t> x mem) 622 (GetClosurePtr) -> (LoweredGetClosurePtr) 623 (IsNonNil ptr) -> (NotEqual (CMPconst [0] ptr)) 624 (IsInBounds idx len) -> (LessThan (CMPU idx len)) 625 (IsSliceInBounds idx len) -> (LessEqual (CMPU idx len)) 626 (NilCheck ptr mem) -> (LoweredNilCheck ptr mem) 627 628 // Optimizations 629 // Note that PPC "logical" immediates come in 0:15 and 16:31 unsigned immediate forms, 630 // so ORconst, XORconst easily expand into a pair. 631 632 // Include very-large constants in the const-const case. 633 (AND (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c&d]) 634 (OR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c|d]) 635 (XOR (MOVDconst [c]) (MOVDconst [d])) -> (MOVDconst [c^d]) 636 637 // Discover consts 638 (AND x (MOVDconst [c])) && isU16Bit(c) -> (ANDconst [c] x) 639 (XOR x (MOVDconst [c])) && isU32Bit(c) -> (XORconst [c] x) 640 (OR x (MOVDconst [c])) && isU32Bit(c) -> (ORconst [c] x) 641 642 // Simplify consts 643 (ANDconst [c] (ANDconst [d] x)) -> (ANDconst [c&d] x) 644 (ORconst [c] (ORconst [d] x)) -> (ORconst [c|d] x) 645 (XORconst [c] (XORconst [d] x)) -> (XORconst [c^d] x) 646 (ANDconst [-1] x) -> x 647 (ANDconst [0] _) -> (MOVDconst [0]) 648 (XORconst [0] x) -> x 649 (ORconst [-1] _) -> (MOVDconst [-1]) 650 (ORconst [0] x) -> x 651 652 // zero-extend of small and -> small and 653 (MOVBZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFF -> y 654 (MOVHZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF -> y 655 (MOVWZreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFFFFFF -> y 656 (MOVWZreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0xFFFFFFFF -> y 657 658 // sign extend of small-positive and -> small-positive-and 659 (MOVBreg y:(ANDconst [c] _)) && uint64(c) <= 0x7F -> y 660 (MOVHreg y:(ANDconst [c] _)) && uint64(c) <= 0x7FFF -> y 661 (MOVWreg y:(ANDconst [c] _)) && uint64(c) <= 0xFFFF -> y // 0xFFFF is largest immediate constant, when regarded as 32-bit is > 0 662 (MOVWreg y:(AND (MOVDconst [c]) _)) && uint64(c) <= 0x7FFFFFFF -> y 663 664 // small and of zero-extend -> either zero-extend or small and 665 // degenerate-and 666 (ANDconst [c] y:(MOVBZreg _)) && c&0xFF == 0xFF -> y 667 (ANDconst [c] y:(MOVHZreg _)) && c&0xFFFF == 0xFFFF -> y 668 (ANDconst [c] y:(MOVWZreg _)) && c&0xFFFFFFFF == 0xFFFFFFFF -> y 669 // normal case 670 (ANDconst [c] (MOVBZreg x)) -> (ANDconst [c&0xFF] x) 671 (ANDconst [c] (MOVHZreg x)) -> (ANDconst [c&0xFFFF] x) 672 (ANDconst [c] (MOVWZreg x)) -> (ANDconst [c&0xFFFFFFFF] x) 673 674 // Various redundant zero/sign extension combinations. 675 (MOVBZreg y:(MOVBZreg _)) -> y // repeat 676 (MOVBreg y:(MOVBreg _)) -> y // repeat 677 (MOVBreg (MOVBZreg x)) -> (MOVBreg x) 678 (MOVBZreg (MOVBreg x)) -> (MOVBZreg x) 679 680 // H - there are more combinations than these 681 682 (MOVHZreg y:(MOVHZreg _)) -> y // repeat 683 (MOVHZreg y:(MOVBZreg _)) -> y // wide of narrow 684 685 (MOVHreg y:(MOVHreg _)) -> y // repeat 686 (MOVHreg y:(MOVBreg _)) -> y // wide of narrow 687 688 (MOVHreg y:(MOVHZreg x)) -> (MOVHreg x) 689 (MOVHZreg y:(MOVHreg x)) -> (MOVHZreg x) 690 691 // W - there are more combinations than these 692 693 (MOVWZreg y:(MOVWZreg _)) -> y // repeat 694 (MOVWZreg y:(MOVHZreg _)) -> y // wide of narrow 695 (MOVWZreg y:(MOVBZreg _)) -> y // wide of narrow 696 697 (MOVWreg y:(MOVWreg _)) -> y // repeat 698 (MOVWreg y:(MOVHreg _)) -> y // wide of narrow 699 (MOVWreg y:(MOVBreg _)) -> y // wide of narrow 700 701 (MOVWreg y:(MOVWZreg x)) -> (MOVWreg x) 702 (MOVWZreg y:(MOVWreg x)) -> (MOVWZreg x) 703 704 // Arithmetic constant ops 705 706 (ADD x (MOVDconst [c])) && is32Bit(c) -> (ADDconst [c] x) 707 (ADDconst [c] (ADDconst [d] x)) && is32Bit(c+d) -> (ADDconst [c+d] x) 708 (ADDconst [0] x) -> x 709 (SUB x (MOVDconst [c])) && is32Bit(-c) -> (ADDconst [-c] x) 710 // TODO deal with subtract-from-const 711 712 (ADDconst [c] (MOVDaddr [d] {sym} x)) -> (MOVDaddr [c+d] {sym} x) 713 714 // Fold offsets for stores. 715 (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} x val mem) 716 (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} x val mem) 717 (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} x val mem) 718 (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} x val mem) 719 720 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is16Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem) 721 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is16Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem) 722 723 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 724 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 725 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 726 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 727 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 728 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 729 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 730 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 731 732 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 733 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 734 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) -> 735 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 736 737 (MOVBZload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 738 (MOVBZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 739 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 740 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 741 (MOVHZload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 742 (MOVHZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 743 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 744 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 745 (MOVWZload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 746 (MOVWZload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 747 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 748 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 749 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 750 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 751 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) -> 752 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 753 754 // Fold offsets for loads. 755 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is16Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem) 756 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is16Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem) 757 758 (MOVDload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVDload [off1+off2] {sym} x mem) 759 (MOVWload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVWload [off1+off2] {sym} x mem) 760 (MOVWZload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} x mem) 761 (MOVHload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVHload [off1+off2] {sym} x mem) 762 (MOVHZload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} x mem) 763 (MOVBZload [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} x mem) 764 765 // Store of zero -> storezero 766 (MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVDstorezero [off] {sym} ptr mem) 767 (MOVWstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVWstorezero [off] {sym} ptr mem) 768 (MOVHstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVHstorezero [off] {sym} ptr mem) 769 (MOVBstore [off] {sym} ptr (MOVDconst [c]) mem) && c == 0 -> (MOVBstorezero [off] {sym} ptr mem) 770 771 // Fold offsets for storezero 772 (MOVDstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> 773 (MOVDstorezero [off1+off2] {sym} x mem) 774 (MOVWstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> 775 (MOVWstorezero [off1+off2] {sym} x mem) 776 (MOVHstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> 777 (MOVHstorezero [off1+off2] {sym} x mem) 778 (MOVBstorezero [off1] {sym} (ADDconst [off2] x) mem) && is16Bit(off1+off2) -> 779 (MOVBstorezero [off1+off2] {sym} x mem) 780 781 // Fold symbols into storezero 782 (MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) -> 783 (MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) 784 (MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) -> 785 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) 786 (MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) -> 787 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) 788 (MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} x) mem) && canMergeSym(sym1,sym2) -> 789 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} x mem) 790 791 // atomic intrinsics 792 (AtomicLoad32 ptr mem) -> (LoweredAtomicLoad32 ptr mem) 793 (AtomicLoad64 ptr mem) -> (LoweredAtomicLoad64 ptr mem) 794 (AtomicLoadPtr ptr mem) -> (LoweredAtomicLoadPtr ptr mem) 795 796 (AtomicStore32 ptr val mem) -> (LoweredAtomicStore32 ptr val mem) 797 (AtomicStore64 ptr val mem) -> (LoweredAtomicStore64 ptr val mem) 798 //(AtomicStorePtrNoWB ptr val mem) -> (STLR ptr val mem) 799 800 (AtomicExchange32 ptr val mem) -> (LoweredAtomicExchange32 ptr val mem) 801 (AtomicExchange64 ptr val mem) -> (LoweredAtomicExchange64 ptr val mem) 802 803 (AtomicAdd32 ptr val mem) -> (LoweredAtomicAdd32 ptr val mem) 804 (AtomicAdd64 ptr val mem) -> (LoweredAtomicAdd64 ptr val mem) 805 806 (AtomicCompareAndSwap32 ptr old new_ mem) -> (LoweredAtomicCas32 ptr old new_ mem) 807 (AtomicCompareAndSwap64 ptr old new_ mem) -> (LoweredAtomicCas64 ptr old new_ mem) 808 809 (AtomicAnd8 ptr val mem) -> (LoweredAtomicAnd8 ptr val mem) 810 (AtomicOr8 ptr val mem) -> (LoweredAtomicOr8 ptr val mem) 811 812 // Lowering extension 813 // Note: we always extend to 64 bits even though some ops don't need that many result bits. 814 (SignExt8to16 x) -> (MOVBreg x) 815 (SignExt8to32 x) -> (MOVBreg x) 816 (SignExt8to64 x) -> (MOVBreg x) 817 (SignExt16to32 x) -> (MOVHreg x) 818 (SignExt16to64 x) -> (MOVHreg x) 819 (SignExt32to64 x) -> (MOVWreg x) 820 821 (ZeroExt8to16 x) -> (MOVBZreg x) 822 (ZeroExt8to32 x) -> (MOVBZreg x) 823 (ZeroExt8to64 x) -> (MOVBZreg x) 824 (ZeroExt16to32 x) -> (MOVHZreg x) 825 (ZeroExt16to64 x) -> (MOVHZreg x) 826 (ZeroExt32to64 x) -> (MOVWZreg x) 827 828 (Trunc16to8 x) -> (MOVBreg x) 829 (Trunc32to8 x) -> (MOVBreg x) 830 (Trunc32to16 x) -> (MOVHreg x) 831 (Trunc64to8 x) -> (MOVBreg x) 832 (Trunc64to16 x) -> (MOVHreg x) 833 (Trunc64to32 x) -> (MOVWreg x) 834 835 (Slicemask <t> x) -> (SRADconst (NEG <t> x) [63]) 836 837 // Note that MOV??reg returns a 64-bit int, x is not necessarily that wide 838 // This may interact with other patterns in the future. (Compare with arm64) 839 (MOVBZreg x:(MOVBZload _ _)) -> x 840 (MOVHZreg x:(MOVHZload _ _)) -> x 841 (MOVHreg x:(MOVHload _ _)) -> x 842 843 (MOVBZreg (MOVDconst [c])) -> (MOVDconst [int64(uint8(c))]) 844 (MOVBreg (MOVDconst [c])) -> (MOVDconst [int64(int8(c))]) 845 (MOVHZreg (MOVDconst [c])) -> (MOVDconst [int64(uint16(c))]) 846 (MOVHreg (MOVDconst [c])) -> (MOVDconst [int64(int16(c))]) 847 848 // Lose widening ops fed to to stores 849 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 850 (MOVBstore [off] {sym} ptr (MOVBZreg x) mem) -> (MOVBstore [off] {sym} ptr x mem) 851 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 852 (MOVHstore [off] {sym} ptr (MOVHZreg x) mem) -> (MOVHstore [off] {sym} ptr x mem) 853 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 854 (MOVWstore [off] {sym} ptr (MOVWZreg x) mem) -> (MOVWstore [off] {sym} ptr x mem) 855 856 // Lose W-widening ops fed to compare-W 857 (CMPW x (MOVWreg y)) -> (CMPW x y) 858 (CMPW (MOVWreg x) y) -> (CMPW x y) 859 (CMPWU x (MOVWZreg y)) -> (CMPWU x y) 860 (CMPWU (MOVWZreg x) y) -> (CMPWU x y) 861 862 (CMP x (MOVDconst [c])) && is16Bit(c) -> (CMPconst x [c]) 863 (CMP (MOVDconst [c]) y) && is16Bit(c) -> (InvertFlags (CMPconst y [c])) 864 (CMPW x (MOVDconst [c])) && is16Bit(c) -> (CMPWconst x [c]) 865 (CMPW (MOVDconst [c]) y) && is16Bit(c) -> (InvertFlags (CMPWconst y [c])) 866 867 (CMPU x (MOVDconst [c])) && isU16Bit(c) -> (CMPUconst x [c]) 868 (CMPU (MOVDconst [c]) y) && isU16Bit(c) -> (InvertFlags (CMPUconst y [c])) 869 (CMPWU x (MOVDconst [c])) && isU16Bit(c) -> (CMPWUconst x [c]) 870 (CMPWU (MOVDconst [c]) y) && isU16Bit(c) -> (InvertFlags (CMPWUconst y [c])) 871 872 // A particular pattern seen in cgo code: 873 (AND (MOVDconst [c]) x:(MOVBZload _ _)) -> (ANDconst [c&0xFF] x) 874 (AND x:(MOVBZload _ _) (MOVDconst [c])) -> (ANDconst [c&0xFF] x) 875 876 // floating-point fused multiply-add/sub 877 (FADD (FMUL x y) z) -> (FMADD x y z) 878 (FSUB (FMUL x y) z) -> (FMSUB x y z) 879 (FADDS (FMULS x y) z) -> (FMADDS x y z) 880 (FSUBS (FMULS x y) z) -> (FMSUBS x y z)