github.com/filosottile/go@v0.0.0-20170906193555-dbed9972d994/src/cmd/internal/obj/arm64/a.out.go (about) 1 // cmd/7c/7.out.h from Vita Nuova. 2 // https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h 3 // 4 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 5 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 6 // Portions Copyright © 1997-1999 Vita Nuova Limited 7 // Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com) 8 // Portions Copyright © 2004,2006 Bruce Ellis 9 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 10 // Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others 11 // Portions Copyright © 2009 The Go Authors. All rights reserved. 12 // 13 // Permission is hereby granted, free of charge, to any person obtaining a copy 14 // of this software and associated documentation files (the "Software"), to deal 15 // in the Software without restriction, including without limitation the rights 16 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 // copies of the Software, and to permit persons to whom the Software is 18 // furnished to do so, subject to the following conditions: 19 // 20 // The above copyright notice and this permission notice shall be included in 21 // all copies or substantial portions of the Software. 22 // 23 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 26 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 // THE SOFTWARE. 30 31 package arm64 32 33 import "cmd/internal/obj" 34 35 const ( 36 NSNAME = 8 37 NSYM = 50 38 NREG = 32 /* number of general registers */ 39 NFREG = 32 /* number of floating point registers */ 40 ) 41 42 // General purpose registers, kept in the low bits of Prog.Reg. 43 const ( 44 // integer 45 REG_R0 = obj.RBaseARM64 + iota 46 REG_R1 47 REG_R2 48 REG_R3 49 REG_R4 50 REG_R5 51 REG_R6 52 REG_R7 53 REG_R8 54 REG_R9 55 REG_R10 56 REG_R11 57 REG_R12 58 REG_R13 59 REG_R14 60 REG_R15 61 REG_R16 62 REG_R17 63 REG_R18 64 REG_R19 65 REG_R20 66 REG_R21 67 REG_R22 68 REG_R23 69 REG_R24 70 REG_R25 71 REG_R26 72 REG_R27 73 REG_R28 74 REG_R29 75 REG_R30 76 REG_R31 77 78 // scalar floating point 79 REG_F0 80 REG_F1 81 REG_F2 82 REG_F3 83 REG_F4 84 REG_F5 85 REG_F6 86 REG_F7 87 REG_F8 88 REG_F9 89 REG_F10 90 REG_F11 91 REG_F12 92 REG_F13 93 REG_F14 94 REG_F15 95 REG_F16 96 REG_F17 97 REG_F18 98 REG_F19 99 REG_F20 100 REG_F21 101 REG_F22 102 REG_F23 103 REG_F24 104 REG_F25 105 REG_F26 106 REG_F27 107 REG_F28 108 REG_F29 109 REG_F30 110 REG_F31 111 112 // SIMD 113 REG_V0 114 REG_V1 115 REG_V2 116 REG_V3 117 REG_V4 118 REG_V5 119 REG_V6 120 REG_V7 121 REG_V8 122 REG_V9 123 REG_V10 124 REG_V11 125 REG_V12 126 REG_V13 127 REG_V14 128 REG_V15 129 REG_V16 130 REG_V17 131 REG_V18 132 REG_V19 133 REG_V20 134 REG_V21 135 REG_V22 136 REG_V23 137 REG_V24 138 REG_V25 139 REG_V26 140 REG_V27 141 REG_V28 142 REG_V29 143 REG_V30 144 REG_V31 145 146 // The EQ in 147 // CSET EQ, R0 148 // is encoded as TYPE_REG, even though it's not really a register. 149 COND_EQ 150 COND_NE 151 COND_HS 152 COND_LO 153 COND_MI 154 COND_PL 155 COND_VS 156 COND_VC 157 COND_HI 158 COND_LS 159 COND_GE 160 COND_LT 161 COND_GT 162 COND_LE 163 COND_AL 164 COND_NV 165 166 REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31 167 ) 168 169 // Not registers, but flags that can be combined with regular register 170 // constants to indicate extended register conversion. When checking, 171 // you should subtract obj.RBaseARM64 first. From this difference, bit 11 172 // indicates extended register, bits 8-10 select the conversion mode. 173 const REG_EXT = obj.RBaseARM64 + 1<<11 174 175 const ( 176 REG_UXTB = REG_EXT + iota<<8 177 REG_UXTH 178 REG_UXTW 179 REG_UXTX 180 REG_SXTB 181 REG_SXTH 182 REG_SXTW 183 REG_SXTX 184 ) 185 186 // Special registers, after subtracting obj.RBaseARM64, bit 12 indicates 187 // a special register and the low bits select the register. 188 const ( 189 REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota 190 REG_DAIF 191 REG_NZCV 192 REG_FPSR 193 REG_FPCR 194 REG_SPSR_EL1 195 REG_ELR_EL1 196 REG_SPSR_EL2 197 REG_ELR_EL2 198 REG_CurrentEL 199 REG_SP_EL0 200 REG_SPSel 201 REG_DAIFSet 202 REG_DAIFClr 203 ) 204 205 // Register assignments: 206 // 207 // compiler allocates R0 up as temps 208 // compiler allocates register variables R7-R25 209 // compiler allocates external registers R26 down 210 // 211 // compiler allocates register variables F7-F26 212 // compiler allocates external registers F26 down 213 const ( 214 REGMIN = REG_R7 // register variables allocated from here to REGMAX 215 REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy 216 REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy 217 REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain 218 REGMAX = REG_R25 219 220 REGCTXT = REG_R26 // environment for closures 221 REGTMP = REG_R27 // reserved for liblink 222 REGG = REG_R28 // G 223 REGFP = REG_R29 // frame pointer, unused in the Go toolchain 224 REGLINK = REG_R30 225 226 // ARM64 uses R31 as both stack pointer and zero register, 227 // depending on the instruction. To differentiate RSP from ZR, 228 // we use a different numeric value for REGZERO and REGSP. 229 REGZERO = REG_R31 230 REGSP = REG_RSP 231 232 FREGRET = REG_F0 233 FREGMIN = REG_F7 // first register variable 234 FREGMAX = REG_F26 // last register variable for 7g only 235 FREGEXT = REG_F26 // first external register 236 ) 237 238 const ( 239 BIG = 2048 - 8 240 ) 241 242 const ( 243 /* mark flags */ 244 LABEL = 1 << iota 245 LEAF 246 FLOAT 247 BRANCH 248 LOAD 249 FCMP 250 SYNC 251 LIST 252 FOLL 253 NOSCHED 254 ) 255 256 const ( 257 // optab is sorted based on the order of these constants 258 // and the first match is chosen. 259 // The more specific class needs to come earlier. 260 C_NONE = iota 261 C_REG // R0..R30 262 C_RSP // R0..R30, RSP 263 C_FREG // F0..F31 264 C_VREG // V0..V31 265 C_PAIR // (Rn, Rm) 266 C_SHIFT // Rn<<2 267 C_EXTREG // Rn.UXTB<<3 268 C_SPR // REG_NZCV 269 C_COND // EQ, NE, etc 270 271 C_ZCON // $0 or ZR 272 C_ABCON0 // could be C_ADDCON0 or C_BITCON 273 C_ADDCON0 // 12-bit unsigned, unshifted 274 C_ABCON // could be C_ADDCON or C_BITCON 275 C_ADDCON // 12-bit unsigned, shifted left by 0 or 12 276 C_MBCON // could be C_MOVCON or C_BITCON 277 C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16 278 C_BITCON // bitfield and logical immediate masks 279 C_LCON // 32-bit constant 280 C_VCON // 64-bit constant 281 C_FCON // floating-point constant 282 C_VCONADDR // 64-bit memory address 283 284 C_AACON // ADDCON offset in auto constant $a(FP) 285 C_LACON // 32-bit offset in auto constant $a(FP) 286 C_AECON // ADDCON offset in extern constant $e(SB) 287 288 // TODO(aram): only one branch class should be enough 289 C_SBRA // for TYPE_BRANCH 290 C_LBRA 291 292 C_NPAUTO // -512 <= x < 0, 0 mod 8 293 C_NSAUTO // -256 <= x < 0 294 C_PSAUTO_8 // 0 to 255, 0 mod 8 295 C_PSAUTO // 0 to 255 296 C_PPAUTO_8 // 0 to 504, 0 mod 8 297 C_PPAUTO // 0 to 504 298 C_UAUTO4K_8 // 0 to 4095, 0 mod 8 299 C_UAUTO4K_4 // 0 to 4095, 0 mod 4 300 C_UAUTO4K_2 // 0 to 4095, 0 mod 2 301 C_UAUTO4K // 0 to 4095 302 C_UAUTO8K_8 // 0 to 8190, 0 mod 8 303 C_UAUTO8K_4 // 0 to 8190, 0 mod 4 304 C_UAUTO8K // 0 to 8190, 0 mod 2 305 C_UAUTO16K_8 // 0 to 16380, 0 mod 8 306 C_UAUTO16K // 0 to 16380, 0 mod 4 307 C_UAUTO32K // 0 to 32760, 0 mod 8 308 C_LAUTO // any other 32-bit constant 309 310 C_SEXT1 // 0 to 4095, direct 311 C_SEXT2 // 0 to 8190 312 C_SEXT4 // 0 to 16380 313 C_SEXT8 // 0 to 32760 314 C_SEXT16 // 0 to 65520 315 C_LEXT 316 317 C_ZOREG // 0(R) 318 C_NPOREG // must mirror NPAUTO, etc 319 C_NSOREG 320 C_PSOREG_8 321 C_PSOREG 322 C_PPOREG_8 323 C_PPOREG 324 C_UOREG4K_8 325 C_UOREG4K_4 326 C_UOREG4K_2 327 C_UOREG4K 328 C_UOREG8K_8 329 C_UOREG8K_4 330 C_UOREG8K 331 C_UOREG16K_8 332 C_UOREG16K 333 C_UOREG32K 334 C_LOREG 335 336 C_ADDR // TODO(aram): explain difference from C_VCONADDR 337 338 // The GOT slot for a symbol in -dynlink mode. 339 C_GOTADDR 340 341 // TLS "var" in local exec mode: will become a constant offset from 342 // thread local base that is ultimately chosen by the program linker. 343 C_TLS_LE 344 345 // TLS "var" in initial exec mode: will become a memory address (chosen 346 // by the program linker) that the dynamic linker will fill with the 347 // offset from the thread local base. 348 C_TLS_IE 349 350 C_ROFF // register offset (including register extended) 351 352 C_GOK 353 C_TEXTSIZE 354 C_NCLASS // must be last 355 ) 356 357 const ( 358 C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it 359 C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it 360 ) 361 362 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64 363 364 const ( 365 AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota 366 AADCS 367 AADCSW 368 AADCW 369 AADD 370 AADDS 371 AADDSW 372 AADDW 373 AADR 374 AADRP 375 AAND 376 AANDS 377 AANDSW 378 AANDW 379 AASR 380 AASRW 381 AAT 382 ABFI 383 ABFIW 384 ABFM 385 ABFMW 386 ABFXIL 387 ABFXILW 388 ABIC 389 ABICS 390 ABICSW 391 ABICW 392 ABRK 393 ACBNZ 394 ACBNZW 395 ACBZ 396 ACBZW 397 ACCMN 398 ACCMNW 399 ACCMP 400 ACCMPW 401 ACINC 402 ACINCW 403 ACINV 404 ACINVW 405 ACLREX 406 ACLS 407 ACLSW 408 ACLZ 409 ACLZW 410 ACMN 411 ACMNW 412 ACMP 413 ACMPW 414 ACNEG 415 ACNEGW 416 ACRC32B 417 ACRC32CB 418 ACRC32CH 419 ACRC32CW 420 ACRC32CX 421 ACRC32H 422 ACRC32W 423 ACRC32X 424 ACSEL 425 ACSELW 426 ACSET 427 ACSETM 428 ACSETMW 429 ACSETW 430 ACSINC 431 ACSINCW 432 ACSINV 433 ACSINVW 434 ACSNEG 435 ACSNEGW 436 ADC 437 ADCPS1 438 ADCPS2 439 ADCPS3 440 ADMB 441 ADRPS 442 ADSB 443 AEON 444 AEONW 445 AEOR 446 AEORW 447 AERET 448 AEXTR 449 AEXTRW 450 AHINT 451 AHLT 452 AHVC 453 AIC 454 AISB 455 ALDAR 456 ALDARB 457 ALDARH 458 ALDARW 459 ALDAXP 460 ALDAXPW 461 ALDAXR 462 ALDAXRB 463 ALDAXRH 464 ALDAXRW 465 ALDP 466 ALDXR 467 ALDXRB 468 ALDXRH 469 ALDXRW 470 ALDXP 471 ALDXPW 472 ALSL 473 ALSLW 474 ALSR 475 ALSRW 476 AMADD 477 AMADDW 478 AMNEG 479 AMNEGW 480 AMOVK 481 AMOVKW 482 AMOVN 483 AMOVNW 484 AMOVZ 485 AMOVZW 486 AMRS 487 AMSR 488 AMSUB 489 AMSUBW 490 AMUL 491 AMULW 492 AMVN 493 AMVNW 494 ANEG 495 ANEGS 496 ANEGSW 497 ANEGW 498 ANGC 499 ANGCS 500 ANGCSW 501 ANGCW 502 AORN 503 AORNW 504 AORR 505 AORRW 506 APRFM 507 APRFUM 508 ARBIT 509 ARBITW 510 AREM 511 AREMW 512 AREV 513 AREV16 514 AREV16W 515 AREV32 516 AREVW 517 AROR 518 ARORW 519 ASBC 520 ASBCS 521 ASBCSW 522 ASBCW 523 ASBFIZ 524 ASBFIZW 525 ASBFM 526 ASBFMW 527 ASBFX 528 ASBFXW 529 ASDIV 530 ASDIVW 531 ASEV 532 ASEVL 533 ASMADDL 534 ASMC 535 ASMNEGL 536 ASMSUBL 537 ASMULH 538 ASMULL 539 ASTXR 540 ASTXRB 541 ASTXRH 542 ASTXP 543 ASTXPW 544 ASTXRW 545 ASTLP 546 ASTLPW 547 ASTLR 548 ASTLRB 549 ASTLRH 550 ASTLRW 551 ASTLXP 552 ASTLXPW 553 ASTLXR 554 ASTLXRB 555 ASTLXRH 556 ASTLXRW 557 ASTP 558 ASUB 559 ASUBS 560 ASUBSW 561 ASUBW 562 ASVC 563 ASXTB 564 ASXTBW 565 ASXTH 566 ASXTHW 567 ASXTW 568 ASYS 569 ASYSL 570 ATBNZ 571 ATBZ 572 ATLBI 573 ATST 574 ATSTW 575 AUBFIZ 576 AUBFIZW 577 AUBFM 578 AUBFMW 579 AUBFX 580 AUBFXW 581 AUDIV 582 AUDIVW 583 AUMADDL 584 AUMNEGL 585 AUMSUBL 586 AUMULH 587 AUMULL 588 AUREM 589 AUREMW 590 AUXTB 591 AUXTH 592 AUXTW 593 AUXTBW 594 AUXTHW 595 AWFE 596 AWFI 597 AYIELD 598 AMOVB 599 AMOVBU 600 AMOVH 601 AMOVHU 602 AMOVW 603 AMOVWU 604 AMOVD 605 AMOVNP 606 AMOVNPW 607 AMOVP 608 AMOVPD 609 AMOVPQ 610 AMOVPS 611 AMOVPSW 612 AMOVPW 613 ABEQ 614 ABNE 615 ABCS 616 ABHS 617 ABCC 618 ABLO 619 ABMI 620 ABPL 621 ABVS 622 ABVC 623 ABHI 624 ABLS 625 ABGE 626 ABLT 627 ABGT 628 ABLE 629 AFABSD 630 AFABSS 631 AFADDD 632 AFADDS 633 AFCCMPD 634 AFCCMPED 635 AFCCMPS 636 AFCCMPES 637 AFCMPD 638 AFCMPED 639 AFCMPES 640 AFCMPS 641 AFCVTSD 642 AFCVTDS 643 AFCVTZSD 644 AFCVTZSDW 645 AFCVTZSS 646 AFCVTZSSW 647 AFCVTZUD 648 AFCVTZUDW 649 AFCVTZUS 650 AFCVTZUSW 651 AFDIVD 652 AFDIVS 653 AFMOVD 654 AFMOVS 655 AFMULD 656 AFMULS 657 AFNEGD 658 AFNEGS 659 AFSQRTD 660 AFSQRTS 661 AFSUBD 662 AFSUBS 663 ASCVTFD 664 ASCVTFS 665 ASCVTFWD 666 ASCVTFWS 667 AUCVTFD 668 AUCVTFS 669 AUCVTFWD 670 AUCVTFWS 671 AWORD 672 ADWORD 673 AFCSELS 674 AFCSELD 675 AFMAXS 676 AFMINS 677 AFMAXD 678 AFMIND 679 AFMAXNMS 680 AFMAXNMD 681 AFNMULS 682 AFNMULD 683 AFRINTNS 684 AFRINTND 685 AFRINTPS 686 AFRINTPD 687 AFRINTMS 688 AFRINTMD 689 AFRINTZS 690 AFRINTZD 691 AFRINTAS 692 AFRINTAD 693 AFRINTXS 694 AFRINTXD 695 AFRINTIS 696 AFRINTID 697 AFMADDS 698 AFMADDD 699 AFMSUBS 700 AFMSUBD 701 AFNMADDS 702 AFNMADDD 703 AFNMSUBS 704 AFNMSUBD 705 AFMINNMS 706 AFMINNMD 707 AFCVTDH 708 AFCVTHS 709 AFCVTHD 710 AFCVTSH 711 AAESD 712 AAESE 713 AAESIMC 714 AAESMC 715 ASHA1C 716 ASHA1H 717 ASHA1M 718 ASHA1P 719 ASHA1SU0 720 ASHA1SU1 721 ASHA256H 722 ASHA256H2 723 ASHA256SU0 724 ASHA256SU1 725 ALAST 726 AB = obj.AJMP 727 ABL = obj.ACALL 728 ) 729 730 const ( 731 // shift types 732 SHIFT_LL = 0 << 22 733 SHIFT_LR = 1 << 22 734 SHIFT_AR = 2 << 22 735 )