github.com/filosottile/go@v0.0.0-20170906193555-dbed9972d994/src/cmd/internal/obj/ppc64/a.out.go (about) 1 // cmd/9c/9.out.h from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import "cmd/internal/obj" 33 34 //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64 35 36 /* 37 * powerpc 64 38 */ 39 const ( 40 NSNAME = 8 41 NSYM = 50 42 NREG = 32 /* number of general registers */ 43 NFREG = 32 /* number of floating point registers */ 44 ) 45 46 const ( 47 /* RBasePPC64 = 4096 */ 48 /* R0=4096 ... R31=4127 */ 49 REG_R0 = obj.RBasePPC64 + iota 50 REG_R1 51 REG_R2 52 REG_R3 53 REG_R4 54 REG_R5 55 REG_R6 56 REG_R7 57 REG_R8 58 REG_R9 59 REG_R10 60 REG_R11 61 REG_R12 62 REG_R13 63 REG_R14 64 REG_R15 65 REG_R16 66 REG_R17 67 REG_R18 68 REG_R19 69 REG_R20 70 REG_R21 71 REG_R22 72 REG_R23 73 REG_R24 74 REG_R25 75 REG_R26 76 REG_R27 77 REG_R28 78 REG_R29 79 REG_R30 80 REG_R31 81 82 /* F0=4128 ... F31=4159 */ 83 REG_F0 84 REG_F1 85 REG_F2 86 REG_F3 87 REG_F4 88 REG_F5 89 REG_F6 90 REG_F7 91 REG_F8 92 REG_F9 93 REG_F10 94 REG_F11 95 REG_F12 96 REG_F13 97 REG_F14 98 REG_F15 99 REG_F16 100 REG_F17 101 REG_F18 102 REG_F19 103 REG_F20 104 REG_F21 105 REG_F22 106 REG_F23 107 REG_F24 108 REG_F25 109 REG_F26 110 REG_F27 111 REG_F28 112 REG_F29 113 REG_F30 114 REG_F31 115 116 /* V0=4160 ... V31=4191 */ 117 REG_V0 118 REG_V1 119 REG_V2 120 REG_V3 121 REG_V4 122 REG_V5 123 REG_V6 124 REG_V7 125 REG_V8 126 REG_V9 127 REG_V10 128 REG_V11 129 REG_V12 130 REG_V13 131 REG_V14 132 REG_V15 133 REG_V16 134 REG_V17 135 REG_V18 136 REG_V19 137 REG_V20 138 REG_V21 139 REG_V22 140 REG_V23 141 REG_V24 142 REG_V25 143 REG_V26 144 REG_V27 145 REG_V28 146 REG_V29 147 REG_V30 148 REG_V31 149 150 /* VS0=4192 ... VS63=4255 */ 151 REG_VS0 152 REG_VS1 153 REG_VS2 154 REG_VS3 155 REG_VS4 156 REG_VS5 157 REG_VS6 158 REG_VS7 159 REG_VS8 160 REG_VS9 161 REG_VS10 162 REG_VS11 163 REG_VS12 164 REG_VS13 165 REG_VS14 166 REG_VS15 167 REG_VS16 168 REG_VS17 169 REG_VS18 170 REG_VS19 171 REG_VS20 172 REG_VS21 173 REG_VS22 174 REG_VS23 175 REG_VS24 176 REG_VS25 177 REG_VS26 178 REG_VS27 179 REG_VS28 180 REG_VS29 181 REG_VS30 182 REG_VS31 183 REG_VS32 184 REG_VS33 185 REG_VS34 186 REG_VS35 187 REG_VS36 188 REG_VS37 189 REG_VS38 190 REG_VS39 191 REG_VS40 192 REG_VS41 193 REG_VS42 194 REG_VS43 195 REG_VS44 196 REG_VS45 197 REG_VS46 198 REG_VS47 199 REG_VS48 200 REG_VS49 201 REG_VS50 202 REG_VS51 203 REG_VS52 204 REG_VS53 205 REG_VS54 206 REG_VS55 207 REG_VS56 208 REG_VS57 209 REG_VS58 210 REG_VS59 211 REG_VS60 212 REG_VS61 213 REG_VS62 214 REG_VS63 215 216 REG_CR0 217 REG_CR1 218 REG_CR2 219 REG_CR3 220 REG_CR4 221 REG_CR5 222 REG_CR6 223 REG_CR7 224 225 REG_MSR 226 REG_FPSCR 227 REG_CR 228 229 REG_SPECIAL = REG_CR0 230 231 REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers 232 REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers 233 234 REG_XER = REG_SPR0 + 1 235 REG_LR = REG_SPR0 + 8 236 REG_CTR = REG_SPR0 + 9 237 238 REGZERO = REG_R0 /* set to zero */ 239 REGSP = REG_R1 240 REGSB = REG_R2 241 REGRET = REG_R3 242 REGARG = -1 /* -1 disables passing the first argument in register */ 243 REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */ 244 REGRT2 = REG_R4 /* reserved for runtime, duffcopy */ 245 REGMIN = REG_R7 /* register variables allocated from here to REGMAX */ 246 REGCTXT = REG_R11 /* context for closures */ 247 REGTLS = REG_R13 /* C ABI TLS base pointer */ 248 REGMAX = REG_R27 249 REGEXT = REG_R30 /* external registers allocated from here down */ 250 REGG = REG_R30 /* G */ 251 REGTMP = REG_R31 /* used by the linker */ 252 FREGRET = REG_F0 253 FREGMIN = REG_F17 /* first register variable */ 254 FREGMAX = REG_F26 /* last register variable for 9g only */ 255 FREGEXT = REG_F26 /* first external register */ 256 ) 257 258 /* 259 * GENERAL: 260 * 261 * compiler allocates R3 up as temps 262 * compiler allocates register variables R7-R27 263 * compiler allocates external registers R30 down 264 * 265 * compiler allocates register variables F17-F26 266 * compiler allocates external registers F26 down 267 */ 268 const ( 269 BIG = 32768 - 8 270 ) 271 272 const ( 273 /* mark flags */ 274 LABEL = 1 << 0 275 LEAF = 1 << 1 276 FLOAT = 1 << 2 277 BRANCH = 1 << 3 278 LOAD = 1 << 4 279 FCMP = 1 << 5 280 SYNC = 1 << 6 281 LIST = 1 << 7 282 FOLL = 1 << 8 283 NOSCHED = 1 << 9 284 ) 285 286 // Values for use in branch instruction BC 287 // BC B0,BI,label 288 // BO is type of branch + likely bits described below 289 // BI is CR value + branch type 290 // ex: BEQ CR2,label is BC 12,10,label 291 // 12 = BO_BCR 292 // 10 = BI_CR2 + BI_EQ 293 294 const ( 295 BI_CR0 = 0 296 BI_CR1 = 4 297 BI_CR2 = 8 298 BI_CR3 = 12 299 BI_CR4 = 16 300 BI_CR5 = 20 301 BI_CR6 = 24 302 BI_CR7 = 28 303 BI_LT = 0 304 BI_GT = 1 305 BI_EQ = 2 306 BI_OVF = 3 307 ) 308 309 // Values for the BO field. Add the branch type to 310 // the likely bits, if a likely setting is known. 311 // If branch likely or unlikely is not known, don't set it. 312 // e.g. branch on cr+likely = 15 313 314 const ( 315 BO_BCTR = 16 // branch on ctr value 316 BO_BCR = 12 // branch on cr value 317 BO_BCRBCTR = 8 // branch on ctr and cr value 318 BO_NOTBCR = 4 // branch on not cr value 319 BO_UNLIKELY = 2 // value for unlikely 320 BO_LIKELY = 3 // value for likely 321 ) 322 323 // Bit settings from the CR 324 325 const ( 326 C_COND_LT = iota // 0 result is negative 327 C_COND_GT // 1 result is positive 328 C_COND_EQ // 2 result is zero 329 C_COND_SO // 3 summary overflow or FP compare w/ NaN 330 ) 331 332 const ( 333 C_NONE = iota 334 C_REG 335 C_FREG 336 C_VREG 337 C_VSREG 338 C_CREG 339 C_SPR /* special processor register */ 340 C_ZCON 341 C_SCON /* 16 bit signed */ 342 C_UCON /* 32 bit signed, low 16 bits 0 */ 343 C_ADDCON /* -0x8000 <= v < 0 */ 344 C_ANDCON /* 0 < v <= 0xFFFF */ 345 C_LCON /* other 32 */ 346 C_DCON /* other 64 (could subdivide further) */ 347 C_SACON /* $n(REG) where n <= int16 */ 348 C_SECON 349 C_LACON /* $n(REG) where int16 < n <= int32 */ 350 C_LECON 351 C_DACON /* $n(REG) where int32 < n */ 352 C_SBRA 353 C_LBRA 354 C_LBRAPIC 355 C_SAUTO 356 C_LAUTO 357 C_SEXT 358 C_LEXT 359 C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG 360 C_SOREG // register + signed offset 361 C_LOREG 362 C_FPSCR 363 C_MSR 364 C_XER 365 C_LR 366 C_CTR 367 C_ANY 368 C_GOK 369 C_ADDR 370 C_GOTADDR 371 C_TLS_LE 372 C_TLS_IE 373 C_TEXTSIZE 374 375 C_NCLASS /* must be the last */ 376 ) 377 378 const ( 379 AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota 380 AADDCC 381 AADDV 382 AADDVCC 383 AADDC 384 AADDCCC 385 AADDCV 386 AADDCVCC 387 AADDME 388 AADDMECC 389 AADDMEVCC 390 AADDMEV 391 AADDE 392 AADDECC 393 AADDEVCC 394 AADDEV 395 AADDZE 396 AADDZECC 397 AADDZEVCC 398 AADDZEV 399 AADDEX 400 AAND 401 AANDCC 402 AANDN 403 AANDNCC 404 ABC 405 ABCL 406 ABEQ 407 ABGE // not LT = G/E/U 408 ABGT 409 ABLE // not GT = L/E/U 410 ABLT 411 ABNE // not EQ = L/G/U 412 ABVC // Unordered-clear 413 ABVS // Unordered-set 414 ACMP 415 ACMPU 416 ACMPEQB 417 ACNTLZW 418 ACNTLZWCC 419 ACRAND 420 ACRANDN 421 ACREQV 422 ACRNAND 423 ACRNOR 424 ACROR 425 ACRORN 426 ACRXOR 427 ADIVW 428 ADIVWCC 429 ADIVWVCC 430 ADIVWV 431 ADIVWU 432 ADIVWUCC 433 ADIVWUVCC 434 ADIVWUV 435 AEQV 436 AEQVCC 437 AEXTSB 438 AEXTSBCC 439 AEXTSH 440 AEXTSHCC 441 AFABS 442 AFABSCC 443 AFADD 444 AFADDCC 445 AFADDS 446 AFADDSCC 447 AFCMPO 448 AFCMPU 449 AFCTIW 450 AFCTIWCC 451 AFCTIWZ 452 AFCTIWZCC 453 AFDIV 454 AFDIVCC 455 AFDIVS 456 AFDIVSCC 457 AFMADD 458 AFMADDCC 459 AFMADDS 460 AFMADDSCC 461 AFMOVD 462 AFMOVDCC 463 AFMOVDU 464 AFMOVS 465 AFMOVSU 466 AFMOVSX 467 AFMOVSZ 468 AFMSUB 469 AFMSUBCC 470 AFMSUBS 471 AFMSUBSCC 472 AFMUL 473 AFMULCC 474 AFMULS 475 AFMULSCC 476 AFNABS 477 AFNABSCC 478 AFNEG 479 AFNEGCC 480 AFNMADD 481 AFNMADDCC 482 AFNMADDS 483 AFNMADDSCC 484 AFNMSUB 485 AFNMSUBCC 486 AFNMSUBS 487 AFNMSUBSCC 488 AFRSP 489 AFRSPCC 490 AFSUB 491 AFSUBCC 492 AFSUBS 493 AFSUBSCC 494 AISEL 495 AMOVMW 496 ALBAR 497 ALSW 498 ALWAR 499 ALWSYNC 500 AMOVDBR 501 AMOVWBR 502 AMOVB 503 AMOVBU 504 AMOVBZ 505 AMOVBZU 506 AMOVH 507 AMOVHBR 508 AMOVHU 509 AMOVHZ 510 AMOVHZU 511 AMOVW 512 AMOVWU 513 AMOVFL 514 AMOVCRFS 515 AMTFSB0 516 AMTFSB0CC 517 AMTFSB1 518 AMTFSB1CC 519 AMULHW 520 AMULHWCC 521 AMULHWU 522 AMULHWUCC 523 AMULLW 524 AMULLWCC 525 AMULLWVCC 526 AMULLWV 527 ANAND 528 ANANDCC 529 ANEG 530 ANEGCC 531 ANEGVCC 532 ANEGV 533 ANOR 534 ANORCC 535 AOR 536 AORCC 537 AORN 538 AORNCC 539 AREM 540 AREMCC 541 AREMV 542 AREMVCC 543 AREMU 544 AREMUCC 545 AREMUV 546 AREMUVCC 547 ARFI 548 ARLWMI 549 ARLWMICC 550 ARLWNM 551 ARLWNMCC 552 ASLW 553 ASLWCC 554 ASRW 555 ASRAW 556 ASRAWCC 557 ASRWCC 558 ASTBCCC 559 ASTSW 560 ASTWCCC 561 ASUB 562 ASUBCC 563 ASUBVCC 564 ASUBC 565 ASUBCCC 566 ASUBCV 567 ASUBCVCC 568 ASUBME 569 ASUBMECC 570 ASUBMEVCC 571 ASUBMEV 572 ASUBV 573 ASUBE 574 ASUBECC 575 ASUBEV 576 ASUBEVCC 577 ASUBZE 578 ASUBZECC 579 ASUBZEVCC 580 ASUBZEV 581 ASYNC 582 AXOR 583 AXORCC 584 585 ADCBF 586 ADCBI 587 ADCBST 588 ADCBT 589 ADCBTST 590 ADCBZ 591 AECIWX 592 AECOWX 593 AEIEIO 594 AICBI 595 AISYNC 596 APTESYNC 597 ATLBIE 598 ATLBIEL 599 ATLBSYNC 600 ATW 601 602 ASYSCALL 603 AWORD 604 605 ARFCI 606 607 /* optional on 32-bit */ 608 AFRES 609 AFRESCC 610 AFRIM 611 AFRIMCC 612 AFRIP 613 AFRIPCC 614 AFRIZ 615 AFRIZCC 616 AFRSQRTE 617 AFRSQRTECC 618 AFSEL 619 AFSELCC 620 AFSQRT 621 AFSQRTCC 622 AFSQRTS 623 AFSQRTSCC 624 625 /* 64-bit */ 626 627 ACNTLZD 628 ACNTLZDCC 629 ACMPW /* CMP with L=0 */ 630 ACMPWU 631 ACMPB 632 AFTDIV 633 AFTSQRT 634 ADIVD 635 ADIVDCC 636 ADIVDE 637 ADIVDECC 638 ADIVDEU 639 ADIVDEUCC 640 ADIVDVCC 641 ADIVDV 642 ADIVDU 643 ADIVDUCC 644 ADIVDUVCC 645 ADIVDUV 646 AEXTSW 647 AEXTSWCC 648 /* AFCFIW; AFCFIWCC */ 649 AFCFID 650 AFCFIDCC 651 AFCFIDU 652 AFCFIDUCC 653 AFCTID 654 AFCTIDCC 655 AFCTIDZ 656 AFCTIDZCC 657 ALDAR 658 AMOVD 659 AMOVDU 660 AMOVWZ 661 AMOVWZU 662 AMULHD 663 AMULHDCC 664 AMULHDU 665 AMULHDUCC 666 AMULLD 667 AMULLDCC 668 AMULLDVCC 669 AMULLDV 670 ARFID 671 ARLDMI 672 ARLDMICC 673 ARLDIMI 674 ARLDIMICC 675 ARLDC 676 ARLDCCC 677 ARLDCR 678 ARLDCRCC 679 ARLDICR 680 ARLDICRCC 681 ARLDCL 682 ARLDCLCC 683 ARLDICL 684 ARLDICLCC 685 AROTL 686 AROTLW 687 ASLBIA 688 ASLBIE 689 ASLBMFEE 690 ASLBMFEV 691 ASLBMTE 692 ASLD 693 ASLDCC 694 ASRD 695 ASRAD 696 ASRADCC 697 ASRDCC 698 ASTDCCC 699 ATD 700 701 /* 64-bit pseudo operation */ 702 ADWORD 703 AREMD 704 AREMDCC 705 AREMDV 706 AREMDVCC 707 AREMDU 708 AREMDUCC 709 AREMDUV 710 AREMDUVCC 711 712 /* more 64-bit operations */ 713 AHRFID 714 APOPCNTD 715 APOPCNTW 716 APOPCNTB 717 ACOPY 718 APASTECC 719 ADARN 720 ALDMX 721 AMADDHD 722 AMADDHDU 723 AMADDLD 724 725 /* Vector */ 726 ALV 727 ALVEBX 728 ALVEHX 729 ALVEWX 730 ALVX 731 ALVXL 732 ALVSL 733 ALVSR 734 ASTV 735 ASTVEBX 736 ASTVEHX 737 ASTVEWX 738 ASTVX 739 ASTVXL 740 AVAND 741 AVANDC 742 AVNAND 743 AVOR 744 AVORC 745 AVNOR 746 AVXOR 747 AVEQV 748 AVADDUM 749 AVADDUBM 750 AVADDUHM 751 AVADDUWM 752 AVADDUDM 753 AVADDUQM 754 AVADDCU 755 AVADDCUQ 756 AVADDCUW 757 AVADDUS 758 AVADDUBS 759 AVADDUHS 760 AVADDUWS 761 AVADDSS 762 AVADDSBS 763 AVADDSHS 764 AVADDSWS 765 AVADDE 766 AVADDEUQM 767 AVADDECUQ 768 AVSUBUM 769 AVSUBUBM 770 AVSUBUHM 771 AVSUBUWM 772 AVSUBUDM 773 AVSUBUQM 774 AVSUBCU 775 AVSUBCUQ 776 AVSUBCUW 777 AVSUBUS 778 AVSUBUBS 779 AVSUBUHS 780 AVSUBUWS 781 AVSUBSS 782 AVSUBSBS 783 AVSUBSHS 784 AVSUBSWS 785 AVSUBE 786 AVSUBEUQM 787 AVSUBECUQ 788 AVPMSUM 789 AVPMSUMB 790 AVPMSUMH 791 AVPMSUMW 792 AVPMSUMD 793 AVMSUMUDM 794 AVR 795 AVRLB 796 AVRLH 797 AVRLW 798 AVRLD 799 AVS 800 AVSLB 801 AVSLH 802 AVSLW 803 AVSL 804 AVSLO 805 AVSRB 806 AVSRH 807 AVSRW 808 AVSR 809 AVSRO 810 AVSLD 811 AVSRD 812 AVSA 813 AVSRAB 814 AVSRAH 815 AVSRAW 816 AVSRAD 817 AVSOI 818 AVSLDOI 819 AVCLZ 820 AVCLZB 821 AVCLZH 822 AVCLZW 823 AVCLZD 824 AVPOPCNT 825 AVPOPCNTB 826 AVPOPCNTH 827 AVPOPCNTW 828 AVPOPCNTD 829 AVCMPEQ 830 AVCMPEQUB 831 AVCMPEQUBCC 832 AVCMPEQUH 833 AVCMPEQUHCC 834 AVCMPEQUW 835 AVCMPEQUWCC 836 AVCMPEQUD 837 AVCMPEQUDCC 838 AVCMPGT 839 AVCMPGTUB 840 AVCMPGTUBCC 841 AVCMPGTUH 842 AVCMPGTUHCC 843 AVCMPGTUW 844 AVCMPGTUWCC 845 AVCMPGTUD 846 AVCMPGTUDCC 847 AVCMPGTSB 848 AVCMPGTSBCC 849 AVCMPGTSH 850 AVCMPGTSHCC 851 AVCMPGTSW 852 AVCMPGTSWCC 853 AVCMPGTSD 854 AVCMPGTSDCC 855 AVCMPNEZB 856 AVCMPNEZBCC 857 AVPERM 858 AVSEL 859 AVSPLT 860 AVSPLTB 861 AVSPLTH 862 AVSPLTW 863 AVSPLTI 864 AVSPLTISB 865 AVSPLTISH 866 AVSPLTISW 867 AVCIPH 868 AVCIPHER 869 AVCIPHERLAST 870 AVNCIPH 871 AVNCIPHER 872 AVNCIPHERLAST 873 AVSBOX 874 AVSHASIGMA 875 AVSHASIGMAW 876 AVSHASIGMAD 877 878 /* VSX */ 879 ALXV 880 ALXVD2X 881 ALXVDSX 882 ALXVW4X 883 ASTXV 884 ASTXVD2X 885 ASTXVW4X 886 ALXS 887 ALXSDX 888 ASTXS 889 ASTXSDX 890 ALXSI 891 ALXSIWAX 892 ALXSIWZX 893 ASTXSI 894 ASTXSIWX 895 AMFVSR 896 AMFVSRD 897 AMFFPRD 898 AMFVRD 899 AMFVSRWZ 900 AMFVSRLD 901 AMTVSR 902 AMTVSRD 903 AMTFPRD 904 AMTVRD 905 AMTVSRWA 906 AMTVSRWZ 907 AMTVSRDD 908 AMTVSRWS 909 AXXLAND 910 AXXLANDQ 911 AXXLANDC 912 AXXLEQV 913 AXXLNAND 914 AXXLOR 915 AXXLORC 916 AXXLNOR 917 AXXLORQ 918 AXXLXOR 919 AXXSEL 920 AXXMRG 921 AXXMRGHW 922 AXXMRGLW 923 AXXSPLT 924 AXXSPLTW 925 AXXPERM 926 AXXPERMDI 927 AXXSI 928 AXXSLDWI 929 AXSCV 930 AXSCVDPSP 931 AXSCVSPDP 932 AXSCVDPSPN 933 AXSCVSPDPN 934 AXVCV 935 AXVCVDPSP 936 AXVCVSPDP 937 AXSCVX 938 AXSCVDPSXDS 939 AXSCVDPSXWS 940 AXSCVDPUXDS 941 AXSCVDPUXWS 942 AXSCVXP 943 AXSCVSXDDP 944 AXSCVUXDDP 945 AXSCVSXDSP 946 AXSCVUXDSP 947 AXVCVX 948 AXVCVDPSXDS 949 AXVCVDPSXWS 950 AXVCVDPUXDS 951 AXVCVDPUXWS 952 AXVCVSPSXDS 953 AXVCVSPSXWS 954 AXVCVSPUXDS 955 AXVCVSPUXWS 956 AXVCVXP 957 AXVCVSXDDP 958 AXVCVSXWDP 959 AXVCVUXDDP 960 AXVCVUXWDP 961 AXVCVSXDSP 962 AXVCVSXWSP 963 AXVCVUXDSP 964 AXVCVUXWSP 965 966 ALAST 967 968 // aliases 969 ABR = obj.AJMP 970 ABL = obj.ACALL 971 )