github.com/filosottile/go@v0.0.0-20170906193555-dbed9972d994/src/cmd/internal/obj/ppc64/asm9.go (about) 1 // cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2 // 3 // Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4 // Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5 // Portions Copyright © 1997-1999 Vita Nuova Limited 6 // Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7 // Portions Copyright © 2004,2006 Bruce Ellis 8 // Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9 // Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10 // Portions Copyright © 2009 The Go Authors. All rights reserved. 11 // 12 // Permission is hereby granted, free of charge, to any person obtaining a copy 13 // of this software and associated documentation files (the "Software"), to deal 14 // in the Software without restriction, including without limitation the rights 15 // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 // copies of the Software, and to permit persons to whom the Software is 17 // furnished to do so, subject to the following conditions: 18 // 19 // The above copyright notice and this permission notice shall be included in 20 // all copies or substantial portions of the Software. 21 // 22 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 // THE SOFTWARE. 29 30 package ppc64 31 32 import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39 ) 40 41 // ctxt9 holds state while assembling a single function. 42 // Each function gets a fresh ctxt9. 43 // This allows for multiple functions to be safely concurrently assembled. 44 type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51 } 52 53 // Instruction layout. 54 55 const ( 56 funcAlign = 16 57 ) 58 59 const ( 60 r0iszero = 1 61 ) 62 63 type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72 } 73 74 var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form */ 366 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 367 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 368 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */ 369 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */ 370 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */ 371 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */ 372 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */ 373 374 /* Vector instructions */ 375 376 /* Vector load */ 377 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 378 379 /* Vector store */ 380 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 381 382 /* Vector logical */ 383 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 384 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 385 386 /* Vector add */ 387 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 388 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 389 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 390 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 391 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 392 393 /* Vector subtract */ 394 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 395 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 396 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 397 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 398 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 399 400 /* Vector multiply */ 401 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 402 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */ 403 404 /* Vector rotate */ 405 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 406 407 /* Vector shift */ 408 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 409 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 410 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 411 412 /* Vector count */ 413 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 414 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 415 416 /* Vector compare */ 417 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 418 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 419 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */ 420 421 /* Vector permute */ 422 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 423 424 /* Vector select */ 425 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 426 427 /* Vector splat */ 428 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 429 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 430 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 431 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 432 433 /* Vector AES */ 434 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 435 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 436 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 437 438 /* Vector SHA */ 439 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 440 441 /* VSX vector load */ 442 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 443 444 /* VSX vector store */ 445 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 446 447 /* VSX scalar load */ 448 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 449 450 /* VSX scalar store */ 451 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 452 453 /* VSX scalar as integer load */ 454 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 455 456 /* VSX scalar store as integer */ 457 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 458 459 /* VSX move from VSR */ 460 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 461 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 462 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 463 464 /* VSX move to VSR */ 465 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 466 {AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0}, 467 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 468 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 469 470 /* VSX logical */ 471 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 472 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 473 474 /* VSX select */ 475 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 476 477 /* VSX merge */ 478 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 479 480 /* VSX splat */ 481 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 482 483 /* VSX permute */ 484 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 485 486 /* VSX shift */ 487 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 488 489 /* VSX scalar FP-FP conversion */ 490 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 491 492 /* VSX vector FP-FP conversion */ 493 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 494 495 /* VSX scalar FP-integer conversion */ 496 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 497 498 /* VSX scalar integer-FP conversion */ 499 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 500 501 /* VSX vector FP-integer conversion */ 502 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 503 504 /* VSX vector integer-FP conversion */ 505 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 506 507 /* 64-bit special registers */ 508 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 509 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 510 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 511 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 512 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 513 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 514 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 515 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 516 517 /* 32-bit special registers (gloss over sign-extension or not?) */ 518 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 519 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 520 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 521 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 522 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 523 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 524 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 525 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 526 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 527 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 528 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 529 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 530 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 531 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 532 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 533 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 534 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 535 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 536 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 537 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 538 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 539 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 540 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 541 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 542 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 543 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 544 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 545 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 546 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 547 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 548 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 549 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 550 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 551 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 552 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 553 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 554 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 555 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 556 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 557 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 558 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 559 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 560 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 561 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 562 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 563 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 564 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 565 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 566 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 567 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 568 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 569 570 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 571 } 572 573 var oprange [ALAST & obj.AMask][]Optab 574 575 var xcmp [C_NCLASS][C_NCLASS]bool 576 577 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 578 p := cursym.Func.Text 579 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 580 return 581 } 582 583 if oprange[AANDN&obj.AMask] == nil { 584 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 585 } 586 587 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 588 589 pc := int64(0) 590 p.Pc = pc 591 592 var m int 593 var o *Optab 594 for p = p.Link; p != nil; p = p.Link { 595 p.Pc = pc 596 o = c.oplook(p) 597 m = int(o.size) 598 if m == 0 { 599 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 600 c.ctxt.Diag("zero-width instruction\n%v", p) 601 } 602 continue 603 } 604 605 pc += int64(m) 606 } 607 608 c.cursym.Size = pc 609 610 /* 611 * if any procedure is large enough to 612 * generate a large SBRA branch, then 613 * generate extra passes putting branches 614 * around jmps to fix. this is rare. 615 */ 616 bflag := 1 617 618 var otxt int64 619 var q *obj.Prog 620 for bflag != 0 { 621 bflag = 0 622 pc = 0 623 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 624 p.Pc = pc 625 o = c.oplook(p) 626 627 // very large conditional branches 628 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 629 otxt = p.Pcond.Pc - pc 630 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 631 q = c.newprog() 632 q.Link = p.Link 633 p.Link = q 634 q.As = ABR 635 q.To.Type = obj.TYPE_BRANCH 636 q.Pcond = p.Pcond 637 p.Pcond = q 638 q = c.newprog() 639 q.Link = p.Link 640 p.Link = q 641 q.As = ABR 642 q.To.Type = obj.TYPE_BRANCH 643 q.Pcond = q.Link.Link 644 645 //addnop(p->link); 646 //addnop(p); 647 bflag = 1 648 } 649 } 650 651 m = int(o.size) 652 if m == 0 { 653 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 654 c.ctxt.Diag("zero-width instruction\n%v", p) 655 } 656 continue 657 } 658 659 pc += int64(m) 660 } 661 662 c.cursym.Size = pc 663 } 664 665 pc += -pc & (funcAlign - 1) 666 c.cursym.Size = pc 667 668 /* 669 * lay out the code, emitting code and data relocations. 670 */ 671 672 c.cursym.Grow(c.cursym.Size) 673 674 bp := c.cursym.P 675 var i int32 676 var out [6]uint32 677 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 678 c.pc = p.Pc 679 o = c.oplook(p) 680 if int(o.size) > 4*len(out) { 681 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 682 } 683 c.asmout(p, o, out[:]) 684 for i = 0; i < int32(o.size/4); i++ { 685 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 686 bp = bp[4:] 687 } 688 } 689 } 690 691 func isint32(v int64) bool { 692 return int64(int32(v)) == v 693 } 694 695 func isuint32(v uint64) bool { 696 return uint64(uint32(v)) == v 697 } 698 699 func (c *ctxt9) aclass(a *obj.Addr) int { 700 switch a.Type { 701 case obj.TYPE_NONE: 702 return C_NONE 703 704 case obj.TYPE_REG: 705 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 706 return C_REG 707 } 708 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 709 return C_FREG 710 } 711 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 712 return C_VREG 713 } 714 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 715 return C_VSREG 716 } 717 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 718 return C_CREG 719 } 720 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 721 switch a.Reg { 722 case REG_LR: 723 return C_LR 724 725 case REG_XER: 726 return C_XER 727 728 case REG_CTR: 729 return C_CTR 730 } 731 732 return C_SPR 733 } 734 735 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 736 return C_SPR 737 } 738 if a.Reg == REG_FPSCR { 739 return C_FPSCR 740 } 741 if a.Reg == REG_MSR { 742 return C_MSR 743 } 744 return C_GOK 745 746 case obj.TYPE_MEM: 747 switch a.Name { 748 case obj.NAME_EXTERN, 749 obj.NAME_STATIC: 750 if a.Sym == nil { 751 break 752 } 753 c.instoffset = a.Offset 754 if a.Sym != nil { // use relocation 755 if a.Sym.Type == objabi.STLSBSS { 756 if c.ctxt.Flag_shared { 757 return C_TLS_IE 758 } else { 759 return C_TLS_LE 760 } 761 } 762 return C_ADDR 763 } 764 return C_LEXT 765 766 case obj.NAME_GOTREF: 767 return C_GOTADDR 768 769 case obj.NAME_AUTO: 770 c.instoffset = int64(c.autosize) + a.Offset 771 if c.instoffset >= -BIG && c.instoffset < BIG { 772 return C_SAUTO 773 } 774 return C_LAUTO 775 776 case obj.NAME_PARAM: 777 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 778 if c.instoffset >= -BIG && c.instoffset < BIG { 779 return C_SAUTO 780 } 781 return C_LAUTO 782 783 case obj.NAME_NONE: 784 c.instoffset = a.Offset 785 if c.instoffset == 0 { 786 return C_ZOREG 787 } 788 if c.instoffset >= -BIG && c.instoffset < BIG { 789 return C_SOREG 790 } 791 return C_LOREG 792 } 793 794 return C_GOK 795 796 case obj.TYPE_TEXTSIZE: 797 return C_TEXTSIZE 798 799 case obj.TYPE_CONST, 800 obj.TYPE_ADDR: 801 switch a.Name { 802 case obj.NAME_NONE: 803 c.instoffset = a.Offset 804 if a.Reg != 0 { 805 if -BIG <= c.instoffset && c.instoffset <= BIG { 806 return C_SACON 807 } 808 if isint32(c.instoffset) { 809 return C_LACON 810 } 811 return C_DACON 812 } 813 814 goto consize 815 816 case obj.NAME_EXTERN, 817 obj.NAME_STATIC: 818 s := a.Sym 819 if s == nil { 820 break 821 } 822 823 c.instoffset = a.Offset 824 825 /* not sure why this barfs */ 826 return C_LCON 827 828 case obj.NAME_AUTO: 829 c.instoffset = int64(c.autosize) + a.Offset 830 if c.instoffset >= -BIG && c.instoffset < BIG { 831 return C_SACON 832 } 833 return C_LACON 834 835 case obj.NAME_PARAM: 836 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 837 if c.instoffset >= -BIG && c.instoffset < BIG { 838 return C_SACON 839 } 840 return C_LACON 841 } 842 843 return C_GOK 844 845 consize: 846 if c.instoffset >= 0 { 847 if c.instoffset == 0 { 848 return C_ZCON 849 } 850 if c.instoffset <= 0x7fff { 851 return C_SCON 852 } 853 if c.instoffset <= 0xffff { 854 return C_ANDCON 855 } 856 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 857 return C_UCON 858 } 859 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 860 return C_LCON 861 } 862 return C_DCON 863 } 864 865 if c.instoffset >= -0x8000 { 866 return C_ADDCON 867 } 868 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 869 return C_UCON 870 } 871 if isint32(c.instoffset) { 872 return C_LCON 873 } 874 return C_DCON 875 876 case obj.TYPE_BRANCH: 877 if a.Sym != nil && c.ctxt.Flag_dynlink { 878 return C_LBRAPIC 879 } 880 return C_SBRA 881 } 882 883 return C_GOK 884 } 885 886 func prasm(p *obj.Prog) { 887 fmt.Printf("%v\n", p) 888 } 889 890 func (c *ctxt9) oplook(p *obj.Prog) *Optab { 891 a1 := int(p.Optab) 892 if a1 != 0 { 893 return &optab[a1-1] 894 } 895 a1 = int(p.From.Class) 896 if a1 == 0 { 897 a1 = c.aclass(&p.From) + 1 898 p.From.Class = int8(a1) 899 } 900 901 a1-- 902 a3 := C_NONE + 1 903 if p.From3 != nil { 904 a3 = int(p.From3.Class) 905 if a3 == 0 { 906 a3 = c.aclass(p.From3) + 1 907 p.From3.Class = int8(a3) 908 } 909 } 910 911 a3-- 912 a4 := int(p.To.Class) 913 if a4 == 0 { 914 a4 = c.aclass(&p.To) + 1 915 p.To.Class = int8(a4) 916 } 917 918 a4-- 919 a2 := C_NONE 920 if p.Reg != 0 { 921 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 922 a2 = C_REG 923 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 924 a2 = C_VREG 925 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 926 a2 = C_VSREG 927 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 928 a2 = C_FREG 929 } 930 } 931 932 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 933 ops := oprange[p.As&obj.AMask] 934 c1 := &xcmp[a1] 935 c3 := &xcmp[a3] 936 c4 := &xcmp[a4] 937 for i := range ops { 938 op := &ops[i] 939 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 940 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 941 return op 942 } 943 } 944 945 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 946 prasm(p) 947 if ops == nil { 948 ops = optab 949 } 950 return &ops[0] 951 } 952 953 func cmp(a int, b int) bool { 954 if a == b { 955 return true 956 } 957 switch a { 958 case C_LCON: 959 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 960 return true 961 } 962 963 case C_ADDCON: 964 if b == C_ZCON || b == C_SCON { 965 return true 966 } 967 968 case C_ANDCON: 969 if b == C_ZCON || b == C_SCON { 970 return true 971 } 972 973 case C_SPR: 974 if b == C_LR || b == C_XER || b == C_CTR { 975 return true 976 } 977 978 case C_UCON: 979 if b == C_ZCON { 980 return true 981 } 982 983 case C_SCON: 984 if b == C_ZCON { 985 return true 986 } 987 988 case C_LACON: 989 if b == C_SACON { 990 return true 991 } 992 993 case C_LBRA: 994 if b == C_SBRA { 995 return true 996 } 997 998 case C_LEXT: 999 if b == C_SEXT { 1000 return true 1001 } 1002 1003 case C_LAUTO: 1004 if b == C_SAUTO { 1005 return true 1006 } 1007 1008 case C_REG: 1009 if b == C_ZCON { 1010 return r0iszero != 0 /*TypeKind(100016)*/ 1011 } 1012 1013 case C_LOREG: 1014 if b == C_ZOREG || b == C_SOREG { 1015 return true 1016 } 1017 1018 case C_SOREG: 1019 if b == C_ZOREG { 1020 return true 1021 } 1022 1023 case C_ANY: 1024 return true 1025 } 1026 1027 return false 1028 } 1029 1030 type ocmp []Optab 1031 1032 func (x ocmp) Len() int { 1033 return len(x) 1034 } 1035 1036 func (x ocmp) Swap(i, j int) { 1037 x[i], x[j] = x[j], x[i] 1038 } 1039 1040 func (x ocmp) Less(i, j int) bool { 1041 p1 := &x[i] 1042 p2 := &x[j] 1043 n := int(p1.as) - int(p2.as) 1044 if n != 0 { 1045 return n < 0 1046 } 1047 n = int(p1.a1) - int(p2.a1) 1048 if n != 0 { 1049 return n < 0 1050 } 1051 n = int(p1.a2) - int(p2.a2) 1052 if n != 0 { 1053 return n < 0 1054 } 1055 n = int(p1.a3) - int(p2.a3) 1056 if n != 0 { 1057 return n < 0 1058 } 1059 n = int(p1.a4) - int(p2.a4) 1060 if n != 0 { 1061 return n < 0 1062 } 1063 return false 1064 } 1065 func opset(a, b0 obj.As) { 1066 oprange[a&obj.AMask] = oprange[b0] 1067 } 1068 1069 func buildop(ctxt *obj.Link) { 1070 if oprange[AANDN&obj.AMask] != nil { 1071 // Already initialized; stop now. 1072 // This happens in the cmd/asm tests, 1073 // each of which re-initializes the arch. 1074 return 1075 } 1076 1077 var n int 1078 1079 for i := 0; i < C_NCLASS; i++ { 1080 for n = 0; n < C_NCLASS; n++ { 1081 if cmp(n, i) { 1082 xcmp[i][n] = true 1083 } 1084 } 1085 } 1086 for n = 0; optab[n].as != obj.AXXX; n++ { 1087 } 1088 sort.Sort(ocmp(optab[:n])) 1089 for i := 0; i < n; i++ { 1090 r := optab[i].as 1091 r0 := r & obj.AMask 1092 start := i 1093 for optab[i].as == r { 1094 i++ 1095 } 1096 oprange[r0] = optab[start:i] 1097 i-- 1098 1099 switch r { 1100 default: 1101 ctxt.Diag("unknown op in build: %v", r) 1102 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1103 1104 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1105 opset(ADCBI, r0) 1106 1107 opset(ADCBST, r0) 1108 opset(ADCBT, r0) 1109 opset(ADCBTST, r0) 1110 opset(ADCBZ, r0) 1111 opset(AICBI, r0) 1112 1113 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1114 opset(ASTWCCC, r0) 1115 opset(ASTBCCC, r0) 1116 1117 opset(ASTDCCC, r0) 1118 1119 case AREM: /* macro */ 1120 opset(AREMCC, r0) 1121 1122 opset(AREMV, r0) 1123 opset(AREMVCC, r0) 1124 1125 case AREMU: 1126 opset(AREMU, r0) 1127 opset(AREMUCC, r0) 1128 opset(AREMUV, r0) 1129 opset(AREMUVCC, r0) 1130 1131 case AREMD: 1132 opset(AREMDCC, r0) 1133 opset(AREMDV, r0) 1134 opset(AREMDVCC, r0) 1135 1136 case AREMDU: 1137 opset(AREMDU, r0) 1138 opset(AREMDUCC, r0) 1139 opset(AREMDUV, r0) 1140 opset(AREMDUVCC, r0) 1141 1142 case ADIVW: /* op Rb[,Ra],Rd */ 1143 opset(AMULHW, r0) 1144 1145 opset(AMULHWCC, r0) 1146 opset(AMULHWU, r0) 1147 opset(AMULHWUCC, r0) 1148 opset(AMULLWCC, r0) 1149 opset(AMULLWVCC, r0) 1150 opset(AMULLWV, r0) 1151 opset(ADIVWCC, r0) 1152 opset(ADIVWV, r0) 1153 opset(ADIVWVCC, r0) 1154 opset(ADIVWU, r0) 1155 opset(ADIVWUCC, r0) 1156 opset(ADIVWUV, r0) 1157 opset(ADIVWUVCC, r0) 1158 opset(AADDCC, r0) 1159 opset(AADDCV, r0) 1160 opset(AADDCVCC, r0) 1161 opset(AADDV, r0) 1162 opset(AADDVCC, r0) 1163 opset(AADDE, r0) 1164 opset(AADDECC, r0) 1165 opset(AADDEV, r0) 1166 opset(AADDEVCC, r0) 1167 opset(ACRAND, r0) 1168 opset(ACRANDN, r0) 1169 opset(ACREQV, r0) 1170 opset(ACRNAND, r0) 1171 opset(ACRNOR, r0) 1172 opset(ACROR, r0) 1173 opset(ACRORN, r0) 1174 opset(ACRXOR, r0) 1175 opset(AMULHD, r0) 1176 opset(AMULHDCC, r0) 1177 opset(AMULHDU, r0) 1178 opset(AMULHDUCC, r0) 1179 opset(AMULLD, r0) 1180 opset(AMULLDCC, r0) 1181 opset(AMULLDVCC, r0) 1182 opset(AMULLDV, r0) 1183 opset(ADIVD, r0) 1184 opset(ADIVDCC, r0) 1185 opset(ADIVDE, r0) 1186 opset(ADIVDEU, r0) 1187 opset(ADIVDECC, r0) 1188 opset(ADIVDEUCC, r0) 1189 opset(ADIVDVCC, r0) 1190 opset(ADIVDV, r0) 1191 opset(ADIVDU, r0) 1192 opset(ADIVDUCC, r0) 1193 opset(ADIVDUVCC, r0) 1194 opset(ADIVDUCC, r0) 1195 1196 case APOPCNTD: 1197 opset(APOPCNTW, r0) 1198 opset(APOPCNTB, r0) 1199 1200 case ACOPY: /* copy, paste. */ 1201 opset(APASTECC, r0) 1202 1203 case AMADDHD: /* maddhd, maddhdu, maddld */ 1204 opset(AMADDHDU, r0) 1205 opset(AMADDLD, r0) 1206 1207 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1208 opset(AMOVH, r0) 1209 opset(AMOVHZ, r0) 1210 1211 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1212 opset(AMOVHU, r0) 1213 1214 opset(AMOVHZU, r0) 1215 opset(AMOVWU, r0) 1216 opset(AMOVWZU, r0) 1217 opset(AMOVDU, r0) 1218 opset(AMOVMW, r0) 1219 1220 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1221 opset(ALVEBX, r0) 1222 opset(ALVEHX, r0) 1223 opset(ALVEWX, r0) 1224 opset(ALVX, r0) 1225 opset(ALVXL, r0) 1226 opset(ALVSL, r0) 1227 opset(ALVSR, r0) 1228 1229 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1230 opset(ASTVEBX, r0) 1231 opset(ASTVEHX, r0) 1232 opset(ASTVEWX, r0) 1233 opset(ASTVX, r0) 1234 opset(ASTVXL, r0) 1235 1236 case AVAND: /* vand, vandc, vnand */ 1237 opset(AVAND, r0) 1238 opset(AVANDC, r0) 1239 opset(AVNAND, r0) 1240 1241 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1242 opset(AVOR, r0) 1243 opset(AVORC, r0) 1244 opset(AVXOR, r0) 1245 opset(AVNOR, r0) 1246 opset(AVEQV, r0) 1247 1248 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1249 opset(AVADDUBM, r0) 1250 opset(AVADDUHM, r0) 1251 opset(AVADDUWM, r0) 1252 opset(AVADDUDM, r0) 1253 opset(AVADDUQM, r0) 1254 1255 case AVADDCU: /* vaddcuq, vaddcuw */ 1256 opset(AVADDCUQ, r0) 1257 opset(AVADDCUW, r0) 1258 1259 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1260 opset(AVADDUBS, r0) 1261 opset(AVADDUHS, r0) 1262 opset(AVADDUWS, r0) 1263 1264 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1265 opset(AVADDSBS, r0) 1266 opset(AVADDSHS, r0) 1267 opset(AVADDSWS, r0) 1268 1269 case AVADDE: /* vaddeuqm, vaddecuq */ 1270 opset(AVADDEUQM, r0) 1271 opset(AVADDECUQ, r0) 1272 1273 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1274 opset(AVSUBUBM, r0) 1275 opset(AVSUBUHM, r0) 1276 opset(AVSUBUWM, r0) 1277 opset(AVSUBUDM, r0) 1278 opset(AVSUBUQM, r0) 1279 1280 case AVSUBCU: /* vsubcuq, vsubcuw */ 1281 opset(AVSUBCUQ, r0) 1282 opset(AVSUBCUW, r0) 1283 1284 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1285 opset(AVSUBUBS, r0) 1286 opset(AVSUBUHS, r0) 1287 opset(AVSUBUWS, r0) 1288 1289 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1290 opset(AVSUBSBS, r0) 1291 opset(AVSUBSHS, r0) 1292 opset(AVSUBSWS, r0) 1293 1294 case AVSUBE: /* vsubeuqm, vsubecuq */ 1295 opset(AVSUBEUQM, r0) 1296 opset(AVSUBECUQ, r0) 1297 1298 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1299 opset(AVPMSUMB, r0) 1300 opset(AVPMSUMH, r0) 1301 opset(AVPMSUMW, r0) 1302 opset(AVPMSUMD, r0) 1303 1304 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1305 opset(AVRLB, r0) 1306 opset(AVRLH, r0) 1307 opset(AVRLW, r0) 1308 opset(AVRLD, r0) 1309 1310 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1311 opset(AVSLB, r0) 1312 opset(AVSLH, r0) 1313 opset(AVSLW, r0) 1314 opset(AVSL, r0) 1315 opset(AVSLO, r0) 1316 opset(AVSRB, r0) 1317 opset(AVSRH, r0) 1318 opset(AVSRW, r0) 1319 opset(AVSR, r0) 1320 opset(AVSRO, r0) 1321 opset(AVSLD, r0) 1322 opset(AVSRD, r0) 1323 1324 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1325 opset(AVSRAB, r0) 1326 opset(AVSRAH, r0) 1327 opset(AVSRAW, r0) 1328 opset(AVSRAD, r0) 1329 1330 case AVSOI: /* vsldoi */ 1331 opset(AVSLDOI, r0) 1332 1333 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1334 opset(AVCLZB, r0) 1335 opset(AVCLZH, r0) 1336 opset(AVCLZW, r0) 1337 opset(AVCLZD, r0) 1338 1339 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1340 opset(AVPOPCNTB, r0) 1341 opset(AVPOPCNTH, r0) 1342 opset(AVPOPCNTW, r0) 1343 opset(AVPOPCNTD, r0) 1344 1345 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1346 opset(AVCMPEQUB, r0) 1347 opset(AVCMPEQUBCC, r0) 1348 opset(AVCMPEQUH, r0) 1349 opset(AVCMPEQUHCC, r0) 1350 opset(AVCMPEQUW, r0) 1351 opset(AVCMPEQUWCC, r0) 1352 opset(AVCMPEQUD, r0) 1353 opset(AVCMPEQUDCC, r0) 1354 1355 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1356 opset(AVCMPGTUB, r0) 1357 opset(AVCMPGTUBCC, r0) 1358 opset(AVCMPGTUH, r0) 1359 opset(AVCMPGTUHCC, r0) 1360 opset(AVCMPGTUW, r0) 1361 opset(AVCMPGTUWCC, r0) 1362 opset(AVCMPGTUD, r0) 1363 opset(AVCMPGTUDCC, r0) 1364 opset(AVCMPGTSB, r0) 1365 opset(AVCMPGTSBCC, r0) 1366 opset(AVCMPGTSH, r0) 1367 opset(AVCMPGTSHCC, r0) 1368 opset(AVCMPGTSW, r0) 1369 opset(AVCMPGTSWCC, r0) 1370 opset(AVCMPGTSD, r0) 1371 opset(AVCMPGTSDCC, r0) 1372 1373 case AVCMPNEZB: /* vcmpnezb[.] */ 1374 opset(AVCMPNEZBCC, r0) 1375 1376 case AVPERM: /* vperm */ 1377 opset(AVPERM, r0) 1378 1379 case AVSEL: /* vsel */ 1380 opset(AVSEL, r0) 1381 1382 case AVSPLT: /* vspltb, vsplth, vspltw */ 1383 opset(AVSPLTB, r0) 1384 opset(AVSPLTH, r0) 1385 opset(AVSPLTW, r0) 1386 1387 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1388 opset(AVSPLTISB, r0) 1389 opset(AVSPLTISH, r0) 1390 opset(AVSPLTISW, r0) 1391 1392 case AVCIPH: /* vcipher, vcipherlast */ 1393 opset(AVCIPHER, r0) 1394 opset(AVCIPHERLAST, r0) 1395 1396 case AVNCIPH: /* vncipher, vncipherlast */ 1397 opset(AVNCIPHER, r0) 1398 opset(AVNCIPHERLAST, r0) 1399 1400 case AVSBOX: /* vsbox */ 1401 opset(AVSBOX, r0) 1402 1403 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1404 opset(AVSHASIGMAW, r0) 1405 opset(AVSHASIGMAD, r0) 1406 1407 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1408 opset(ALXVD2X, r0) 1409 opset(ALXVDSX, r0) 1410 opset(ALXVW4X, r0) 1411 1412 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1413 opset(ASTXVD2X, r0) 1414 opset(ASTXVW4X, r0) 1415 1416 case ALXS: /* lxsdx */ 1417 opset(ALXSDX, r0) 1418 1419 case ASTXS: /* stxsdx */ 1420 opset(ASTXSDX, r0) 1421 1422 case ALXSI: /* lxsiwax, lxsiwzx */ 1423 opset(ALXSIWAX, r0) 1424 opset(ALXSIWZX, r0) 1425 1426 case ASTXSI: /* stxsiwx */ 1427 opset(ASTXSIWX, r0) 1428 1429 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */ 1430 opset(AMFVSRD, r0) 1431 opset(AMFFPRD, r0) 1432 opset(AMFVRD, r0) 1433 opset(AMFVSRWZ, r0) 1434 opset(AMFVSRLD, r0) 1435 1436 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */ 1437 opset(AMTVSRD, r0) 1438 opset(AMTFPRD, r0) 1439 opset(AMTVRD, r0) 1440 opset(AMTVSRWA, r0) 1441 opset(AMTVSRWZ, r0) 1442 opset(AMTVSRDD, r0) 1443 opset(AMTVSRWS, r0) 1444 1445 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1446 opset(AXXLANDQ, r0) 1447 opset(AXXLANDC, r0) 1448 opset(AXXLEQV, r0) 1449 opset(AXXLNAND, r0) 1450 1451 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1452 opset(AXXLORC, r0) 1453 opset(AXXLNOR, r0) 1454 opset(AXXLORQ, r0) 1455 opset(AXXLXOR, r0) 1456 1457 case AXXSEL: /* xxsel */ 1458 opset(AXXSEL, r0) 1459 1460 case AXXMRG: /* xxmrghw, xxmrglw */ 1461 opset(AXXMRGHW, r0) 1462 opset(AXXMRGLW, r0) 1463 1464 case AXXSPLT: /* xxspltw */ 1465 opset(AXXSPLTW, r0) 1466 1467 case AXXPERM: /* xxpermdi */ 1468 opset(AXXPERMDI, r0) 1469 1470 case AXXSI: /* xxsldwi */ 1471 opset(AXXSLDWI, r0) 1472 1473 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1474 opset(AXSCVDPSP, r0) 1475 opset(AXSCVSPDP, r0) 1476 opset(AXSCVDPSPN, r0) 1477 opset(AXSCVSPDPN, r0) 1478 1479 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1480 opset(AXVCVDPSP, r0) 1481 opset(AXVCVSPDP, r0) 1482 1483 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1484 opset(AXSCVDPSXDS, r0) 1485 opset(AXSCVDPSXWS, r0) 1486 opset(AXSCVDPUXDS, r0) 1487 opset(AXSCVDPUXWS, r0) 1488 1489 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1490 opset(AXSCVSXDDP, r0) 1491 opset(AXSCVUXDDP, r0) 1492 opset(AXSCVSXDSP, r0) 1493 opset(AXSCVUXDSP, r0) 1494 1495 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1496 opset(AXVCVDPSXDS, r0) 1497 opset(AXVCVDPSXWS, r0) 1498 opset(AXVCVDPUXDS, r0) 1499 opset(AXVCVDPUXWS, r0) 1500 opset(AXVCVSPSXDS, r0) 1501 opset(AXVCVSPSXWS, r0) 1502 opset(AXVCVSPUXDS, r0) 1503 opset(AXVCVSPUXWS, r0) 1504 1505 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1506 opset(AXVCVSXDDP, r0) 1507 opset(AXVCVSXWDP, r0) 1508 opset(AXVCVUXDDP, r0) 1509 opset(AXVCVUXWDP, r0) 1510 opset(AXVCVSXDSP, r0) 1511 opset(AXVCVSXWSP, r0) 1512 opset(AXVCVUXDSP, r0) 1513 opset(AXVCVUXWSP, r0) 1514 1515 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1516 opset(AANDN, r0) 1517 1518 opset(AANDNCC, r0) 1519 opset(AEQV, r0) 1520 opset(AEQVCC, r0) 1521 opset(ANAND, r0) 1522 opset(ANANDCC, r0) 1523 opset(ANOR, r0) 1524 opset(ANORCC, r0) 1525 opset(AORCC, r0) 1526 opset(AORN, r0) 1527 opset(AORNCC, r0) 1528 opset(AXORCC, r0) 1529 1530 case AADDME: /* op Ra, Rd */ 1531 opset(AADDMECC, r0) 1532 1533 opset(AADDMEV, r0) 1534 opset(AADDMEVCC, r0) 1535 opset(AADDZE, r0) 1536 opset(AADDZECC, r0) 1537 opset(AADDZEV, r0) 1538 opset(AADDZEVCC, r0) 1539 opset(ASUBME, r0) 1540 opset(ASUBMECC, r0) 1541 opset(ASUBMEV, r0) 1542 opset(ASUBMEVCC, r0) 1543 opset(ASUBZE, r0) 1544 opset(ASUBZECC, r0) 1545 opset(ASUBZEV, r0) 1546 opset(ASUBZEVCC, r0) 1547 1548 case AADDC: 1549 opset(AADDCCC, r0) 1550 1551 case ABEQ: 1552 opset(ABGE, r0) 1553 opset(ABGT, r0) 1554 opset(ABLE, r0) 1555 opset(ABLT, r0) 1556 opset(ABNE, r0) 1557 opset(ABVC, r0) 1558 opset(ABVS, r0) 1559 1560 case ABR: 1561 opset(ABL, r0) 1562 1563 case ABC: 1564 opset(ABCL, r0) 1565 1566 case AEXTSB: /* op Rs, Ra */ 1567 opset(AEXTSBCC, r0) 1568 1569 opset(AEXTSH, r0) 1570 opset(AEXTSHCC, r0) 1571 opset(ACNTLZW, r0) 1572 opset(ACNTLZWCC, r0) 1573 opset(ACNTLZD, r0) 1574 opset(AEXTSW, r0) 1575 opset(AEXTSWCC, r0) 1576 opset(ACNTLZDCC, r0) 1577 1578 case AFABS: /* fop [s,]d */ 1579 opset(AFABSCC, r0) 1580 1581 opset(AFNABS, r0) 1582 opset(AFNABSCC, r0) 1583 opset(AFNEG, r0) 1584 opset(AFNEGCC, r0) 1585 opset(AFRSP, r0) 1586 opset(AFRSPCC, r0) 1587 opset(AFCTIW, r0) 1588 opset(AFCTIWCC, r0) 1589 opset(AFCTIWZ, r0) 1590 opset(AFCTIWZCC, r0) 1591 opset(AFCTID, r0) 1592 opset(AFCTIDCC, r0) 1593 opset(AFCTIDZ, r0) 1594 opset(AFCTIDZCC, r0) 1595 opset(AFCFID, r0) 1596 opset(AFCFIDCC, r0) 1597 opset(AFCFIDU, r0) 1598 opset(AFCFIDUCC, r0) 1599 opset(AFRES, r0) 1600 opset(AFRESCC, r0) 1601 opset(AFRIM, r0) 1602 opset(AFRIMCC, r0) 1603 opset(AFRIP, r0) 1604 opset(AFRIPCC, r0) 1605 opset(AFRIZ, r0) 1606 opset(AFRIZCC, r0) 1607 opset(AFRSQRTE, r0) 1608 opset(AFRSQRTECC, r0) 1609 opset(AFSQRT, r0) 1610 opset(AFSQRTCC, r0) 1611 opset(AFSQRTS, r0) 1612 opset(AFSQRTSCC, r0) 1613 1614 case AFADD: 1615 opset(AFADDS, r0) 1616 opset(AFADDCC, r0) 1617 opset(AFADDSCC, r0) 1618 opset(AFDIV, r0) 1619 opset(AFDIVS, r0) 1620 opset(AFDIVCC, r0) 1621 opset(AFDIVSCC, r0) 1622 opset(AFSUB, r0) 1623 opset(AFSUBS, r0) 1624 opset(AFSUBCC, r0) 1625 opset(AFSUBSCC, r0) 1626 1627 case AFMADD: 1628 opset(AFMADDCC, r0) 1629 opset(AFMADDS, r0) 1630 opset(AFMADDSCC, r0) 1631 opset(AFMSUB, r0) 1632 opset(AFMSUBCC, r0) 1633 opset(AFMSUBS, r0) 1634 opset(AFMSUBSCC, r0) 1635 opset(AFNMADD, r0) 1636 opset(AFNMADDCC, r0) 1637 opset(AFNMADDS, r0) 1638 opset(AFNMADDSCC, r0) 1639 opset(AFNMSUB, r0) 1640 opset(AFNMSUBCC, r0) 1641 opset(AFNMSUBS, r0) 1642 opset(AFNMSUBSCC, r0) 1643 opset(AFSEL, r0) 1644 opset(AFSELCC, r0) 1645 1646 case AFMUL: 1647 opset(AFMULS, r0) 1648 opset(AFMULCC, r0) 1649 opset(AFMULSCC, r0) 1650 1651 case AFCMPO: 1652 opset(AFCMPU, r0) 1653 1654 case AISEL: 1655 opset(AISEL, r0) 1656 1657 case AMTFSB0: 1658 opset(AMTFSB0CC, r0) 1659 opset(AMTFSB1, r0) 1660 opset(AMTFSB1CC, r0) 1661 1662 case ANEG: /* op [Ra,] Rd */ 1663 opset(ANEGCC, r0) 1664 1665 opset(ANEGV, r0) 1666 opset(ANEGVCC, r0) 1667 1668 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1669 opset(AXOR, r0) 1670 1671 case ASLW: 1672 opset(ASLWCC, r0) 1673 opset(ASRW, r0) 1674 opset(ASRWCC, r0) 1675 opset(AROTLW, r0) 1676 1677 case ASLD: 1678 opset(ASLDCC, r0) 1679 opset(ASRD, r0) 1680 opset(ASRDCC, r0) 1681 opset(AROTL, r0) 1682 1683 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1684 opset(ASRAWCC, r0) 1685 1686 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1687 opset(ASRADCC, r0) 1688 1689 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1690 opset(ASUB, r0) 1691 1692 opset(ASUBCC, r0) 1693 opset(ASUBV, r0) 1694 opset(ASUBVCC, r0) 1695 opset(ASUBCCC, r0) 1696 opset(ASUBCV, r0) 1697 opset(ASUBCVCC, r0) 1698 opset(ASUBE, r0) 1699 opset(ASUBECC, r0) 1700 opset(ASUBEV, r0) 1701 opset(ASUBEVCC, r0) 1702 1703 case ASYNC: 1704 opset(AISYNC, r0) 1705 opset(ALWSYNC, r0) 1706 opset(APTESYNC, r0) 1707 opset(ATLBSYNC, r0) 1708 1709 case ARLWMI: 1710 opset(ARLWMICC, r0) 1711 opset(ARLWNM, r0) 1712 opset(ARLWNMCC, r0) 1713 1714 case ARLDMI: 1715 opset(ARLDMICC, r0) 1716 opset(ARLDIMI, r0) 1717 opset(ARLDIMICC, r0) 1718 1719 case ARLDC: 1720 opset(ARLDCCC, r0) 1721 1722 case ARLDCL: 1723 opset(ARLDCR, r0) 1724 opset(ARLDCLCC, r0) 1725 opset(ARLDCRCC, r0) 1726 1727 case ARLDICL: 1728 opset(ARLDICLCC, r0) 1729 opset(ARLDICR, r0) 1730 opset(ARLDICRCC, r0) 1731 1732 case AFMOVD: 1733 opset(AFMOVDCC, r0) 1734 opset(AFMOVDU, r0) 1735 opset(AFMOVS, r0) 1736 opset(AFMOVSU, r0) 1737 1738 case AECIWX: 1739 opset(ALBAR, r0) 1740 opset(ALWAR, r0) 1741 opset(ALDAR, r0) 1742 1743 case ASYSCALL: /* just the op; flow of control */ 1744 opset(ARFI, r0) 1745 1746 opset(ARFCI, r0) 1747 opset(ARFID, r0) 1748 opset(AHRFID, r0) 1749 1750 case AMOVHBR: 1751 opset(AMOVWBR, r0) 1752 opset(AMOVDBR, r0) 1753 1754 case ASLBMFEE: 1755 opset(ASLBMFEV, r0) 1756 1757 case ATW: 1758 opset(ATD, r0) 1759 1760 case ATLBIE: 1761 opset(ASLBIE, r0) 1762 opset(ATLBIEL, r0) 1763 1764 case AEIEIO: 1765 opset(ASLBIA, r0) 1766 1767 case ACMP: 1768 opset(ACMPW, r0) 1769 1770 case ACMPU: 1771 opset(ACMPWU, r0) 1772 1773 case ACMPB: 1774 opset(ACMPB, r0) 1775 1776 case AFTDIV: 1777 opset(AFTDIV, r0) 1778 1779 case AFTSQRT: 1780 opset(AFTSQRT, r0) 1781 1782 case AADD, 1783 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1784 AFMOVSX, 1785 AFMOVSZ, 1786 ALSW, 1787 AMOVW, 1788 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1789 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1790 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1791 AMOVB, /* macro: move byte with sign extension */ 1792 AMOVBU, /* macro: move byte with sign extension & update */ 1793 AMOVFL, 1794 AMULLW, 1795 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1796 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1797 ASTSW, 1798 ASLBMTE, 1799 AWORD, 1800 ADWORD, 1801 ADARN, 1802 ALDMX, 1803 AVMSUMUDM, 1804 AADDEX, 1805 ACMPEQB, 1806 obj.ANOP, 1807 obj.ATEXT, 1808 obj.AUNDEF, 1809 obj.AFUNCDATA, 1810 obj.APCDATA, 1811 obj.ADUFFZERO, 1812 obj.ADUFFCOPY: 1813 break 1814 } 1815 } 1816 } 1817 1818 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1819 return o<<26 | xo<<1 | oe<<11 1820 } 1821 1822 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1823 return o<<26 | xo<<2 | oe<<11 1824 } 1825 1826 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1827 return o<<26 | xo<<3 | oe<<11 1828 } 1829 1830 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1831 return o<<26 | xo<<4 | oe<<11 1832 } 1833 1834 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1835 return o<<26 | xo | oe<<11 | rc&1 1836 } 1837 1838 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1839 return o<<26 | xo | oe<<11 | (rc&1)<<10 1840 } 1841 1842 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1843 return o<<26 | xo<<1 | oe<<10 | rc&1 1844 } 1845 1846 func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1847 return OPVCC(o, xo, 0, rc) 1848 } 1849 1850 func OP(o uint32, xo uint32) uint32 { 1851 return OPVCC(o, xo, 0, 0) 1852 } 1853 1854 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1855 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1856 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1857 } 1858 1859 /* VX-form 2-register operands, r/none/r */ 1860 func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1861 return op | (d&31)<<21 | (a&31)<<11 1862 } 1863 1864 /* VA-form 4-register operands */ 1865 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1866 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1867 } 1868 1869 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1870 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1871 } 1872 1873 /* VX-form 2-register + UIM operands */ 1874 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1875 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1876 } 1877 1878 /* VX-form 2-register + ST + SIX operands */ 1879 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1880 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1881 } 1882 1883 /* VA-form 3-register + SHB operands */ 1884 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1885 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1886 } 1887 1888 /* VX-form 1-register + SIM operands */ 1889 func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1890 return op | (d&31)<<21 | (simm&31)<<16 1891 } 1892 1893 /* XX1-form 3-register operands, 1 VSR operand */ 1894 func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1895 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1896 /* between 0-63, so we can properly set the rightmost bits. */ 1897 r := d - REG_VS0 1898 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1899 } 1900 1901 /* XX2-form 3-register operands, 2 VSR operands */ 1902 func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1903 xt := d - REG_VS0 1904 xb := b - REG_VS0 1905 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1906 } 1907 1908 /* XX3-form 3 VSR operands */ 1909 func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1910 xt := d - REG_VS0 1911 xa := a - REG_VS0 1912 xb := b - REG_VS0 1913 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1914 } 1915 1916 /* XX3-form 3 VSR operands + immediate */ 1917 func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1918 xt := d - REG_VS0 1919 xa := a - REG_VS0 1920 xb := b - REG_VS0 1921 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1922 } 1923 1924 /* XX4-form, 4 VSR operands */ 1925 func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1926 xt := d - REG_VS0 1927 xa := a - REG_VS0 1928 xb := b - REG_VS0 1929 xc := c - REG_VS0 1930 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1931 } 1932 1933 /* Z23-form, 3-register operands + CY field */ 1934 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1935 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7 1936 } 1937 1938 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1939 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1940 } 1941 1942 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1943 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1944 } 1945 1946 func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1947 return op | li&0x03FFFFFC | aa<<1 1948 } 1949 1950 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1951 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1952 } 1953 1954 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1955 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1956 } 1957 1958 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1959 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1960 } 1961 1962 func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1963 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1964 } 1965 1966 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1967 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1968 } 1969 1970 const ( 1971 /* each rhs is OPVCC(_, _, _, _) */ 1972 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1973 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1974 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1975 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1976 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1977 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1978 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1979 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1980 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1981 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1982 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1983 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1984 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1985 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1986 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1987 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1988 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1989 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1990 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1991 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1992 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1993 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1994 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1995 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1996 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1997 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1998 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1999 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 2000 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 2001 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 2002 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 2003 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 2004 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 2005 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 2006 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 2007 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 2008 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 2009 ) 2010 2011 func oclass(a *obj.Addr) int { 2012 return int(a.Class) - 1 2013 } 2014 2015 const ( 2016 D_FORM = iota 2017 DS_FORM 2018 ) 2019 2020 // This function determines when a non-indexed load or store is D or 2021 // DS form for use in finding the size of the offset field in the instruction. 2022 // The size is needed when setting the offset value in the instruction 2023 // and when generating relocation for that field. 2024 // DS form instructions include: ld, ldu, lwa, std, stdu. All other 2025 // loads and stores with an offset field are D form. This function should 2026 // only be called with the same opcodes as are handled by opstore and opload. 2027 func (c *ctxt9) opform(insn uint32) int { 2028 switch insn { 2029 default: 2030 c.ctxt.Diag("bad insn in loadform: %x", insn) 2031 case OPVCC(58, 0, 0, 0), // ld 2032 OPVCC(58, 0, 0, 1), // ldu 2033 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2034 OPVCC(62, 0, 0, 0), // std 2035 OPVCC(62, 0, 0, 1): //stdu 2036 return DS_FORM 2037 case OP_ADDI, // add 2038 OPVCC(32, 0, 0, 0), // lwz 2039 OPVCC(33, 0, 0, 0), // lwzu 2040 OPVCC(34, 0, 0, 0), // lbz 2041 OPVCC(35, 0, 0, 0), // lbzu 2042 OPVCC(40, 0, 0, 0), // lhz 2043 OPVCC(41, 0, 0, 0), // lhzu 2044 OPVCC(42, 0, 0, 0), // lha 2045 OPVCC(43, 0, 0, 0), // lhau 2046 OPVCC(46, 0, 0, 0), // lmw 2047 OPVCC(48, 0, 0, 0), // lfs 2048 OPVCC(49, 0, 0, 0), // lfsu 2049 OPVCC(50, 0, 0, 0), // lfd 2050 OPVCC(51, 0, 0, 0), // lfdu 2051 OPVCC(36, 0, 0, 0), // stw 2052 OPVCC(37, 0, 0, 0), // stwu 2053 OPVCC(38, 0, 0, 0), // stb 2054 OPVCC(39, 0, 0, 0), // stbu 2055 OPVCC(44, 0, 0, 0), // sth 2056 OPVCC(45, 0, 0, 0), // sthu 2057 OPVCC(47, 0, 0, 0), // stmw 2058 OPVCC(52, 0, 0, 0), // stfs 2059 OPVCC(53, 0, 0, 0), // stfsu 2060 OPVCC(54, 0, 0, 0), // stfd 2061 OPVCC(55, 0, 0, 0): // stfdu 2062 return D_FORM 2063 } 2064 return 0 2065 } 2066 2067 // Encode instructions and create relocation for accessing s+d according to the 2068 // instruction op with source or destination (as appropriate) register reg. 2069 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2070 var base uint32 2071 form := c.opform(op) 2072 if c.ctxt.Flag_shared { 2073 base = REG_R2 2074 } else { 2075 base = REG_R0 2076 } 2077 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2078 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2079 rel := obj.Addrel(c.cursym) 2080 rel.Off = int32(c.pc) 2081 rel.Siz = 8 2082 rel.Sym = s 2083 rel.Add = d 2084 if c.ctxt.Flag_shared { 2085 switch form { 2086 case D_FORM: 2087 rel.Type = objabi.R_ADDRPOWER_TOCREL 2088 case DS_FORM: 2089 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2090 } 2091 2092 } else { 2093 switch form { 2094 case D_FORM: 2095 rel.Type = objabi.R_ADDRPOWER 2096 case DS_FORM: 2097 rel.Type = objabi.R_ADDRPOWER_DS 2098 } 2099 } 2100 return 2101 } 2102 2103 /* 2104 * 32-bit masks 2105 */ 2106 func getmask(m []byte, v uint32) bool { 2107 m[1] = 0 2108 m[0] = m[1] 2109 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2110 if getmask(m, ^v) { 2111 i := int(m[0]) 2112 m[0] = m[1] + 1 2113 m[1] = byte(i - 1) 2114 return true 2115 } 2116 2117 return false 2118 } 2119 2120 for i := 0; i < 32; i++ { 2121 if v&(1<<uint(31-i)) != 0 { 2122 m[0] = byte(i) 2123 for { 2124 m[1] = byte(i) 2125 i++ 2126 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2127 break 2128 } 2129 } 2130 2131 for ; i < 32; i++ { 2132 if v&(1<<uint(31-i)) != 0 { 2133 return false 2134 } 2135 } 2136 return true 2137 } 2138 } 2139 2140 return false 2141 } 2142 2143 func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2144 if !getmask(m, v) { 2145 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2146 } 2147 } 2148 2149 /* 2150 * 64-bit masks (rldic etc) 2151 */ 2152 func getmask64(m []byte, v uint64) bool { 2153 m[1] = 0 2154 m[0] = m[1] 2155 for i := 0; i < 64; i++ { 2156 if v&(uint64(1)<<uint(63-i)) != 0 { 2157 m[0] = byte(i) 2158 for { 2159 m[1] = byte(i) 2160 i++ 2161 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2162 break 2163 } 2164 } 2165 2166 for ; i < 64; i++ { 2167 if v&(uint64(1)<<uint(63-i)) != 0 { 2168 return false 2169 } 2170 } 2171 return true 2172 } 2173 } 2174 2175 return false 2176 } 2177 2178 func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2179 if !getmask64(m, v) { 2180 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2181 } 2182 } 2183 2184 func loadu32(r int, d int64) uint32 { 2185 v := int32(d >> 16) 2186 if isuint32(uint64(d)) { 2187 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2188 } 2189 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2190 } 2191 2192 func high16adjusted(d int32) uint16 { 2193 if d&0x8000 != 0 { 2194 return uint16((d >> 16) + 1) 2195 } 2196 return uint16(d >> 16) 2197 } 2198 2199 func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2200 o1 := uint32(0) 2201 o2 := uint32(0) 2202 o3 := uint32(0) 2203 o4 := uint32(0) 2204 o5 := uint32(0) 2205 2206 //print("%v => case %d\n", p, o->type); 2207 switch o.type_ { 2208 default: 2209 c.ctxt.Diag("unknown type %d", o.type_) 2210 prasm(p) 2211 2212 case 0: /* pseudo ops */ 2213 break 2214 2215 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2216 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2217 v := c.regoff(&p.From) 2218 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2219 //nerrors--; 2220 c.ctxt.Diag("literal operation on R0\n%v", p) 2221 } 2222 2223 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2224 break 2225 } 2226 2227 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2228 2229 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2230 r := int(p.Reg) 2231 2232 if r == 0 { 2233 r = int(p.To.Reg) 2234 } 2235 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2236 2237 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2238 d := c.vregoff(&p.From) 2239 2240 v := int32(d) 2241 r := int(p.From.Reg) 2242 if r == 0 { 2243 r = int(o.param) 2244 } 2245 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2246 c.ctxt.Diag("literal operation on R0\n%v", p) 2247 } 2248 a := OP_ADDI 2249 if o.a1 == C_UCON { 2250 if d&0xffff != 0 { 2251 log.Fatalf("invalid handling of %v", p) 2252 } 2253 v >>= 16 2254 if r == REGZERO && isuint32(uint64(d)) { 2255 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2256 break 2257 } 2258 2259 a = OP_ADDIS 2260 } else { 2261 if int64(int16(d)) != d { 2262 log.Fatalf("invalid handling of %v", p) 2263 } 2264 } 2265 2266 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2267 2268 case 4: /* add/mul $scon,[r1],r2 */ 2269 v := c.regoff(&p.From) 2270 2271 r := int(p.Reg) 2272 if r == 0 { 2273 r = int(p.To.Reg) 2274 } 2275 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2276 c.ctxt.Diag("literal operation on R0\n%v", p) 2277 } 2278 if int32(int16(v)) != v { 2279 log.Fatalf("mishandled instruction %v", p) 2280 } 2281 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2282 2283 case 5: /* syscall */ 2284 o1 = c.oprrr(p.As) 2285 2286 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2287 r := int(p.Reg) 2288 2289 if r == 0 { 2290 r = int(p.To.Reg) 2291 } 2292 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2293 switch p.As { 2294 case AROTL: 2295 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2296 case AROTLW: 2297 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2298 default: 2299 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2300 } 2301 2302 case 7: /* mov r, soreg ==> stw o(r) */ 2303 r := int(p.To.Reg) 2304 2305 if r == 0 { 2306 r = int(o.param) 2307 } 2308 v := c.regoff(&p.To) 2309 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2310 if v != 0 { 2311 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2312 } 2313 if c.ctxt.Flag_shared && r == REG_R13 { 2314 rel := obj.Addrel(c.cursym) 2315 rel.Off = int32(c.pc) 2316 rel.Siz = 4 2317 // This (and the matching part in the load case 2318 // below) are the only places in the ppc64 toolchain 2319 // that knows the name of the tls variable. Possibly 2320 // we could add some assembly syntax so that the name 2321 // of the variable does not have to be assumed. 2322 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2323 rel.Type = objabi.R_POWER_TLS 2324 } 2325 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2326 } else { 2327 if int32(int16(v)) != v { 2328 log.Fatalf("mishandled instruction %v", p) 2329 } 2330 // Offsets in DS form stores must be a multiple of 4 2331 inst := c.opstore(p.As) 2332 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2333 log.Fatalf("invalid offset for DS form load/store %v", p) 2334 } 2335 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2336 } 2337 2338 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2339 r := int(p.From.Reg) 2340 2341 if r == 0 { 2342 r = int(o.param) 2343 } 2344 v := c.regoff(&p.From) 2345 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2346 if v != 0 { 2347 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2348 } 2349 if c.ctxt.Flag_shared && r == REG_R13 { 2350 rel := obj.Addrel(c.cursym) 2351 rel.Off = int32(c.pc) 2352 rel.Siz = 4 2353 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2354 rel.Type = objabi.R_POWER_TLS 2355 } 2356 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2357 } else { 2358 if int32(int16(v)) != v { 2359 log.Fatalf("mishandled instruction %v", p) 2360 } 2361 // Offsets in DS form loads must be a multiple of 4 2362 inst := c.opload(p.As) 2363 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2364 log.Fatalf("invalid offset for DS form load/store %v", p) 2365 } 2366 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2367 } 2368 2369 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2370 r := int(p.From.Reg) 2371 2372 if r == 0 { 2373 r = int(o.param) 2374 } 2375 v := c.regoff(&p.From) 2376 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2377 if v != 0 { 2378 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2379 } 2380 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2381 } else { 2382 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2383 } 2384 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2385 2386 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2387 r := int(p.Reg) 2388 2389 if r == 0 { 2390 r = int(p.To.Reg) 2391 } 2392 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2393 2394 case 11: /* br/bl lbra */ 2395 v := int32(0) 2396 2397 if p.Pcond != nil { 2398 v = int32(p.Pcond.Pc - p.Pc) 2399 if v&03 != 0 { 2400 c.ctxt.Diag("odd branch target address\n%v", p) 2401 v &^= 03 2402 } 2403 2404 if v < -(1<<25) || v >= 1<<24 { 2405 c.ctxt.Diag("branch too far\n%v", p) 2406 } 2407 } 2408 2409 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2410 if p.To.Sym != nil { 2411 rel := obj.Addrel(c.cursym) 2412 rel.Off = int32(c.pc) 2413 rel.Siz = 4 2414 rel.Sym = p.To.Sym 2415 v += int32(p.To.Offset) 2416 if v&03 != 0 { 2417 c.ctxt.Diag("odd branch target address\n%v", p) 2418 v &^= 03 2419 } 2420 2421 rel.Add = int64(v) 2422 rel.Type = objabi.R_CALLPOWER 2423 } 2424 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2425 2426 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2427 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2428 v := c.regoff(&p.From) 2429 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2430 c.ctxt.Diag("literal operation on R0\n%v", p) 2431 } 2432 2433 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2434 break 2435 } 2436 2437 if p.As == AMOVW { 2438 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2439 } else { 2440 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2441 } 2442 2443 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2444 if p.As == AMOVBZ { 2445 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2446 } else if p.As == AMOVH { 2447 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2448 } else if p.As == AMOVHZ { 2449 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2450 } else if p.As == AMOVWZ { 2451 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2452 } else { 2453 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2454 } 2455 2456 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2457 r := int(p.Reg) 2458 2459 if r == 0 { 2460 r = int(p.To.Reg) 2461 } 2462 d := c.vregoff(p.From3) 2463 var a int 2464 switch p.As { 2465 2466 // These opcodes expect a mask operand that has to be converted into the 2467 // appropriate operand. The way these were defined, not all valid masks are possible. 2468 // Left here for compatibility in case they were used or generated. 2469 case ARLDCL, ARLDCLCC: 2470 var mask [2]uint8 2471 c.maskgen64(p, mask[:], uint64(d)) 2472 2473 a = int(mask[0]) /* MB */ 2474 if mask[1] != 63 { 2475 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2476 } 2477 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2478 o1 |= (uint32(a) & 31) << 6 2479 if a&0x20 != 0 { 2480 o1 |= 1 << 5 /* mb[5] is top bit */ 2481 } 2482 2483 case ARLDCR, ARLDCRCC: 2484 var mask [2]uint8 2485 c.maskgen64(p, mask[:], uint64(d)) 2486 2487 a = int(mask[1]) /* ME */ 2488 if mask[0] != 0 { 2489 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2490 } 2491 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2492 o1 |= (uint32(a) & 31) << 6 2493 if a&0x20 != 0 { 2494 o1 |= 1 << 5 /* mb[5] is top bit */ 2495 } 2496 2497 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2498 case ARLDICR, ARLDICRCC: 2499 me := int(d) 2500 sh := c.regoff(&p.From) 2501 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2502 2503 case ARLDICL, ARLDICLCC: 2504 mb := int(d) 2505 sh := c.regoff(&p.From) 2506 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2507 2508 default: 2509 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2510 a = 0 2511 } 2512 2513 case 17, /* bc bo,bi,lbra (same for now) */ 2514 16: /* bc bo,bi,sbra */ 2515 a := 0 2516 2517 r := int(p.Reg) 2518 2519 if p.From.Type == obj.TYPE_CONST { 2520 a = int(c.regoff(&p.From)) 2521 } else if p.From.Type == obj.TYPE_REG { 2522 if r != 0 { 2523 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2524 } 2525 // BI values for the CR 2526 switch p.From.Reg { 2527 case REG_CR0: 2528 r = BI_CR0 2529 case REG_CR1: 2530 r = BI_CR1 2531 case REG_CR2: 2532 r = BI_CR2 2533 case REG_CR3: 2534 r = BI_CR3 2535 case REG_CR4: 2536 r = BI_CR4 2537 case REG_CR5: 2538 r = BI_CR5 2539 case REG_CR6: 2540 r = BI_CR6 2541 case REG_CR7: 2542 r = BI_CR7 2543 default: 2544 c.ctxt.Diag("unrecognized register: expecting CR\n") 2545 } 2546 } 2547 v := int32(0) 2548 if p.Pcond != nil { 2549 v = int32(p.Pcond.Pc - p.Pc) 2550 } 2551 if v&03 != 0 { 2552 c.ctxt.Diag("odd branch target address\n%v", p) 2553 v &^= 03 2554 } 2555 2556 if v < -(1<<16) || v >= 1<<15 { 2557 c.ctxt.Diag("branch too far\n%v", p) 2558 } 2559 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2560 2561 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2562 var v int32 2563 if p.As == ABC || p.As == ABCL { 2564 v = c.regoff(&p.To) & 31 2565 } else { 2566 v = 20 /* unconditional */ 2567 } 2568 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2569 o2 = OPVCC(19, 16, 0, 0) 2570 if p.As == ABL || p.As == ABCL { 2571 o2 |= 1 2572 } 2573 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2574 2575 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2576 var v int32 2577 if p.As == ABC || p.As == ABCL { 2578 v = c.regoff(&p.From) & 31 2579 } else { 2580 v = 20 /* unconditional */ 2581 } 2582 r := int(p.Reg) 2583 if r == 0 { 2584 r = 0 2585 } 2586 switch oclass(&p.To) { 2587 case C_CTR: 2588 o1 = OPVCC(19, 528, 0, 0) 2589 2590 case C_LR: 2591 o1 = OPVCC(19, 16, 0, 0) 2592 2593 default: 2594 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2595 v = 0 2596 } 2597 2598 if p.As == ABL || p.As == ABCL { 2599 o1 |= 1 2600 } 2601 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2602 2603 case 19: /* mov $lcon,r ==> cau+or */ 2604 d := c.vregoff(&p.From) 2605 2606 if p.From.Sym == nil { 2607 o1 = loadu32(int(p.To.Reg), d) 2608 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2609 } else { 2610 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2611 } 2612 2613 //if(dlm) reloc(&p->from, p->pc, 0); 2614 2615 case 20: /* add $ucon,,r */ 2616 v := c.regoff(&p.From) 2617 2618 r := int(p.Reg) 2619 if r == 0 { 2620 r = int(p.To.Reg) 2621 } 2622 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2623 c.ctxt.Diag("literal operation on R0\n%v", p) 2624 } 2625 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2626 2627 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2628 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2629 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2630 } 2631 d := c.vregoff(&p.From) 2632 o1 = loadu32(REGTMP, d) 2633 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2634 r := int(p.Reg) 2635 if r == 0 { 2636 r = int(p.To.Reg) 2637 } 2638 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2639 if p.From.Sym != nil { 2640 c.ctxt.Diag("%v is not supported", p) 2641 } 2642 2643 //if(dlm) reloc(&p->from, p->pc, 0); 2644 2645 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2646 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2647 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2648 } 2649 d := c.vregoff(&p.From) 2650 o1 = loadu32(REGTMP, d) 2651 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2652 r := int(p.Reg) 2653 if r == 0 { 2654 r = int(p.To.Reg) 2655 } 2656 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2657 if p.From.Sym != nil { 2658 c.ctxt.Diag("%v is not supported", p) 2659 } 2660 2661 //if(dlm) reloc(&p->from, p->pc, 0); 2662 2663 /*24*/ 2664 case 25: 2665 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2666 v := c.regoff(&p.From) 2667 2668 if v < 0 { 2669 v = 0 2670 } else if v > 63 { 2671 v = 63 2672 } 2673 r := int(p.Reg) 2674 if r == 0 { 2675 r = int(p.To.Reg) 2676 } 2677 var a int 2678 op := uint32(0) 2679 switch p.As { 2680 case ASLD, ASLDCC: 2681 a = int(63 - v) 2682 op = OP_RLDICR 2683 2684 case ASRD, ASRDCC: 2685 a = int(v) 2686 v = 64 - v 2687 op = OP_RLDICL 2688 case AROTL: 2689 a = int(0) 2690 op = OP_RLDICL 2691 default: 2692 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2693 a = 0 2694 o1 = 0 2695 } 2696 2697 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2698 if p.As == ASLDCC || p.As == ASRDCC { 2699 o1 |= 1 // Set the condition code bit 2700 } 2701 2702 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2703 if p.To.Reg == REGTMP { 2704 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2705 } 2706 v := c.regoff(&p.From) 2707 r := int(p.From.Reg) 2708 if r == 0 { 2709 r = int(o.param) 2710 } 2711 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2712 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2713 2714 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2715 v := c.regoff(p.From3) 2716 2717 r := int(p.From.Reg) 2718 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2719 2720 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2721 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2722 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2723 } 2724 v := c.regoff(p.From3) 2725 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2726 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2727 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2728 if p.From.Sym != nil { 2729 c.ctxt.Diag("%v is not supported", p) 2730 } 2731 2732 //if(dlm) reloc(&p->from3, p->pc, 0); 2733 2734 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2735 v := c.regoff(&p.From) 2736 2737 d := c.vregoff(p.From3) 2738 var mask [2]uint8 2739 c.maskgen64(p, mask[:], uint64(d)) 2740 var a int 2741 switch p.As { 2742 case ARLDC, ARLDCCC: 2743 a = int(mask[0]) /* MB */ 2744 if int32(mask[1]) != (63 - v) { 2745 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2746 } 2747 2748 case ARLDCL, ARLDCLCC: 2749 a = int(mask[0]) /* MB */ 2750 if mask[1] != 63 { 2751 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2752 } 2753 2754 case ARLDCR, ARLDCRCC: 2755 a = int(mask[1]) /* ME */ 2756 if mask[0] != 0 { 2757 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2758 } 2759 2760 default: 2761 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2762 a = 0 2763 } 2764 2765 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2766 o1 |= (uint32(a) & 31) << 6 2767 if v&0x20 != 0 { 2768 o1 |= 1 << 1 2769 } 2770 if a&0x20 != 0 { 2771 o1 |= 1 << 5 /* mb[5] is top bit */ 2772 } 2773 2774 case 30: /* rldimi $sh,s,$mask,a */ 2775 v := c.regoff(&p.From) 2776 2777 d := c.vregoff(p.From3) 2778 2779 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2780 // the ppc64 asm. 2781 switch p.As { 2782 case ARLDMI, ARLDMICC: 2783 var mask [2]uint8 2784 c.maskgen64(p, mask[:], uint64(d)) 2785 if int32(mask[1]) != (63 - v) { 2786 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2787 } 2788 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2789 o1 |= (uint32(mask[0]) & 31) << 6 2790 if v&0x20 != 0 { 2791 o1 |= 1 << 1 2792 } 2793 if mask[0]&0x20 != 0 { 2794 o1 |= 1 << 5 /* mb[5] is top bit */ 2795 } 2796 2797 // Opcodes with shift count operands. 2798 case ARLDIMI, ARLDIMICC: 2799 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2800 o1 |= (uint32(d) & 31) << 6 2801 if d&0x20 != 0 { 2802 o1 |= 1 << 5 2803 } 2804 if v&0x20 != 0 { 2805 o1 |= 1 << 1 2806 } 2807 } 2808 2809 case 31: /* dword */ 2810 d := c.vregoff(&p.From) 2811 2812 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2813 o1 = uint32(d >> 32) 2814 o2 = uint32(d) 2815 } else { 2816 o1 = uint32(d) 2817 o2 = uint32(d >> 32) 2818 } 2819 2820 if p.From.Sym != nil { 2821 rel := obj.Addrel(c.cursym) 2822 rel.Off = int32(c.pc) 2823 rel.Siz = 8 2824 rel.Sym = p.From.Sym 2825 rel.Add = p.From.Offset 2826 rel.Type = objabi.R_ADDR 2827 o2 = 0 2828 o1 = o2 2829 } 2830 2831 case 32: /* fmul frc,fra,frd */ 2832 r := int(p.Reg) 2833 2834 if r == 0 { 2835 r = int(p.To.Reg) 2836 } 2837 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2838 2839 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2840 r := int(p.From.Reg) 2841 2842 if oclass(&p.From) == C_NONE { 2843 r = int(p.To.Reg) 2844 } 2845 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2846 2847 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2848 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2849 2850 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2851 v := c.regoff(&p.To) 2852 2853 r := int(p.To.Reg) 2854 if r == 0 { 2855 r = int(o.param) 2856 } 2857 // Offsets in DS form stores must be a multiple of 4 2858 inst := c.opstore(p.As) 2859 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2860 log.Fatalf("invalid offset for DS form load/store %v", p) 2861 } 2862 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2863 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2864 2865 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2866 v := c.regoff(&p.From) 2867 2868 r := int(p.From.Reg) 2869 if r == 0 { 2870 r = int(o.param) 2871 } 2872 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2873 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2874 2875 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2876 v := c.regoff(&p.From) 2877 2878 r := int(p.From.Reg) 2879 if r == 0 { 2880 r = int(o.param) 2881 } 2882 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2883 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2884 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2885 2886 case 40: /* word */ 2887 o1 = uint32(c.regoff(&p.From)) 2888 2889 case 41: /* stswi */ 2890 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2891 2892 case 42: /* lswi */ 2893 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2894 2895 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2896 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2897 2898 case 44: /* indexed store */ 2899 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2900 2901 case 45: /* indexed load */ 2902 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2903 2904 case 46: /* plain op */ 2905 o1 = c.oprrr(p.As) 2906 2907 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2908 r := int(p.From.Reg) 2909 2910 if r == 0 { 2911 r = int(p.To.Reg) 2912 } 2913 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2914 2915 case 48: /* op Rs, Ra */ 2916 r := int(p.From.Reg) 2917 2918 if r == 0 { 2919 r = int(p.To.Reg) 2920 } 2921 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2922 2923 case 49: /* op Rb; op $n, Rb */ 2924 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2925 v := c.regoff(&p.From) & 1 2926 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2927 } else { 2928 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2929 } 2930 2931 case 50: /* rem[u] r1[,r2],r3 */ 2932 r := int(p.Reg) 2933 2934 if r == 0 { 2935 r = int(p.To.Reg) 2936 } 2937 v := c.oprrr(p.As) 2938 t := v & (1<<10 | 1) /* OE|Rc */ 2939 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2940 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2941 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2942 if p.As == AREMU { 2943 o4 = o3 2944 2945 /* Clear top 32 bits */ 2946 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2947 } 2948 2949 case 51: /* remd[u] r1[,r2],r3 */ 2950 r := int(p.Reg) 2951 2952 if r == 0 { 2953 r = int(p.To.Reg) 2954 } 2955 v := c.oprrr(p.As) 2956 t := v & (1<<10 | 1) /* OE|Rc */ 2957 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2958 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2959 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2960 2961 case 52: /* mtfsbNx cr(n) */ 2962 v := c.regoff(&p.From) & 31 2963 2964 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2965 2966 case 53: /* mffsX ,fr1 */ 2967 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2968 2969 case 54: /* mov msr,r1; mov r1, msr*/ 2970 if oclass(&p.From) == C_REG { 2971 if p.As == AMOVD { 2972 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2973 } else { 2974 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2975 } 2976 } else { 2977 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2978 } 2979 2980 case 55: /* op Rb, Rd */ 2981 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2982 2983 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2984 v := c.regoff(&p.From) 2985 2986 r := int(p.Reg) 2987 if r == 0 { 2988 r = int(p.To.Reg) 2989 } 2990 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2991 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2992 o1 |= 1 << 1 /* mb[5] */ 2993 } 2994 2995 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2996 v := c.regoff(&p.From) 2997 2998 r := int(p.Reg) 2999 if r == 0 { 3000 r = int(p.To.Reg) 3001 } 3002 3003 /* 3004 * Let user (gs) shoot himself in the foot. 3005 * qc has already complained. 3006 * 3007 if(v < 0 || v > 31) 3008 ctxt->diag("illegal shift %ld\n%v", v, p); 3009 */ 3010 if v < 0 { 3011 v = 0 3012 } else if v > 32 { 3013 v = 32 3014 } 3015 var mask [2]uint8 3016 switch p.As { 3017 case AROTLW: 3018 mask[0], mask[1] = 0, 31 3019 case ASRW, ASRWCC: 3020 mask[0], mask[1] = uint8(v), 31 3021 v = 32 - v 3022 default: 3023 mask[0], mask[1] = 0, uint8(31-v) 3024 } 3025 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3026 if p.As == ASLWCC || p.As == ASRWCC { 3027 o1 |= 1 // set the condition code 3028 } 3029 3030 case 58: /* logical $andcon,[s],a */ 3031 v := c.regoff(&p.From) 3032 3033 r := int(p.Reg) 3034 if r == 0 { 3035 r = int(p.To.Reg) 3036 } 3037 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3038 3039 case 59: /* or/and $ucon,,r */ 3040 v := c.regoff(&p.From) 3041 3042 r := int(p.Reg) 3043 if r == 0 { 3044 r = int(p.To.Reg) 3045 } 3046 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3047 3048 case 60: /* tw to,a,b */ 3049 r := int(c.regoff(&p.From) & 31) 3050 3051 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3052 3053 case 61: /* tw to,a,$simm */ 3054 r := int(c.regoff(&p.From) & 31) 3055 3056 v := c.regoff(&p.To) 3057 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3058 3059 case 62: /* rlwmi $sh,s,$mask,a */ 3060 v := c.regoff(&p.From) 3061 3062 var mask [2]uint8 3063 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3064 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3065 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3066 3067 case 63: /* rlwmi b,s,$mask,a */ 3068 var mask [2]uint8 3069 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3070 3071 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3072 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3073 3074 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3075 var v int32 3076 if p.From3Type() != obj.TYPE_NONE { 3077 v = c.regoff(p.From3) & 255 3078 } else { 3079 v = 255 3080 } 3081 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3082 3083 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3084 if p.To.Reg == 0 { 3085 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3086 } 3087 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3088 3089 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3090 var r int 3091 var v int32 3092 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3093 r = int(p.From.Reg) 3094 v = int32(p.To.Reg) 3095 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3096 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3097 } else { 3098 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3099 } 3100 } else { 3101 r = int(p.To.Reg) 3102 v = int32(p.From.Reg) 3103 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3104 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3105 } else { 3106 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3107 } 3108 } 3109 3110 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3111 3112 case 67: /* mcrf crfD,crfS */ 3113 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3114 c.ctxt.Diag("illegal CR field number\n%v", p) 3115 } 3116 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3117 3118 case 68: /* mfcr rD; mfocrf CRM,rD */ 3119 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3120 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3121 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3122 } else { 3123 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3124 } 3125 3126 case 69: /* mtcrf CRM,rS */ 3127 var v int32 3128 if p.From3Type() != obj.TYPE_NONE { 3129 if p.To.Reg != 0 { 3130 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3131 } 3132 v = c.regoff(p.From3) & 0xff 3133 } else { 3134 if p.To.Reg == 0 { 3135 v = 0xff /* CR */ 3136 } else { 3137 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3138 } 3139 } 3140 3141 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3142 3143 case 70: /* [f]cmp r,r,cr*/ 3144 var r int 3145 if p.Reg == 0 { 3146 r = 0 3147 } else { 3148 r = (int(p.Reg) & 7) << 2 3149 } 3150 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3151 3152 case 71: /* cmp[l] r,i,cr*/ 3153 var r int 3154 if p.Reg == 0 { 3155 r = 0 3156 } else { 3157 r = (int(p.Reg) & 7) << 2 3158 } 3159 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3160 3161 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3162 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3163 3164 case 73: /* mcrfs crfD,crfS */ 3165 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3166 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3167 } 3168 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3169 3170 case 77: /* syscall $scon, syscall Rx */ 3171 if p.From.Type == obj.TYPE_CONST { 3172 if p.From.Offset > BIG || p.From.Offset < -BIG { 3173 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3174 } 3175 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3176 } else if p.From.Type == obj.TYPE_REG { 3177 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3178 } else { 3179 c.ctxt.Diag("illegal syscall: %v", p) 3180 o1 = 0x7fe00008 // trap always 3181 } 3182 3183 o2 = c.oprrr(p.As) 3184 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3185 3186 case 78: /* undef */ 3187 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3188 always to be an illegal instruction." */ 3189 3190 /* relocation operations */ 3191 case 74: 3192 v := c.vregoff(&p.To) 3193 // Offsets in DS form stores must be a multiple of 4 3194 inst := c.opstore(p.As) 3195 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3196 log.Fatalf("invalid offset for DS form load/store %v", p) 3197 } 3198 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3199 3200 //if(dlm) reloc(&p->to, p->pc, 1); 3201 3202 case 75: 3203 v := c.vregoff(&p.From) 3204 // Offsets in DS form loads must be a multiple of 4 3205 inst := c.opload(p.As) 3206 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3207 log.Fatalf("invalid offset for DS form load/store %v", p) 3208 } 3209 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3210 3211 //if(dlm) reloc(&p->from, p->pc, 1); 3212 3213 case 76: 3214 v := c.vregoff(&p.From) 3215 // Offsets in DS form loads must be a multiple of 4 3216 inst := c.opload(p.As) 3217 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3218 log.Fatalf("invalid offset for DS form load/store %v", p) 3219 } 3220 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3221 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3222 3223 //if(dlm) reloc(&p->from, p->pc, 1); 3224 3225 case 79: 3226 if p.From.Offset != 0 { 3227 c.ctxt.Diag("invalid offset against tls var %v", p) 3228 } 3229 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3230 rel := obj.Addrel(c.cursym) 3231 rel.Off = int32(c.pc) 3232 rel.Siz = 4 3233 rel.Sym = p.From.Sym 3234 rel.Type = objabi.R_POWER_TLS_LE 3235 3236 case 80: 3237 if p.From.Offset != 0 { 3238 c.ctxt.Diag("invalid offset against tls var %v", p) 3239 } 3240 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3241 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3242 rel := obj.Addrel(c.cursym) 3243 rel.Off = int32(c.pc) 3244 rel.Siz = 8 3245 rel.Sym = p.From.Sym 3246 rel.Type = objabi.R_POWER_TLS_IE 3247 3248 case 81: 3249 v := c.vregoff(&p.To) 3250 if v != 0 { 3251 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3252 } 3253 3254 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3255 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3256 rel := obj.Addrel(c.cursym) 3257 rel.Off = int32(c.pc) 3258 rel.Siz = 8 3259 rel.Sym = p.From.Sym 3260 rel.Type = objabi.R_ADDRPOWER_GOT 3261 case 82: /* vector instructions, VX-form and VC-form */ 3262 if p.From.Type == obj.TYPE_REG { 3263 /* reg reg none OR reg reg reg */ 3264 /* 3-register operand order: VRA, VRB, VRT */ 3265 /* 2-register operand order: VRA, VRT */ 3266 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3267 } else if p.From3Type() == obj.TYPE_CONST { 3268 /* imm imm reg reg */ 3269 /* operand order: SIX, VRA, ST, VRT */ 3270 six := int(c.regoff(&p.From)) 3271 st := int(c.regoff(p.From3)) 3272 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3273 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3274 /* imm reg reg */ 3275 /* operand order: UIM, VRB, VRT */ 3276 uim := int(c.regoff(&p.From)) 3277 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3278 } else { 3279 /* imm reg */ 3280 /* operand order: SIM, VRT */ 3281 sim := int(c.regoff(&p.From)) 3282 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3283 } 3284 3285 case 83: /* vector instructions, VA-form */ 3286 if p.From.Type == obj.TYPE_REG { 3287 /* reg reg reg reg */ 3288 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3289 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3290 } else if p.From.Type == obj.TYPE_CONST { 3291 /* imm reg reg reg */ 3292 /* operand order: SHB, VRA, VRB, VRT */ 3293 shb := int(c.regoff(&p.From)) 3294 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3295 } 3296 3297 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3298 bc := c.vregoff(&p.From) 3299 3300 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3301 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3302 3303 case 85: /* vector instructions, VX-form */ 3304 /* reg none reg */ 3305 /* 2-register operand order: VRB, VRT */ 3306 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3307 3308 case 86: /* VSX indexed store, XX1-form */ 3309 /* reg reg reg */ 3310 /* 3-register operand order: XT, (RB)(RA*1) */ 3311 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3312 3313 case 87: /* VSX indexed load, XX1-form */ 3314 /* reg reg reg */ 3315 /* 3-register operand order: (RB)(RA*1), XT */ 3316 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3317 3318 case 88: /* VSX instructions, XX1-form */ 3319 /* reg reg none OR reg reg reg */ 3320 /* 3-register operand order: RA, RB, XT */ 3321 /* 2-register operand order: XS, RA or RA, XT */ 3322 xt := int32(p.To.Reg) 3323 xs := int32(p.From.Reg) 3324 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3325 if REG_V0 <= xt && xt <= REG_V31 { 3326 /* Convert V0-V31 to VS32-VS63 */ 3327 xt = xt + 64 3328 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3329 } else if REG_F0 <= xt && xt <= REG_F31 { 3330 /* Convert F0-F31 to VS0-VS31 */ 3331 xt = xt + 64 3332 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3333 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3334 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3335 } else if REG_V0 <= xs && xs <= REG_V31 { 3336 /* Likewise for XS */ 3337 xs = xs + 64 3338 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3339 } else if REG_F0 <= xs && xs <= REG_F31 { 3340 xs = xs + 64 3341 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3342 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3343 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3344 } 3345 3346 case 89: /* VSX instructions, XX2-form */ 3347 /* reg none reg OR reg imm reg */ 3348 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3349 uim := int(c.regoff(p.From3)) 3350 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3351 3352 case 90: /* VSX instructions, XX3-form */ 3353 if p.From3Type() == obj.TYPE_NONE { 3354 /* reg reg reg */ 3355 /* 3-register operand order: XA, XB, XT */ 3356 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3357 } else if p.From3Type() == obj.TYPE_CONST { 3358 /* reg reg reg imm */ 3359 /* operand order: XA, XB, DM, XT */ 3360 dm := int(c.regoff(p.From3)) 3361 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3362 } 3363 3364 case 91: /* VSX instructions, XX4-form */ 3365 /* reg reg reg reg */ 3366 /* 3-register operand order: XA, XB, XC, XT */ 3367 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3368 3369 case 92: /* X-form instructions, 3-operands */ 3370 if p.To.Type == obj.TYPE_CONST { 3371 /* imm reg reg */ 3372 xf := int32(p.From.Reg) 3373 if REG_F0 <= xf && xf <= REG_F31 { 3374 /* operand order: FRA, FRB, BF */ 3375 bf := int(c.regoff(&p.To)) << 2 3376 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3377 } else { 3378 /* operand order: RA, RB, L */ 3379 l := int(c.regoff(&p.To)) 3380 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg)) 3381 } 3382 } else if p.From3Type() == obj.TYPE_CONST { 3383 /* reg reg imm */ 3384 /* operand order: RB, L, RA */ 3385 l := int(c.regoff(p.From3)) 3386 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg)) 3387 } else if p.To.Type == obj.TYPE_REG { 3388 cr := int32(p.To.Reg) 3389 if REG_CR0 <= cr && cr <= REG_CR7 { 3390 /* cr reg reg */ 3391 /* operand order: RA, RB, BF */ 3392 bf := (int(p.To.Reg) & 7) << 2 3393 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3394 } else if p.From.Type == obj.TYPE_CONST { 3395 /* reg imm */ 3396 /* operand order: L, RT */ 3397 l := int(c.regoff(&p.From)) 3398 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg)) 3399 } else { 3400 switch p.As { 3401 case ACOPY, APASTECC: 3402 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg)) 3403 default: 3404 /* reg reg reg */ 3405 /* operand order: RS, RB, RA */ 3406 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3407 } 3408 } 3409 } 3410 3411 case 93: /* X-form instructions, 2-operands */ 3412 if p.To.Type == obj.TYPE_CONST { 3413 /* imm reg */ 3414 /* operand order: FRB, BF */ 3415 bf := int(c.regoff(&p.To)) << 2 3416 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3417 } else if p.Reg == 0 { 3418 /* popcnt* r,r, X-form */ 3419 /* operand order: RS, RA */ 3420 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3421 } 3422 3423 case 94: /* Z23-form instructions, 4-operands */ 3424 /* reg reg reg imm */ 3425 /* operand order: RA, RB, CY, RT */ 3426 cy := int(c.regoff(p.From3)) 3427 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy)) 3428 } 3429 3430 out[0] = o1 3431 out[1] = o2 3432 out[2] = o3 3433 out[3] = o4 3434 out[4] = o5 3435 return 3436 } 3437 3438 func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3439 c.instoffset = 0 3440 if a != nil { 3441 c.aclass(a) 3442 } 3443 return c.instoffset 3444 } 3445 3446 func (c *ctxt9) regoff(a *obj.Addr) int32 { 3447 return int32(c.vregoff(a)) 3448 } 3449 3450 func (c *ctxt9) oprrr(a obj.As) uint32 { 3451 switch a { 3452 case AADD: 3453 return OPVCC(31, 266, 0, 0) 3454 case AADDCC: 3455 return OPVCC(31, 266, 0, 1) 3456 case AADDV: 3457 return OPVCC(31, 266, 1, 0) 3458 case AADDVCC: 3459 return OPVCC(31, 266, 1, 1) 3460 case AADDC: 3461 return OPVCC(31, 10, 0, 0) 3462 case AADDCCC: 3463 return OPVCC(31, 10, 0, 1) 3464 case AADDCV: 3465 return OPVCC(31, 10, 1, 0) 3466 case AADDCVCC: 3467 return OPVCC(31, 10, 1, 1) 3468 case AADDE: 3469 return OPVCC(31, 138, 0, 0) 3470 case AADDECC: 3471 return OPVCC(31, 138, 0, 1) 3472 case AADDEV: 3473 return OPVCC(31, 138, 1, 0) 3474 case AADDEVCC: 3475 return OPVCC(31, 138, 1, 1) 3476 case AADDME: 3477 return OPVCC(31, 234, 0, 0) 3478 case AADDMECC: 3479 return OPVCC(31, 234, 0, 1) 3480 case AADDMEV: 3481 return OPVCC(31, 234, 1, 0) 3482 case AADDMEVCC: 3483 return OPVCC(31, 234, 1, 1) 3484 case AADDZE: 3485 return OPVCC(31, 202, 0, 0) 3486 case AADDZECC: 3487 return OPVCC(31, 202, 0, 1) 3488 case AADDZEV: 3489 return OPVCC(31, 202, 1, 0) 3490 case AADDZEVCC: 3491 return OPVCC(31, 202, 1, 1) 3492 case AADDEX: 3493 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */ 3494 3495 case AAND: 3496 return OPVCC(31, 28, 0, 0) 3497 case AANDCC: 3498 return OPVCC(31, 28, 0, 1) 3499 case AANDN: 3500 return OPVCC(31, 60, 0, 0) 3501 case AANDNCC: 3502 return OPVCC(31, 60, 0, 1) 3503 3504 case ACMP: 3505 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3506 case ACMPU: 3507 return OPVCC(31, 32, 0, 0) | 1<<21 3508 case ACMPW: 3509 return OPVCC(31, 0, 0, 0) /* L=0 */ 3510 case ACMPWU: 3511 return OPVCC(31, 32, 0, 0) 3512 case ACMPB: 3513 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3514 3515 case ACNTLZW: 3516 return OPVCC(31, 26, 0, 0) 3517 case ACNTLZWCC: 3518 return OPVCC(31, 26, 0, 1) 3519 case ACNTLZD: 3520 return OPVCC(31, 58, 0, 0) 3521 case ACNTLZDCC: 3522 return OPVCC(31, 58, 0, 1) 3523 3524 case ACRAND: 3525 return OPVCC(19, 257, 0, 0) 3526 case ACRANDN: 3527 return OPVCC(19, 129, 0, 0) 3528 case ACREQV: 3529 return OPVCC(19, 289, 0, 0) 3530 case ACRNAND: 3531 return OPVCC(19, 225, 0, 0) 3532 case ACRNOR: 3533 return OPVCC(19, 33, 0, 0) 3534 case ACROR: 3535 return OPVCC(19, 449, 0, 0) 3536 case ACRORN: 3537 return OPVCC(19, 417, 0, 0) 3538 case ACRXOR: 3539 return OPVCC(19, 193, 0, 0) 3540 3541 case ADCBF: 3542 return OPVCC(31, 86, 0, 0) 3543 case ADCBI: 3544 return OPVCC(31, 470, 0, 0) 3545 case ADCBST: 3546 return OPVCC(31, 54, 0, 0) 3547 case ADCBT: 3548 return OPVCC(31, 278, 0, 0) 3549 case ADCBTST: 3550 return OPVCC(31, 246, 0, 0) 3551 case ADCBZ: 3552 return OPVCC(31, 1014, 0, 0) 3553 3554 case AREM, ADIVW: 3555 return OPVCC(31, 491, 0, 0) 3556 3557 case AREMCC, ADIVWCC: 3558 return OPVCC(31, 491, 0, 1) 3559 3560 case AREMV, ADIVWV: 3561 return OPVCC(31, 491, 1, 0) 3562 3563 case AREMVCC, ADIVWVCC: 3564 return OPVCC(31, 491, 1, 1) 3565 3566 case AREMU, ADIVWU: 3567 return OPVCC(31, 459, 0, 0) 3568 3569 case AREMUCC, ADIVWUCC: 3570 return OPVCC(31, 459, 0, 1) 3571 3572 case AREMUV, ADIVWUV: 3573 return OPVCC(31, 459, 1, 0) 3574 3575 case AREMUVCC, ADIVWUVCC: 3576 return OPVCC(31, 459, 1, 1) 3577 3578 case AREMD, ADIVD: 3579 return OPVCC(31, 489, 0, 0) 3580 3581 case AREMDCC, ADIVDCC: 3582 return OPVCC(31, 489, 0, 1) 3583 3584 case ADIVDE: 3585 return OPVCC(31, 425, 0, 0) 3586 3587 case ADIVDECC: 3588 return OPVCC(31, 425, 0, 1) 3589 3590 case ADIVDEU: 3591 return OPVCC(31, 393, 0, 0) 3592 3593 case ADIVDEUCC: 3594 return OPVCC(31, 393, 0, 1) 3595 3596 case AREMDV, ADIVDV: 3597 return OPVCC(31, 489, 1, 0) 3598 3599 case AREMDVCC, ADIVDVCC: 3600 return OPVCC(31, 489, 1, 1) 3601 3602 case AREMDU, ADIVDU: 3603 return OPVCC(31, 457, 0, 0) 3604 3605 case AREMDUCC, ADIVDUCC: 3606 return OPVCC(31, 457, 0, 1) 3607 3608 case AREMDUV, ADIVDUV: 3609 return OPVCC(31, 457, 1, 0) 3610 3611 case AREMDUVCC, ADIVDUVCC: 3612 return OPVCC(31, 457, 1, 1) 3613 3614 case AEIEIO: 3615 return OPVCC(31, 854, 0, 0) 3616 3617 case AEQV: 3618 return OPVCC(31, 284, 0, 0) 3619 case AEQVCC: 3620 return OPVCC(31, 284, 0, 1) 3621 3622 case AEXTSB: 3623 return OPVCC(31, 954, 0, 0) 3624 case AEXTSBCC: 3625 return OPVCC(31, 954, 0, 1) 3626 case AEXTSH: 3627 return OPVCC(31, 922, 0, 0) 3628 case AEXTSHCC: 3629 return OPVCC(31, 922, 0, 1) 3630 case AEXTSW: 3631 return OPVCC(31, 986, 0, 0) 3632 case AEXTSWCC: 3633 return OPVCC(31, 986, 0, 1) 3634 3635 case AFABS: 3636 return OPVCC(63, 264, 0, 0) 3637 case AFABSCC: 3638 return OPVCC(63, 264, 0, 1) 3639 case AFADD: 3640 return OPVCC(63, 21, 0, 0) 3641 case AFADDCC: 3642 return OPVCC(63, 21, 0, 1) 3643 case AFADDS: 3644 return OPVCC(59, 21, 0, 0) 3645 case AFADDSCC: 3646 return OPVCC(59, 21, 0, 1) 3647 case AFCMPO: 3648 return OPVCC(63, 32, 0, 0) 3649 case AFCMPU: 3650 return OPVCC(63, 0, 0, 0) 3651 case AFCFID: 3652 return OPVCC(63, 846, 0, 0) 3653 case AFCFIDCC: 3654 return OPVCC(63, 846, 0, 1) 3655 case AFCFIDU: 3656 return OPVCC(63, 974, 0, 0) 3657 case AFCFIDUCC: 3658 return OPVCC(63, 974, 0, 1) 3659 case AFCTIW: 3660 return OPVCC(63, 14, 0, 0) 3661 case AFCTIWCC: 3662 return OPVCC(63, 14, 0, 1) 3663 case AFCTIWZ: 3664 return OPVCC(63, 15, 0, 0) 3665 case AFCTIWZCC: 3666 return OPVCC(63, 15, 0, 1) 3667 case AFCTID: 3668 return OPVCC(63, 814, 0, 0) 3669 case AFCTIDCC: 3670 return OPVCC(63, 814, 0, 1) 3671 case AFCTIDZ: 3672 return OPVCC(63, 815, 0, 0) 3673 case AFCTIDZCC: 3674 return OPVCC(63, 815, 0, 1) 3675 case AFDIV: 3676 return OPVCC(63, 18, 0, 0) 3677 case AFDIVCC: 3678 return OPVCC(63, 18, 0, 1) 3679 case AFDIVS: 3680 return OPVCC(59, 18, 0, 0) 3681 case AFDIVSCC: 3682 return OPVCC(59, 18, 0, 1) 3683 case AFMADD: 3684 return OPVCC(63, 29, 0, 0) 3685 case AFMADDCC: 3686 return OPVCC(63, 29, 0, 1) 3687 case AFMADDS: 3688 return OPVCC(59, 29, 0, 0) 3689 case AFMADDSCC: 3690 return OPVCC(59, 29, 0, 1) 3691 3692 case AFMOVS, AFMOVD: 3693 return OPVCC(63, 72, 0, 0) /* load */ 3694 case AFMOVDCC: 3695 return OPVCC(63, 72, 0, 1) 3696 case AFMSUB: 3697 return OPVCC(63, 28, 0, 0) 3698 case AFMSUBCC: 3699 return OPVCC(63, 28, 0, 1) 3700 case AFMSUBS: 3701 return OPVCC(59, 28, 0, 0) 3702 case AFMSUBSCC: 3703 return OPVCC(59, 28, 0, 1) 3704 case AFMUL: 3705 return OPVCC(63, 25, 0, 0) 3706 case AFMULCC: 3707 return OPVCC(63, 25, 0, 1) 3708 case AFMULS: 3709 return OPVCC(59, 25, 0, 0) 3710 case AFMULSCC: 3711 return OPVCC(59, 25, 0, 1) 3712 case AFNABS: 3713 return OPVCC(63, 136, 0, 0) 3714 case AFNABSCC: 3715 return OPVCC(63, 136, 0, 1) 3716 case AFNEG: 3717 return OPVCC(63, 40, 0, 0) 3718 case AFNEGCC: 3719 return OPVCC(63, 40, 0, 1) 3720 case AFNMADD: 3721 return OPVCC(63, 31, 0, 0) 3722 case AFNMADDCC: 3723 return OPVCC(63, 31, 0, 1) 3724 case AFNMADDS: 3725 return OPVCC(59, 31, 0, 0) 3726 case AFNMADDSCC: 3727 return OPVCC(59, 31, 0, 1) 3728 case AFNMSUB: 3729 return OPVCC(63, 30, 0, 0) 3730 case AFNMSUBCC: 3731 return OPVCC(63, 30, 0, 1) 3732 case AFNMSUBS: 3733 return OPVCC(59, 30, 0, 0) 3734 case AFNMSUBSCC: 3735 return OPVCC(59, 30, 0, 1) 3736 case AFRES: 3737 return OPVCC(59, 24, 0, 0) 3738 case AFRESCC: 3739 return OPVCC(59, 24, 0, 1) 3740 case AFRIM: 3741 return OPVCC(63, 488, 0, 0) 3742 case AFRIMCC: 3743 return OPVCC(63, 488, 0, 1) 3744 case AFRIP: 3745 return OPVCC(63, 456, 0, 0) 3746 case AFRIPCC: 3747 return OPVCC(63, 456, 0, 1) 3748 case AFRIZ: 3749 return OPVCC(63, 424, 0, 0) 3750 case AFRIZCC: 3751 return OPVCC(63, 424, 0, 1) 3752 case AFRSP: 3753 return OPVCC(63, 12, 0, 0) 3754 case AFRSPCC: 3755 return OPVCC(63, 12, 0, 1) 3756 case AFRSQRTE: 3757 return OPVCC(63, 26, 0, 0) 3758 case AFRSQRTECC: 3759 return OPVCC(63, 26, 0, 1) 3760 case AFSEL: 3761 return OPVCC(63, 23, 0, 0) 3762 case AFSELCC: 3763 return OPVCC(63, 23, 0, 1) 3764 case AFSQRT: 3765 return OPVCC(63, 22, 0, 0) 3766 case AFSQRTCC: 3767 return OPVCC(63, 22, 0, 1) 3768 case AFSQRTS: 3769 return OPVCC(59, 22, 0, 0) 3770 case AFSQRTSCC: 3771 return OPVCC(59, 22, 0, 1) 3772 case AFSUB: 3773 return OPVCC(63, 20, 0, 0) 3774 case AFSUBCC: 3775 return OPVCC(63, 20, 0, 1) 3776 case AFSUBS: 3777 return OPVCC(59, 20, 0, 0) 3778 case AFSUBSCC: 3779 return OPVCC(59, 20, 0, 1) 3780 3781 case AICBI: 3782 return OPVCC(31, 982, 0, 0) 3783 case AISYNC: 3784 return OPVCC(19, 150, 0, 0) 3785 3786 case AMTFSB0: 3787 return OPVCC(63, 70, 0, 0) 3788 case AMTFSB0CC: 3789 return OPVCC(63, 70, 0, 1) 3790 case AMTFSB1: 3791 return OPVCC(63, 38, 0, 0) 3792 case AMTFSB1CC: 3793 return OPVCC(63, 38, 0, 1) 3794 3795 case AMULHW: 3796 return OPVCC(31, 75, 0, 0) 3797 case AMULHWCC: 3798 return OPVCC(31, 75, 0, 1) 3799 case AMULHWU: 3800 return OPVCC(31, 11, 0, 0) 3801 case AMULHWUCC: 3802 return OPVCC(31, 11, 0, 1) 3803 case AMULLW: 3804 return OPVCC(31, 235, 0, 0) 3805 case AMULLWCC: 3806 return OPVCC(31, 235, 0, 1) 3807 case AMULLWV: 3808 return OPVCC(31, 235, 1, 0) 3809 case AMULLWVCC: 3810 return OPVCC(31, 235, 1, 1) 3811 3812 case AMULHD: 3813 return OPVCC(31, 73, 0, 0) 3814 case AMULHDCC: 3815 return OPVCC(31, 73, 0, 1) 3816 case AMULHDU: 3817 return OPVCC(31, 9, 0, 0) 3818 case AMULHDUCC: 3819 return OPVCC(31, 9, 0, 1) 3820 case AMULLD: 3821 return OPVCC(31, 233, 0, 0) 3822 case AMULLDCC: 3823 return OPVCC(31, 233, 0, 1) 3824 case AMULLDV: 3825 return OPVCC(31, 233, 1, 0) 3826 case AMULLDVCC: 3827 return OPVCC(31, 233, 1, 1) 3828 3829 case ANAND: 3830 return OPVCC(31, 476, 0, 0) 3831 case ANANDCC: 3832 return OPVCC(31, 476, 0, 1) 3833 case ANEG: 3834 return OPVCC(31, 104, 0, 0) 3835 case ANEGCC: 3836 return OPVCC(31, 104, 0, 1) 3837 case ANEGV: 3838 return OPVCC(31, 104, 1, 0) 3839 case ANEGVCC: 3840 return OPVCC(31, 104, 1, 1) 3841 case ANOR: 3842 return OPVCC(31, 124, 0, 0) 3843 case ANORCC: 3844 return OPVCC(31, 124, 0, 1) 3845 case AOR: 3846 return OPVCC(31, 444, 0, 0) 3847 case AORCC: 3848 return OPVCC(31, 444, 0, 1) 3849 case AORN: 3850 return OPVCC(31, 412, 0, 0) 3851 case AORNCC: 3852 return OPVCC(31, 412, 0, 1) 3853 3854 case APOPCNTD: 3855 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3856 case APOPCNTW: 3857 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3858 case APOPCNTB: 3859 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3860 3861 case ARFI: 3862 return OPVCC(19, 50, 0, 0) 3863 case ARFCI: 3864 return OPVCC(19, 51, 0, 0) 3865 case ARFID: 3866 return OPVCC(19, 18, 0, 0) 3867 case AHRFID: 3868 return OPVCC(19, 274, 0, 0) 3869 3870 case ARLWMI: 3871 return OPVCC(20, 0, 0, 0) 3872 case ARLWMICC: 3873 return OPVCC(20, 0, 0, 1) 3874 case ARLWNM: 3875 return OPVCC(23, 0, 0, 0) 3876 case ARLWNMCC: 3877 return OPVCC(23, 0, 0, 1) 3878 3879 case ARLDCL: 3880 return OPVCC(30, 8, 0, 0) 3881 case ARLDCR: 3882 return OPVCC(30, 9, 0, 0) 3883 3884 case ARLDICL: 3885 return OPVCC(30, 0, 0, 0) 3886 case ARLDICLCC: 3887 return OPVCC(30, 0, 0, 1) 3888 case ARLDICR: 3889 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3890 case ARLDICRCC: 3891 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3892 3893 case ASYSCALL: 3894 return OPVCC(17, 1, 0, 0) 3895 3896 case ASLW: 3897 return OPVCC(31, 24, 0, 0) 3898 case ASLWCC: 3899 return OPVCC(31, 24, 0, 1) 3900 case ASLD: 3901 return OPVCC(31, 27, 0, 0) 3902 case ASLDCC: 3903 return OPVCC(31, 27, 0, 1) 3904 3905 case ASRAW: 3906 return OPVCC(31, 792, 0, 0) 3907 case ASRAWCC: 3908 return OPVCC(31, 792, 0, 1) 3909 case ASRAD: 3910 return OPVCC(31, 794, 0, 0) 3911 case ASRADCC: 3912 return OPVCC(31, 794, 0, 1) 3913 3914 case ASRW: 3915 return OPVCC(31, 536, 0, 0) 3916 case ASRWCC: 3917 return OPVCC(31, 536, 0, 1) 3918 case ASRD: 3919 return OPVCC(31, 539, 0, 0) 3920 case ASRDCC: 3921 return OPVCC(31, 539, 0, 1) 3922 3923 case ASUB: 3924 return OPVCC(31, 40, 0, 0) 3925 case ASUBCC: 3926 return OPVCC(31, 40, 0, 1) 3927 case ASUBV: 3928 return OPVCC(31, 40, 1, 0) 3929 case ASUBVCC: 3930 return OPVCC(31, 40, 1, 1) 3931 case ASUBC: 3932 return OPVCC(31, 8, 0, 0) 3933 case ASUBCCC: 3934 return OPVCC(31, 8, 0, 1) 3935 case ASUBCV: 3936 return OPVCC(31, 8, 1, 0) 3937 case ASUBCVCC: 3938 return OPVCC(31, 8, 1, 1) 3939 case ASUBE: 3940 return OPVCC(31, 136, 0, 0) 3941 case ASUBECC: 3942 return OPVCC(31, 136, 0, 1) 3943 case ASUBEV: 3944 return OPVCC(31, 136, 1, 0) 3945 case ASUBEVCC: 3946 return OPVCC(31, 136, 1, 1) 3947 case ASUBME: 3948 return OPVCC(31, 232, 0, 0) 3949 case ASUBMECC: 3950 return OPVCC(31, 232, 0, 1) 3951 case ASUBMEV: 3952 return OPVCC(31, 232, 1, 0) 3953 case ASUBMEVCC: 3954 return OPVCC(31, 232, 1, 1) 3955 case ASUBZE: 3956 return OPVCC(31, 200, 0, 0) 3957 case ASUBZECC: 3958 return OPVCC(31, 200, 0, 1) 3959 case ASUBZEV: 3960 return OPVCC(31, 200, 1, 0) 3961 case ASUBZEVCC: 3962 return OPVCC(31, 200, 1, 1) 3963 3964 case ASYNC: 3965 return OPVCC(31, 598, 0, 0) 3966 case ALWSYNC: 3967 return OPVCC(31, 598, 0, 0) | 1<<21 3968 3969 case APTESYNC: 3970 return OPVCC(31, 598, 0, 0) | 2<<21 3971 3972 case ATLBIE: 3973 return OPVCC(31, 306, 0, 0) 3974 case ATLBIEL: 3975 return OPVCC(31, 274, 0, 0) 3976 case ATLBSYNC: 3977 return OPVCC(31, 566, 0, 0) 3978 case ASLBIA: 3979 return OPVCC(31, 498, 0, 0) 3980 case ASLBIE: 3981 return OPVCC(31, 434, 0, 0) 3982 case ASLBMFEE: 3983 return OPVCC(31, 915, 0, 0) 3984 case ASLBMFEV: 3985 return OPVCC(31, 851, 0, 0) 3986 case ASLBMTE: 3987 return OPVCC(31, 402, 0, 0) 3988 3989 case ATW: 3990 return OPVCC(31, 4, 0, 0) 3991 case ATD: 3992 return OPVCC(31, 68, 0, 0) 3993 3994 /* Vector (VMX/Altivec) instructions */ 3995 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3996 /* are enabled starting at POWER6 (ISA 2.05). */ 3997 case AVAND: 3998 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3999 case AVANDC: 4000 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 4001 case AVNAND: 4002 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 4003 4004 case AVOR: 4005 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 4006 case AVORC: 4007 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 4008 case AVNOR: 4009 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 4010 case AVXOR: 4011 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 4012 case AVEQV: 4013 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 4014 4015 case AVADDUBM: 4016 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 4017 case AVADDUHM: 4018 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 4019 case AVADDUWM: 4020 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 4021 case AVADDUDM: 4022 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 4023 case AVADDUQM: 4024 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 4025 4026 case AVADDCUQ: 4027 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 4028 case AVADDCUW: 4029 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 4030 4031 case AVADDUBS: 4032 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 4033 case AVADDUHS: 4034 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 4035 case AVADDUWS: 4036 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 4037 4038 case AVADDSBS: 4039 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 4040 case AVADDSHS: 4041 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 4042 case AVADDSWS: 4043 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 4044 4045 case AVADDEUQM: 4046 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 4047 case AVADDECUQ: 4048 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4049 4050 case AVPMSUMB: 4051 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4052 case AVPMSUMH: 4053 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4054 case AVPMSUMW: 4055 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4056 case AVPMSUMD: 4057 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4058 4059 case AVMSUMUDM: 4060 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */ 4061 4062 case AVSUBUBM: 4063 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4064 case AVSUBUHM: 4065 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4066 case AVSUBUWM: 4067 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4068 case AVSUBUDM: 4069 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4070 case AVSUBUQM: 4071 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4072 4073 case AVSUBCUQ: 4074 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4075 case AVSUBCUW: 4076 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4077 4078 case AVSUBUBS: 4079 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4080 case AVSUBUHS: 4081 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4082 case AVSUBUWS: 4083 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4084 4085 case AVSUBSBS: 4086 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4087 case AVSUBSHS: 4088 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4089 case AVSUBSWS: 4090 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4091 4092 case AVSUBEUQM: 4093 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4094 case AVSUBECUQ: 4095 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4096 4097 case AVRLB: 4098 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4099 case AVRLH: 4100 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4101 case AVRLW: 4102 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4103 case AVRLD: 4104 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4105 4106 case AVSLB: 4107 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4108 case AVSLH: 4109 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4110 case AVSLW: 4111 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4112 case AVSL: 4113 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4114 case AVSLO: 4115 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4116 case AVSRB: 4117 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4118 case AVSRH: 4119 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4120 case AVSRW: 4121 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4122 case AVSR: 4123 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4124 case AVSRO: 4125 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4126 case AVSLD: 4127 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4128 case AVSRD: 4129 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4130 4131 case AVSRAB: 4132 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4133 case AVSRAH: 4134 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4135 case AVSRAW: 4136 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4137 case AVSRAD: 4138 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4139 4140 case AVCLZB: 4141 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4142 case AVCLZH: 4143 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4144 case AVCLZW: 4145 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4146 case AVCLZD: 4147 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4148 4149 case AVPOPCNTB: 4150 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4151 case AVPOPCNTH: 4152 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4153 case AVPOPCNTW: 4154 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4155 case AVPOPCNTD: 4156 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4157 4158 case AVCMPEQUB: 4159 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4160 case AVCMPEQUBCC: 4161 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4162 case AVCMPEQUH: 4163 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4164 case AVCMPEQUHCC: 4165 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4166 case AVCMPEQUW: 4167 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4168 case AVCMPEQUWCC: 4169 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4170 case AVCMPEQUD: 4171 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4172 case AVCMPEQUDCC: 4173 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4174 4175 case AVCMPGTUB: 4176 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4177 case AVCMPGTUBCC: 4178 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4179 case AVCMPGTUH: 4180 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4181 case AVCMPGTUHCC: 4182 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4183 case AVCMPGTUW: 4184 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4185 case AVCMPGTUWCC: 4186 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4187 case AVCMPGTUD: 4188 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4189 case AVCMPGTUDCC: 4190 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4191 case AVCMPGTSB: 4192 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4193 case AVCMPGTSBCC: 4194 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4195 case AVCMPGTSH: 4196 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4197 case AVCMPGTSHCC: 4198 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4199 case AVCMPGTSW: 4200 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4201 case AVCMPGTSWCC: 4202 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4203 case AVCMPGTSD: 4204 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4205 case AVCMPGTSDCC: 4206 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4207 4208 case AVCMPNEZB: 4209 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */ 4210 case AVCMPNEZBCC: 4211 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */ 4212 4213 case AVPERM: 4214 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4215 4216 case AVSEL: 4217 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4218 4219 case AVCIPHER: 4220 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4221 case AVCIPHERLAST: 4222 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4223 case AVNCIPHER: 4224 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4225 case AVNCIPHERLAST: 4226 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4227 case AVSBOX: 4228 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4229 /* End of vector instructions */ 4230 4231 /* Vector scalar (VSX) instructions */ 4232 /* ISA 2.06 enables these for POWER7. */ 4233 case AMFVSRD, AMFVRD, AMFFPRD: 4234 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4235 case AMFVSRWZ: 4236 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4237 case AMFVSRLD: 4238 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */ 4239 4240 case AMTVSRD, AMTFPRD, AMTVRD: 4241 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4242 case AMTVSRWA: 4243 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4244 case AMTVSRWZ: 4245 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4246 case AMTVSRDD: 4247 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */ 4248 case AMTVSRWS: 4249 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */ 4250 4251 case AXXLANDQ: 4252 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4253 case AXXLANDC: 4254 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4255 case AXXLEQV: 4256 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4257 case AXXLNAND: 4258 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4259 4260 case AXXLORC: 4261 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4262 case AXXLNOR: 4263 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4264 case AXXLORQ: 4265 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4266 case AXXLXOR: 4267 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4268 4269 case AXXSEL: 4270 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4271 4272 case AXXMRGHW: 4273 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4274 case AXXMRGLW: 4275 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4276 4277 case AXXSPLTW: 4278 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4279 4280 case AXXPERMDI: 4281 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4282 4283 case AXXSLDWI: 4284 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4285 4286 case AXSCVDPSP: 4287 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4288 case AXSCVSPDP: 4289 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4290 case AXSCVDPSPN: 4291 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4292 case AXSCVSPDPN: 4293 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4294 4295 case AXVCVDPSP: 4296 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4297 case AXVCVSPDP: 4298 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4299 4300 case AXSCVDPSXDS: 4301 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4302 case AXSCVDPSXWS: 4303 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4304 case AXSCVDPUXDS: 4305 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4306 case AXSCVDPUXWS: 4307 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4308 4309 case AXSCVSXDDP: 4310 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4311 case AXSCVUXDDP: 4312 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4313 case AXSCVSXDSP: 4314 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4315 case AXSCVUXDSP: 4316 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4317 4318 case AXVCVDPSXDS: 4319 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4320 case AXVCVDPSXWS: 4321 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4322 case AXVCVDPUXDS: 4323 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4324 case AXVCVDPUXWS: 4325 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4326 case AXVCVSPSXDS: 4327 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4328 case AXVCVSPSXWS: 4329 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4330 case AXVCVSPUXDS: 4331 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4332 case AXVCVSPUXWS: 4333 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4334 4335 case AXVCVSXDDP: 4336 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4337 case AXVCVSXWDP: 4338 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4339 case AXVCVUXDDP: 4340 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4341 case AXVCVUXWDP: 4342 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4343 case AXVCVSXDSP: 4344 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4345 case AXVCVSXWSP: 4346 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4347 case AXVCVUXDSP: 4348 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4349 case AXVCVUXWSP: 4350 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4351 /* End of VSX instructions */ 4352 4353 case AMADDHD: 4354 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */ 4355 case AMADDHDU: 4356 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */ 4357 case AMADDLD: 4358 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */ 4359 4360 case AXOR: 4361 return OPVCC(31, 316, 0, 0) 4362 case AXORCC: 4363 return OPVCC(31, 316, 0, 1) 4364 } 4365 4366 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4367 return 0 4368 } 4369 4370 func (c *ctxt9) opirrr(a obj.As) uint32 { 4371 switch a { 4372 /* Vector (VMX/Altivec) instructions */ 4373 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4374 /* are enabled starting at POWER6 (ISA 2.05). */ 4375 case AVSLDOI: 4376 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4377 } 4378 4379 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4380 return 0 4381 } 4382 4383 func (c *ctxt9) opiirr(a obj.As) uint32 { 4384 switch a { 4385 /* Vector (VMX/Altivec) instructions */ 4386 /* ISA 2.07 enables these for POWER8 and beyond. */ 4387 case AVSHASIGMAW: 4388 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4389 case AVSHASIGMAD: 4390 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4391 } 4392 4393 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4394 return 0 4395 } 4396 4397 func (c *ctxt9) opirr(a obj.As) uint32 { 4398 switch a { 4399 case AADD: 4400 return OPVCC(14, 0, 0, 0) 4401 case AADDC: 4402 return OPVCC(12, 0, 0, 0) 4403 case AADDCCC: 4404 return OPVCC(13, 0, 0, 0) 4405 case -AADD: 4406 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4407 4408 case AANDCC: 4409 return OPVCC(28, 0, 0, 0) 4410 case -AANDCC: 4411 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4412 4413 case ABR: 4414 return OPVCC(18, 0, 0, 0) 4415 case ABL: 4416 return OPVCC(18, 0, 0, 0) | 1 4417 case obj.ADUFFZERO: 4418 return OPVCC(18, 0, 0, 0) | 1 4419 case obj.ADUFFCOPY: 4420 return OPVCC(18, 0, 0, 0) | 1 4421 case ABC: 4422 return OPVCC(16, 0, 0, 0) 4423 case ABCL: 4424 return OPVCC(16, 0, 0, 0) | 1 4425 4426 case ABEQ: 4427 return AOP_RRR(16<<26, 12, 2, 0) 4428 case ABGE: 4429 return AOP_RRR(16<<26, 4, 0, 0) 4430 case ABGT: 4431 return AOP_RRR(16<<26, 12, 1, 0) 4432 case ABLE: 4433 return AOP_RRR(16<<26, 4, 1, 0) 4434 case ABLT: 4435 return AOP_RRR(16<<26, 12, 0, 0) 4436 case ABNE: 4437 return AOP_RRR(16<<26, 4, 2, 0) 4438 case ABVC: 4439 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4440 case ABVS: 4441 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4442 4443 case ACMP: 4444 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4445 case ACMPU: 4446 return OPVCC(10, 0, 0, 0) | 1<<21 4447 case ACMPW: 4448 return OPVCC(11, 0, 0, 0) /* L=0 */ 4449 case ACMPWU: 4450 return OPVCC(10, 0, 0, 0) 4451 case ACMPEQB: 4452 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 4453 4454 case ALSW: 4455 return OPVCC(31, 597, 0, 0) 4456 4457 case ACOPY: 4458 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */ 4459 case APASTECC: 4460 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */ 4461 case ADARN: 4462 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */ 4463 4464 case AMULLW: 4465 return OPVCC(7, 0, 0, 0) 4466 4467 case AOR: 4468 return OPVCC(24, 0, 0, 0) 4469 case -AOR: 4470 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4471 4472 case ARLWMI: 4473 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4474 case ARLWMICC: 4475 return OPVCC(20, 0, 0, 1) 4476 case ARLDMI: 4477 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4478 case ARLDMICC: 4479 return OPVCC(30, 0, 0, 1) | 3<<2 4480 case ARLDIMI: 4481 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4482 case ARLDIMICC: 4483 return OPVCC(30, 0, 0, 1) | 3<<2 4484 case ARLWNM: 4485 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4486 case ARLWNMCC: 4487 return OPVCC(21, 0, 0, 1) 4488 4489 case ARLDCL: 4490 return OPVCC(30, 0, 0, 0) /* rldicl */ 4491 case ARLDCLCC: 4492 return OPVCC(30, 0, 0, 1) 4493 case ARLDCR: 4494 return OPVCC(30, 1, 0, 0) /* rldicr */ 4495 case ARLDCRCC: 4496 return OPVCC(30, 1, 0, 1) 4497 case ARLDC: 4498 return OPVCC(30, 0, 0, 0) | 2<<2 4499 case ARLDCCC: 4500 return OPVCC(30, 0, 0, 1) | 2<<2 4501 4502 case ASRAW: 4503 return OPVCC(31, 824, 0, 0) 4504 case ASRAWCC: 4505 return OPVCC(31, 824, 0, 1) 4506 case ASRAD: 4507 return OPVCC(31, (413 << 1), 0, 0) 4508 case ASRADCC: 4509 return OPVCC(31, (413 << 1), 0, 1) 4510 4511 case ASTSW: 4512 return OPVCC(31, 725, 0, 0) 4513 4514 case ASUBC: 4515 return OPVCC(8, 0, 0, 0) 4516 4517 case ATW: 4518 return OPVCC(3, 0, 0, 0) 4519 case ATD: 4520 return OPVCC(2, 0, 0, 0) 4521 4522 /* Vector (VMX/Altivec) instructions */ 4523 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4524 /* are enabled starting at POWER6 (ISA 2.05). */ 4525 case AVSPLTB: 4526 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4527 case AVSPLTH: 4528 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4529 case AVSPLTW: 4530 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4531 4532 case AVSPLTISB: 4533 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4534 case AVSPLTISH: 4535 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4536 case AVSPLTISW: 4537 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4538 /* End of vector instructions */ 4539 4540 case AFTDIV: 4541 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4542 case AFTSQRT: 4543 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4544 4545 case AXOR: 4546 return OPVCC(26, 0, 0, 0) /* XORIL */ 4547 case -AXOR: 4548 return OPVCC(27, 0, 0, 0) /* XORIU */ 4549 } 4550 4551 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4552 return 0 4553 } 4554 4555 /* 4556 * load o(a),d 4557 */ 4558 func (c *ctxt9) opload(a obj.As) uint32 { 4559 switch a { 4560 case AMOVD: 4561 return OPVCC(58, 0, 0, 0) /* ld */ 4562 case AMOVDU: 4563 return OPVCC(58, 0, 0, 1) /* ldu */ 4564 case AMOVWZ: 4565 return OPVCC(32, 0, 0, 0) /* lwz */ 4566 case AMOVWZU: 4567 return OPVCC(33, 0, 0, 0) /* lwzu */ 4568 case AMOVW: 4569 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4570 4571 /* no AMOVWU */ 4572 case AMOVB, AMOVBZ: 4573 return OPVCC(34, 0, 0, 0) 4574 /* load */ 4575 4576 case AMOVBU, AMOVBZU: 4577 return OPVCC(35, 0, 0, 0) 4578 case AFMOVD: 4579 return OPVCC(50, 0, 0, 0) 4580 case AFMOVDU: 4581 return OPVCC(51, 0, 0, 0) 4582 case AFMOVS: 4583 return OPVCC(48, 0, 0, 0) 4584 case AFMOVSU: 4585 return OPVCC(49, 0, 0, 0) 4586 case AMOVH: 4587 return OPVCC(42, 0, 0, 0) 4588 case AMOVHU: 4589 return OPVCC(43, 0, 0, 0) 4590 case AMOVHZ: 4591 return OPVCC(40, 0, 0, 0) 4592 case AMOVHZU: 4593 return OPVCC(41, 0, 0, 0) 4594 case AMOVMW: 4595 return OPVCC(46, 0, 0, 0) /* lmw */ 4596 } 4597 4598 c.ctxt.Diag("bad load opcode %v", a) 4599 return 0 4600 } 4601 4602 /* 4603 * indexed load a(b),d 4604 */ 4605 func (c *ctxt9) oploadx(a obj.As) uint32 { 4606 switch a { 4607 case AMOVWZ: 4608 return OPVCC(31, 23, 0, 0) /* lwzx */ 4609 case AMOVWZU: 4610 return OPVCC(31, 55, 0, 0) /* lwzux */ 4611 case AMOVW: 4612 return OPVCC(31, 341, 0, 0) /* lwax */ 4613 case AMOVWU: 4614 return OPVCC(31, 373, 0, 0) /* lwaux */ 4615 4616 case AMOVB, AMOVBZ: 4617 return OPVCC(31, 87, 0, 0) /* lbzx */ 4618 4619 case AMOVBU, AMOVBZU: 4620 return OPVCC(31, 119, 0, 0) /* lbzux */ 4621 case AFMOVD: 4622 return OPVCC(31, 599, 0, 0) /* lfdx */ 4623 case AFMOVDU: 4624 return OPVCC(31, 631, 0, 0) /* lfdux */ 4625 case AFMOVS: 4626 return OPVCC(31, 535, 0, 0) /* lfsx */ 4627 case AFMOVSU: 4628 return OPVCC(31, 567, 0, 0) /* lfsux */ 4629 case AFMOVSX: 4630 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4631 case AFMOVSZ: 4632 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4633 case AMOVH: 4634 return OPVCC(31, 343, 0, 0) /* lhax */ 4635 case AMOVHU: 4636 return OPVCC(31, 375, 0, 0) /* lhaux */ 4637 case AMOVHBR: 4638 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4639 case AMOVWBR: 4640 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4641 case AMOVDBR: 4642 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4643 case AMOVHZ: 4644 return OPVCC(31, 279, 0, 0) /* lhzx */ 4645 case AMOVHZU: 4646 return OPVCC(31, 311, 0, 0) /* lhzux */ 4647 case AECIWX: 4648 return OPVCC(31, 310, 0, 0) /* eciwx */ 4649 case ALBAR: 4650 return OPVCC(31, 52, 0, 0) /* lbarx */ 4651 case ALWAR: 4652 return OPVCC(31, 20, 0, 0) /* lwarx */ 4653 case ALDAR: 4654 return OPVCC(31, 84, 0, 0) 4655 case ALSW: 4656 return OPVCC(31, 533, 0, 0) /* lswx */ 4657 case AMOVD: 4658 return OPVCC(31, 21, 0, 0) /* ldx */ 4659 case AMOVDU: 4660 return OPVCC(31, 53, 0, 0) /* ldux */ 4661 case ALDMX: 4662 return OPVCC(31, 309, 0, 0) /* ldmx */ 4663 4664 /* Vector (VMX/Altivec) instructions */ 4665 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4666 /* are enabled starting at POWER6 (ISA 2.05). */ 4667 case ALVEBX: 4668 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4669 case ALVEHX: 4670 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4671 case ALVEWX: 4672 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4673 case ALVX: 4674 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4675 case ALVXL: 4676 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4677 case ALVSL: 4678 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4679 case ALVSR: 4680 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4681 /* End of vector instructions */ 4682 4683 /* Vector scalar (VSX) instructions */ 4684 /* ISA 2.06 enables these for POWER7. */ 4685 case ALXVD2X: 4686 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4687 case ALXVDSX: 4688 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4689 case ALXVW4X: 4690 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4691 4692 case ALXSDX: 4693 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4694 4695 case ALXSIWAX: 4696 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4697 case ALXSIWZX: 4698 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4699 /* End of vector scalar instructions */ 4700 4701 } 4702 4703 c.ctxt.Diag("bad loadx opcode %v", a) 4704 return 0 4705 } 4706 4707 /* 4708 * store s,o(d) 4709 */ 4710 func (c *ctxt9) opstore(a obj.As) uint32 { 4711 switch a { 4712 case AMOVB, AMOVBZ: 4713 return OPVCC(38, 0, 0, 0) /* stb */ 4714 4715 case AMOVBU, AMOVBZU: 4716 return OPVCC(39, 0, 0, 0) /* stbu */ 4717 case AFMOVD: 4718 return OPVCC(54, 0, 0, 0) /* stfd */ 4719 case AFMOVDU: 4720 return OPVCC(55, 0, 0, 0) /* stfdu */ 4721 case AFMOVS: 4722 return OPVCC(52, 0, 0, 0) /* stfs */ 4723 case AFMOVSU: 4724 return OPVCC(53, 0, 0, 0) /* stfsu */ 4725 4726 case AMOVHZ, AMOVH: 4727 return OPVCC(44, 0, 0, 0) /* sth */ 4728 4729 case AMOVHZU, AMOVHU: 4730 return OPVCC(45, 0, 0, 0) /* sthu */ 4731 case AMOVMW: 4732 return OPVCC(47, 0, 0, 0) /* stmw */ 4733 case ASTSW: 4734 return OPVCC(31, 725, 0, 0) /* stswi */ 4735 4736 case AMOVWZ, AMOVW: 4737 return OPVCC(36, 0, 0, 0) /* stw */ 4738 4739 case AMOVWZU, AMOVWU: 4740 return OPVCC(37, 0, 0, 0) /* stwu */ 4741 case AMOVD: 4742 return OPVCC(62, 0, 0, 0) /* std */ 4743 case AMOVDU: 4744 return OPVCC(62, 0, 0, 1) /* stdu */ 4745 } 4746 4747 c.ctxt.Diag("unknown store opcode %v", a) 4748 return 0 4749 } 4750 4751 /* 4752 * indexed store s,a(b) 4753 */ 4754 func (c *ctxt9) opstorex(a obj.As) uint32 { 4755 switch a { 4756 case AMOVB, AMOVBZ: 4757 return OPVCC(31, 215, 0, 0) /* stbx */ 4758 4759 case AMOVBU, AMOVBZU: 4760 return OPVCC(31, 247, 0, 0) /* stbux */ 4761 case AFMOVD: 4762 return OPVCC(31, 727, 0, 0) /* stfdx */ 4763 case AFMOVDU: 4764 return OPVCC(31, 759, 0, 0) /* stfdux */ 4765 case AFMOVS: 4766 return OPVCC(31, 663, 0, 0) /* stfsx */ 4767 case AFMOVSU: 4768 return OPVCC(31, 695, 0, 0) /* stfsux */ 4769 case AFMOVSX: 4770 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4771 4772 case AMOVHZ, AMOVH: 4773 return OPVCC(31, 407, 0, 0) /* sthx */ 4774 case AMOVHBR: 4775 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4776 4777 case AMOVHZU, AMOVHU: 4778 return OPVCC(31, 439, 0, 0) /* sthux */ 4779 4780 case AMOVWZ, AMOVW: 4781 return OPVCC(31, 151, 0, 0) /* stwx */ 4782 4783 case AMOVWZU, AMOVWU: 4784 return OPVCC(31, 183, 0, 0) /* stwux */ 4785 case ASTSW: 4786 return OPVCC(31, 661, 0, 0) /* stswx */ 4787 case AMOVWBR: 4788 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4789 case ASTBCCC: 4790 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4791 case ASTWCCC: 4792 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4793 case ASTDCCC: 4794 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4795 case AECOWX: 4796 return OPVCC(31, 438, 0, 0) /* ecowx */ 4797 case AMOVD: 4798 return OPVCC(31, 149, 0, 0) /* stdx */ 4799 case AMOVDU: 4800 return OPVCC(31, 181, 0, 0) /* stdux */ 4801 4802 /* Vector (VMX/Altivec) instructions */ 4803 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4804 /* are enabled starting at POWER6 (ISA 2.05). */ 4805 case ASTVEBX: 4806 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4807 case ASTVEHX: 4808 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4809 case ASTVEWX: 4810 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4811 case ASTVX: 4812 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4813 case ASTVXL: 4814 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4815 /* End of vector instructions */ 4816 4817 /* Vector scalar (VSX) instructions */ 4818 /* ISA 2.06 enables these for POWER7. */ 4819 case ASTXVD2X: 4820 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4821 case ASTXVW4X: 4822 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4823 4824 case ASTXSDX: 4825 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4826 4827 case ASTXSIWX: 4828 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4829 /* End of vector scalar instructions */ 4830 4831 } 4832 4833 c.ctxt.Diag("unknown storex opcode %v", a) 4834 return 0 4835 }